1 /* 2 * Copyright 2020, NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_RESET_H_ 9 #define _FSL_RESET_H_ 10 11 #include <assert.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <string.h> 15 #include "fsl_device_registers.h" 16 17 /*! 18 * @addtogroup reset 19 * @{ 20 */ 21 22 /******************************************************************************* 23 * Definitions 24 ******************************************************************************/ 25 26 /*! @name Driver version */ 27 /*@{*/ 28 /*! @brief reset driver version 2.0.0. */ 29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 30 /*@}*/ 31 32 /*! 33 * @brief Enumeration for peripheral reset control bits 34 * 35 * Defines the enumeration for peripheral reset control in PCC registers 36 */ 37 typedef enum _pcc_reset 38 { 39 kRESET_IpInvalid = 0U, 40 41 /* PCC 0 for CM33 */ 42 kRESET_Wdog0 = (uint32_t)(PCC0_BASE + 0xB0), 43 kRESET_Wdog1 = (uint32_t)(PCC0_BASE + 0xB4), 44 kRESET_Flexspi0 = (uint32_t)(PCC0_BASE + 0xE4), 45 kRESET_Lpit0 = (uint32_t)(PCC0_BASE + 0xEC), 46 kRESET_Flexio0 = (uint32_t)(PCC0_BASE + 0xF0), 47 kRESET_I3c0 = (uint32_t)(PCC0_BASE + 0xF4), 48 kRESET_Lpspi0 = (uint32_t)(PCC0_BASE + 0xF8), 49 kRESET_Lpspi1 = (uint32_t)(PCC0_BASE + 0xFC), 50 kRESET_Adc0 = (uint32_t)(PCC0_BASE + 0x100), 51 kRESET_Dac0 = (uint32_t)(PCC0_BASE + 0x10C), 52 kRESET_Dac1 = (uint32_t)(PCC0_BASE + 0x110), 53 54 /* PCC 1 for CM33 */ 55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48), 56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54), 57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58), 58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60), 59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64), 60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68), 61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C), 62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70), 63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74), 64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88), 65 kRESET_Flexcan = (uint32_t)(PCC1_BASE + 0xA0), 66 67 /* PCC 2 for FusionF1 */ 68 kRESET_Wdog2 = (uint32_t)(PCC2_BASE + 0x4), 69 kRESET_Tpm2 = (uint32_t)(PCC2_BASE + 0x14), 70 kRESET_Tpm3 = (uint32_t)(PCC2_BASE + 0x18), 71 kRESET_Mrt = (uint32_t)(PCC2_BASE + 0x1C), 72 kRESET_Lpi2c2 = (uint32_t)(PCC2_BASE + 0x20), 73 kRESET_Lpi2c3 = (uint32_t)(PCC2_BASE + 0x24), 74 kRESET_I3c1 = (uint32_t)(PCC2_BASE + 0x28), 75 kRESET_Lpuart2 = (uint32_t)(PCC2_BASE + 0x2C), 76 kRESET_Lpuart3 = (uint32_t)(PCC2_BASE + 0x30), 77 kRESET_Lpspi2 = (uint32_t)(PCC2_BASE + 0x34), 78 kRESET_Lpspi3 = (uint32_t)(PCC2_BASE + 0x38), 79 kRESET_Sai2 = (uint32_t)(PCC2_BASE + 0x3C), 80 kRESET_Sai3 = (uint32_t)(PCC2_BASE + 0x40), 81 kRESET_Micfil = (uint32_t)(PCC2_BASE + 0x44), 82 83 /* PCC 3 for CA35 */ 84 kRESET_Wdog3 = (uint32_t)(PCC3_BASE + 0xA8), 85 kRESET_Wdog4 = (uint32_t)(PCC3_BASE + 0xAC), 86 kRESET_Lpit1 = (uint32_t)(PCC3_BASE + 0xC8), 87 kRESET_Tpm4 = (uint32_t)(PCC3_BASE + 0xCC), 88 kRESET_Tpm5 = (uint32_t)(PCC3_BASE + 0xD0), 89 kRESET_Flexio1 = (uint32_t)(PCC3_BASE + 0xD4), 90 kRESET_I3c2 = (uint32_t)(PCC3_BASE + 0xD8), 91 kRESET_Lpi2c4 = (uint32_t)(PCC3_BASE + 0xDC), 92 kRESET_Lpi2c5 = (uint32_t)(PCC3_BASE + 0xE0), 93 kRESET_Lpuart4 = (uint32_t)(PCC3_BASE + 0xE4), 94 kRESET_Lpuart5 = (uint32_t)(PCC3_BASE + 0xE8), 95 kRESET_Lpspi4 = (uint32_t)(PCC3_BASE + 0xEC), 96 kRESET_Lpspi5 = (uint32_t)(PCC3_BASE + 0xF0), 97 98 /* PCC 4 for CA35 */ 99 kRESET_Flexspi2 = (uint32_t)(PCC4_BASE + 0x4), 100 kRESET_Tpm6 = (uint32_t)(PCC4_BASE + 0x8), 101 kRESET_Tpm7 = (uint32_t)(PCC4_BASE + 0xC), 102 kRESET_Lpi2c6 = (uint32_t)(PCC4_BASE + 0x10), 103 kRESET_Lpi2c7 = (uint32_t)(PCC4_BASE + 0x14), 104 kRESET_Lpuart6 = (uint32_t)(PCC4_BASE + 0x18), 105 kRESET_Lpuart7 = (uint32_t)(PCC4_BASE + 0x1C), 106 kRESET_Sai4 = (uint32_t)(PCC4_BASE + 0x20), 107 kRESET_Sai5 = (uint32_t)(PCC4_BASE + 0x24), 108 kRESET_Usdhc0 = (uint32_t)(PCC4_BASE + 0x34), 109 kRESET_Usdhc1 = (uint32_t)(PCC4_BASE + 0x38), 110 kRESET_Usdhc2 = (uint32_t)(PCC4_BASE + 0x3C), 111 kRESET_Usb0 = (uint32_t)(PCC4_BASE + 0x40), 112 kRESET_Usb0Phy = (uint32_t)(PCC4_BASE + 0x44), 113 kRESET_Usb1 = (uint32_t)(PCC4_BASE + 0x48), 114 kRESET_Usb1Phy = (uint32_t)(PCC4_BASE + 0x4C), 115 kRESET_Enet = (uint32_t)(PCC4_BASE + 0x54), 116 117 /* PCC 5 for HiFi4 */ 118 kRESET_Tpm8 = (uint32_t)(PCC5_BASE + 0xA0), 119 kRESET_Sai6 = (uint32_t)(PCC5_BASE + 0xA4), 120 kRESET_Sai7 = (uint32_t)(PCC5_BASE + 0xA8), 121 kRESET_Spdif = (uint32_t)(PCC5_BASE + 0xAC), 122 kRESET_Isi = (uint32_t)(PCC5_BASE + 0xB0), 123 kRESET_Csi = (uint32_t)(PCC5_BASE + 0xBC), 124 kRESET_Dsi = (uint32_t)(PCC5_BASE + 0xC0), 125 kRESET_Wdog5 = (uint32_t)(PCC5_BASE + 0xC8), 126 kRESET_Epdc = (uint32_t)(PCC5_BASE + 0xCC), 127 kRESET_Pxp = (uint32_t)(PCC5_BASE + 0xD0), 128 kRESET_Gpu2d = (uint32_t)(PCC5_BASE + 0xF0), 129 kRESET_Gpu3d = (uint32_t)(PCC5_BASE + 0xF4), 130 kRESET_Dcnano = (uint32_t)(PCC5_BASE + 0xF8), 131 kRESET_Lpddr4 = (uint32_t)(PCC5_BASE + 0x108), 132 kRESET_CsiClkUi = (uint32_t)(PCC5_BASE + 0x10C), 133 } pcc_reset_t; 134 135 /** Array initializers with peripheral reset bits **/ 136 #define DAC_RSTS \ 137 { \ 138 kRESET_Dac0, kRESET_Dac1 \ 139 } /* Reset bits for DAC peripheral */ 140 #define ENET_RSTS \ 141 { \ 142 kRESET_Enet \ 143 } /* Reset bits for ENET peripheral */ 144 #define EPDC_RSTS \ 145 { \ 146 kRESET_Epdc \ 147 } /* Reset bits for EPDC peripheral */ 148 #define FLEXCAN_RSTS \ 149 { \ 150 kRESET_Flexcan \ 151 } /* Resets bits for FLEXCAN peripheral */ 152 #define FLEXIO_RSTS \ 153 { \ 154 kRESET_Flexio0, kRESET_Flexio1 \ 155 } /* Resets bits for FLEXIO peripheral */ 156 #define FLEXSPI_RSTS \ 157 { \ 158 kRESET_Flexspi0, kRESET_Flexspi1, kRESET_Flexspi2 \ 159 } /* Resets bits for FLEXSPI peripheral */ 160 #define I3C_RSTS \ 161 { \ 162 kRESET_I3c0, kRESET_I3c1, kRESET_I3c2 \ 163 } /* Reset bits for I3C peripheral */ 164 #define ISI_RSTS \ 165 { \ 166 kRESET_Isi \ 167 } /* Reset bits for ISI peripheral */ 168 #define LCDIF_RSTS \ 169 { \ 170 kRESET_Dcnano \ 171 } /* Reset bits for LCDIF peripheral */ 172 #define LPADC_RSTS \ 173 { \ 174 kRESET_Adc0, kRESET_Adc1 \ 175 } /* Reset bits for ADC peripheral */ 176 #define LPI2C_RSTS \ 177 { \ 178 kRESET_Lpi2c0, kRESET_Lpi2c1, kRESET_Lpi2c2, kRESET_Lpi2c3, kRESET_Lpi2c4, kRESET_Lpi2c5, kRESET_Lpi2c6, \ 179 kRESET_Lpi2c7 \ 180 } /* Reset bits for LPI2C peripheral */ 181 #define LPIT_RSTS \ 182 { \ 183 kRESET_Lpit0, kRESET_Lpit1 \ 184 } /* Reset bits for LPIT peripheral */ 185 #define LPSPI_RSTS \ 186 { \ 187 kRESET_Lpspi0, kRESET_Lpspi1, kRESET_Lpspi2, kRESET_Lpspi3, kRESET_Lpspi4, kRESET_Lpspi5 \ 188 } /* Reset bits for LPSPI peripheral */ 189 #define LPUART_RSTS \ 190 { \ 191 kRESET_Lpuart0, kRESET_Lpuart1, kRESET_Lpuart2, kRESET_Lpuart3, kRESET_Lpuart4, kRESET_Lpuart5, \ 192 kRESET_Lpuart6, kRESET_Lpuart7 \ 193 } /* Reset bits for LPUART peripheral */ 194 #define MIPI_DSI_RSTS \ 195 { \ 196 kRESET_Dsi \ 197 } /* Reset bits for DSI peripheral */ 198 #define MRT_RSTS \ 199 { \ 200 kRESET_Mrt \ 201 } /* Reset bits for MRT peripheral */ 202 #define PXP_RSTS \ 203 { \ 204 kRESET_Pxp \ 205 } /* Reset bits for PXP peripheral */ 206 #define SAI_RSTS \ 207 { \ 208 kRESET_Sai0, kRESET_Sai1, kRESET_Sai2, kRESET_Sai3, kRESET_Sai4, kRESET_Sai5, kRESET_Sai6, kRESET_Sai7 \ 209 } /* Reset bits for SAI peripheral */ 210 #define SPDIF_RSTS \ 211 { \ 212 kRESET_Spdif \ 213 } /* Reset bits for SPDIF peripheral */ 214 #define TPM_RSTS \ 215 { \ 216 kRESET_Tpm0, kRESET_Tpm1, kRESET_Tpm2, kRESET_Tpm3, kRESET_Tpm4, kRESET_Tpm5, kRESET_Tpm6, kRESET_Tpm7, \ 217 kRESET_Tpm8 \ 218 } /* Reset bits for TPM peripheral */ 219 #define USDHC_RSTS \ 220 { \ 221 kRESET_Usdhc0, kRESET_Usdhc1, kRESET_Usdhc2 \ 222 } /* Reset bits for USDHC peripheral */ 223 #define WDOG_RSTS \ 224 { \ 225 kRESET_Wdog0, kRESET_Wdog1, kRESET_Wdog2, kRESET_Wdog3, kRESET_Wdog4, kRESET_Wdog5, kRESET_Invalid \ 226 } /* Reset bits for WDOG peripheral */ 227 228 /*! 229 * @brief IP reset handle 230 */ 231 typedef pcc_reset_t reset_ip_name_t; 232 233 /******************************************************************************* 234 * API 235 ******************************************************************************/ 236 #if defined(__cplusplus) 237 extern "C" { 238 #endif 239 240 /*! 241 * @brief Assert reset to peripheral. 242 * 243 * Asserts reset signal to specified peripheral module. 244 * 245 * @param peripheral Assert reset to this peripheral. 246 */ 247 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 248 249 /*! 250 * @brief Clear reset to peripheral. 251 * 252 * Clears reset signal to specified peripheral module, allows it to operate. 253 * 254 * @param peripheral Clear reset to this peripheral. 255 */ 256 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 257 258 /*! 259 * @brief Reset peripheral module. 260 * 261 * Reset peripheral module. 262 * 263 * @param peripheral Peripheral to reset. 264 */ 265 void RESET_PeripheralReset(reset_ip_name_t peripheral); 266 267 #if defined(__cplusplus) 268 } 269 #endif 270 271 /*! @} */ 272 273 #endif /* _FSL_RESET_H_ */ 274
