1 /*
2 ** ###################################################################
3 ** Processors: MCXW716CMFPA
4 ** MCXW716CMFTA
5 **
6 ** Compilers: GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 ** Keil ARM C/C++ Compiler
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: Rev. 1, April 2024
12 ** Version: rev. 1.0, 2024-03-21
13 ** Build: b240524
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2024 NXP
22 ** SPDX-License-Identifier: BSD-3-Clause
23 **
24 ** http: www.nxp.com
25 ** mail: support@nxp.com
26 **
27 ** Revisions:
28 ** - rev. 1.0 (2024-03-21)
29 ** Initial version.
30 **
31 ** ###################################################################
32 */
33
34 /*!
35 * @file MCXW716C
36 * @version 1.0
37 * @date 2024-03-21
38 * @brief Device specific configuration file for MCXW716C (implementation file)
39 *
40 * Provides a system configuration function and a global variable that contains
41 * the system frequency. It configures the device and initializes the oscillator
42 * (PLL) that is part of the microcontroller device.
43 */
44
45 #include <stdint.h>
46 #include "fsl_device_registers.h"
47
48 #if defined(USE_SMU2_AS_SYSTEM_MEMORY)
49 #define SMU2_CM33_BASE_ADDR 0x489C0000ULL
50 #define SMU2_CM33_END_ADDR 0x489CA000ULL
51 #define SMU2_MAIR_IDX 1
52 #endif
53
54 #if defined(USE_PB_RAM_AS_SYSTEM_MEMORY)
55 #define PB_RAM_CM33_BASE_ADDR 0x48A08000ULL
56 #define PB_RAM_CM33_END_ADDR 0x48A0A000ULL
57 #define PB_RAM_MAIR_IDX 2
58 #endif
59
60 /* ----------------------------------------------------------------------------
61 -- Core clock
62 ---------------------------------------------------------------------------- */
63
64 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
65
66 /* ----------------------------------------------------------------------------
67 -- SystemInit()
68 ---------------------------------------------------------------------------- */
69
SystemInit(void)70 __attribute__ ((weak)) void SystemInit (void) {
71 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
72 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */
73 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
74 SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */
75 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
76 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
77
78 #if (DISABLE_WDOG)
79 while ((WDOG0->CS & WDOG_CS_RCS_MASK) != WDOG_CS_RCS_MASK)
80 {
81 }
82
83 if ((WDOG0->CS & WDOG_CS_CMD32EN_MASK) != 0U)
84 {
85 WDOG0->CNT = 0xD928C520U;
86 }
87 else
88 {
89 WDOG0->CNT = 0xC520U;
90 WDOG0->CNT = 0xD928U;
91 }
92
93 while ((WDOG0->CS & WDOG_CS_ULK_MASK) != WDOG_CS_ULK_MASK)
94 {
95 }
96
97 WDOG0->TOVAL = 0xFFFF;
98 WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
99
100 while ((WDOG0->CS & WDOG_CS_RCS_MASK) != WDOG_CS_RCS_MASK)
101 {
102 }
103 #endif /* (DISABLE_WDOG) */
104
105 #if defined(__MCUXPRESSO)
106 extern void(*const g_pfnVectors[]) (void);
107 SCB->VTOR = (uint32_t) &g_pfnVectors;
108 #endif
109
110 #if defined(USE_SMU2_AS_SYSTEM_MEMORY)
111 /* The SMU2 memory area in the default system memory map is configured as
112 * "device memory". This means that any unaligned access will fault, when
113 * driven from the CM33 core. Since we want to be able to use this as an
114 * extension to the system SRAM, remap it here as "memory"
115 * This is done by adding an entry to the MPU. This is done in 2 steps, as
116 * seen below. The 3rd step is to actually enable the MPU.
117 *
118 * Step 1: Add an entry in the MPU by setting the MPU_RNR register to select
119 * the position in the table, then by writing the MPU_RLAR &
120 * MPU_RBAR registers. For the RLAR, also set the Enable bit and the
121 * corresponding index in the MPU_MAIR0/1 registers.
122 */
123 ARM_MPU_SetRegionEx(MPU, SMU2_MAIR_IDX,
124 SMU2_CM33_BASE_ADDR,
125 SMU2_CM33_END_ADDR |
126 (MPU_RLAR_EN_Msk << MPU_RLAR_EN_Pos) |
127 (SMU2_MAIR_IDX << MPU_RLAR_AttrIndx_Pos));
128 /*
129 * Step 2: Set the attributes in the corresponding index in the MPU_MAIR
130 * registers (the index is the same index used when adding the entry in the
131 * MPU via the MPU_RNR register.
132 */
133 ARM_MPU_SetMemAttrEx(MPU,
134 SMU2_MAIR_IDX,
135 ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE,
136 ARM_MPU_ATTR_NON_CACHEABLE));
137 #endif
138
139 #if defined(USE_PB_RAM_AS_SYSTEM_MEMORY)
140 /* See Step 1 from USE_SMU2_AS_SYSTEM_MEMORY */
141 ARM_MPU_SetRegionEx(MPU, PB_RAM_MAIR_IDX,
142 PB_RAM_CM33_BASE_ADDR,
143 PB_RAM_CM33_END_ADDR |
144 (MPU_RLAR_EN_Msk << MPU_RLAR_EN_Pos) |
145 (PB_RAM_MAIR_IDX << MPU_RLAR_AttrIndx_Pos));
146 /* See Step 2 from USE_SMU2_AS_SYSTEM_MEMORY */
147 ARM_MPU_SetMemAttrEx(MPU,
148 PB_RAM_MAIR_IDX,
149 ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE,
150 ARM_MPU_ATTR_NON_CACHEABLE));
151 #endif
152 #if defined(USE_SMU2_AS_SYSTEM_MEMORY) || \
153 defined(USE_PB_RAM_AS_SYSTEM_MEMORY)
154 /*
155 * Step 3: Enable the MPU, and also enable default memory map for the
156 * privileged software. This is needed due to 2 reasons:
157 * 1. we run as privileged software (TZ secure mode)
158 * 2. we don't "rewrite" set all the necessary memory zones in the
159 * MPU; this means that once MPU is enabled, not even the
160 * code area will be available to the core, leading to the core
161 * hanging (no response to the read requests)
162 *
163 */
164 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
165 #endif
166 SystemInitHook();
167 }
168
169 /* ----------------------------------------------------------------------------
170 -- SystemCoreClockUpdate()
171 ---------------------------------------------------------------------------- */
172
SystemCoreClockUpdate(void)173 void SystemCoreClockUpdate (void) {
174
175 }
176
177 /* ----------------------------------------------------------------------------
178 -- SystemInitHook()
179 ---------------------------------------------------------------------------- */
180
SystemInitHook(void)181 __attribute__ ((weak)) void SystemInitHook (void) {
182 /* Void implementation of the weak function. */
183 }
184
