1 /* 2 * Copyright 2022, NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef _FSL_POWER_H_ 8 #define _FSL_POWER_H_ 9 10 #include "fsl_common.h" 11 #include "fsl_device_registers.h" 12 #include <stdint.h> 13 14 /*! 15 * @addtogroup power 16 * @{ 17 */ 18 /******************************************************************************* 19 * Definitions 20 ******************************************************************************/ 21 22 /*! @name Driver version */ 23 /*@{*/ 24 /*! @brief power driver version 1.0.0. */ 25 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) 26 /*@}*/ 27 28 /* Power mode configuration API parameter */ 29 typedef enum _power_mode_config 30 { 31 kPmu_Sleep = 0U, 32 kPmu_Deep_Sleep = 1U, 33 kPmu_PowerDown = 2U, 34 kPmu_Deep_PowerDown = 3U, 35 } power_mode_cfg_t; 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 /******************************************************************************* 41 * API 42 ******************************************************************************/ 43 44 /** 45 * @brief Configures and enters in SLEEP low power mode 46 * @param : 47 * @return Nothing 48 */ 49 void POWER_EnterSleep(void); 50 51 /** 52 * @brief Configures and enters in DEEP-SLEEP low power mode 53 * @param exclude_from_pd: 54 * @param sram_retention_ctrl: 55 * @param wakeup_interrupts: 56 * @param hardware_wake_ctrl: 57 58 * @return Nothing 59 * 60 * !!! IMPORTANT NOTES : 61 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 62 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in 63 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 64 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be 65 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 66 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip 67 reset) reset) 68 */ 69 void POWER_EnterDeepSleep(uint32_t exclude_from_pd, 70 uint32_t sram_retention_ctrl, 71 uint64_t wakeup_interrupts, 72 uint32_t hardware_wake_ctrl); 73 74 /** 75 * @brief Configures and enters in POWERDOWN low power mode 76 * @param exclude_from_pd: 77 * @param sram_retention_ctrl: 78 * @param wakeup_interrupts: 79 * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are 80 RESERVED. 81 82 * @return Nothing 83 * 84 * !!! IMPORTANT NOTES : 85 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 86 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in 87 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 88 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be 89 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 90 * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance 91 containing the stack used to call this function WILL BE preserved during low power (via parameter 92 "sram_retention_ctrl") 93 * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip 94 reset) reset) 95 */ 96 97 void POWER_EnterPowerDown(uint32_t exclude_from_pd, 98 uint32_t sram_retention_ctrl, 99 uint64_t wakeup_interrupts, 100 uint32_t cpu_retention_ctrl); 101 102 /** 103 * @brief Configures and enters in DEEPPOWERDOWN low power mode 104 * @param exclude_from_pd: 105 * @param sram_retention_ctrl: 106 * @param wakeup_interrupts: 107 * @param wakeup_io_ctrl: 108 109 * @return Nothing 110 * 111 * !!! IMPORTANT NOTES : 112 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 113 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if 114 DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 115 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be 116 restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 117 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip 118 reset) 119 */ 120 void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, 121 uint32_t sram_retention_ctrl, 122 uint64_t wakeup_interrupts, 123 uint32_t wakeup_io_ctrl); 124 125 /*! 126 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. 127 * 128 * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, 129 * note that the voltage and flash wait states should be set before changing frequency 130 * @return none 131 */ 132 void POWER_SetVoltageForFreq(uint32_t system_freq_hz); 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 /** 139 * @} 140 */ 141 142 #endif /* _FSL_POWER_H_ */ 143