1 /*
2 ** ###################################################################
3 **     Processors:          MCXN236VDF
4 **                          MCXN236VNL
5 **
6 **     Compilers:           GNU C Compiler
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **                          Keil ARM C/C++ Compiler
9 **                          MCUXpresso Compiler
10 **
11 **     Reference manual:    MCXN23XRM
12 **     Version:             rev. 1.0, 2023-10-01
13 **     Build:               b240307
14 **
15 **     Abstract:
16 **         Provides a system configuration function and a global variable that
17 **         contains the system frequency. It configures the device and initializes
18 **         the oscillator (PLL) that is part of the microcontroller device.
19 **
20 **     Copyright 2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016-2024 NXP
22 **     SPDX-License-Identifier: BSD-3-Clause
23 **
24 **     http:                 www.nxp.com
25 **     mail:                 support@nxp.com
26 **
27 **     Revisions:
28 **     - rev. 1.0 (2023-10-01)
29 **         Initial version based on RM 1.2
30 **
31 ** ###################################################################
32 */
33 
34 /*!
35  * @file MCXN236
36  * @version 1.0
37  * @date 2023-10-01
38  * @brief Device specific configuration file for MCXN236 (implementation file)
39  *
40  * Provides a system configuration function and a global variable that contains
41  * the system frequency. It configures the device and initializes the oscillator
42  * (PLL) that is part of the microcontroller device.
43  */
44 
45 #include <stdint.h>
46 #include "fsl_device_registers.h"
47 
48 
49 
50 
51 
52 
53 /* ----------------------------------------------------------------------------
54    -- Core clock
55    ---------------------------------------------------------------------------- */
56 
57 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
58 
59 /* ----------------------------------------------------------------------------
60    -- SystemInit()
61    ---------------------------------------------------------------------------- */
62 
SystemInit(void)63 __attribute__ ((weak)) void SystemInit (void) {
64 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
65   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
66   #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
67   SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
68   #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
69 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
70 
71 
72   SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
73 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
74   SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
75 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
76 
77   SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
78 
79   SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */
80 
81   SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */
82 
83 #if !defined(__ZEPHYR__)
84 #if defined(__MCUXPRESSO)
85     extern void(*const g_pfnVectors[]) (void);
86     SCB->VTOR = (uint32_t) &g_pfnVectors;
87 #else
88     extern void *__Vectors;
89     SCB->VTOR = (uint32_t) &__Vectors;
90 #endif
91 #endif
92 
93     /* enable the flash cache LPCAC */
94     SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
95 
96     /* Disable aGDET trigger the CHIP_RESET */
97     ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
98     ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
99     /* Disable aGDET interrupt and reset */
100     SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
101     SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
102     SPC0->GLITCH_DETECT_SC = 0x3C;
103     SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
104 
105     /* Disable dGDET trigger the CHIP_RESET */
106     ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
107     ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
108     GDET0->GDET_ENABLE1 = 0;
109     GDET1->GDET_ENABLE1 = 0;
110 
111   SystemInitHook();
112 }
113 
114 /* ----------------------------------------------------------------------------
115    -- SystemCoreClockUpdate()
116    ---------------------------------------------------------------------------- */
117 
SystemCoreClockUpdate(void)118 void SystemCoreClockUpdate (void) {
119 
120 
121 
122 }
123 
124 /* ----------------------------------------------------------------------------
125    -- SystemInitHook()
126    ---------------------------------------------------------------------------- */
127 
SystemInitHook(void)128 __attribute__ ((weak)) void SystemInitHook (void) {
129   /* Void implementation of the weak function. */
130 }
131