1 /*
2 * Copyright 2022, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */
40 kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */
41 kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */
42 kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */
43 kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */
44 kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */
45 kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */
46 kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */
47 kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */
48 kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */
49 kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */
50 kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */
51 kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */
52 kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */
53 kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */
54
55 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
56 kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */
57 kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */
58 kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */
59 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
60 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
61 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
62 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
63 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
64 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
65 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
66 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
67 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
68 kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */
69 kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
70 kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */
71 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
72 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
73 kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */
74
75 kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
76 kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */
77 kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */
78 kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */
79 kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */
80 kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */
81 kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
82 kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */
83 kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */
84 kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */
85 kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */
86 kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */
87 kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
88 kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
89 kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
90 kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */
91 kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */
92
93 kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */
94 kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */
95 kQDC0_RST_SHIFT_RSTn = 196608 | 4U, /**< QDC0 reset control */
96 kQDC1_RST_SHIFT_RSTn = 196608 | 5U, /**< QDC1 reset control */
97 kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */
98 kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */
99 kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */
100 kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */
101 kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */
102 kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */
103 } SYSCON_RSTn_t;
104
105 /** Array initializers with peripheral reset bits **/
106 #define ADC_RSTS \
107 { \
108 kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
109 } /* Reset bits for ADC peripheral */
110 #define CRC_RSTS \
111 { \
112 kCRC_RST_SHIFT_RSTn \
113 } /* Reset bits for CRC peripheral */
114 #define CTIMER_RSTS \
115 { \
116 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
117 kCTIMER4_RST_SHIFT_RSTn \
118 } /* Reset bits for CTIMER peripheral */
119 #define DMA_RSTS_N \
120 { \
121 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
122 } /* Reset bits for DMA peripheral */
123
124 #define LP_FLEXCOMM_RSTS \
125 { \
126 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
127 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \
128 } /* Reset bits for FLEXCOMM peripheral */
129 #define GPIO_RSTS_N \
130 { \
131 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
132 kGPIO4_RST_SHIFT_RSTn \
133 } /* Reset bits for GPIO peripheral */
134 #define INPUTMUX_RSTS \
135 { \
136 kMUX_RST_SHIFT_RSTn \
137 } /* Reset bits for INPUTMUX peripheral */
138 #define FLASH_RSTS \
139 { \
140 kFMC_RST_SHIFT_RSTn \
141 } /* Reset bits for Flash peripheral */
142 #define MRT_RSTS \
143 { \
144 kMRT_RST_SHIFT_RSTn \
145 } /* Reset bits for MRT peripheral */
146 #define PINT_RSTS \
147 { \
148 kPINT_RST_SHIFT_RSTn \
149 } /* Reset bits for PINT peripheral */
150 #define TRNG_RSTS \
151 { \
152 kTRNG_RST_SHIFT_RSTn \
153 } /* Reset bits for TRNG peripheral */
154 #define UTICK_RSTS \
155 { \
156 kUTICK_RST_SHIFT_RSTn \
157 } /* Reset bits for UTICK peripheral */
158 #define OSTIMER_RSTS \
159 { \
160 kOSTIMER_RST_SHIFT_RSTn \
161 } /* Reset bits for OSTIMER peripheral */
162 #define I3C_RSTS \
163 { \
164 kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \
165 } /* Reset bits for I3C peripheral */
166 typedef SYSCON_RSTn_t reset_ip_name_t;
167
168 /*******************************************************************************
169 * API
170 ******************************************************************************/
171 #if defined(__cplusplus)
172 extern "C" {
173 #endif
174
175 /*!
176 * @brief Assert reset to peripheral.
177 *
178 * Asserts reset signal to specified peripheral module.
179 *
180 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
181 * and reset bit position in the reset register.
182 */
183 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
184
185 /*!
186 * @brief Clear reset to peripheral.
187 *
188 * Clears reset signal to specified peripheral module, allows it to operate.
189 *
190 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
191 * and reset bit position in the reset register.
192 */
193 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
194
195 /*!
196 * @brief Reset peripheral module.
197 *
198 * Reset peripheral module.
199 *
200 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
201 * and reset bit position in the reset register.
202 */
203 void RESET_PeripheralReset(reset_ip_name_t peripheral);
204
205 /*!
206 * @brief Release peripheral module.
207 *
208 * Release peripheral module.
209 *
210 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
211 * and reset bit position in the reset register.
212 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)213 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
214 {
215 RESET_ClearPeripheralReset(peripheral);
216 }
217
218 #if defined(__cplusplus)
219 }
220 #endif
221
222 /*! @} */
223
224 #endif /* _FSL_RESET_H_ */
225
