1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2024-03-11 4 ** Build: b240411 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2024-03-11) 18 ** Initial version. 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _MCXC243_FEATURES_H_ 24 #define _MCXC243_FEATURES_H_ 25 26 /* SOC module features */ 27 28 /* @brief ADC16 availability on the SoC. */ 29 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 30 /* @brief CMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_CMP_COUNT (1) 32 /* @brief DAC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_DAC_COUNT (1) 34 /* @brief DMA availability on the SoC. */ 35 #define FSL_FEATURE_SOC_DMA_COUNT (1) 36 /* @brief DMAMUX availability on the SoC. */ 37 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 38 /* @brief FGPIO availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 40 /* @brief FLEXIO availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 42 /* @brief FTFA availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 46 /* @brief I2C availability on the SoC. */ 47 #define FSL_FEATURE_SOC_I2C_COUNT (2) 48 /* @brief I2S availability on the SoC. */ 49 #define FSL_FEATURE_SOC_I2S_COUNT (1) 50 /* @brief LLWU availability on the SoC. */ 51 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 52 /* @brief LPTMR availability on the SoC. */ 53 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 54 /* @brief LPUART availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LPUART_COUNT (2) 56 /* @brief MCGLITE availability on the SoC. */ 57 #define FSL_FEATURE_SOC_MCGLITE_COUNT (1) 58 /* @brief MCM availability on the SoC. */ 59 #define FSL_FEATURE_SOC_MCM_COUNT (1) 60 /* @brief MTB availability on the SoC. */ 61 #define FSL_FEATURE_SOC_MTB_COUNT (1) 62 /* @brief MTBDWT availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 64 /* @brief OSC availability on the SoC. */ 65 #define FSL_FEATURE_SOC_OSC_COUNT (1) 66 /* @brief PIT availability on the SoC. */ 67 #define FSL_FEATURE_SOC_PIT_COUNT (1) 68 /* @brief PMC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PMC_COUNT (1) 70 /* @brief PORT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_PORT_COUNT (5) 72 /* @brief RCM availability on the SoC. */ 73 #define FSL_FEATURE_SOC_RCM_COUNT (1) 74 /* @brief RFSYS availability on the SoC. */ 75 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 76 /* @brief ROM availability on the SoC. */ 77 #define FSL_FEATURE_SOC_ROM_COUNT (1) 78 /* @brief RTC availability on the SoC. */ 79 #define FSL_FEATURE_SOC_RTC_COUNT (1) 80 /* @brief SIM availability on the SoC. */ 81 #define FSL_FEATURE_SOC_SIM_COUNT (1) 82 /* @brief SMC availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SMC_COUNT (1) 84 /* @brief SPI availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SPI_COUNT (2) 86 /* @brief TPM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_TPM_COUNT (3) 88 /* @brief UART availability on the SoC. */ 89 #define FSL_FEATURE_SOC_UART_COUNT (1) 90 /* @brief USB availability on the SoC. */ 91 #define FSL_FEATURE_SOC_USB_COUNT (1) 92 /* @brief VREF availability on the SoC. */ 93 #define FSL_FEATURE_SOC_VREF_COUNT (1) 94 95 /* ADC16 module features */ 96 97 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 98 #define FSL_FEATURE_ADC16_HAS_PGA (0) 99 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 100 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 101 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 102 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 103 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 104 #define FSL_FEATURE_ADC16_HAS_DMA (1) 105 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 106 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 107 /* @brief Has FIFO (bit SC4[AFDEP]). */ 108 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 109 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 110 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 111 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 112 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 113 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 114 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 115 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 116 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 117 /* @brief Has HW averaging (bit SC3[AVGE]). */ 118 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 119 /* @brief Has offset correction (register OFS). */ 120 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 121 /* @brief Maximum ADC resolution. */ 122 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 123 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 124 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 125 126 /* CMP module features */ 127 128 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 129 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 130 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 131 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) 132 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 133 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) 134 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 135 #define FSL_FEATURE_CMP_HAS_DMA (1) 136 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 137 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 138 /* @brief Has DAC Test function in CMP (register DACTEST). */ 139 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 140 141 /* COP module features */ 142 143 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ 144 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) 145 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ 146 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) 147 /* @brief Has more clock sources like MCGIRC */ 148 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) 149 /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ 150 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) 151 152 /* DAC module features */ 153 154 /* @brief Define the size of hardware buffer */ 155 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 156 /* @brief Define whether the buffer supports watermark event detection or not. */ 157 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) 158 /* @brief Define whether the buffer supports watermark selection detection or not. */ 159 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) 160 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 161 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) 162 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 163 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) 164 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 165 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) 166 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 167 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) 168 /* @brief Define whether FIFO buffer mode is available or not. */ 169 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 170 /* @brief Define whether swing buffer mode is available or not.. */ 171 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 172 173 /* DMA module features */ 174 175 /* @brief Number of DMA channels. */ 176 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) 177 /* @brief Total number of DMA channels on all modules. */ 178 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (4) 179 180 /* DMAMUX module features */ 181 182 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 183 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 184 /* @brief Total number of DMA channels on all modules. */ 185 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 186 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 187 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 188 /* @brief Register CHCFGn width. */ 189 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 190 191 /* FGPIO module features */ 192 193 /* No feature definitions */ 194 195 /* FLEXIO module features */ 196 197 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 198 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 199 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 200 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0) 201 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 202 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) 203 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 204 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) 205 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 206 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) 207 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 208 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) 209 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 210 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) 211 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 212 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) 213 /* @brief Reset value of the FLEXIO_VERID register */ 214 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000) 215 /* @brief Reset value of the FLEXIO_PARAM register */ 216 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404) 217 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 218 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) 219 /* @brief Flexio DMA request base channel */ 220 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 221 222 /* FLASH module features */ 223 224 /* @brief Is of type FTFA. */ 225 #define FSL_FEATURE_FLASH_IS_FTFA (1) 226 /* @brief Is of type FTFE. */ 227 #define FSL_FEATURE_FLASH_IS_FTFE (0) 228 /* @brief Is of type FTFL. */ 229 #define FSL_FEATURE_FLASH_IS_FTFL (0) 230 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 231 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 232 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 233 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 234 /* @brief Has EEPROM region protection (register FEPROT). */ 235 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 236 /* @brief Has data flash region protection (register FDPROT). */ 237 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 238 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 239 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 240 /* @brief Has flash cache control in FMC module. */ 241 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 242 /* @brief Has flash cache control in MCM module. */ 243 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 244 /* @brief Has flash cache control in MSCM module. */ 245 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 246 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 247 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 248 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 249 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 250 /* @brief P-Flash start address. */ 251 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 252 /* @brief P-Flash block count. */ 253 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 254 /* @brief P-Flash block size. */ 255 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 256 /* @brief P-Flash sector size. */ 257 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 258 /* @brief P-Flash write unit size. */ 259 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 260 /* @brief P-Flash data path width. */ 261 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 262 /* @brief P-Flash block swap feature. */ 263 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 264 /* @brief P-Flash protection region count. */ 265 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 266 /* @brief Has FlexNVM memory. */ 267 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 268 /* @brief Has FlexNVM alias. */ 269 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 270 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 271 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 272 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 273 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 274 /* @brief FlexNVM block count. */ 275 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 276 /* @brief FlexNVM block size. */ 277 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 278 /* @brief FlexNVM sector size. */ 279 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 280 /* @brief FlexNVM write unit size. */ 281 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 282 /* @brief FlexNVM data path width. */ 283 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 284 /* @brief Has FlexRAM memory. */ 285 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 286 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 287 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 288 /* @brief FlexRAM size. */ 289 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 290 /* @brief Has 0x00 Read 1s Block command. */ 291 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 292 /* @brief Has 0x01 Read 1s Section command. */ 293 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 294 /* @brief Has 0x02 Program Check command. */ 295 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 296 /* @brief Has 0x03 Read Resource command. */ 297 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 298 /* @brief Has 0x06 Program Longword command. */ 299 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 300 /* @brief Has 0x07 Program Phrase command. */ 301 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 302 /* @brief Has 0x08 Erase Flash Block command. */ 303 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 304 /* @brief Has 0x09 Erase Flash Sector command. */ 305 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 306 /* @brief Has 0x0B Program Section command. */ 307 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 308 /* @brief Has 0x40 Read 1s All Blocks command. */ 309 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 310 /* @brief Has 0x41 Read Once command. */ 311 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 312 /* @brief Has 0x43 Program Once command. */ 313 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 314 /* @brief Has 0x44 Erase All Blocks command. */ 315 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 316 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 317 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 318 /* @brief Has 0x46 Swap Control command. */ 319 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 320 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 321 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 322 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 323 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 324 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 325 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 326 /* @brief Has 0x80 Program Partition command. */ 327 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 328 /* @brief Has 0x81 Set FlexRAM Function command. */ 329 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 330 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 331 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 332 /* @brief P-Flash Erase sector command address alignment. */ 333 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 334 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 335 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 336 /* @brief P-Flash Read resource command address alignment. */ 337 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 338 /* @brief P-Flash Program check command address alignment. */ 339 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 340 /* @brief P-Flash Program check command address alignment. */ 341 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 342 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 343 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 344 /* @brief FlexNVM Erase sector command address alignment. */ 345 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 346 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 347 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 348 /* @brief FlexNVM Read resource command address alignment. */ 349 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 350 /* @brief FlexNVM Program check command address alignment. */ 351 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 352 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 353 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 354 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 355 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 356 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 357 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 358 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 359 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 360 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 362 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 364 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 366 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 368 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 370 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 372 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 374 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 376 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 378 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 380 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 382 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 384 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 386 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 388 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 390 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 392 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 394 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 396 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 398 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 400 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 402 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 404 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 406 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 408 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 410 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 412 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 414 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 416 417 /* GPIO module features */ 418 419 /* @brief Has GPIO attribute checker register (GACR). */ 420 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 421 422 /* I2C module features */ 423 424 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 425 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 426 /* @brief Maximum supported baud rate in kilobit per second. */ 427 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 428 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 429 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 430 /* @brief Has DMA support (register bit C1[DMAEN]). */ 431 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 432 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 433 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 434 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 435 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 436 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 437 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 438 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 439 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 440 /* @brief Has control of the drive capability of the I2C pins. */ 441 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 442 /* @brief Has double buffering support (register S2). */ 443 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 444 /* @brief Has double buffer enable. */ 445 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 446 447 /* SAI module features */ 448 449 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 450 #define FSL_FEATURE_SAI_HAS_FIFO (0) 451 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 452 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (0) 453 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 454 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (1) 455 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 456 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) 457 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 458 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 459 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 460 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 461 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 462 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 463 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 464 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 465 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 466 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 467 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 468 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 469 /* @brief Ihe interrupt source number */ 470 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 471 /* @brief Has register of MCR. */ 472 #define FSL_FEATURE_SAI_HAS_MCR (1) 473 /* @brief Has register of MDR */ 474 #define FSL_FEATURE_SAI_HAS_MDR (0) 475 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 476 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 477 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 478 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 479 480 /* LLWU module features */ 481 482 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 483 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 484 /* @brief Has pins 8-15 connected to LLWU device. */ 485 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 486 /* @brief Maximum number of internal modules connected to LLWU device. */ 487 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 488 /* @brief Number of digital filters. */ 489 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 490 /* @brief Has MF register. */ 491 #define FSL_FEATURE_LLWU_HAS_MF (0) 492 /* @brief Has PF register. */ 493 #define FSL_FEATURE_LLWU_HAS_PF (0) 494 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 495 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 496 /* @brief Has no internal module wakeup flag register. */ 497 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 498 /* @brief Has external pin 0 connected to LLWU device. */ 499 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 500 /* @brief Index of port of external pin. */ 501 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 502 /* @brief Number of external pin port on specified port. */ 503 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 504 /* @brief Has external pin 1 connected to LLWU device. */ 505 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 506 /* @brief Index of port of external pin. */ 507 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 508 /* @brief Number of external pin port on specified port. */ 509 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 510 /* @brief Has external pin 2 connected to LLWU device. */ 511 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 512 /* @brief Index of port of external pin. */ 513 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 514 /* @brief Number of external pin port on specified port. */ 515 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 516 /* @brief Has external pin 3 connected to LLWU device. */ 517 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) 518 /* @brief Index of port of external pin. */ 519 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) 520 /* @brief Number of external pin port on specified port. */ 521 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) 522 /* @brief Has external pin 4 connected to LLWU device. */ 523 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 524 /* @brief Index of port of external pin. */ 525 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 526 /* @brief Number of external pin port on specified port. */ 527 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 528 /* @brief Has external pin 5 connected to LLWU device. */ 529 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 530 /* @brief Index of port of external pin. */ 531 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 532 /* @brief Number of external pin port on specified port. */ 533 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 534 /* @brief Has external pin 6 connected to LLWU device. */ 535 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 536 /* @brief Index of port of external pin. */ 537 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 538 /* @brief Number of external pin port on specified port. */ 539 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 540 /* @brief Has external pin 7 connected to LLWU device. */ 541 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 542 /* @brief Index of port of external pin. */ 543 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 544 /* @brief Number of external pin port on specified port. */ 545 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 546 /* @brief Has external pin 8 connected to LLWU device. */ 547 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 548 /* @brief Index of port of external pin. */ 549 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 550 /* @brief Number of external pin port on specified port. */ 551 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 552 /* @brief Has external pin 9 connected to LLWU device. */ 553 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 554 /* @brief Index of port of external pin. */ 555 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 556 /* @brief Number of external pin port on specified port. */ 557 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 558 /* @brief Has external pin 10 connected to LLWU device. */ 559 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 560 /* @brief Index of port of external pin. */ 561 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 562 /* @brief Number of external pin port on specified port. */ 563 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 564 /* @brief Has external pin 11 connected to LLWU device. */ 565 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 566 /* @brief Index of port of external pin. */ 567 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 568 /* @brief Number of external pin port on specified port. */ 569 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 570 /* @brief Has external pin 12 connected to LLWU device. */ 571 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 572 /* @brief Index of port of external pin. */ 573 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 574 /* @brief Number of external pin port on specified port. */ 575 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 576 /* @brief Has external pin 13 connected to LLWU device. */ 577 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 578 /* @brief Index of port of external pin. */ 579 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 580 /* @brief Number of external pin port on specified port. */ 581 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 582 /* @brief Has external pin 14 connected to LLWU device. */ 583 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 584 /* @brief Index of port of external pin. */ 585 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 586 /* @brief Number of external pin port on specified port. */ 587 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 588 /* @brief Has external pin 15 connected to LLWU device. */ 589 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 590 /* @brief Index of port of external pin. */ 591 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 592 /* @brief Number of external pin port on specified port. */ 593 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 594 /* @brief Has external pin 16 connected to LLWU device. */ 595 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 596 /* @brief Index of port of external pin. */ 597 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 598 /* @brief Number of external pin port on specified port. */ 599 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 600 /* @brief Has external pin 17 connected to LLWU device. */ 601 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 602 /* @brief Index of port of external pin. */ 603 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 604 /* @brief Number of external pin port on specified port. */ 605 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 606 /* @brief Has external pin 18 connected to LLWU device. */ 607 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 608 /* @brief Index of port of external pin. */ 609 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 610 /* @brief Number of external pin port on specified port. */ 611 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 612 /* @brief Has external pin 19 connected to LLWU device. */ 613 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 614 /* @brief Index of port of external pin. */ 615 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 616 /* @brief Number of external pin port on specified port. */ 617 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 618 /* @brief Has external pin 20 connected to LLWU device. */ 619 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 620 /* @brief Index of port of external pin. */ 621 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 622 /* @brief Number of external pin port on specified port. */ 623 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 624 /* @brief Has external pin 21 connected to LLWU device. */ 625 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 626 /* @brief Index of port of external pin. */ 627 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 628 /* @brief Number of external pin port on specified port. */ 629 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 630 /* @brief Has external pin 22 connected to LLWU device. */ 631 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 632 /* @brief Index of port of external pin. */ 633 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 634 /* @brief Number of external pin port on specified port. */ 635 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 636 /* @brief Has external pin 23 connected to LLWU device. */ 637 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 638 /* @brief Index of port of external pin. */ 639 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 640 /* @brief Number of external pin port on specified port. */ 641 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 642 /* @brief Has external pin 24 connected to LLWU device. */ 643 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 644 /* @brief Index of port of external pin. */ 645 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 646 /* @brief Number of external pin port on specified port. */ 647 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 648 /* @brief Has external pin 25 connected to LLWU device. */ 649 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 650 /* @brief Index of port of external pin. */ 651 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 652 /* @brief Number of external pin port on specified port. */ 653 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 654 /* @brief Has external pin 26 connected to LLWU device. */ 655 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 656 /* @brief Index of port of external pin. */ 657 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 658 /* @brief Number of external pin port on specified port. */ 659 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 660 /* @brief Has external pin 27 connected to LLWU device. */ 661 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 662 /* @brief Index of port of external pin. */ 663 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 664 /* @brief Number of external pin port on specified port. */ 665 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 666 /* @brief Has external pin 28 connected to LLWU device. */ 667 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 668 /* @brief Index of port of external pin. */ 669 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 670 /* @brief Number of external pin port on specified port. */ 671 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 672 /* @brief Has external pin 29 connected to LLWU device. */ 673 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 674 /* @brief Index of port of external pin. */ 675 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 676 /* @brief Number of external pin port on specified port. */ 677 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 678 /* @brief Has external pin 30 connected to LLWU device. */ 679 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 680 /* @brief Index of port of external pin. */ 681 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 682 /* @brief Number of external pin port on specified port. */ 683 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 684 /* @brief Has external pin 31 connected to LLWU device. */ 685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 686 /* @brief Index of port of external pin. */ 687 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 688 /* @brief Number of external pin port on specified port. */ 689 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 690 /* @brief Has internal module 0 connected to LLWU device. */ 691 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 692 /* @brief Has internal module 1 connected to LLWU device. */ 693 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 694 /* @brief Has internal module 2 connected to LLWU device. */ 695 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 696 /* @brief Has internal module 3 connected to LLWU device. */ 697 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 698 /* @brief Has internal module 4 connected to LLWU device. */ 699 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 700 /* @brief Has internal module 5 connected to LLWU device. */ 701 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 702 /* @brief Has internal module 6 connected to LLWU device. */ 703 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 704 /* @brief Has internal module 7 connected to LLWU device. */ 705 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 706 /* @brief Has Version ID Register (LLWU_VERID). */ 707 #define FSL_FEATURE_LLWU_HAS_VERID (0) 708 /* @brief Has Parameter Register (LLWU_PARAM). */ 709 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 710 /* @brief Width of registers of the LLWU. */ 711 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 712 /* @brief Has DMA Enable register (LLWU_DE). */ 713 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 714 715 /* LPTMR module features */ 716 717 /* @brief Has shared interrupt handler with another LPTMR module. */ 718 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 719 /* @brief Whether LPTMR counter is 32 bits width. */ 720 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 721 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 722 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 723 724 /* LPUART module features */ 725 726 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 727 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 728 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 729 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 730 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 731 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 732 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 733 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 734 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 735 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 736 /* @brief Has 32-bit register MODIR */ 737 #define FSL_FEATURE_LPUART_HAS_MODIR (0) 738 /* @brief Hardware flow control (RTS, CTS) is supported. */ 739 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) 740 /* @brief Infrared (modulation) is supported. */ 741 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) 742 /* @brief 2 bits long stop bit is available. */ 743 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 744 /* @brief If 10-bit mode is supported. */ 745 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 746 /* @brief If 7-bit mode is supported. */ 747 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 748 /* @brief Baud rate fine adjustment is available. */ 749 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 750 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 751 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 752 /* @brief Baud rate oversampling is available. */ 753 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 754 /* @brief Baud rate oversampling is available. */ 755 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 756 /* @brief Peripheral type. */ 757 #define FSL_FEATURE_LPUART_IS_SCI (1) 758 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 759 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 760 /* @brief Supports two match addresses to filter incoming frames. */ 761 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 762 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 763 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 764 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 765 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 766 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 767 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 768 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 769 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 770 /* @brief Has improved smart card (ISO7816 protocol) support. */ 771 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 772 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 773 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 774 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 775 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 776 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 777 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 778 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 779 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 780 /* @brief Has separate DMA RX and TX requests. */ 781 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 782 /* @brief Has separate RX and TX interrupts. */ 783 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 784 /* @brief Has LPAURT_PARAM. */ 785 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 786 /* @brief Has LPUART_VERID. */ 787 #define FSL_FEATURE_LPUART_HAS_VERID (0) 788 /* @brief Has LPUART_GLOBAL. */ 789 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 790 /* @brief Has LPUART_PINCFG. */ 791 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 792 793 /* MCGLITE module features */ 794 795 /* @brief Defines that clock generator is MCG Lite. */ 796 #define FSL_FEATURE_MCGLITE_MCGLITE (1) 797 /* @brief Has Crystal Oscillator Operation Mode Selection. */ 798 #define FSL_FEATURE_MCGLITE_HAS_HGO0 (1) 799 /* @brief Has HCTRIM register available. */ 800 #define FSL_FEATURE_MCGLITE_HAS_HCTRIM (1) 801 /* @brief Has HTTRIM register available. */ 802 #define FSL_FEATURE_MCGLITE_HAS_HTTRIM (1) 803 /* @brief Has HFTRIM register available. */ 804 #define FSL_FEATURE_MCGLITE_HAS_HFTRIM (1) 805 /* @brief Has LTRIMRNG register available. */ 806 #define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (1) 807 /* @brief Has LFTRIM register available. */ 808 #define FSL_FEATURE_MCGLITE_HAS_LFTRIM (1) 809 /* @brief Has LSTRIM register available. */ 810 #define FSL_FEATURE_MCGLITE_HAS_LSTRIM (1) 811 /* @brief Has External Clock Source Frequency Range Selection. */ 812 #define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1) 813 814 /* interrupt module features */ 815 816 /* @brief Lowest interrupt request number. */ 817 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 818 /* @brief Highest interrupt request number. */ 819 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 820 821 /* OSC module features */ 822 823 /* @brief Has OSC1 external oscillator. */ 824 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 825 /* @brief Has OSC0 external oscillator. */ 826 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 827 /* @brief Has OSC external oscillator (without index). */ 828 #define FSL_FEATURE_OSC_HAS_OSC (0) 829 /* @brief Number of OSC external oscillators. */ 830 #define FSL_FEATURE_OSC_OSC_COUNT (1) 831 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 832 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 833 834 /* PIT module features */ 835 836 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 837 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 838 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 839 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 840 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 841 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 842 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 843 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 844 /* @brief Has timer enable control. */ 845 #define FSL_FEATURE_PIT_HAS_MDIS (1) 846 /* @brief Has ERRATA 7914. */ 847 #define FSL_FEATURE_PIT_HAS_ERRATA_7914 (1) 848 849 /* PMC module features */ 850 851 /* @brief Has Bandgap Enable In VLPx Operation support. */ 852 #define FSL_FEATURE_PMC_HAS_BGEN (1) 853 /* @brief Has Bandgap Buffer Enable. */ 854 #define FSL_FEATURE_PMC_HAS_BGBE (1) 855 /* @brief Has Bandgap Buffer Drive Select. */ 856 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 857 /* @brief Has Low-Voltage Detect Voltage Select support. */ 858 #define FSL_FEATURE_PMC_HAS_LVDV (1) 859 /* @brief Has Low-Voltage Warning Voltage Select support. */ 860 #define FSL_FEATURE_PMC_HAS_LVWV (1) 861 /* @brief Has LPO. */ 862 #define FSL_FEATURE_PMC_HAS_LPO (0) 863 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 864 #define FSL_FEATURE_PMC_HAS_VLPO (0) 865 /* @brief Has acknowledge isolation support. */ 866 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 867 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 868 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 869 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 870 #define FSL_FEATURE_PMC_HAS_REGONS (1) 871 /* @brief Has PMC_HVDSC1. */ 872 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 873 /* @brief Has PMC_PARAM. */ 874 #define FSL_FEATURE_PMC_HAS_PARAM (0) 875 /* @brief Has PMC_VERID. */ 876 #define FSL_FEATURE_PMC_HAS_VERID (0) 877 878 /* PORT module features */ 879 880 /* @brief Has control lock (register bit PCR[LK]). */ 881 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 882 /* @brief Has open drain control (register bit PCR[ODE]). */ 883 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 884 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 885 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 886 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 887 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 888 /* @brief Has pull resistor selection available. */ 889 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 890 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 891 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 892 /* @brief Has slew rate control (register bit PCR[SRE]). */ 893 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 894 /* @brief Has passive filter (register bit field PCR[PFE]). */ 895 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 896 /* @brief Has drive strength control (register bit PCR[DSE]). */ 897 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 898 /* @brief Has separate drive strength register (HDRVE). */ 899 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 900 /* @brief Has glitch filter (register IOFLT). */ 901 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 902 /* @brief Defines width of PCR[MUX] field. */ 903 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 904 /* @brief Has dedicated interrupt vector. */ 905 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 906 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 907 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 908 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 909 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 910 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 911 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 912 913 /* RCM module features */ 914 915 /* @brief Has Loss-of-Lock Reset support. */ 916 #define FSL_FEATURE_RCM_HAS_LOL (0) 917 /* @brief Has Loss-of-Clock Reset support. */ 918 #define FSL_FEATURE_RCM_HAS_LOC (0) 919 /* @brief Has JTAG generated Reset support. */ 920 #define FSL_FEATURE_RCM_HAS_JTAG (0) 921 /* @brief Has EzPort generated Reset support. */ 922 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 923 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 924 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 925 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 926 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 927 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 928 #define FSL_FEATURE_RCM_HAS_SSRS (1) 929 /* @brief Has Version ID Register (RCM_VERID). */ 930 #define FSL_FEATURE_RCM_HAS_VERID (0) 931 /* @brief Has Parameter Register (RCM_PARAM). */ 932 #define FSL_FEATURE_RCM_HAS_PARAM (0) 933 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 934 #define FSL_FEATURE_RCM_HAS_SRIE (0) 935 /* @brief Width of registers of the RCM. */ 936 #define FSL_FEATURE_RCM_REG_WIDTH (8) 937 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 938 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 939 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 940 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 941 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 942 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 943 944 /* RTC module features */ 945 946 /* @brief Has wakeup pin. */ 947 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 948 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 949 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 950 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 951 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 952 /* @brief Has read/write access control (registers WAR and RAR). */ 953 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 954 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 955 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 956 /* @brief Has RTC_CLKIN available. */ 957 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 958 /* @brief Has prescaler adjust for LPO. */ 959 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 960 /* @brief Has Clock Pin Enable field. */ 961 #define FSL_FEATURE_RTC_HAS_CPE (0) 962 /* @brief Has Timer Seconds Interrupt Configuration field. */ 963 #define FSL_FEATURE_RTC_HAS_TSIC (0) 964 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 965 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 966 /* @brief Has Tamper Interrupt Register (register TIR). */ 967 #define FSL_FEATURE_RTC_HAS_TIR (0) 968 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 969 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 970 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 971 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 972 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 973 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 974 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 975 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 976 /* @brief Has Tamper Detect Register (register TDR). */ 977 #define FSL_FEATURE_RTC_HAS_TDR (0) 978 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 979 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 980 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 981 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 982 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 983 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 984 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 985 #define FSL_FEATURE_RTC_HAS_TTSR (0) 986 /* @brief Has Pin Configuration Register (register PCR). */ 987 #define FSL_FEATURE_RTC_HAS_PCR (0) 988 989 /* SIM module features */ 990 991 /* @brief Has USB FS divider. */ 992 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 993 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 994 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 995 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 996 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 997 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 998 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) 999 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1000 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1001 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1002 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1003 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1004 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1005 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1006 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1007 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1008 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1009 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1010 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1011 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1012 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1013 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1014 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1015 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1016 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1017 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1018 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 1019 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1020 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2) 1021 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1022 #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) 1023 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1024 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1025 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1026 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1027 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1028 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) 1029 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1030 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) 1031 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1032 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) 1033 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1034 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1035 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1036 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1037 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1038 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1039 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1040 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) 1041 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1042 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) 1043 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1044 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1045 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1046 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1047 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1048 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1049 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1050 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1051 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1052 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1053 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1054 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1055 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1056 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1057 /* @brief Has FTM module(s) configuration. */ 1058 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1059 /* @brief Number of FTM modules. */ 1060 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1061 /* @brief Number of FTM triggers with selectable source. */ 1062 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1063 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1064 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1065 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1066 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1067 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1068 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1069 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1070 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1071 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1072 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1073 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1074 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1075 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1076 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1077 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1078 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1079 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1080 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1081 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1082 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1083 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1084 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1085 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1086 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1087 /* @brief Has TPM module(s) configuration. */ 1088 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1089 /* @brief The highest TPM module index. */ 1090 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1091 /* @brief Has TPM module with index 0. */ 1092 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) 1093 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1094 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) 1095 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1096 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) 1097 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1098 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1099 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1100 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) 1101 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1102 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) 1103 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1104 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) 1105 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1106 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) 1107 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1108 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1109 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1110 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1111 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1112 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1113 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1114 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1115 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1116 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1117 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1118 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1119 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1120 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1121 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1122 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1123 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1124 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1125 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1126 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1127 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1128 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1129 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1130 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1131 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1132 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) 1133 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1134 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) 1135 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1136 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) 1137 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1138 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1139 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1140 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1141 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1142 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1143 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1144 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1145 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1146 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1147 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1148 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1149 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1150 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1151 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1152 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1153 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1154 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1155 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1156 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1157 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1158 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1159 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1160 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1161 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1162 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1163 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1164 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1165 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1166 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1167 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1168 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1169 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1170 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1171 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1172 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1173 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1174 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1175 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1176 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1177 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1178 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) 1179 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1180 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1181 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1182 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1183 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1184 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1185 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1186 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1187 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1188 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1189 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1190 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1191 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1192 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1193 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1194 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1195 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1196 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1197 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1198 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1199 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1200 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1201 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1202 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1203 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1204 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1205 /* @brief Has miscellanious control register (register MCR). */ 1206 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1207 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1208 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) 1209 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1210 #define FSL_FEATURE_SIM_HAS_COP_STOP (1) 1211 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1212 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1213 /* @brief Has UIDH registers. */ 1214 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1215 /* @brief Has UIDM registers. */ 1216 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1217 1218 /* SMC module features */ 1219 1220 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1221 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1222 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1223 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1224 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1225 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1226 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1227 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1228 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1229 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1230 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1231 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1232 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1233 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1234 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1235 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1236 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1237 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1238 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1239 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1240 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1241 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1242 /* @brief Has stop submode. */ 1243 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1244 /* @brief Has stop submode 0(VLLS0). */ 1245 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1246 /* @brief Has stop submode 1(VLLS1). */ 1247 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1248 /* @brief Has stop submode 2(VLLS2). */ 1249 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1250 /* @brief Has SMC_PARAM. */ 1251 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1252 /* @brief Has SMC_VERID. */ 1253 #define FSL_FEATURE_SMC_HAS_VERID (0) 1254 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1255 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1256 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1257 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1258 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1259 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1260 /* @brief Width of SMC registers. */ 1261 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1262 1263 /* SPI module features */ 1264 1265 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1266 #define FSL_FEATURE_SPI_HAS_FIFO (1) 1267 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 1268 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 1269 /* @brief Has separate DMA RX and TX requests. */ 1270 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1271 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 1272 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ 1273 (((x) == SPI0) ? (0) : \ 1274 (((x) == SPI1) ? (4) : (-1))) 1275 /* @brief Maximum transfer data width in bits. */ 1276 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) 1277 /* @brief The data register name has postfix (L as low and H as high). */ 1278 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) 1279 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1280 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1281 /* @brief Has 16-bit data transfer support. */ 1282 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) 1283 1284 /* SysTick module features */ 1285 1286 /* @brief Systick has external reference clock. */ 1287 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1288 /* @brief Systick external reference clock is core clock divided by this value. */ 1289 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1290 1291 /* TPM module features */ 1292 1293 /* @brief Bus clock is the source clock for the module. */ 1294 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1295 /* @brief Number of channels. */ 1296 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1297 (((x) == TPM0) ? (6) : \ 1298 (((x) == TPM1) ? (2) : \ 1299 (((x) == TPM2) ? (2) : (-1)))) 1300 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1301 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1302 /* @brief Has TPM_PARAM. */ 1303 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1304 /* @brief Has TPM_VERID. */ 1305 #define FSL_FEATURE_TPM_HAS_VERID (0) 1306 /* @brief Has TPM_GLOBAL. */ 1307 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1308 /* @brief Has TPM_TRIG. */ 1309 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1310 /* @brief Whether TRIG register has effect. */ 1311 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ 1312 (((x) == TPM0) ? (1) : \ 1313 (((x) == TPM1) ? (0) : \ 1314 (((x) == TPM2) ? (0) : (-1)))) 1315 /* @brief Has counter pause on trigger. */ 1316 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1317 /* @brief Has external trigger selection. */ 1318 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1319 /* @brief Has TPM_COMBINE register. */ 1320 #define FSL_FEATURE_TPM_HAS_COMBINE (0) 1321 /* @brief Whether COMBINE register has effect. */ 1322 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0) 1323 /* @brief Has TPM_POL. */ 1324 #define FSL_FEATURE_TPM_HAS_POL (1) 1325 /* @brief Whether POL register has effect. */ 1326 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1327 /* @brief Has TPM_FILTER register. */ 1328 #define FSL_FEATURE_TPM_HAS_FILTER (0) 1329 /* @brief Whether FILTER register has effect. */ 1330 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0) 1331 /* @brief Has TPM_QDCTRL register. */ 1332 #define FSL_FEATURE_TPM_HAS_QDCTRL (0) 1333 /* @brief Whether QDCTRL register has effect. */ 1334 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0) 1335 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1336 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1337 /* @brief Whether 32 bits counter has effect. */ 1338 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1339 1340 /* UART module features */ 1341 1342 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1343 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 1344 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1345 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1346 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1347 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 1348 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1349 #define FSL_FEATURE_UART_HAS_FIFO (0) 1350 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1351 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) 1352 /* @brief Infrared (modulation) is supported. */ 1353 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1354 /* @brief 2 bits long stop bit is available. */ 1355 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1356 /* @brief If 10-bit mode is supported. */ 1357 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1358 /* @brief Baud rate fine adjustment is available. */ 1359 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1360 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1361 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1362 /* @brief Baud rate oversampling is available. */ 1363 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1364 /* @brief Baud rate oversampling is available. */ 1365 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1366 /* @brief Peripheral type. */ 1367 #define FSL_FEATURE_UART_IS_SCI (0) 1368 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1369 #define FSL_FEATURE_UART_FIFO_SIZEn(x) (0) 1370 /* @brief Supports two match addresses to filter incoming frames. */ 1371 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1372 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1373 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1374 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1375 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1376 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1377 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1378 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1379 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1380 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1381 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1382 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1383 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1384 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1385 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1386 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1387 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) 1388 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1389 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) 1390 /* @brief Has separate DMA RX and TX requests. */ 1391 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1392 1393 /* USB module features */ 1394 1395 /* @brief KHCI module instance count */ 1396 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1397 /* @brief HOST mode enabled */ 1398 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) 1399 /* @brief OTG mode enabled */ 1400 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) 1401 /* @brief Size of the USB dedicated RAM */ 1402 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1403 /* @brief Has KEEP_ALIVE_CTRL register */ 1404 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1405 /* @brief Has the Dynamic SOF threshold compare support */ 1406 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 1407 /* @brief Has the VBUS detect support */ 1408 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 1409 /* @brief Has the IRC48M module clock support */ 1410 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 1411 /* @brief Number of endpoints supported */ 1412 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1413 /* @brief Has STALL_IL/OL_DIS registers */ 1414 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1415 /* @brief Has STALL_IH/OH_DIS registers */ 1416 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1417 1418 /* VREF module features */ 1419 1420 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1421 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1422 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1423 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1424 /* @brief If high/low buffer mode supported */ 1425 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1426 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1427 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1428 /* @brief Has VREF_TRM4. */ 1429 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1430 1431 #endif /* _MCXC243_FEATURES_H_ */ 1432 1433
