1 /* 2 ** ################################################################### 3 ** Version: rev. 1.9, 2016-06-08 4 ** Build: b240516 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2014-05-12) 18 ** Initial version. 19 ** - rev. 1.1 (2014-07-10) 20 ** UART0 - UART0 module renamed to UART2. 21 ** - rev. 1.2 (2014-08-12) 22 ** CRC - CRC register renamed to DATA. 23 ** - rev. 1.3 (2014-09-02) 24 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. 25 ** USB - USB0_CTL1 was renamed to USB0_CTL register. 26 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. 27 ** - rev. 1.4 (2014-09-22) 28 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. 29 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. 30 ** SIM - Removed bitfield DIEID in SDID register. 31 ** UART2 - Removed ED register. 32 ** UART2 - Removed MODEM register. 33 ** UART2 - Removed IR register. 34 ** UART2 - Removed PFIFO register. 35 ** UART2 - Removed CFIFO register. 36 ** UART2 - Removed SFIFO register. 37 ** UART2 - Removed TWFIFO register. 38 ** UART2 - Removed TCFIFO register. 39 ** UART2 - Removed RWFIFO register. 40 ** UART2 - Removed RCFIFO register. 41 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. 42 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. 43 ** - rev. 1.5 (2015-01-21) 44 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 45 ** - rev. 1.6 (2015-05-19) 46 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 47 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 48 ** Added features for PORT. 49 ** - rev. 1.7 (2015-05-25) 50 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 51 ** - rev. 1.8 (2015-05-27) 52 ** Several USB features added. 53 ** - rev. 1.9 (2016-06-08) 54 ** Corrected FSL_FEATURE_GPIO_HAS_FAST_GPIO to (1). 55 ** 56 ** ################################################################### 57 */ 58 59 #ifndef _MCXC141_FEATURES_H_ 60 #define _MCXC141_FEATURES_H_ 61 62 /* SOC module features */ 63 64 /* @brief ADC16 availability on the SoC. */ 65 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 66 /* @brief CMP availability on the SoC. */ 67 #define FSL_FEATURE_SOC_CMP_COUNT (1) 68 /* @brief CRC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_CRC_COUNT (1) 70 /* @brief DMA availability on the SoC. */ 71 #define FSL_FEATURE_SOC_DMA_COUNT (1) 72 /* @brief DMAMUX availability on the SoC. */ 73 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 74 /* @brief FGPIO availability on the SoC. */ 75 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 76 /* @brief FLEXIO availability on the SoC. */ 77 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 78 /* @brief FTFA availability on the SoC. */ 79 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 80 /* @brief GPIO availability on the SoC. */ 81 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 82 /* @brief I2C availability on the SoC. */ 83 #define FSL_FEATURE_SOC_I2C_COUNT (2) 84 /* @brief LLWU availability on the SoC. */ 85 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 86 /* @brief LPTMR availability on the SoC. */ 87 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 88 /* @brief LPUART availability on the SoC. */ 89 #define FSL_FEATURE_SOC_LPUART_COUNT (2) 90 /* @brief MCGLITE availability on the SoC. */ 91 #define FSL_FEATURE_SOC_MCGLITE_COUNT (1) 92 /* @brief MCM availability on the SoC. */ 93 #define FSL_FEATURE_SOC_MCM_COUNT (1) 94 /* @brief MTB availability on the SoC. */ 95 #define FSL_FEATURE_SOC_MTB_COUNT (1) 96 /* @brief MTBDWT availability on the SoC. */ 97 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 98 /* @brief OSC availability on the SoC. */ 99 #define FSL_FEATURE_SOC_OSC_COUNT (1) 100 /* @brief PIT availability on the SoC. */ 101 #define FSL_FEATURE_SOC_PIT_COUNT (1) 102 /* @brief PMC availability on the SoC. */ 103 #define FSL_FEATURE_SOC_PMC_COUNT (1) 104 /* @brief PORT availability on the SoC. */ 105 #define FSL_FEATURE_SOC_PORT_COUNT (5) 106 /* @brief RCM availability on the SoC. */ 107 #define FSL_FEATURE_SOC_RCM_COUNT (1) 108 /* @brief RFSYS availability on the SoC. */ 109 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 110 /* @brief ROM availability on the SoC. */ 111 #define FSL_FEATURE_SOC_ROM_COUNT (1) 112 /* @brief RTC availability on the SoC. */ 113 #define FSL_FEATURE_SOC_RTC_COUNT (1) 114 /* @brief SIM availability on the SoC. */ 115 #define FSL_FEATURE_SOC_SIM_COUNT (1) 116 /* @brief SMC availability on the SoC. */ 117 #define FSL_FEATURE_SOC_SMC_COUNT (1) 118 /* @brief SPI availability on the SoC. */ 119 #define FSL_FEATURE_SOC_SPI_COUNT (2) 120 /* @brief TPM availability on the SoC. */ 121 #define FSL_FEATURE_SOC_TPM_COUNT (3) 122 /* @brief UART availability on the SoC. */ 123 #define FSL_FEATURE_SOC_UART_COUNT (1) 124 /* @brief VREF availability on the SoC. */ 125 #define FSL_FEATURE_SOC_VREF_COUNT (1) 126 127 /* ADC16 module features */ 128 129 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 130 #define FSL_FEATURE_ADC16_HAS_PGA (0) 131 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 132 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 133 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 134 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 135 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 136 #define FSL_FEATURE_ADC16_HAS_DMA (1) 137 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 138 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 139 /* @brief Has FIFO (bit SC4[AFDEP]). */ 140 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 141 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 142 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 143 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 144 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 145 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 146 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 147 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 148 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 149 /* @brief Has HW averaging (bit SC3[AVGE]). */ 150 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 151 /* @brief Has offset correction (register OFS). */ 152 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 153 /* @brief Maximum ADC resolution. */ 154 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 155 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 156 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 157 158 /* CMP module features */ 159 160 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 161 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 162 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 163 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) 164 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 165 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) 166 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 167 #define FSL_FEATURE_CMP_HAS_DMA (1) 168 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 169 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 170 /* @brief Has DAC Test function in CMP (register DACTEST). */ 171 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 172 173 /* COP module features */ 174 175 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ 176 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) 177 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ 178 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) 179 /* @brief Has more clock sources like MCGIRC */ 180 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) 181 /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ 182 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) 183 184 /* CRC module features */ 185 186 /* @brief Has data register with name CRC */ 187 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 188 189 /* DMA module features */ 190 191 /* @brief Number of DMA channels. */ 192 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) 193 /* @brief Total number of DMA channels on all modules. */ 194 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (4) 195 196 /* DMAMUX module features */ 197 198 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 199 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 200 /* @brief Total number of DMA channels on all modules. */ 201 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 202 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 203 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 204 /* @brief Register CHCFGn width. */ 205 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 206 207 /* FGPIO module features */ 208 209 /* No feature definitions */ 210 211 /* FLEXIO module features */ 212 213 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 214 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 215 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 216 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0) 217 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 218 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) 219 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 220 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) 221 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 222 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) 223 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 224 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) 225 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 226 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) 227 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 228 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) 229 /* @brief Reset value of the FLEXIO_VERID register */ 230 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000) 231 /* @brief Reset value of the FLEXIO_PARAM register */ 232 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404) 233 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 234 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) 235 /* @brief Flexio DMA request base channel */ 236 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 237 238 /* FLASH module features */ 239 240 /* @brief Is of type FTFA. */ 241 #define FSL_FEATURE_FLASH_IS_FTFA (1) 242 /* @brief Is of type FTFE. */ 243 #define FSL_FEATURE_FLASH_IS_FTFE (0) 244 /* @brief Is of type FTFL. */ 245 #define FSL_FEATURE_FLASH_IS_FTFL (0) 246 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 247 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 248 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 249 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 250 /* @brief Has EEPROM region protection (register FEPROT). */ 251 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 252 /* @brief Has data flash region protection (register FDPROT). */ 253 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 254 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 255 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 256 /* @brief Has flash cache control in FMC module. */ 257 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 258 /* @brief Has flash cache control in MCM module. */ 259 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 260 /* @brief Has flash cache control in MSCM module. */ 261 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 262 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 263 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 264 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 265 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 266 /* @brief P-Flash start address. */ 267 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 268 /* @brief P-Flash block count. */ 269 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 270 /* @brief P-Flash block size. */ 271 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 272 /* @brief P-Flash sector size. */ 273 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 274 /* @brief P-Flash write unit size. */ 275 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 276 /* @brief P-Flash data path width. */ 277 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 278 /* @brief P-Flash block swap feature. */ 279 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 280 /* @brief P-Flash protection region count. */ 281 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 282 /* @brief Has FlexNVM memory. */ 283 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 284 /* @brief Has FlexNVM alias. */ 285 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 286 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 287 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 288 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 289 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 290 /* @brief FlexNVM block count. */ 291 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 292 /* @brief FlexNVM block size. */ 293 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 294 /* @brief FlexNVM sector size. */ 295 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 296 /* @brief FlexNVM write unit size. */ 297 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 298 /* @brief FlexNVM data path width. */ 299 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 300 /* @brief Has FlexRAM memory. */ 301 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 302 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 303 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 304 /* @brief FlexRAM size. */ 305 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 306 /* @brief Has 0x00 Read 1s Block command. */ 307 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 308 /* @brief Has 0x01 Read 1s Section command. */ 309 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 310 /* @brief Has 0x02 Program Check command. */ 311 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 312 /* @brief Has 0x03 Read Resource command. */ 313 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 314 /* @brief Has 0x06 Program Longword command. */ 315 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 316 /* @brief Has 0x07 Program Phrase command. */ 317 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 318 /* @brief Has 0x08 Erase Flash Block command. */ 319 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 320 /* @brief Has 0x09 Erase Flash Sector command. */ 321 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 322 /* @brief Has 0x0B Program Section command. */ 323 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 324 /* @brief Has 0x40 Read 1s All Blocks command. */ 325 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 326 /* @brief Has 0x41 Read Once command. */ 327 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 328 /* @brief Has 0x43 Program Once command. */ 329 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 330 /* @brief Has 0x44 Erase All Blocks command. */ 331 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 332 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 333 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 334 /* @brief Has 0x46 Swap Control command. */ 335 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 336 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 337 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 338 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 339 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 340 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 341 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 342 /* @brief Has 0x80 Program Partition command. */ 343 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 344 /* @brief Has 0x81 Set FlexRAM Function command. */ 345 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 346 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 347 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 348 /* @brief P-Flash Erase sector command address alignment. */ 349 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 350 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 351 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 352 /* @brief P-Flash Read resource command address alignment. */ 353 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 354 /* @brief P-Flash Program check command address alignment. */ 355 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 356 /* @brief P-Flash Program check command address alignment. */ 357 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 358 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 359 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 360 /* @brief FlexNVM Erase sector command address alignment. */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 362 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 364 /* @brief FlexNVM Read resource command address alignment. */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 366 /* @brief FlexNVM Program check command address alignment. */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 368 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 370 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 372 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 374 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 376 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 378 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 380 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 382 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 384 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 386 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 388 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 390 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 392 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 394 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 396 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 398 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 400 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 402 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 404 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 406 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 408 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 410 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 412 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 414 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 416 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 418 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 420 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 422 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 424 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 426 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 428 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 429 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 430 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 431 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 432 433 /* GPIO module features */ 434 435 /* @brief Has GPIO attribute checker register (GACR). */ 436 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 437 438 /* I2C module features */ 439 440 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 441 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 442 /* @brief Maximum supported baud rate in kilobit per second. */ 443 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 444 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 445 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 446 /* @brief Has DMA support (register bit C1[DMAEN]). */ 447 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 448 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 449 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 450 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 451 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 452 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 453 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 454 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 455 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 456 /* @brief Has control of the drive capability of the I2C pins. */ 457 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 458 /* @brief Has double buffering support (register S2). */ 459 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 460 /* @brief Has double buffer enable. */ 461 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 462 463 /* LLWU module features */ 464 465 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 466 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 467 /* @brief Has pins 8-15 connected to LLWU device. */ 468 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 469 /* @brief Maximum number of internal modules connected to LLWU device. */ 470 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 471 /* @brief Number of digital filters. */ 472 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 473 /* @brief Has MF register. */ 474 #define FSL_FEATURE_LLWU_HAS_MF (0) 475 /* @brief Has PF register. */ 476 #define FSL_FEATURE_LLWU_HAS_PF (0) 477 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 478 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 479 /* @brief Has no internal module wakeup flag register. */ 480 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 481 /* @brief Has external pin 0 connected to LLWU device. */ 482 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 483 /* @brief Index of port of external pin. */ 484 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 485 /* @brief Number of external pin port on specified port. */ 486 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 487 /* @brief Has external pin 1 connected to LLWU device. */ 488 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 489 /* @brief Index of port of external pin. */ 490 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 491 /* @brief Number of external pin port on specified port. */ 492 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 493 /* @brief Has external pin 2 connected to LLWU device. */ 494 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 495 /* @brief Index of port of external pin. */ 496 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 497 /* @brief Number of external pin port on specified port. */ 498 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 499 /* @brief Has external pin 3 connected to LLWU device. */ 500 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) 501 /* @brief Index of port of external pin. */ 502 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) 503 /* @brief Number of external pin port on specified port. */ 504 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) 505 /* @brief Has external pin 4 connected to LLWU device. */ 506 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 507 /* @brief Index of port of external pin. */ 508 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 509 /* @brief Number of external pin port on specified port. */ 510 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 511 /* @brief Has external pin 5 connected to LLWU device. */ 512 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 513 /* @brief Index of port of external pin. */ 514 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 515 /* @brief Number of external pin port on specified port. */ 516 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 517 /* @brief Has external pin 6 connected to LLWU device. */ 518 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 519 /* @brief Index of port of external pin. */ 520 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 521 /* @brief Number of external pin port on specified port. */ 522 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 523 /* @brief Has external pin 7 connected to LLWU device. */ 524 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 525 /* @brief Index of port of external pin. */ 526 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 527 /* @brief Number of external pin port on specified port. */ 528 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 529 /* @brief Has external pin 8 connected to LLWU device. */ 530 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 531 /* @brief Index of port of external pin. */ 532 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 533 /* @brief Number of external pin port on specified port. */ 534 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 535 /* @brief Has external pin 9 connected to LLWU device. */ 536 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 537 /* @brief Index of port of external pin. */ 538 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 539 /* @brief Number of external pin port on specified port. */ 540 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 541 /* @brief Has external pin 10 connected to LLWU device. */ 542 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 543 /* @brief Index of port of external pin. */ 544 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 545 /* @brief Number of external pin port on specified port. */ 546 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 547 /* @brief Has external pin 11 connected to LLWU device. */ 548 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 549 /* @brief Index of port of external pin. */ 550 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 551 /* @brief Number of external pin port on specified port. */ 552 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 553 /* @brief Has external pin 12 connected to LLWU device. */ 554 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 555 /* @brief Index of port of external pin. */ 556 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 557 /* @brief Number of external pin port on specified port. */ 558 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 559 /* @brief Has external pin 13 connected to LLWU device. */ 560 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 561 /* @brief Index of port of external pin. */ 562 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 563 /* @brief Number of external pin port on specified port. */ 564 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 565 /* @brief Has external pin 14 connected to LLWU device. */ 566 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 567 /* @brief Index of port of external pin. */ 568 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 569 /* @brief Number of external pin port on specified port. */ 570 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 571 /* @brief Has external pin 15 connected to LLWU device. */ 572 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 573 /* @brief Index of port of external pin. */ 574 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 575 /* @brief Number of external pin port on specified port. */ 576 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 577 /* @brief Has external pin 16 connected to LLWU device. */ 578 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 579 /* @brief Index of port of external pin. */ 580 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 581 /* @brief Number of external pin port on specified port. */ 582 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 583 /* @brief Has external pin 17 connected to LLWU device. */ 584 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 585 /* @brief Index of port of external pin. */ 586 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 587 /* @brief Number of external pin port on specified port. */ 588 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 589 /* @brief Has external pin 18 connected to LLWU device. */ 590 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 591 /* @brief Index of port of external pin. */ 592 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 593 /* @brief Number of external pin port on specified port. */ 594 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 595 /* @brief Has external pin 19 connected to LLWU device. */ 596 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 597 /* @brief Index of port of external pin. */ 598 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 599 /* @brief Number of external pin port on specified port. */ 600 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 601 /* @brief Has external pin 20 connected to LLWU device. */ 602 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 603 /* @brief Index of port of external pin. */ 604 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 605 /* @brief Number of external pin port on specified port. */ 606 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 607 /* @brief Has external pin 21 connected to LLWU device. */ 608 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 609 /* @brief Index of port of external pin. */ 610 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 611 /* @brief Number of external pin port on specified port. */ 612 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 613 /* @brief Has external pin 22 connected to LLWU device. */ 614 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 615 /* @brief Index of port of external pin. */ 616 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 617 /* @brief Number of external pin port on specified port. */ 618 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 619 /* @brief Has external pin 23 connected to LLWU device. */ 620 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 621 /* @brief Index of port of external pin. */ 622 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 623 /* @brief Number of external pin port on specified port. */ 624 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 625 /* @brief Has external pin 24 connected to LLWU device. */ 626 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 627 /* @brief Index of port of external pin. */ 628 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 629 /* @brief Number of external pin port on specified port. */ 630 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 631 /* @brief Has external pin 25 connected to LLWU device. */ 632 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 633 /* @brief Index of port of external pin. */ 634 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 635 /* @brief Number of external pin port on specified port. */ 636 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 637 /* @brief Has external pin 26 connected to LLWU device. */ 638 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 639 /* @brief Index of port of external pin. */ 640 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 641 /* @brief Number of external pin port on specified port. */ 642 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 643 /* @brief Has external pin 27 connected to LLWU device. */ 644 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 645 /* @brief Index of port of external pin. */ 646 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 647 /* @brief Number of external pin port on specified port. */ 648 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 649 /* @brief Has external pin 28 connected to LLWU device. */ 650 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 651 /* @brief Index of port of external pin. */ 652 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 653 /* @brief Number of external pin port on specified port. */ 654 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 655 /* @brief Has external pin 29 connected to LLWU device. */ 656 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 657 /* @brief Index of port of external pin. */ 658 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 659 /* @brief Number of external pin port on specified port. */ 660 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 661 /* @brief Has external pin 30 connected to LLWU device. */ 662 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 663 /* @brief Index of port of external pin. */ 664 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 665 /* @brief Number of external pin port on specified port. */ 666 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 667 /* @brief Has external pin 31 connected to LLWU device. */ 668 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 669 /* @brief Index of port of external pin. */ 670 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 671 /* @brief Number of external pin port on specified port. */ 672 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 673 /* @brief Has internal module 0 connected to LLWU device. */ 674 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 675 /* @brief Has internal module 1 connected to LLWU device. */ 676 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 677 /* @brief Has internal module 2 connected to LLWU device. */ 678 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 679 /* @brief Has internal module 3 connected to LLWU device. */ 680 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 681 /* @brief Has internal module 4 connected to LLWU device. */ 682 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 683 /* @brief Has internal module 5 connected to LLWU device. */ 684 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 685 /* @brief Has internal module 6 connected to LLWU device. */ 686 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 687 /* @brief Has internal module 7 connected to LLWU device. */ 688 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 689 /* @brief Has Version ID Register (LLWU_VERID). */ 690 #define FSL_FEATURE_LLWU_HAS_VERID (0) 691 /* @brief Has Parameter Register (LLWU_PARAM). */ 692 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 693 /* @brief Width of registers of the LLWU. */ 694 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 695 /* @brief Has DMA Enable register (LLWU_DE). */ 696 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 697 698 /* LPTMR module features */ 699 700 /* @brief Has shared interrupt handler with another LPTMR module. */ 701 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 702 /* @brief Whether LPTMR counter is 32 bits width. */ 703 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 704 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 705 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 706 707 /* LPUART module features */ 708 709 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 710 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 711 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 712 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 713 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 714 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 715 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 716 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 717 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 718 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 719 /* @brief Has 32-bit register MODIR */ 720 #define FSL_FEATURE_LPUART_HAS_MODIR (0) 721 /* @brief Hardware flow control (RTS, CTS) is supported. */ 722 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) 723 /* @brief Infrared (modulation) is supported. */ 724 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) 725 /* @brief 2 bits long stop bit is available. */ 726 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 727 /* @brief If 10-bit mode is supported. */ 728 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 729 /* @brief If 7-bit mode is supported. */ 730 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 731 /* @brief Baud rate fine adjustment is available. */ 732 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 733 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 734 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 735 /* @brief Baud rate oversampling is available. */ 736 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 737 /* @brief Baud rate oversampling is available. */ 738 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 739 /* @brief Peripheral type. */ 740 #define FSL_FEATURE_LPUART_IS_SCI (1) 741 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 742 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 743 /* @brief Supports two match addresses to filter incoming frames. */ 744 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 745 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 746 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 747 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 748 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 749 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 750 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 751 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 752 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 753 /* @brief Has improved smart card (ISO7816 protocol) support. */ 754 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 755 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 756 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 757 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 758 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 759 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 760 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 761 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 762 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 763 /* @brief Has separate DMA RX and TX requests. */ 764 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 765 /* @brief Has separate RX and TX interrupts. */ 766 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 767 /* @brief Has LPAURT_PARAM. */ 768 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 769 /* @brief Has LPUART_VERID. */ 770 #define FSL_FEATURE_LPUART_HAS_VERID (0) 771 /* @brief Has LPUART_GLOBAL. */ 772 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 773 /* @brief Has LPUART_PINCFG. */ 774 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 775 776 /* MCGLITE module features */ 777 778 /* @brief Defines that clock generator is MCG Lite. */ 779 #define FSL_FEATURE_MCGLITE_MCGLITE (1) 780 /* @brief Has Crystal Oscillator Operation Mode Selection. */ 781 #define FSL_FEATURE_MCGLITE_HAS_HGO0 (1) 782 /* @brief Has HCTRIM register available. */ 783 #define FSL_FEATURE_MCGLITE_HAS_HCTRIM (0) 784 /* @brief Has HTTRIM register available. */ 785 #define FSL_FEATURE_MCGLITE_HAS_HTTRIM (0) 786 /* @brief Has HFTRIM register available. */ 787 #define FSL_FEATURE_MCGLITE_HAS_HFTRIM (0) 788 /* @brief Has LTRIMRNG register available. */ 789 #define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (0) 790 /* @brief Has LFTRIM register available. */ 791 #define FSL_FEATURE_MCGLITE_HAS_LFTRIM (0) 792 /* @brief Has LSTRIM register available. */ 793 #define FSL_FEATURE_MCGLITE_HAS_LSTRIM (0) 794 /* @brief Has External Clock Source Frequency Range Selection. */ 795 #define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1) 796 797 /* interrupt module features */ 798 799 /* @brief Lowest interrupt request number. */ 800 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 801 /* @brief Highest interrupt request number. */ 802 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 803 804 /* OSC module features */ 805 806 /* @brief Has OSC1 external oscillator. */ 807 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 808 /* @brief Has OSC0 external oscillator. */ 809 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 810 /* @brief Has OSC external oscillator (without index). */ 811 #define FSL_FEATURE_OSC_HAS_OSC (0) 812 /* @brief Number of OSC external oscillators. */ 813 #define FSL_FEATURE_OSC_OSC_COUNT (1) 814 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 815 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 816 817 /* PIT module features */ 818 819 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 820 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 821 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 822 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 823 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 824 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 825 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 826 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 827 /* @brief Has timer enable control. */ 828 #define FSL_FEATURE_PIT_HAS_MDIS (1) 829 /* @brief Has ERRATA 7914. */ 830 #define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0) 831 832 /* PMC module features */ 833 834 /* @brief Has Bandgap Enable In VLPx Operation support. */ 835 #define FSL_FEATURE_PMC_HAS_BGEN (1) 836 /* @brief Has Bandgap Buffer Enable. */ 837 #define FSL_FEATURE_PMC_HAS_BGBE (1) 838 /* @brief Has Bandgap Buffer Drive Select. */ 839 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 840 /* @brief Has Low-Voltage Detect Voltage Select support. */ 841 #define FSL_FEATURE_PMC_HAS_LVDV (1) 842 /* @brief Has Low-Voltage Warning Voltage Select support. */ 843 #define FSL_FEATURE_PMC_HAS_LVWV (1) 844 /* @brief Has LPO. */ 845 #define FSL_FEATURE_PMC_HAS_LPO (0) 846 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 847 #define FSL_FEATURE_PMC_HAS_VLPO (1) 848 /* @brief Has acknowledge isolation support. */ 849 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 850 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 851 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 852 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 853 #define FSL_FEATURE_PMC_HAS_REGONS (1) 854 /* @brief Has PMC_HVDSC1. */ 855 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 856 /* @brief Has PMC_PARAM. */ 857 #define FSL_FEATURE_PMC_HAS_PARAM (0) 858 /* @brief Has PMC_VERID. */ 859 #define FSL_FEATURE_PMC_HAS_VERID (0) 860 861 /* PORT module features */ 862 863 /* @brief Has control lock (register bit PCR[LK]). */ 864 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 865 /* @brief Has open drain control (register bit PCR[ODE]). */ 866 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 867 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 868 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 869 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 870 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 871 /* @brief Has pull resistor selection available. */ 872 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 873 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 874 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 875 /* @brief Has slew rate control (register bit PCR[SRE]). */ 876 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 877 /* @brief Has passive filter (register bit field PCR[PFE]). */ 878 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 879 /* @brief Has drive strength control (register bit PCR[DSE]). */ 880 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 881 /* @brief Has separate drive strength register (HDRVE). */ 882 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 883 /* @brief Has glitch filter (register IOFLT). */ 884 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 885 /* @brief Defines width of PCR[MUX] field. */ 886 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 887 /* @brief Has dedicated interrupt vector. */ 888 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 889 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 890 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 891 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 892 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 893 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 894 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 895 896 /* RCM module features */ 897 898 /* @brief Has Loss-of-Lock Reset support. */ 899 #define FSL_FEATURE_RCM_HAS_LOL (0) 900 /* @brief Has Loss-of-Clock Reset support. */ 901 #define FSL_FEATURE_RCM_HAS_LOC (0) 902 /* @brief Has JTAG generated Reset support. */ 903 #define FSL_FEATURE_RCM_HAS_JTAG (0) 904 /* @brief Has EzPort generated Reset support. */ 905 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 906 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 907 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 908 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 909 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 910 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 911 #define FSL_FEATURE_RCM_HAS_SSRS (1) 912 /* @brief Has Version ID Register (RCM_VERID). */ 913 #define FSL_FEATURE_RCM_HAS_VERID (0) 914 /* @brief Has Parameter Register (RCM_PARAM). */ 915 #define FSL_FEATURE_RCM_HAS_PARAM (0) 916 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 917 #define FSL_FEATURE_RCM_HAS_SRIE (0) 918 /* @brief Width of registers of the RCM. */ 919 #define FSL_FEATURE_RCM_REG_WIDTH (8) 920 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 921 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 922 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 923 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 924 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 925 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 926 927 /* RTC module features */ 928 929 /* @brief Has wakeup pin. */ 930 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 931 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 932 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 933 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 934 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 935 /* @brief Has read/write access control (registers WAR and RAR). */ 936 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 937 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 938 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 939 /* @brief Has RTC_CLKIN available. */ 940 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 941 /* @brief Has prescaler adjust for LPO. */ 942 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 943 /* @brief Has Clock Pin Enable field. */ 944 #define FSL_FEATURE_RTC_HAS_CPE (0) 945 /* @brief Has Timer Seconds Interrupt Configuration field. */ 946 #define FSL_FEATURE_RTC_HAS_TSIC (0) 947 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 948 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 949 /* @brief Has Tamper Interrupt Register (register TIR). */ 950 #define FSL_FEATURE_RTC_HAS_TIR (0) 951 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 952 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 953 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 954 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 955 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 956 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 957 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 958 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 959 /* @brief Has Tamper Detect Register (register TDR). */ 960 #define FSL_FEATURE_RTC_HAS_TDR (0) 961 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 962 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 963 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 964 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 965 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 966 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 967 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 968 #define FSL_FEATURE_RTC_HAS_TTSR (0) 969 /* @brief Has Pin Configuration Register (register PCR). */ 970 #define FSL_FEATURE_RTC_HAS_PCR (0) 971 972 /* SIM module features */ 973 974 /* @brief Has USB FS divider. */ 975 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 976 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 977 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 978 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 979 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 980 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 981 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) 982 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 983 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 984 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 985 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 986 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 987 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 988 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 989 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 990 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 991 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 992 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 993 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 994 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 995 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 996 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 997 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 998 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 999 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1000 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1001 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 1002 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1003 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2) 1004 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1005 #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) 1006 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1007 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1008 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1009 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1010 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1011 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) 1012 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1013 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) 1014 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1015 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) 1016 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1017 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1018 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1019 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1020 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1021 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1022 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1023 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) 1024 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1025 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) 1026 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1027 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1028 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1029 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1030 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1031 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1032 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1033 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1034 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1035 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1036 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1037 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1038 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1039 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1040 /* @brief Has FTM module(s) configuration. */ 1041 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1042 /* @brief Number of FTM modules. */ 1043 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1044 /* @brief Number of FTM triggers with selectable source. */ 1045 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1046 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1047 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1048 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1049 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1050 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1051 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1052 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1053 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1054 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1055 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1056 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1057 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1058 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1059 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1060 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1061 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1062 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1063 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1064 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1065 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1066 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1067 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1068 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1069 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1070 /* @brief Has TPM module(s) configuration. */ 1071 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1072 /* @brief The highest TPM module index. */ 1073 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1074 /* @brief Has TPM module with index 0. */ 1075 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) 1076 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1077 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) 1078 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1079 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) 1080 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1081 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1082 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1083 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) 1084 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1085 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) 1086 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1087 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) 1088 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1089 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) 1090 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1091 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1092 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1093 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1094 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1095 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1096 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1097 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1098 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1099 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1100 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1101 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1102 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1103 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1104 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1105 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1106 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1107 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1108 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1109 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1110 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1111 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1112 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1113 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1114 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1115 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) 1116 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1117 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) 1118 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1119 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) 1120 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1121 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1122 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1123 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1124 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1125 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1126 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1127 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1128 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1129 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1130 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1131 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1132 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1133 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1134 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1135 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1136 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1137 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1138 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1139 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1140 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1141 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1142 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1143 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1144 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1145 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1146 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1147 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1148 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1149 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1150 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1151 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1152 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1153 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1154 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1155 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1156 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1157 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1158 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1159 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1160 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1161 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) 1162 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1163 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1164 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1165 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1166 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1167 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1168 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1169 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1170 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1171 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1172 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1173 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1174 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1175 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1176 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1177 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1178 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1179 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1180 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1181 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1182 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1183 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1184 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1185 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1186 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1187 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1188 /* @brief Has miscellanious control register (register MCR). */ 1189 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1190 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1191 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) 1192 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1193 #define FSL_FEATURE_SIM_HAS_COP_STOP (1) 1194 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1195 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1196 /* @brief Has UIDH registers. */ 1197 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1198 /* @brief Has UIDM registers. */ 1199 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1200 1201 /* SMC module features */ 1202 1203 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1204 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1205 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1206 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1207 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1208 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1209 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1210 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1211 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1212 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1213 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1214 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1215 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1216 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1217 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1218 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1219 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1220 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1221 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1222 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1223 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1224 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1225 /* @brief Has stop submode. */ 1226 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1227 /* @brief Has stop submode 0(VLLS0). */ 1228 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1229 /* @brief Has stop submode 1(VLLS1). */ 1230 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1231 /* @brief Has stop submode 2(VLLS2). */ 1232 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1233 /* @brief Has SMC_PARAM. */ 1234 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1235 /* @brief Has SMC_VERID. */ 1236 #define FSL_FEATURE_SMC_HAS_VERID (0) 1237 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1238 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1239 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1240 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1241 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1242 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1243 /* @brief Width of SMC registers. */ 1244 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1245 1246 /* SPI module features */ 1247 1248 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1249 #define FSL_FEATURE_SPI_HAS_FIFO (1) 1250 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 1251 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 1252 /* @brief Has separate DMA RX and TX requests. */ 1253 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1254 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 1255 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ 1256 (((x) == SPI0) ? (0) : \ 1257 (((x) == SPI1) ? (4) : (-1))) 1258 /* @brief Maximum transfer data width in bits. */ 1259 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) 1260 /* @brief The data register name has postfix (L as low and H as high). */ 1261 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) 1262 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1263 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1264 /* @brief Has 16-bit data transfer support. */ 1265 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) 1266 1267 /* SysTick module features */ 1268 1269 /* @brief Systick has external reference clock. */ 1270 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1271 /* @brief Systick external reference clock is core clock divided by this value. */ 1272 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1273 1274 /* TPM module features */ 1275 1276 /* @brief Bus clock is the source clock for the module. */ 1277 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1278 /* @brief Number of channels. */ 1279 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1280 (((x) == TPM0) ? (6) : \ 1281 (((x) == TPM1) ? (2) : \ 1282 (((x) == TPM2) ? (2) : (-1)))) 1283 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1284 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1285 /* @brief Has TPM_PARAM. */ 1286 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1287 /* @brief Has TPM_VERID. */ 1288 #define FSL_FEATURE_TPM_HAS_VERID (0) 1289 /* @brief Has TPM_GLOBAL. */ 1290 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1291 /* @brief Has TPM_TRIG. */ 1292 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1293 /* @brief Whether TRIG register has effect. */ 1294 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ 1295 (((x) == TPM0) ? (1) : \ 1296 (((x) == TPM1) ? (0) : \ 1297 (((x) == TPM2) ? (0) : (-1)))) 1298 /* @brief Has counter pause on trigger. */ 1299 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1300 /* @brief Has external trigger selection. */ 1301 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1302 /* @brief Has TPM_COMBINE register. */ 1303 #define FSL_FEATURE_TPM_HAS_COMBINE (0) 1304 /* @brief Whether COMBINE register has effect. */ 1305 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0) 1306 /* @brief Has TPM_POL. */ 1307 #define FSL_FEATURE_TPM_HAS_POL (1) 1308 /* @brief Whether POL register has effect. */ 1309 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1310 /* @brief Has TPM_FILTER register. */ 1311 #define FSL_FEATURE_TPM_HAS_FILTER (0) 1312 /* @brief Whether FILTER register has effect. */ 1313 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0) 1314 /* @brief Has TPM_QDCTRL register. */ 1315 #define FSL_FEATURE_TPM_HAS_QDCTRL (0) 1316 /* @brief Whether QDCTRL register has effect. */ 1317 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0) 1318 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1319 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1320 /* @brief Whether 32 bits counter has effect. */ 1321 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1322 1323 /* UART module features */ 1324 1325 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1326 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 1327 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1328 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1329 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1330 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 1331 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1332 #define FSL_FEATURE_UART_HAS_FIFO (0) 1333 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1334 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) 1335 /* @brief Infrared (modulation) is supported. */ 1336 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1337 /* @brief 2 bits long stop bit is available. */ 1338 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) 1339 /* @brief If 10-bit mode is supported. */ 1340 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1341 /* @brief Baud rate fine adjustment is available. */ 1342 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1343 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1344 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1345 /* @brief Baud rate oversampling is available. */ 1346 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1347 /* @brief Baud rate oversampling is available. */ 1348 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1349 /* @brief Peripheral type. */ 1350 #define FSL_FEATURE_UART_IS_SCI (0) 1351 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1352 #define FSL_FEATURE_UART_FIFO_SIZEn(x) (0) 1353 /* @brief Supports two match addresses to filter incoming frames. */ 1354 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1355 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1356 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1357 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1358 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1359 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1360 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1361 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1362 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1363 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1364 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1365 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1366 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1367 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1368 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1369 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1370 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) 1371 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1372 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) 1373 /* @brief Has separate DMA RX and TX requests. */ 1374 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1375 1376 /* VREF module features */ 1377 1378 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1379 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1380 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1381 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1382 /* @brief If high/low buffer mode supported */ 1383 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1384 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1385 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1386 /* @brief Has VREF_TRM4. */ 1387 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1388 1389 #endif /* _MCXC141_FEATURES_H_ */ 1390 1391
