1 /*
2 * Copyright 2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kINPUTMUX0_RST_SHIFT_RSTn = (0U | (0U)), /*!< INPUTMUX0 reset control */
40 kI3C0_RST_SHIFT_RSTn = (0U | (1U)), /*!< I3C0 reset control */
41 kCTIMER0_RST_SHIFT_RSTn = (0U | (2U)), /*!< CTIMER0 reset control */
42 kCTIMER1_RST_SHIFT_RSTn = (0U | (3U)), /*!< CTIMER1 reset control */
43 kCTIMER2_RST_SHIFT_RSTn = (0U | (4U)), /*!< CTIMER2 reset control */
44 kFREQME_RST_SHIFT_RSTn = (0U | (5U)), /*!< FREQME reset control */
45 kUTICK0_RST_SHIFT_RSTn = (0U | (6U)), /*!< UTICK0 reset control */
46 kDMA_RST_SHIFT_RSTn = (0U | (8U)), /*!< DMA reset control */
47 kAOI0_RST_SHIFT_RSTn = (0U | (9U)), /*!< AOI0 reset control */
48 kCRC_RST_SHIFT_RSTn = (0U | (10U)), /*!< CRC reset control */
49 kEIM_RST_SHIFT_RSTn = (0U | (11U)), /*!< EIM reset control */
50 kERM_RST_SHIFT_RSTn = (0U | (12U)), /*!< ERM reset control */
51 kLPI2C0_RST_SHIFT_RSTn = (0U | (16U)), /*!< LPI2C0 reset control */
52 kLPSPI0_RST_SHIFT_RSTn = (0U | (17U)), /*!< LPSPI0 reset control */
53 kLPSPI1_RST_SHIFT_RSTn = (0U | (18U)), /*!< LPSPI1 reset control */
54 kLPUART0_RST_SHIFT_RSTn = (0U | (19U)), /*!< LPUART0 reset control */
55 kLPUART1_RST_SHIFT_RSTn = (0U | (20U)), /*!< LPUART1 reset control */
56 kLPUART2_RST_SHIFT_RSTn = (0U | (21U)), /*!< LPUART2 reset control */
57 kUSB0_RST_SHIFT_RSTn = (0U | (22U)), /*!< USB0 reset control */
58 kQDC0_RST_SHIFT_RSTn = (0U | (23U)), /*!< QDC0 reset control */
59 kFLEXPWM0_RST_SHIFT_RSTn = (0U | (24U)), /*!< FLEXPWM0 reset control */
60 kOSTIMER0_RST_SHIFT_RSTn = (0U | (25U)), /*!< OSTIMER0 reset control */
61 kADC0_RST_SHIFT_RSTn = (0U | (26U)), /*!< ADC0 reset control */
62 kCMP1_RST_SHIFT_RSTn = (0U | (28U)), /*!< CMP1 reset control */
63 kPORT0_RST_SHIFT_RSTn = (0U | (29U)), /*!< PORT0 reset control */
64 kPORT1_RST_SHIFT_RSTn = (0U | (30U)), /*!< PORT1 reset control */
65 kPORT2_RST_SHIFT_RSTn = (0U | (31U)), /*!< PORT2 reset control */
66 kPORT3_RST_SHIFT_RSTn = ((1U << 8U) | (0U)), /*!< PORT3 reset control */
67 kATX0_RST_SHIFT_RSTn = ((1U << 8U) | (1U)), /*!< ATX0 reset control */
68 kGPIO0_RST_SHIFT_RSTn = ((1U << 8U) | (5U)), /*!< GPIO0 reset control */
69 kGPIO1_RST_SHIFT_RSTn = ((1U << 8U) | (6U)), /*!< GPIO1 reset control */
70 kGPIO2_RST_SHIFT_RSTn = ((1U << 8U) | (7U)), /*!< GPIO2 reset control */
71 kGPIO3_RST_SHIFT_RSTn = ((1U << 8U) | (8U)), /*!< GPIO3 reset control */
72 NotAvail_RSTn = (0xFFFFU), /*!< No reset control */
73 } SYSCON_RSTn_t;
74
75 /** Array initializers with peripheral reset bits **/
76 #define AOI_RSTS \
77 { \
78 kAOI0_RST_SHIFT_RSTn \
79 } /* Reset bits for ADC peripheral */
80 #define ADC_RSTS \
81 { \
82 kADC0_RST_SHIFT_RSTn \
83 } /* Reset bits for ADC peripheral */
84 #define CRC_RSTS \
85 { \
86 kCRC_RST_SHIFT_RSTn \
87 } /* Reset bits for CRC peripheral */
88 #define CTIMER_RSTS \
89 { \
90 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn \
91 } /* Reset bits for CTIMER peripheral */
92 #define DMA_RSTS_N \
93 { \
94 kDMA_RST_SHIFT_RSTn \
95 } /* Reset bits for DMA peripheral */
96 #define FLEXPWM_RSTS_N \
97 { \
98 kFLEXPWM0_RST_SHIFT_RSTn \
99 } /* Reset bits for FLEXPWM peripheral */
100 #define FREQME_RSTS_N \
101 { \
102 kFREQME_RST_SHIFT_RSTn \
103 } /* Reset bits for FREQME peripheral */
104 #define GPIO_RSTS_N \
105 { \
106 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn \
107 } /* Reset bits for GPIO peripheral */
108 #define I3C_RSTS \
109 { \
110 kI3C0_RST_SHIFT_RSTn \
111 } /* Reset bits for I3C peripheral */
112 #define INPUTMUX_RSTS \
113 { \
114 kINPUTMUX0_RST_SHIFT_RSTn \
115 } /* Reset bits for INPUTMUX peripheral */
116 #define LPUART_RSTS \
117 { \
118 kLPUART0_RST_SHIFT_RSTn, kLPUART1_RST_SHIFT_RSTn, kLPUART2_RST_SHIFT_RSTn \
119 } /* Reset bits for LPUART peripheral */
120 #define LPSPI_RSTS \
121 { \
122 kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \
123 } /* Reset bits for LPSPI peripheral */
124 #define LPI2C_RSTS \
125 { \
126 kLPI2C0_RST_SHIFT_RSTn \
127 } /* Reset bits for LPI2C peripheral */
128 #define LPCMP_RSTS \
129 { \
130 NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn \
131 } /* Reset bits for LPCMP peripheral */
132 #define OSTIMER_RSTS \
133 { \
134 kOSTIMER0_RST_SHIFT_RSTn \
135 } /* Reset bits for OSTIMER peripheral */
136 #define PORT_RSTS_N \
137 { \
138 kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn \
139 } /* Reset bits for PORT peripheral */
140 #define EQDC_RSTS \
141 { \
142 kQDC0_RST_SHIFT_RSTn \
143 } /* Reset bits for EQDC peripheral */
144 #define UTICK_RSTS \
145 { \
146 kUTICK0_RST_SHIFT_RSTn \
147 } /* Reset bits for UTICK peripheral */
148
149 typedef SYSCON_RSTn_t reset_ip_name_t;
150
151 /*******************************************************************************
152 * API
153 ******************************************************************************/
154 #if defined(__cplusplus)
155 extern "C" {
156 #endif
157
158 /*!
159 * @brief Assert reset to peripheral.
160 *
161 * Asserts reset signal to specified peripheral module.
162 *
163 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
164 * and reset bit position in the reset register.
165 */
166 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
167
168 /*!
169 * @brief Clear reset to peripheral.
170 *
171 * Clears reset signal to specified peripheral module, allows it to operate.
172 *
173 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
174 * and reset bit position in the reset register.
175 */
176 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
177
178 /*!
179 * @brief Reset peripheral module.
180 *
181 * Reset peripheral module.
182 *
183 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
184 * and reset bit position in the reset register.
185 */
186 void RESET_PeripheralReset(reset_ip_name_t peripheral);
187
188 /*!
189 * @brief Release peripheral module.
190 *
191 * Release peripheral module.
192 *
193 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
194 * and reset bit position in the reset register.
195 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)196 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
197 {
198 RESET_SetPeripheralReset(peripheral);
199 }
200
201 #if defined(__cplusplus)
202 }
203 #endif
204
205 /*! @} */
206
207 #endif /* _FSL_RESET_H_ */
208
