1 /*
2 * Copyright 2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kINPUTMUX0_RST_SHIFT_RSTn = (0U | (0U)), /*!< INPUTMUX0 reset control */
40 kI3C0_RST_SHIFT_RSTn = (0U | (1U)), /*!< I3C0 reset control */
41 kCTIMER0_RST_SHIFT_RSTn = (0U | (2U)), /*!< CTIMER0 reset control */
42 kCTIMER1_RST_SHIFT_RSTn = (0U | (3U)), /*!< CTIMER1 reset control */
43 kCTIMER2_RST_SHIFT_RSTn = (0U | (4U)), /*!< CTIMER2 reset control */
44 kCTIMER3_RST_SHIFT_RSTn = (0U | (5U)), /*!< CTIMER3 reset control */
45 kCTIMER4_RST_SHIFT_RSTn = (0U | (6U)), /*!< CTIMER4 reset control */
46 kFREQME_RST_SHIFT_RSTn = (0U | (7U)), /*!< FREQME reset control */
47 kUTICK0_RST_SHIFT_RSTn = (0U | (8U)), /*!< UTICK0 reset control */
48 kDMA_RST_SHIFT_RSTn = (0U | (10U)), /*!< DMA reset control */
49 kAOI0_RST_SHIFT_RSTn = (0U | (11U)), /*!< AOI0 reset control */
50 kCRC0_RST_SHIFT_RSTn = (0U | (12U)), /*!< CRC0 reset control */
51 kEIM0_RST_SHIFT_RSTn = (0U | (13U)), /*!< EIM0 reset control */
52 kERM0_RST_SHIFT_RSTn = (0U | (14U)), /*!< ERM0 reset control */
53 kAOI1_RST_SHIFT_RSTn = (0U | (16U)), /*!< AOI1 reset control */
54 kFLEXIO0_RST_SHIFT_RSTn = (0U | (17U)), /*!< FLEXIO0 reset control */
55 kLPI2C0_RST_SHIFT_RSTn = (0U | (18U)), /*!< LPI2C0 reset control */
56 kLPI2C1_RST_SHIFT_RSTn = (0U | (19U)), /*!< LPI2C1 reset control */
57 kLPSPI0_RST_SHIFT_RSTn = (0U | (20U)), /*!< LPSPI0 reset control */
58 kLPSPI1_RST_SHIFT_RSTn = (0U | (21U)), /*!< LPSPI1 reset control */
59 kLPUART0_RST_SHIFT_RSTn = (0U | (22U)), /*!< LPUART0 reset control */
60 kLPUART1_RST_SHIFT_RSTn = (0U | (23U)), /*!< LPUART1 reset control */
61 kLPUART2_RST_SHIFT_RSTn = (0U | (24U)), /*!< LPUART2 reset control */
62 kLPUART3_RST_SHIFT_RSTn = (0U | (25U)), /*!< LPUART3 reset control */
63 kLPUART4_RST_SHIFT_RSTn = (0U | (26U)), /*!< LPUART4 reset control */
64 kUSB0_RST_SHIFT_RSTn = (0U | (27U)), /*!< USB0 reset control */
65 kQDC0_RST_SHIFT_RSTn = (0U | (28U)), /*!< QDC0 reset control */
66 kQDC1_RST_SHIFT_RSTn = (0U | (29U)), /*!< QDC1 reset control */
67 kFLEXPWM0_RST_SHIFT_RSTn = (0U | (30U)), /*!< FLEXPWM0 reset control */
68 kFLEXPWM1_RST_SHIFT_RSTn = (0U | (31U)), /*!< FLEXPWM1 reset control */
69 kOSTIMER0_RST_SHIFT_RSTn = ((1U << 8U) | (0U)), /*!< OSTIMER0 reset control */
70 kADC0_RST_SHIFT_RSTn = ((1U << 8U) | (1U)), /*!< ADC0 reset control */
71 kADC1_RST_SHIFT_RSTn = ((1U << 8U) | (2U)), /*!< ADC1 reset control */
72 kCMP1_RST_SHIFT_RSTn = ((1U << 8U) | (4U)), /*!< CMP1 reset control */
73 kDAC0_RST_SHIFT_RSTn = ((1U << 8U) | (5U)), /*!< DAC0 reset control */
74 kOPAMP0_RST_SHIFT_RSTn = ((1U << 8U) | (6U)), /*!< OPAMP0 reset control */
75 kPORT0_RST_SHIFT_RSTn = ((1U << 8U) | (7U)), /*!< PORT0 reset control */
76 kPORT1_RST_SHIFT_RSTn = ((1U << 8U) | (8U)), /*!< PORT1 reset control */
77 kPORT2_RST_SHIFT_RSTn = ((1U << 8U) | (9U)), /*!< PORT2 reset control */
78 kPORT3_RST_SHIFT_RSTn = ((1U << 8U) | (10U)), /*!< PORT3 reset control */
79 kPORT4_RST_SHIFT_RSTn = ((1U << 8U) | (11U)), /*!< PORT4 reset control */
80 kFLEXCAN0_RST_SHIFT_RSTn = ((1U << 8U) | (12U)), /*!< FLEXCAN0 reset control */
81 kLPI2C2_RST_SHIFT_RSTn = ((1U << 8U) | (13U)), /*!< LPI2C2 reset control */
82 kLPI2C3_RST_SHIFT_RSTn = ((1U << 8U) | (14U)), /*!< LPI2C3 reset control */
83 kGPIO0_RST_SHIFT_RSTn = ((1U << 8U) | (20U)), /*!< GPIO0 reset control */
84 kGPIO1_RST_SHIFT_RSTn = ((1U << 8U) | (21U)), /*!< GPIO1 reset control */
85 kGPIO2_RST_SHIFT_RSTn = ((1U << 8U) | (22U)), /*!< GPIO2 reset control */
86 kGPIO3_RST_SHIFT_RSTn = ((1U << 8U) | (23U)), /*!< GPIO3 reset control */
87 kGPIO4_RST_SHIFT_RSTn = ((1U << 8U) | (24U)), /*!< GPIO4 reset control */
88 NotAvail_RSTn = (0xFFFFU), /*!< No reset control */
89 } SYSCON_RSTn_t;
90
91 /** Array initializers with peripheral reset bits **/
92 #define AOI_RSTS \
93 { \
94 kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \
95 } /* Reset bits for ADC peripheral */
96 #define ADC_RSTS \
97 { \
98 kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
99 } /* Reset bits for ADC peripheral */
100 #define CRC_RSTS \
101 { \
102 kCRC0_RST_SHIFT_RSTn \
103 } /* Reset bits for CRC peripheral */
104 #define CTIMER_RSTS \
105 { \
106 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
107 kCTIMER4_RST_SHIFT_RSTn \
108 } /* Reset bits for CTIMER peripheral */
109 #define DAC_RSTS_N \
110 { \
111 kDAC0_RST_SHIFT_RSTn \
112 } /* Reset bits for DAC peripheral */
113 #define DMA_RSTS_N \
114 { \
115 kDMA_RST_SHIFT_RSTn \
116 } /* Reset bits for DMA peripheral */
117 #define EIM_RSTS_N \
118 { \
119 kEIM0_RST_SHIFT_RSTn \
120 } /* Reset bits for EIM peripheral */
121 #define ERM_RSTS_N \
122 { \
123 kERM0_RST_SHIFT_RSTn \
124 } /* Reset bits for ERM peripheral */
125 #define FLEXCAN_RSTS_N \
126 { \
127 kFLEXCAN0_RST_SHIFT_RSTn \
128 } /* Reset bits for FLEXCAN peripheral */
129 #define FLEXIO_RSTS_N \
130 { \
131 kFLEXIO0_RST_SHIFT_RSTn \
132 } /* Reset bits for FLEXIO peripheral */
133 #define FLEXPWM_RSTS_N \
134 { \
135 kFLEXPWM0_RST_SHIFT_RSTn, kFLEXPWM1_RST_SHIFT_RSTn \
136 } /* Reset bits for FLEXPWM peripheral */
137 #define FREQME_RSTS_N \
138 { \
139 kFREQME_RST_SHIFT_RSTn \
140 } /* Reset bits for FREQME peripheral */
141 #define GPIO_RSTS_N \
142 { \
143 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
144 kGPIO4_RST_SHIFT_RSTn \
145 } /* Reset bits for GPIO peripheral */
146 #define I3C_RSTS \
147 { \
148 kI3C0_RST_SHIFT_RSTn \
149 } /* Reset bits for I3C peripheral */
150 #define INPUTMUX_RSTS \
151 { \
152 kINPUTMUX0_RST_SHIFT_RSTn \
153 } /* Reset bits for INPUTMUX peripheral */
154 #define LPUART_RSTS \
155 { \
156 kLPUART0_RST_SHIFT_RSTn, kLPUART1_RST_SHIFT_RSTn, kLPUART2_RST_SHIFT_RSTn, kLPUART3_RST_SHIFT_RSTn, \
157 kLPUART4_RST_SHIFT_RSTn \
158 } /* Reset bits for LPUART peripheral */
159 #define LPSPI_RSTS \
160 { \
161 kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \
162 } /* Reset bits for LPSPI peripheral */
163 #define LPI2C_RSTS \
164 { \
165 kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn, kLPI2C2_RST_SHIFT_RSTn, kLPI2C3_RST_SHIFT_RSTn \
166 } /* Reset bits for LPI2C peripheral */
167 #define LPCMP_RSTS \
168 { \
169 NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn \
170 } /* Reset bits for LPCMP peripheral */
171 #define OPAMP_RSTS \
172 { \
173 kOPAMP0_RST_SHIFT_RSTn \
174 } /* Reset bits for OPAMP peripheral */
175 #define OSTIMER_RSTS \
176 { \
177 kOSTIMER0_RST_SHIFT_RSTn \
178 } /* Reset bits for OSTIMER peripheral */
179 #define PORT_RSTS_N \
180 { \
181 kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn, \
182 kPORT4_RST_SHIFT_RSTn \
183 } /* Reset bits for PORT peripheral */
184 #define EQDC_RSTS \
185 { \
186 kQDC0_RST_SHIFT_RSTn, kQDC1_RST_SHIFT_RSTn \
187 } /* Reset bits for EQDC peripheral */
188 #define UTICK_RSTS \
189 { \
190 kUTICK0_RST_SHIFT_RSTn \
191 } /* Reset bits for UTICK peripheral */
192
193 typedef SYSCON_RSTn_t reset_ip_name_t;
194
195 /*******************************************************************************
196 * API
197 ******************************************************************************/
198 #if defined(__cplusplus)
199 extern "C" {
200 #endif
201
202 /*!
203 * @brief Assert reset to peripheral.
204 *
205 * Asserts reset signal to specified peripheral module.
206 *
207 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
208 * and reset bit position in the reset register.
209 */
210 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
211
212 /*!
213 * @brief Clear reset to peripheral.
214 *
215 * Clears reset signal to specified peripheral module, allows it to operate.
216 *
217 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
218 * and reset bit position in the reset register.
219 */
220 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
221
222 /*!
223 * @brief Reset peripheral module.
224 *
225 * Reset peripheral module.
226 *
227 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
228 * and reset bit position in the reset register.
229 */
230 void RESET_PeripheralReset(reset_ip_name_t peripheral);
231
232 /*!
233 * @brief Release peripheral module.
234 *
235 * Release peripheral module.
236 *
237 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
238 * and reset bit position in the reset register.
239 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)240 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
241 {
242 RESET_SetPeripheralReset(peripheral);
243 }
244
245 #if defined(__cplusplus)
246 }
247 #endif
248
249 /*! @} */
250
251 #endif /* _FSL_RESET_H_ */
252
