1 /* 2 ** ################################################################### 3 ** Version: rev. 7.0, 2018-11-05 4 ** Build: b240229 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2016-04-13) 18 ** Initial version. 19 ** - rev. 2.0 (2016-07-19) 20 ** RevC Header ER 21 ** - rev. 3.0 (2017-02-28) 22 ** RevD Header ER 23 ** - rev. 4.0 (2017-05-02) 24 ** RevE Header ER 25 ** - rev. 5.0 (2017-12-22) 26 ** RevA(B0) Header GA 27 ** - rev. 6.0 (2018-02-01) 28 ** RevB(B0) Header GA 29 ** - rev. 7.0 (2018-11-05) 30 ** RevA(B1) Header 31 ** 32 ** ################################################################### 33 */ 34 35 #ifndef _MCIMX7U5_cm4_FEATURES_H_ 36 #define _MCIMX7U5_cm4_FEATURES_H_ 37 38 /* SOC module features */ 39 40 /* @brief ACMP availability on the SoC. */ 41 #define FSL_FEATURE_SOC_ACMP_COUNT (2) 42 /* @brief AXBS availability on the SoC. */ 43 #define FSL_FEATURE_SOC_AXBS_COUNT (2) 44 /* @brief CRC availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CRC_COUNT (1) 46 /* @brief DAC12 availability on the SoC. */ 47 #define FSL_FEATURE_SOC_DAC12_COUNT (2) 48 /* @brief DMAMUX availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMAMUX_COUNT (2) 50 /* @brief EDMA availability on the SoC. */ 51 #define FSL_FEATURE_SOC_EDMA_COUNT (2) 52 /* @brief EWM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_EWM_COUNT (1) 54 /* @brief FB availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FB_COUNT (1) 56 /* @brief FGPIO availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FGPIO_COUNT (2) 58 /* @brief FLEXIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) 60 /* @brief GPIO availability on the SoC. */ 61 #define FSL_FEATURE_SOC_GPIO_COUNT (6) 62 /* @brief I2S availability on the SoC. */ 63 #define FSL_FEATURE_SOC_I2S_COUNT (2) 64 /* @brief LCDIF availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LCDIF_COUNT (1) 66 /* @brief LLWU availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 68 /* @brief LMEM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 70 /* @brief LPADC availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPADC_COUNT (2) 72 /* @brief LPI2C availability on the SoC. */ 73 #define FSL_FEATURE_SOC_LPI2C_COUNT (8) 74 /* @brief LPIT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_LPIT_COUNT (2) 76 /* @brief LPSPI availability on the SoC. */ 77 #define FSL_FEATURE_SOC_LPSPI_COUNT (4) 78 /* @brief LPTMR availability on the SoC. */ 79 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 80 /* @brief LPUART availability on the SoC. */ 81 #define FSL_FEATURE_SOC_LPUART_COUNT (8) 82 /* @brief LTC availability on the SoC. */ 83 #define FSL_FEATURE_SOC_LTC_COUNT (1) 84 /* @brief MCM availability on the SoC. */ 85 #define FSL_FEATURE_SOC_MCM_COUNT (1) 86 /* @brief MIPI_DSI_HOST availability on the SoC. */ 87 #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) 88 /* @brief MMCAU availability on the SoC. */ 89 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 90 /* @brief MMDC availability on the SoC. */ 91 #define FSL_FEATURE_SOC_MMDC_COUNT (1) 92 /* @brief MU availability on the SoC. */ 93 #define FSL_FEATURE_SOC_MU_COUNT (1) 94 /* @brief OCOTP availability on the SoC. */ 95 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 96 /* @brief OTFAD availability on the SoC. */ 97 #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 98 /* @brief PCC availability on the SoC. */ 99 #define FSL_FEATURE_SOC_PCC_COUNT (4) 100 /* @brief PMC availability on the SoC. */ 101 #define FSL_FEATURE_SOC_PMC_COUNT (2) 102 /* @brief PORT availability on the SoC. */ 103 #define FSL_FEATURE_SOC_PORT_COUNT (6) 104 /* @brief QuadSPI availability on the SoC. */ 105 #define FSL_FEATURE_SOC_QuadSPI_COUNT (1) 106 /* @brief ROMC availability on the SoC. */ 107 #define FSL_FEATURE_SOC_ROMC_COUNT (2) 108 /* @brief SCG availability on the SoC. */ 109 #define FSL_FEATURE_SOC_SCG_COUNT (2) 110 /* @brief SEMA42 availability on the SoC. */ 111 #define FSL_FEATURE_SOC_SEMA42_COUNT (2) 112 /* @brief SIM availability on the SoC. */ 113 #define FSL_FEATURE_SOC_SIM_COUNT (1) 114 /* @brief SMC availability on the SoC. */ 115 #define FSL_FEATURE_SOC_SMC_COUNT (2) 116 /* @brief SNVS availability on the SoC. */ 117 #define FSL_FEATURE_SOC_SNVS_COUNT (1) 118 /* @brief TPM availability on the SoC. */ 119 #define FSL_FEATURE_SOC_TPM_COUNT (8) 120 /* @brief TRGMUX availability on the SoC. */ 121 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) 122 /* @brief TRNG availability on the SoC. */ 123 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 124 /* @brief TSTMR availability on the SoC. */ 125 #define FSL_FEATURE_SOC_TSTMR_COUNT (2) 126 /* @brief USBHS availability on the SoC. */ 127 #define FSL_FEATURE_SOC_USBHS_COUNT (2) 128 /* @brief USBHSDCD availability on the SoC. */ 129 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 130 /* @brief USBNC availability on the SoC. */ 131 #define FSL_FEATURE_SOC_USBNC_COUNT (2) 132 /* @brief USBPHY availability on the SoC. */ 133 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 134 /* @brief USDHC availability on the SoC. */ 135 #define FSL_FEATURE_SOC_USDHC_COUNT (2) 136 /* @brief VIU availability on the SoC. */ 137 #define FSL_FEATURE_SOC_VIU_COUNT (1) 138 /* @brief WDOG availability on the SoC. */ 139 #define FSL_FEATURE_SOC_WDOG_COUNT (3) 140 /* @brief XRDC availability on the SoC. */ 141 #define FSL_FEATURE_SOC_XRDC_COUNT (1) 142 143 /* LPADC module features */ 144 145 /* @brief FIFO availability on the SoC. */ 146 #define FSL_FEATURE_LPADC_FIFO_COUNT (1) 147 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 148 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 149 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 150 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) 151 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 152 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) 153 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 154 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) 155 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 156 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) 157 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 158 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 159 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 160 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0) 161 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 162 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) 163 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 164 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) 165 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 166 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) 167 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 168 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 169 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 170 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 171 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 172 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 173 /* @brief Has offset trim (register OFSTRIM). */ 174 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) 175 /* @brief Has Trigger status register. */ 176 #define FSL_FEATURE_LPADC_HAS_TSTAT (0) 177 /* @brief Has power select (bitfield CFG[PWRSEL]). */ 178 #define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) 179 /* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ 180 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) 181 /* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ 182 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) 183 /* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ 184 #define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) 185 /* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ 186 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) 187 /* @brief Conversion averaged bitfiled width. */ 188 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) 189 /* @brief Has B side channels. */ 190 #define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) 191 /* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ 192 #define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (0) 193 /* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ 194 #define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (0) 195 /* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ 196 #define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (0) 197 /* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ 198 #define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) 199 /* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ 200 #define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (0) 201 /* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ 202 #define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (0) 203 /* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ 204 #define FSL_FEATURE_LPADC_HAS_CFG_TRES (0) 205 /* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ 206 #define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (0) 207 /* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ 208 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (0) 209 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ 210 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (1) 211 212 /* ACMP module features */ 213 214 /* @brief Has CMP_C3. */ 215 #define FSL_FEATURE_ACMP_HAS_C3_REG (1) 216 /* @brief Has C0 LINKEN Bit */ 217 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) 218 /* @brief Has C0 OFFSET Bit */ 219 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) 220 /* @brief Has C0 HYSTCTR Bit */ 221 #define FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT (1) 222 /* @brief Has C1 INPSEL Bit */ 223 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) 224 /* @brief Has C1 INNSEL Bit */ 225 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) 226 /* @brief Has C1 DACOE Bit */ 227 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1) 228 /* @brief Has C1 DMODE Bit */ 229 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) 230 /* @brief Has C2 RRE Bit */ 231 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) 232 233 /* CRC module features */ 234 235 /* @brief Has data register with name CRC */ 236 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 237 238 /* DAC12 module features */ 239 240 /* @brief Has no ITRM register. */ 241 #define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (0) 242 /* @brief Has hardware trigger. */ 243 #define FSL_FEATURE_DAC12_HAS_HW_TRIGGER (1) 244 245 /* EDMA module features */ 246 247 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 248 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 249 /* @brief Total number of DMA channels on all modules. */ 250 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 251 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 252 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 253 /* @brief Has DMA_Error interrupt vector. */ 254 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 255 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 256 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 257 /* @brief Channel IRQ entry shared offset. */ 258 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) 259 /* @brief If 8 bytes transfer supported. */ 260 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 261 /* @brief If 16 bytes transfer supported. */ 262 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) 263 /* @brief If 32 bytes transfer supported. */ 264 #define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1) 265 266 /* DMAMUX module features */ 267 268 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 269 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 270 /* @brief Total number of DMA channels on all modules. */ 271 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (64) 272 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 273 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 274 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ 275 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) 276 /* @brief Register CHCFGn width. */ 277 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) 278 279 /* EWM module features */ 280 281 /* @brief Has clock select (register CLKCTRL). */ 282 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 283 /* @brief Has clock prescaler (register CLKPRESCALER). */ 284 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 285 286 /* FLEXIO module features */ 287 288 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 289 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 290 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 291 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 292 /* @brief Has pin input output related registers */ 293 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) 294 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 295 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 296 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 297 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 298 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 299 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 300 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 301 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 302 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 303 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 304 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 305 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 306 /* @brief Reset value of the FLEXIO_VERID register */ 307 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 308 /* @brief Reset value of the FLEXIO_PARAM register */ 309 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) 310 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 311 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) 312 313 /* GPIO module features */ 314 315 /* @brief Has GPIO attribute checker register (GACR). */ 316 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 317 /* @brief Has GPIO version ID register (VERID). */ 318 #define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (0) 319 /* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ 320 #define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) 321 /* @brief Has GPIO port input disable register (PIDR). */ 322 #define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (0) 323 /* @brief Has GPIO interrupt/DMA request/trigger output selection. */ 324 #define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) 325 326 /* SAI module features */ 327 328 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 329 #define FSL_FEATURE_SAI_HAS_FIFO (1) 330 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 331 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (16) 332 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 333 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ 334 (((x) == I2S0) ? (2) : \ 335 (((x) == I2S1) ? (4) : (-1))) 336 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 337 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 338 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 339 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 340 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 341 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 342 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 343 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 344 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 345 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 346 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 347 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 348 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 349 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 350 /* @brief Interrupt source number */ 351 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 352 /* @brief Has register of MCR. */ 353 #define FSL_FEATURE_SAI_HAS_MCR (0) 354 /* @brief Has bit field MICS of the MCR register. */ 355 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 356 /* @brief Has register of MDR */ 357 #define FSL_FEATURE_SAI_HAS_MDR (0) 358 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 359 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) 360 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 361 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 362 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 363 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 364 /* @brief Support synchronous with another SAI. */ 365 #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) 366 367 /* LLWU module features */ 368 369 /* @brief Maximum number of pins connected to LLWU device. */ 370 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 371 /* @brief Maximum number of internal modules connected to LLWU device. */ 372 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 373 /* @brief Number of digital filters. */ 374 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 375 /* @brief Has MF register. */ 376 #define FSL_FEATURE_LLWU_HAS_MF (1) 377 /* @brief Has PF register. */ 378 #define FSL_FEATURE_LLWU_HAS_PF (1) 379 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 380 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 381 /* @brief Has no internal module wakeup flag register. */ 382 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 383 /* @brief Has external pin 0 connected to LLWU device. */ 384 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 385 /* @brief Index of port of external pin. */ 386 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX) 387 /* @brief Number of external pin port on specified port. */ 388 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 389 /* @brief Has external pin 1 connected to LLWU device. */ 390 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 391 /* @brief Index of port of external pin. */ 392 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX) 393 /* @brief Number of external pin port on specified port. */ 394 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (3) 395 /* @brief Has external pin 2 connected to LLWU device. */ 396 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 397 /* @brief Index of port of external pin. */ 398 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX) 399 /* @brief Number of external pin port on specified port. */ 400 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (13) 401 /* @brief Has external pin 3 connected to LLWU device. */ 402 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 403 /* @brief Index of port of external pin. */ 404 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 405 /* @brief Number of external pin port on specified port. */ 406 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (14) 407 /* @brief Has external pin 4 connected to LLWU device. */ 408 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 409 /* @brief Index of port of external pin. */ 410 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 411 /* @brief Number of external pin port on specified port. */ 412 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (18) 413 /* @brief Has external pin 5 connected to LLWU device. */ 414 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 415 /* @brief Index of port of external pin. */ 416 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) 417 /* @brief Number of external pin port on specified port. */ 418 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (19) 419 /* @brief Has external pin 6 connected to LLWU device. */ 420 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 421 /* @brief Index of port of external pin. */ 422 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) 423 /* @brief Number of external pin port on specified port. */ 424 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (23) 425 /* @brief Has external pin 7 connected to LLWU device. */ 426 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 427 /* @brief Index of port of external pin. */ 428 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) 429 /* @brief Number of external pin port on specified port. */ 430 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (31) 431 /* @brief Has external pin 8 connected to LLWU device. */ 432 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 433 /* @brief Index of port of external pin. */ 434 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) 435 /* @brief Number of external pin port on specified port. */ 436 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (1) 437 /* @brief Has external pin 9 connected to LLWU device. */ 438 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 439 /* @brief Index of port of external pin. */ 440 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX) 441 /* @brief Number of external pin port on specified port. */ 442 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (3) 443 /* @brief Has external pin 10 connected to LLWU device. */ 444 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 445 /* @brief Index of port of external pin. */ 446 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX) 447 /* @brief Number of external pin port on specified port. */ 448 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 449 /* @brief Has external pin 11 connected to LLWU device. */ 450 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 451 /* @brief Index of port of external pin. */ 452 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX) 453 /* @brief Number of external pin port on specified port. */ 454 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (7) 455 /* @brief Has external pin 12 connected to LLWU device. */ 456 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 457 /* @brief Index of port of external pin. */ 458 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX) 459 /* @brief Number of external pin port on specified port. */ 460 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (9) 461 /* @brief Has external pin 13 connected to LLWU device. */ 462 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 463 /* @brief Index of port of external pin. */ 464 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX) 465 /* @brief Number of external pin port on specified port. */ 466 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (14) 467 /* @brief Has external pin 14 connected to LLWU device. */ 468 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 469 /* @brief Index of port of external pin. */ 470 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX) 471 /* @brief Number of external pin port on specified port. */ 472 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (16) 473 /* @brief Has external pin 15 connected to LLWU device. */ 474 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 475 /* @brief Index of port of external pin. */ 476 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOB_IDX) 477 /* @brief Number of external pin port on specified port. */ 478 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (19) 479 /* @brief Has external pin 16 connected to LLWU device. */ 480 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 481 /* @brief Index of port of external pin. */ 482 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 483 /* @brief Number of external pin port on specified port. */ 484 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 485 /* @brief Has external pin 17 connected to LLWU device. */ 486 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 487 /* @brief Index of port of external pin. */ 488 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 489 /* @brief Number of external pin port on specified port. */ 490 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 491 /* @brief Has external pin 18 connected to LLWU device. */ 492 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 493 /* @brief Index of port of external pin. */ 494 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 495 /* @brief Number of external pin port on specified port. */ 496 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 497 /* @brief Has external pin 19 connected to LLWU device. */ 498 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 499 /* @brief Index of port of external pin. */ 500 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 501 /* @brief Number of external pin port on specified port. */ 502 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 503 /* @brief Has external pin 20 connected to LLWU device. */ 504 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 505 /* @brief Index of port of external pin. */ 506 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 507 /* @brief Number of external pin port on specified port. */ 508 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 509 /* @brief Has external pin 21 connected to LLWU device. */ 510 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 511 /* @brief Index of port of external pin. */ 512 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 513 /* @brief Number of external pin port on specified port. */ 514 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 515 /* @brief Has external pin 22 connected to LLWU device. */ 516 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 517 /* @brief Index of port of external pin. */ 518 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 519 /* @brief Number of external pin port on specified port. */ 520 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 521 /* @brief Has external pin 23 connected to LLWU device. */ 522 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 523 /* @brief Index of port of external pin. */ 524 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 525 /* @brief Number of external pin port on specified port. */ 526 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 527 /* @brief Has external pin 24 connected to LLWU device. */ 528 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 529 /* @brief Index of port of external pin. */ 530 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 531 /* @brief Number of external pin port on specified port. */ 532 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 533 /* @brief Has external pin 25 connected to LLWU device. */ 534 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 535 /* @brief Index of port of external pin. */ 536 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 537 /* @brief Number of external pin port on specified port. */ 538 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 539 /* @brief Has external pin 26 connected to LLWU device. */ 540 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 541 /* @brief Index of port of external pin. */ 542 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 543 /* @brief Number of external pin port on specified port. */ 544 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 545 /* @brief Has external pin 27 connected to LLWU device. */ 546 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 547 /* @brief Index of port of external pin. */ 548 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 549 /* @brief Number of external pin port on specified port. */ 550 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 551 /* @brief Has external pin 28 connected to LLWU device. */ 552 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 553 /* @brief Index of port of external pin. */ 554 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 555 /* @brief Number of external pin port on specified port. */ 556 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 557 /* @brief Has external pin 29 connected to LLWU device. */ 558 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 559 /* @brief Index of port of external pin. */ 560 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 561 /* @brief Number of external pin port on specified port. */ 562 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 563 /* @brief Has external pin 30 connected to LLWU device. */ 564 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 565 /* @brief Index of port of external pin. */ 566 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 567 /* @brief Number of external pin port on specified port. */ 568 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 569 /* @brief Has external pin 31 connected to LLWU device. */ 570 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 571 /* @brief Index of port of external pin. */ 572 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 573 /* @brief Number of external pin port on specified port. */ 574 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 575 /* @brief Has internal module 0 connected to LLWU device. */ 576 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 577 /* @brief Has internal module 1 connected to LLWU device. */ 578 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 579 /* @brief Has internal module 2 connected to LLWU device. */ 580 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 581 /* @brief Has internal module 3 connected to LLWU device. */ 582 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 583 /* @brief Has internal module 4 connected to LLWU device. */ 584 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 585 /* @brief Has internal module 5 connected to LLWU device. */ 586 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 587 /* @brief Has internal module 6 connected to LLWU device. */ 588 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1) 589 /* @brief Has internal module 7 connected to LLWU device. */ 590 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 591 /* @brief Has LLWU_VERID. */ 592 #define FSL_FEATURE_LLWU_HAS_VERID (1) 593 /* @brief Has LLWU_PARAM. */ 594 #define FSL_FEATURE_LLWU_HAS_PARAM (1) 595 /* @brief LLWU register bit width. */ 596 #define FSL_FEATURE_LLWU_REG_BITWIDTH (32) 597 /* @brief Has DMA Enable register LLWU_DE. */ 598 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 599 600 /* LMEM module features */ 601 602 /* @brief Has process identifier support. */ 603 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) 604 /* @brief Support instruction cache demote. */ 605 #define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1) 606 /* @brief Has no NONCACHEABLE section. */ 607 #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (1) 608 /* @brief L1 ICACHE line size in byte. */ 609 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 610 /* @brief L1 DCACHE line size in byte. */ 611 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 612 613 /* LPI2C module features */ 614 615 /* @brief Has separate DMA RX and TX requests. */ 616 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 617 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 618 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 619 620 /* LPIT module features */ 621 622 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 623 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 624 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 625 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 626 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 627 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 628 629 /* LPSPI module features */ 630 631 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 632 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) \ 633 (((x) == LPSPI0) ? (4) : \ 634 (((x) == LPSPI1) ? (4) : \ 635 (((x) == LPSPI2) ? (16) : \ 636 (((x) == LPSPI3) ? (16) : (-1))))) 637 /* @brief Has separate DMA RX and TX requests. */ 638 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 639 /* @brief Has CCR1 (related to existence of registers CCR1). */ 640 #define FSL_FEATURE_LPSPI_HAS_CCR1 (0) 641 /* @brief Has no PCSCFG bit in CFGR1 register */ 642 #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) 643 /* @brief Has no WIDTH bits in TCR register */ 644 #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) 645 646 /* LPTMR module features */ 647 648 /* @brief Has shared interrupt handler with another LPTMR module. */ 649 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 650 /* @brief Whether LPTMR counter is 32 bits width. */ 651 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 652 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 653 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 654 /* @brief Do not has prescaler clock source 0. */ 655 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) 656 /* @brief Do not has prescaler clock source 1. */ 657 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) 658 /* @brief Do not has prescaler clock source 2. */ 659 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) 660 /* @brief Do not has prescaler clock source 3. */ 661 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) 662 663 /* LPUART module features */ 664 665 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 666 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 667 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 668 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 669 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 670 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 671 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 672 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 673 /* @brief Has 32-bit register MODIR */ 674 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 675 /* @brief Hardware flow control (RTS, CTS) is supported. */ 676 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 677 /* @brief Infrared (modulation) is supported. */ 678 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 679 /* @brief 2 bits long stop bit is available. */ 680 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 681 /* @brief If 10-bit mode is supported. */ 682 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 683 /* @brief If 7-bit mode is supported. */ 684 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 685 /* @brief Baud rate fine adjustment is available. */ 686 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 687 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 688 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 689 /* @brief Baud rate oversampling is available. */ 690 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 691 /* @brief Baud rate oversampling is available. */ 692 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 693 /* @brief Peripheral type. */ 694 #define FSL_FEATURE_LPUART_IS_SCI (1) 695 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 696 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ 697 (((x) == LPUART0) ? (4) : \ 698 (((x) == LPUART1) ? (4) : \ 699 (((x) == LPUART2) ? (8) : \ 700 (((x) == LPUART3) ? (8) : \ 701 (((x) == LPUART4) ? (8) : \ 702 (((x) == LPUART5) ? (8) : \ 703 (((x) == LPUART6) ? (8) : \ 704 (((x) == LPUART7) ? (8) : (-1))))))))) 705 /* @brief Supports two match addresses to filter incoming frames. */ 706 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 707 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 708 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 709 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 710 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 711 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 712 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 713 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 714 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 715 /* @brief Has improved smart card (ISO7816 protocol) support. */ 716 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 717 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 718 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 719 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 720 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 721 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 722 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 723 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 724 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 725 /* @brief Has separate DMA RX and TX requests. */ 726 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 727 /* @brief Has separate RX and TX interrupts. */ 728 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 729 /* @brief Has LPAURT_PARAM. */ 730 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 731 /* @brief Has LPUART_VERID. */ 732 #define FSL_FEATURE_LPUART_HAS_VERID (1) 733 /* @brief Has LPUART_GLOBAL. */ 734 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 735 /* @brief Has LPUART_PINCFG. */ 736 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 737 /* @brief Has register MODEM Control. */ 738 #define FSL_FEATURE_LPUART_HAS_MCR (0) 739 /* @brief Has register Half Duplex Control. */ 740 #define FSL_FEATURE_LPUART_HAS_HDCR (0) 741 /* @brief Has register Timeout. */ 742 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) 743 744 /* LTC module features */ 745 746 /* @brief LTC module supports DES algorithm. */ 747 #define FSL_FEATURE_LTC_HAS_DES (0) 748 /* @brief LTC module supports PKHA algorithm. */ 749 #define FSL_FEATURE_LTC_HAS_PKHA (0) 750 /* @brief LTC module supports SHA algorithm. */ 751 #define FSL_FEATURE_LTC_HAS_SHA (0) 752 /* @brief LTC module supports AES GCM mode. */ 753 #define FSL_FEATURE_LTC_HAS_GCM (0) 754 /* @brief LTC module supports DPAMS registers. */ 755 #define FSL_FEATURE_LTC_HAS_DPAMS (0) 756 /* @brief LTC module supports AES with 24 bytes key. */ 757 #define FSL_FEATURE_LTC_HAS_AES192 (0) 758 /* @brief LTC module supports AES with 32 bytes key. */ 759 #define FSL_FEATURE_LTC_HAS_AES256 (0) 760 761 /* SMC module features */ 762 763 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 764 #define FSL_FEATURE_SMC_HAS_PSTOPO (0) 765 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 766 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 767 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 768 #define FSL_FEATURE_SMC_HAS_PORPO (0) 769 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 770 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 771 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 772 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 773 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 774 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 775 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 776 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 777 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 778 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 779 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 780 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 781 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 782 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 783 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 784 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 785 /* @brief Has stop submode. */ 786 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) 787 /* @brief Has stop submode 0(VLLS0). */ 788 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) 789 /* @brief Has stop submode 2(VLLS2). */ 790 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 791 /* @brief Has SMC_PARAM. */ 792 #define FSL_FEATURE_SMC_HAS_PARAM (1) 793 /* @brief Has SMC_VERID. */ 794 #define FSL_FEATURE_SMC_HAS_VERID (1) 795 /* @brief Has SMC_CSRE. */ 796 #define FSL_FEATURE_SMC_HAS_CSRE (1) 797 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 798 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 799 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 800 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (1) 801 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 802 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (1) 803 /* @brief Has security violation reset (register bit SRS[VBAT]). */ 804 #define FSL_FEATURE_SMC_HAS_SRS_VBAT (1) 805 /* @brief Has security violation reset (register bit SRS[CORE0]). */ 806 #define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1) 807 /* @brief Has security violation reset (register bit SRS[CORE1]). */ 808 #define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1) 809 /* @brief Has security violation reset (register bit SRIE[VBAT]). */ 810 #define FSL_FEATURE_SMC_HAS_SRIE_VBAT (1) 811 /* @brief Has security violation reset (register bit SRIE[CORE0]). */ 812 #define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (0) 813 /* @brief Has security violation reset (register bit SRIE[CORE1]). */ 814 #define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (0) 815 /* @brief Width of SMC registers. */ 816 #define FSL_FEATURE_SMC_REG_WIDTH (32) 817 818 /* MU module features */ 819 820 /* @brief MU side for current core */ 821 #define FSL_FEATURE_MU_SIDE_A (1) 822 /* @brief MU Has register CCR */ 823 #define FSL_FEATURE_MU_HAS_CCR (0) 824 /* @brief MU Has register SR[RS], BSR[ARS] */ 825 #define FSL_FEATURE_MU_HAS_SR_RS (1) 826 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 827 #define FSL_FEATURE_MU_HAS_RESET_INT (1) 828 /* @brief MU Has register SR[MURIP] */ 829 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 830 /* @brief MU Has register SR[HRIP] */ 831 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 832 /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 833 #define FSL_FEATURE_MU_NO_CLKE (0) 834 /* @brief MU does not support NMI, CR[NMI]. */ 835 #define FSL_FEATURE_MU_NO_NMI (0) 836 /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 837 #define FSL_FEATURE_MU_NO_RSTH (0) 838 /* @brief MU does not supports MU reset, CR[MUR]. */ 839 #define FSL_FEATURE_MU_NO_MUR (0) 840 /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 841 #define FSL_FEATURE_MU_NO_HR (0) 842 /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 843 #define FSL_FEATURE_MU_HAS_HRM (0) 844 /* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */ 845 #define FSL_FEATURE_MU_NO_PM (0) 846 /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ 847 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1) 848 /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ 849 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (1) 850 851 /* interrupt module features */ 852 853 /* @brief Lowest interrupt request number. */ 854 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 855 /* @brief Highest interrupt request number. */ 856 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) 857 858 /* PCC module features */ 859 860 /* @brief PCC has SAI clock divider. */ 861 #define FSL_FEATURE_PCC_HAS_SAI_DIVIDER (1) 862 /* @brief Remove EWM Clock Gate. */ 863 #define FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE (1) 864 865 /* PORT module features */ 866 867 /* @brief Has control lock (register bit PCR[LK]). */ 868 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 869 /* @brief Has open drain control (register bit PCR[ODE]). */ 870 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 871 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 872 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 873 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 874 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 875 /* @brief Has pull resistor selection available. */ 876 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0) 877 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 878 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (0) 879 /* @brief Has slew rate control (register bit PCR[SRE]). */ 880 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) 881 /* @brief Has passive filter (register bit field PCR[PFE]). */ 882 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (0) 883 /* @brief Has drive strength control (register bit PCR[DSE]). */ 884 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0) 885 /* @brief Has separate drive strength register (HDRVE). */ 886 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 887 /* @brief Has glitch filter (register IOFLT). */ 888 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 889 /* @brief Defines width of PCR[MUX] field. */ 890 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (0) 891 /* @brief Has dedicated interrupt vector. */ 892 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 893 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 894 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) 895 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 896 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1) 897 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 898 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1) 899 900 /* QSPI module features */ 901 902 /* @brief QSPI lookup table depth. */ 903 #define FSL_FEATURE_QSPI_LUT_DEPTH (64) 904 /* @brief QSPI Tx FIFO depth. */ 905 #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) 906 /* @brief QSPI Rx FIFO depth. */ 907 #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) 908 /* @brief QSPI AHB buffer count. */ 909 #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) 910 /* @brief QSPI has command usage error flag. */ 911 #define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (0) 912 /* @brief QSPI support parallel mode. */ 913 #define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (0) 914 /* @brief QSPI support dual die. */ 915 #define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (0) 916 /* @brief there is no SCLKCFG bit in MCR register. */ 917 #define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (0) 918 /* @brief there is no AITEF bit in FR register. */ 919 #define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) 920 /* @brief there is no AIBSEF bit in FR register. */ 921 #define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (0) 922 /* @brief there is no TXDMA and TXWA bit in SR register. */ 923 #define FSL_FEATURE_QSPI_HAS_NO_TXDMA (0) 924 /* @brief there is no SFACR register. */ 925 #define FSL_FEATURE_QSPI_HAS_NO_SFACR (0) 926 /* @brief there is no TDH bit in FLSHCR register. */ 927 #define FSL_FEATURE_QSPI_HAS_NO_TDH (0) 928 /* @brief QSPI AHB buffer size in byte. */ 929 #define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (128U) 930 /* @brief QSPI AMBA base address. */ 931 #define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U) 932 /* @brief QSPI AHB buffer ARDB base address. */ 933 #define FSL_FEATURE_QSPI_ARDB_BASE (0x24000000U) 934 935 /* SCG module features */ 936 937 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ 938 #define FSL_FEATURE_SCG_HAS_DIVPLAT (1) 939 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ 940 #define FSL_FEATURE_SCG_HAS_DIVBUS (1) 941 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ 942 #define FSL_FEATURE_SCG_HAS_DIVEXT (0) 943 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ 944 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) 945 /* @brief Has SOSCCSR[SOSCERCLKEN]. */ 946 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0) 947 /* @brief Has OSC freq range SOSCCFG[RANGE]. */ 948 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0) 949 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ 950 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) 951 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ 952 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (1) 953 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ 954 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1) 955 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ 956 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1) 957 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ 958 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1) 959 /* @brief Has SCG_SIRCCSR[LPOPO]. */ 960 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (1) 961 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ 962 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1) 963 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ 964 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1) 965 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ 966 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) 967 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ 968 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (0) 969 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ 970 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (1) 971 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ 972 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (1) 973 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ 974 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) 975 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ 976 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) 977 /* @brief Has SCG_SPLLCFG[PLLS]. */ 978 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (1) 979 /* @brief Has SCG_SPLLCFG[BYPASS]. */ 980 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) 981 /* @brief Has SCG_SPLLCFG[PFDSEL]. */ 982 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (1) 983 /* @brief Has SCG_SPLLCSR[SPLLCM]. */ 984 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) 985 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ 986 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) 987 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ 988 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) 989 /* @brief Has low power FLL, SCG_LPFLLCSR. */ 990 #define FSL_FEATURE_SCG_HAS_LPFLL (0) 991 /* @brief Has system PLL, SCG_SPLLCSR. */ 992 #define FSL_FEATURE_SCG_HAS_SPLL (1) 993 /* @brief Has system PLL PFD, SCG_SPLLPFD. */ 994 #define FSL_FEATURE_SCG_HAS_SPLLPFD (1) 995 /* @brief Has auxiliary PLL, SCG_APLLCSR. */ 996 #define FSL_FEATURE_SCG_HAS_APLL (1) 997 /* @brief Has RTC OSC control, SCG_ROSCCSR. */ 998 #define FSL_FEATURE_SCG_HAS_ROSC (1) 999 /* @brief Has RTC OSC clock source. */ 1000 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1) 1001 /* @brief Has RTC OSC clock out select. */ 1002 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1) 1003 /* @brief Has EXTERNAL clock out select. */ 1004 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) 1005 /* @brief Has no System OSC configuration register, SCG_SOSCCFG. */ 1006 #define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1) 1007 /* @brief Has no SCG_SOSCCSR[SOSCEN]. */ 1008 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (1) 1009 /* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */ 1010 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (1) 1011 /* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */ 1012 #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (1) 1013 /* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */ 1014 #define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (1) 1015 /* @brief Has FIRC trim source USB0 Start of Frame. */ 1016 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (1) 1017 /* @brief Has FIRC trim source USB1 Start of Frame. */ 1018 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (1) 1019 /* @brief Has FIRC trim source system OSC. */ 1020 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) 1021 /* @brief Has FIRC trim source RTC OSC. */ 1022 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1) 1023 1024 /* SEMA42 module features */ 1025 1026 /* @brief Gate counts */ 1027 #define FSL_FEATURE_SEMA42_GATE_COUNT (16) 1028 1029 /* SIM module features */ 1030 1031 /* @brief Has USB FS divider. */ 1032 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1033 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1034 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1035 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1036 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1037 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1038 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1039 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1040 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0) 1041 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1042 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0) 1043 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1044 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1045 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1046 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1047 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1048 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1049 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1050 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1051 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1052 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1053 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1054 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1055 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1056 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1057 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1058 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1059 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1060 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1061 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1062 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) 1063 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1064 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1065 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1066 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1067 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1068 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1069 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1070 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1071 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1072 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1073 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1074 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1075 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1076 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1077 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1078 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1079 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1080 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1081 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1082 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1083 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1084 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1085 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1086 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1087 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1088 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1089 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1090 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1091 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1092 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1093 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1094 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1095 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1096 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1097 /* @brief Has FTM module(s) configuration. */ 1098 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1099 /* @brief Number of FTM modules. */ 1100 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1101 /* @brief Number of FTM triggers with selectable source. */ 1102 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1103 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1104 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1105 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1106 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1107 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1108 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1109 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1110 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1111 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1112 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1113 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1114 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1115 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1116 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1117 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1118 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1119 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1120 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1121 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1122 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1123 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1124 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1125 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1126 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1127 /* @brief Has TPM module(s) configuration. */ 1128 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1129 /* @brief The highest TPM module index. */ 1130 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1131 /* @brief Has TPM module with index 0. */ 1132 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1133 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1134 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1135 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1136 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1137 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1138 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1139 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1140 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1141 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1142 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1143 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1144 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1145 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1146 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1147 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1148 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1149 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1150 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1151 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1152 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1153 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1154 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1155 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1156 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1157 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1158 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1159 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1160 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1161 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1162 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1163 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1164 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1165 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1166 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1167 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1168 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1169 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1170 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1171 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1172 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1173 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1174 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1175 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1176 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1177 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1178 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1179 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1180 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1181 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1182 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1183 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1184 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1185 /* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */ 1186 #define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0) 1187 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1188 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) 1189 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1190 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1191 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1192 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1193 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1194 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1195 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1196 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1197 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1198 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1199 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1200 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1201 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1202 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1203 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1204 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1205 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1206 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1207 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1208 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1209 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1210 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1211 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1212 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) 1213 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1214 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) 1215 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1216 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1217 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1218 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1219 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1220 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1221 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1222 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1223 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1224 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1225 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1226 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1227 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1228 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1229 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1230 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1231 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1232 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1233 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1234 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) 1235 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1236 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) 1237 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1238 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) 1239 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1240 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) 1241 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1242 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1243 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1244 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0) 1245 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1246 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0) 1247 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1248 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1249 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1250 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1251 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1252 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1253 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1254 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1255 /* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */ 1256 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (0) 1257 /* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */ 1258 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (0) 1259 /* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */ 1260 #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (0) 1261 /* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */ 1262 #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (0) 1263 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1264 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) 1265 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1266 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1267 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1268 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1269 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1270 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1271 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1272 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1273 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1274 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1275 /* @brief Has miscellanious control register (register MCR). */ 1276 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1277 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1278 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1279 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1280 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1281 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1282 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1283 /* @brief Has MISCCTRL reg. */ 1284 #define FSL_FEATURE_SIM_HAS_MISCCTRL (0) 1285 /* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */ 1286 #define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0) 1287 /* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */ 1288 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0) 1289 /* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */ 1290 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0) 1291 /* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */ 1292 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0) 1293 /* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */ 1294 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0) 1295 /* @brief Has SECKEY0 reg. */ 1296 #define FSL_FEATURE_SIM_HAS_SECKEY0 (0) 1297 /* @brief Has SECKEY bit (e.g SIM_SECKEY0). */ 1298 #define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0) 1299 /* @brief Has SECKEY1 reg. */ 1300 #define FSL_FEATURE_SIM_HAS_SECKEY1 (0) 1301 /* @brief Has SECKEY bit (e.g SIM_SECKEY1). */ 1302 #define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0) 1303 /* @brief Has SECKEY2 reg. */ 1304 #define FSL_FEATURE_SIM_HAS_SECKEY2 (0) 1305 /* @brief Has SECKEY bit (e.g SIM_SECKEY2). */ 1306 #define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0) 1307 /* @brief Has SECKEY3 reg. */ 1308 #define FSL_FEATURE_SIM_HAS_SECKEY3 (0) 1309 /* @brief Has SECKEY bit (e.g SIM_SECKEY3). */ 1310 #define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0) 1311 /* @brief Has no SDID reg. */ 1312 #define FSL_FEATURE_SIM_HAS_NO_SDID (1) 1313 /* @brief Has no UID reg. */ 1314 #define FSL_FEATURE_SIM_HAS_NO_UID (1) 1315 /* @brief Has RFADDRL and RFADDRH registers. */ 1316 #define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (0) 1317 /* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */ 1318 #define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (0) 1319 /* @brief Has UIDH registers. */ 1320 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1321 /* @brief Has UIDM registers. */ 1322 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1323 1324 /* SNVS module features */ 1325 1326 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ 1327 #define FSL_FEATURE_SNVS_HAS_SRTC (1) 1328 /* @brief Has Passive Tamper Filter (regitser LPTGFCR). */ 1329 #define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0) 1330 /* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */ 1331 #define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0) 1332 /* @brief Number of TAMPER. */ 1333 #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) 1334 /* @brief Has Set Lock. */ 1335 #define FSL_FEATURE_SNVS_HAS_SET_LOCK (1) 1336 /* @brief Has State Transition. */ 1337 #define FSL_FEATURE_SNVS_HAS_STATE_TRANSITION (1) 1338 1339 /* SysTick module features */ 1340 1341 /* @brief Systick has external reference clock. */ 1342 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1343 /* @brief Systick external reference clock is core clock divided by this value. */ 1344 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1345 1346 /* TPM module features */ 1347 1348 /* @brief Number of channels. */ 1349 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1350 (((x) == TPM0) ? (6) : \ 1351 (((x) == TPM1) ? (2) : \ 1352 (((x) == TPM2) ? (2) : \ 1353 (((x) == TPM3) ? (6) : \ 1354 (((x) == TPM4) ? (6) : \ 1355 (((x) == TPM5) ? (2) : \ 1356 (((x) == TPM6) ? (2) : \ 1357 (((x) == TPM7) ? (6) : (-1))))))))) 1358 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1359 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1360 /* @brief Has TPM_PARAM. */ 1361 #define FSL_FEATURE_TPM_HAS_PARAM (1) 1362 /* @brief Has TPM_VERID. */ 1363 #define FSL_FEATURE_TPM_HAS_VERID (1) 1364 /* @brief Has TPM_GLOBAL. */ 1365 #define FSL_FEATURE_TPM_HAS_GLOBAL (1) 1366 /* @brief Has TPM_TRIG. */ 1367 #define FSL_FEATURE_TPM_HAS_TRIG (1) 1368 /* @brief Whether TRIG register has effect. */ 1369 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ 1370 (((x) == TPM0) ? (1) : \ 1371 (((x) == TPM1) ? (0) : \ 1372 (((x) == TPM2) ? (0) : \ 1373 (((x) == TPM3) ? (1) : \ 1374 (((x) == TPM4) ? (1) : \ 1375 (((x) == TPM5) ? (0) : \ 1376 (((x) == TPM6) ? (0) : \ 1377 (((x) == TPM7) ? (1) : (-1))))))))) 1378 /* @brief Has counter pause on trigger. */ 1379 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1380 /* @brief Has external trigger selection. */ 1381 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1382 /* @brief Has TPM_COMBINE register. */ 1383 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 1384 /* @brief Whether COMBINE register has effect. */ 1385 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 1386 /* @brief Has TPM_POL. */ 1387 #define FSL_FEATURE_TPM_HAS_POL (1) 1388 /* @brief Whether POL register has effect. */ 1389 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \ 1390 (((x) == TPM0) ? (1) : \ 1391 (((x) == TPM1) ? (0) : \ 1392 (((x) == TPM2) ? (0) : \ 1393 (((x) == TPM3) ? (1) : \ 1394 (((x) == TPM4) ? (1) : \ 1395 (((x) == TPM5) ? (0) : \ 1396 (((x) == TPM6) ? (0) : \ 1397 (((x) == TPM7) ? (1) : (-1))))))))) 1398 /* @brief Has TPM_FILTER register. */ 1399 #define FSL_FEATURE_TPM_HAS_FILTER (1) 1400 /* @brief Whether FILTER register has effect. */ 1401 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 1402 /* @brief Has TPM_QDCTRL register. */ 1403 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 1404 /* @brief Whether QDCTRL register has effect. */ 1405 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 1406 /* @brief Has pause level select. */ 1407 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (0) 1408 /* @brief Whether 32 bits counter has effect. */ 1409 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) \ 1410 (((x) == TPM0) ? (0) : \ 1411 (((x) == TPM1) ? (1) : \ 1412 (((x) == TPM2) ? (1) : \ 1413 (((x) == TPM3) ? (0) : \ 1414 (((x) == TPM4) ? (0) : \ 1415 (((x) == TPM5) ? (1) : \ 1416 (((x) == TPM6) ? (1) : \ 1417 (((x) == TPM7) ? (0) : (-1))))))))) 1418 1419 /* TRNG module features */ 1420 1421 /* No feature definitions */ 1422 1423 /* USBHS module features */ 1424 1425 /* @brief EHCI module instance count */ 1426 #define FSL_FEATURE_USBHS_EHCI_COUNT (2) 1427 /* @brief Number of endpoints supported */ 1428 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 1429 1430 /* USBPHY module features */ 1431 1432 /* @brief USBPHY contain DCD analog module */ 1433 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) 1434 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 1435 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) 1436 /* @brief USBPHY is 28FDSOI */ 1437 #define FSL_FEATURE_USBPHY_28FDSOI (0) 1438 1439 /* WDOG module features */ 1440 1441 /* @brief Watchdog is available. */ 1442 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1443 /* @brief WDOG_CNT can be 32-bit written. */ 1444 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 1445 1446 /* XRDC module features */ 1447 1448 /* @brief Has domain ID of faulted access (register bit FDID[FDID]). */ 1449 #define FSL_FEATURE_XRDC_HAS_FDID (0) 1450 /* @brief Has special 4-state model option (register bit PID[SP4SM]). */ 1451 #define FSL_FEATURE_XRDC_HAS_PID_SP4SM (0) 1452 /* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */ 1453 #define FSL_FEATURE_XRDC_NO_MDA_LPID (1) 1454 /* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */ 1455 #define FSL_FEATURE_XRDC_NO_MDA_LPE (1) 1456 /* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */ 1457 #define FSL_FEATURE_XRDC_NO_PDAC_SE (0) 1458 /* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */ 1459 #define FSL_FEATURE_XRDC_NO_PDAC_SNUM (0) 1460 /* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */ 1461 #define FSL_FEATURE_XRDC_HAS_PDAC_EALO (0) 1462 /* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */ 1463 #define FSL_FEATURE_XRDC_HAS_PDAC_EAL (0) 1464 /* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */ 1465 #define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (0) 1466 /* @brief Does not have region size configuration (register bit MRGD_W1[SZ]). */ 1467 #define FSL_FEATURE_XRDC_NO_MRGD_SZ (0) 1468 /* @brief Does not have subregion disable option (register bit MRGD_W1[SRD]). */ 1469 #define FSL_FEATURE_XRDC_NO_MRGD_SRD (0) 1470 /* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */ 1471 #define FSL_FEATURE_XRDC_NO_MRGD_SE (0) 1472 /* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */ 1473 #define FSL_FEATURE_XRDC_NO_MRGD_SNUM (0) 1474 /* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */ 1475 #define FSL_FEATURE_XRDC_NO_MRGD_DXACP (0) 1476 /* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */ 1477 #define FSL_FEATURE_XRDC_HAS_MRGD_EALO (0) 1478 /* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */ 1479 #define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (0) 1480 /* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */ 1481 #define FSL_FEATURE_XRDC_HAS_MRGD_EAL (0) 1482 /* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */ 1483 #define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (0) 1484 /* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */ 1485 #define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (0) 1486 /* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */ 1487 #define FSL_FEATURE_XRDC_HAS_MRGD_CR (0) 1488 /* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */ 1489 #define FSL_FEATURE_XRDC_DOMAIN_COUNT (8) 1490 1491 #endif /* _MCIMX7U5_cm4_FEATURES_H_ */ 1492 1493
