1 /*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kFLASH_RST_N_SHIFT_RSTn = 0 | 4U, /**< Flash controller reset control */
40 kI2C0_RST_N_SHIFT_RSTn = 0 | 5U, /**< I2C0 reset control */
41 kGPIO0_RST_N_SHIFT_RSTn = 0 | 6U, /**< GPIO0 reset control */
42 kSWM_RST_N_SHIFT_RSTn = 0 | 7U, /**< SWM reset control */
43 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
44 kMRT_RST_N_SHIFT_RSTn = 0 | 10U, /**< Multi-rate timer(MRT) reset control */
45 kSPI0_RST_N_SHIFT_RSTn = 0 | 11U, /**< SPI0 reset control. */
46 kSPI1_RST_N_SHIFT_RSTn = 0 | 12U, /**< SPI1 reset control */
47 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
48 kUART0_RST_N_SHIFT_RSTn = 0 | 14U, /**< UART0 reset control */
49 kUART1_RST_N_SHIFT_RSTn = 0 | 15U, /**< UART1 reset control */
50 kUART2_RST_N_SHIFT_RSTn = 0 | 16U, /**< UART2 reset control */
51 kIOCON_RST_N_SHIFT_RSTn = 0 | 18U, /**< IOCON reset control */
52 kACMP_RST_N_SHIFT_RSTn = 0 | 19U, /**< Analog comparator reset control */
53 kGPIO1_RST_N_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */
54 kFTM0_RST_N_SHIFT_RSTn = 0 | 21U, /**< FTM0 reset control */
55 kFTM1_RST_N_SHIFT_RSTn = 0 | 22U, /**< FTM1 reset control */
56 kI3C_RST_N_SHIFT_RSTn = 0 | 23U, /**< I3C reset control */
57 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
58 kGPIOINT_RST_N_SHIFT_RSTn = 0 | 28U, /**< GPIOINT reset control */
59 kDMA_RST_N_SHIFT_RSTn = 0 | 29U, /**< DMA reset control */
60
61 kFRG0_RST_N_SHIFT_RSTn = 65536 | 3U, /**< Fractional baud rate generator 0 reset control */
62 kFRG1_RST_N_SHIFT_RSTn = 65536 | 4U, /**< Fractional baud rate generator 1 reset control */
63
64 } SYSCON_RSTn_t;
65
66 /** Array initializers with peripheral reset bits **/
67 #define FLASH_RSTS_N \
68 { \
69 kFLASH_RST_N_SHIFT_RSTn \
70 } /* Reset bits for Flash peripheral */
71 #define I2C_RSTS_N \
72 { \
73 kI2C0_RST_N_SHIFT_RSTn \
74 } /* Reset bits for I2C peripheral */
75 #define GPIO_RSTS_N \
76 { \
77 kGPIO0_RST_N_SHIFT_RSTn, kGPIO1_RST_N_SHIFT_RSTn \
78 } /* Reset bits for GPIO peripheral */
79 #define SWM_RSTS_N \
80 { \
81 kSWM_RST_N_SHIFT_RSTn \
82 } /* Reset bits for SWM peripheral */
83 #define WKT_RSTS_N \
84 { \
85 kWKT_RST_N_SHIFT_RSTn \
86 } /* Reset bits for WKT peripheral */
87 #define MRT_RSTS_N \
88 { \
89 kMRT_RST_N_SHIFT_RSTn \
90 } /* Reset bits for MRT peripheral */
91 #define SPI_RSTS_N \
92 { \
93 kSPI0_RST_N_SHIFT_RSTn, kSPI1_RST_N_SHIFT_RSTn \
94 } /* Reset bits for SPI peripheral */
95 #define CRC_RSTS_N \
96 { \
97 kCRC_RST_SHIFT_RSTn \
98 } /* Reset bits for CRC peripheral */
99 #define UART_RSTS_N \
100 { \
101 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn, kUART2_RST_N_SHIFT_RSTn \
102 } /* Reset bits for UART peripheral */
103 #define IOCON_RSTS_N \
104 { \
105 kIOCON_RST_N_SHIFT_RSTn \
106 } /* Reset bits for IOCON peripheral */
107 #define ACMP_RSTS_N \
108 { \
109 kACMP_RST_N_SHIFT_RSTn \
110 } /* Reset bits for ACMP peripheral */
111
112 #define FTM_RSTS_N \
113 { \
114 kFTM0_RST_N_SHIFT_RSTn, kFTM1_RST_N_SHIFT_RSTn \
115 } /* Reset bits for FTM peripheral */
116
117 #define I3C_RSTS \
118 { \
119 kI3C_RST_N_SHIFT_RSTn \
120 } /* Reset bits for I3C peripheral */
121 #define ADC_RSTS_N \
122 { \
123 kADC_RST_N_SHIFT_RSTn \
124 } /* Reset bits for ADC peripheral */
125 #define GPIOINT_RSTS_N \
126 { \
127 kGPIOINT_RST_N_SHIFT_RSTn \
128 } /* Reset bits for GPIOINT peripheral */
129 #define DMA_RSTS_N \
130 { \
131 kDMA_RST_N_SHIFT_RSTn \
132 } /* Reset bits for DMA peripheral */
133 #define FRG_RSTS_N \
134 { \
135 kFRG0_RST_N_SHIFT_RSTn, kFRG1_RST_N_SHIFT_RSTn \
136 } /* Reset bits for FRG peripheral */
137
138 typedef SYSCON_RSTn_t reset_ip_name_t;
139
140 /*******************************************************************************
141 * API
142 ******************************************************************************/
143 #if defined(__cplusplus)
144 extern "C" {
145 #endif
146
147 /*!
148 * @brief Assert reset to peripheral.
149 *
150 * Asserts reset signal to specified peripheral module.
151 *
152 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
153 * and reset bit position in the reset register.
154 */
155 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
156
157 /*!
158 * @brief Clear reset to peripheral.
159 *
160 * Clears reset signal to specified peripheral module, allows it to operate.
161 *
162 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
163 * and reset bit position in the reset register.
164 */
165 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
166
167 /*!
168 * @brief Reset peripheral module.
169 *
170 * Reset peripheral module.
171 *
172 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
173 * and reset bit position in the reset register.
174 */
175 void RESET_PeripheralReset(reset_ip_name_t peripheral);
176
177 /*!
178 * @brief Release peripheral module.
179 *
180 * Release peripheral module.
181 *
182 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
183 * and reset bit position in the reset register.
184 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)185 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
186 {
187 RESET_ClearPeripheralReset(peripheral);
188 }
189
190 #if defined(__cplusplus)
191 }
192 #endif
193
194 /*! @} */
195
196 #endif /* _FSL_RESET_H_ */
197
