1 /* 2 * Copyright 2017 NXP 3 * All rights reserved. 4 * 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_INPUTMUX_CONNECTIONS_ 10 #define _FSL_INPUTMUX_CONNECTIONS_ 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 /* Component ID definition, used by tools. */ 16 #ifndef FSL_COMPONENT_ID 17 #define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" 18 #endif 19 20 /*! 21 * @addtogroup inputmux_driver 22 * @{ 23 */ 24 25 /*! 26 * @name Input multiplexing connections 27 * @{ 28 */ 29 30 /*! @brief Periphinmux IDs */ 31 #define DMA_OTRIG_PMUX_ID 0x00U 32 #define DMA_TRIG0_PMUX_ID 0x40U 33 #define PMUX_SHIFT 20U 34 35 /*! @brief INPUTMUX connections type */ 36 typedef enum _inputmux_connection_t 37 { 38 /*!< DMA OTRIG. */ 39 kINPUTMUX_DmaChannel0TrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 40 kINPUTMUX_DmaChannel1TrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 41 kINPUTMUX_DmaChannel2TrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 42 kINPUTMUX_DmaChannel3TrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 43 kINPUTMUX_DmaChannel4TrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 44 kINPUTMUX_DmaChannel5TrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 45 kINPUTMUX_DmaChannel6TrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 46 kINPUTMUX_DmaChannel7TrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 47 kINPUTMUX_DmaChannel8TrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 48 kINPUTMUX_DmaChannel9TrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 49 kINPUTMUX_DmaChannel10TrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 50 kINPUTMUX_DmaChannel11TrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 51 kINPUTMUX_DmaChannel12TrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 52 kINPUTMUX_DmaChannel13TrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 53 kINPUTMUX_DmaChannel14TrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 54 kINPUTMUX_DmaChannel15TrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), 55 56 /*!< DMA ITRIG. */ 57 kINPUTMUX_GpioInt4ToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 58 kINPUTMUX_GpioInt5ToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 59 kINPUTMUX_GpioInt6ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 60 kINPUTMUX_GpioInt7ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 61 kINPUTMUX_Adc0SeqaIrqToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 62 kINPUTMUX_Adc0SeqbIrqToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 63 kINPUTMUX_Comp0OutToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 64 kINPUTMUX_Ftm0InitTrigToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 65 kINPUTMUX_Ftm1InitTrigToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 66 kINPUTMUX_Ftm0Ch0ToCh5ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 67 kINPUTMUX_Ftm1Ch0ToCh3ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 68 kINPUTMUX_SdmaTrigoutAToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 69 kINPUTMUX_SdmaTrigoutBToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), 70 } inputmux_connection_t; 71 72 /*@}*/ 73 74 /*@}*/ 75 76 #endif /* _FSL_INPUTMUX_CONNECTIONS_ */ 77
