1 /* 2 ** ################################################################### 3 ** Processors: LPC844M201JBD48 4 ** LPC844M201JBD64 5 ** LPC844M201JHI33 6 ** LPC844M201JHI48 7 ** 8 ** Compilers: GNU C Compiler 9 ** IAR ANSI C/C++ Compiler for ARM 10 ** Keil ARM C/C++ Compiler 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: LPC84x User manual Rev.1.6 8 Dec 2017 14 ** Version: rev. 1.2, 2017-06-08 15 ** Build: b240408 16 ** 17 ** Abstract: 18 ** Provides a system configuration function and a global variable that 19 ** contains the system frequency. It configures the device and initializes 20 ** the oscillator (PLL) that is part of the microcontroller device. 21 ** 22 ** Copyright 2016 Freescale Semiconductor, Inc. 23 ** Copyright 2016-2024 NXP 24 ** SPDX-License-Identifier: BSD-3-Clause 25 ** 26 ** http: www.nxp.com 27 ** mail: support@nxp.com 28 ** 29 ** Revisions: 30 ** - rev. 1.0 (2016-08-12) 31 ** Initial version. 32 ** - rev. 1.1 (2016-11-25) 33 ** Update CANFD and Classic CAN register. 34 ** Add MAC TIMERSTAMP registers. 35 ** - rev. 1.2 (2017-06-08) 36 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 37 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 38 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 39 ** 40 ** ################################################################### 41 */ 42 43 /*! 44 * @file LPC844 45 * @version 1.2 46 * @date 2017-06-08 47 * @brief Device specific configuration file for LPC844 (implementation file) 48 * 49 * Provides a system configuration function and a global variable that contains 50 * the system frequency. It configures the device and initializes the oscillator 51 * (PLL) that is part of the microcontroller device. 52 */ 53 54 #include <stdint.h> 55 #include "fsl_device_registers.h" 56 57 58 59 60 61 /* ---------------------------------------------------------------------------- 62 -- Core clock 63 ---------------------------------------------------------------------------- */ 64 65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 66 67 /* ---------------------------------------------------------------------------- 68 -- SystemInit() 69 ---------------------------------------------------------------------------- */ 70 SystemInit(void)71void SystemInit (void) { 72 73 #if defined(__MCUXPRESSO) 74 extern void(*const g_pfnVectors[]) (void); 75 SCB->VTOR = (uint32_t) &g_pfnVectors; 76 #else 77 extern void *__Vectors; 78 SCB->VTOR = (uint32_t) &__Vectors; 79 #endif 80 SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 81 SystemInitHook(); 82 } 83 84 /* ---------------------------------------------------------------------------- 85 -- SystemCoreClockUpdate() 86 ---------------------------------------------------------------------------- */ 87 SystemCoreClockUpdate(void)88void SystemCoreClockUpdate (void) { 89 uint32_t wdt_osc = 0U; 90 uint32_t fro_osc = 0U; 91 92 /* Determine clock frequency according to clock register values */ 93 switch ((SYSCON->FROOSCCTRL ) & 0x03U) { 94 case 0U: fro_osc = 18000000U; break; 95 case 1U: fro_osc = 24000000U; break; 96 case 2U: fro_osc = 30000000U; break; 97 case 3U: fro_osc = 30000000U; break; 98 default: fro_osc = 0U; break; 99 } 100 if (((SYSCON->FROOSCCTRL >> SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT) & 0x01U) == 0U) { 101 fro_osc = fro_osc >> 1U; 102 } 103 104 switch ((SYSCON->WDTOSCCTRL >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) & 0x0FU) { 105 case 0U: wdt_osc = 0U; break; 106 case 1U: wdt_osc = 600000U; break; 107 case 2U: wdt_osc = 1050000U; break; 108 case 3U: wdt_osc = 1400000U; break; 109 case 4U: wdt_osc = 1750000U; break; 110 case 5U: wdt_osc = 2100000U; break; 111 case 6U: wdt_osc = 2400000U; break; 112 case 7U: wdt_osc = 2700000U; break; 113 case 8U: wdt_osc = 3000000U; break; 114 case 9U: wdt_osc = 3250000U; break; 115 case 10U: wdt_osc = 3500000U; break; 116 case 11U: wdt_osc = 3750000U; break; 117 case 12U: wdt_osc = 4000000U; break; 118 case 13U: wdt_osc = 4200000U; break; 119 case 14U: wdt_osc = 4400000U; break; 120 case 15U: wdt_osc = 4600000U; break; 121 default: wdt_osc = 0U; break; 122 } 123 wdt_osc /= (((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1U) << 1U); 124 125 switch (SYSCON->MAINCLKPLLSEL & 0x01U) { 126 case 0U: /* main_clk_pre_pll */ 127 switch (SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) { 128 case 0U: /* Free running oscillator (FRO) */ 129 SystemCoreClock = fro_osc; 130 break; 131 case 1U: /* System oscillator */ 132 SystemCoreClock = CLK_OSC_IN; 133 break; 134 case 2U: /* watchdog oscillator */ 135 SystemCoreClock = wdt_osc; 136 break; 137 case 3U: /* Free running oscillator (FRO) / 2 */ 138 SystemCoreClock = (fro_osc >> 1U); 139 break; 140 default: 141 SystemCoreClock = 0U; 142 break; 143 } 144 break; 145 case 1U: /* System PLL Clock Out */ 146 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) { 147 case 0U: /* Free running oscillator (FRO) */ 148 SystemCoreClock = fro_osc * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 149 break; 150 case 1U: /* System oscillator */ 151 SystemCoreClock = CLK_OSC_IN * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 152 break; 153 case 2U: /* watchdog oscillator */ 154 SystemCoreClock = wdt_osc * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 155 break; 156 case 3U: /* Free running oscillator (FRO) / 2 */ 157 SystemCoreClock = (fro_osc >> 1U) * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U); 158 break; 159 default: 160 SystemCoreClock = 0U; 161 break; 162 } 163 break; 164 default: 165 SystemCoreClock = 0U; 166 break; 167 } 168 169 SystemCoreClock /= SYSCON->SYSAHBCLKDIV; 170 } 171 172 /* ---------------------------------------------------------------------------- 173 -- SystemInitHook() 174 ---------------------------------------------------------------------------- */ 175 SystemInitHook(void)176__attribute__ ((weak)) void SystemInitHook (void) { 177 /* Void implementation of the weak function. */ 178 } 179
