1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.4.4. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31 #endif
32
33 /*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38 extern uint32_t g_Wdt_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern uint32_t g_Ext_Clk_Freq;
49
50 extern uint32_t g_Sys_Pll_Freq;
51
52 /*! @brief Clock ip name array for ADC. */
53 #define ADC_CLOCKS \
54 { \
55 kCLOCK_Adc, \
56 }
57 /*! @brief Clock ip name array for ACMP. */
58 #define ACMP_CLOCKS \
59 { \
60 kCLOCK_Acmp, \
61 }
62 /*! @brief Clock ip name array for SWM. */
63 #define SWM_CLOCKS \
64 { \
65 kCLOCK_Swm, \
66 }
67 /*! @brief Clock ip name array for ROM. */
68 #define ROM_CLOCKS \
69 { \
70 kCLOCK_Rom, \
71 }
72 /*! @brief Clock ip name array for SRAM. */
73 #define SRAM_CLOCKS \
74 { \
75 kCLOCK_Ram0_1, \
76 }
77 /*! @brief Clock ip name array for IOCON. */
78 #define IOCON_CLOCKS \
79 { \
80 kCLOCK_Iocon, \
81 }
82 /*! @brief Clock ip name array for GPIO. */
83 #define GPIO_CLOCKS \
84 { \
85 kCLOCK_Gpio0, \
86 }
87 /*! @brief Clock ip name array for GPIO_INT. */
88 #define GPIO_INT_CLOCKS \
89 { \
90 kCLOCK_GpioInt, \
91 }
92 /*! @brief Clock ip name array for DMA. */
93 #define DMA_CLOCKS \
94 { \
95 kCLOCK_Dma, \
96 }
97 /*! @brief Clock ip name array for CRC. */
98 #define CRC_CLOCKS \
99 { \
100 kCLOCK_Crc, \
101 }
102 /*! @brief Clock ip name array for WWDT. */
103 #define WWDT_CLOCKS \
104 { \
105 kCLOCK_Wwdt, \
106 }
107 /*! @brief Clock ip name array for SCT0. */
108 #define SCT_CLOCKS \
109 { \
110 kCLOCK_Sct, \
111 }
112 /*! @brief Clock ip name array for I2C. */
113 #define I2C_CLOCKS \
114 { \
115 kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, \
116 }
117 /*! @brief Clock ip name array for I2C. */
118 #define USART_CLOCKS \
119 { \
120 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
121 }
122 /*! @brief Clock ip name array for SPI. */
123 #define SPI_CLOCKS \
124 { \
125 kCLOCK_Spi0, kCLOCK_Spi1, \
126 }
127 /*! @brief Clock ip name array for MTB. */
128 #define MTB_CLOCKS \
129 { \
130 kCLOCK_Mtb, \
131 }
132 /*! @brief Clock ip name array for MRT. */
133 #define MRT_CLOCKS \
134 { \
135 kCLOCK_Mrt, \
136 }
137 /*! @brief Clock ip name array for WKT. */
138 #define WKT_CLOCKS \
139 { \
140 kCLOCK_Wkt, \
141 }
142
143 /*! @brief Internal used Clock definition only. */
144 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
145 #define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
146 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
147 /* clock mux register definition */
148 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
149 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
150 #define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
151 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
152 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) ((((uint32_t)(x)) >> 8U) & 0xFFU)
153 #define CLK_MAIN_CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
154 /* clock divider register definition */
155 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
156 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
157 /* watch dog oscillator definition */
158 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
159 #define CLK_WDT_OSC_GET_FREQ(x) (((uint32_t)(x)) & 0xFFFFFFU)
160 #define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
161 /* register offset */
162 #define SYS_AHB_CLK_CTRL (0U)
163 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
164 typedef enum _clock_ip_name
165 {
166 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U), /*!< Clock gate name: Sys. */
167 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U), /*!< Clock gate name: Rom. */
168 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U), /*!< Clock gate name: Ram0_1. */
169 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U), /*!< Clock gate name: Flashreg. */
170 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U), /*!< Clock gate name: Flash. */
171 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U), /*!< Clock gate name: I2c0. */
172 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U), /*!< Clock gate name: Gpio0. */
173 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U), /*!< Clock gate name: Swm. */
174 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U), /*!< Clock gate name: Sct. */
175 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U), /*!< Clock gate name: Wkt. */
176 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U), /*!< Clock gate name: Mrt. */
177 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U), /*!< Clock gate name: Spi0. */
178 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U), /*!< Clock gate name: Spi1. */
179 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U), /*!< Clock gate name: Crc. */
180 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U), /*!< Clock gate name: Uart0. */
181 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U), /*!< Clock gate name: Uart1. */
182 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U), /*!< Clock gate name: Uart2. */
183 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U), /*!< Clock gate name: Wwdt. */
184 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U), /*!< Clock gate name: Iocon. */
185 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U), /*!< Clock gate name: Acmp. */
186 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 21U), /*!< Clock gate name: I2c1. */
187 kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 22U), /*!< Clock gate name: I2c2. */
188 kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 23U), /*!< Clock gate name: I2c3. */
189 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 24U), /*!< Clock gate name: Adc. */
190 kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 26U), /*!< Clock gate name: Mtb. */
191 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 29U), /*!< Clock gate name: Dma. */
192 } clock_ip_name_t;
193
194 /*! @brief Clock name used to get clock frequency. */
195 typedef enum _clock_name
196 {
197 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
198 kCLOCK_MainClk, /*!< Main clock */
199 kCLOCK_SysOsc, /*!< Crystal Oscillator */
200 kCLOCK_Irc, /*!< IRC12M */
201 kCLOCK_ExtClk, /*!< External Clock */
202 kCLOCK_PllOut, /*!< PLL Output */
203 kCLOCK_Pllin, /*!< PLL Input */
204 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
205 } clock_name_t;
206
207 /*! @brief Clock Mux Switches
208 *CLK_MUX_DEFINE(reg, mux)
209 *reg is used to define the mux register
210 *mux is used to define the mux value
211 *
212 */
213 typedef enum _clock_select
214 {
215
216 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U), /*!< Mux SYSPLL from Irc. */
217
218 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U), /*!< Mux SYSPLL from SysOsc. */
219
220 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U), /*!< Mux SYSPLL from ExtClk. */
221
222 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U), /*!< Mux MAINCLK from Irc. */
223
224 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U), /*!< Mux MAINCLK from SysPllIn. */
225
226 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U), /*!< Mux MAINCLK from WdtOsc. */
227
228 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U), /*!< Mux MAINCLK from SysPll. */
229
230 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Irc. */
231
232 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from SysOsc. */
233
234 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U), /*!< Mux CLKOUT from WdtOsc. */
235
236 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U) /*!< Mux clock out from Main clock. */
237 } clock_select_t;
238
239 /*! @brief Clock divider
240 */
241 typedef enum _clock_divider
242 {
243
244 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV), /*!< Usart Clock Divider. */
245
246 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), /*!< Clk Out Divider. */
247
248 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV), /*!< Uart Frg Divider. */
249
250 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6), /*!< IOCON Clock Div6 Divider. */
251
252 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5), /*!< IOCON Clock Div5 Divider. */
253
254 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4), /*!< IOCON Clock Div4 Divider. */
255
256 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3), /*!< IOCON Clock Div3 Divider. */
257
258 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2), /*!< IOCON Clock Div2 Divider. */
259
260 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1), /*!< IOCON Clock Div1 Divider. */
261
262 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0), /*!< IOCON Clock Div0 Divider. */
263
264 } clock_divider_t;
265
266 /*! @brief watch dog analog output frequency */
267 typedef enum _clock_wdt_analog_freq
268 {
269 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U), /*!< Watch dog analog output frequency is 0HZ. */
270
271 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U), /*!< Watch dog analog output frequency is 600KHZ. */
272
273 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u), /*!< Watch dog analog output frequency is 1050KHZ. */
274
275 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U), /*!< Watch dog analog output frequency is 1400KHZ. */
276
277 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U), /*!< Watch dog analog output frequency is 1750KHZ. */
278
279 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U), /*!< Watch dog analog output frequency is 2100KHZ. */
280
281 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U), /*!< Watch dog analog output frequency is 2400KHZ. */
282
283 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U), /*!< Watch dog analog output frequency is 2700KHZ. */
284
285 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U), /*!< Watch dog analog output frequency is 3000KHZ. */
286
287 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U), /*!< Watch dog analog output frequency is 3250KHZ. */
288
289 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U), /*!< Watch dog analog output frequency is 3500KHZ. */
290
291 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U), /*!< Watch dog analog output frequency is 3750KHZ. */
292
293 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U), /*!< Watch dog analog output frequency is 4000KHZ. */
294
295 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U), /*!< Watch dog analog output frequency is 4200KHZ. */
296
297 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U), /*!< Watch dog analog output frequency is 4400KHZ. */
298
299 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U), /*!< Watch dog analog output frequency is 4600KHZ. */
300
301 } clock_wdt_analog_freq_t;
302
303 /*! @brief PLL clock definition.*/
304 typedef enum _clock_sys_pll_src
305 {
306 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
307 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
308 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
309 } clock_sys_pll_src;
310
311 /*! @brief Main clock source definition */
312 typedef enum _clock_main_clk_src
313 {
314 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
315 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
316 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
317 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
318 } clock_main_clk_src_t;
319
320 /*! @brief PLL configuration structure */
321 typedef struct _clock_sys_pll
322 {
323 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
324 clock_sys_pll_src src; /*!< System pll clock source */
325 } clock_sys_pll_t;
326
327 /*******************************************************************************
328 * API
329 ******************************************************************************/
330
331 #if defined(__cplusplus)
332 extern "C" {
333 #endif /* __cplusplus */
334
335 /*!
336 * @name Clock gate, mux, and divider.
337 * @{
338 */
339
340 /*
341 *! @brief enable ip clock.
342 *
343 * @param clk clock ip definition.
344 */
CLOCK_EnableClock(clock_ip_name_t clk)345 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
346 {
347 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
348 }
349
350 /*
351 *!@brief disable ip clock.
352 *
353 * @param clk clock ip definition.
354 */
CLOCK_DisableClock(clock_ip_name_t clk)355 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
356 {
357 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
358 }
359
360 /*
361 *! @brief Configure the clock selection muxes.
362 * @param mux : Clock to be configured.
363 * @return Nothing
364 */
CLOCK_Select(clock_select_t sel)365 static inline void CLOCK_Select(clock_select_t sel)
366 {
367 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
368 }
369
370 /*
371 *! @brief Setup peripheral clock dividers.
372 * @param name : Clock divider name
373 * @param value: Value to be divided
374 * @return Nothing
375 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)376 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
377 {
378 CLK_DIV_GET_REG(name) = value & 0xFFU;
379 }
380
381 /*
382 *! @brief Get peripheral clock dividers.
383 * @param name : Clock divider name
384 * @return clock divider value
385 */
CLOCK_GetClkDivider(clock_divider_t name)386 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
387 {
388 return CLK_DIV_GET_REG(name) & 0xFFU;
389 }
390
391 /*
392 *! @brief Setup Core clock dividers.
393 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
394 * @param value: Value to be divided
395 * @return Nothing
396 */
CLOCK_SetCoreSysClkDiv(uint32_t value)397 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
398 {
399 assert(value != 0U);
400
401 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
402 }
403
404 /*! @brief Set main clock reference source.
405 * @param src, reference clock_main_clk_src_t to set the main clock source.
406 */
407 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
408
409 /*
410 *! @brief Set Fractional generator 0 multiplier value.
411 * @param mul : FRG0 multiplier value.
412 * @return Nothing
413 */
CLOCK_SetFRGClkMul(uint32_t mul)414 static inline void CLOCK_SetFRGClkMul(uint32_t mul)
415 {
416 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
417 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
418 }
419 /* @} */
420
421 /*!
422 * @name Get frequency
423 * @{
424 */
425
426 /*! @brief Return Frequency of Main Clock.
427 * @return Frequency of Main Clock.
428 */
429 uint32_t CLOCK_GetMainClkFreq(void);
430
431 /*! @brief Return Frequency of core.
432 * @return Frequency of core.
433 */
CLOCK_GetCoreSysClkFreq(void)434 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
435 {
436 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
437 }
438
439 /*! @brief Return Frequency of ClockOut
440 * @return Frequency of ClockOut
441 */
442 uint32_t CLOCK_GetClockOutClkFreq(void);
443
444 /*! @brief Return Frequency of IRC
445 * @return Frequency of IRC
446 */
447 uint32_t CLOCK_GetIrcFreq(void);
448
449 /*! @brief Return Frequency of SYSOSC
450 * @return Frequency of SYSOSC
451 */
452 uint32_t CLOCK_GetSysOscFreq(void);
453
454 /*! @brief Get UART0 frequency
455 * @retval UART0 frequency value.
456 */
457 uint32_t CLOCK_GetUartClkFreq(void);
458
459 /*! @brief Get UART0 frequency
460 * @retval UART0 frequency value.
461 */
462 uint32_t CLOCK_GetUart0ClkFreq(void);
463
464 /*! @brief Get UART1 frequency
465 * @retval UART1 frequency value.
466 */
467 uint32_t CLOCK_GetUart1ClkFreq(void);
468
469 /*! @brief Get UART2 frequency
470 * @retval UART2 frequency value.
471 */
472 uint32_t CLOCK_GetUart2ClkFreq(void);
473
474 /*! @brief Return Frequency of selected clock
475 * @return Frequency of selected clock
476 */
477 uint32_t CLOCK_GetFreq(clock_name_t clockName);
478
479 /*! @brief Return System PLL input clock rate
480 * @return System PLL input clock rate
481 */
482 uint32_t CLOCK_GetSystemPLLInClockRate(void);
483
484 /*! @brief Return Frequency of System PLL
485 * @return Frequency of PLL
486 */
CLOCK_GetSystemPLLFreq(void)487 static inline uint32_t CLOCK_GetSystemPLLFreq(void)
488 {
489 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
490 }
491
492 /*! @brief Get watch dog OSC frequency
493 * @retval watch dog OSC frequency value.
494 */
CLOCK_GetWdtOscFreq(void)495 static inline uint32_t CLOCK_GetWdtOscFreq(void)
496 {
497 return g_Wdt_Osc_Freq;
498 }
499
500 /*! @brief Get external clock frequency
501 * @retval external clock frequency value.
502 */
CLOCK_GetExtClkFreq(void)503 static inline uint32_t CLOCK_GetExtClkFreq(void)
504 {
505 return g_Ext_Clk_Freq;
506 }
507 /* @} */
508
509 /*!
510 * @name PLL operations
511 * @{
512 */
513
514 /*! @brief System PLL initialize.
515 * @param config System PLL configurations.
516 */
517 void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
518
519 /*! @brief System PLL Deinitialize.*/
CLOCK_DenitSystemPll(void)520 static inline void CLOCK_DenitSystemPll(void)
521 {
522 /* Power off PLL */
523 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
524 }
525
526 /* @} */
527
528 /*!
529 * @name External/internal oscillator clock operations
530 * @{
531 */
532
533 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
534 * @param clkInFreq external clock in frequency.
535 */
536 void CLOCK_InitExtClkin(uint32_t clkInFreq);
537
538 /*! @brief Init SYS OSC
539 * @param oscFreq oscillator frequency value.
540 */
541 void CLOCK_InitSysOsc(uint32_t oscFreq);
542
543 /*! @brief XTALIN init function
544 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
545 * @param xtalInFreq XTALIN frequency value
546 * @return Frequency of PLL
547 */
548 void CLOCK_InitXtalin(uint32_t xtalInFreq);
549
550 /*! @brief Deinit SYS OSC
551 * @param config oscillator configuration.
552 */
CLOCK_DeinitSysOsc(void)553 static inline void CLOCK_DeinitSysOsc(void)
554 {
555 /* Deinit system osc power */
556 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
557 }
558
559 /*! @brief Init watch dog OSC
560 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
561 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
562 * consumption. If accurate timing is required, use the FRO or system oscillator.
563 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
564 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
565 * using the watchdog oscillator.
566 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
567 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
568 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
569 */
570 void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
571
572 /*! @brief Deinit watch dog OSC
573 * @param config oscillator configuration.
574 */
CLOCK_DeinitWdtOsc(void)575 static inline void CLOCK_DeinitWdtOsc(void)
576 {
577 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
578 }
579
580 /*! @brief Set UARTFRG
581 * @param target UART clock src.
582 */
583 bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
584
585 /*! @brief updates the clock source of the CLKOUT
586 */
587 void CLOCK_UpdateClkOUTsrc(void);
588
589 /*! @brief Set UARTFRGMULT
590 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
591 * @param UARTFRGMULT.
592 */
CLOCK_SetUARTFRGMULT(uint32_t mul)593 static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
594 {
595 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
596 }
597
598 /* @} */
599
600 #if defined(__cplusplus)
601 }
602 #endif /* __cplusplus */
603
604 /*! @} */
605
606 #endif /* _FSL_CLOCK_H_ */
607
