1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.4.4. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31 #endif
32
33 /*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38 extern volatile uint32_t g_Wdt_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern volatile uint32_t g_Ext_Clk_Freq;
49
50 /*! @brief Clock ip name array for ADC. */
51 #define ADC_CLOCKS \
52 { \
53 kCLOCK_Adc, \
54 }
55 /*! @brief Clock ip name array for ACMP. */
56 #define ACMP_CLOCKS \
57 { \
58 kCLOCK_Acmp, \
59 }
60 /*! @brief Clock ip name array for SWM. */
61 #define SWM_CLOCKS \
62 { \
63 kCLOCK_Swm, \
64 }
65 /*! @brief Clock ip name array for ROM. */
66 #define ROM_CLOCKS \
67 { \
68 kCLOCK_Rom, \
69 }
70 /*! @brief Clock ip name array for SRAM. */
71 #define SRAM_CLOCKS \
72 { \
73 kCLOCK_Ram0_1, \
74 }
75 /*! @brief Clock ip name array for IOCON. */
76 #define IOCON_CLOCKS \
77 { \
78 kCLOCK_Iocon, \
79 }
80 /*! @brief Clock ip name array for GPIO. */
81 #define GPIO_CLOCKS \
82 { \
83 kCLOCK_Gpio0, \
84 }
85 /*! @brief Clock ip name array for GPIO_INT. */
86 #define GPIO_INT_CLOCKS \
87 { \
88 kCLOCK_GpioInt, \
89 }
90 /*! @brief Clock ip name array for DMA. */
91 #define DMA_CLOCKS \
92 { \
93 kCLOCK_Dma, \
94 }
95 /*! @brief Clock ip name array for CRC. */
96 #define CRC_CLOCKS \
97 { \
98 kCLOCK_Crc, \
99 }
100 /*! @brief Clock ip name array for WWDT. */
101 #define WWDT_CLOCKS \
102 { \
103 kCLOCK_Wwdt, \
104 }
105 /*! @brief Clock ip name array for SCT0. */
106 #define SCT_CLOCKS \
107 { \
108 kCLOCK_Sct, \
109 }
110 /*! @brief Clock ip name array for I2C. */
111 #define I2C_CLOCKS \
112 { \
113 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, \
114 }
115 /*! @brief Clock ip name array for I2C. */
116 #define USART_CLOCKS \
117 { \
118 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
119 }
120 /*! @brief Clock ip name array for SPI. */
121 #define SPI_CLOCKS \
122 { \
123 kCLOCK_Spi0, kCLOCK_Spi1, \
124 }
125 /*! @brief Clock ip name array for MTB. */
126 #define MTB_CLOCKS \
127 { \
128 kCLOCK_Mtb, \
129 }
130 /*! @brief Clock ip name array for MRT. */
131 #define MRT_CLOCKS \
132 { \
133 kCLOCK_Mrt, \
134 }
135 /*! @brief Clock ip name array for WKT. */
136 #define WKT_CLOCKS \
137 { \
138 kCLOCK_Wkt, \
139 }
140
141 /*! @brief Internal used Clock definition only. */
142 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
143 #define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
144 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
145 /* clock mux register definition */
146 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
147 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
148 #define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
149 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
150 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) ((((uint32_t)(x)) >> 8U) & 0xFFU)
151 #define CLK_MAIN_CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
152 /* clock divider register definition */
153 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
154 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
155 /* watch dog oscillator definition */
156 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
157 #define CLK_WDT_OSC_GET_FREQ(x) (((uint32_t)(x)) & 0xFFFFFFU)
158 #define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
159 /* register offset */
160 #define SYS_AHB_CLK_CTRL (0U)
161 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
162 typedef enum _clock_ip_name
163 {
164 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U), /*!< Clock gate name: Sys. */
165 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U), /*!< Clock gate name: Rom. */
166 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U), /*!< Clock gate name: Ram0_1. */
167 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U), /*!< Clock gate name: Flashreg. */
168 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U), /*!< Clock gate name: Flash. */
169 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U), /*!< Clock gate name: I2c0. */
170 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U), /*!< Clock gate name: Gpio0. */
171 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U), /*!< Clock gate name: Swm. */
172 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U), /*!< Clock gate name: Sct. */
173 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U), /*!< Clock gate name: Wkt. */
174 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U), /*!< Clock gate name: Mrt. */
175 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U), /*!< Clock gate name: Spi0. */
176 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U), /*!< Clock gate name: Spi1. */
177 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U), /*!< Clock gate name: Crc. */
178 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U), /*!< Clock gate name: Uart0. */
179 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U), /*!< Clock gate name: Uart1. */
180 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U), /*!< Clock gate name: Uart2. */
181 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U), /*!< Clock gate name: Wwdt. */
182 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U), /*!< Clock gate name: Iocon. */
183 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U), /*!< Clock gate name: Acmp. */
184 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 21U), /*!< Clock gate name: I2c1. */
185 kCLOCK_I2c2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 22U), /*!< Clock gate name: I2c2. */
186 kCLOCK_I2c3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 23U), /*!< Clock gate name: I2c3. */
187 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 24U), /*!< Clock gate name: Adc. */
188 kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 26U), /*!< Clock gate name: Mtb. */
189 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 29U), /*!< Clock gate name: Dma. */
190 } clock_ip_name_t;
191
192 /*! @brief Clock name used to get clock frequency. */
193 typedef enum _clock_name
194 {
195 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
196 kCLOCK_MainClk, /*!< Main clock */
197 kCLOCK_SysOsc, /*!< Crystal Oscillator */
198 kCLOCK_Irc, /*!< IRC12M */
199 kCLOCK_ExtClk, /*!< External Clock */
200 kCLOCK_PllOut, /*!< PLL Output */
201 kCLOCK_Pllin, /*!< PLL Input */
202 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
203 } clock_name_t;
204
205 /*! @brief Clock Mux Switches
206 *CLK_MUX_DEFINE(reg, mux)
207 *reg is used to define the mux register
208 *mux is used to define the mux value
209 *
210 */
211 typedef enum _clock_select
212 {
213
214 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U), /*!< Mux SYSPLL from Irc. */
215
216 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U), /*!< Mux SYSPLL from SysOsc. */
217
218 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U), /*!< Mux SYSPLL from ExtClk. */
219
220 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U), /*!< Mux MAINCLK from Irc. */
221
222 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U), /*!< Mux MAINCLK from SysPllIn. */
223
224 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U), /*!< Mux MAINCLK from WdtOsc. */
225
226 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U), /*!< Mux MAINCLK from SysPll. */
227
228 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Irc. */
229
230 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from SysOsc. */
231
232 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U), /*!< Mux CLKOUT from WdtOsc. */
233
234 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U) /*!< Mux clock out from Main clock. */
235 } clock_select_t;
236
237 /*! @brief Clock divider
238 */
239 typedef enum _clock_divider
240 {
241
242 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV), /*!< Usart Clock Divider. */
243
244 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), /*!< Clk Out Divider. */
245
246 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV), /*!< Uart Frg Divider. */
247
248 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6), /*!< IOCON Clock Div6 Divider. */
249
250 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5), /*!< IOCON Clock Div5 Divider. */
251
252 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4), /*!< IOCON Clock Div4 Divider. */
253
254 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3), /*!< IOCON Clock Div3 Divider. */
255
256 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2), /*!< IOCON Clock Div2 Divider. */
257
258 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1), /*!< IOCON Clock Div1 Divider. */
259
260 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0), /*!< IOCON Clock Div0 Divider. */
261
262 } clock_divider_t;
263
264 /*! @brief watch dog analog output frequency */
265 typedef enum _clock_wdt_analog_freq
266 {
267 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U), /*!< Watch dog analog output frequency is 0HZ. */
268
269 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U), /*!< Watch dog analog output frequency is 600KHZ. */
270
271 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u), /*!< Watch dog analog output frequency is 1050KHZ. */
272
273 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U), /*!< Watch dog analog output frequency is 1400KHZ. */
274
275 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U), /*!< Watch dog analog output frequency is 1750KHZ. */
276
277 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U), /*!< Watch dog analog output frequency is 2100KHZ. */
278
279 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U), /*!< Watch dog analog output frequency is 2400KHZ. */
280
281 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U), /*!< Watch dog analog output frequency is 2700KHZ. */
282
283 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U), /*!< Watch dog analog output frequency is 3000KHZ. */
284
285 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U), /*!< Watch dog analog output frequency is 3250KHZ. */
286
287 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U), /*!< Watch dog analog output frequency is 3500KHZ. */
288
289 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U), /*!< Watch dog analog output frequency is 3750KHZ. */
290
291 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U), /*!< Watch dog analog output frequency is 4000KHZ. */
292
293 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U), /*!< Watch dog analog output frequency is 4200KHZ. */
294
295 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U), /*!< Watch dog analog output frequency is 4400KHZ. */
296
297 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U), /*!< Watch dog analog output frequency is 4600KHZ. */
298
299 } clock_wdt_analog_freq_t;
300
301 /*! @brief PLL clock definition.*/
302 typedef enum _clock_sys_pll_src
303 {
304 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
305 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
306 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
307 } clock_sys_pll_src;
308
309 /*! @brief Main clock source definition */
310 typedef enum _clock_main_clk_src
311 {
312 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
313 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
314 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
315 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
316 } clock_main_clk_src_t;
317
318 /*! @brief PLL configuration structure */
319 typedef struct _clock_sys_pll
320 {
321 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
322 clock_sys_pll_src src; /*!< System pll clock source */
323 } clock_sys_pll_t;
324
325 /*******************************************************************************
326 * API
327 ******************************************************************************/
328
329 #if defined(__cplusplus)
330 extern "C" {
331 #endif /* __cplusplus */
332
333 /*!
334 * @name Clock gate, mux, and divider.
335 * @{
336 */
337
338 /*
339 *! @brief enable ip clock.
340 *
341 * @param clk clock ip definition.
342 */
CLOCK_EnableClock(clock_ip_name_t clk)343 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
344 {
345 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
346 }
347
348 /*
349 *!@brief disable ip clock.
350 *
351 * @param clk clock ip definition.
352 */
CLOCK_DisableClock(clock_ip_name_t clk)353 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
354 {
355 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
356 }
357
358 /*
359 *! @brief Configure the clock selection muxes.
360 * @param mux : Clock to be configured.
361 * @return Nothing
362 */
CLOCK_Select(clock_select_t sel)363 static inline void CLOCK_Select(clock_select_t sel)
364 {
365 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
366 }
367
368 /*
369 *! @brief Setup peripheral clock dividers.
370 * @param name : Clock divider name
371 * @param value: Value to be divided
372 * @return Nothing
373 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)374 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
375 {
376 CLK_DIV_GET_REG(name) = value & 0xFFU;
377 }
378
379 /*
380 *! @brief Get peripheral clock dividers.
381 * @param name : Clock divider name
382 * @return clock divider value
383 */
CLOCK_GetClkDivider(clock_divider_t name)384 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
385 {
386 return CLK_DIV_GET_REG(name) & 0xFFU;
387 }
388
389 /*
390 *! @brief Setup Core clock dividers.
391 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
392 * @param value: Value to be divided
393 * @return Nothing
394 */
CLOCK_SetCoreSysClkDiv(uint32_t value)395 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
396 {
397 assert(value != 0U);
398
399 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
400 }
401
402 /*! @brief Set main clock reference source.
403 * @param src, reference clock_main_clk_src_t to set the main clock source.
404 */
405 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
406
407 /*
408 *! @brief Set Fractional generator 0 multiplier value.
409 * @param mul : FRG0 multiplier value.
410 * @return Nothing
411 */
CLOCK_SetFRGClkMul(uint32_t mul)412 static inline void CLOCK_SetFRGClkMul(uint32_t mul)
413 {
414 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
415 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
416 }
417 /* @} */
418
419 /*!
420 * @name Get frequency
421 * @{
422 */
423
424 /*! @brief Return Frequency of Main Clock.
425 * @return Frequency of Main Clock.
426 */
427 uint32_t CLOCK_GetMainClkFreq(void);
428
429 /*! @brief Return Frequency of core.
430 * @return Frequency of core.
431 */
CLOCK_GetCoreSysClkFreq(void)432 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
433 {
434 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
435 }
436
437 /*! @brief Return Frequency of ClockOut
438 * @return Frequency of ClockOut
439 */
440 uint32_t CLOCK_GetClockOutClkFreq(void);
441
442 /*! @brief Return Frequency of IRC
443 * @return Frequency of IRC
444 */
445 uint32_t CLOCK_GetIrcFreq(void);
446
447 /*! @brief Return Frequency of SYSOSC
448 * @return Frequency of SYSOSC
449 */
450 uint32_t CLOCK_GetSysOscFreq(void);
451
452 /*! @brief Get UART0 frequency
453 * @retval UART0 frequency value.
454 */
455 uint32_t CLOCK_GetUartClkFreq(void);
456
457 /*! @brief Get UART0 frequency
458 * @retval UART0 frequency value.
459 */
460 uint32_t CLOCK_GetUart0ClkFreq(void);
461
462 /*! @brief Get UART1 frequency
463 * @retval UART1 frequency value.
464 */
465 uint32_t CLOCK_GetUart1ClkFreq(void);
466
467 /*! @brief Get UART2 frequency
468 * @retval UART2 frequency value.
469 */
470 uint32_t CLOCK_GetUart2ClkFreq(void);
471
472 /*! @brief Return Frequency of selected clock
473 * @return Frequency of selected clock
474 */
475 uint32_t CLOCK_GetFreq(clock_name_t clockName);
476
477 /*! @brief Return System PLL input clock rate
478 * @return System PLL input clock rate
479 */
480 uint32_t CLOCK_GetSystemPLLInClockRate(void);
481
482 /*! @brief Return Frequency of System PLL
483 * @return Frequency of PLL
484 */
CLOCK_GetSystemPLLFreq(void)485 static inline uint32_t CLOCK_GetSystemPLLFreq(void)
486 {
487 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
488 }
489
490 /*! @brief Get watch dog OSC frequency
491 * @retval watch dog OSC frequency value.
492 */
CLOCK_GetWdtOscFreq(void)493 static inline uint32_t CLOCK_GetWdtOscFreq(void)
494 {
495 return g_Wdt_Osc_Freq;
496 }
497
498 /*! @brief Get external clock frequency
499 * @retval external clock frequency value.
500 */
CLOCK_GetExtClkFreq(void)501 static inline uint32_t CLOCK_GetExtClkFreq(void)
502 {
503 return g_Ext_Clk_Freq;
504 }
505 /* @} */
506
507 /*!
508 * @name PLL operations
509 * @{
510 */
511
512 /*! @brief System PLL initialize.
513 * @param config System PLL configurations.
514 */
515 void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
516
517 /*! @brief System PLL Deinitialize.*/
CLOCK_DenitSystemPll(void)518 static inline void CLOCK_DenitSystemPll(void)
519 {
520 /* Power off PLL */
521 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
522 }
523
524 /* @} */
525
526 /*!
527 * @name External/internal oscillator clock operations
528 * @{
529 */
530
531 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
532 * @param clkInFreq external clock in frequency.
533 */
534 void CLOCK_InitExtClkin(uint32_t clkInFreq);
535
536 /*! @brief Init SYS OSC
537 * @param oscFreq oscillator frequency value.
538 */
539 void CLOCK_InitSysOsc(uint32_t oscFreq);
540
541 /*! @brief XTALIN init function
542 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
543 * @param xtalInFreq XTALIN frequency value
544 * @return Frequency of PLL
545 */
546 void CLOCK_InitXtalin(uint32_t xtalInFreq);
547
548 /*! @brief Deinit SYS OSC
549 * @param config oscillator configuration.
550 */
CLOCK_DeinitSysOsc(void)551 static inline void CLOCK_DeinitSysOsc(void)
552 {
553 /* Deinit system osc power */
554 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
555 }
556
557 /*! @brief Init watch dog OSC
558 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
559 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
560 * consumption. If accurate timing is required, use the FRO or system oscillator.
561 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
562 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
563 * using the watchdog oscillator.
564 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
565 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
566 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
567 */
568 void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
569
570 /*! @brief Deinit watch dog OSC
571 * @param config oscillator configuration.
572 */
CLOCK_DeinitWdtOsc(void)573 static inline void CLOCK_DeinitWdtOsc(void)
574 {
575 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
576 }
577
578 /*! @brief Set UARTFRG
579 * @param target UART clock src.
580 */
581 bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
582
583 /*! @brief updates the clock source of the CLKOUT
584 */
585 void CLOCK_UpdateClkOUTsrc(void);
586
587 /*! @brief Set UARTFRGMULT
588 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
589 * @param UARTFRGMULT.
590 */
CLOCK_SetUARTFRGMULT(uint32_t mul)591 static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
592 {
593 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
594 }
595
596 /* @} */
597
598 #if defined(__cplusplus)
599 }
600 #endif /* __cplusplus */
601
602 /*! @} */
603
604 #endif /* _FSL_CLOCK_H_ */
605
