1 /*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.4.2. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31 #endif
32
33 /*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38 extern volatile uint32_t g_Wdt_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern volatile uint32_t g_Ext_Clk_Freq;
49
50 /*! @brief Clock ip name array for ADC. */
51 #define ADC_CLOCKS \
52 { \
53 kCLOCK_Adc, \
54 }
55 /*! @brief Clock ip name array for ACMP. */
56 #define ACMP_CLOCKS \
57 { \
58 kCLOCK_Acmp, \
59 }
60 /*! @brief Clock ip name array for SWM. */
61 #define SWM_CLOCKS \
62 { \
63 kCLOCK_Swm, \
64 }
65 /*! @brief Clock ip name array for ROM. */
66 #define ROM_CLOCKS \
67 { \
68 kCLOCK_Rom, \
69 }
70 /*! @brief Clock ip name array for SRAM. */
71 #define SRAM_CLOCKS \
72 { \
73 kCLOCK_Ram0_1, \
74 }
75 /*! @brief Clock ip name array for IOCON. */
76 #define IOCON_CLOCKS \
77 { \
78 kCLOCK_Iocon, \
79 }
80 /*! @brief Clock ip name array for GPIO. */
81 #define GPIO_CLOCKS \
82 { \
83 kCLOCK_Gpio0, \
84 }
85 /*! @brief Clock ip name array for GPIO_INT. */
86 #define GPIO_INT_CLOCKS \
87 { \
88 kCLOCK_GpioInt, \
89 }
90 /*! @brief Clock ip name array for DMA. */
91 #define DMA_CLOCKS \
92 { \
93 kCLOCK_Dma, \
94 }
95 /*! @brief Clock ip name array for CRC. */
96 #define CRC_CLOCKS \
97 { \
98 kCLOCK_Crc, \
99 }
100 /*! @brief Clock ip name array for WWDT. */
101 #define WWDT_CLOCKS \
102 { \
103 kCLOCK_Wwdt, \
104 }
105 /*! @brief Clock ip name array for SCT0. */
106 #define SCT_CLOCKS \
107 { \
108 kCLOCK_Sct, \
109 }
110 /*! @brief Clock ip name array for I2C. */
111 #define I2C_CLOCKS \
112 { \
113 kCLOCK_I2c0, \
114 }
115 /*! @brief Clock ip name array for I2C. */
116 #define USART_CLOCKS \
117 { \
118 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
119 }
120 /*! @brief Clock ip name array for SPI. */
121 #define SPI_CLOCKS \
122 { \
123 kCLOCK_Spi0, kCLOCK_Spi1, \
124 }
125 /*! @brief Clock ip name array for MTB. */
126 #define MTB_CLOCKS \
127 { \
128 kCLOCK_Mtb, \
129 }
130 /*! @brief Clock ip name array for MRT. */
131 #define MRT_CLOCKS \
132 { \
133 kCLOCK_Mrt, \
134 }
135 /*! @brief Clock ip name array for WKT. */
136 #define WKT_CLOCKS \
137 { \
138 kCLOCK_Wkt, \
139 }
140
141 /*! @brief Internal used Clock definition only. */
142 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
143 #define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
144 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
145 /* clock mux register definition */
146 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
147 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
148 #define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
149 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
150 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
151 #define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
152 /* clock divider register definition */
153 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
154 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
155 /* watch dog oscillator definition */
156 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
157 #define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)(x)&0xFFFFFFU)
158 #define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
159 /* register offset */
160 #define SYS_AHB_CLK_CTRL (0U)
161 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
162 typedef enum _clock_ip_name
163 {
164 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U),
165 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U),
166 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U),
167 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U),
168 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U),
169 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U),
170 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U),
171 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U),
172 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U),
173 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U),
174 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U),
175 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U),
176 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U),
177 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U),
178 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U),
179 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U),
180 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U),
181 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U),
182 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U),
183 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U),
184 } clock_ip_name_t;
185
186 /*! @brief Clock name used to get clock frequency. */
187 typedef enum _clock_name
188 {
189 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
190 kCLOCK_MainClk, /*!< Main clock */
191 kCLOCK_SysOsc, /*!< Crystal Oscillator */
192 kCLOCK_Irc, /*!< IRC12M */
193 kCLOCK_ExtClk, /*!< External Clock */
194 kCLOCK_PllOut, /*!< PLL Output */
195 kCLOCK_Pllin, /*!< PLL Input */
196 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
197 } clock_name_t;
198
199 /*! @brief Clock Mux Switches
200 *CLK_MUX_DEFINE(reg, mux)
201 *reg is used to define the mux register
202 *mux is used to define the mux value
203 *
204 */
205 typedef enum _clock_select
206 {
207
208 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U),
209 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U),
210 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U),
211
212 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U),
213 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U),
214 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U),
215 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U),
216
217 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
218 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
219 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
220 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U)
221 } clock_select_t;
222
223 /*! @brief Clock divider
224 */
225 typedef enum _clock_divider
226 {
227
228 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV),
229 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
230 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV),
231
232 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
233 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
234 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
235 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
236 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
237 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
238 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
239
240 } clock_divider_t;
241
242 /*! @brief watch dog analog output frequency */
243 typedef enum _clock_wdt_analog_freq
244 {
245 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
246 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
247 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
248 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
249 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
250 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
251 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
252 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
253 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
254 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
255 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
256 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
257 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
258 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
259 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
260 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
261 } clock_wdt_analog_freq_t;
262
263 /*! @brief PLL clock definition.*/
264 typedef enum _clock_sys_pll_src
265 {
266 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
267 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
268 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
269 } clock_sys_pll_src;
270
271 /*! @brief Main clock source definition */
272 typedef enum _clock_main_clk_src
273 {
274 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
275 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
276 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
277 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
278 } clock_main_clk_src_t;
279
280 /*! @brief PLL configuration structure */
281 typedef struct _clock_sys_pll
282 {
283 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
284 clock_sys_pll_src src; /*!< System pll clock source */
285 } clock_sys_pll_t;
286
287 /*******************************************************************************
288 * API
289 ******************************************************************************/
290
291 #if defined(__cplusplus)
292 extern "C" {
293 #endif /* __cplusplus */
294
295 /*!
296 * @name Clock gate, mux, and divider.
297 * @{
298 */
299
300 /*
301 *! @brief enable ip clock.
302 *
303 * @param clk clock ip definition.
304 */
CLOCK_EnableClock(clock_ip_name_t clk)305 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
306 {
307 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
308 }
309
310 /*
311 *!@brief disable ip clock.
312 *
313 * @param clk clock ip definition.
314 */
CLOCK_DisableClock(clock_ip_name_t clk)315 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
316 {
317 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
318 }
319
320 /*
321 *! @brief Configure the clock selection muxes.
322 * @param mux : Clock to be configured.
323 * @return Nothing
324 */
CLOCK_Select(clock_select_t sel)325 static inline void CLOCK_Select(clock_select_t sel)
326 {
327 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
328 }
329
330 /*
331 *! @brief Setup peripheral clock dividers.
332 * @param name : Clock divider name
333 * @param value: Value to be divided
334 * @return Nothing
335 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)336 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
337 {
338 CLK_DIV_GET_REG(name) = value & 0xFFU;
339 }
340
341 /*
342 *! @brief Get peripheral clock dividers.
343 * @param name : Clock divider name
344 * @return clock divider value
345 */
CLOCK_GetClkDivider(clock_divider_t name)346 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
347 {
348 return CLK_DIV_GET_REG(name) & 0xFFU;
349 }
350
351 /*
352 *! @brief Setup Core clock dividers.
353 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
354 * @param value: Value to be divided
355 * @return Nothing
356 */
CLOCK_SetCoreSysClkDiv(uint32_t value)357 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
358 {
359 assert(value != 0U);
360
361 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
362 }
363
364 /*! @brief Set main clock reference source.
365 * @param src Refer to clock_main_clk_src_t to set the main clock source.
366 */
367 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
368
369 /*
370 *! @brief Set Fractional generator 0 multiplier value.
371 * @param mul : FRG0 multiplier value.
372 * @return Nothing
373 */
CLOCK_SetFRGClkMul(uint32_t mul)374 static inline void CLOCK_SetFRGClkMul(uint32_t mul)
375 {
376 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
377 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
378 }
379 /* @} */
380
381 /*!
382 * @name Get frequency
383 * @{
384 */
385
386 /*! @brief Return Frequency of Main Clock.
387 * @return Frequency of Main Clock.
388 */
389 uint32_t CLOCK_GetMainClkFreq(void);
390
391 /*! @brief Return Frequency of core.
392 * @return Frequency of core.
393 */
CLOCK_GetCoreSysClkFreq(void)394 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
395 {
396 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
397 }
398
399 /*! @brief Return Frequency of ClockOut
400 * @return Frequency of ClockOut
401 */
402 uint32_t CLOCK_GetClockOutClkFreq(void);
403
404 /*! @brief Return Frequency of IRC
405 * @return Frequency of IRC
406 */
407 uint32_t CLOCK_GetIrcFreq(void);
408
409 /*! @brief Return Frequency of SYSOSC
410 * @return Frequency of SYSOSC
411 */
412 uint32_t CLOCK_GetSysOscFreq(void);
413
414 /*! @brief Get UART0 frequency
415 * @retval UART0 frequency value.
416 */
417 uint32_t CLOCK_GetUartClkFreq(void);
418
419 /*! @brief Get UART0 frequency
420 * @retval UART0 frequency value.
421 */
422 uint32_t CLOCK_GetUart0ClkFreq(void);
423
424 /*! @brief Get UART1 frequency
425 * @retval UART1 frequency value.
426 */
427 uint32_t CLOCK_GetUart1ClkFreq(void);
428
429 /*! @brief Get UART2 frequency
430 * @retval UART2 frequency value.
431 */
432 uint32_t CLOCK_GetUart2ClkFreq(void);
433
434 /*! @brief Return Frequency of selected clock
435 * @return Frequency of selected clock
436 */
437 uint32_t CLOCK_GetFreq(clock_name_t clockName);
438
439 /*! @brief Return System PLL input clock rate
440 * @return System PLL input clock rate
441 */
442 uint32_t CLOCK_GetSystemPLLInClockRate(void);
443
444 /*! @brief Return Frequency of System PLL
445 * @return Frequency of PLL
446 */
CLOCK_GetSystemPLLFreq(void)447 static inline uint32_t CLOCK_GetSystemPLLFreq(void)
448 {
449 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
450 }
451
452 /*! @brief Get watch dog OSC frequency
453 * @retval watch dog OSC frequency value.
454 */
CLOCK_GetWdtOscFreq(void)455 static inline uint32_t CLOCK_GetWdtOscFreq(void)
456 {
457 return g_Wdt_Osc_Freq;
458 }
459
460 /*! @brief Get external clock frequency
461 * @retval external clock frequency value.
462 */
CLOCK_GetExtClkFreq(void)463 static inline uint32_t CLOCK_GetExtClkFreq(void)
464 {
465 return g_Ext_Clk_Freq;
466 }
467 /* @} */
468
469 /*!
470 * @name PLL operations
471 * @{
472 */
473
474 /*! @brief System PLL initialize.
475 * @param config System PLL configurations.
476 */
477 void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
478
479 /*! @brief System PLL Deinitialize.*/
CLOCK_DenitSystemPll(void)480 static inline void CLOCK_DenitSystemPll(void)
481 {
482 /* Power off PLL */
483 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
484 }
485
486 /* @} */
487
488 /*!
489 * @name External/internal oscillator clock operations
490 * @{
491 */
492
493 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
494 * @param clkInFreq external clock in frequency.
495 */
496 void CLOCK_InitExtClkin(uint32_t clkInFreq);
497
498 /*! @brief Init SYS OSC
499 * @param oscFreq oscillator frequency value.
500 */
501 void CLOCK_InitSysOsc(uint32_t oscFreq);
502
503 /*! @brief XTALIN init function
504 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
505 * @param xtalInFreq XTALIN frequency value
506 * @return Frequency of PLL
507 */
508 void CLOCK_InitXtalin(uint32_t xtalInFreq);
509
510 /*! @brief Deinit SYS OSC */
CLOCK_DeinitSysOsc(void)511 static inline void CLOCK_DeinitSysOsc(void)
512 {
513 /* Deinit system osc power */
514 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
515 }
516
517 /*! @brief Init watch dog OSC
518 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
519 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
520 * consumption. If accurate timing is required, use the FRO or system oscillator.
521 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
522 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
523 * using the watchdog oscillator.
524 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
525 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
526 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
527 */
528 void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
529
530 /*! @brief Deinit watch dog OSC */
CLOCK_DeinitWdtOsc(void)531 static inline void CLOCK_DeinitWdtOsc(void)
532 {
533 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
534 }
535
536 /*! @brief Set UARTFRG
537 * @param freq The frequency specified by src.
538 */
539 bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
540
541 /*! @brief Set UARTFRGMULT
542 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
543 * @param mul UARTFRGMULT.
544 */
CLOCK_SetUARTFRGMULT(uint32_t mul)545 static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
546 {
547 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
548 }
549
550 /*! @brief Update CLKOUT src */
551 void CLOCK_UpdateClkOUTsrc(void);
552
553 /* @} */
554
555 #if defined(__cplusplus)
556 }
557 #endif /* __cplusplus */
558
559 /*! @} */
560
561 #endif /* _FSL_CLOCK_H_ */
562
