1 /*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kSPI0_RST_N_SHIFT_RSTn = 0 | 0U, /**< SPI0 reset control. */
40 kSPI1_RST_N_SHIFT_RSTn = 0 | 1U, /**< SPI1 reset control */
41 kUARTFRG_RST_N_SHIFT_RSTn = 0 | 2U, /**< UARTFRG reset control */
42 kUART0_RST_N_SHIFT_RSTn = 0 | 3U, /**< UART0 reset control */
43 kUART1_RST_N_SHIFT_RSTn = 0 | 4U, /**< UART1 reset control */
44 kUART2_RST_N_SHIFT_RSTn = 0 | 5U, /**< UART2 reset control */
45 kI2C0_RST_N_SHIFT_RSTn = 0 | 6U, /**< I2C0 reset control */
46 kMRT_RST_N_SHIFT_RSTn = 0 | 7U, /**< Multi-rate timer(MRT) reset control */
47 kSCT_RST_N_SHIFT_RSTn = 0 | 8U, /**< SCT reset control */
48 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
49 kGPIO0_RST_N_SHIFT_RSTn = 0 | 10U, /**< GPIO0 reset control */
50 kFLASH_RST_N_SHIFT_RSTn = 0 | 11U, /**< Flash controller reset control */
51 kACMP_RST_N_SHIFT_RSTn = 0 | 12U, /**< Analog comparator reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
53 kI2C1_RST_N_SHIFT_RSTn = 0 | 14U, /**< I2C1 reset control */
54 kI2C2_RST_N_SHIFT_RSTn = 0 | 15U, /**< I2C2 reset control */
55 kI2C3_RST_N_SHIFT_RSTn = 0 | 16U, /**< I2C3 reset control */
56 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
57 kDMA_RST_N_SHIFT_RSTn = 0 | 29U, /**< DMA reset control */
58
59 } SYSCON_RSTn_t;
60
61 /** Array initializers with peripheral reset bits **/
62 #define FLASH_RSTS_N \
63 { \
64 kFLASH_RST_N_SHIFT_RSTn \
65 } /* Reset bits for Flash peripheral */
66 #define I2C_RSTS_N \
67 { \
68 kI2C0_RST_N_SHIFT_RSTn, kI2C1_RST_N_SHIFT_RSTn, kI2C2_RST_N_SHIFT_RSTn, kI2C3_RST_N_SHIFT_RSTn \
69 } /* Reset bits for I2C peripheral */
70 #define GPIO_RSTS_N \
71 { \
72 kGPIO0_RST_N_SHIFT_RSTn \
73 } /* Reset bits for GPIO peripheral */
74 #define SWM_RSTS_N \
75 { \
76 kSWM_RST_N_SHIFT_RSTn \
77 } /* Reset bits for SWM peripheral */
78 #define SCT_RSTS_N \
79 { \
80 kSCT_RST_N_SHIFT_RSTn \
81 } /* Reset bits for SCT peripheral */
82 #define WKT_RSTS_N \
83 { \
84 kWKT_RST_N_SHIFT_RSTn \
85 } /* Reset bits for WKT peripheral */
86 #define MRT_RSTS_N \
87 { \
88 kMRT_RST_N_SHIFT_RSTn \
89 } /* Reset bits for MRT peripheral */
90 #define SPI_RSTS_N \
91 { \
92 kSPI0_RST_N_SHIFT_RSTn, kSPI1_RST_N_SHIFT_RSTn \
93 } /* Reset bits for SPI peripheral */
94 #define UART_RSTS_N \
95 { \
96 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn, kUART2_RST_N_SHIFT_RSTn \
97 } /* Reset bits for UART peripheral */
98 #define ACMP_RSTS_N \
99 { \
100 kACMP_RST_N_SHIFT_RSTn \
101 } /* Reset bits for ACMP peripheral */
102 #define ADC_RSTS_N \
103 { \
104 kADC_RST_N_SHIFT_RSTn \
105 } /* Reset bits for ADC peripheral */
106 #define DAC_RSTS_N \
107 { \
108 kDAC0_RST_N_SHIFT_RSTn, kDAC1_RST_N_SHIFT_RSTn \
109 } /* Reset bits for DAC peripheral */
110 #define DMA_RSTS_N \
111 { \
112 kDMA_RST_N_SHIFT_RSTn \
113 } /* Reset bits for DMA peripheral */
114
115 typedef SYSCON_RSTn_t reset_ip_name_t;
116
117 /*******************************************************************************
118 * API
119 ******************************************************************************/
120 #if defined(__cplusplus)
121 extern "C" {
122 #endif
123
124 /*!
125 * @brief Assert reset to peripheral.
126 *
127 * Asserts reset signal to specified peripheral module.
128 *
129 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
130 * and reset bit position in the reset register.
131 */
132 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
133
134 /*!
135 * @brief Clear reset to peripheral.
136 *
137 * Clears reset signal to specified peripheral module, allows it to operate.
138 *
139 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
140 * and reset bit position in the reset register.
141 */
142 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
143
144 /*!
145 * @brief Reset peripheral module.
146 *
147 * Reset peripheral module.
148 *
149 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
150 * and reset bit position in the reset register.
151 */
152 void RESET_PeripheralReset(reset_ip_name_t peripheral);
153
154 /*!
155 * @brief Release peripheral module.
156 *
157 * Release peripheral module.
158 *
159 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
160 * and reset bit position in the reset register.
161 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)162 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
163 {
164 RESET_ClearPeripheralReset(peripheral);
165 }
166
167 #if defined(__cplusplus)
168 }
169 #endif
170
171 /*! @} */
172
173 #endif /* _FSL_RESET_H_ */
174
