1 /*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.4.2. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31 #endif
32
33 /*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38 extern uint32_t g_Wdt_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern uint32_t g_Ext_Clk_Freq;
49
50 extern uint32_t g_Sys_Pll_Freq;
51
52 /*! @brief Clock ip name array for ADC. */
53 #define ADC_CLOCKS \
54 { \
55 kCLOCK_Adc, \
56 }
57 /*! @brief Clock ip name array for ACMP. */
58 #define ACMP_CLOCKS \
59 { \
60 kCLOCK_Acmp, \
61 }
62 /*! @brief Clock ip name array for SWM. */
63 #define SWM_CLOCKS \
64 { \
65 kCLOCK_Swm, \
66 }
67 /*! @brief Clock ip name array for ROM. */
68 #define ROM_CLOCKS \
69 { \
70 kCLOCK_Rom, \
71 }
72 /*! @brief Clock ip name array for SRAM. */
73 #define SRAM_CLOCKS \
74 { \
75 kCLOCK_Ram0_1, \
76 }
77 /*! @brief Clock ip name array for IOCON. */
78 #define IOCON_CLOCKS \
79 { \
80 kCLOCK_Iocon, \
81 }
82 /*! @brief Clock ip name array for GPIO. */
83 #define GPIO_CLOCKS \
84 { \
85 kCLOCK_Gpio0, \
86 }
87 /*! @brief Clock ip name array for GPIO_INT. */
88 #define GPIO_INT_CLOCKS \
89 { \
90 kCLOCK_GpioInt, \
91 }
92 /*! @brief Clock ip name array for DMA. */
93 #define DMA_CLOCKS \
94 { \
95 kCLOCK_Dma, \
96 }
97 /*! @brief Clock ip name array for CRC. */
98 #define CRC_CLOCKS \
99 { \
100 kCLOCK_Crc, \
101 }
102 /*! @brief Clock ip name array for WWDT. */
103 #define WWDT_CLOCKS \
104 { \
105 kCLOCK_Wwdt, \
106 }
107 /*! @brief Clock ip name array for SCT0. */
108 #define SCT_CLOCKS \
109 { \
110 kCLOCK_Sct, \
111 }
112 /*! @brief Clock ip name array for I2C. */
113 #define I2C_CLOCKS \
114 { \
115 kCLOCK_I2c0, \
116 }
117 /*! @brief Clock ip name array for I2C. */
118 #define USART_CLOCKS \
119 { \
120 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
121 }
122 /*! @brief Clock ip name array for SPI. */
123 #define SPI_CLOCKS \
124 { \
125 kCLOCK_Spi0, kCLOCK_Spi1, \
126 }
127 /*! @brief Clock ip name array for MTB. */
128 #define MTB_CLOCKS \
129 { \
130 kCLOCK_Mtb, \
131 }
132 /*! @brief Clock ip name array for MRT. */
133 #define MRT_CLOCKS \
134 { \
135 kCLOCK_Mrt, \
136 }
137 /*! @brief Clock ip name array for WKT. */
138 #define WKT_CLOCKS \
139 { \
140 kCLOCK_Wkt, \
141 }
142
143 /*! @brief Internal used Clock definition only. */
144 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
145 #define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
146 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
147 /* clock mux register definition */
148 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
149 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
150 #define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
151 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
152 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) ((((uint32_t)(x)) >> 8U) & 0xFFU)
153 #define CLK_MAIN_CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
154 /* clock divider register definition */
155 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
156 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
157 /* watch dog oscillator definition */
158 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
159 #define CLK_WDT_OSC_GET_FREQ(x) (((uint32_t)(x)) & 0xFFFFFFU)
160 #define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
161 /* register offset */
162 #define SYS_AHB_CLK_CTRL (0U)
163 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
164 typedef enum _clock_ip_name
165 {
166 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 0U),
167 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 1U),
168 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 2U),
169 kCLOCK_Flashreg = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 3U),
170 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 4U),
171 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 5U),
172 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 6U),
173 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 7U),
174 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 8U),
175 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 9U),
176 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 10U),
177 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 11U),
178 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 12U),
179 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 13U),
180 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 14U),
181 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 15U),
182 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 16U),
183 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 17U),
184 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 18U),
185 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL, 19U),
186 } clock_ip_name_t;
187
188 /*! @brief Clock name used to get clock frequency. */
189 typedef enum _clock_name
190 {
191 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
192 kCLOCK_MainClk, /*!< Main clock */
193 kCLOCK_SysOsc, /*!< Crystal Oscillator */
194 kCLOCK_Irc, /*!< IRC12M */
195 kCLOCK_ExtClk, /*!< External Clock */
196 kCLOCK_PllOut, /*!< PLL Output */
197 kCLOCK_Pllin, /*!< PLL Input */
198 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
199 } clock_name_t;
200
201 /*! @brief Clock Mux Switches
202 *CLK_MUX_DEFINE(reg, mux)
203 *reg is used to define the mux register
204 *mux is used to define the mux value
205 *
206 */
207 typedef enum _clock_select
208 {
209
210 kSYSPLL_From_Irc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 0U),
211 kSYSPLL_From_SysOsc = CLK_MUX_DEFINE(SYSPLLCLKSEL, 1U),
212 kSYSPLL_From_ExtClk = CLK_MUX_DEFINE(SYSPLLCLKSEL, 3U),
213
214 kMAINCLK_From_Irc = CLK_MUX_DEFINE(MAINCLKSEL, 0U),
215 kMAINCLK_From_SysPllIn = CLK_MUX_DEFINE(MAINCLKSEL, 1U),
216 kMAINCLK_From_WdtOsc = CLK_MUX_DEFINE(MAINCLKSEL, 2U),
217 kMAINCLK_From_SysPll = CLK_MUX_DEFINE(MAINCLKSEL, 3U),
218
219 kCLKOUT_From_Irc = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
220 kCLKOUT_From_SysOsc = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
221 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
222 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U)
223 } clock_select_t;
224
225 /*! @brief Clock divider
226 */
227 typedef enum _clock_divider
228 {
229
230 kCLOCK_DivUsartClk = CLK_DIV_DEFINE(UARTCLKDIV),
231 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
232 kCLOCK_DivUartFrg = CLK_DIV_DEFINE(UARTFRGDIV),
233
234 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
235 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
236 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
237 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
238 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
239 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
240 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
241
242 } clock_divider_t;
243
244 /*! @brief watch dog analog output frequency */
245 typedef enum _clock_wdt_analog_freq
246 {
247 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
248 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
249 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
250 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
251 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
252 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
253 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
254 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
255 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
256 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
257 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
258 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
259 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
260 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
261 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
262 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
263 } clock_wdt_analog_freq_t;
264
265 /*! @brief PLL clock definition.*/
266 typedef enum _clock_sys_pll_src
267 {
268 kCLOCK_SysPllSrcIrc = 0U, /*!< system pll source from FRO */
269 kCLOCK_SysPllSrcSysosc = 1U, /*!< system pll source from system osc */
270 kCLOCK_SysPllSrcExtClk = 3U, /*!< system pll source from ext clkin */
271 } clock_sys_pll_src;
272
273 /*!< Main clock source definition */
274 typedef enum _clock_main_clk_src
275 {
276 kCLOCK_MainClkSrcIrc = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
277 kCLOCK_MainClkSrcSysPllin = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from pll input */
278 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
279 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from system pll */
280 } clock_main_clk_src_t;
281
282 /*! @brief PLL configuration structure */
283 typedef struct _clock_sys_pll
284 {
285 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
286 clock_sys_pll_src src; /*!< System pll clock source */
287 } clock_sys_pll_t;
288
289 /*******************************************************************************
290 * API
291 ******************************************************************************/
292
293 #if defined(__cplusplus)
294 extern "C" {
295 #endif /* __cplusplus */
296
297 /*!
298 * @name Clock gate, mux, and divider.
299 * @{
300 */
301
302 /*
303 *! @brief enable ip clock.
304 *
305 * @param clk clock ip definition.
306 */
CLOCK_EnableClock(clock_ip_name_t clk)307 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
308 {
309 SYSCON->SYSAHBCLKCTRL |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
310 }
311
312 /*
313 *!@brief disable ip clock.
314 *
315 * @param clk clock ip definition.
316 */
CLOCK_DisableClock(clock_ip_name_t clk)317 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
318 {
319 SYSCON->SYSAHBCLKCTRL &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
320 }
321
322 /*
323 *! @brief Configure the clock selection muxes.
324 * @param mux : Clock to be configured.
325 * @return Nothing
326 */
CLOCK_Select(clock_select_t sel)327 static inline void CLOCK_Select(clock_select_t sel)
328 {
329 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
330 }
331
332 /*
333 *! @brief Setup peripheral clock dividers.
334 * @param name : Clock divider name
335 * @param value: Value to be divided
336 * @return Nothing
337 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)338 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
339 {
340 CLK_DIV_GET_REG(name) = value & 0xFFU;
341 }
342
343 /*
344 *! @brief Get peripheral clock dividers.
345 * @param name : Clock divider name
346 * @return clock divider value
347 */
CLOCK_GetClkDivider(clock_divider_t name)348 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
349 {
350 return CLK_DIV_GET_REG(name) & 0xFFU;
351 }
352
353 /*
354 *! @brief Setup Core clock dividers.
355 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
356 * @param value: Value to be divided
357 * @return Nothing
358 */
CLOCK_SetCoreSysClkDiv(uint32_t value)359 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
360 {
361 assert(value != 0U);
362
363 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
364 }
365
366 /*! @brief Set main clock reference source.
367 * @param src, reference clock_main_clk_src_t to set the main clock source.
368 */
369 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
370
371 /*
372 *! @brief Set Fractional generator 0 multiplier value.
373 * @param mul : FRG0 multiplier value.
374 * @return Nothing
375 */
CLOCK_SetFRGClkMul(uint32_t mul)376 static inline void CLOCK_SetFRGClkMul(uint32_t mul)
377 {
378 SYSCON->UARTFRGDIV = SYSCON_UARTFRGDIV_DIV_MASK;
379 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
380 }
381 /* @} */
382
383 /*!
384 * @name Get frequency
385 * @{
386 */
387
388 /*! @brief Return Frequency of Main Clock.
389 * @return Frequency of Main Clock.
390 */
391 uint32_t CLOCK_GetMainClkFreq(void);
392
393 /*! @brief Return Frequency of core.
394 * @return Frequency of core.
395 */
CLOCK_GetCoreSysClkFreq(void)396 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
397 {
398 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
399 }
400
401 /*! @brief Return Frequency of ClockOut
402 * @return Frequency of ClockOut
403 */
404 uint32_t CLOCK_GetClockOutClkFreq(void);
405
406 /*! @brief Return Frequency of IRC
407 * @return Frequency of IRC
408 */
409 uint32_t CLOCK_GetIrcFreq(void);
410
411 /*! @brief Return Frequency of SYSOSC
412 * @return Frequency of SYSOSC
413 */
414 uint32_t CLOCK_GetSysOscFreq(void);
415
416 /*! @brief Get UART0 frequency
417 * @retval UART0 frequency value.
418 */
419 uint32_t CLOCK_GetUartClkFreq(void);
420
421 /*! @brief Get UART0 frequency
422 * @retval UART0 frequency value.
423 */
424 uint32_t CLOCK_GetUart0ClkFreq(void);
425
426 /*! @brief Get UART1 frequency
427 * @retval UART1 frequency value.
428 */
429 uint32_t CLOCK_GetUart1ClkFreq(void);
430
431 /*! @brief Get UART2 frequency
432 * @retval UART2 frequency value.
433 */
434 uint32_t CLOCK_GetUart2ClkFreq(void);
435
436 /*! @brief Return Frequency of selected clock
437 * @return Frequency of selected clock
438 */
439 uint32_t CLOCK_GetFreq(clock_name_t clockName);
440
441 /*! @brief Return System PLL input clock rate
442 * @return System PLL input clock rate
443 */
444 uint32_t CLOCK_GetSystemPLLInClockRate(void);
445
446 /*! @brief Return Frequency of System PLL
447 * @return Frequency of PLL
448 */
CLOCK_GetSystemPLLFreq(void)449 static inline uint32_t CLOCK_GetSystemPLLFreq(void)
450 {
451 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
452 }
453
454 /*! @brief Get watch dog OSC frequency
455 * @retval watch dog OSC frequency value.
456 */
CLOCK_GetWdtOscFreq(void)457 static inline uint32_t CLOCK_GetWdtOscFreq(void)
458 {
459 return g_Wdt_Osc_Freq;
460 }
461
462 /*! @brief Get external clock frequency
463 * @retval external clock frequency value.
464 */
CLOCK_GetExtClkFreq(void)465 static inline uint32_t CLOCK_GetExtClkFreq(void)
466 {
467 return g_Ext_Clk_Freq;
468 }
469 /* @} */
470
471 /*!
472 * @name PLL operations
473 * @{
474 */
475
476 /*! @brief System PLL initialize.
477 * @param config System PLL configurations.
478 */
479 void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
480
481 /*! @brief System PLL Deinitialize.*/
CLOCK_DenitSystemPll(void)482 static inline void CLOCK_DenitSystemPll(void)
483 {
484 /* Power off PLL */
485 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
486 }
487
488 /* @} */
489
490 /*!
491 * @name External/internal oscillator clock operations
492 * @{
493 */
494
495 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
496 * @param clkInFreq external clock in frequency.
497 */
498 void CLOCK_InitExtClkin(uint32_t clkInFreq);
499
500 /*! @brief Init SYS OSC
501 * @param oscFreq oscillator frequency value.
502 */
503 void CLOCK_InitSysOsc(uint32_t oscFreq);
504
505 /*! @brief Deinit SYS OSC
506 * @param config oscillator configuration.
507 */
CLOCK_DeinitSysOsc(void)508 static inline void CLOCK_DeinitSysOsc(void)
509 {
510 /* Deinit system osc power */
511 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
512 }
513
514 /*! @brief Init watch dog OSC
515 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
516 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
517 * consumption. If accurate timing is required, use the FRO or system oscillator.
518 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
519 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
520 * using the watchdog oscillator.
521 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
522 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
523 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
524 */
525 void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
526
527 /*! @brief Deinit watch dog OSC
528 * @param config oscillator configuration.
529 */
CLOCK_DeinitWdtOsc(void)530 static inline void CLOCK_DeinitWdtOsc(void)
531 {
532 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
533 }
534
535 /*! @brief Set UARTFRG
536 * @param target UART clock src.
537 */
538 bool CLOCK_SetUARTFRGClkFreq(uint32_t freq);
539
540 /*! @brief Set UARTFRGMULT
541 * @deprecated Do not use this function. Refer to CLOCK_SetFRGClkMul().
542 * @param UARTFRGMULT.
543 */
CLOCK_SetUARTFRGMULT(uint32_t mul)544 static inline void CLOCK_SetUARTFRGMULT(uint32_t mul)
545 {
546 SYSCON->UARTFRGMULT = SYSCON_UARTFRGMULT_MULT(mul);
547 }
548
549 /*! @brief Update CLKOUT src
550 * @param none.
551 */
552 void CLOCK_UpdateClkOUTsrc(void);
553
554 /* @} */
555
556 #if defined(__cplusplus)
557 }
558 #endif /* __cplusplus */
559
560 /*! @} */
561
562 #endif /* _FSL_CLOCK_H_ */
563
