1 /*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_RESET_H_
9 #define _FSL_RESET_H_
10
11 #include <assert.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <string.h>
15 #include "fsl_device_registers.h"
16
17 /*!
18 * @addtogroup reset
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief reset driver version 2.4.0 */
29 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
30 /*@}*/
31
32 /*!
33 * @brief Enumeration for peripheral reset control bits
34 *
35 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
36 */
37 typedef enum _SYSCON_RSTn
38 {
39 kFLASH_RST_N_SHIFT_RSTn = 0 | 4U, /**< Flash controller reset control */
40 kI2C0_RST_N_SHIFT_RSTn = 0 | 5U, /**< I2C0 reset control */
41 kGPIO0_RST_N_SHIFT_RSTn = 0 | 6U, /**< GPIO0 reset control */
42 kSWM_RST_N_SHIFT_RSTn = 0 | 7U, /**< SWM reset control */
43 kWKT_RST_N_SHIFT_RSTn = 0 | 9U, /**< Self-wake-up timer(WKT) reset control */
44 kMRT_RST_N_SHIFT_RSTn = 0 | 10U, /**< Multi-rate timer(MRT) reset control */
45 kSPI0_RST_N_SHIFT_RSTn = 0 | 11U, /**< SPI0 reset control. */
46 kCRC_RST_SHIFT_RSTn = 0 | 13U, /**< CRC reset control */
47 kUART0_RST_N_SHIFT_RSTn = 0 | 14U, /**< UART0 reset control */
48 kUART1_RST_N_SHIFT_RSTn = 0 | 15U, /**< UART1 reset control */
49 kIOCON_RST_N_SHIFT_RSTn = 0 | 18U, /**< IOCON reset control */
50 kACMP_RST_N_SHIFT_RSTn = 0 | 19U, /**< Analog comparator reset control */
51 kADC_RST_N_SHIFT_RSTn = 0 | 24U, /**< ADC reset control */
52 kCTIMER0_RST_N_SHIFT_RSTn = 0 | 25U, /**< CTIMER0 reset control */
53 kGPIOINT_RST_N_SHIFT_RSTn = 0 | 28U, /**< GPIOINT reset control */
54 kFRG0_RST_N_SHIFT_RSTn = 65536 | 3U, /**< Fractional baud rate generator 0 reset control */
55 kOTHER_RST_N_SHIFT_RSTn = (int)0xFFFFFFFFU /**< Some functions don't need reset */
56 } SYSCON_RSTn_t;
57
58 /** Array initializers with peripheral reset bits **/
59 #define FLASH_RSTS_N \
60 { \
61 kFLASH_RST_N_SHIFT_RSTn \
62 } /* Reset bits for Flash peripheral */
63 #define I2C_RSTS_N \
64 { \
65 kI2C0_RST_N_SHIFT_RSTn \
66 } /* Reset bits for I2C peripheral */
67 #define GPIO_RSTS_N \
68 { \
69 kGPIO0_RST_N_SHIFT_RSTn \
70 } /* Reset bits for GPIO peripheral */
71 #define SWM_RSTS_N \
72 { \
73 kSWM_RST_N_SHIFT_RSTn \
74 } /* Reset bits for SWM peripheral */
75 #define WKT_RSTS_N \
76 { \
77 kWKT_RST_N_SHIFT_RSTn \
78 } /* Reset bits for WKT peripheral */
79 #define MRT_RSTS_N \
80 { \
81 kMRT_RST_N_SHIFT_RSTn \
82 } /* Reset bits for MRT peripheral */
83 #define SPI_RSTS_N \
84 { \
85 kSPI0_RST_N_SHIFT_RSTn \
86 } /* Reset bits for SPI peripheral */
87 #define CRC_RSTS_N \
88 { \
89 kCRC_RST_SHIFT_RSTn \
90 } /* Reset bits for CRC peripheral */
91 #define UART_RSTS_N \
92 { \
93 kUART0_RST_N_SHIFT_RSTn, kUART1_RST_N_SHIFT_RSTn \
94 } /* Reset bits for UART peripheral */
95 #define IOCON_RSTS_N \
96 { \
97 kIOCON_RST_N_SHIFT_RSTn \
98 } /* Reset bits for IOCON peripheral */
99 #define ACMP_RSTS_N \
100 { \
101 kACMP_RST_N_SHIFT_RSTn \
102 } /* Reset bits for ACMP peripheral */
103 #define ADC_RSTS_N \
104 { \
105 kADC_RST_N_SHIFT_RSTn \
106 } /* Reset bits for ADC peripheral */
107 #define CTIMER_RSTS_N \
108 { \
109 kCTIMER0_RST_N_SHIFT_RSTn \
110 } /* Reset bits for CTIMER peripheral */
111 #define GPIOINT_RSTS_N \
112 { \
113 kGPIOINT_RST_N_SHIFT_RSTn \
114 } /* Reset bits for GPIOINT peripheral */
115 #define FRG_RSTS_N \
116 { \
117 kFRG0_RST_N_SHIFT_RSTn \
118 } /* Reset bits for FRG peripheral */
119 #define WWDT_RSTS_N \
120 { \
121 kOTHER_RST_N_SHIFT_RSTn \
122 } /* WWDT don't need reset */
123 typedef SYSCON_RSTn_t reset_ip_name_t;
124
125 /*******************************************************************************
126 * API
127 ******************************************************************************/
128 #if defined(__cplusplus)
129 extern "C" {
130 #endif
131
132 /*!
133 * @brief Assert reset to peripheral.
134 *
135 * Asserts reset signal to specified peripheral module.
136 *
137 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
138 * and reset bit position in the reset register.
139 */
140 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
141
142 /*!
143 * @brief Clear reset to peripheral.
144 *
145 * Clears reset signal to specified peripheral module, allows it to operate.
146 *
147 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
148 * and reset bit position in the reset register.
149 */
150 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
151
152 /*!
153 * @brief Reset peripheral module.
154 *
155 * Reset peripheral module.
156 *
157 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
158 * and reset bit position in the reset register.
159 */
160 void RESET_PeripheralReset(reset_ip_name_t peripheral);
161
162 /*!
163 * @brief Release peripheral module.
164 *
165 * Release peripheral module.
166 *
167 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
168 * and reset bit position in the reset register.
169 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)170 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
171 {
172 RESET_ClearPeripheralReset(peripheral);
173 }
174
175 #if defined(__cplusplus)
176 }
177 #endif
178
179 /*! @} */
180
181 #endif /* _FSL_RESET_H_ */
182
