1 /*
2 * Copyright 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_POWER_H_
8 #define _FSL_POWER_H_
9
10 #include <stdint.h>
11 #include "fsl_common.h"
12 #include "fsl_device_registers.h"
13
14 /*!
15 * @addtogroup power
16 * @{
17 */
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief power driver version 2.0.1. */
25 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
26 /*@}*/
27
28 /**
29 * @brief Low Power Modes configuration
30 */
31 typedef enum _power_mode_config
32 {
33 kPmu_Sleep = 0U,
34 kPmu_Deep_Sleep = 1U,
35 kPmu_PowerDown = 2U,
36 kPmu_Deep_PowerDown = 3U,
37 } power_mode_cfg_t;
38
39 /**
40 * @brief Device Reset Causes
41 */
42 typedef enum _power_reset_cause
43 {
44 kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
45 kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
46 kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
47 kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
48 kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
49 kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
50 kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
51 /* Reset causes in DEEP-POWER-DOWN low power mode */
52 kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 5 wake-up pins */
53 kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Clock (RTC) */
54 kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
55 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC =
56 10UL, /*!< Any of the 5 wake-up pins and RTC (the 2 events occured within 1 nano-second of each other) */
57 kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER =
58 11UL, /*!< Any of the 5 wake-up pins and OSTIMER (the 2 events occured within 1 nano-second of each other) */
59 kRESET_CAUSE_DPDRESET_RTC_OSTIMER =
60 12UL, /*!< Real Time Clock or OS Event Timer (the 2 events occured within 1 nano-second of each other) */
61 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 5 wake-up pins or RTC or OS Event Timer (the 3
62 events occured within 1 nano-second of each other) */
63 /* Miscallenous */
64 kRESET_CAUSE_NOT_RELEVANT =
65 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
66 kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
67 application point of view. */
68 } power_reset_cause_t;
69
70 /**
71 * @brief Device Boot Modes
72 */
73 typedef enum _power_boot_mode
74 {
75 kBOOT_MODE_POWER_UP =
76 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
77 kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
78 kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
79 kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
80 } power_boot_mode_t;
81
82 /**
83 * @brief Device wake up pins events
84 */
85 typedef enum _power_wakeup_pin_t
86 {
87 kWAKEUP_PIN_NONE = 0UL, /*!< No wake up pin event */
88 kWAKEUP_PIN_0 = (1UL << 0), /*!< Wake up pin 0 event */
89 kWAKEUP_PIN_1 = (1UL << 1), /*!< Wake up pin 1 event */
90 kWAKEUP_PIN_2 = (1UL << 2), /*!< Wake up pin 2 event */
91 kWAKEUP_PIN_3 = (1UL << 3), /*!< Wake up pin 3 event */
92 kWAKEUP_PIN_4 = (1UL << 4), /*!< Wake up pin 4 event */
93 kWAKEUP_PIN_MULTIPLE = 0x1FUL, /*!< More than 1 wake up pins events occured (within 1 nano-second of each other) */
94 } power_wakeup_pin_t;
95
96 /**
97 * @brief analog components power modes control during low power modes
98 */
99 typedef enum _power_pd_bit
100 {
101 /* Power Down Vector 0 */
102 kPDRUNCFG_PD_DCDC = (1UL << 0),
103 kPDRUNCFG_PD_BIAS = (1UL << 1),
104 kPDRUNCFG_PD_BODCORE = (1UL << 2),
105 kPDRUNCFG_PD_BODVDDMAIN = (1UL << 3),
106 kPDRUNCFG_PD_FRO1M = (1UL << 4),
107 kPDRUNCFG_PD_FRO192M = (1UL << 5),
108 kPDRUNCFG_PD_FRO32K = (1UL << 6),
109 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
110 kPDRUNCFG_PD_XTALHF = (1UL << 8),
111 kPDRUNCFG_PD_PLL0 = (1UL << 9),
112 kPDRUNCFG_PD_PLL1 = (1UL << 10),
113 kPDRUNCFG_PD_USBFSPHY = (1UL << 11),
114 kPDRUNCFG_PD_COMP = (1UL << 13),
115 kPDRUNCFG_PD_LDOMEM = (1UL << 16),
116 kPDRUNCFG_PD_LDOEFUSEPROG = (1UL << 18),
117 kPDRUNCFG_PD_LDOXTALHF = (1UL << 20),
118 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
119 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
120 kPDRUNCFG_PD_ROM = (1UL << 24),
121 kPDRUNCFG_PD_HSCMP0 = (1UL << 25),
122 kPDRUNCFG_PD_HSCMP1 = (1UL << 26),
123 kPDRUNCFG_PD_HSCMP2 = (1UL << 27),
124 kPDRUNCFG_PD_OPAMP0 = (1UL << 28),
125 kPDRUNCFG_PD_OPAMP1 = (1UL << 29),
126 kPDRUNCFG_PD_OPAMP2 = (1UL << 30),
127 kPDRUNCFG_PD_VREF = (1UL << 31),
128
129 /* Power Down Vector 1 */
130 kPDRUNCFG_PD_CMPBIAS = (1UL << 0) | (1UL << 31),
131 kPDRUNCFG_PD_HSCMP0_DAC = (1UL << 1) | (1UL << 31),
132 kPDRUNCFG_PD_HSCMP1_DAC = (1UL << 2) | (1UL << 31),
133 kPDRUNCFG_PD_HSCMP2_DAC = (1UL << 3) | (1UL << 31),
134 kPDRUNCFG_PD_DAC0 = (1UL << 4) | (1UL << 31),
135 kPDRUNCFG_PD_DAC1 = (1UL << 5) | (1UL << 31),
136 kPDRUNCFG_PD_DAC2 = (1UL << 6) | (1UL << 31),
137 kPDRUNCFG_STOP_DAC0 = (1UL << 7) | (1UL << 31),
138 kPDRUNCFG_STOP_DAC1 = (1UL << 8) | (1UL << 31),
139 kPDRUNCFG_STOP_DAC2 = (1UL << 9) | (1UL << 31),
140
141 /*
142 This enum member has no practical meaning,it is used to avoid MISRA issue,
143 user should not trying to use it.
144 */
145 kPDRUNCFG_ForceUnsigned = 0x80000000U,
146 } pd_bit_t;
147
148 /**
149 * @brief SRAM instances bit masks
150 */
151 typedef enum _power_sram_bit
152 {
153 kPOWER_SRAM_RAM_X0 = (1UL << 0), /*!< RAM_X0 */
154 kPOWER_SRAM_RAM_00 = (1UL << 1), /*!< RAM_00 */
155 kPOWER_SRAM_RAM_01 = (1UL << 2), /*!< RAM_01 */
156 kPOWER_SRAM_RAM_02 = (1UL << 3), /*!< RAM_02 */
157 kPOWER_SRAM_RAM_03 = (1UL << 4), /*!< RAM_03 */
158 kPOWER_SRAM_RAM_10 = (1UL << 5), /*!< RAM_10 */
159 kPOWER_SRAM_RAM_20 = (1UL << 6), /*!< RAM_20 */
160 kPOWER_SRAM_RAM_30 = (1UL << 7), /*!< RAM_30 */
161 kPOWER_SRAM_RAM_40 = (1UL << 8), /*!< RAM_40 */
162 kPOWER_SRAM_RAM_41 = (1UL << 9), /*!< RAM_41 */
163 kPOWER_SRAM_RAM_42 = (1UL << 10), /*!< RAM_42 */
164 kPOWER_SRAM_RAM_43 = (1UL << 11), /*!< RAM_43 */
165 kPOWER_SRAM_FLASHCACHE = (1UL << 12), /*!< Reserved. Flash Cache SRAM instance */
166 kPOWER_SRAM_FLEXSPICACHE = (1UL << 13), /*!< Reserved. FlexSPI Cache SRAM instance */
167 kPOWER_SRAM_FLEXSPIH2PREG = (1UL << 14), /*!< Reserved. FlexSPI Dual Port Register Files instances */
168
169 kPOWER_SRAM_DSLP_MASK = 0x7FFFUL, /*!< Reserved. DEEP-SLEEP SRAM instances */
170 kPOWER_SRAM_PDWN_MASK = 0xFFFUL, /*!< Reserved. POWER-DOWN SRAM instances */
171
172 #if (defined(LPC55S36_SERIES) || defined(LPC5536_SERIES) || defined(LPC5534_SERIES))
173 kPOWER_SRAM_DPWD_MASK = 0xFE6UL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_X0, RAM_02 and RAM_03 excluded:
174 they are used by ROM Boot code) */
175 #else
176 kPOWER_SRAM_DPWD_MASK = 0xF3FUL, /*!< Reserved. DEEP-POWER-DOWN SRAM instances (RAM_20 & RAM_30 excluded).*/
177 #endif
178
179 /*
180 This enum member has no practical meaning,it is used to avoid MISRA issue,
181 user should not trying to use it.
182 */
183 kPOWER_SRAM_ForceUnsigned = 0x80000000U,
184 } power_sram_bit_t;
185
186 /**
187 * @brief SRAM instances indexes
188 */
189 typedef enum _power_sram_index
190 {
191 kPOWER_SRAM_IDX_RAM_X0 = 0UL, /*!< RAM_X0 */
192 kPOWER_SRAM_IDX_RAM_00 = 1UL, /*!< RAM_00 */
193 kPOWER_SRAM_IDX_RAM_01 = 2UL, /*!< RAM_01 */
194 kPOWER_SRAM_IDX_RAM_02 = 3UL, /*!< RAM_02 */
195 kPOWER_SRAM_IDX_RAM_03 = 4UL, /*!< RAM_03 */
196 kPOWER_SRAM_IDX_RAM_10 = 5UL, /*!< RAM_10 */
197 kPOWER_SRAM_IDX_RAM_20 = 6UL, /*!< RAM_20 */
198 kPOWER_SRAM_IDX_RAM_30 = 7UL, /*!< RAM_30 */
199 kPOWER_SRAM_IDX_RAM_40 = 8UL, /*!< RAM_40 */
200 kPOWER_SRAM_IDX_RAM_41 = 9UL, /*!< RAM_41 */
201 kPOWER_SRAM_IDX_RAM_42 = 10UL, /*!< RAM_42 */
202 kPOWER_SRAM_IDX_RAM_43 = 11UL, /*!< RAM_43 */
203 kPOWER_SRAM_IDX_FLASHCACHE = 12UL, /*!< Reserved. Flash Cache SRAM instance */
204 kPOWER_SRAM_IDX_FLEXSPICACHE = 13UL, /*!< Reserved. FlexSPI Cache SRAM instance */
205 kPOWER_SRAM_IDX_FLEXSPIH2PREG = 14UL, /*!< Reserved. FlexSPI Dual Port Register Files instances */
206 } power_sram_index_t;
207
208 /**
209 * @brief SRAM Power Mode
210 */
211 typedef enum _power_sram_pwr_mode
212 {
213 kPOWER_SRAMPwrActive = 0U, /*!< Active */
214 kPOWER_SRAMPwrLightSleep = 1U, /*!< RESERVED, DO NOT USE (Light Sleep) */
215 kPOWER_SRAMPwrDeepSleep = 2U, /*!< Deep Sleep : SRAM content retained */
216 kPOWER_SRAMPwrShutDown = 3U, /*!< Shutdown: SRAM content lost */
217 } power_sram_pwr_mode_t;
218
219 /**
220 * @brief BOD VDDMAIN level
221 */
222 typedef enum _power_bod_vddmain_level
223 {
224 kPOWER_BodVddmainLevel1000mv = 0, /*!< VDDMAIN Brown out detector level 1V */
225 kPOWER_BodVddmainLevel1100mv = 1, /*!< VDDMAIN Brown out detector level 1.1V */
226 kPOWER_BodVddmainLevel1200mv = 2, /*!< VDDMAIN Brown out detector level 1.2V */
227 kPOWER_BodVddmainLevel1300mv = 3, /*!< VDDMAIN Brown out detector level 1.3V */
228 kPOWER_BodVddmainLevel1400mv = 4, /*!< VDDMAIN Brown out detector level 1.4V */
229 kPOWER_BodVddmainLevel1500mv = 5, /*!< VDDMAIN Brown out detector level 1.5V */
230 kPOWER_BodVddmainLevel1600mv = 6, /*!< VDDMAIN Brown out detector level 1.6V */
231 kPOWER_BodVddmainLevel1650mv = 7, /*!< VDDMAIN Brown out detector level 1.65V */
232 kPOWER_BodVddmainLevel1700mv = 8, /*!< VDDMAIN Brown out detector level 1.7V */
233 kPOWER_BodVddmainLevel1750mv = 9, /*!< VDDMAIN Brown out detector level 1.75V */
234 kPOWER_BodVddmainLevel1800mv = 10, /*!< VDDMAIN Brown out detector level 1.8V */
235 kPOWER_BodVddmainLevel1900mv = 11, /*!< VDDMAIN Brown out detector level 1.9V */
236 kPOWER_BodVddmainLevel2000mv = 12, /*!< VDDMAIN Brown out detector level 2V */
237 kPOWER_BodVddmainLevel2100mv = 13, /*!< VDDMAIN Brown out detector level 2.1V */
238 kPOWER_BodVddmainLevel2200mv = 14, /*!< VDDMAIN Brown out detector level 2.2V */
239 kPOWER_BodVddmainLevel2300mv = 15, /*!< VDDMAIN Brown out detector level 2.3V */
240 kPOWER_BodVddmainLevel2400mv = 16, /*!< VDDMAIN Brown out detector level 2.4V */
241 kPOWER_BodVddmainLevel2500mv = 17, /*!< VDDMAIN Brown out detector level 2.5V */
242 kPOWER_BodVddmainLevel2600mv = 18, /*!< VDDMAIN Brown out detector level 2.6V */
243 kPOWER_BodVddmainLevel2700mv = 19, /*!< VDDMAIN Brown out detector level 2.7V */
244 kPOWER_BodVddmainLevel2800mv = 20, /*!< VDDMAIN Brown out detector level 2.80 V */
245 kPOWER_BodVddmainLevel2900mv = 21, /*!< VDDMAIN Brown out detector level 2.9V */
246 kPOWER_BodVddmainLevel3000mv = 22, /*!< VDDMAIN Brown out detector level 3.0V */
247 kPOWER_BodVddmainLevel3100mv = 23, /*!< VDDMAIN Brown out detector level 3.1V */
248 kPOWER_BodVddmainLevel3200mv = 24, /*!< VDDMAIN Brown out detector level 3.2V */
249 kPOWER_BodVddmainLevel3300mv = 25, /*!< VDDMAIN Brown out detector level 3.3V */
250 } power_bod_vddmain_level_t;
251
252 /**
253 * @brief BOD core level
254 */
255 typedef enum _power_bod_core_level
256 {
257 kPOWER_BodCoreLevel0A600mv = 0, /*!< core Brown out detector level 600mV for 0A */
258 kPOWER_BodCoreLevel0A650mv = 1, /*!< core Brown out detector level 650mV for 0A */
259 kPOWER_BodCoreLevel0A700mv = 2, /*!< core Brown out detector level 700mV for 0A */
260 kPOWER_BodCoreLevel0A750mv = 3, /*!< core Brown out detector level 750mV for 0A */
261 kPOWER_BodCoreLevel0A800mv = 4, /*!< core Brown out detector level 800mV for 0A */
262 kPOWER_BodCoreLevel0A850mv = 5, /*!< core Brown out detector level 850mV for 0A */
263 kPOWER_BodCoreLevel0A900mv = 6, /*!< core Brown out detector level 900mV for 0A */
264 kPOWER_BodCoreLevel0A950mv = 7, /*!< core Brown out detector level 950mV for 0A */
265 kPOWER_BodCoreLevel1B929mv = 5, /*!< core Brown out detector level 929mV for 1B */
266 kPOWER_BodCoreLevel1B984mv = 6, /*!< core Brown out detector level 984mV for 1B */
267 kPOWER_BodCoreLevel1B1038mv = 7, /*!< core Brown out detector level 1038mV for 1B */
268 } power_bod_core_level_t;
269
270 /**
271 * @brief BODs (VDDMAIN & Core) Hysteresis control
272 */
273 typedef enum _power_bod_hyst
274 {
275 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
276 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
277 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
278 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
279 } power_bod_hyst_t;
280
281 /**
282 * @brief Core Power Source
283 */
284 typedef enum _power_core_pwr_source
285 {
286 kPOWER_CoreSrcDCDC = 0U, /*!< DCDC */
287 kPOWER_CoreSrcLDOCoreHP = 1U, /*!< LDO Core High Power Mode */
288 kPOWER_CoreSrcLDOCoreLP = 2U, /*!< LDO Core Low Power Mode (DO NOT USE : Reserved for test purposes) */
289 kPOWER_CoreSrcExternal = 3U, /*!< External (DO NOT USE : Reserved for test purposes) */
290 } power_core_pwr_source_t;
291
292 /**
293 * @brief Core Regulators Power State
294 */
295 typedef enum _power_core_pwr_state
296 {
297 kPOWER_CorePwrDisable = 0U, /*!< Disable */
298 kPOWER_CorePwrEnable = 1U, /*!< Enable */
299 } power_core_pwr_state_t;
300
301 /**
302 * @brief Generic Power Library APIs Status codes
303 */
304 typedef enum _power_status
305 {
306 kPOWER_Status_Success = 0U, /*!< OK */
307 kPOWER_Status_Fail = 1U, /*!< Generic error code */
308 } power_status_t;
309
310 /**
311 * @brief Low Power Modes Wake up sources
312 */
313 /* Wake up source vector 0 */
314 #define WAKEUP_SYS (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
315 #define WAKEUP_SDMA0 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */
316 #define WAKEUP_GPIO_GLOBALINT0 (1UL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
317 #define WAKEUP_GPIO_GLOBALINT1 (1UL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
318 #define WAKEUP_GPIO_INT0_0 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */
319 #define WAKEUP_GPIO_INT0_1 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */
320 #define WAKEUP_GPIO_INT0_2 (1UL << 6) /*!< [SLEEP, DEEP SLEEP ] */
321 #define WAKEUP_GPIO_INT0_3 (1UL << 7) /*!< [SLEEP, DEEP SLEEP ] */
322 #define WAKEUP_UTICK (1UL << 8) /*!< [SLEEP, DEEP SLEEP ] */
323 #define WAKEUP_MRT (1UL << 9) /*!< [SLEEP, ] */
324 #define WAKEUP_CTIMER0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */
325 #define WAKEUP_CTIMER1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */
326 #define WAKEUP_SCT (1UL << 12) /*!< [SLEEP, ] */
327 #define WAKEUP_CTIMER3 (1UL << 13) /*!< [SLEEP, DEEP SLEEP ] */
328 #define WAKEUP_FLEXCOMM0 (1UL << 14) /*!< [SLEEP, DEEP SLEEP ] */
329 #define WAKEUP_FLEXCOMM1 (1UL << 15) /*!< [SLEEP, DEEP SLEEP ] */
330 #define WAKEUP_FLEXCOMM2 (1UL << 16) /*!< [SLEEP, DEEP SLEEP ] */
331 #define WAKEUP_FLEXCOMM3 (1UL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
332 #define WAKEUP_FLEXCOMM4 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */
333 #define WAKEUP_FLEXCOMM5 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */
334 #define WAKEUP_FLEXCOMM6 (1UL << 20) /*!< [SLEEP, DEEP SLEEP ] */
335 #define WAKEUP_FLEXCOMM7 (1UL << 21) /*!< [SLEEP, DEEP SLEEP ] */
336 #define WAKEUP_ADC0 (1UL << 22) /*!< [SLEEP, ] */
337 #define WAKEUP_ADC1 (1UL << 23) /*!< [SLEEP, ] */
338 #define WAKEUP_ACMP (1UL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
339 #define WAKEUP_DMIC (1UL << 25) /*!< [SLEEP, ] */
340 #define WAKEUP_HWVAD (1UL << 26) /*!< [SLEEP, DEEP SLEEP, ] */
341 #define WAKEUP_USB0_NEEDCLK (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */
342 #define WAKEUP_USB0 (1UL << 28) /*!< [SLEEP, DEEP SLEEP ] */
343 #define WAKEUP_RTC_ALARM_WAKEUP (1UL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
344 #define WAKEUP_EZH_ARCH_B (1UL << 30) /*!< [SLEEP, ] */
345 #define WAKEUP_WAKEUP_MAILBOX (1UL << 31) /*!< [SLEEP, DEEP SLEEP, ] */
346
347 /* Wake up source vector 1 */
348 #define WAKEUP_GPIO_INT0_4 (1UL << 0) /*!< [SLEEP, DEEP SLEEP ] */
349 #define WAKEUP_GPIO_INT0_5 (1UL << 1) /*!< [SLEEP, DEEP SLEEP ] */
350 #define WAKEUP_GPIO_INT0_6 (1UL << 2) /*!< [SLEEP, DEEP SLEEP ] */
351 #define WAKEUP_GPIO_INT0_7 (1UL << 3) /*!< [SLEEP, DEEP SLEEP ] */
352 #define WAKEUP_CTIMER2 (1UL << 4) /*!< [SLEEP, DEEP SLEEP ] */
353 #define WAKEUP_CTIMER4 (1UL << 5) /*!< [SLEEP, DEEP SLEEP ] */
354 #define WAKEUP_OS_EVENT_TIMER (1UL << 6) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
355 #define WAKEUP_FLEXSPI (1UL << 7) /*!< [SLEEP, ] */
356 // reserved (1UL << 8)
357 // reserved (1UL << 9)
358 // reserved (1UL << 10)
359 #define WAKEUP_CAN0_0 (1UL << 11) /*!< [SLEEP, ] */
360 #define WAKEUP_CAN0_1 (1UL << 12) /*!< [SLEEP, ] */
361 #define WAKEUP_SPIFILTER (1UL << 13) /*!< [SLEEP, ] */
362 // reserved (1UL << 14)
363 // reserved (1UL << 15)
364 // reserved (1UL << 16)
365 #define WAKEUP_SEC_HYPERVISOR_CALL (1UL << 17) /*!< [SLEEP, ] */
366 #define WAKEUP_SEC_GPIO_INT0_0 (1UL << 18) /*!< [SLEEP, DEEP SLEEP ] */
367 #define WAKEUP_SEC_GPIO_INT0_1 (1UL << 19) /*!< [SLEEP, DEEP SLEEP ] */
368 // reserved (1UL << 20)
369 #define WAKEUP_SEC_VIO (1UL << 21) /*!< [SLEEP, ] */
370 #define WAKEUP_CSS_IRQ0 (1UL << 22) /*!< [SLEEP, ] */
371 #define WAKEUP_PKC (1UL << 23) /*!< [SLEEP, ] */
372 #define WAKEUP_PUF (1UL << 24) /*!< [SLEEP, ] */
373 #define WAKEUP_PQ (1UL << 25) /*!< [SLEEP, ] */
374 #define WAKEUP_SDMA1 (1UL << 26) /*!< [SLEEP, DEEP SLEEP ] */
375 #define WAKEUP_LSPI_HS (1UL << 27) /*!< [SLEEP, DEEP SLEEP ] */
376 #define WAKEUP_CODE_WDG (1UL << 28) /*!< [SLEEP, ] */
377 // reserved (1UL << 29)
378 #define WAKEUP_I3C (1UL << 30) /*!< [SLEEP, DEEP SLEEP ] */
379 // reserved (1UL << 31)
380
381 /* Wake up source vector 2 */
382 #define WAKEUP_NEUTRON (1UL << 0) /*!< [SLEEP, ] */
383 #define WAKEUP_CSS_IRQ1 (1UL << 1) /*!< [SLEEP, ] */
384 // reserved (1UL << 2)
385 #define WAKEUP_ANA_GLITCH_DETECT (1UL << 3)
386 // reserved (1UL << 4)
387 // reserved (1UL << 5)
388 // reserved (1UL << 6)
389 // reserved (1UL << 7)
390 // reserved (1UL << 8)
391 // reserved (1UL << 9)
392 #define WAKEUP_DAC0 (1UL << 10) /*!< [SLEEP, DEEP SLEEP ] */
393 #define WAKEUP_DAC1 (1UL << 11) /*!< [SLEEP, DEEP SLEEP ] */
394 #define WAKEUP_DAC2 (1UL << 12) /*!< [SLEEP, DEEP SLEEP ] */
395 #define WAKEUP_HS_COMP0 (1UL << 13) /*!< [SLEEP, ] */
396 #define WAKEUP_HS_COMP1 (1UL << 14) /*!< [SLEEP, ] */
397 #define WAKEUP_HS_COMP2 (1UL << 15) /*!< [SLEEP, ] */
398 #define WAKEUP_FLEXPWM0_CAPTURE (1UL << 16) /*!< [SLEEP, ] */
399 #define WAKEUP_FLEXPWM0_FAULT (1UL << 17) /*!< [SLEEP, ] */
400 #define WAKEUP_FLEXPWM0_RELOAD_ERROR (1UL << 18) /*!< [SLEEP, ] */
401 #define WAKEUP_FLEXPWM0_COMPARE0 (1UL << 19) /*!< [SLEEP, ] */
402 #define WAKEUP_FLEXPWM0_RELOAD0 (1UL << 20) /*!< [SLEEP, ] */
403 #define WAKEUP_FLEXPWM0_COMPARE1 (1UL << 21) /*!< [SLEEP, ] */
404 #define WAKEUP_FLEXPWM0_RELOAD1 (1UL << 22) /*!< [SLEEP, ] */
405 #define WAKEUP_FLEXPWM0_COMPARE2 (1UL << 23) /*!< [SLEEP, ] */
406 #define WAKEUP_FLEXPWM0_RELOAD2 (1UL << 24) /*!< [SLEEP, ] */
407 #define WAKEUP_FLEXPWM0_COMPARE3 (1UL << 25) /*!< [SLEEP, ] */
408 #define WAKEUP_FLEXPWM0_RELOAD3 (1UL << 26) /*!< [SLEEP, ] */
409 #define WAKEUP_FLEXPWM1_CAPTURE (1UL << 27) /*!< [SLEEP, ] */
410 #define WAKEUP_FLEXPWM1_FAULT (1UL << 28) /*!< [SLEEP, ] */
411 #define WAKEUP_FLEXPWM1_RELOAD_ERROR (1UL << 29) /*!< [SLEEP, ] */
412 #define WAKEUP_FLEXPWM1_COMPARE0 (1UL << 30) /*!< [SLEEP, ] */
413 #define WAKEUP_FLEXPWM1_RELOAD0 (1UL << 31) /*!< [SLEEP, ] */
414
415 /* Wake up source vector 3 */
416 #define WAKEUP_FLEXPWM1_COMPARE1 (1UL << 0) /*!< [SLEEP, ] */
417 #define WAKEUP_FLEXPWM1_RELOAD1 (1UL << 1) /*!< [SLEEP, ] */
418 #define WAKEUP_FLEXPWM1_COMPARE2 (1UL << 2) /*!< [SLEEP, ] */
419 #define WAKEUP_FLEXPWM1_RELOAD2 (1UL << 3) /*!< [SLEEP, ] */
420 #define WAKEUP_FLEXPWM1_COMPARE3 (1UL << 4) /*!< [SLEEP, ] */
421 #define WAKEUP_FLEXPWM1_RELOAD3 (1UL << 5) /*!< [SLEEP, ] */
422 #define WAKEUP_ENC0_COMPARE (1UL << 6) /*!< [SLEEP, ] */
423 #define WAKEUP_ENC0_HOME (1UL << 7) /*!< [SLEEP, ] */
424 #define WAKEUP_ENC0_WDG (1UL << 8) /*!< [SLEEP, ] */
425 #define WAKEUP_ENC0_IDX (1UL << 9) /*!< [SLEEP, ] */
426 #define WAKEUP_ENC1_COMPARE (1UL << 10) /*!< [SLEEP, ] */
427 #define WAKEUP_ENC1_HOME (1UL << 11) /*!< [SLEEP, ] */
428 #define WAKEUP_ENC1_WDG (1UL << 12) /*!< [SLEEP, ] */
429 #define WAKEUP_ENC1_IDX (1UL << 13) /*!< [SLEEP, ] */
430 #define WAKEUP_ITRC (1UL << 14) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
431 #define WAKEUP_CF_DSP24L_IRQ0 (1UL << 15) /*!< [SLEEP, ] */
432 #define WAKEUP_CF_DSP24L_IRQ1 (1UL << 16) /*!< [SLEEP, ] */
433 #define WAKEUP_FTM0 (1UL << 17) /*!< [SLEEP, ] */
434 // reserved (1UL << 18)
435 // reserved (1UL << 19)
436 // reserved (1UL << 20)
437 // reserved (1UL << 21)
438 // reserved (1UL << 22)
439 // reserved (1UL << 23)
440 // reserved (1UL << 24)
441 // reserved (1UL << 25)
442 // reserved (1UL << 26)
443 // reserved (1UL << 27)
444 // reserved (1UL << 28)
445 // reserved (1UL << 29)
446 // reserved (1UL << 30)
447 // reserved (1UL << 31)
448
449 /**
450 * @brief Sleep Postpone (DEEP-SLEEP)
451 */
452 #define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */
453 #define LOWPOWER_HWWAKE_PERIPHERALS \
454 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
455 peripheral clocking to wake up temporarily while the related status is asserted */
456 #define LOWPOWER_HWWAKE_DMIC \
457 (1UL << 2) /*!< Wake for DMIC. DMIC being busy will cause peripheral clocking to remain running until DMIC \
458 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
459 #define LOWPOWER_HWWAKE_SDMA0 \
460 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
461 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */
462 #define LOWPOWER_HWWAKE_SDMA1 \
463 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
464 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS or LOWPOWER_HWWAKE_DAC */
465 #define LOWPOWER_HWWAKE_DAC \
466 (1UL << 6) /*!< Wake for DAC0, DAC1, DAC2. Any DAC0/1/2 FIFO reaching the level specified by the configuration \
467 will generate an asynchronous SDMA0 request, and SDMA0 will wake up the bus \
468 clock temporarily to transfer data to DAC0/1/2.*/
469 #define LOWPOWER_HWWAKE_ENABLE_FRO192M \
470 (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \
471 LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0, LOWPOWER_HWWAKE_SDMA1 or LOWPOWER_HWWAKE_DAC is \
472 set */
473
474 /**
475 * @brief CPU State retention (POWER-DOWN)
476 */
477 #define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
478 #define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
479
480 /**
481 * @brief Wake up I/O sources (DEEP POWER-DOWN)
482 */
483 #define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
484 #define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
485 #define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
486 #define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
487 #define LOWPOWER_WAKEUPIOSRC_PIO4_INDEX 8 /*!< Pin P0(26) */
488
489 #define LOWPOWER_WAKEUPIOSRC_DISABLE 0UL /*!< Wake up is disable */
490 #define LOWPOWER_WAKEUPIOSRC_RISING 1UL /*!< Wake up on rising edge */
491 #define LOWPOWER_WAKEUPIOSRC_FALLING 2UL /*!< Wake up on falling edge */
492 #define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3UL /*!< Wake up on both rising or falling edges */
493
494 #define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 10 /*!< Pin P1( 1) */
495 #define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 12 /*!< Pin P0(28) */
496 #define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 14 /*!< Pin P1(18) */
497 #define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 16 /*!< Pin P1(30) */
498 #define LOWPOWER_WAKEUPIOSRC_PIO4MODE_INDEX 18 /*!< Pin P0(26) */
499
500 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */
501 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */
502 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */
503 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */
504
505 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
506 20 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
507 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \
508 21 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */
509 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \
510 22 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */
511 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \
512 23 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */
513 #define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX \
514 24 /*!< Wake-up I/O 4 pull-up/down disable/enable control index */
515
516 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \
517 (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */
518 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \
519 (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */
520 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \
521 (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */
522 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
523 (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
524 #define LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_MASK \
525 (1UL << LOWPOWER_WAKEUPIO_PIO4_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down disable/enable mask */
526
527 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 25 /*!< Wake-up I/O 0 pull-up/down configuration index */
528 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 26 /*!< Wake-up I/O 1 pull-up/down configuration index */
529 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 27 /*!< Wake-up I/O 2 pull-up/down configuration index */
530 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 28 /*!< Wake-up I/O 3 pull-up/down configuration index */
531 #define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX 29 /*!< Wake-up I/O 4 pull-up/down configuration index */
532
533 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \
534 (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */
535 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \
536 (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */
537 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \
538 (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */
539 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \
540 (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
541 #define LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_MASK \
542 (1UL << LOWPOWER_WAKEUPIO_PIO4_PULLUPDOWN_INDEX) /*!< Wake-up I/O 4 pull-up/down mask */
543
544 #define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
545 #define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
546
547 #define LOWPOWER_WAKEUPIO_CFG_SRC_IOCON \
548 0 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from IOCON (valid for \
549 DEEP-SLEEP and POWER-DOWN) */
550 #define LOWPOWER_WAKEUPIO_CFG_SRC_PMC \
551 1 /*!< Wake-up pins configuration (in/out, pull up/down plain input ...) is coming from PMC and set up via \
552 the second parameter (wakeup_io_ctrl) of POWER_SetWakeUpPins API (valid for DEEP-SLEEP and POWER-DOWN) */
553
554 #ifdef __cplusplus
555 extern "C" {
556 #endif
557 /*******************************************************************************
558 * API
559 ******************************************************************************/
560
561 /*!
562 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
563 *
564 * @param en peripheral for which to enable the PDRUNCFG bit
565 * @return none
566 */
POWER_EnablePD(pd_bit_t en)567 static inline void POWER_EnablePD(pd_bit_t en)
568 {
569 if ((((uint32_t)en & (1UL << 31)) != 0UL) && ((uint32_t)en != (1UL << 31)))
570 {
571 /* PDRUNCFGSET1 */
572 PMC->PDRUNCFGSET1 = (uint32_t)((uint32_t)en & ~(1UL << 31));
573 }
574 else
575 {
576 /* PDRUNCFGSET0 */
577 PMC->PDRUNCFGSET0 = (uint32_t)en;
578 }
579 }
580
581 /*!
582 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
583 *
584 * @param en peripheral for which to disable the PDRUNCFG bit
585 * @return none
586 */
POWER_DisablePD(pd_bit_t en)587 static inline void POWER_DisablePD(pd_bit_t en)
588 {
589 if ((((uint32_t)en & (1UL << 31)) != 0UL) && ((uint32_t)en != (1UL << 31)))
590 {
591 /* PDRUNCFGCLR1 */
592 PMC->PDRUNCFGCLR1 = (uint32_t)((uint32_t)en & ~(1UL << 31));
593 }
594 else
595 {
596 /* PDRUNCFGCLR0 */
597 PMC->PDRUNCFGCLR0 = (uint32_t)en;
598 }
599 }
600
601 /**
602 * @brief SoC Power Management Controller initialization
603 * @return power_status_t
604 */
605 power_status_t POWER_PowerInit(void);
606
607 /**
608 * @brief Selects the core logic supply source
609 * @param pwr_source : Defines which regulator will be used to power the part core logic (internally)
610 * @return power_status_t
611 */
612 power_status_t POWER_SetCorePowerSource(power_core_pwr_source_t pwr_source);
613
614 /**
615 * @brief Returns the current core logic supply source.
616 * @return power_core_pwr_source_t
617 */
618 power_core_pwr_source_t POWER_GetCorePowerSource(void);
619
620 /**
621 * @brief Allows to control the state (enabled or disabled) of the core logic internal regulators (DCDC, LDO_CORE)
622 * @param pwr_source : Defines which regulator will be enabled or disabled
623 * @param pwr_state : Defines the state of the internal regulator indicated by pwr_source
624 * @return power_status_t
625 */
626 power_status_t POWER_CorePowerSourceControl(power_core_pwr_source_t pwr_source, power_core_pwr_state_t pwr_state);
627
628 /**
629 * @brief Allows to configure SRAM instances (low) power modes when the part is in ACTIVE mode.
630 * @param sram_inst : Defines the SRAM instance(s) to be configured.
631 * @param pwr_mode : Defines the SRAM low power mode to be applied to all SRAM instances given by sram_inst
632 * @return power_status_t
633 */
634 power_status_t POWER_SRAMPowerModeControl(power_sram_bit_t sram_inst, power_sram_pwr_mode_t pwr_mode);
635
636 /**
637 * @brief
638 * @param sram_index : SRAM instances indexes
639 * @return power_sram_pwr_mode_t
640 */
641 power_sram_pwr_mode_t POWER_GetSRAMPowerMode(power_sram_index_t sram_index);
642
643 /**
644 * @brief Configures and enters in SLEEP low power mode
645 * @return Nothing
646 */
647 void POWER_EnterSleep(void);
648
649 /**
650 * @brief Configures and enters in DEEP-SLEEP low power mode
651 * @param exclude_from_pd: Defines which analog peripherals shall NOT be powered down (it is a 2 x 32-bit vectors,
652 aligned with "pd_bit_t" definition)
653 * @param sram_retention_ctrl: Defines which SRAM instances will be put in "retention" mode during deep-sleep (aligned
654 with "power_sram_bit_t" definition)
655 * @param wakeup_interrupts: Defines which peripheral interrupts can be a wake-up source during deep-sleep (it is a 4
656 x 32-bit vectors, aligned with "WAKEUP_" definition)
657 * @param hardware_wake_ctrl: configure DMA services during deep-sleep without waking up entire device (see
658 "LOWPOWER_HWWAKE_*" definition).
659
660 * @return Nothing
661 *
662 * !!! IMPORTANT NOTES :
663 * 1 - CPU & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
664 */
665 void POWER_EnterDeepSleep(uint32_t exclude_from_pd[2],
666 uint32_t sram_retention_ctrl,
667 uint32_t wakeup_interrupts[4],
668 uint32_t hardware_wake_ctrl);
669
670 /**
671 * @brief Configures and enters in POWERDOWN low power mode
672 * @param exclude_from_pd: Defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector,
673 aligned with "pd_bit_t" definition)
674 * @param sram_retention_ctrl: Defines which SRAM instances will be put in "retention" mode during power-down (aligned
675 with "power_sram_bit_t" definition)
676 * @param wakeup_interrupts: Defines which peripheral interrupts can be a wake-up source during power-down (it is a 2
677 x 32-bit vectors, aligned with "WAKEUP_" definition)
678 * @param cpu_retention_addr: Must be:
679 - Word aligned (address ending by 0x0, 0x4, 0x8 and 0xC).
680 - Between 0x2000_0000 and 0x2000_09FC (inside RAM_00) or
681 - Between 0x2000_1000 and 0x2000_19FC (inside RAM_01) or
682 - Between 0x2000_2000 and 0x2000_29FC (inside RAM_02) or
683 - Between 0x2000_3000 and 0x2000_39FC (inside RAM_03)
684 - The CPU state will be stored in SRAM from "cpu_retention_addr" to "cpu_retention_addr + 1540".
685 Therefore, any data present in this area before calling the function will be lost.
686
687 * @return Nothing
688 *
689 * !!! IMPORTANT NOTES :
690 * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API.
691 * 2 - It is the responsability of the user to make sure that SRAM instance containing the application
692 * software stack and variables WILL BE preserved during low power (via parameter "sram_retention_ctrl")
693 */
694 void POWER_EnterPowerDown(uint32_t exclude_from_pd[1],
695 uint32_t sram_retention_ctrl,
696 uint32_t wakeup_interrupts[4],
697 uint32_t cpu_retention_addr);
698
699 /**
700 * @brief Configures and enters in DEEPPOWERDOWN low power mode
701 * @param exclude_from_pd: Defines which analog peripherals shall NOT be powered down (it is a 1 x 32-bit vector,
702 aligned with "pd_bit_t" definition)
703 * @param sram_retention_ctrl: Defines which SRAM instances will be put in "retention" mode during deep power-down
704 (aligned with "power_sram_bit_t" definition)
705 * @param wakeup_interrupts: Defines which peripheral interrupts can be a wake-up source during deep power-down (it is
706 a 2 x 32-bit vectors, aligned with "WAKEUP_" definition)
707 * @param wakeup_io_ctrl: configure the 5 wake-up pins that can wake-up the part from deep power-down mode (see
708 "LOWPOWER_WAKEUPIOSRC_*" definition)
709
710 * @return Nothing
711 *
712 * !!! IMPORTANT NOTES :
713 * 1 - CPU0 & System Clock frequency is switched to FRO12MHz and is NOT restored back by the API.
714 * 2 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
715 reset)
716 */
717 void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd[1],
718 uint32_t sram_retention_ctrl,
719 uint32_t wakeup_interrupts[2],
720 uint32_t wakeup_io_ctrl);
721
722 /**
723 * @brief Configures the 5 wake-up pins to wake up the part in DEEP-SLEEP and POWER-DOWN low power modes.
724 * @param wakeup_io_cfg_src : for all wake-up pins : indicates if the config is from IOCON (0) or from PMC (1).
725 * @param wakeup_io_ctrl: the 5 wake-up pins configurations (see "LOWPOWER_WAKEUPIOSRC_*" definition)
726
727 * @return Nothing
728 *
729 * !!! IMPORTANT NOTES :
730 * 1 - To be called just before POWER_EnterDeepSleep() or POWER_EnterPowerDown().
731 */
732 void POWER_SetWakeUpPins(uint32_t wakeup_io_cfg_src, uint32_t wakeup_io_ctrl);
733
734 /**
735 * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes.
736 * @param reset_cause : the device reset cause, according to the definition of power_reset_cause_t type.
737 * @param boot_mode : the device boot mode, according to the definition of power_boot_mode_t type.
738 * @param wakeup_pin_cause: the wake-up pin sources, according to the definition of power_wakeup_pin_t type.
739
740 * @return Nothing
741 *
742 */
743 void POWER_GetWakeUpCause(power_reset_cause_t *reset_cause,
744 power_boot_mode_t *boot_mode,
745 power_wakeup_pin_t *wakeup_pin_cause);
746
747 /**
748 * @brief Configures the device internal power control settings
749 * @param system_freq_hz: operating frequency required (in Hertz).
750 * @return Nothing
751 *
752 * prepare on-chip power regulators (DC-DC Converter / Core and Always-on
753 * Low Drop-Out regulators) to deliver the amount of power needed for the
754 * requested performance level, as defined by the CPU operating frequency.
755 */
756 void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
757
758 #ifdef __cplusplus
759 }
760 #endif
761
762 /*! @} */
763
764 #endif /* _FSL_POWER_H_ */
765
