1 /*
2 * Copyright 2017, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_POWER_H_
8 #define _FSL_POWER_H_
9
10 #include "fsl_common.h"
11 #include "fsl_device_registers.h"
12 #include <stdint.h>
13
14 /*!
15 * @addtogroup power
16 * @{
17 */
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief power driver version 1.0.0. */
25 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
26 /*@}*/
27
28 /* Power mode configuration API parameter */
29 typedef enum _power_mode_config
30 {
31 kPmu_Sleep = 0U,
32 kPmu_Deep_Sleep = 1U,
33 kPmu_PowerDown = 2U,
34 kPmu_Deep_PowerDown = 3U,
35 } power_mode_cfg_t;
36
37 /**
38 * @brief Analog components power modes control during low power modes
39 */
40 typedef enum pd_bits
41 {
42 kPDRUNCFG_PD_DCDC = (1UL << 0),
43 kPDRUNCFG_PD_BIAS = (1UL << 1),
44 kPDRUNCFG_PD_BODCORE = (1UL << 2),
45 kPDRUNCFG_PD_BODVBAT = (1UL << 3),
46 kPDRUNCFG_PD_FRO1M = (1UL << 4),
47 kPDRUNCFG_PD_FRO192M = (1UL << 5),
48 kPDRUNCFG_PD_FRO32K = (1UL << 6),
49 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
50 kPDRUNCFG_PD_XTAL32M = (1UL << 8),
51 kPDRUNCFG_PD_PLL0 = (1UL << 9),
52 kPDRUNCFG_PD_PLL1 = (1UL << 10),
53 kPDRUNCFG_PD_USB0_PHY = (1UL << 11),
54 kPDRUNCFG_PD_USB1_PHY = (1UL << 12),
55 kPDRUNCFG_PD_COMP = (1UL << 13),
56 kPDRUNCFG_PD_TEMPSENS = (1UL << 14),
57 kPDRUNCFG_PD_GPADC = (1UL << 15),
58 kPDRUNCFG_PD_LDOMEM = (1UL << 16),
59 kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),
60 kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),
61 kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
62 kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
63 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
64 kPDRUNCFG_PD_RNG = (1UL << 22),
65 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
66 kPDRUNCFG_PD_ROM = (1UL << 24),
67 /*
68 This enum member has no practical meaning,it is used to avoid MISRA issue,
69 user should not trying to use it.
70 */
71 kPDRUNCFG_ForceUnsigned = 0x80000000U,
72 } pd_bit_t;
73
74 /**
75 * @brief BOD VBAT level
76 */
77 typedef enum _power_bod_vbat_level
78 {
79 kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
80 kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
81 kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
82 kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
83 kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
84 kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
85 kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
86 kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
87 kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
88 kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
89 kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
90 kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
91 kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
92 kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
93 kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
94 kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
95 kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
96 kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
97 kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
98 kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
99 kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
100 kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
101 kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
102 kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
103 kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
104 kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
105 } power_bod_vbat_level_t;
106
107 /**
108 * @brief BOD Hysteresis control
109 */
110 typedef enum _power_bod_hyst
111 {
112 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
113 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
114 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
115 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
116 } power_bod_hyst_t;
117 /**
118 * @brief BOD core level
119 */
120 typedef enum _power_bod_core_level
121 {
122 kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
123 kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
124 kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
125 kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
126 kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
127 kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
128 kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
129 kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
130 } power_bod_core_level_t;
131
132 /**
133 * @brief Device Reset Causes
134 */
135 typedef enum _power_device_reset_cause
136 {
137 kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
138 kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
139 kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
140 kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
141 kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
142 kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
143 kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
144 /* Reset causes in DEEP-POWER-DOWN low power mode */
145 kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */
146 kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */
147 kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
148 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish
149 which of these 2 events occured first) */
150 kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to
151 distinguish which of these 2 events occured first) */
152 kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to
153 distinguish which of these 2 events occured first) */
154 kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish
155 which of these 3 events occured first) */
156 /* Miscallenous */
157 kRESET_CAUSE_NOT_RELEVANT =
158 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
159 kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
160 application point of view. */
161 } power_device_reset_cause_t;
162
163 /**
164 * @brief Device Boot Modes
165 */
166 typedef enum _power_device_boot_mode
167 {
168 kBOOT_MODE_POWER_UP =
169 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
170 kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
171 kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
172 kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
173 } power_device_boot_mode_t;
174
175 /**
176 * @brief SRAM instances retention control during low power modes
177 */
178 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \
179 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
180 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \
181 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
182 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \
183 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
184 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \
185 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
186 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \
187 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
188 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \
189 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
190 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \
191 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
192 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \
193 (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */
194
195 /**
196 * @brief Low Power Modes Wake up sources
197 */
198 #define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
199 #define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
200 #define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
201 #define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
202 #define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
203 #define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
204 #define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
205 #define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
206 #define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
207 #define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
208 #define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
209 #define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
210 #define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
211 #define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
212 #define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
213 #define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
214 #define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
215 #define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
216 #define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
217 #define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
218 #define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
219 #define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
220 #define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
221 // reserved (1ULL << 23)
222 #define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
223 // reserved (1ULL << 25)
224 // reserved (1ULL << 26)
225 #define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
226 #define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
227 #define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
228 // reserved (1ULL << 30)
229 // reserved (1ULL << 31)
230 #define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
231 #define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
232 #define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
233 #define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
234 #define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
235 #define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
236 #define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
237 // reserved (1ULL << 39)
238 // reserved (1ULL << 40)
239 // reserved (1ULL << 41)
240 // reserved (1ULL << 42)
241 #define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */
242 #define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */
243 // reserved (1ULL << 45)
244 // reserved (1ULL << 46)
245 #define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
246 #define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
247 #define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
248 #define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
249 #define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
250 #define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
251 #define WAKEUP_SEC_VIO (1ULL << 53)
252 #define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
253 #define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
254 #define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */
255 // reserved (1ULL << 57)
256 #define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
257 #define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
258 //#define CDOG (1ULL << 60) !< [SLEEP, ]
259 // reserved (1ULL << 61)
260 // reserved (1ULL << 62)
261 #define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
262
263 /**
264 * @brief Sleep Postpone
265 */
266 #define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */
267 #define LOWPOWER_HWWAKE_PERIPHERALS \
268 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
269 peripheral clocking to wake up temporarily while the related status is asserted */
270 #define LOWPOWER_HWWAKE_SDMA0 \
271 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
272 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
273 #define LOWPOWER_HWWAKE_SDMA1 \
274 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
275 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
276 #define LOWPOWER_HWWAKE_ENABLE_FRO192M \
277 (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \
278 LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */
279
280 #define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
281 #define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
282 /**
283 * @brief Wake up I/O sources
284 */
285 #define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
286 #define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
287 #define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
288 #define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
289
290 #define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
291 #define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
292 #define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
293 #define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
294
295 #define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */
296 #define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */
297 #define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */
298 #define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */
299
300 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */
301 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */
302 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */
303 #define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */
304
305 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
306 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */
307 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */
308 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */
309
310 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \
311 (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */
312 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \
313 (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */
314 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \
315 (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */
316 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \
317 (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
318
319 #define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
320 #define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
321
322 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
323 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
324 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \
325 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */
326 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \
327 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */
328 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \
329 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */
330 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \
331 (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */
332 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \
333 (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */
334 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \
335 (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */
336 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
337 (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
338
339 #define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \
340 (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/
341 #define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \
342 (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */
343 #define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \
344 (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */
345 #define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \
346 (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */
347 #define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \
348 (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \
349 disable/enable mask, 0: disable, 1: enable */
350 #define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \
351 (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \
352 disable/enable mask, 0: disable, 1: enable */
353 #define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \
354 (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \
355 disable/enable mask, 0: disable, 1: enable */
356 #define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \
357 (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \
358 disable/enable mask, 0: disable, 1: enable */
359
360 #ifdef __cplusplus
361 extern "C" {
362 #endif
363 /*******************************************************************************
364 * API
365 ******************************************************************************/
366
367 /*!
368 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
369 *
370 * @param en peripheral for which to enable the PDRUNCFG bit
371 * @return none
372 */
POWER_EnablePD(pd_bit_t en)373 static inline void POWER_EnablePD(pd_bit_t en)
374 {
375 /* PDRUNCFGSET */
376 PMC->PDRUNCFGSET0 = (uint32_t)en;
377 }
378
379 /*!
380 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
381 *
382 * @param en peripheral for which to disable the PDRUNCFG bit
383 * @return none
384 */
POWER_DisablePD(pd_bit_t en)385 static inline void POWER_DisablePD(pd_bit_t en)
386 {
387 /* PDRUNCFGCLR */
388 PMC->PDRUNCFGCLR0 = (uint32_t)en;
389 }
390
391 /*!
392 * @brief set BOD VBAT level.
393 *
394 * @param level BOD detect level
395 * @param hyst BoD Hysteresis control
396 * @param enBodVbatReset VBAT brown out detect reset
397 */
398 void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset);
399
400 #if defined(PMC_BODCORE_TRIGLVL_MASK)
401 /*!
402 * @brief set BOD core level.
403 *
404 * @param level BOD detect level
405 * @param hyst BoD Hysteresis control
406 * @param enBodCoreReset core brown out detect reset
407 */
408 void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset);
409 #endif
410
411 /*!
412 * @brief API to enable deep sleep bit in the ARM Core.
413 *
414 * @return none
415 */
POWER_EnableDeepSleep(void)416 static inline void POWER_EnableDeepSleep(void)
417 {
418 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
419 }
420
421 /*!
422 * @brief API to disable deep sleep bit in the ARM Core.
423 *
424 * @return none
425 */
POWER_DisableDeepSleep(void)426 static inline void POWER_DisableDeepSleep(void)
427 {
428 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
429 }
430
431 /**
432 * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event
433 * This MUST BE EXECUTED outside the Flash:
434 * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
435 * preferable to have all functions defined in this file implemented in ROM.
436 *
437 * @return Nothing
438 */
439 void POWER_CycleCpuAndFlash(void);
440
441 /**
442 * @brief Configures and enters in DEEP-SLEEP low power mode
443 * @param exclude_from_pd:
444 * @param sram_retention_ctrl:
445 * @param wakeup_interrupts:
446 * @param hardware_wake_ctrl:
447
448 * @return Nothing
449 *
450 * !!! IMPORTANT NOTES :
451 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
452 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
453 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
454 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
455 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
456 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
457 reset) reset)
458 */
459 void POWER_EnterDeepSleep(uint32_t exclude_from_pd,
460 uint32_t sram_retention_ctrl,
461 uint64_t wakeup_interrupts,
462 uint32_t hardware_wake_ctrl);
463
464 /**
465 * @brief Configures and enters in POWERDOWN low power mode
466 * @param exclude_from_pd:
467 * @param sram_retention_ctrl:
468 * @param wakeup_interrupts:
469 * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
470 RESERVED.
471
472 * @return Nothing
473 *
474 * !!! IMPORTANT NOTES :
475 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
476 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
477 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
478 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
479 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
480 * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance
481 containing the stack used to call this function WILL BE preserved during low power (via parameter
482 "sram_retention_ctrl")
483 * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
484 reset) reset)
485 */
486
487 void POWER_EnterPowerDown(uint32_t exclude_from_pd,
488 uint32_t sram_retention_ctrl,
489 uint64_t wakeup_interrupts,
490 uint32_t cpu_retention_ctrl);
491
492 /**
493 * @brief Configures and enters in DEEPPOWERDOWN low power mode
494 * @param exclude_from_pd:
495 * @param sram_retention_ctrl:
496 * @param wakeup_interrupts:
497 * @param wakeup_io_ctrl:
498
499 * @return Nothing
500 *
501 * !!! IMPORTANT NOTES :
502 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
503 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if
504 DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
505 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
506 restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
507 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
508 reset)
509 */
510 void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,
511 uint32_t sram_retention_ctrl,
512 uint64_t wakeup_interrupts,
513 uint32_t wakeup_io_ctrl);
514
515 /**
516 * @brief Configures and enters in SLEEP low power mode
517 *
518 * @return Nothing
519 */
520 void POWER_EnterSleep(void);
521
522 /*!
523 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
524 *
525 * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,
526 * note that the voltage and flash wait states should be set before changing frequency
527 * @return none
528 */
529 void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
530
531 /**
532 * @brief Sets board-specific trim values for 16MHz XTAL
533 * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
534 * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
535 * becomes 120
536 * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
537 * becomes 120
538 * @return none
539 * @note Following default Values can be used:
540 * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
541 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
542 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
543 */
544 extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,
545 int32_t pi32_16MfXtalPPcbParCappF_x100,
546 int32_t pi32_16MfXtalNPcbParCappF_x100);
547 /**
548 * @brief Sets board-specific trim values for 32kHz XTAL
549 * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
550 * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
551 becomes 120
552 * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
553 becomes 120
554
555 * @return none
556 * @note Following default Values can be used:
557 * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
558 * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
559 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
560 */
561 extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
562 int32_t pi32_32kfXtalPPcbParCappF_x100,
563 int32_t pi32_32kfXtalNPcbParCappF_x100);
564 /**
565 * @brief Enables and sets LDO for 16MHz XTAL
566 * @return none
567 */
568 extern void POWER_SetXtal16mhzLdo(void);
569
570 /**
571 * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes.
572 * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type.
573 * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type.
574 * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0].
575
576 * @return Nothing
577 *
578 * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!!
579 * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!!
580 * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!!
581 * - 1. p_wakeupio_cause is NOT ACCURATE
582 * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when
583 * several wake-up sources are enabled during DEEP-POWER-DOWN
584 * (like enabling wake-up on RTC and Falling edge wake-up pins)
585 *
586 */
587 void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause,
588 power_device_boot_mode_t *p_boot_mode,
589 uint32_t *p_wakeupio_cause);
590 #ifdef __cplusplus
591 }
592 #endif
593
594 /**
595 * @}
596 */
597
598 #endif /* _FSL_POWER_H_ */
599
