1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_RESET_H_
10 #define _FSL_RESET_H_
11
12 #include <assert.h>
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include <string.h>
16 #include "fsl_device_registers.h"
17
18 /*!
19 * @addtogroup reset
20 * @{
21 */
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief reset driver version 2.4.0 */
30 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
31 /*@}*/
32
33 /*!
34 * @brief Enumeration for peripheral reset control bits
35 *
36 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
37 */
38 typedef enum _SYSCON_RSTn
39 {
40 kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */
41 kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */
42 kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */
43 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
44 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
45 kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */
46 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
47 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
48 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
49 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
50 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
51 kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
53 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
54 kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */
55 kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */
56 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
57
58 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
59 kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */
60 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
61 kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */
62 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
63 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
64 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
65 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
66 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
67 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
68 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
69 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
70 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
71 kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
72 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
73 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
74 kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */
75 kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */
76
77 kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
78 kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */
79 kSRAM3_RST_SHIFT_RSTn = 131072 | 6U, /**< SRAM3 reset control */
80 kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
81 kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */
82 kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
83 kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */
84 kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */
85 kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */
86 kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
87 kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
88 kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
89 kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */
90 kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */
91 kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */
92 kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */
93 kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */
94 } SYSCON_RSTn_t;
95
96 /** Array initializers with peripheral reset bits **/
97 #define ADC_RSTS \
98 { \
99 kADC0_RST_SHIFT_RSTn \
100 } /* Reset bits for ADC peripheral */
101 #define MCAN_RSTS \
102 { \
103 kMCAN_RST_SHIFT_RSTn \
104 } /* Reset bits for CAN peripheral */
105 #define CRC_RSTS \
106 { \
107 kCRC_RST_SHIFT_RSTn \
108 } /* Reset bits for CRC peripheral */
109 #define CTIMER_RSTS \
110 { \
111 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
112 kCTIMER4_RST_SHIFT_RSTn \
113 } /* Reset bits for CTIMER peripheral */
114 #define DMA_RSTS_N \
115 { \
116 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
117 } /* Reset bits for DMA peripheral */
118
119 #define FLEXCOMM_RSTS \
120 { \
121 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
122 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \
123 } /* Reset bits for FLEXCOMM peripheral */
124 #define GINT_RSTS \
125 { \
126 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
127 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
128 #define GPIO_RSTS_N \
129 { \
130 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
131 } /* Reset bits for GPIO peripheral */
132 #define INPUTMUX_RSTS \
133 { \
134 kMUX0_RST_SHIFT_RSTn \
135 } /* Reset bits for INPUTMUX peripheral */
136 #define IOCON_RSTS \
137 { \
138 kIOCON_RST_SHIFT_RSTn \
139 } /* Reset bits for IOCON peripheral */
140 #define FLASH_RSTS \
141 { \
142 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
143 } /* Reset bits for Flash peripheral */
144 #define MRT_RSTS \
145 { \
146 kMRT_RST_SHIFT_RSTn \
147 } /* Reset bits for MRT peripheral */
148 #define PINT_RSTS \
149 { \
150 kPINT_RST_SHIFT_RSTn \
151 } /* Reset bits for PINT peripheral */
152 #define CDOG_RSTS \
153 { \
154 kCDOG_RST_SHIFT_RSTn \
155 } /* Reset bits for CDOG peripheral */
156 #define RNG_RSTS \
157 { \
158 kRNG_RST_SHIFT_RSTn \
159 } /* Reset bits for RNG peripheral */
160 #define SCT_RSTS \
161 { \
162 kSCT0_RST_SHIFT_RSTn \
163 } /* Reset bits for SCT peripheral */
164 #define UTICK_RSTS \
165 { \
166 kUTICK_RST_SHIFT_RSTn \
167 } /* Reset bits for UTICK peripheral */
168 #define WWDT_RSTS \
169 { \
170 kWWDT_RST_SHIFT_RSTn \
171 } /* Reset bits for WWDT peripheral */
172 #define PLU_RSTS_N \
173 { \
174 kPLULUT_RST_SHIFT_RSTn \
175 } /* Reset bits for PLU peripheral */
176 #define OSTIMER_RSTS \
177 { \
178 kOSTIMER0_RST_SHIFT_RSTn \
179 } /* Reset bits for OSTIMER peripheral */
180 #define CASPER_RSTS \
181 { \
182 kCASPER_RST_SHIFT_RSTn \
183 } /* Reset bits for Casper peripheral */
184 #define HASHCRYPT_RSTS \
185 { \
186 kHASHCRYPT_RST_SHIFT_RSTn \
187 } /* Reset bits for Hashcrypt peripheral */
188 #define PUF_RSTS \
189 { \
190 kPUF_RST_SHIFT_RSTn \
191 } /* Reset bits for PUF peripheral */
192 typedef SYSCON_RSTn_t reset_ip_name_t;
193
194 /*******************************************************************************
195 * API
196 ******************************************************************************/
197 #if defined(__cplusplus)
198 extern "C" {
199 #endif
200
201 /*!
202 * @brief Assert reset to peripheral.
203 *
204 * Asserts reset signal to specified peripheral module.
205 *
206 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
207 * and reset bit position in the reset register.
208 */
209 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
210
211 /*!
212 * @brief Clear reset to peripheral.
213 *
214 * Clears reset signal to specified peripheral module, allows it to operate.
215 *
216 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
217 * and reset bit position in the reset register.
218 */
219 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
220
221 /*!
222 * @brief Reset peripheral module.
223 *
224 * Reset peripheral module.
225 *
226 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
227 * and reset bit position in the reset register.
228 */
229 void RESET_PeripheralReset(reset_ip_name_t peripheral);
230
231 /*!
232 * @brief Release peripheral module.
233 *
234 * Release peripheral module.
235 *
236 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
237 * and reset bit position in the reset register.
238 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)239 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
240 {
241 RESET_ClearPeripheralReset(peripheral);
242 }
243
244 #if defined(__cplusplus)
245 }
246 #endif
247
248 /*! @} */
249
250 #endif /* _FSL_RESET_H_ */
251
