1 /*
2 * Copyright 2017 - 2021 , 2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.8. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 8))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40 #endif
41
42 /*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51 #endif
52
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
56 #endif
57
58 /*! @brief Clock ip name array for ROM. */
59 #define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63 /*! @brief Clock ip name array for SRAM. */
64 #define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
67 }
68 /*! @brief Clock ip name array for FLASH. */
69 #define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73 /*! @brief Clock ip name array for FMC. */
74 #define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78 /*! @brief Clock ip name array for INPUTMUX. */
79 #define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83 /*! @brief Clock ip name array for IOCON. */
84 #define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88 /*! @brief Clock ip name array for GPIO. */
89 #define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1 \
92 }
93 /*! @brief Clock ip name array for PINT. */
94 #define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98 /*! @brief Clock ip name array for GINT. */
99 #define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103 /*! @brief Clock ip name array for DMA. */
104 #define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108 /*! @brief Clock ip name array for CRC. */
109 #define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113 /*! @brief Clock ip name array for WWDT. */
114 #define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118 /*! @brief Clock ip name array for RTC. */
119 #define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123 /*! @brief Clock ip name array for Mailbox. */
124 #define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128 /*! @brief Clock ip name array for LPADC. */
129 #define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133 /*! @brief Clock ip name array for MRT. */
134 #define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138 /*! @brief Clock ip name array for OSTIMER. */
139 #define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143 /*! @brief Clock ip name array for SCT0. */
144 #define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148 /*! @brief Clock ip name array for MCAN. */
149 #define MCAN_CLOCKS \
150 { \
151 kCLOCK_Mcan \
152 }
153 /*! @brief Clock ip name array for UTICK. */
154 #define UTICK_CLOCKS \
155 { \
156 kCLOCK_Utick0 \
157 }
158 /*! @brief Clock ip name array for FLEXCOMM. */
159 #define FLEXCOMM_CLOCKS \
160 { \
161 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
162 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
163 }
164 /*! @brief Clock ip name array for LPUART. */
165 #define LPUART_CLOCKS \
166 { \
167 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
168 kCLOCK_MinUart6, kCLOCK_MinUart7 \
169 }
170
171 /*! @brief Clock ip name array for BI2C. */
172 #define BI2C_CLOCKS \
173 { \
174 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
175 }
176 /*! @brief Clock ip name array for LSPI. */
177 #define LPSPI_CLOCKS \
178 { \
179 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
180 }
181 /*! @brief Clock ip name array for FLEXI2S. */
182 #define FLEXI2S_CLOCKS \
183 { \
184 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
185 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
186 }
187 /*! @brief Clock ip name array for CTIMER. */
188 #define CTIMER_CLOCKS \
189 { \
190 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
191 }
192 /*! @brief Clock ip name array for COMP */
193 #define COMP_CLOCKS \
194 { \
195 kCLOCK_Comp \
196 }
197 /*! @brief Clock ip name array for FREQME. */
198 #define FREQME_CLOCKS \
199 { \
200 kCLOCK_Freqme \
201 }
202 /*! @brief Clock ip name array for CDOG. */
203 #define CDOG_CLOCKS \
204 { \
205 kCLOCK_Cdog \
206 }
207 /*! @brief Clock ip name array for RNG. */
208 #define RNG_CLOCKS \
209 { \
210 kCLOCK_Rng \
211 }
212 /*! @brief Clock ip name array for HashCrypt. */
213 #define HASHCRYPT_CLOCKS \
214 { \
215 kCLOCK_HashCrypt \
216 }
217 /*! @brief Clock ip name array for PLULUT. */
218 #define PLULUT_CLOCKS \
219 { \
220 kCLOCK_PluLut \
221 }
222 /*! @brief Clock ip name array for PUF. */
223 #define PUF_CLOCKS \
224 { \
225 kCLOCK_Puf \
226 }
227 /*! @brief Clock ip name array for CASPER. */
228 #define CASPER_CLOCKS \
229 { \
230 kCLOCK_Casper \
231 }
232 /*! @brief Clock ip name array for ANALOGCTRL. */
233 #define ANALOGCTRL_CLOCKS \
234 { \
235 kCLOCK_AnalogCtrl \
236 }
237 /*! @brief Clock ip name array for HS_LSPI. */
238 #define HS_LSPI_CLOCKS \
239 { \
240 kCLOCK_Hs_Lspi \
241 }
242 /*! @brief Clock ip name array for GPIO_SEC. */
243 #define GPIO_SEC_CLOCKS \
244 { \
245 kCLOCK_Gpio_Sec \
246 }
247 /*! @brief Clock ip name array for GPIO_SEC_INT. */
248 #define GPIO_SEC_INT_CLOCKS \
249 { \
250 kCLOCK_Gpio_Sec_Int \
251 }
252 #define PLU_CLOCKS \
253 { \
254 kCLOCK_PluLut \
255 }
256 #define SYSCTL_CLOCKS \
257 { \
258 kCLOCK_Sysctl \
259 }
260 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
261 /*------------------------------------------------------------------------------
262 clock_ip_name_t definition:
263 ------------------------------------------------------------------------------*/
264
265 #define CLK_GATE_REG_OFFSET_SHIFT 8U
266 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
267 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
268 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
269
270 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
271 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
272 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
273
274 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
275 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
276
277 #define AHB_CLK_CTRL0 0
278 #define AHB_CLK_CTRL1 1
279 #define AHB_CLK_CTRL2 2
280
281 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
282 typedef enum _clock_ip_name
283 {
284 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
285 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
286
287 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
288
289 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
290
291 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
292
293 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
294
295 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
296
297 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
298
299 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
300
301 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
302
303 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
304
305 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
306
307 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */
308
309 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
310
311 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
312
313 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
314
315 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */
316
317 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
318
319 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
320
321 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */
322
323 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
324
325 kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan. */
326
327 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */
328
329 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
330
331 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
332
333 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
334
335 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
336
337 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
338
339 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
340
341 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
342
343 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
344
345 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
346
347 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
348
349 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
350
351 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
352
353 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
354
355 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
356
357 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
358
359 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
360
361 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
362
363 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
364
365 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
366
367 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
368
369 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
370
371 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
372
373 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
374
375 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
376
377 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
378
379 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
380
381 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
382
383 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
384
385 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
386
387 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
388
389 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
390
391 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
392
393 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
394
395 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
396
397 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
398
399 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
400
401 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
402
403 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
404
405 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
406
407 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
408
409 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */
410
411 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */
412
413 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */
414
415 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */
416
417 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */
418
419 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sram3. */
420
421 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */
422
423 kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Cdog. */
424
425 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
426
427 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */
428
429 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */
430
431 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */
432
433 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */
434
435 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */
436
437 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */
438
439 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */
440
441 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */
442
443 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */
444
445 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */
446
447 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: Gpio Sec Int */
448 } clock_ip_name_t;
449
450 /*! @brief Peripherals clock source definition. */
451 #define BUS_CLK kCLOCK_BusClk
452
453 #define I2C0_CLK_SRC BUS_CLK
454
455 /*! @brief Clock name used to get clock frequency. */
456 typedef enum _clock_name
457 {
458 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
459 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
460 kCLOCK_ClockOut, /*!< CLOCKOUT */
461 kCLOCK_FroHf, /*!< FRO48/96 */
462 kCLOCK_Pll1Out, /*!< PLL1 Output */
463 kCLOCK_Mclk, /*!< MCLK */
464 kCLOCK_Fro12M, /*!< FRO12M */
465 kCLOCK_Fro1M, /*!< FRO1M */
466 kCLOCK_ExtClk, /*!< External Clock */
467 kCLOCK_Pll0Out, /*!< PLL0 Output */
468 kCLOCK_FlexI2S, /*!< FlexI2S clock */
469
470 } clock_name_t;
471
472 /*! @brief Clock Mux Switches
473 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
474 * starting from LSB upwards
475 *
476 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
477 *
478 */
479
480 #define CLK_ATTACH_ID(mux, sel, pos) \
481 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
482 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
483 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
484
485 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
486 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
487 #define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
488 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
489 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
490
491 #define CM_SYSTICKCLKSEL0 0
492 #define CM_TRACECLKSEL 2
493 #define CM_CTIMERCLKSEL0 3
494 #define CM_CTIMERCLKSEL1 4
495 #define CM_CTIMERCLKSEL2 5
496 #define CM_CTIMERCLKSEL3 6
497 #define CM_CTIMERCLKSEL4 7
498 #define CM_MAINCLKSELA 8
499 #define CM_MAINCLKSELB 9
500 #define CM_CLKOUTCLKSEL 10
501 #define CM_PLL0CLKSEL 12
502 #define CM_PLL1CLKSEL 13
503 #define CM_MCANCLKSEL 16
504 #define CM_ADCASYNCCLKSEL 17
505 #define CM_CLK32KCLKSEL 19
506 #define CM_FXCOMCLKSEL0 20
507 #define CM_FXCOMCLKSEL1 21
508 #define CM_FXCOMCLKSEL2 22
509 #define CM_FXCOMCLKSEL3 23
510 #define CM_FXCOMCLKSEL4 24
511 #define CM_FXCOMCLKSEL5 25
512 #define CM_FXCOMCLKSEL6 26
513 #define CM_FXCOMCLKSEL7 27
514 #define CM_HSLSPICLKSEL 28
515 #define CM_MCLKCLKSEL 32
516 #define CM_SCTCLKSEL 36
517
518 #define CM_OSTIMERCLKSEL (62U)
519 #define CM_RTCOSC32KCLKSEL 63U
520
521 /*!
522 * @brief The enumerator of clock attach Id.
523 */
524 typedef enum _clock_attach_id
525 {
526
527 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
528
529 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
530
531 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */
532
533 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
534
535 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */
536
537 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */
538
539 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
540
541 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
542
543 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
544
545 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */
546
547 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
548
549 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */
550
551 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */
552
553 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */
554
555 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */
556
557 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */
558
559 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */
560
561 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */
562
563 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */
564
565 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */
566
567 kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */
568
569 kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */
570
571 kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */
572
573 kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */
574
575 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */
576
577 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */
578
579 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */
580
581 kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4), /*!< Attach EXT_CLK to ADC_CLK. */
582
583 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
584
585 kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0), /*!< Attach OSC32K to CLK32K. */
586
587 kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1), /*!< Attach FRO1MDIV to CLK32K. */
588
589 kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7), /*!< Attach NONE to CLK32K. */
590
591 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */
592
593 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */
594
595 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
596
597 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
598
599 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */
600
601 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */
602
603 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */
604
605 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
606
607 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */
608
609 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */
610
611 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
612
613 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
614
615 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */
616
617 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */
618
619 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */
620
621 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
622
623 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */
624
625 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */
626
627 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
628
629 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
630
631 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */
632
633 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */
634
635 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */
636
637 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
638
639 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */
640
641 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */
642
643 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
644
645 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
646
647 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */
648
649 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */
650
651 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */
652
653 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
654
655 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */
656
657 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */
658
659 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
660
661 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
662
663 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */
664
665 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */
666
667 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */
668
669 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
670
671 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */
672
673 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */
674
675 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
676
677 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
678
679 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */
680
681 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */
682
683 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */
684
685 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
686
687 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */
688
689 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */
690
691 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
692
693 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
694
695 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */
696
697 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */
698
699 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */
700
701 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
702
703 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */
704
705 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */
706
707 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */
708
709 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */
710
711 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */
712
713 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */
714
715 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */
716
717 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
718
719 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */
720
721 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */
722
723 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */
724
725 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */
726
727 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */
728
729 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */
730
731 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */
732
733 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
734
735 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */
736
737 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
738
739 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
740
741 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */
742
743 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */
744
745 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */
746
747 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */
748
749 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
750
751 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */
752
753 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */
754
755 kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach OSC32K to OSTIMER. */
756
757 kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach FRO1M to OSTIMER. */
758
759 kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach MAIN_CLK to OSTIMER. */
760
761 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
762
763 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */
764
765 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */
766
767 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
768
769 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */
770
771 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */
772
773 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */
774
775 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
776
777 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */
778
779 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */
780
781 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */
782
783 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */
784
785 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */
786
787 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */
788
789 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
790
791 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
792
793 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */
794
795 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */
796
797 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */
798
799 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */
800
801 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */
802
803 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
804
805 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
806
807 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */
808
809 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */
810
811 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */
812
813 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */
814
815 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */
816
817 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
818
819 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
820
821 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */
822
823 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */
824
825 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */
826
827 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */
828
829 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */
830
831 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
832
833 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
834
835 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */
836
837 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */
838
839 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */
840
841 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */
842
843 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */
844
845 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
846
847 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
848
849 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */
850
851 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */
852
853 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */
854
855 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */
856
857 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
858
859 } clock_attach_id_t;
860
861 /*! @brief Clock dividers */
862 typedef enum _clock_div_name
863 {
864 kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */
865
866 kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */
867
868 kCLOCK_DivCanClk = 3, /*!< Can Clock Divider. */
869
870 kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */
871
872 kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */
873
874 kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */
875
876 kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */
877
878 kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */
879
880 kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */
881
882 kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */
883
884 kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */
885
886 kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
887
888 kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
889
890 kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
891
892 kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */
893
894 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
895
896 kCLOCK_DivFro1mClk = 40, /*!< Fro1m Clock Divider. */
897
898 kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
899
900 kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
901
902 kCLOCK_DivPll0Clk = 49 /*!< PLL0 clock divider. */
903 } clock_div_name_t;
904
905 /*******************************************************************************
906 * API
907 ******************************************************************************/
908
909 #if defined(__cplusplus)
910 extern "C" {
911 #endif /* __cplusplus */
912
913 /**
914 * @brief Enable the clock for specific IP.
915 * @param clk : Clock to be enabled.
916 * @return Nothing
917 */
CLOCK_EnableClock(clock_ip_name_t clk)918 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
919 {
920 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
921 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
922 }
923 /**
924 * @brief Disable the clock for specific IP.
925 * @param clk : Clock to be Disabled.
926 * @return Nothing
927 */
CLOCK_DisableClock(clock_ip_name_t clk)928 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
929 {
930 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
931 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
932 }
933 /**
934 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
935 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
936 * enabled.
937 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
938 * @return returns success or fail status.
939 */
940 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
941 /**
942 * @brief Set the flash wait states for the input freuqency.
943 * @param system_freq_hz : Input frequency
944 * @return Nothing
945 */
946 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz);
947 /**
948 * @brief Initialize the external osc clock to given frequency.
949 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
950 * @return returns success or fail status.
951 */
952 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
953 /**
954 * @brief Initialize the I2S MCLK clock to given frequency.
955 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
956 * @return returns success or fail status.
957 */
958 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
959 /**
960 * @brief Initialize the PLU CLKIN clock to given frequency.
961 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
962 * @return returns success or fail status.
963 */
964 status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
965 /**
966 * @brief Configure the clock selection muxes.
967 * @param connection : Clock to be configured.
968 * @return Nothing
969 */
970 void CLOCK_AttachClk(clock_attach_id_t connection);
971 /**
972 * @brief Get the actual clock attach id.
973 * This fuction uses the offset in input attach id, then it reads the actual source value in
974 * the register and combine the offset to obtain an actual attach id.
975 * @param attachId : Clock attach id to get.
976 * @return Clock source value.
977 */
978 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
979 /**
980 * @brief Setup peripheral clock dividers.
981 * @param div_name : Clock divider name
982 * @param divided_by_value: Value to be divided
983 * @param reset : Whether to reset the divider counter.
984 * @return Nothing
985 */
986 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
987 /**
988 * @brief Setup rtc 1khz clock divider.
989 * @param divided_by_value: Value to be divided
990 * @return Nothing
991 */
992 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
993 /**
994 * @brief Setup rtc 1hz clock divider.
995 * @param divided_by_value: Value to be divided
996 * @return Nothing
997 */
998 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
999
1000 /**
1001 * @brief Set the flexcomm output frequency.
1002 * @param id : flexcomm instance id
1003 * @param freq : output frequency
1004 * @return 0 : the frequency range is out of range.
1005 * 1 : switch successfully.
1006 */
1007 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
1008
1009 /*! @brief Return Frequency of flexcomm input clock
1010 * @param id : flexcomm instance id
1011 * @return Frequency value
1012 */
1013 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
1014
1015 /*! @brief Return Frequency of selected clock
1016 * @return Frequency of selected clock
1017 */
1018 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1019 /*! @brief Return Frequency of FRO 12MHz
1020 * @return Frequency of FRO 12MHz
1021 */
1022 uint32_t CLOCK_GetFro12MFreq(void);
1023 /*! @brief Return Frequency of FRO 1MHz
1024 * @return Frequency of FRO 1MHz
1025 */
1026 uint32_t CLOCK_GetFro1MFreq(void);
1027 /*! @brief Return Frequency of ClockOut
1028 * @return Frequency of ClockOut
1029 */
1030 uint32_t CLOCK_GetClockOutClkFreq(void);
1031 /*! @brief Return Frequency of Can Clock
1032 * @return Frequency of Can.
1033 */
1034 uint32_t CLOCK_GetMCanClkFreq(void);
1035 /*! @brief Return Frequency of Adc Clock
1036 * @return Frequency of Adc.
1037 */
1038 uint32_t CLOCK_GetAdcClkFreq(void);
1039 /*! @brief Return Frequency of MClk Clock
1040 * @return Frequency of MClk Clock.
1041 */
1042 uint32_t CLOCK_GetMclkClkFreq(void);
1043 /*! @brief Return Frequency of SCTimer Clock
1044 * @return Frequency of SCTimer Clock.
1045 */
1046 uint32_t CLOCK_GetSctClkFreq(void);
1047 /*! @brief Return Frequency of External Clock
1048 * @return Frequency of External Clock. If no external clock is used returns 0.
1049 */
1050 uint32_t CLOCK_GetExtClkFreq(void);
1051 /*! @brief Return Frequency of Watchdog
1052 * @return Frequency of Watchdog
1053 */
1054 uint32_t CLOCK_GetWdtClkFreq(void);
1055 /*! @brief Return Frequency of High-Freq output of FRO
1056 * @return Frequency of High-Freq output of FRO
1057 */
1058 uint32_t CLOCK_GetFroHfFreq(void);
1059 /*! @brief Return Frequency of PLL
1060 * @return Frequency of PLL
1061 */
1062 uint32_t CLOCK_GetPll0OutFreq(void);
1063 /*! @brief Return Frequency of USB PLL
1064 * @return Frequency of PLL
1065 */
1066 uint32_t CLOCK_GetPll1OutFreq(void);
1067 /*! @brief Return Frequency of 32kHz osc
1068 * @return Frequency of 32kHz osc
1069 */
1070 uint32_t CLOCK_GetOsc32KFreq(void);
1071 /*! @brief Return Frequency of Core System
1072 * @return Frequency of Core System
1073 */
1074 uint32_t CLOCK_GetCoreSysClkFreq(void);
1075 /*! @brief Return Frequency of I2S MCLK Clock
1076 * @return Frequency of I2S MCLK Clock
1077 */
1078 uint32_t CLOCK_GetI2SMClkFreq(void);
1079 /*! @brief Return Frequency of PLU CLKIN Clock
1080 * @return Frequency of PLU CLKIN Clock
1081 */
1082 uint32_t CLOCK_GetPLUClkInFreq(void);
1083 /*! @brief Return Frequency of FlexComm Clock
1084 * @return Frequency of FlexComm Clock
1085 */
1086 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1087 /*! @brief Return Frequency of High speed SPI Clock
1088 * @return Frequency of High speed SPI Clock
1089 */
1090 uint32_t CLOCK_GetHsLspiClkFreq(void);
1091 /*! @brief Return Frequency of CTimer functional Clock
1092 * @return Frequency of CTimer functional Clock
1093 */
1094 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
1095 /*! @brief Return Frequency of SystickClock
1096 * @return Frequency of Systick Clock
1097 */
1098 uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
1099
1100 /*! @brief Return PLL0 input clock rate
1101 * @return PLL0 input clock rate
1102 */
1103 uint32_t CLOCK_GetPLL0InClockRate(void);
1104
1105 /*! @brief Return PLL1 input clock rate
1106 * @return PLL1 input clock rate
1107 */
1108 uint32_t CLOCK_GetPLL1InClockRate(void);
1109
1110 /*! @brief Return PLL0 output clock rate
1111 * @param recompute : Forces a PLL rate recomputation if true
1112 * @return PLL0 output clock rate
1113 * @note The PLL rate is cached in the driver in a variable as
1114 * the rate computation function can take some time to perform. It
1115 * is recommended to use 'false' with the 'recompute' parameter.
1116 */
1117 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
1118
1119 /*! @brief Return PLL1 output clock rate
1120 * @param recompute : Forces a PLL rate recomputation if true
1121 * @return PLL1 output clock rate
1122 * @note The PLL rate is cached in the driver in a variable as
1123 * the rate computation function can take some time to perform. It
1124 * is recommended to use 'false' with the 'recompute' parameter.
1125 */
1126 uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
1127
1128 /*! @brief Enables and disables PLL0 bypass mode
1129 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
1130 * @return PLL0 output clock rate
1131 */
CLOCK_SetBypassPLL0(bool bypass)1132 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
1133 {
1134 if (bypass)
1135 {
1136 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1137 }
1138 else
1139 {
1140 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
1141 }
1142 }
1143
1144 /*! @brief Enables and disables PLL1 bypass mode
1145 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
1146 * @return PLL1 output clock rate
1147 */
CLOCK_SetBypassPLL1(bool bypass)1148 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
1149 {
1150 if (bypass)
1151 {
1152 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1153 }
1154 else
1155 {
1156 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
1157 }
1158 }
1159
1160 /*! @brief Check if PLL is locked or not
1161 * @return true if the PLL is locked, false if not locked
1162 */
CLOCK_IsPLL0Locked(void)1163 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
1164 {
1165 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
1166 }
1167
1168 /*! @brief Check if PLL1 is locked or not
1169 * @return true if the PLL1 is locked, false if not locked
1170 */
CLOCK_IsPLL1Locked(void)1171 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
1172 {
1173 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
1174 }
1175
1176 /*! @brief Store the current PLL0 rate
1177 * @param rate: Current rate of the PLL0
1178 * @return Nothing
1179 **/
1180 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1181
1182 /*! @brief PLL configuration structure flags for 'flags' field
1183 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1184 *
1185 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1186 * configuration structure must be assigned with the expected PLL frequency. If the
1187 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1188 * function and the driver will determine the PLL rate from the currently selected
1189 * PLL source. This flag might be used to configure the PLL input clock more accurately
1190 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1191 *
1192 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1193 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1194 * are not used.<br>
1195 */
1196 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1197 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1198 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1199
1200 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1201 * See (MF) field in the PLL0SSCG1 register in the UM.
1202 */
1203 typedef enum _ss_progmodfm
1204 {
1205 kSS_MF_512 = (0U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1206 kSS_MF_384 = (1U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1207 kSS_MF_256 = (2U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1208 kSS_MF_128 = (3U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1209 kSS_MF_64 = (4U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1210 kSS_MF_32 = (5U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1211 kSS_MF_24 = (6U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1212 kSS_MF_16 = (7U << SYSCON_PLL0SSCG1_MF_SHIFT) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1213 } ss_progmodfm_t;
1214
1215 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1216 * See (MR) field in the PLL0SSCG1 register in the UM.
1217 */
1218 typedef enum _ss_progmoddp
1219 {
1220 kSS_MR_K0 = (0U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 0 (no spread spectrum) */
1221 kSS_MR_K1 = (1U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1 */
1222 kSS_MR_K1_5 = (2U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1.5 */
1223 kSS_MR_K2 = (3U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 2 */
1224 kSS_MR_K3 = (4U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 3 */
1225 kSS_MR_K4 = (5U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 4 */
1226 kSS_MR_K6 = (6U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 6 */
1227 kSS_MR_K8 = (7U << SYSCON_PLL0SSCG1_MR_SHIFT) /*!< k = 8 */
1228 } ss_progmoddp_t;
1229
1230 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1231 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1232 * Compensation for low pass filtering of the PLL to get a triangular
1233 * modulation at the output of the PLL, giving a flat frequency spectrum.
1234 */
1235 typedef enum _ss_modwvctrl
1236 {
1237 kSS_MC_NOC = (0U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< no compensation */
1238 kSS_MC_RECC = (2U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< recommended setting */
1239 kSS_MC_MAXC = (3U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< max. compensation */
1240 } ss_modwvctrl_t;
1241
1242 /*! @brief PLL configuration structure
1243 *
1244 * This structure can be used to configure the settings for a PLL
1245 * setup structure. Fill in the desired configuration for the PLL
1246 * and call the PLL setup function to fill in a PLL setup structure.
1247 */
1248 typedef struct _pll_config
1249 {
1250 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1251 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1252 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1253 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1254 PLL_CONFIGFLAG_FORCENOFRACT flag */
1255 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1256 PLL_CONFIGFLAG_FORCENOFRACT flag */
1257 ss_modwvctrl_t
1258 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1259 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1260 PLL_CONFIGFLAG_FORCENOFRACT flag */
1261
1262 } pll_config_t;
1263
1264 /*! @brief PLL setup structure flags for 'flags' field
1265 * These flags control how the PLL setup function sets up the PLL
1266 */
1267 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1268 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1269 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1270 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1271
1272 /*! @brief PLL0 setup structure
1273 * This structure can be used to pre-build a PLL setup configuration
1274 * at run-time and quickly set the PLL to the configuration. It can be
1275 * populated with the PLL setup function. If powering up or waiting
1276 * for PLL lock, the PLL input clock source should be configured prior
1277 * to PLL setup.
1278 */
1279 typedef struct _pll_setup
1280 {
1281 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1282 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1283 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1284 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1285 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1286 uint32_t pllRate; /*!< Acutal PLL rate */
1287 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1288 } pll_setup_t;
1289
1290 /*! @brief PLL status definitions
1291 */
1292 typedef enum _pll_error
1293 {
1294 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1295 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1296 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1297 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1298 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1299 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1300 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1301 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1302 } pll_error_t;
1303
1304 /*! @brief Return PLL0 output clock rate from setup structure
1305 * @param pSetup : Pointer to a PLL setup structure
1306 * @return System PLL output clock rate the setup structure will generate
1307 */
1308 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1309
1310 /*! @brief Return PLL1 output clock rate from setup structure
1311 * @param pSetup : Pointer to a PLL setup structure
1312 * @return PLL0 output clock rate the setup structure will generate
1313 */
1314 uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup);
1315
1316 /*! @brief Set PLL0 output based on the passed PLL setup data
1317 * @param pControl : Pointer to populated PLL control structure to generate setup with
1318 * @param pSetup : Pointer to PLL setup structure to be filled
1319 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1320 * @note Actual frequency for setup may vary from the desired frequency based on the
1321 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1322 */
1323 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1324
1325 /*! @brief Set PLL output from PLL setup structure (precise frequency)
1326 * @param pSetup : Pointer to populated PLL setup structure
1327 * @param flagcfg : Flag configuration for PLL config structure
1328 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1329 * @note This function will power off the PLL, setup the PLL with the
1330 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1331 * and adjust system voltages to the new PLL rate. The function will not
1332 * alter any source clocks (ie, main systen clock) that may use the PLL,
1333 * so these should be setup prior to and after exiting the function.
1334 */
1335 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1336
1337 /**
1338 * @brief Set PLL output from PLL setup structure (precise frequency)
1339 * @param pSetup : Pointer to populated PLL setup structure
1340 * @return kStatus_PLL_Success on success, or PLL setup error code
1341 * @note This function will power off the PLL, setup the PLL with the
1342 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1343 * and adjust system voltages to the new PLL rate. The function will not
1344 * alter any source clocks (ie, main systen clock) that may use the PLL,
1345 * so these should be setup prior to and after exiting the function.
1346 */
1347 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1348
1349 /**
1350 * @brief Set PLL output from PLL setup structure (precise frequency)
1351 * @param pSetup : Pointer to populated PLL setup structure
1352 * @return kStatus_PLL_Success on success, or PLL setup error code
1353 * @note This function will power off the PLL, setup the PLL with the
1354 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1355 * and adjust system voltages to the new PLL rate. The function will not
1356 * alter any source clocks (ie, main systen clock) that may use the PLL,
1357 * so these should be setup prior to and after exiting the function.
1358 */
1359 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1360
1361 /*! @brief Set PLL0 output based on the multiplier and input frequency
1362 * @param multiply_by : multiplier
1363 * @param input_freq : Clock input frequency of the PLL
1364 * @return Nothing
1365 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1366 * function does not disable or enable PLL power, wait for PLL lock,
1367 * or adjust system voltages. These must be done in the application.
1368 * The function will not alter any source clocks (ie, main systen clock)
1369 * that may use the PLL, so these should be setup prior to and after
1370 * exiting the function.
1371 */
1372 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1373
1374 /*! @brief Enable the OSTIMER 32k clock.
1375 * @return Nothing
1376 */
1377 void CLOCK_EnableOstimer32kClock(void);
1378
1379 #if defined(__cplusplus)
1380 }
1381 #endif /* __cplusplus */
1382
1383 /*! @} */
1384
1385 #endif /* _FSL_CLOCK_H_ */
1386
