1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_RESET_H_
10 #define _FSL_RESET_H_
11
12 #include <assert.h>
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include <string.h>
16 #include "fsl_device_registers.h"
17
18 /*!
19 * @addtogroup reset
20 * @{
21 */
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief reset driver version 2.4.0 */
30 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
31 /*@}*/
32
33 /*!
34 * @brief Enumeration for peripheral reset control bits
35 *
36 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
37 */
38 typedef enum _SYSCON_RSTn
39 {
40 kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */
41 kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */
42 kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */
43 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
44 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
45 kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */
46 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
47 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
48 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
49 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
50 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
51 kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
53 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
54 kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */
55 kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */
56 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
57
58 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
59 kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */
60 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
61 kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */
62 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
63 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
64 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
65 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
66 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
67 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
68 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
69 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
70 kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
71 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
72 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
73 kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */
74 kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */
75
76 kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
77 kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */
78 kSRAM3_RST_SHIFT_RSTn = 131072 | 6U, /**< SRAM3 reset control */
79 kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
80 kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */
81 kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
82 kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */
83 kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */
84 kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */
85 kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
86 kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
87 kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
88 kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */
89 kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */
90 kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */
91 kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */
92 kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */
93 } SYSCON_RSTn_t;
94
95 /** Array initializers with peripheral reset bits **/
96 #define ADC_RSTS \
97 { \
98 kADC0_RST_SHIFT_RSTn \
99 } /* Reset bits for ADC peripheral */
100 #define MCAN_RSTS \
101 { \
102 kMCAN_RST_SHIFT_RSTn \
103 } /* Reset bits for CAN peripheral */
104 #define CRC_RSTS \
105 { \
106 kCRC_RST_SHIFT_RSTn \
107 } /* Reset bits for CRC peripheral */
108 #define CTIMER_RSTS \
109 { \
110 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
111 kCTIMER4_RST_SHIFT_RSTn \
112 } /* Reset bits for CTIMER peripheral */
113 #define DMA_RSTS_N \
114 { \
115 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
116 } /* Reset bits for DMA peripheral */
117
118 #define FLEXCOMM_RSTS \
119 { \
120 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
121 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \
122 } /* Reset bits for FLEXCOMM peripheral */
123 #define GINT_RSTS \
124 { \
125 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
126 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
127 #define GPIO_RSTS_N \
128 { \
129 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
130 } /* Reset bits for GPIO peripheral */
131 #define INPUTMUX_RSTS \
132 { \
133 kMUX0_RST_SHIFT_RSTn \
134 } /* Reset bits for INPUTMUX peripheral */
135 #define IOCON_RSTS \
136 { \
137 kIOCON_RST_SHIFT_RSTn \
138 } /* Reset bits for IOCON peripheral */
139 #define FLASH_RSTS \
140 { \
141 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
142 } /* Reset bits for Flash peripheral */
143 #define MRT_RSTS \
144 { \
145 kMRT_RST_SHIFT_RSTn \
146 } /* Reset bits for MRT peripheral */
147 #define PINT_RSTS \
148 { \
149 kPINT_RST_SHIFT_RSTn \
150 } /* Reset bits for PINT peripheral */
151 #define CDOG_RSTS \
152 { \
153 kCDOG_RST_SHIFT_RSTn \
154 } /* Reset bits for CDOG peripheral */
155 #define RNG_RSTS \
156 { \
157 kRNG_RST_SHIFT_RSTn \
158 } /* Reset bits for RNG peripheral */
159 #define SCT_RSTS \
160 { \
161 kSCT0_RST_SHIFT_RSTn \
162 } /* Reset bits for SCT peripheral */
163 #define UTICK_RSTS \
164 { \
165 kUTICK_RST_SHIFT_RSTn \
166 } /* Reset bits for UTICK peripheral */
167 #define WWDT_RSTS \
168 { \
169 kWWDT_RST_SHIFT_RSTn \
170 } /* Reset bits for WWDT peripheral */
171 #define PLU_RSTS_N \
172 { \
173 kPLULUT_RST_SHIFT_RSTn \
174 } /* Reset bits for PLU peripheral */
175 #define OSTIMER_RSTS \
176 { \
177 kOSTIMER0_RST_SHIFT_RSTn \
178 } /* Reset bits for OSTIMER peripheral */
179 #define CASPER_RSTS \
180 { \
181 kCASPER_RST_SHIFT_RSTn \
182 } /* Reset bits for Casper peripheral */
183 #define HASHCRYPT_RSTS \
184 { \
185 kHASHCRYPT_RST_SHIFT_RSTn \
186 } /* Reset bits for Hashcrypt peripheral */
187 #define PUF_RSTS \
188 { \
189 kPUF_RST_SHIFT_RSTn \
190 } /* Reset bits for PUF peripheral */
191 typedef SYSCON_RSTn_t reset_ip_name_t;
192
193 /*******************************************************************************
194 * API
195 ******************************************************************************/
196 #if defined(__cplusplus)
197 extern "C" {
198 #endif
199
200 /*!
201 * @brief Assert reset to peripheral.
202 *
203 * Asserts reset signal to specified peripheral module.
204 *
205 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
206 * and reset bit position in the reset register.
207 */
208 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
209
210 /*!
211 * @brief Clear reset to peripheral.
212 *
213 * Clears reset signal to specified peripheral module, allows it to operate.
214 *
215 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
216 * and reset bit position in the reset register.
217 */
218 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
219
220 /*!
221 * @brief Reset peripheral module.
222 *
223 * Reset peripheral module.
224 *
225 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
226 * and reset bit position in the reset register.
227 */
228 void RESET_PeripheralReset(reset_ip_name_t peripheral);
229
230 /*!
231 * @brief Release peripheral module.
232 *
233 * Release peripheral module.
234 *
235 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
236 * and reset bit position in the reset register.
237 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)238 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
239 {
240 RESET_ClearPeripheralReset(peripheral);
241 }
242
243 #if defined(__cplusplus)
244 }
245 #endif
246
247 /*! @} */
248
249 #endif /* _FSL_RESET_H_ */
250
