1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_RESET_H_
11 #define _FSL_RESET_H_
12
13 #include <assert.h>
14 #include <stdbool.h>
15 #include <stdint.h>
16 #include <string.h>
17 #include "fsl_device_registers.h"
18
19 /*!
20 * @addtogroup reset
21 * @{
22 */
23
24 /*******************************************************************************
25 * Definitions
26 ******************************************************************************/
27
28 /*! @name Driver version */
29 /*@{*/
30 /*! @brief reset driver version 2.4.0 */
31 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
32 /*@}*/
33
34 /*!
35 * @brief Enumeration for peripheral reset control bits
36 *
37 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
38 */
39 typedef enum _SYSCON_RSTn
40 {
41 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
42 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
43 kEEPROM_RST_SHIFT_RSTn = 0 | 9U, /**< EEPROM reset control */
44 kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */
45 kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */
46 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
47 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
48 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
49 kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */
50 kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */
51 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
52 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
53 kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
54 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
55 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
56 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
57
58 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
59 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
60 kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */
61 kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */
62 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
63 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
64 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
65 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
66 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
67 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
68 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
69 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
70 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
71 kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */
72 kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */
73 kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */
74 kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */
75 kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */
76
77 kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */
78 kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */
79 kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */
80 kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */
81 kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */
82 kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */
83 kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */
84 kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */
85 kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */
86 kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */
87 kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */
88 kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
89 kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */
90 kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */
91 kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */
92 kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */
93 kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */
94 kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */
95 kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */
96
97 kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
98 kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
99 } SYSCON_RSTn_t;
100
101 /** Array initializers with peripheral reset bits **/
102 #define ADC_RSTS \
103 { \
104 kADC0_RST_SHIFT_RSTn \
105 } /* Reset bits for ADC peripheral */
106 #define AES_RSTS \
107 { \
108 kAES_RST_SHIFT_RSTn \
109 } /* Reset bits for AES peripheral */
110 #define CRC_RSTS \
111 { \
112 kCRC_RST_SHIFT_RSTn \
113 } /* Reset bits for CRC peripheral */
114 #define CTIMER_RSTS \
115 { \
116 kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
117 kCT32B4_RST_SHIFT_RSTn \
118 } /* Reset bits for CTIMER peripheral */
119 #define DMA_RSTS_N \
120 { \
121 kDMA_RST_SHIFT_RSTn \
122 } /* Reset bits for DMA peripheral */
123 #define DMIC_RSTS \
124 { \
125 kDMIC_RST_SHIFT_RSTn \
126 } /* Reset bits for DMIC peripheral */
127 #define EMC_RSTS \
128 { \
129 kEMC_RST_SHIFT_RSTn \
130 } /* Reset bits for EMC peripheral */
131 #define ETH_RST \
132 { \
133 kETH_RST_SHIFT_RSTn \
134 } /* Reset bits for EMC peripheral */
135 #define FLEXCOMM_RSTS \
136 { \
137 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
138 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \
139 } /* Reset bits for FLEXCOMM peripheral */
140 #define GINT_RSTS \
141 { \
142 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
143 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
144 #define GPIO_RSTS_N \
145 { \
146 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
147 kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \
148 } /* Reset bits for GPIO peripheral */
149 #define INPUTMUX_RSTS \
150 { \
151 kMUX_RST_SHIFT_RSTn \
152 } /* Reset bits for INPUTMUX peripheral */
153 #define IOCON_RSTS \
154 { \
155 kIOCON_RST_SHIFT_RSTn \
156 } /* Reset bits for IOCON peripheral */
157 #define FLASH_RSTS \
158 { \
159 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
160 } /* Reset bits for Flash peripheral */
161 #define LCD_RSTS \
162 { \
163 kLCD_RST_SHIFT_RSTn \
164 } /* Reset bits for LCD peripheral */
165 #define MRT_RSTS \
166 { \
167 kMRT_RST_SHIFT_RSTn \
168 } /* Reset bits for MRT peripheral */
169 #define MCAN_RSTS \
170 { \
171 kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
172 } /* Reset bits for MCAN0&MACN1 peripheral */
173 #define OTP_RSTS \
174 { \
175 kOTP_RST_SHIFT_RSTn \
176 } /* Reset bits for OTP peripheral */
177 #define PINT_RSTS \
178 { \
179 kPINT_RST_SHIFT_RSTn \
180 } /* Reset bits for PINT peripheral */
181 #define RNG_RSTS \
182 { \
183 kRNG_RST_SHIFT_RSTn \
184 } /* Reset bits for RNG peripheral */
185 #define SDIO_RST \
186 { \
187 kSDIO_RST_SHIFT_RSTn \
188 } /* Reset bits for SDIO peripheral */
189 #define SCT_RSTS \
190 { \
191 kSCT0_RST_SHIFT_RSTn \
192 } /* Reset bits for SCT peripheral */
193 #define SHA_RST \
194 { \
195 kSHA_RST_SHIFT_RSTn \
196 } /* Reset bits for SHA peripheral */
197 #define SPIFI_RSTS \
198 { \
199 kSPIFI_RST_SHIFT_RSTn \
200 } /* Reset bits for SPIFI peripheral */
201 #define USB0D_RST \
202 { \
203 kUSB0D_RST_SHIFT_RSTn \
204 } /* Reset bits for USB0D peripheral */
205 #define USB0HMR_RST \
206 { \
207 kUSB0HMR_RST_SHIFT_RSTn \
208 } /* Reset bits for USB0HMR peripheral */
209 #define USB0HSL_RST \
210 { \
211 kUSB0HSL_RST_SHIFT_RSTn \
212 } /* Reset bits for USB0HSL peripheral */
213 #define USB1H_RST \
214 { \
215 kUSB1H_RST_SHIFT_RSTn \
216 } /* Reset bits for USB1H peripheral */
217 #define USB1D_RST \
218 { \
219 kUSB1D_RST_SHIFT_RSTn \
220 } /* Reset bits for USB1D peripheral */
221 #define USB1RAM_RST \
222 { \
223 kUSB1RAM_RST_SHIFT_RSTn \
224 } /* Reset bits for USB1RAM peripheral */
225 #define UTICK_RSTS \
226 { \
227 kUTICK_RST_SHIFT_RSTn \
228 } /* Reset bits for UTICK peripheral */
229 #define WWDT_RSTS \
230 { \
231 kWWDT_RST_SHIFT_RSTn \
232 } /* Reset bits for WWDT peripheral */
233
234 typedef SYSCON_RSTn_t reset_ip_name_t;
235 #define USB1RAM_RSTS USB1RAM_RST
236 #define USB1H_RSTS USB1H_RST
237 #define USB1D_RSTS USB1D_RST
238 #define USB0HSL_RSTS USB0HSL_RST
239 #define USB0HMR_RSTS USB0HMR_RST
240 #define USB0D_RSTS USB0D_RST
241 #define SHA_RSTS SHA_RST
242 #define SDIO_RSTS SDIO_RST
243 #define ETH_RSTS ETH_RST
244
245 /*******************************************************************************
246 * API
247 ******************************************************************************/
248 #if defined(__cplusplus)
249 extern "C" {
250 #endif
251
252 /*!
253 * @brief Assert reset to peripheral.
254 *
255 * Asserts reset signal to specified peripheral module.
256 *
257 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
258 * and reset bit position in the reset register.
259 */
260 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
261
262 /*!
263 * @brief Clear reset to peripheral.
264 *
265 * Clears reset signal to specified peripheral module, allows it to operate.
266 *
267 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
268 * and reset bit position in the reset register.
269 */
270 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
271
272 /*!
273 * @brief Reset peripheral module.
274 *
275 * Reset peripheral module.
276 *
277 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
278 * and reset bit position in the reset register.
279 */
280 void RESET_PeripheralReset(reset_ip_name_t peripheral);
281
282 /*!
283 * @brief Release peripheral module.
284 *
285 * Release peripheral module.
286 *
287 * @param peripheral Peripheral to release. The enum argument contains encoding of reset register
288 * and reset bit position in the reset register.
289 */
RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)290 static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
291 {
292 RESET_ClearPeripheralReset(peripheral);
293 }
294
295 #if defined(__cplusplus)
296 }
297 #endif
298
299 /*! @} */
300
301 #endif /* _FSL_RESET_H_ */
302
