1 //*****************************************************************************
2 // LPC5411x startup code for use with MCUXpresso IDE
3 //
4 // Version : 161214
5 //*****************************************************************************
6 //
7 // Copyright 2016, NXP
8 // All rights reserved.
9 //
10 // Software that is described herein is for illustrative purposes only
11 // which provides customers with programming information regarding the
12 // LPC products. This software is supplied "AS IS" without any warranties of
13 // any kind, and NXP Semiconductors and its licensor disclaim any and
14 // all warranties, express or implied, including all implied warranties of
15 // merchantability, fitness for a particular purpose and non-infringement of
16 // intellectual property rights. NXP Semiconductors assumes no responsibility
17 // or liability for the use of the software, conveys no license or rights under any
18 // patent, copyright, mask work right, or any other intellectual property rights in
19 // or to any products. NXP Semiconductors reserves the right to make changes
20 // in the software without notification. NXP Semiconductors also makes no
21 // representation or warranty that such application will be suitable for the
22 // specified use without further testing or modification.
23 //
24 // Permission to use, copy, modify, and distribute this software and its
25 // documentation is hereby granted, under NXP Semiconductors' and its
26 // licensor's relevant copyrights in the software, without fee, provided that it
27 // is used in conjunction with NXP Semiconductors microcontrollers. This
28 // copyright, permission, and disclaimer notice must appear in all copies of
29 // this code.
30 //*****************************************************************************
31
32 #if defined (DEBUG)
33 #pragma GCC push_options
34 #pragma GCC optimize ("Og")
35 #endif // (DEBUG)
36
37 #if defined (__cplusplus)
38 #ifdef __REDLIB__
39 #error Redlib does not support C++
40 #else
41 //*****************************************************************************
42 //
43 // The entry point for the C++ library startup
44 //
45 //*****************************************************************************
46 extern "C" {
47 extern void __libc_init_array(void);
48 }
49 #endif
50 #endif
51
52 #define WEAK __attribute__ ((weak))
53 #define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
54 #define ALIAS(f) __attribute__ ((weak, alias (#f)))
55
56 //*****************************************************************************
57 #if defined (__cplusplus)
58 extern "C" {
59 #endif
60
61 //*****************************************************************************
62 // Variable to store CRP value in. Will be placed automatically
63 // by the linker when "Enable Code Read Protect" selected.
64 // See crp.h header for more information
65 //*****************************************************************************
66 #if !defined (CORE_M0PLUS)
67 #include <NXP/crp.h>
68 __CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
69 #endif
70
71 //*****************************************************************************
72 // Declaration of external SystemInit function
73 //*****************************************************************************
74 #if defined (__USE_CMSIS)
75 extern void SystemInit(void);
76 #endif // (__USE_CMSIS)
77
78 //*****************************************************************************
79 #if !defined (DONT_ENABLE_SWVTRACECLK) && !defined (CORE_M0PLUS)
80 // Allow confirmation that SWV trace has been enabled
81 unsigned int __SWVtrace_Enabled;
82 #endif
83
84 //*****************************************************************************
85 // Forward declaration of the core exception handlers.
86 // When the application defines a handler (with the same name), this will
87 // automatically take precedence over these weak definitions
88 //*****************************************************************************
89 void ResetISR(void);
90 #if defined (__MULTICORE_MASTER)
91 void ResetISR2(void);
92 #endif
93 WEAK void NMI_Handler(void);
94 WEAK void HardFault_Handler(void);
95 WEAK void MemManage_Handler(void);
96 WEAK void BusFault_Handler(void);
97 WEAK void UsageFault_Handler(void);
98 WEAK void SVC_Handler(void);
99 WEAK void DebugMon_Handler(void);
100 WEAK void PendSV_Handler(void);
101 WEAK void SysTick_Handler(void);
102 WEAK void IntDefaultHandler(void);
103
104 //*****************************************************************************
105 // Forward declaration of the application IRQ handlers. When the application
106 // defines a handler (with the same name), this will automatically take
107 // precedence over weak definitions below
108 //*****************************************************************************
109 // External Interrupts - Available on M0+/M4
110 WEAK void WDT_BOD_IRQHandler(void);
111 WEAK void DMA0_IRQHandler(void);
112 WEAK void GINT0_IRQHandler(void);
113 WEAK void GINT1_IRQHandler(void);
114 WEAK void PIN_INT0_IRQHandler(void);
115 WEAK void PIN_INT1_IRQHandler(void);
116 WEAK void PIN_INT2_IRQHandler(void);
117 WEAK void PIN_INT3_IRQHandler(void);
118 WEAK void UTICK0_IRQHandler(void);
119 WEAK void MRT0_IRQHandler(void);
120 WEAK void CTIMER0_IRQHandler(void);
121 WEAK void CTIMER1_IRQHandler(void);
122 WEAK void SCT0_IRQHandler(void);
123 WEAK void CTIMER3_IRQHandler(void);
124 WEAK void FLEXCOMM0_IRQHandler(void);
125 WEAK void FLEXCOMM1_IRQHandler(void);
126 WEAK void FLEXCOMM2_IRQHandler(void);
127 WEAK void FLEXCOMM3_IRQHandler(void);
128 WEAK void FLEXCOMM4_IRQHandler(void);
129 WEAK void FLEXCOMM5_IRQHandler(void);
130 WEAK void FLEXCOMM6_IRQHandler(void);
131 WEAK void FLEXCOMM7_IRQHandler(void);
132 WEAK void ADC0_SEQA_IRQHandler(void);
133 WEAK void ADC0_SEQB_IRQHandler(void);
134 WEAK void ADC0_THCMP_IRQHandler(void);
135 WEAK void DMIC0_IRQHandler(void);
136 WEAK void HWVAD0_IRQHandler(void);
137 WEAK void USB0_NEEDCLK_IRQHandler(void);
138 WEAK void USB0_IRQHandler(void);
139 WEAK void RTC_IRQHandler(void);
140 WEAK void IOH_IRQHandler(void);
141 WEAK void MAILBOX_IRQHandler(void);
142 // External Interrupts - For M4 only
143 #if defined (CORE_M4)
144 WEAK void PIN_INT4_IRQHandler(void);
145 WEAK void PIN_INT5_IRQHandler(void);
146 WEAK void PIN_INT6_IRQHandler(void);
147 WEAK void PIN_INT7_IRQHandler(void);
148 WEAK void CTIMER2_IRQHandler(void);
149 WEAK void CTIMER4_IRQHandler(void);
150 WEAK void Reserved54_IRQHandler(void);
151 WEAK void SPIFI0_IRQHandler(void);
152 #endif
153
154 //*****************************************************************************
155 // Forward declaration of the driver IRQ handlers. These are aliased
156 // to the IntDefaultHandler, which is a 'forever' loop. When the driver
157 // defines a handler (with the same name), this will automatically take
158 // precedence over these weak definitions
159 //*****************************************************************************
160 // External Interrupts - Available on M0+/M4
161 void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
162 void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
163 void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
164 void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
165 void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
166 void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
167 void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
168 void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
169 void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
170 void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
171 void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
172 void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
173 void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
174 void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
175 void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
176 void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
177 void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
178 void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
179 void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
180 void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
181 void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
182 void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
183 void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
184 void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
185 void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
186 void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
187 void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
188 void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
189 void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
190 void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
191 void IOH_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
192 void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
193 // External Interrupts - For M4 only
194 #if defined (CORE_M4)
195 void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
196 void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
197 void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
198 void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
199 void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
200 void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
201 void Reserved54_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
202 void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
203 #endif
204
205 //*****************************************************************************
206 // The entry point for the application.
207 // __main() is the entry point for Redlib based applications
208 // main() is the entry point for Newlib based applications
209 //*****************************************************************************
210 #if defined (__REDLIB__)
211 extern void __main(void);
212 #endif
213 extern int main(void);
214
215 //*****************************************************************************
216 // External declaration for the pointer to the stack top from the Linker Script
217 //*****************************************************************************
218 extern void _vStackTop(void);
219
220 //*****************************************************************************
221 //
222 // External declaration for LPC MCU vector table checksum from Linker Script
223 //
224 //*****************************************************************************
225 WEAK extern void __valid_user_code_checksum();
226
227 //*****************************************************************************
228 #if defined (__cplusplus)
229 } // extern "C"
230 #endif
231
232 //*****************************************************************************
233 // The vector table.
234 // This relies on the linker script to place at correct location in memory.
235 //*****************************************************************************
236 extern void (* const g_pfnVectors[])(void);
237 extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
238
239 __attribute__ ((section(".isr_vector")))
240 void (* const g_pfnVectors[])(void) = {
241 #if defined (CORE_M4)
242 // Core Level - CM4
243 &_vStackTop, // The initial stack pointer
244 ResetISR, // The reset handler
245 NMI_Handler, // The NMI handler
246 HardFault_Handler, // The hard fault handler
247 MemManage_Handler, // The MPU fault handler
248 BusFault_Handler, // The bus fault handler
249 UsageFault_Handler, // The usage fault handler
250 __valid_user_code_checksum, // LPC MCU Checksum
251 0, // Reserved
252 0, // Reserved
253 0, // Reserved
254 SVC_Handler, // SVCall handler
255 DebugMon_Handler, // Debug monitor handler
256 0, // Reserved
257 PendSV_Handler, // The PendSV handler
258 SysTick_Handler, // The SysTick handler
259 #else
260 // Core Level - CM0plus
261 &_vStackTop, // The initial stack pointer
262 ResetISR, // The reset handler
263 NMI_Handler, // The NMI handler
264 HardFault_Handler, // The hard fault handler
265 0, // Reserved
266 0, // Reserved
267 0, // Reserved
268 0, // Reserved
269 0, // Reserved
270 0, // Reserved
271 0, // Reserved
272 SVC_Handler, // SVCall handler
273 0, // Reserved
274 0, // Reserved
275 PendSV_Handler, // The PendSV handler
276 SysTick_Handler, // The SysTick handler
277 #endif
278
279 // External Interrupts - Available on M0+/M4
280 WDT_BOD_IRQHandler, // 16: Windowed watchdog timer / Brownout detect
281 DMA0_IRQHandler, // 17: DMA controller
282 GINT0_IRQHandler, // 18: GPIO group 0
283 GINT1_IRQHandler, // 19: GPIO group 1
284 PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0
285 PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1
286 PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2
287 PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3
288 UTICK0_IRQHandler, // 24: Micro-tick Timer
289 MRT0_IRQHandler, // 25: Multi-rate timer
290 CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0
291 CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1
292 SCT0_IRQHandler, // 28: SCTimer/PWM
293 CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3
294 FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART
295 FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART
296 FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART
297 FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART
298 FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART
299 FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART
300 FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART
301 FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART
302 ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion
303 ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion
304 ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error
305 DMIC0_IRQHandler, // 41: Digital microphone and DMIC subsystem
306 HWVAD0_IRQHandler, // 42: Hardware Voice Activity Detector
307 USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt
308 USB0_IRQHandler, // 44: USB device
309 RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts
310 IOH_IRQHandler, // 46: IOH
311 MAILBOX_IRQHandler, // 47: Mailbox interrupt (present on selected devices)
312 // External Interrupts - For M4 only
313 #if defined (CORE_M4)
314 PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int
315 PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int
316 PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int
317 PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int
318 CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2
319 CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4
320 Reserved54_IRQHandler, // 54: Reserved interrupt
321 SPIFI0_IRQHandler, // 55: SPI flash interface
322 #endif
323
324 }; /* End of g_pfnVectors */
325
326 //*****************************************************************************
327 // Functions to carry out the initialization of RW and BSS data sections. These
328 // are written as separate functions rather than being inlined within the
329 // ResetISR() function in order to cope with MCUs with multiple banks of
330 // memory.
331 //*****************************************************************************
332 __attribute__ ((section(".after_vectors.init_data")))
data_init(unsigned int romstart,unsigned int start,unsigned int len)333 void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
334 unsigned int *pulDest = (unsigned int*) start;
335 unsigned int *pulSrc = (unsigned int*) romstart;
336 unsigned int loop;
337 for (loop = 0; loop < len; loop = loop + 4)
338 *pulDest++ = *pulSrc++;
339 }
340
341 __attribute__ ((section(".after_vectors.init_bss")))
bss_init(unsigned int start,unsigned int len)342 void bss_init(unsigned int start, unsigned int len) {
343 unsigned int *pulDest = (unsigned int*) start;
344 unsigned int loop;
345 for (loop = 0; loop < len; loop = loop + 4)
346 *pulDest++ = 0;
347 }
348
349 //*****************************************************************************
350 // The following symbols are constructs generated by the linker, indicating
351 // the location of various points in the "Global Section Table". This table is
352 // created by the linker via the Code Red managed linker script mechanism. It
353 // contains the load address, execution address and length of each RW data
354 // section and the execution and length of each BSS (zero initialized) section.
355 //*****************************************************************************
356 extern unsigned int __data_section_table;
357 extern unsigned int __data_section_table_end;
358 extern unsigned int __bss_section_table;
359 extern unsigned int __bss_section_table_end;
360
361 //*****************************************************************************
362 // Reset entry point for your code.
363 // Sets up a simple runtime environment and initializes the C/C++
364 // library.
365 //*****************************************************************************
366
367 #if defined (__MULTICORE_MASTER)
368 //#define cpu_ctrl 0x40000800
369 //#define coproc_boot 0x40000804
370 //#define set coproc_stack 0x40000808
371 __attribute__ ((naked, section(".after_vectors.reset")))
ResetISR(void)372 void ResetISR(void) {
373 asm volatile(
374 ".set cpu_ctrl, 0x40000800\t\n"
375 ".set coproc_boot, 0x40000804\t\n"
376 ".set coproc_stack, 0x40000808\t\n"
377 "MOVS R5, #1\t\n"
378 "LDR R0, =0xE000ED00\t\n"
379 "LDR R1, [R0]\t\n" // READ CPUID register
380 "LDR R2,=0x410CC601\t\n" // CM0 R0p1 identifier
381 "EORS R1,R1,R2\t\n" // XOR to see if we are C0
382 "LDR R3, =cpu_ctrl\t\n" // get address of CPU_CTRL
383 "LDR R1,[R3]\t\n" // read cpu_ctrl reg into R1
384 "BEQ.N cm0_boot\t\n"
385 "cm4_boot:\t\n"
386 "LDR R0,=coproc_boot\t\n" // coproc boot address
387 "LDR R0,[R0]\t\n" // get address to branch to
388 "MOVS R0,R0\t\n" // Check if 0
389 "BEQ.N check_master_m4\t\n" // if zero in boot reg, we just branch to real reset
390 "BX R0\t\n" // otherwise, we branch to boot address
391 "commonboot:\t\n"
392 "LDR R0, =ResetISR2\t\n" // Jump to 'real' reset handler
393 "BX R0\t\n"
394 "cm0_boot:\t\n"
395 "LDR R0,=coproc_boot\t\n" // coproc boot address
396 "LDR R0,[R0]\t\n" // get address to branch to
397 "MOVS R0,R0\t\n" // Check if 0
398 "BEQ.N check_master_m0\t\n" // if zero in boot reg, we just branch to real reset
399 "LDR R1,=coproc_stack\t\n" // pickup coprocesor stackpointer (from syscon CPSTACK)
400 "LDR R1,[R1]\t\n"
401 "MOV SP,R1\t\n"
402 "BX R0\t\n" // goto boot address
403 "check_master_m0:\t\n"
404 "ANDS R1,R1,R5\t\n" // bit test bit0
405 "BEQ.N commonboot\t\n" // if we get 0, that means we are masters
406 "B.N goto_sleep_pending_reset\t\n" // Otherwise, there is no startup vector for slave, so we go to sleep
407 "check_master_m4:\t\n"
408 "ANDS R1,R1,R5\t\n" // bit test bit0
409 "BNE.N commonboot\t\n" // if we get 1, that means we are masters
410 "goto_sleep_pending_reset:\t\n"
411 "MOV SP,R5\t\n" // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup
412 // and write to uninitialised Stack area (instead it will LOCK us up before we cause damage)
413 // this code should only be reached if debugger bypassed ROM or we changed master without giving
414 // correct start address, the only way out of this is through a debugger change of SP and PC
415 "sleepo:\t\n"
416 "WFI\t\n" // go to sleep
417 "B.N sleepo\t\n"
418 );
419 }
420
ResetISR2(void)421 void ResetISR2(void) {
422
423 #else
424 __attribute__ ((section(".after_vectors.reset")))
425 void ResetISR(void) {
426 #endif
427
428 // Disable interrupts
429 __asm volatile ("cpsid i");
430
431 // If this is not the CM0+ core...
432 #if !defined (CORE_M0PLUS)
433 // If this is not a slave project...
434 #if !defined (__MULTICORE_M0SLAVE)
435 // Optionally enable RAM banks that may be off by default at reset
436 #if !defined (DONT_ENABLE_DISABLED_RAMBANKS)
437 volatile unsigned int *SYSCON_AHBCLKCTRLSET0 = (unsigned int *) 0x40000220;
438 // Ensure that SRAM2(4) in SYSAHBCLKCTRL0 set
439 *SYSCON_AHBCLKCTRLSET0 = (1 << 4);
440 #endif
441 #endif
442 #endif
443
444 #if defined (__USE_CMSIS)
445 // If __USE_CMSIS defined, then call CMSIS SystemInit code
446 SystemInit();
447 #endif // (__USE_CMSIS)
448
449 //
450 // Copy the data sections from flash to SRAM.
451 //
452 unsigned int LoadAddr, ExeAddr, SectionLen;
453 unsigned int *SectionTableAddr;
454
455 // Load base address of Global Section Table
456 SectionTableAddr = &__data_section_table;
457
458 // Copy the data sections from flash to SRAM.
459 while (SectionTableAddr < &__data_section_table_end) {
460 LoadAddr = *SectionTableAddr++;
461 ExeAddr = *SectionTableAddr++;
462 SectionLen = *SectionTableAddr++;
463 data_init(LoadAddr, ExeAddr, SectionLen);
464 }
465
466 // At this point, SectionTableAddr = &__bss_section_table;
467 // Zero fill the bss segment
468 while (SectionTableAddr < &__bss_section_table_end) {
469 ExeAddr = *SectionTableAddr++;
470 SectionLen = *SectionTableAddr++;
471 bss_init(ExeAddr, SectionLen);
472 }
473
474 // Optionally enable Cortex-M4 SWV trace (off by default at reset)
475 // Note - your board support must also set up pinmuxing such that
476 // SWO is output on GPIO PIO0-15 (FUNC2) or PIO1_1 (FUNC2).
477 #if !defined (DONT_ENABLE_SWVTRACECLK) && !defined (CORE_M0PLUS)
478 volatile unsigned int *TRACECLKDIV = (unsigned int *) 0x40000304;
479 volatile unsigned int *SYSAHBCLKCTRLSET = (unsigned int *) 0x40000220;
480 volatile unsigned int *SYSAHBCLKCTRL = (unsigned int *) 0x40000200;
481 // Write 0x00000000 to TRACECLKDIV - Trace divider
482 *TRACECLKDIV = 0;
483 // Enable IOCON peripheral clock (for SWO on PIO0-15 or PIO1_1)
484 // by setting bit13 via SYSAHBCLKCTRLSET[0]
485 *SYSAHBCLKCTRLSET = 1 << 13; // 0x2000
486 // Read SYSAHBCLKCTRL[0] and check bit 13
487 __SWVtrace_Enabled = ((*SYSAHBCLKCTRL & 1 << 13) == 1 << 13);
488 #endif
489
490 #if !defined (__USE_CMSIS)
491 // Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
492 // will enable the FPU
493 #if defined (__VFP_FP__) && !defined (__SOFTFP__)
494 //
495 // Code to enable the Cortex-M4 FPU only included
496 // if appropriate build options have been selected.
497 // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
498 //
499 // Read CPACR (located at address 0xE000ED88)
500 // Set bits 20-23 to enable CP10 and CP11 coprocessors
501 // Write back the modified value to the CPACR
502 asm volatile ("LDR.W R0, =0xE000ED88\n\t"
503 "LDR R1, [R0]\n\t"
504 "ORR R1, R1, #(0xF << 20)\n\t"
505 "STR R1, [R0]");
506 #endif // (__VFP_FP__) && !(__SOFTFP__)
507 #endif // (__USE_CMSIS)
508
509 #if !defined (__USE_CMSIS)
510 // Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
511 // will setup the VTOR register
512
513 // Check to see if we are running the code from a non-zero
514 // address (eg RAM, external flash), in which case we need
515 // to modify the VTOR register to tell the CPU that the
516 // vector table is located at a non-0x0 address.
517 unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
518 if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
519 *pSCB_VTOR = (unsigned int)g_pfnVectors;
520 }
521 #endif // (__USE_CMSIS)
522
523 #if defined (__cplusplus)
524 //
525 // Call C++ library initialisation
526 //
527 __libc_init_array();
528 #endif
529
530 // Reenable interrupts
531 __asm volatile ("cpsie i");
532
533 #if defined (__REDLIB__)
534 // Call the Redlib library, which in turn calls main()
535 __main() ;
536 #else
537 main();
538 #endif
539
540 //
541 // main() shouldn't return, but if it does, we'll just enter an infinite loop
542 //
543 while (1) {
544 ;
545 }
546 }
547
548 //*****************************************************************************
549 // Default core exception handlers. Override the ones here by defining your own
550 // handler routines in your application code.
551 //*****************************************************************************
552 WEAK_AV void NMI_Handler(void)
553 { while(1) {}
554 }
555
556 WEAK_AV void HardFault_Handler(void)
557 { while(1) {}
558 }
559
560 WEAK_AV void SVC_Handler(void)
561 { while(1) {}
562 }
563
564 WEAK_AV void PendSV_Handler(void)
565 { while(1) {}
566 }
567
568 WEAK_AV void SysTick_Handler(void)
569 { while(1) {}
570 }
571
572 // Core Level Interrupts - For M4 only
573 #if defined (CORE_M4)
574 WEAK_AV void MemManage_Handler(void)
575 { while(1) {}
576 }
577
578 WEAK_AV void BusFault_Handler(void)
579 { while(1) {}
580 }
581
582 WEAK_AV void UsageFault_Handler(void)
583 { while(1) {}
584 }
585
586 WEAK_AV void DebugMon_Handler(void)
587 { while(1) {}
588 }
589 #endif // External Interrupts - For M4 only
590
591 //*****************************************************************************
592 // Processor ends up here if an unexpected interrupt occurs or a specific
593 // handler is not present in the application code.
594 //*****************************************************************************
595 WEAK_AV void IntDefaultHandler(void)
596 { while(1) {}
597 }
598
599 //*****************************************************************************
600 // Default application exception handlers. Override the ones here by defining
601 // your own handler routines in your application code. These routines call
602 // driver exception handlers or IntDefaultHandler() if no driver exception
603 // handler is included.
604 //*****************************************************************************
605 WEAK void WDT_BOD_IRQHandler(void)
606 { WDT_BOD_DriverIRQHandler();
607 }
608
609 WEAK void DMA0_IRQHandler(void)
610 { DMA0_DriverIRQHandler();
611 }
612
613 WEAK void GINT0_IRQHandler(void)
614 { GINT0_DriverIRQHandler();
615 }
616
617 WEAK void GINT1_IRQHandler(void)
618 { GINT1_DriverIRQHandler();
619 }
620
621 WEAK void PIN_INT0_IRQHandler(void)
622 { PIN_INT0_DriverIRQHandler();
623 }
624
625 WEAK void PIN_INT1_IRQHandler(void)
626 { PIN_INT1_DriverIRQHandler();
627 }
628
629 WEAK void PIN_INT2_IRQHandler(void)
630 { PIN_INT2_DriverIRQHandler();
631 }
632
633 WEAK void PIN_INT3_IRQHandler(void)
634 { PIN_INT3_DriverIRQHandler();
635 }
636
637 WEAK void UTICK0_IRQHandler(void)
638 { UTICK0_DriverIRQHandler();
639 }
640
641 WEAK void MRT0_IRQHandler(void)
642 { MRT0_DriverIRQHandler();
643 }
644
645 WEAK void CTIMER0_IRQHandler(void)
646 { CTIMER0_DriverIRQHandler();
647 }
648
649 WEAK void CTIMER1_IRQHandler(void)
650 { CTIMER1_DriverIRQHandler();
651 }
652
653 WEAK void SCT0_IRQHandler(void)
654 { SCT0_DriverIRQHandler();
655 }
656
657 WEAK void CTIMER3_IRQHandler(void)
658 { CTIMER3_DriverIRQHandler();
659 }
660
661 WEAK void FLEXCOMM0_IRQHandler(void)
662 { FLEXCOMM0_DriverIRQHandler();
663 }
664
665 WEAK void FLEXCOMM1_IRQHandler(void)
666 { FLEXCOMM1_DriverIRQHandler();
667 }
668
669 WEAK void FLEXCOMM2_IRQHandler(void)
670 { FLEXCOMM2_DriverIRQHandler();
671 }
672
673 WEAK void FLEXCOMM3_IRQHandler(void)
674 { FLEXCOMM3_DriverIRQHandler();
675 }
676
677 WEAK void FLEXCOMM4_IRQHandler(void)
678 { FLEXCOMM4_DriverIRQHandler();
679 }
680
681 WEAK void FLEXCOMM5_IRQHandler(void)
682 { FLEXCOMM5_DriverIRQHandler();
683 }
684
685 WEAK void FLEXCOMM6_IRQHandler(void)
686 { FLEXCOMM6_DriverIRQHandler();
687 }
688
689 WEAK void FLEXCOMM7_IRQHandler(void)
690 { FLEXCOMM7_DriverIRQHandler();
691 }
692
693 WEAK void ADC0_SEQA_IRQHandler(void)
694 { ADC0_SEQA_DriverIRQHandler();
695 }
696
697 WEAK void ADC0_SEQB_IRQHandler(void)
698 { ADC0_SEQB_DriverIRQHandler();
699 }
700
701 WEAK void ADC0_THCMP_IRQHandler(void)
702 { ADC0_THCMP_DriverIRQHandler();
703 }
704
705 WEAK void DMIC0_IRQHandler(void)
706 { DMIC0_DriverIRQHandler();
707 }
708
709 WEAK void HWVAD0_IRQHandler(void)
710 { HWVAD0_DriverIRQHandler();
711 }
712
713 WEAK void USB0_NEEDCLK_IRQHandler(void)
714 { USB0_NEEDCLK_DriverIRQHandler();
715 }
716
717 WEAK void USB0_IRQHandler(void)
718 { USB0_DriverIRQHandler();
719 }
720
721 WEAK void RTC_IRQHandler(void)
722 { RTC_DriverIRQHandler();
723 }
724
725 WEAK void IOH_IRQHandler(void)
726 { IOH_DriverIRQHandler();
727 }
728
729 WEAK void MAILBOX_IRQHandler(void)
730 { MAILBOX_DriverIRQHandler();
731 }
732
733 // External Interrupts - For M4 only
734 #if defined (CORE_M4)
735 WEAK void PIN_INT4_IRQHandler(void)
736 { PIN_INT4_DriverIRQHandler();
737 }
738
739 WEAK void PIN_INT5_IRQHandler(void)
740 { PIN_INT5_DriverIRQHandler();
741 }
742
743 WEAK void PIN_INT6_IRQHandler(void)
744 { PIN_INT6_DriverIRQHandler();
745 }
746
747 WEAK void PIN_INT7_IRQHandler(void)
748 { PIN_INT7_DriverIRQHandler();
749 }
750
751 WEAK void CTIMER2_IRQHandler(void)
752 { CTIMER2_DriverIRQHandler();
753 }
754
755 WEAK void CTIMER4_IRQHandler(void)
756 { CTIMER4_DriverIRQHandler();
757 }
758
759 WEAK void Reserved54_IRQHandler(void)
760 { Reserved54_DriverIRQHandler();
761 }
762
763 WEAK void SPIFI0_IRQHandler(void)
764 { SPIFI0_DriverIRQHandler();
765 }
766 #endif // External Interrupts - For M4 only
767
768 //*****************************************************************************
769
770 #if defined (DEBUG)
771 #pragma GCC pop_options
772 #endif // (DEBUG)
773
