1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, 2021 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9 #ifndef _FSL_POWER_H_
10 #define _FSL_POWER_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup power */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief power driver version 2.1.0. */
26 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
27 /*@}*/
28
29 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
30 #define PDRCFG0 0x0U
31 #define PDRCFG1 0x1U
32
33 typedef enum pd_bits
34 {
35 kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
36 kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
37 kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
38 kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
39 kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
40 kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
41 kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
42 kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
43 kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
44 kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
45 kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
46 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
47 kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
48 kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
49 kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
50 kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
51 kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
52 kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
53 kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
54 kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
55 kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
56 kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
57 kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
58 kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
59
60 kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
61 kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
62 kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
63 kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
64 kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
65 kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
66
67 /*
68 This enum member has no practical meaning,it is used to avoid MISRA issue,
69 user should not trying to use it.
70 */
71 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
72 } pd_bit_t;
73
74 /* Power mode configuration API parameter */
75 typedef enum _power_mode_config
76 {
77 kPmu_Sleep = 0U,
78 kPmu_Deep_Sleep = 1U,
79 kPmu_Deep_PowerDown = 2U,
80 } power_mode_cfg_t;
81
82 /*!
83 * @brief The enumeration of BOD reset level.
84 */
85 typedef enum _power_bod_reset_level
86 {
87 kBod_ResetLevel0 = 0U, /*!< Reset Level0: 1.5V. */
88 kBod_ResetLevel1, /*!< Reset Level0: 1.85V. */
89 kBod_ResetLevel2, /*!< Reset Level0: 2.0V. */
90 kBod_ResetLevel3, /*!< Reset Level0: 2.3V. */
91 } power_bod_reset_level_t;
92
93 /*!
94 * @brief The enumeration of BOD interrupt level.
95 */
96 typedef enum _power_bod_interrupt_level
97 {
98 kBod_InterruptLevel0 = 0U, /*!< Interrupt level: 2.05V. */
99 kBod_InterruptLevel1, /*!< Interrupt level: 2.45V. */
100 kBod_InterruptLevel2, /*!< Interrupt level: 2.75V. */
101 kBod_InterruptLevel3, /*!< Interrupt level: 3s.05V. */
102 } power_bod_interrupt_level_t;
103
104 /*!
105 * @brief The configuration of power bod, including reset level, interrupt level, and so on.
106 */
107 typedef struct _power_bod_config
108 {
109 bool enableReset; /*!< Enable/disable BOD reset function. */
110 power_bod_reset_level_t resetLevel; /*!< BOD reset level, please refer to @ref power_bod_reset_level_t. */
111 bool enableInterrupt; /*!< Enable/disable BOD interrupt function. */
112 power_bod_interrupt_level_t
113 interruptLevel; /*!< BOD interrupt level, please refer to @ref power_bod_interrupt_level_t. */
114 } power_bod_config_t;
115
116 /*******************************************************************************
117 * API
118 ******************************************************************************/
119
120 #ifdef __cplusplus
121 extern "C" {
122 #endif
123
124 /*!
125 * @name Power Configuration
126 * @{
127 */
128
129 /*!
130 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
131 *
132 * @param en peripheral for which to enable the PDRUNCFG bit
133 * @return none
134 */
POWER_EnablePD(pd_bit_t en)135 static inline void POWER_EnablePD(pd_bit_t en)
136 {
137 /* PDRUNCFGSET */
138 SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
139 }
140
141 /*!
142 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
143 *
144 * @param en peripheral for which to disable the PDRUNCFG bit
145 * @return none
146 */
POWER_DisablePD(pd_bit_t en)147 static inline void POWER_DisablePD(pd_bit_t en)
148 {
149 /* PDRUNCFGCLR */
150 SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
151 }
152
153 /*!
154 * @brief API to enable deep sleep bit in the ARM Core.
155 *
156 * @return none
157 */
POWER_EnableDeepSleep(void)158 static inline void POWER_EnableDeepSleep(void)
159 {
160 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
161 }
162
163 /*!
164 * @brief API to disable deep sleep bit in the ARM Core.
165 *
166 * @return none
167 */
POWER_DisableDeepSleep(void)168 static inline void POWER_DisableDeepSleep(void)
169 {
170 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
171 }
172
173 /*!
174 * @brief Power Library API to reload OTP.
175 * This API must be called if VD6 is power down
176 * and power back again since FROHF TRIM value
177 * is store in OTP. If not, when calling FROHF settng
178 * API in clock driver then the FROHF clock out put
179 * will be inaccurate.
180 * @return none
181 */
182 void POWER_OtpReload(void);
183
184 /*!
185 * @brief Power Library API to power the PLLs.
186 *
187 * @return none
188 */
189 void POWER_SetPLL(void);
190
191 /*!
192 * @brief Power Library API to power the USB PHY.
193 *
194 * @return none
195 */
196 void POWER_SetUsbPhy(void);
197
198 /*!
199 * @brief Power Library API to enter different power mode.
200 *
201 * @param mode Power mode.
202 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
203 * during power mode selected.
204 * @return none
205 */
206 void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
207
208 /*!
209 * @brief Power Library API to enter sleep mode.
210 *
211 * @return none
212 */
213 void POWER_EnterSleep(void);
214
215 /*!
216 * @brief Power Library API to enter deep sleep mode.
217 *
218 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
219 * powered on during deep sleep
220 * @return none
221 */
222 void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
223
224 /*!
225 * @brief Power Library API to enter deep power down mode.
226 *
227 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
228 during deep power
229 * down mode, but this is has no effect as the voltages are cut off.
230
231 * @return none
232 */
233 void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
234
235 /*!
236 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
237 *
238 * @param freq - The desired frequency at which the part would like to operate,
239 * note that the voltage and flash wait states should be set before changing frequency
240 * @return none
241 */
242 void POWER_SetVoltageForFreq(uint32_t freq);
243
244 /*!
245 * @brief Power Library API to return the library version.
246 *
247 * @return version number of the power library
248 */
249 uint32_t POWER_GetLibVersion(void);
250
251 void POWER_InitBod(const power_bod_config_t *bodConfig);
252
253 void POWER_GetDefaultBodConfig(power_bod_config_t *bodConfig);
254
POWER_DeinitBod(void)255 static inline void POWER_DeinitBod(void)
256 {
257 SYSCON->BODCTRL &= ~(SYSCON_BODCTRL_BODRSTENA_MASK | SYSCON_BODCTRL_BODINTENA_MASK);
258 }
259
260 /*@}*/
261
262 #ifdef __cplusplus
263 }
264 #endif
265
266 /*@}*/
267
268 #endif /* _FSL_POWER_H_ */
269
