1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016, 2021, NXP
4  * All rights reserved.
5  *
6  *
7  * SPDX-License-Identifier: BSD-3-Clause
8  */
9 #ifndef _FSL_POWER_H_
10 #define _FSL_POWER_H_
11 
12 #include "fsl_common.h"
13 
14 /*! @addtogroup power */
15 /*! @{ */
16 
17 /*! @file */
18 
19 /*******************************************************************************
20  * Definitions
21  ******************************************************************************/
22 
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief power driver version 2.1.0. */
26 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
27 /*@}*/
28 
29 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
30 #define PDRCFG0                 0x0U
31 #define PDRCFG1                 0x1U
32 
33 typedef enum pd_bits
34 {
35     kPDRUNCFG_PD_FRO_EN    = MAKE_PD_BITS(PDRCFG0, 4U),
36     kPDRUNCFG_PD_FLASH     = MAKE_PD_BITS(PDRCFG0, 5U),
37     kPDRUNCFG_PD_TEMPS     = MAKE_PD_BITS(PDRCFG0, 6U),
38     kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
39     kPDRUNCFG_PD_BOD_INTR  = MAKE_PD_BITS(PDRCFG0, 8U),
40     kPDRUNCFG_PD_ADC0      = MAKE_PD_BITS(PDRCFG0, 10U),
41     kPDRUNCFG_PD_VDDFLASH  = MAKE_PD_BITS(PDRCFG0, 11U),
42     kPDRUNCFG_LP_VDDFLASH  = MAKE_PD_BITS(PDRCFG0, 12U),
43     kPDRUNCFG_PD_RAM0      = MAKE_PD_BITS(PDRCFG0, 13U),
44     kPDRUNCFG_PD_RAM1      = MAKE_PD_BITS(PDRCFG0, 14U),
45     kPDRUNCFG_PD_RAM2      = MAKE_PD_BITS(PDRCFG0, 15U),
46     kPDRUNCFG_PD_RAMX      = MAKE_PD_BITS(PDRCFG0, 16U),
47     kPDRUNCFG_PD_ROM       = MAKE_PD_BITS(PDRCFG0, 17U),
48     kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U),
49     kPDRUNCFG_PD_VD7_ENA   = MAKE_PD_BITS(PDRCFG0, 19U),
50     kPDRUNCFG_PD_WDT_OSC   = MAKE_PD_BITS(PDRCFG0, 20U),
51     kPDRUNCFG_PD_USB0_PHY  = MAKE_PD_BITS(PDRCFG0, 21U),
52     kPDRUNCFG_PD_SYS_PLL0  = MAKE_PD_BITS(PDRCFG0, 22U),
53     kPDRUNCFG_PD_VREFP_SW  = MAKE_PD_BITS(PDRCFG0, 23U),
54     kPDRUNCFG_PD_FLASH_BG  = MAKE_PD_BITS(PDRCFG0, 25U),
55 
56     kPDRUNCFG_PD_ALT_FLASH_IBG  = MAKE_PD_BITS(PDRCFG1, 28U),
57     kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U),
58 
59     kPDRUNCFG_ForceUnsigned = (int)0x80000000U
60 } pd_bit_t;
61 
62 /* Power mode configuration API parameter */
63 typedef enum _power_mode_config
64 {
65     kPmu_Sleep          = 0U,
66     kPmu_Deep_Sleep     = 1U,
67     kPmu_Deep_PowerDown = 2U,
68 } power_mode_cfg_t;
69 
70 /*!
71  * @brief The enumeration of BOD status flags.
72  */
73 typedef enum _power_bod_status
74 {
75     kBod_ResetStatusFlag     = SYSCON_BODCTRL_BODRSTSTAT_MASK, /*!< BOD reset has occurred. */
76     kBod_InterruptStatusFlag = SYSCON_BODCTRL_BODINTSTAT_MASK, /*!< BOD interrupt has occurred */
77 } power_bod_status_t;
78 
79 /*!
80  * @brief The enumeration of BOD reset level.
81  */
82 typedef enum _power_bod_reset_level
83 {
84     kBod_ResetLevel0 = 0U, /*!< Reset Level0: 1.5V. */
85     kBod_ResetLevel1,      /*!< Reset Level0: 1.85V. */
86     kBod_ResetLevel2,      /*!< Reset Level0: 2.0V. */
87     kBod_ResetLevel3,      /*!< Reset Level0: 2.3V. */
88 } power_bod_reset_level_t;
89 
90 /*!
91  * @brief The enumeration of BOD interrupt level.
92  */
93 typedef enum _power_bod_interrupt_level
94 {
95     kBod_InterruptLevel0 = 0U, /*!< Interrupt level: 2.05V. */
96     kBod_InterruptLevel1,      /*!< Interrupt level: 2.45V. */
97     kBod_InterruptLevel2,      /*!< Interrupt level: 2.75V. */
98     kBod_InterruptLevel3,      /*!< Interrupt level: 3.05V. */
99 } power_bod_interrupt_level_t;
100 
101 /*!
102  * @brief The configuration of power bod, including reset level, interrupt level, and so on.
103  */
104 typedef struct _power_bod_config
105 {
106     bool enableReset;                   /*!< Enable/disable BOD reset function. */
107     power_bod_reset_level_t resetLevel; /*!< BOD reset level, please refer to @ref power_bod_reset_level_t. */
108     bool enableInterrupt;               /*!< Enable/disable BOD interrupt function. */
109     power_bod_interrupt_level_t
110         interruptLevel; /*!< BOD interrupt level, please refer to @ref power_bod_interrupt_level_t. */
111 } power_bod_config_t;
112 
113 /*******************************************************************************
114  * API
115  ******************************************************************************/
116 
117 #ifdef __cplusplus
118 extern "C" {
119 #endif
120 
121 /*!
122  * @name Power Configuration
123  * @{
124  */
125 
126 /*!
127  * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
128  *
129  * @param en    peripheral for which to enable the PDRUNCFG bit
130  * @return none
131  */
POWER_EnablePD(pd_bit_t en)132 static inline void POWER_EnablePD(pd_bit_t en)
133 {
134     /* PDRUNCFGSET */
135     SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
136 }
137 
138 /*!
139  * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
140  *
141  * @param en    peripheral for which to disable the PDRUNCFG bit
142  * @return none
143  */
POWER_DisablePD(pd_bit_t en)144 static inline void POWER_DisablePD(pd_bit_t en)
145 {
146     /* PDRUNCFGCLR */
147     SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
148 }
149 
150 /*!
151  * @brief API to enable deep sleep bit in the ARM Core.
152  *
153  * @return none
154  */
POWER_EnableDeepSleep(void)155 static inline void POWER_EnableDeepSleep(void)
156 {
157     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
158 }
159 
160 /*!
161  * @brief API to disable deep sleep bit in the ARM Core.
162  *
163  * @return none
164  */
POWER_DisableDeepSleep(void)165 static inline void POWER_DisableDeepSleep(void)
166 {
167     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
168 }
169 
170 /*!
171  * @brief API to power down flash controller.
172  *
173  * @return none
174  */
POWER_PowerDownFlash(void)175 static inline void POWER_PowerDownFlash(void)
176 {
177 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
178     /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */
179     CLOCK_DisableClock(kCLOCK_Flash);
180 
181     /* TURN OFF clock for Flash Accelerator */
182     CLOCK_DisableClock(kCLOCK_Fmc);
183 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
184 }
185 
186 /*!
187  * @brief API to power up flash controller.
188  *
189  * @return none
190  */
POWER_PowerUpFlash(void)191 static inline void POWER_PowerUpFlash(void)
192 {
193 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
194     /* TURN ON clock for flash Accelerator */
195     CLOCK_EnableClock(kCLOCK_Fmc);
196 
197     /* TURN ON clock for flash Controller */
198     CLOCK_EnableClock(kCLOCK_Flash);
199 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
200 }
201 
202 /*!
203  * @brief Power Library API to enter different power mode.
204  *
205  * @param mode
206  * @param exclude_from_pd  Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
207  * @return none
208  */
209 void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
210 
211 /*!
212  * @brief Power Library API to enter sleep mode.
213  *
214  * @return none
215  */
216 void POWER_EnterSleep(void);
217 
218 /*!
219  * @brief Power Library API to enter deep sleep mode.
220  *
221  * @param exclude_from_pd  Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
222  * @return none
223  */
224 void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
225 
226 /*!
227  * @brief Power Library API to enter deep power down mode.
228  *
229  * @param exclude_from_pd  Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode,
230  *                         but this is has no effect as the voltages are cut off.
231  * @return none
232  */
233 void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
234 
235 /*!
236  * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
237  *
238  * @param freq  - The desired frequency at which the part would like to operate,
239  *                note that the voltage and flash wait states should be set before changing frequency
240  * @return none
241  */
242 void POWER_SetVoltageForFreq(uint32_t freq);
243 
244 /*!
245  * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency.
246  *
247  * @param freq  - The desired frequency at which the part would like to operate,
248  *                note only 12MHz and 48Mhz are supported
249  * @return none
250  */
251 void POWER_SetLowPowerVoltageForFreq(uint32_t freq);
252 
253 /*!
254  * @brief Power Library API to return the library version.
255  *
256  * @return version number of the power library
257  */
258 uint32_t POWER_GetLibVersion(void);
259 
260 /*!
261  * @brief Initialize BOD, including enabling/disabling BOD interrupt, enabling/disabling BOD reset, setting BOD
262  * interrupt level, and reset level.
263  *
264  * @param bodConfig Pointer the the structure @ref power_bod_config_t.
265  */
266 void POWER_InitBod(const power_bod_config_t *bodConfig);
267 
268 /*!
269  * @brief Get default BOD configuration.
270  *
271  * @code
272  *      bodConfig->enableReset = true;
273  *      bodConfig->resetLevel = kBod_ResetLevel0;
274  *      bodConfig->enableInterrupt = false;
275  *      bodConfig->interruptLevel = kBod_InterruptLevel0;
276  * @endcode
277  *
278  * @param bodConfig Pointer the the structure @ref power_bod_config_t.
279  */
280 void POWER_GetDefaultBodConfig(power_bod_config_t *bodConfig);
281 
282 /*!
283  * @brief De-initialize BOD.
284  *
285  */
POWER_DeinitBod(void)286 static inline void POWER_DeinitBod(void)
287 {
288     SYSCON->BODCTRL &= ~(SYSCON_BODCTRL_BODRSTENA_MASK | SYSCON_BODCTRL_BODINTENA_MASK);
289 }
290 
291 /*!
292  * @brief Get Bod status flags.
293  *
294  * @return Flags of Bod status.
295  */
POWER_GetBodStatusFlags(void)296 static inline uint32_t POWER_GetBodStatusFlags(void)
297 {
298     return (uint32_t)((SYSCON->BODCTRL) & (SYSCON_BODCTRL_BODRSTSTAT_MASK | SYSCON_BODCTRL_BODINTSTAT_MASK));
299 }
300 
301 /*!
302  * @brief Clear Bod status flags.
303  *
304  * @param mask The mask of status flags to clear, should be the OR'ed value of @ref power_bod_status_t.
305  */
POWER_ClearBodStatusFlags(uint32_t mask)306 static inline void POWER_ClearBodStatusFlags(uint32_t mask)
307 {
308     SYSCON->BODCTRL = mask;
309 }
310 
311 /* @} */
312 
313 #ifdef __cplusplus
314 }
315 #endif
316 
317 /*! @} */
318 
319 #endif /* _FSL_POWER_H_ */
320