1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, 2021 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_CLOCK_H_
11 #define _FSL_CLOCK_H_
12
13 #include "fsl_common.h"
14
15 /*! @addtogroup clock */
16 /*! @{ */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief CLOCK driver version 2.4.2. */
27 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
28 /*@}*/
29
30 /* Definition for delay API in clock driver, users can redefine it to the real application. */
31 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
32 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
33 #endif
34
35 /*!
36 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
37 *
38 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
39 * would cache the recent calulation and accelerate the execution to get the
40 * right settings.
41 */
42 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
43 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
44 #endif
45
46 /*! @brief Clock ip name array for FLEXCOMM. */
47 #define FLEXCOMM_CLOCKS \
48 { \
49 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
50 kCLOCK_FlexComm6, kCLOCK_FlexComm7 \
51 }
52 /*! @brief Clock ip name array for LPUART. */
53 #define LPUART_CLOCKS \
54 { \
55 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
56 kCLOCK_MinUart6, kCLOCK_MinUart7 \
57 }
58
59 /*! @brief Clock ip name array for BI2C. */
60 #define BI2C_CLOCKS \
61 { \
62 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
63 }
64 /*! @brief Clock ip name array for LSPI. */
65 #define LPSI_CLOCKS \
66 { \
67 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
68 }
69 /*! @brief Clock ip name array for FLEXI2S. */
70 #define FLEXI2S_CLOCKS \
71 { \
72 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
73 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
74 }
75 /*! @brief Clock ip name array for UTICK. */
76 #define UTICK_CLOCKS \
77 { \
78 kCLOCK_Utick \
79 }
80 /*! @brief Clock ip name array for DMA. */
81 #define DMA_CLOCKS \
82 { \
83 kCLOCK_Dma \
84 }
85 /*! @brief Clock ip name array for CT32B. */
86 #define CTIMER_CLOCKS \
87 { \
88 kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_IpInvalid, kCLOCK_Ctimer3 \
89 }
90
91 /*! @brief Clock ip name array for GPIO. */
92 #define GPIO_CLOCKS \
93 { \
94 kCLOCK_Gpio0, kCLOCK_Gpio1 \
95 }
96 /*! @brief Clock ip name array for ADC. */
97 #define ADC_CLOCKS \
98 { \
99 kCLOCK_Adc0 \
100 }
101 /*! @brief Clock ip name array for MRT. */
102 #define MRT_CLOCKS \
103 { \
104 kCLOCK_Mrt \
105 }
106 /*! @brief Clock ip name array for MRT. */
107 #define SCT_CLOCKS \
108 { \
109 kCLOCK_Sct0 \
110 }
111 /*! @brief Clock ip name array for RTC. */
112 #define RTC_CLOCKS \
113 { \
114 kCLOCK_Rtc \
115 }
116 /*! @brief Clock ip name array for WWDT. */
117 #define WWDT_CLOCKS \
118 { \
119 kCLOCK_Wwdt \
120 }
121 /*! @brief Clock ip name array for CRC. */
122 #define CRC_CLOCKS \
123 { \
124 kCLOCK_Crc \
125 }
126 /*! @brief Clock ip name array for USBD. */
127 #define USBD_CLOCKS \
128 { \
129 kCLOCK_Usbd0 \
130 }
131
132 /*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */
133 #define GINT_CLOCKS \
134 { \
135 kCLOCK_Gint, kCLOCK_Gint \
136 }
137
138 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
139 /*------------------------------------------------------------------------------
140 clock_ip_name_t definition:
141 ------------------------------------------------------------------------------*/
142
143 #define CLK_GATE_REG_OFFSET_SHIFT 8U
144 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
145 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
146 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
147
148 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
149 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
150 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
151
152 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
153 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
154
155 #define AHB_CLK_CTRL0 0
156 #define AHB_CLK_CTRL1 1
157 #define ASYNC_CLK_CTRL0 2
158
159 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
160 typedef enum _clock_ip_name
161 {
162 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
163 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
164
165 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
166
167 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
168
169 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
170
171 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
172
173 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
174
175 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
176
177 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
178
179 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint,
180 GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */
181 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma. */
182
183 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
184
185 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
186
187 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
188
189 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
190
191 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
192
193 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
194
195 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */
196
197 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
198
199 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
200
201 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
202
203 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
204
205 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
206
207 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
208
209 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
210
211 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
212
213 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
214
215 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
216
217 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
218
219 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
220
221 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
222
223 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
224
225 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
226
227 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
228
229 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
230
231 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
232
233 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
234
235 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
236
237 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
238
239 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
240
241 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
242
243 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
244
245 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
246
247 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
248
249 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
250
251 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
252
253 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
254
255 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
256
257 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
258
259 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
260
261 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
262
263 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
264
265 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
266
267 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
268
269 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
270
271 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
272
273 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
274
275 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
276
277 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Ct32b2. */
278
279 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */
280
281 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Ctimer0. */
282
283 kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Ctimer1. */
284
285 kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), /*!< Clock gate name: Ctimer3. */
286
287 } clock_ip_name_t;
288
289 /*! @brief Clock name used to get clock frequency. */
290 typedef enum _clock_name
291 {
292 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
293 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
294 kCLOCK_ClockOut, /*!< CLOCKOUT */
295 kCLOCK_FroHf, /*!< FRO48/96 */
296 kCLOCK_Fro12M, /*!< FRO12M */
297 kCLOCK_ExtClk, /*!< External Clock */
298 kCLOCK_PllOut, /*!< PLL Output */
299 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
300 kCLOCK_Frg, /*!< Frg Clock */
301 kCLOCK_AsyncApbClk, /*!< Async APB clock */
302 kCLOCK_FlexI2S, /*!< FlexI2S clock */
303 } clock_name_t;
304
305 /**
306 * @brief Clock source selections for the asynchronous APB clock.
307 */
308 typedef enum _async_clock_src
309 {
310 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
311 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
312 } async_clock_src_t;
313
314 /*! @brief Clock Mux Switches
315 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
316 * starting from LSB upwards
317 *
318 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
319 *
320 */
321
322 #define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
323 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
324 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
325
326 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
327 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
328 #define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
329 #define GET_ID_ITEM_SEL(connection) ((uint8_t)(((connection)&0xF00U) >> 8U) - 1U)
330 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
331
332 #define CM_MAINCLKSELA 0
333 #define CM_MAINCLKSELB 1
334 #define CM_CLKOUTCLKSELA 2
335 #define CM_CLKOUTCLKSELB 3
336 #define CM_SYSPLLCLKSEL 4
337 #define CM_USBPLLCLKSEL 5
338 #define CM_AUDPLLCLKSEL 6
339 #define CM_SCTPLLCLKSEL 7
340 #define CM_ADCASYNCCLKSEL 9
341 #define CM_USBCLKSEL 10
342 #define CM_USB1CLKSEL 11
343 #define CM_FXCOMCLKSEL0 12
344 #define CM_FXCOMCLKSEL1 13
345 #define CM_FXCOMCLKSEL2 14
346 #define CM_FXCOMCLKSEL3 15
347 #define CM_FXCOMCLKSEL4 16
348 #define CM_FXCOMCLKSEL5 17
349 #define CM_FXCOMCLKSEL6 18
350 #define CM_FXCOMCLKSEL7 19
351 #define CM_FXCOMCLKSEL8 20
352 #define CM_FXCOMCLKSEL9 21
353 #define CM_FXCOMCLKSEL10 22
354 #define CM_FXCOMCLKSEL11 23
355 #define CM_FXI2S0MCLKCLKSEL 24
356 #define CM_FXI2S1MCLKCLKSEL 25
357 #define CM_FRGCLKSEL 26
358
359 #define CM_ASYNCAPB 28U
360
361 /*!
362 * @brief The enumerator of clock attach Id.
363 */
364 typedef enum _clock_attach_id
365 {
366
367 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
368
369 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
370
371 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach WDT_OSC to MAIN_CLK. */
372
373 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
374
375 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach SYS_PLL to MAIN_CLK. */
376
377 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
378
379 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), /*!< Attach FRO12M to SYS_PLL. */
380
381 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), /*!< Attach EXT_CLK to SYS_PLL. */
382
383 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), /*!< Attach WDT_OSC to SYS_PLL. */
384
385 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), /*!< Attach OSC32K to SYS_PLL. */
386
387 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), /*!< Attach NONE to SYS_PLL. */
388
389 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Attach MAIN_CLK to ASYNC_APB. */
390
391 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Attach FRO12M to ASYNC_APB. */
392
393 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */
394
395 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach SYS_PLL to ADC_CLK. */
396
397 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */
398
399 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
400
401 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach FRO12M to FLEXCOMM0. */
402
403 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach FRO_HF to FLEXCOMM0. */
404
405 kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach SYS_PLL to FLEXCOMM0. */
406
407 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach MCLK to FLEXCOMM0. */
408
409 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRG to FLEXCOMM0. */
410
411 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
412
413 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach FRO12M to FLEXCOMM1. */
414
415 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach FRO_HF to FLEXCOMM1. */
416
417 kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach SYS_PLL to FLEXCOMM1. */
418
419 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach MCLK to FLEXCOMM1. */
420
421 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRG to FLEXCOMM1. */
422
423 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
424
425 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach FRO12M to FLEXCOMM2. */
426
427 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach FRO_HF to FLEXCOMM2. */
428
429 kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach SYS_PLL to FLEXCOMM2. */
430
431 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach MCLK to FLEXCOMM2. */
432
433 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRG to FLEXCOMM2. */
434
435 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
436
437 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach FRO12M to FLEXCOMM3. */
438
439 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach FRO_HF to FLEXCOMM3. */
440
441 kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach SYS_PLL to FLEXCOMM3. */
442
443 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach MCLK to FLEXCOMM3. */
444
445 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRG to FLEXCOMM3. */
446
447 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
448
449 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach FRO12M to FLEXCOMM4. */
450
451 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach FRO_HF to FLEXCOMM4. */
452
453 kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach SYS_PLL to FLEXCOMM4. */
454
455 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach MCLK to FLEXCOMM4. */
456
457 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRG to FLEXCOMM4. */
458
459 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
460
461 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach FRO12M to FLEXCOMM5. */
462
463 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach FRO_HF to FLEXCOMM5. */
464
465 kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach SYS_PLL to FLEXCOMM5. */
466
467 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach MCLK to FLEXCOMM5. */
468
469 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRG to FLEXCOMM5. */
470
471 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
472
473 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach FRO12M to FLEXCOMM6. */
474
475 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach FRO_HF to FLEXCOMM6. */
476
477 kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach SYS_PLL to FLEXCOMM6. */
478
479 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach MCLK to FLEXCOMM6. */
480
481 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRG to FLEXCOMM6. */
482
483 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
484
485 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach FRO12M to FLEXCOMM7. */
486
487 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach FRO_HF to FLEXCOMM7. */
488
489 kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach SYS_PLL to FLEXCOMM7. */
490
491 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach MCLK to FLEXCOMM7. */
492
493 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRG to FLEXCOMM7. */
494
495 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
496
497 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), /*!< Attach MAIN_CLK to FRG. */
498
499 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), /*!< Attach SYS_PLL to FRG. */
500
501 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), /*!< Attach FRO12M to FRG. */
502
503 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), /*!< Attach FRO_HF to FRG. */
504
505 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), /*!< Attach NONE to FRG. */
506
507 kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
508
509 kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), /*!< Attach SYS_PLL to MCLK. */
510
511 kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2), /*!< Attach MAIN_CLK to MCLK. */
512
513 kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
514
515 kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), /*!< Attach FRO_HF to USB_CLK. */
516
517 kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), /*!< Attach SYS_PLL to USB_CLK. */
518
519 kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), /*!< Attach MAIN_CLK to USB_CLK. */
520
521 kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), /*!< Attach NONE to USB_CLK. */
522
523 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), /*!< Attach MAIN_CLK to CLKOUT. */
524
525 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), /*!< Attach EXT_CLK to CLKOUT. */
526
527 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), /*!< Attach WDT_OSC to CLKOUT. */
528
529 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), /*!< Attach FRO_HF to CLKOUT. */
530
531 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), /*!< Attach SYS_PLL to CLKOUT. */
532
533 kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), /*!< Attach FRO12M to CLKOUT. */
534
535 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), /*!< Attach OSC32K to CLKOUT. */
536
537 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), /*!< Attach NONE to CLKOUT. */
538
539 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
540
541 } clock_attach_id_t;
542
543 /*! @brief Clock dividers. */
544 typedef enum _clock_div_name
545 {
546 kCLOCK_DivSystickClk = 0, /*!< Systick clock divider. */
547 kCLOCK_DivTraceClk = 1, /*!< Trace clock divider. */
548 kCLOCK_DivAhbClk = 32, /*!< Ahb clock divider. */
549 kCLOCK_DivClkOut = 33, /*!< Clock out divider. */
550 kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async clock divider. */
551 kCLOCK_DivUsbClk = 38, /*!< Usb clock divier. */
552 kCLOCK_DivFrg = 40, /*!< Frg clock divider. */
553 kCLOCK_DivFxI2s0MClk = 43 /*!< FxI2S0 clock divider. */
554 } clock_div_name_t;
555
556 /*******************************************************************************
557 * API
558 ******************************************************************************/
559
560 #if defined(__cplusplus)
561 extern "C" {
562 #endif /* __cplusplus */
563
CLOCK_EnableClock(clock_ip_name_t clk)564 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
565 {
566 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
567 if (index < 2UL)
568 {
569 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
570 }
571 else
572 {
573 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
574 }
575 }
576
CLOCK_DisableClock(clock_ip_name_t clk)577 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
578 {
579 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
580 if (index < 2UL)
581 {
582 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
583 }
584 else
585 {
586 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
587 }
588 }
589 /**
590 * @brief FLASH Access time definitions
591 */
592 typedef enum _clock_flashtim
593 {
594 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
595 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
596 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
597 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
598 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
599 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
600 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
601 } clock_flashtim_t;
602
603 /**
604 * @brief Set FLASH memory access time in clocks
605 * @param clks : Clock cycles for FLASH access
606 * @return Nothing
607 */
CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)608 static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
609 {
610 uint32_t tmp;
611
612 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
613
614 /* Don't alter lower bits */
615 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
616 }
617
618 /**
619 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
620 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
621 * enabled.
622 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
623 * @return returns success or fail status.
624 */
625 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
626 /**
627 * @brief Configure the clock selection muxes.
628 * @param connection : Clock to be configured.
629 * @return Nothing
630 */
631 void CLOCK_AttachClk(clock_attach_id_t connection);
632 /**
633 * @brief Get the actual clock attach id.
634 * This fuction uses the offset in input attach id, then it reads the actual source value in
635 * the register and combine the offset to obtain an actual attach id.
636 * @param attachId : Clock attach id to get.
637 * @return Clock source value.
638 */
639 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
640 /**
641 * @brief Setup peripheral clock dividers.
642 * @param div_name : Clock divider name
643 * @param divided_by_value: Value to be divided
644 * @param reset : Whether to reset the divider counter.
645 * @return Nothing
646 */
647 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
648 /**
649 * @brief Set the flash wait states for the input freuqency.
650 * @param iFreq : Input frequency
651 * @return Nothing
652 */
653 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
654 /*! @brief Return Frequency of selected clock
655 * @return Frequency of selected clock
656 */
657 uint32_t CLOCK_GetFreq(clock_name_t clockName);
658
659 /*! @brief Return Input frequency for the Fractional baud rate generator
660 * @return Input Frequency for FRG
661 */
662 uint32_t CLOCK_GetFRGInputClock(void);
663
664 /*! @brief Set output of the Fractional baud rate generator
665 * @param freq : Desired output frequency
666 * @return Error Code 0 - fail 1 - success
667 */
668 uint32_t CLOCK_SetFRGClock(uint32_t freq);
669
670 /*! @brief Return Frequency of FRO 12MHz
671 * @return Frequency of FRO 12MHz
672 */
673 uint32_t CLOCK_GetFro12MFreq(void);
674 /*! @brief Return Frequency of External Clock
675 * @return Frequency of External Clock. If no external clock is used returns 0.
676 */
677 uint32_t CLOCK_GetExtClkFreq(void);
678 /*! @brief Return Frequency of Watchdog Oscillator
679 * @return Frequency of Watchdog Oscillator
680 */
681 uint32_t CLOCK_GetWdtOscFreq(void);
682 /*! @brief Return Frequency of High-Freq output of FRO
683 * @return Frequency of High-Freq output of FRO
684 */
685 uint32_t CLOCK_GetFroHfFreq(void);
686 /*! @brief Return Frequency of PLL
687 * @return Frequency of PLL
688 */
689 uint32_t CLOCK_GetPllOutFreq(void);
690 /*! @brief Return Frequency of 32kHz osc
691 * @return Frequency of 32kHz osc
692 */
693 uint32_t CLOCK_GetOsc32KFreq(void);
694 /*! @brief Return Frequency of Core System
695 * @return Frequency of Core System
696 */
697 uint32_t CLOCK_GetCoreSysClkFreq(void);
698 /*! @brief Return Frequency of I2S MCLK Clock
699 * @return Frequency of I2S MCLK Clock
700 */
701 uint32_t CLOCK_GetI2SMClkFreq(void);
702 /*! @brief Return Frequency of Flexcomm functional Clock
703 * @return Frequency of Flexcomm functional Clock
704 */
705 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
706 /*! brief Return Frequency of Usb Clock
707 * return Frequency of Usb Clock.
708 */
709 uint32_t CLOCK_GetUsbClkFreq(void);
710 /*! @brief Return Frequency of Adc Clock
711 * @return Frequency of Adc Clock.
712 */
713 uint32_t CLOCK_GetAdcClkFreq(void);
714 /*! @brief Return Frequency of ClockOut
715 * @return Frequency of ClockOut
716 */
717 uint32_t CLOCK_GetClockOutClkFreq(void);
718 /*! @brief Return Asynchronous APB Clock source
719 * @return Asynchronous APB CLock source
720 */
CLOCK_GetAsyncApbClkSrc(void)721 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
722 {
723 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3UL);
724 }
725 /*! @brief Return Frequency of Asynchronous APB Clock
726 * @return Frequency of Asynchronous APB Clock Clock
727 */
728 uint32_t CLOCK_GetAsyncApbClkFreq(void);
729 /*! @brief Return System PLL input clock rate
730 * @return System PLL input clock rate
731 */
732 uint32_t CLOCK_GetSystemPLLInClockRate(void);
733
734 /*! @brief Return System PLL output clock rate
735 * @param recompute : Forces a PLL rate recomputation if true
736 * @return System PLL output clock rate
737 * @note The PLL rate is cached in the driver in a variable as
738 * the rate computation function can take some time to perform. It
739 * is recommended to use 'false' with the 'recompute' parameter.
740 */
741 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
742
743 /*! @brief Enables and disables PLL bypass mode
744 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
745 * @return System PLL output clock rate
746 */
CLOCK_SetBypassPLL(bool bypass)747 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
748 {
749 if (bypass)
750 {
751 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
752 }
753 else
754 {
755 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
756 }
757 }
758
759 /*! @brief Check if PLL is locked or not
760 * @return true if the PLL is locked, false if not locked
761 */
CLOCK_IsSystemPLLLocked(void)762 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
763 {
764 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0UL);
765 }
766
767 /*! @brief Store the current PLL rate
768 * @param rate: Current rate of the PLL
769 * @return Nothing
770 **/
771 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
772
773 /*! @brief PLL configuration structure flags for 'flags' field
774 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
775 *
776 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
777 * configuration structure must be assigned with the expected PLL frequency. If the
778 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
779 * function and the driver will determine the PLL rate from the currently selected
780 * PLL source. This flag might be used to configure the PLL input clock more accurately
781 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
782 *
783 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
784 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
785 * are not used.<br>
786 */
787 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
788 #define PLL_CONFIGFLAG_FORCENOFRACT \
789 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
790 SS hardware */
791
792 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
793 * See (MF) field in the SYSPLLSSCTRL1 register in the UM.
794 */
795 typedef enum _ss_progmodfm
796 {
797 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
798 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
799 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
800 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
801 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
802 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
803 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
804 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
805 } ss_progmodfm_t;
806
807 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
808 * See (MR) field in the SYSPLLSSCTRL1 register in the UM.
809 */
810 typedef enum _ss_progmoddp
811 {
812 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
813 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
814 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
815 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
816 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
817 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
818 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
819 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
820 } ss_progmoddp_t;
821
822 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
823 * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
824 * Compensation for low pass filtering of the PLL to get a triangular
825 * modulation at the output of the PLL, giving a flat frequency spectrum.
826 */
827 typedef enum _ss_modwvctrl
828 {
829 kSS_MC_NOC = (0 << 26), /*!< no compensation */
830 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
831 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
832 } ss_modwvctrl_t;
833
834 /*! @brief PLL configuration structure
835 *
836 * This structure can be used to configure the settings for a PLL
837 * setup structure. Fill in the desired configuration for the PLL
838 * and call the PLL setup function to fill in a PLL setup structure.
839 */
840 typedef struct _pll_config
841 {
842 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
843 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
844 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
845 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
846 PLL_CONFIGFLAG_FORCENOFRACT flag */
847 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
848 PLL_CONFIGFLAG_FORCENOFRACT flag */
849 ss_modwvctrl_t
850 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
851 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
852 PLL_CONFIGFLAG_FORCENOFRACT flag */
853
854 } pll_config_t;
855
856 /*! @brief PLL setup structure flags for 'flags' field
857 * These flags control how the PLL setup function sets up the PLL
858 */
859 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
860 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
861 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
862 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
863
864 /*! @brief PLL setup structure
865 * This structure can be used to pre-build a PLL setup configuration
866 * at run-time and quickly set the PLL to the configuration. It can be
867 * populated with the PLL setup function. If powering up or waiting
868 * for PLL lock, the PLL input clock source should be configured prior
869 * to PLL setup.
870 */
871 typedef struct _pll_setup
872 {
873 uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */
874 uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */
875 uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */
876 uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
877 uint32_t pllRate; /*!< Acutal PLL rate */
878 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
879 } pll_setup_t;
880
881 /*! @brief PLL status definitions
882 */
883 typedef enum _pll_error
884 {
885 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
886 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
887 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
888 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
889 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
890 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
891 } pll_error_t;
892
893 /*! @brief USB clock source definition. */
894 typedef enum _clock_usb_src
895 {
896 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
897 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
898 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
899 kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(
900 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
901 } clock_usb_src_t;
902
903 /*! @brief Return System PLL output clock rate from setup structure
904 * @param pSetup : Pointer to a PLL setup structure
905 * @return System PLL output clock rate calculated from the setup structure
906 */
907 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
908
909 /*! @brief Set PLL output based on the passed PLL setup data
910 * @param pControl : Pointer to populated PLL control structure to generate setup with
911 * @param pSetup : Pointer to PLL setup structure to be filled
912 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
913 * @note Actual frequency for setup may vary from the desired frequency based on the
914 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
915 */
916 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
917
918 /*! @brief Set PLL output from PLL setup structure (precise frequency)
919 * @param pSetup : Pointer to populated PLL setup structure
920 * @param flagcfg : Flag configuration for PLL config structure
921 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
922 * @note This function will power off the PLL, setup the PLL with the
923 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
924 * and adjust system voltages to the new PLL rate. The function will not
925 * alter any source clocks (ie, main systen clock) that may use the PLL,
926 * so these should be setup prior to and after exiting the function.
927 */
928 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
929
930 /**
931 * @brief Set PLL output from PLL setup structure (precise frequency)
932 * @param pSetup : Pointer to populated PLL setup structure
933 * @return kStatus_PLL_Success on success, or PLL setup error code
934 * @note This function will power off the PLL, setup the PLL with the
935 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
936 * and adjust system voltages to the new PLL rate. The function will not
937 * alter any source clocks (ie, main systen clock) that may use the PLL,
938 * so these should be setup prior to and after exiting the function.
939 */
940 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
941
942 /*! @brief Set PLL output based on the multiplier and input frequency
943 * @param multiply_by : multiplier
944 * @param input_freq : Clock input frequency of the PLL
945 * @return Nothing
946 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
947 * function does not disable or enable PLL power, wait for PLL lock,
948 * or adjust system voltages. These must be done in the application.
949 * The function will not alter any source clocks (ie, main systen clock)
950 * that may use the PLL, so these should be setup prior to and after
951 * exiting the function.
952 */
953 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
954
955 /*! @brief Disable USB FS clock.
956 *
957 * Disable USB FS clock.
958 */
CLOCK_DisableUsbfs0Clock(void)959 static inline void CLOCK_DisableUsbfs0Clock(void)
960 {
961 CLOCK_DisableClock(kCLOCK_Usbd0);
962 }
963 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
964
965 #if defined(__cplusplus)
966 }
967 #endif /* __cplusplus */
968
969 /*! @} */
970
971 #endif /* _FSL_CLOCK_H_ */
972
