1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_CACHE_H_
9 #define FSL_CACHE_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup cache_lplmem
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief cache driver version 2.1.1. */
25 #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
26 /*! @} */
27 /*******************************************************************************
28 * API
29 ******************************************************************************/
30
31 #if defined(__cplusplus)
32 extern "C" {
33 #endif
34
35 /*!
36 * @name cache control for the L1 low power local memory controller
37 *@{
38 */
39
40 /*!
41 * @brief Enables the processor code bus cache.
42 *
43 */
L1CACHE_EnableCodeCache(void)44 static inline void L1CACHE_EnableCodeCache(void)
45 {
46 MCM->CPCR2 &= ~MCM_CPCR2_DCC_MASK;
47 }
48
49 /*!
50 * @brief Disables the processor code bus cache.
51 *
52 */
L1CACHE_DisableCodeCache(void)53 static inline void L1CACHE_DisableCodeCache(void)
54 {
55 MCM->CPCR2 |= MCM_CPCR2_DCC_MASK;
56 }
57
58 /*!
59 * @brief Invalidates the processor code bus cache.
60 *
61 */
L1CACHE_InvalidateCodeCache(void)62 static inline void L1CACHE_InvalidateCodeCache(void)
63 {
64 MCM->CPCR2 |= MCM_CPCR2_CCBC_MASK;
65 }
66
67 /*! @} */
68
69 /*!
70 * @name The unified L1 cache controller
71 * The LPLMEM is write-through design, so there is no cache maintain by range
72 * control operation. So all cache maintain by range unified functions are
73 * directly call the cache maintain all functions since they have the same effect.
74 *@{
75 */
76
77 /*!
78 * @brief Invalidates L1 instrument cache by range.
79 *
80 * @param address The start address of the memory to be invalidated.
81 * @param size_byte The memory size.
82 */
83 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
84
85 /*!
86 * @brief Invalidates L1 data cache by range.
87 *
88 * @param address The start address of the memory to be invalidated.
89 * @param size_byte The memory size.
90 */
L1CACHE_InvalidateDCacheByRange(uint32_t address,uint32_t size_byte)91 static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
92 {
93 L1CACHE_InvalidateICacheByRange(address, size_byte);
94 }
95
96 /*!
97 * @brief Cleans L1 data cache by range.
98 *
99 * The cache is write through mode, so there is nothing to do with
100 * the cache flush/clean operation.
101 *
102 * @param address The start address of the memory to be cleaned.
103 * @param size_byte The memory size.
104 */
L1CACHE_CleanDCacheByRange(uint32_t address,uint32_t size_byte)105 static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
106 {
107 }
108
109 /*!
110 * @brief Cleans and Invalidates L1 data cache by range.
111 *
112 * @param address The start address of the memory to be clean and invalidated.
113 * @param size_byte The memory size.
114 */
L1CACHE_CleanInvalidateDCacheByRange(uint32_t address,uint32_t size_byte)115 static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
116 {
117 L1CACHE_InvalidateDCacheByRange(address, size_byte);
118 }
119
120 /*! @} */
121
122 /*!
123 * @name Unified Cache Control for caches in all levels
124 *@{
125 */
126
127 /*!
128 * @brief Invalidates instruction cache by range.
129 *
130 * @param address The physical address.
131 * @param size_byte size of the memory to be invalidated.
132 */
ICACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)133 static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
134 {
135 L1CACHE_InvalidateICacheByRange(address, size_byte);
136 }
137
138 /*!
139 * @brief Invalidates data cache by range.
140 *
141 * @param address The physical address.
142 * @param size_byte size of the memory to be invalidated.
143 */
DCACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)144 static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
145 {
146 L1CACHE_InvalidateDCacheByRange(address, size_byte);
147 }
148
149 /*!
150 * @brief Clean data cache by range.
151 *
152 * @param address The physical address.
153 * @param size_byte size of the memory to be cleaned.
154 */
DCACHE_CleanByRange(uint32_t address,uint32_t size_byte)155 static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
156 {
157 L1CACHE_CleanDCacheByRange(address, size_byte);
158 }
159
160 /*!
161 * @brief Cleans and Invalidates data cache by range.
162 *
163 * @param address The physical address.
164 * @param size_byte size of the memory to be Cleaned and Invalidated.
165 */
DCACHE_CleanInvalidateByRange(uint32_t address,uint32_t size_byte)166 static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
167 {
168 L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
169 }
170
171 /*! @} */
172
173 #if defined(__cplusplus)
174 }
175 #endif
176
177 /*! @}*/
178
179 #endif /* FSL_CACHE_H_*/
180
