1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2019-10-30 4 ** Build: b240301 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2024 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 1.0 (2019-10-30) 18 ** Initial version. 19 ** 20 ** ################################################################### 21 */ 22 23 #ifndef _K32L2A41A_FEATURES_H_ 24 #define _K32L2A41A_FEATURES_H_ 25 26 /* SOC module features */ 27 28 /* @brief ADC16 availability on the SoC. */ 29 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 30 /* @brief MMCAU availability on the SoC. */ 31 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 32 /* @brief CMP availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CMP_COUNT (2) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief DAC availability on the SoC. */ 37 #define FSL_FEATURE_SOC_DAC_COUNT (1) 38 /* @brief EDMA availability on the SoC. */ 39 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 40 /* @brief DMAMUX availability on the SoC. */ 41 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 42 /* @brief EMVSIM availability on the SoC. */ 43 #define FSL_FEATURE_SOC_EMVSIM_COUNT (1) 44 /* @brief FGPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_FGPIO_COUNT (1) 46 /* @brief FLEXIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 48 /* @brief FTFA availability on the SoC. */ 49 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 50 /* @brief GPIO availability on the SoC. */ 51 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 52 /* @brief INTMUX availability on the SoC. */ 53 #define FSL_FEATURE_SOC_INTMUX_COUNT (1) 54 /* @brief LLWU availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 56 /* @brief LPI2C availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LPI2C_COUNT (3) 58 /* @brief LPIT availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPIT_COUNT (1) 60 /* @brief LPSPI availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPSPI_COUNT (3) 62 /* @brief LPTMR availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 64 /* @brief LPUART availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPUART_COUNT (3) 66 /* @brief MCM availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MCM_COUNT (1) 68 /* @brief MMDVSQ availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) 70 /* @brief MSCM availability on the SoC. */ 71 #define FSL_FEATURE_SOC_MSCM_COUNT (1) 72 /* @brief MTB availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MTB_COUNT (1) 74 /* @brief MTBDWT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 76 /* @brief PCC availability on the SoC. */ 77 #define FSL_FEATURE_SOC_PCC_COUNT (2) 78 /* @brief PMC availability on the SoC. */ 79 #define FSL_FEATURE_SOC_PMC_COUNT (1) 80 /* @brief PORT availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PORT_COUNT (5) 82 /* @brief RCM availability on the SoC. */ 83 #define FSL_FEATURE_SOC_RCM_COUNT (1) 84 /* @brief RFSYS availability on the SoC. */ 85 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 86 /* @brief ROM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_ROM_COUNT (1) 88 /* @brief RTC availability on the SoC. */ 89 #define FSL_FEATURE_SOC_RTC_COUNT (1) 90 /* @brief SCG availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SCG_COUNT (1) 92 /* @brief SIM availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SIM_COUNT (1) 94 /* @brief SMC availability on the SoC. */ 95 #define FSL_FEATURE_SOC_SMC_COUNT (1) 96 /* @brief TPM availability on the SoC. */ 97 #define FSL_FEATURE_SOC_TPM_COUNT (3) 98 /* @brief TRGMUX availability on the SoC. */ 99 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) 100 /* @brief TRNG availability on the SoC. */ 101 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 102 /* @brief TSI availability on the SoC. */ 103 #define FSL_FEATURE_SOC_TSI_COUNT (1) 104 /* @brief TSTMR availability on the SoC. */ 105 #define FSL_FEATURE_SOC_TSTMR_COUNT (1) 106 /* @brief USB availability on the SoC. */ 107 #define FSL_FEATURE_SOC_USB_COUNT (1) 108 /* @brief VREF availability on the SoC. */ 109 #define FSL_FEATURE_SOC_VREF_COUNT (1) 110 /* @brief WDOG availability on the SoC. */ 111 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 112 113 /* ADC16 module features */ 114 115 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 116 #define FSL_FEATURE_ADC16_HAS_PGA (0) 117 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 118 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 119 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 120 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 121 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 122 #define FSL_FEATURE_ADC16_HAS_DMA (1) 123 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 124 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 125 /* @brief Has FIFO (bit SC4[AFDEP]). */ 126 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 127 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 128 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 129 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 130 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 131 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 132 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 133 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 134 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 135 /* @brief Has HW averaging (bit SC3[AVGE]). */ 136 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 137 /* @brief Has offset correction (register OFS). */ 138 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 139 /* @brief Maximum ADC resolution. */ 140 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 141 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 142 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 143 144 /* CMP module features */ 145 146 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 147 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 148 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 149 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 150 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 151 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 152 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 153 #define FSL_FEATURE_CMP_HAS_DMA (1) 154 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 155 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 156 /* @brief Has DAC Test function in CMP (register DACTEST). */ 157 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 158 159 /* CRC module features */ 160 161 /* @brief Has data register with name CRC */ 162 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 163 164 /* DAC module features */ 165 166 /* @brief Define the size of hardware buffer */ 167 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 168 /* @brief Define whether the buffer supports watermark event detection or not. */ 169 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 170 /* @brief Define whether the buffer supports watermark selection detection or not. */ 171 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 172 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 173 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 174 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 175 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 176 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 177 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 178 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 179 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 180 /* @brief Define whether FIFO buffer mode is available or not. */ 181 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 182 /* @brief Define whether swing buffer mode is available or not.. */ 183 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 184 185 /* EDMA module features */ 186 187 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 188 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) 189 /* @brief Total number of DMA channels on all modules. */ 190 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8) 191 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 192 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 193 /* @brief Has DMA_Error interrupt vector. */ 194 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 195 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 196 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) 197 /* @brief Channel IRQ entry shared offset. */ 198 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) 199 /* @brief If 8 bytes transfer supported. */ 200 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 201 /* @brief If 16 bytes transfer supported. */ 202 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 203 204 /* DMAMUX module features */ 205 206 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 207 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8) 208 /* @brief Total number of DMA channels on all modules. */ 209 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (8) 210 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 211 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 212 /* @brief Register CHCFGn width. */ 213 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 214 215 /* FGPIO module features */ 216 217 /* No feature definitions */ 218 219 /* FLEXIO module features */ 220 221 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 222 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 223 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 224 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 225 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 226 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 227 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 228 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 229 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 230 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 231 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 232 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) 233 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 234 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) 235 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 236 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 237 /* @brief Reset value of the FLEXIO_VERID register */ 238 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 239 /* @brief Reset value of the FLEXIO_PARAM register */ 240 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4040810) 241 /* @brief Flexio DMA request base channel */ 242 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 243 244 /* FLASH module features */ 245 246 /* @brief Is of type FTFA. */ 247 #define FSL_FEATURE_FLASH_IS_FTFA (1) 248 /* @brief Is of type FTFE. */ 249 #define FSL_FEATURE_FLASH_IS_FTFE (0) 250 /* @brief Is of type FTFL. */ 251 #define FSL_FEATURE_FLASH_IS_FTFL (0) 252 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 253 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 254 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 255 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 256 /* @brief Has EEPROM region protection (register FEPROT). */ 257 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 258 /* @brief Has data flash region protection (register FDPROT). */ 259 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 260 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 261 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 262 /* @brief Has flash cache control in FMC module. */ 263 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 264 /* @brief Has flash cache control in MCM module. */ 265 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 266 /* @brief Has flash cache control in MSCM module. */ 267 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 268 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 269 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 270 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 271 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 272 /* @brief P-Flash start address. */ 273 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 274 /* @brief P-Flash block count. */ 275 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 276 /* @brief P-Flash block size. */ 277 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 278 /* @brief P-Flash sector size. */ 279 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 280 /* @brief P-Flash write unit size. */ 281 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 282 /* @brief P-Flash data path width. */ 283 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 284 /* @brief P-Flash block swap feature. */ 285 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 286 /* @brief P-Flash protection region count. */ 287 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 288 /* @brief Has FlexNVM memory. */ 289 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 290 /* @brief Has FlexNVM alias. */ 291 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 292 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 293 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 294 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 295 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 296 /* @brief FlexNVM block count. */ 297 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 298 /* @brief FlexNVM block size. */ 299 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 300 /* @brief FlexNVM sector size. */ 301 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 302 /* @brief FlexNVM write unit size. */ 303 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 304 /* @brief FlexNVM data path width. */ 305 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 306 /* @brief Has FlexRAM memory. */ 307 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 308 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 309 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 310 /* @brief FlexRAM size. */ 311 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 312 /* @brief Has 0x00 Read 1s Block command. */ 313 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 314 /* @brief Has 0x01 Read 1s Section command. */ 315 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 316 /* @brief Has 0x02 Program Check command. */ 317 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 318 /* @brief Has 0x03 Read Resource command. */ 319 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 320 /* @brief Has 0x06 Program Longword command. */ 321 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 322 /* @brief Has 0x07 Program Phrase command. */ 323 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 324 /* @brief Has 0x08 Erase Flash Block command. */ 325 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 326 /* @brief Has 0x09 Erase Flash Sector command. */ 327 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 328 /* @brief Has 0x0B Program Section command. */ 329 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 330 /* @brief Has 0x40 Read 1s All Blocks command. */ 331 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 332 /* @brief Has 0x41 Read Once command. */ 333 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 334 /* @brief Has 0x43 Program Once command. */ 335 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 336 /* @brief Has 0x44 Erase All Blocks command. */ 337 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 338 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 339 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 340 /* @brief Has 0x46 Swap Control command. */ 341 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 342 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 343 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 344 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 345 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 346 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 347 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 348 /* @brief Has 0x80 Program Partition command. */ 349 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 350 /* @brief Has 0x81 Set FlexRAM Function command. */ 351 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 352 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 353 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 354 /* @brief P-Flash Erase sector command address alignment. */ 355 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 356 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 357 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 358 /* @brief P-Flash Read resource command address alignment. */ 359 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 360 /* @brief P-Flash Program check command address alignment. */ 361 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 362 /* @brief P-Flash Program check command address alignment. */ 363 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 364 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 366 /* @brief FlexNVM Erase sector command address alignment. */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 368 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 370 /* @brief FlexNVM Read resource command address alignment. */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 372 /* @brief FlexNVM Program check command address alignment. */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 374 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 376 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 378 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 380 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 382 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 384 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 386 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 388 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 390 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 392 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 394 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 396 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 398 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 400 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 402 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 404 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 406 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 408 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 410 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 412 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 414 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 416 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 418 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 420 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 422 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 424 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 426 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 428 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 429 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 430 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 431 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 432 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 433 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 434 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 435 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 436 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 437 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 438 439 /* GPIO module features */ 440 441 /* @brief Has GPIO attribute checker register (GACR). */ 442 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 443 444 /* INTMUX module features */ 445 446 /* @brief Number of INTMUX channels (related to number of register CHn_CSR). */ 447 #define FSL_FEATURE_INTMUX_CHANNEL_COUNT (4) 448 /* @brief Number of INTMUX IRQ source. */ 449 #define FSL_FEATURE_INTMUX_IRQ_COUNT (32) 450 /* @brief The start IRQ index of first INTMUX source IRQ. */ 451 #define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32) 452 /* @brief The total number of level1 interrupt vectors. */ 453 #define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32) 454 455 /* LLWU module features */ 456 457 #if defined(CPU_K32L2A41VLH1A) 458 /* @brief Maximum number of pins connected to LLWU device. */ 459 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 460 /* @brief Maximum number of internal modules connected to LLWU device. */ 461 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 462 /* @brief Number of digital filters. */ 463 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 464 /* @brief Has MF register. */ 465 #define FSL_FEATURE_LLWU_HAS_MF (1) 466 /* @brief Has PF register. */ 467 #define FSL_FEATURE_LLWU_HAS_PF (1) 468 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 469 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 470 /* @brief Has no internal module wakeup flag register. */ 471 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 472 /* @brief Has external pin 0 connected to LLWU device. */ 473 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 474 /* @brief Index of port of external pin. */ 475 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 476 /* @brief Number of external pin port on specified port. */ 477 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 478 /* @brief Has external pin 1 connected to LLWU device. */ 479 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 480 /* @brief Index of port of external pin. */ 481 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 482 /* @brief Number of external pin port on specified port. */ 483 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 484 /* @brief Has external pin 2 connected to LLWU device. */ 485 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 486 /* @brief Index of port of external pin. */ 487 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 488 /* @brief Number of external pin port on specified port. */ 489 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 490 /* @brief Has external pin 3 connected to LLWU device. */ 491 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 492 /* @brief Index of port of external pin. */ 493 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 494 /* @brief Number of external pin port on specified port. */ 495 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 496 /* @brief Has external pin 4 connected to LLWU device. */ 497 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 498 /* @brief Index of port of external pin. */ 499 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 500 /* @brief Number of external pin port on specified port. */ 501 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 502 /* @brief Has external pin 5 connected to LLWU device. */ 503 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 504 /* @brief Index of port of external pin. */ 505 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 506 /* @brief Number of external pin port on specified port. */ 507 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 508 /* @brief Has external pin 6 connected to LLWU device. */ 509 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 510 /* @brief Index of port of external pin. */ 511 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 512 /* @brief Number of external pin port on specified port. */ 513 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 514 /* @brief Has external pin 7 connected to LLWU device. */ 515 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 516 /* @brief Index of port of external pin. */ 517 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 518 /* @brief Number of external pin port on specified port. */ 519 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 520 /* @brief Has external pin 8 connected to LLWU device. */ 521 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 522 /* @brief Index of port of external pin. */ 523 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 524 /* @brief Number of external pin port on specified port. */ 525 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 526 /* @brief Has external pin 9 connected to LLWU device. */ 527 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 528 /* @brief Index of port of external pin. */ 529 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 530 /* @brief Number of external pin port on specified port. */ 531 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 532 /* @brief Has external pin 10 connected to LLWU device. */ 533 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 534 /* @brief Index of port of external pin. */ 535 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 536 /* @brief Number of external pin port on specified port. */ 537 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 538 /* @brief Has external pin 11 connected to LLWU device. */ 539 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 540 /* @brief Index of port of external pin. */ 541 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 542 /* @brief Number of external pin port on specified port. */ 543 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 544 /* @brief Has external pin 12 connected to LLWU device. */ 545 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 546 /* @brief Index of port of external pin. */ 547 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 548 /* @brief Number of external pin port on specified port. */ 549 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 550 /* @brief Has external pin 13 connected to LLWU device. */ 551 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 552 /* @brief Index of port of external pin. */ 553 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 554 /* @brief Number of external pin port on specified port. */ 555 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 556 /* @brief Has external pin 14 connected to LLWU device. */ 557 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 558 /* @brief Index of port of external pin. */ 559 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 560 /* @brief Number of external pin port on specified port. */ 561 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 562 /* @brief Has external pin 15 connected to LLWU device. */ 563 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 564 /* @brief Index of port of external pin. */ 565 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 566 /* @brief Number of external pin port on specified port. */ 567 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 568 /* @brief Has external pin 16 connected to LLWU device. */ 569 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 570 /* @brief Index of port of external pin. */ 571 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 572 /* @brief Number of external pin port on specified port. */ 573 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 574 /* @brief Has external pin 17 connected to LLWU device. */ 575 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 576 /* @brief Index of port of external pin. */ 577 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 578 /* @brief Number of external pin port on specified port. */ 579 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 580 /* @brief Has external pin 18 connected to LLWU device. */ 581 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 582 /* @brief Index of port of external pin. */ 583 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 584 /* @brief Number of external pin port on specified port. */ 585 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 586 /* @brief Has external pin 19 connected to LLWU device. */ 587 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 588 /* @brief Index of port of external pin. */ 589 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 590 /* @brief Number of external pin port on specified port. */ 591 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 592 /* @brief Has external pin 20 connected to LLWU device. */ 593 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 594 /* @brief Index of port of external pin. */ 595 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 596 /* @brief Number of external pin port on specified port. */ 597 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 598 /* @brief Has external pin 21 connected to LLWU device. */ 599 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 600 /* @brief Index of port of external pin. */ 601 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 602 /* @brief Number of external pin port on specified port. */ 603 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 604 /* @brief Has external pin 22 connected to LLWU device. */ 605 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 606 /* @brief Index of port of external pin. */ 607 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 608 /* @brief Number of external pin port on specified port. */ 609 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 610 /* @brief Has external pin 23 connected to LLWU device. */ 611 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 612 /* @brief Index of port of external pin. */ 613 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 614 /* @brief Number of external pin port on specified port. */ 615 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 616 /* @brief Has external pin 24 connected to LLWU device. */ 617 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 618 /* @brief Index of port of external pin. */ 619 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 620 /* @brief Number of external pin port on specified port. */ 621 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 622 /* @brief Has external pin 25 connected to LLWU device. */ 623 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 624 /* @brief Index of port of external pin. */ 625 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 626 /* @brief Number of external pin port on specified port. */ 627 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 628 /* @brief Has external pin 26 connected to LLWU device. */ 629 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 630 /* @brief Index of port of external pin. */ 631 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 632 /* @brief Number of external pin port on specified port. */ 633 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 634 /* @brief Has external pin 27 connected to LLWU device. */ 635 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 636 /* @brief Index of port of external pin. */ 637 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 638 /* @brief Number of external pin port on specified port. */ 639 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 640 /* @brief Has external pin 28 connected to LLWU device. */ 641 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 642 /* @brief Index of port of external pin. */ 643 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 644 /* @brief Number of external pin port on specified port. */ 645 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 646 /* @brief Has external pin 29 connected to LLWU device. */ 647 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 648 /* @brief Index of port of external pin. */ 649 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 650 /* @brief Number of external pin port on specified port. */ 651 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 652 /* @brief Has external pin 30 connected to LLWU device. */ 653 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 654 /* @brief Index of port of external pin. */ 655 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 656 /* @brief Number of external pin port on specified port. */ 657 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 658 /* @brief Has external pin 31 connected to LLWU device. */ 659 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 660 /* @brief Index of port of external pin. */ 661 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 662 /* @brief Number of external pin port on specified port. */ 663 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 664 /* @brief Has internal module 0 connected to LLWU device. */ 665 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 666 /* @brief Has internal module 1 connected to LLWU device. */ 667 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 668 /* @brief Has internal module 2 connected to LLWU device. */ 669 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 670 /* @brief Has internal module 3 connected to LLWU device. */ 671 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 672 /* @brief Has internal module 4 connected to LLWU device. */ 673 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 674 /* @brief Has internal module 5 connected to LLWU device. */ 675 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 676 /* @brief Has internal module 6 connected to LLWU device. */ 677 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 678 /* @brief Has internal module 7 connected to LLWU device. */ 679 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 680 /* @brief Has LLWU_VERID. */ 681 #define FSL_FEATURE_LLWU_HAS_VERID (1) 682 /* @brief Has LLWU_PARAM. */ 683 #define FSL_FEATURE_LLWU_HAS_PARAM (1) 684 /* @brief LLWU register bit width. */ 685 #define FSL_FEATURE_LLWU_REG_BITWIDTH (32) 686 /* @brief Has DMA Enable register LLWU_DE. */ 687 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1) 688 #elif defined(CPU_K32L2A41VLL1A) 689 /* @brief Maximum number of pins connected to LLWU device. */ 690 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 691 /* @brief Maximum number of internal modules connected to LLWU device. */ 692 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 693 /* @brief Number of digital filters. */ 694 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 695 /* @brief Has MF register. */ 696 #define FSL_FEATURE_LLWU_HAS_MF (1) 697 /* @brief Has PF register. */ 698 #define FSL_FEATURE_LLWU_HAS_PF (1) 699 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 700 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 701 /* @brief Has no internal module wakeup flag register. */ 702 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 703 /* @brief Has external pin 0 connected to LLWU device. */ 704 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 705 /* @brief Index of port of external pin. */ 706 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 707 /* @brief Number of external pin port on specified port. */ 708 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 709 /* @brief Has external pin 1 connected to LLWU device. */ 710 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 711 /* @brief Index of port of external pin. */ 712 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 713 /* @brief Number of external pin port on specified port. */ 714 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 715 /* @brief Has external pin 2 connected to LLWU device. */ 716 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 717 /* @brief Index of port of external pin. */ 718 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 719 /* @brief Number of external pin port on specified port. */ 720 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 721 /* @brief Has external pin 3 connected to LLWU device. */ 722 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 723 /* @brief Index of port of external pin. */ 724 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 725 /* @brief Number of external pin port on specified port. */ 726 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 727 /* @brief Has external pin 4 connected to LLWU device. */ 728 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 729 /* @brief Index of port of external pin. */ 730 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 731 /* @brief Number of external pin port on specified port. */ 732 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 733 /* @brief Has external pin 5 connected to LLWU device. */ 734 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 735 /* @brief Index of port of external pin. */ 736 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 737 /* @brief Number of external pin port on specified port. */ 738 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 739 /* @brief Has external pin 6 connected to LLWU device. */ 740 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 741 /* @brief Index of port of external pin. */ 742 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 743 /* @brief Number of external pin port on specified port. */ 744 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 745 /* @brief Has external pin 7 connected to LLWU device. */ 746 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 747 /* @brief Index of port of external pin. */ 748 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 749 /* @brief Number of external pin port on specified port. */ 750 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 751 /* @brief Has external pin 8 connected to LLWU device. */ 752 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 753 /* @brief Index of port of external pin. */ 754 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 755 /* @brief Number of external pin port on specified port. */ 756 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 757 /* @brief Has external pin 9 connected to LLWU device. */ 758 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 759 /* @brief Index of port of external pin. */ 760 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 761 /* @brief Number of external pin port on specified port. */ 762 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 763 /* @brief Has external pin 10 connected to LLWU device. */ 764 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 765 /* @brief Index of port of external pin. */ 766 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 767 /* @brief Number of external pin port on specified port. */ 768 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 769 /* @brief Has external pin 11 connected to LLWU device. */ 770 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 771 /* @brief Index of port of external pin. */ 772 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 773 /* @brief Number of external pin port on specified port. */ 774 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 775 /* @brief Has external pin 12 connected to LLWU device. */ 776 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 777 /* @brief Index of port of external pin. */ 778 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 779 /* @brief Number of external pin port on specified port. */ 780 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 781 /* @brief Has external pin 13 connected to LLWU device. */ 782 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 783 /* @brief Index of port of external pin. */ 784 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 785 /* @brief Number of external pin port on specified port. */ 786 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 787 /* @brief Has external pin 14 connected to LLWU device. */ 788 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 789 /* @brief Index of port of external pin. */ 790 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 791 /* @brief Number of external pin port on specified port. */ 792 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 793 /* @brief Has external pin 15 connected to LLWU device. */ 794 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 795 /* @brief Index of port of external pin. */ 796 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 797 /* @brief Number of external pin port on specified port. */ 798 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 799 /* @brief Has external pin 16 connected to LLWU device. */ 800 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 801 /* @brief Index of port of external pin. */ 802 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 803 /* @brief Number of external pin port on specified port. */ 804 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 805 /* @brief Has external pin 17 connected to LLWU device. */ 806 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 807 /* @brief Index of port of external pin. */ 808 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 809 /* @brief Number of external pin port on specified port. */ 810 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 811 /* @brief Has external pin 18 connected to LLWU device. */ 812 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 813 /* @brief Index of port of external pin. */ 814 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 815 /* @brief Number of external pin port on specified port. */ 816 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 817 /* @brief Has external pin 19 connected to LLWU device. */ 818 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 819 /* @brief Index of port of external pin. */ 820 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 821 /* @brief Number of external pin port on specified port. */ 822 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 823 /* @brief Has external pin 20 connected to LLWU device. */ 824 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 825 /* @brief Index of port of external pin. */ 826 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 827 /* @brief Number of external pin port on specified port. */ 828 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 829 /* @brief Has external pin 21 connected to LLWU device. */ 830 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 831 /* @brief Index of port of external pin. */ 832 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 833 /* @brief Number of external pin port on specified port. */ 834 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 835 /* @brief Has external pin 22 connected to LLWU device. */ 836 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 837 /* @brief Index of port of external pin. */ 838 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 839 /* @brief Number of external pin port on specified port. */ 840 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 841 /* @brief Has external pin 23 connected to LLWU device. */ 842 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 843 /* @brief Index of port of external pin. */ 844 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 845 /* @brief Number of external pin port on specified port. */ 846 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 847 /* @brief Has external pin 24 connected to LLWU device. */ 848 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 849 /* @brief Index of port of external pin. */ 850 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 851 /* @brief Number of external pin port on specified port. */ 852 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 853 /* @brief Has external pin 25 connected to LLWU device. */ 854 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 855 /* @brief Index of port of external pin. */ 856 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 857 /* @brief Number of external pin port on specified port. */ 858 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 859 /* @brief Has external pin 26 connected to LLWU device. */ 860 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 861 /* @brief Index of port of external pin. */ 862 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 863 /* @brief Number of external pin port on specified port. */ 864 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 865 /* @brief Has external pin 27 connected to LLWU device. */ 866 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 867 /* @brief Index of port of external pin. */ 868 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 869 /* @brief Number of external pin port on specified port. */ 870 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 871 /* @brief Has external pin 28 connected to LLWU device. */ 872 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 873 /* @brief Index of port of external pin. */ 874 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 875 /* @brief Number of external pin port on specified port. */ 876 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 877 /* @brief Has external pin 29 connected to LLWU device. */ 878 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 879 /* @brief Index of port of external pin. */ 880 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 881 /* @brief Number of external pin port on specified port. */ 882 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 883 /* @brief Has external pin 30 connected to LLWU device. */ 884 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 885 /* @brief Index of port of external pin. */ 886 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 887 /* @brief Number of external pin port on specified port. */ 888 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 889 /* @brief Has external pin 31 connected to LLWU device. */ 890 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 891 /* @brief Index of port of external pin. */ 892 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 893 /* @brief Number of external pin port on specified port. */ 894 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 895 /* @brief Has internal module 0 connected to LLWU device. */ 896 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 897 /* @brief Has internal module 1 connected to LLWU device. */ 898 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 899 /* @brief Has internal module 2 connected to LLWU device. */ 900 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 901 /* @brief Has internal module 3 connected to LLWU device. */ 902 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 903 /* @brief Has internal module 4 connected to LLWU device. */ 904 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 905 /* @brief Has internal module 5 connected to LLWU device. */ 906 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 907 /* @brief Has internal module 6 connected to LLWU device. */ 908 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 909 /* @brief Has internal module 7 connected to LLWU device. */ 910 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 911 /* @brief Has LLWU_VERID. */ 912 #define FSL_FEATURE_LLWU_HAS_VERID (1) 913 /* @brief Has LLWU_PARAM. */ 914 #define FSL_FEATURE_LLWU_HAS_PARAM (1) 915 /* @brief LLWU register bit width. */ 916 #define FSL_FEATURE_LLWU_REG_BITWIDTH (32) 917 /* @brief Has DMA Enable register LLWU_DE. */ 918 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1) 919 #endif /* defined(CPU_K32L2A41VLH1A) */ 920 921 /* LPI2C module features */ 922 923 /* @brief Has separate DMA RX and TX requests. */ 924 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 925 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 926 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 927 928 /* LPIT module features */ 929 930 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 931 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 932 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 933 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 934 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 935 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 936 937 /* LPSPI module features */ 938 939 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 940 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) 941 /* @brief Has separate DMA RX and TX requests. */ 942 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 943 944 /* LPTMR module features */ 945 946 /* @brief Has shared interrupt handler with another LPTMR module. */ 947 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 948 /* @brief Whether LPTMR counter is 32 bits width. */ 949 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 950 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 951 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 952 953 /* LPUART module features */ 954 955 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 956 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 957 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 958 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 959 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 960 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 961 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 962 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 963 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 964 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 965 /* @brief Has 32-bit register MODIR */ 966 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 967 /* @brief Hardware flow control (RTS, CTS) is supported. */ 968 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 969 /* @brief Infrared (modulation) is supported. */ 970 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 971 /* @brief 2 bits long stop bit is available. */ 972 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 973 /* @brief If 10-bit mode is supported. */ 974 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 975 /* @brief If 7-bit mode is supported. */ 976 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 977 /* @brief Baud rate fine adjustment is available. */ 978 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 979 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 980 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 981 /* @brief Baud rate oversampling is available. */ 982 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 983 /* @brief Baud rate oversampling is available. */ 984 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 985 /* @brief Peripheral type. */ 986 #define FSL_FEATURE_LPUART_IS_SCI (1) 987 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 988 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 989 /* @brief Supports two match addresses to filter incoming frames. */ 990 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 991 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 992 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 993 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 994 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 995 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 996 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 997 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 998 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 999 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1000 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1001 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1002 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1003 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1004 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1005 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1006 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1007 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1008 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1009 /* @brief Has separate DMA RX and TX requests. */ 1010 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1011 /* @brief Has separate RX and TX interrupts. */ 1012 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1013 /* @brief Has LPAURT_PARAM. */ 1014 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 1015 /* @brief Has LPUART_VERID. */ 1016 #define FSL_FEATURE_LPUART_HAS_VERID (1) 1017 /* @brief Has LPUART_GLOBAL. */ 1018 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 1019 /* @brief Has LPUART_PINCFG. */ 1020 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 1021 1022 /* MMDVSQ module features */ 1023 1024 /* No feature definitions */ 1025 1026 /* MSCM module features */ 1027 1028 /* @brief Number of configuration information for processors. */ 1029 #define FSL_FEATURE_MSCM_HAS_CP_COUNT (1) 1030 /* @brief Has data cache. */ 1031 #define FSL_FEATURE_MSCM_HAS_DATACACHE (0) 1032 1033 /* interrupt module features */ 1034 1035 /* @brief Lowest interrupt request number. */ 1036 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1037 /* @brief Highest interrupt request number. */ 1038 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1039 1040 /* PMC module features */ 1041 1042 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1043 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1044 /* @brief Has Bandgap Buffer Enable. */ 1045 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1046 /* @brief Has Bandgap Buffer Drive Select. */ 1047 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1048 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1049 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1050 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1051 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1052 /* @brief Has LPO. */ 1053 #define FSL_FEATURE_PMC_HAS_LPO (0) 1054 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1055 #define FSL_FEATURE_PMC_HAS_VLPO (1) 1056 /* @brief Has acknowledge isolation support. */ 1057 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1058 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1059 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1060 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1061 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1062 /* @brief Has PMC_HVDSC1. */ 1063 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1) 1064 /* @brief Has PMC_PARAM. */ 1065 #define FSL_FEATURE_PMC_HAS_PARAM (1) 1066 /* @brief Has PMC_VERID. */ 1067 #define FSL_FEATURE_PMC_HAS_VERID (1) 1068 1069 /* PORT module features */ 1070 1071 /* @brief Has control lock (register bit PCR[LK]). */ 1072 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1073 /* @brief Has open drain control (register bit PCR[ODE]). */ 1074 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1075 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1076 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 1077 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1078 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1079 /* @brief Has pull resistor selection available. */ 1080 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1081 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1082 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1083 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1084 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1085 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1086 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1087 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1088 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1089 /* @brief Has separate drive strength register (HDRVE). */ 1090 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1091 /* @brief Has glitch filter (register IOFLT). */ 1092 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1093 /* @brief Defines width of PCR[MUX] field. */ 1094 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1095 /* @brief Has dedicated interrupt vector. */ 1096 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1097 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1098 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) 1099 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1100 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1) 1101 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1102 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1) 1103 1104 /* RCM module features */ 1105 1106 /* @brief Has Loss-of-Lock Reset support. */ 1107 #define FSL_FEATURE_RCM_HAS_LOL (1) 1108 /* @brief Has Loss-of-Clock Reset support. */ 1109 #define FSL_FEATURE_RCM_HAS_LOC (1) 1110 /* @brief Has JTAG generated Reset support. */ 1111 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1112 /* @brief Has EzPort generated Reset support. */ 1113 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1114 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1115 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1116 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1117 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 1118 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1119 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1120 /* @brief Has RCM_VERID. */ 1121 #define FSL_FEATURE_RCM_HAS_VERID (1) 1122 /* @brief Has RCM_PARAM. */ 1123 #define FSL_FEATURE_RCM_HAS_PARAM (1) 1124 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1125 #define FSL_FEATURE_RCM_HAS_SRIE (1) 1126 /* @brief RCM register bit width. */ 1127 #define FSL_FEATURE_RCM_REG_WIDTH (32) 1128 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1129 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1130 /* @brief Has MDM-AP system reset support RCM_SRS[MDM_AP] */ 1131 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1132 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1133 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1134 1135 /* RTC module features */ 1136 1137 /* @brief Has wakeup pin. */ 1138 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1139 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1140 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1141 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1142 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1143 /* @brief Has read/write access control (registers WAR and RAR). */ 1144 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 1145 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1146 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 1147 /* @brief Has RTC_CLKIN available. */ 1148 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1149 /* @brief Has prescaler adjust for LPO. */ 1150 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) 1151 /* @brief Has Clock Pin Enable field. */ 1152 #define FSL_FEATURE_RTC_HAS_CPE (1) 1153 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1154 #define FSL_FEATURE_RTC_HAS_TSIC (1) 1155 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1156 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1157 /* @brief Has Tamper Interrupt Register (register TIR). */ 1158 #define FSL_FEATURE_RTC_HAS_TIR (0) 1159 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1160 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1161 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1162 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1163 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1164 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1165 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1166 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1167 /* @brief Has Tamper Detect Register (register TDR). */ 1168 #define FSL_FEATURE_RTC_HAS_TDR (0) 1169 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1170 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1171 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1172 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1173 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1174 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1175 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1176 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1177 /* @brief Has Pin Configuration Register (register PCR). */ 1178 #define FSL_FEATURE_RTC_HAS_PCR (0) 1179 1180 /* SCG module features */ 1181 1182 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ 1183 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0) 1184 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ 1185 #define FSL_FEATURE_SCG_HAS_DIVBUS (0) 1186 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ 1187 #define FSL_FEATURE_SCG_HAS_DIVEXT (0) 1188 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ 1189 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (1) 1190 /* @brief Has OSC freq range SOSCCFG[RANGE]. */ 1191 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (1) 1192 /* @brief Has SOSCCSR[SOSCERCLKEN]. */ 1193 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (1) 1194 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ 1195 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) 1196 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ 1197 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (1) 1198 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ 1199 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1) 1200 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ 1201 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1) 1202 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ 1203 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1) 1204 /* @brief Has SCG_SIRCCSR[LPOPO]. */ 1205 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) 1206 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ 1207 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1) 1208 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ 1209 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1) 1210 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ 1211 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) 1212 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ 1213 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) 1214 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ 1215 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (1) 1216 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ 1217 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (1) 1218 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ 1219 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) 1220 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ 1221 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) 1222 /* @brief Has SCG_SPLLCFG[PLLS]. */ 1223 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) 1224 /* @brief Has SCG_SPLLCFG[BYPASS]. */ 1225 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) 1226 /* @brief Has SCG_SPLLCFG[PFDSEL]. */ 1227 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) 1228 /* @brief Has SCG_SPLLCSR[SPLLCM]. */ 1229 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (1) 1230 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ 1231 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) 1232 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ 1233 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) 1234 /* @brief Has low power FLL, SCG_LPFLLCSR. */ 1235 #define FSL_FEATURE_SCG_HAS_LPFLL (0) 1236 /* @brief Has low power FLL stop enable. */ 1237 #define FSL_FEATURE_SCG_HAS_LPFLLSTEN (0) 1238 /* @brief Has system PLL, SCG_SPLLCSR. */ 1239 #define FSL_FEATURE_SCG_HAS_SPLL (1) 1240 /* @brief Has system PLL PFD, SCG_SPLLPFD. */ 1241 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0) 1242 /* @brief Has auxiliary PLL, SCG_APLLCSR. */ 1243 #define FSL_FEATURE_SCG_HAS_APLL (0) 1244 /* @brief Has RTC OSC control, SCG_ROSCCSR. */ 1245 #define FSL_FEATURE_SCG_HAS_ROSC (0) 1246 /* @brief Has RTC OSC clock source. */ 1247 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (0) 1248 /* @brief Has RTC OSC clock out select. */ 1249 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (0) 1250 /* @brief Has SIRC clock out select. */ 1251 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) 1252 /* @brief Has FIRC trim source USB0 Start of Frame. */ 1253 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (1) 1254 /* @brief Has FIRC trim source USB1 Start of Frame. */ 1255 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) 1256 /* @brief Has FIRC trim source system OSC. */ 1257 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) 1258 /* @brief Has FIRC trim source RTC OSC. */ 1259 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (0) 1260 1261 /* SIM module features */ 1262 1263 /* @brief Has USB FS divider. */ 1264 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1265 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1266 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1267 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1268 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1269 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1270 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1271 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1272 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0) 1273 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1274 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0) 1275 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1276 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1277 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1278 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1279 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1280 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1281 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1282 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1283 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1284 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1285 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1286 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1287 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1288 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1289 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1290 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1291 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1292 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1293 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1294 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) 1295 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1296 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1297 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1298 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1299 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1300 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1301 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1302 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1303 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1304 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1305 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1306 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1307 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1308 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1309 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1310 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1311 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1312 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1313 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1314 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1315 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1316 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1317 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1318 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1319 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1320 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1321 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1322 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1323 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1324 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1325 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1326 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1327 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1328 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1329 /* @brief Has FTM module(s) configuration. */ 1330 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1331 /* @brief Number of FTM modules. */ 1332 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1333 /* @brief Number of FTM triggers with selectable source. */ 1334 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1335 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1336 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1337 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1338 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1339 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1340 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1341 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1342 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1343 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1344 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1345 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1346 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1347 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1348 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1349 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1350 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1351 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1352 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1353 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1354 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1355 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1356 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1357 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1358 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1359 /* @brief Has TPM module(s) configuration. */ 1360 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1361 /* @brief The highest TPM module index. */ 1362 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1363 /* @brief Has TPM module with index 0. */ 1364 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1365 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1366 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1367 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1368 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1369 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1370 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1371 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1372 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1373 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1374 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1375 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1376 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1377 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1378 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1379 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1380 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1381 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1382 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1383 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1384 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1385 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1386 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1387 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1388 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1389 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1390 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1391 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1392 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1393 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1394 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1395 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1396 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1397 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1398 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1399 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1400 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1401 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1402 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1403 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1404 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1405 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1406 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1407 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1408 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1409 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1410 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1411 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1412 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1413 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1414 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1415 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1416 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) 1417 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1418 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1419 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1420 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1421 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1422 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) 1423 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1424 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) 1425 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1426 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1427 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1428 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1429 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1430 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1431 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1432 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1433 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1434 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1435 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1436 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1437 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1438 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1439 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1440 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1441 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1442 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1443 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1444 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1445 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1446 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1447 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1448 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1449 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1450 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1451 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1452 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1453 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1454 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1455 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1456 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1457 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1458 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1459 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1460 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1461 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1462 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1463 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1464 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1465 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1466 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1467 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1468 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1469 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1470 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1471 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1472 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1473 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1474 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1475 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1476 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1477 /* @brief Has miscellanious control register (register MCR). */ 1478 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1479 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1480 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1481 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1482 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1483 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1484 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1485 /* @brief Has UIDH registers. */ 1486 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1487 /* @brief Has UIDM registers. */ 1488 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1489 1490 /* SMC module features */ 1491 1492 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1493 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1494 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1495 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1496 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1497 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1498 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1499 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1500 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1501 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1502 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1503 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1504 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1505 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1506 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1507 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1508 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1509 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1510 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1511 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1512 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1513 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1514 /* @brief Has stop submode. */ 1515 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1516 /* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */ 1517 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1518 /* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */ 1519 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1520 /* @brief Has SMC_PARAM. */ 1521 #define FSL_FEATURE_SMC_HAS_PARAM (1) 1522 /* @brief Has SMC_VERID. */ 1523 #define FSL_FEATURE_SMC_HAS_VERID (1) 1524 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1525 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1526 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1527 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1528 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1529 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1530 /* @brief Width of SMC registers. */ 1531 #define FSL_FEATURE_SMC_REG_WIDTH (32) 1532 1533 /* SysTick module features */ 1534 1535 /* @brief Systick has external reference clock. */ 1536 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1537 /* @brief Systick external reference clock is core clock divided by this value. */ 1538 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1539 1540 /* TPM module features */ 1541 1542 /* @brief Bus clock is the source clock for the module. */ 1543 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1544 /* @brief Number of channels. */ 1545 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1546 (((x) == TPM0) ? (6) : \ 1547 (((x) == TPM1) ? (2) : \ 1548 (((x) == TPM2) ? (2) : (-1)))) 1549 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1550 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1551 /* @brief Has TPM_PARAM. */ 1552 #define FSL_FEATURE_TPM_HAS_PARAM (1) 1553 /* @brief Has TPM_VERID. */ 1554 #define FSL_FEATURE_TPM_HAS_VERID (1) 1555 /* @brief Has TPM_GLOBAL. */ 1556 #define FSL_FEATURE_TPM_HAS_GLOBAL (1) 1557 /* @brief Has TPM_TRIG. */ 1558 #define FSL_FEATURE_TPM_HAS_TRIG (1) 1559 /* @brief Whether TRIG register has effect. */ 1560 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) \ 1561 (((x) == TPM0) ? (1) : \ 1562 (((x) == TPM1) ? (0) : \ 1563 (((x) == TPM2) ? (0) : (-1)))) 1564 /* @brief Has counter pause on trigger. */ 1565 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1566 /* @brief Has external trigger selection. */ 1567 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1568 /* @brief Has TPM_COMBINE register. */ 1569 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 1570 /* @brief Whether COMBINE register has effect. */ 1571 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 1572 /* @brief Has TPM_POL. */ 1573 #define FSL_FEATURE_TPM_HAS_POL (1) 1574 /* @brief Whether POL register has effect. */ 1575 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1576 /* @brief Has TPM_FILTER register. */ 1577 #define FSL_FEATURE_TPM_HAS_FILTER (1) 1578 /* @brief Whether FILTER register has effect. */ 1579 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 1580 /* @brief Has TPM_QDCTRL register. */ 1581 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 1582 /* @brief Whether QDCTRL register has effect. */ 1583 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 1584 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1585 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1586 /* @brief Has pause level select. */ 1587 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (0) 1588 /* @brief Whether 32 bits counter has effect. */ 1589 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1590 1591 /* TSI module features */ 1592 1593 /* @brief TSI module version. */ 1594 #define FSL_FEATURE_TSI_VERSION (4) 1595 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 1596 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1) 1597 /* @brief Number of TSI channels. */ 1598 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 1599 1600 /* USB module features */ 1601 1602 /* @brief KHCI module instance count */ 1603 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1604 /* @brief HOST mode enabled */ 1605 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1606 /* @brief OTG mode enabled */ 1607 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1608 /* @brief Size of the USB dedicated RAM */ 1609 #define FSL_FEATURE_USB_KHCI_USB_RAM (2048) 1610 /* @brief Base address of the USB dedicated RAM */ 1611 #define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074790400) 1612 /* @brief Has KEEP_ALIVE_CTRL register */ 1613 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1614 /* @brief Has the Dynamic SOF threshold compare support */ 1615 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) 1616 /* @brief Has the VBUS detect support */ 1617 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) 1618 /* @brief Has the IRC48M module clock support */ 1619 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) 1620 /* @brief Number of endpoints supported */ 1621 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1622 /* @brief Has STALL_IL/OL_DIS registers */ 1623 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1624 /* @brief Has STALL_IH/OH_DIS registers */ 1625 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1626 1627 /* VREF module features */ 1628 1629 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1630 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1631 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1632 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1633 /* @brief If high/low buffer mode supported */ 1634 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1635 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1636 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1637 /* @brief Has VREF_TRM4. */ 1638 #define FSL_FEATURE_VREF_HAS_TRM4 (1) 1639 1640 /* WDOG module features */ 1641 1642 /* @brief Watchdog is available. */ 1643 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1644 /* @brief WDOG_CNT can be 32-bit written. */ 1645 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 1646 1647 #endif /* _K32L2A41A_FEATURES_H_ */ 1648 1649
