1 /*
2  * Copyright 2021-2022 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_PM_DEVICE_H_
9 #define _FSL_PM_DEVICE_H_
10 
11 #include "fsl_common.h"
12 
13 #include "fsl_pm_config.h"
14 
15 /* Power Mode Index */
16 #define PM_LP_STATE_PM0           (0U)
17 #define PM_LP_STATE_PM1           (1U)
18 #define PM_LP_STATE_PM2           (2U)
19 #define PM_LP_STATE_PM3           (3U)
20 #define PM_LP_STATE_PM4           (4U)
21 #define PM_LP_STATE_NO_CONSTRAINT (0xFFU)
22 
23 /* Constraints used by application. */
24 #define PM_RESC_CAU_SOC_SLP_REF_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 0U)
25 
26 #define PM_RESC_SYSOSC_FRO_PLL_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 1U)
27 
28 #define PM_RESC_ENET_CLK_ON PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 2U)
29 
30 #define PM_RESC_ENET_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 4U)
31 #define PM_RESC_ENET_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 4U)
32 
33 #define PM_RESC_SDIO_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 5U)
34 #define PM_RESC_SDIO_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 5U)
35 
36 #define PM_RESC_OTP_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 6U)
37 #define PM_RESC_OTP_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 6U)
38 
39 #define PM_RESC_ROM_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 7U)
40 #define PM_RESC_ROM_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 7U)
41 
42 #define PM_RESC_FLEXSPI_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 8U)
43 #define PM_RESC_FLEXSPI_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 8U)
44 
45 #define PM_RESC_POWERQUAD_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 9U)
46 #define PM_RESC_POWERQUAD_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 9U)
47 
48 #define PM_RESC_PKC_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 10U)
49 #define PM_RESC_PKC_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 10U)
50 
51 #define PM_RESC_CSS_MEM_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 11U)
52 #define PM_RESC_CSS_MEM_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 11U)
53 
54 #define PM_RESC_SRAM_0K_384K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 12U)
55 #define PM_RESC_SRAM_0K_384K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 12U)
56 #define PM_RESC_SRAM_0K_384K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 13U)
57 
58 #define PM_RESC_SRAM_384K_448K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 14U)
59 #define PM_RESC_SRAM_384K_448K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 14U)
60 #define PM_RESC_SRAM_384K_448K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 15U)
61 
62 #define PM_RESC_SRAM_448K_512K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 16U)
63 #define PM_RESC_SRAM_448K_512K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 16U)
64 #define PM_RESC_SRAM_448K_512K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 17U)
65 
66 #define PM_RESC_SRAM_512K_640K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 18U)
67 #define PM_RESC_SRAM_512K_640K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 18U)
68 #define PM_RESC_SRAM_512K_640K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 19U)
69 
70 #define PM_RESC_SRAM_640K_896K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 20U)
71 #define PM_RESC_SRAM_640K_896K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 20U)
72 #define PM_RESC_SRAM_640K_896K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 21U)
73 
74 #define PM_RESC_SRAM_896K_1216K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 22U)
75 #define PM_RESC_SRAM_896K_1216K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 22U)
76 #define PM_RESC_SRAM_896K_1216K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 23U)
77 
78 #define PM_RESC_AON_MEM_0K_8K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 24U)
79 #define PM_RESC_AON_MEM_0K_8K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 24U)
80 #define PM_RESC_AON_MEM_0K_8K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 25U)
81 
82 #define PM_RESC_AON_MEM_8K_16K_ACTIVE    PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 26U)
83 #define PM_RESC_AON_MEM_8K_16K_STANDBY   PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON2, 26U)
84 #define PM_RESC_AON_MEM_8K_16K_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 27U)
85 
86 #define PM_RESC_GAU_ANA_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 28U)
87 #define PM_RESC_USB_ANA_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 29U)
88 
89 #define PM_RESC_BUCK18_NORMAL PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 30U)
90 #define PM_RESC_BUCK18_SLEEP  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 30U)
91 
92 #define PM_RESC_BUCK11_NORMAL PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, 31U)
93 #define PM_RESC_BUCK11_SLEEP  PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, 31U)
94 
95 #if FSL_PM_SUPPORT_WAKEUP_SOURCE_MANAGER
96 
97 #define PM_WSID_WAKEUP_PIN0_LOW_LEVEL  PM_ENCODE_WAKEUP_SOURCE_ID(PIN0_INT_IRQn, 0UL)
98 #define PM_WSID_WAKEUP_PIN0_HIGH_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN0_INT_IRQn, 1UL)
99 #define PM_WSID_WAKEUP_PIN1_LOW_LEVEL  PM_ENCODE_WAKEUP_SOURCE_ID(PIN1_INT_IRQn, 0UL)
100 #define PM_WSID_WAKEUP_PIN1_HIGH_LEVEL PM_ENCODE_WAKEUP_SOURCE_ID(PIN1_INT_IRQn, 1UL)
101 
102 /* The other WSID is identical to the XX_IRQn macro in RW610.h */
103 
104 #endif /* FSL_PM_SUPPORT_WAKEUP_SOURCE_MANAGER */
105 
106 #endif /* _FSL_PM_DEVICE_H_ */
107