1 /*
2 * Copyright 2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_adapter_imu_common.h"
10 #include "fsl_adapter_imu.h"
11 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
12 #include "fsl_gdma.h"
13 #endif
14
15 /*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18 #if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
19 #ifndef IMU_ISR_PRIORITY
20 #define IMU_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
21 #endif
22 #else
23 #ifndef IMU_ISR_PRIORITY
24 #define IMU_ISR_PRIORITY (2U)
25 #endif
26 #endif
27
28 #ifndef IMU_LINK_WAIT_DELAY_MS
29 #define IMU_LINK_WAIT_DELAY_MS 1U
30 #endif
31
32 #ifndef IMUMC_ALLOC_FAILED_DELAY_MS
33 #define IMUMC_ALLOC_FAILED_DELAY_MS 1U
34 #endif
35
36 #ifndef IMUMC_ALLOC_RETRY_COUNT
37 #define IMUMC_ALLOC_RETRY_COUNT 10U
38 #endif
39
40 #if defined(CPU2)
41 #define os_InterruptMaskClear(irq_num) DisableIRQ((IRQn_Type)irq_num)
42 #define os_InterruptMaskSet(irq_num) EnableIRQ((IRQn_Type)irq_num)
43 #define os_ClearPendingISR(irq_num) NVIC_ClearPendingIRQ((IRQn_Type)irq_num)
44 #else
45 #define os_InterruptMaskClear(irq_num) DisableIRQ(irq_num)
46 #define os_InterruptMaskSet(irq_num) EnableIRQ(irq_num)
47 #define os_ClearPendingISR(irq_num) NVIC_ClearPendingIRQ(irq_num)
48 #endif
49
50 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
51 #define HAL_GDMA GDMA
52 #define HAL_GDMA_CH 0
53 #define HAL_GDMA_IRQn GDMA_IRQn
54 #define HAL_GDMA_DONE_EVENT (1U << 0U)
55 #define GDMA_ISR_PRIORITY IMU_ISR_PRIORITY
56 #define HAL_IMU_MEMCPY HAL_ImuGdmaCopyData
57 #else
58 #define HAL_IMU_MEMCPY memcpy
59 #endif
60
61 /*******************************************************************************
62 * Declaration
63 ******************************************************************************/
64 #ifdef __ZEPHYR__
65 const uint8_t gUseRtos_c = 1;
66 #endif
67
68 /*! IMU handle instance for each IMU link */
69 static hal_imu_handle_t imuHandleCh[kIMU_LinkMax];
70
71 /*! IMU interrput callback for each IMU link */
72 static imu_irq_callback_t imuIrqCallback[kIMU_LinkMax];
73
74 /*! IMU message sequence number */
75 static uint8_t seq_num = 0;
76
77 /*! IMU initializtion flag
78 bit 0: flag for IMU link #0
79 bit 1: flag for IMU link #1
80 */
81 static uint8_t imu_init_flag = 0;
82
83 /*! IMUMC initializtion flag
84 */
85 static uint8_t imumc_init_flag = 0;
86
87 /*! imu task created flag
88 */
89 static uint8_t imu_task_flag = 0;
90
91 #ifndef CPU2
92 /*! Sleep flag address between CPU1 and CPU3 or CPU2 and CPU3 */
93 #define IMU_SLEEP_FLAG13 0x4138248C
94 #define IMU_SLEEP_FLAG23 0x443CFE88
95 #define IMU_SLEEP_FLAG_ADDR(imuLinkId) \
96 (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? ((uint32_t *)IMU_SLEEP_FLAG13) : ((uint32_t *)IMU_SLEEP_FLAG23))
97 #endif
98
99 /*! wait imu task lock
100 */
101 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
102 #ifdef __ZEPHYR__
103 struct k_mutex imu_task_lock;
104 #else
105 static OSA_MUTEX_HANDLE_DEFINE(imu_task_lock);
106 #endif
107 #endif
108 /*******************************************************************************
109 * Code
110 ******************************************************************************/
111 #if defined(CPU2)
112 extern IMU_Msg_Wrapper_short_t __attribute__((aligned(4))) SQRAM_CPU12_MBOX;
113 extern IMU_Msg_Wrapper_long_t __attribute__((aligned(4))) SQRAM_CPU23_MBOX;
114 volatile static IMU_Msg_Wrapper_short_t *imuMsgQ12 = &SQRAM_CPU12_MBOX;
115 volatile static IMU_Msg_Wrapper_long_t *imuMsgQ23 = &SQRAM_CPU23_MBOX;
116 __attribute__((section(".smu_cpu23_txq"))) volatile static uint8_t __attribute__((aligned(4)))
117 imumcTxBuf23[IMUMC_TXQ23_BUFSIZE][IMUMC_TXQ23_BUFLENGTH];
118
119 static void HAL_ImuMain(void *argv);
120 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandle);
121 static OSA_TASK_DEFINE(HAL_ImuMain, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
122 OSA_EVENT_HANDLE_DEFINE(ImuQFlagsRef);
123 #else
124 __attribute__((section(".smu_cpu13_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
125 SQRAM_CPU13_MBOX;
126 __attribute__((section(".smu_cpu23_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
127 SQRAM_CPU23_MBOX;
128 static volatile IMU_Msg_Wrapper_long_t *imuMsgQ13 = &SQRAM_CPU13_MBOX;
129 static volatile IMU_Msg_Wrapper_long_t *imuMsgQ23 = &SQRAM_CPU23_MBOX;
130 __attribute__((section(".smu_cpu31_txq"))) static volatile uint8_t __attribute__((aligned(4)))
131 imumcTxBuf13[IMUMC_TXQ13_BUFSIZE][IMUMC_TXQ13_BUFLENGTH];
132 __attribute__((section(".smu_cpu32_txq"))) static volatile uint8_t __attribute__((aligned(4)))
133 imumcTxBuf23[IMUMC_TXQ23_BUFSIZE][IMUMC_TXQ23_BUFLENGTH];
134
135 /* seperate CPU2 to CPU3 and CPU1 to CPU3 IMU RX tasks */
136 #ifdef __ZEPHYR__
137 static void HAL_ImuMainCpu13(void *argv1, void *argv2, void *argv3);
138 static void HAL_ImuMainCpu23(void *argv1, void *argv2, void *argv3);
139
140 K_THREAD_STACK_DEFINE(ImuTaskStackCpu13, IMU_TASK_STACK_SIZE);
141 K_THREAD_STACK_DEFINE(ImuTaskStackCpu23, IMU_TASK_STACK_SIZE);
142
143 k_tid_t ImuTaskCpu13;
144 k_tid_t ImuTaskCpu23;
145
146 K_EVENT_DEFINE(ImuQ13FlagsRef);
147 K_EVENT_DEFINE(ImuQ23FlagsRef);
148
149 struct k_thread ImuTaskHandleCpu13;
150 struct k_thread ImuTaskHandleCpu23;
151 #else
152 static void HAL_ImuMainCpu13(void *argv);
153 static void HAL_ImuMainCpu23(void *argv);
154
155 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu13);
156 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu23);
157 static OSA_TASK_DEFINE(HAL_ImuMainCpu13, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
158 static OSA_TASK_DEFINE(HAL_ImuMainCpu23, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
159 OSA_EVENT_HANDLE_DEFINE(ImuQ13FlagsRef);
160 OSA_EVENT_HANDLE_DEFINE(ImuQ23FlagsRef);
161 #endif /* __ZEPHYR__ */
162 #endif
163
164 #ifdef __ZEPHYR__
165 struct k_event imumcQFlagsRef;
166 #else
167 OSA_EVENT_HANDLE_DEFINE(imumcQFlagsRef);
168 #endif /* __ZEPHYR__ */
169
170 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
171 static gdma_handle_t gdmaHandle;
172 OSA_SEMAPHORE_HANDLE_DEFINE(gdmaSemHandle);
173 OSA_EVENT_HANDLE_DEFINE(gdmaFlagsRef);
174 #endif
175
176 /**************Internal helper functions***********************/
177 /// \cond
178 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
HAL_GdmaCallback(gdma_handle_t * handle,void * userData,uint32_t interrupts)179 static void HAL_GdmaCallback(gdma_handle_t *handle, void *userData, uint32_t interrupts)
180 {
181 if (0UL != (interrupts & kGDMA_TransferDoneFlag))
182 {
183 (void)OSA_EventSet((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT);
184 }
185 }
186
HAL_InitGdma(void)187 static void HAL_InitGdma(void)
188 {
189 if (gdmaHandle.callback)
190 return;
191
192 GDMA_Init(HAL_GDMA);
193 GDMA_CreateHandle(&gdmaHandle, HAL_GDMA, HAL_GDMA_CH);
194 GDMA_SetCallback(&gdmaHandle, HAL_GdmaCallback, NULL);
195 OSA_SemaphoreCreate(gdmaSemHandle, 1U);
196 (void)OSA_EventCreate(gdmaFlagsRef, 1U);
197 NVIC_SetPriority(GDMA_IRQn, GDMA_ISR_PRIORITY);
198 }
199
HAL_ImuGdmaCopyData(void * destAddr,void * srcAddr,uint32_t len)200 void HAL_ImuGdmaCopyData(void *destAddr, void *srcAddr, uint32_t len)
201 {
202 uint32_t Events;
203 gdma_channel_xfer_config_t xferConfig = {0};
204
205 xferConfig.srcAddr = (uint32_t)srcAddr;
206 xferConfig.destAddr = (uint32_t)destAddr;
207 xferConfig.linkListAddr = 0; /* Don't use LLI */
208 xferConfig.ahbProt = kGDMA_ProtPrevilegedMode;
209 xferConfig.srcBurstSize = kGDMA_BurstSize16;
210 xferConfig.destBurstSize = kGDMA_BurstSize16;
211 xferConfig.srcWidth = kGDMA_TransferWidth1Byte;
212 xferConfig.destWidth = kGDMA_TransferWidth1Byte;
213 xferConfig.srcAddrInc = true;
214 xferConfig.destAddrInc = true;
215 xferConfig.transferLen = len;
216 xferConfig.enableLinkList = false;
217
218 if (KOSA_StatusSuccess == OSA_SemaphoreWait(gdmaSemHandle, osaWaitForever_c))
219 {
220 GDMA_SubmitTransfer(&gdmaHandle, &xferConfig);
221 GDMA_StartTransfer(&gdmaHandle);
222 /* Wait for GMDA transfer done. */
223 (void)OSA_EventWait((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT, 0, osaWaitForever_c, &Events);
224 OSA_SemaphorePost(gdmaSemHandle);
225 }
226 }
227 #endif
228
HAL_ImuSetCpuReadyFlag(uint8_t cpuId)229 static void HAL_ImuSetCpuReadyFlag(uint8_t cpuId)
230 {
231 }
232
HAL_ImuGetCpuReadyFlag(uint8_t cpuId)233 bool HAL_ImuGetCpuReadyFlag(uint8_t cpuId)
234 {
235 return TRUE;
236 }
237
238 /*!
239 * @brief
240 * Create a new imumc endpoint, which can be used
241 * for communication.
242 *
243 * @param handle Imumc instance
244 * @param addr source endpoint address
245 *
246 * @return RL_NULL if not found, node pointer containing the ept on success
247 *
248 */
HAL_ImumcGetEndpointFromAddr(hal_imu_handle_t * imuHandle,uint32_t addr)249 static hal_imumc_handle_t HAL_ImumcGetEndpointFromAddr(hal_imu_handle_t *imuHandle, uint32_t addr)
250 {
251 LIST_ELEM_st *cur;
252 hal_imumc_state_t *pEnd;
253
254 assert(NULL != imuHandle);
255
256 list_for_each(cur, &imuHandle->eptList)
257 {
258 pEnd = (hal_imumc_state_t *)cur;
259 if (pEnd->local_addr == addr)
260 {
261 return pEnd;
262 }
263 }
264
265 return NULL;
266 }
267
HAL_ImumcCreateEndpoint(hal_imumc_handle_t handle)268 static hal_imumc_handle_t HAL_ImumcCreateEndpoint(hal_imumc_handle_t handle)
269 {
270 hal_imu_handle_t *imuHandle;
271 hal_imumc_state_t *imumcHandle;
272 assert(NULL != handle);
273
274 imumcHandle = (hal_imumc_state_t *)handle;
275 imuHandle = &imuHandleCh[imumcHandle->imuLink];
276 // env_lock_mutex(imumcHandle->lock);
277 {
278 if (NULL == HAL_ImumcGetEndpointFromAddr(imuHandle, imumcHandle->local_addr))
279 {
280 LIST_addTail(&imuHandle->eptList, &imumcHandle->eptLink);
281 // env_unlock_mutex(imumcHandle->lock);
282 return imumcHandle;
283 }
284 }
285 // env_unlock_mutex(imumcHandle->lock);
286 return NULL;
287 }
288
HAL_ImumcDestroyEndpoint(hal_imumc_handle_t handle)289 static hal_imumc_status_t HAL_ImumcDestroyEndpoint(hal_imumc_handle_t handle)
290 {
291 hal_imu_handle_t *imuHandle;
292 hal_imumc_state_t *imumcHandle;
293 assert(NULL != handle);
294
295 imumcHandle = (hal_imumc_state_t *)handle;
296 imuHandle = &imuHandleCh[imumcHandle->imuLink];
297
298 // env_lock_mutex(imumcHandle->lock);
299 {
300 imumcHandle = HAL_ImumcGetEndpointFromAddr(imuHandle, imumcHandle->local_addr);
301
302 if (NULL == imumcHandle)
303 {
304 // env_unlock_mutex(imumcHandle->lock);
305 return kStatus_HAL_ImumcError;
306 }
307 LIST_remove(&imuHandle->eptList, &imumcHandle->eptLink);
308 }
309 // env_unlock_mutex(imumcHandle->lock);
310 return kStatus_HAL_ImumcSuccess;
311 }
312
HAL_ImuGetWlanTxBuf(hal_imu_handle_t * imuHandle)313 static uint8_t *HAL_ImuGetWlanTxBuf(hal_imu_handle_t *imuHandle)
314 {
315 uint32_t wlanTxBuf;
316 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
317
318 assert(NULL != imuHandle);
319 wlanTxqCtl = &imuHandle->wlanTxqCtl;
320
321 if (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl))
322 {
323 return NULL;
324 }
325 else
326 {
327 wlanTxBuf = wlanTxqCtl->txBufQue[wlanTxqCtl->readIndex & IMU_TXQ_ENTRY_MASK];
328 INCR_WLAN_TXBQ_RD_INDEX(wlanTxqCtl, 1U);
329 return (uint8_t *)wlanTxBuf;
330 }
331 }
332
HAL_ImuPutWlanTxBuf(hal_imu_handle_t * imuHandle,uint8_t * txBuf)333 static hal_imumc_status_t HAL_ImuPutWlanTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
334 {
335 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
336 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
337
338 assert(NULL != imuHandle);
339 wlanTxqCtl = &imuHandle->wlanTxqCtl;
340
341 if (IS_WLAN_TXBQ_FULL(wlanTxqCtl))
342 {
343 state = kStatus_HAL_ImumcError;
344 }
345 else
346 {
347 wlanTxqCtl->txBufQue[wlanTxqCtl->writeIndex & IMU_TXQ_ENTRY_MASK] = (uint32_t)txBuf;
348 INCR_WLAN_TXBQ_WR_INDEX(wlanTxqCtl, 1U);
349 }
350
351 return state;
352 }
353
HAL_ImumcGetTxBuf(hal_imu_handle_t * imuHandle)354 static uint8_t *HAL_ImumcGetTxBuf(hal_imu_handle_t *imuHandle)
355 {
356 uint8_t *imumcTxBuf = NULL;
357 IMUMC_TXQ_CTRL_st *imumcTxqCtl;
358 OSA_SR_ALLOC();
359
360 assert(NULL != imuHandle);
361 imumcTxqCtl = &imuHandle->imumcTxqCtl;
362
363 OSA_ENTER_CRITICAL();
364
365 do
366 {
367 if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
368 {
369 if (IS_IMUMC_TXBQ23_EMPTY(imumcTxqCtl))
370 {
371 break;
372 }
373 else
374 {
375 imumcTxBuf = (uint8_t *)(imumcTxqCtl->txBufQue[imumcTxqCtl->readIndex & IMUMC_TXQ23_ENTRY_MASK]);
376 INCR_IMUMC_TXBQ23_RD_INDEX(imumcTxqCtl, 1U);
377 }
378 }
379 else
380 {
381 if (IS_IMUMC_TXBQ13_EMPTY(imumcTxqCtl))
382 {
383 break;
384 }
385 else
386 {
387 imumcTxBuf = (uint8_t *)(imumcTxqCtl->txBufQue[imumcTxqCtl->readIndex & IMUMC_TXQ13_ENTRY_MASK]);
388 INCR_IMUMC_TXBQ13_RD_INDEX(imumcTxqCtl, 1U);
389 }
390 }
391 } while (false);
392
393 OSA_EXIT_CRITICAL();
394
395 return imumcTxBuf;
396 }
397
HAL_ImumcPutTxBuf(hal_imu_handle_t * imuHandle,uint8_t * txBuf)398 static hal_imumc_status_t HAL_ImumcPutTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
399 {
400 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
401 IMUMC_TXQ_CTRL_st *imumcTxqCtl;
402 OSA_SR_ALLOC();
403
404 assert(NULL != imuHandle);
405 imumcTxqCtl = &imuHandle->imumcTxqCtl;
406
407 OSA_ENTER_CRITICAL();
408
409 if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
410 {
411 if (IS_IMUMC_TXBQ23_FULL(imumcTxqCtl))
412 {
413 state = kStatus_HAL_ImumcError;
414 }
415 else
416 {
417 imumcTxqCtl->txBufQue[imumcTxqCtl->writeIndex & IMUMC_TXQ23_ENTRY_MASK] = (uint32_t)txBuf;
418 INCR_IMUMC_TXBQ23_WR_INDEX(imumcTxqCtl, 1U);
419 }
420 }
421 else
422 {
423 if (IS_IMUMC_TXBQ13_FULL(imumcTxqCtl))
424 {
425 state = kStatus_HAL_ImumcError;
426 }
427 else
428 {
429 imumcTxqCtl->txBufQue[imumcTxqCtl->writeIndex & IMUMC_TXQ13_ENTRY_MASK] = (uint32_t)txBuf;
430 INCR_IMUMC_TXBQ13_WR_INDEX(imumcTxqCtl, 1U);
431 }
432 }
433
434 OSA_EXIT_CRITICAL();
435
436 return state;
437 }
438
HAL_ImuLinkIsUp(uint8_t imuLink)439 hal_imumc_status_t HAL_ImuLinkIsUp(uint8_t imuLink)
440 {
441 hal_imu_handle_t *imuHandle;
442
443 assert((uint8_t)kIMU_LinkMax > imuLink);
444 imuHandle = &imuHandleCh[imuLink];
445
446 if ((uint8_t)IMU_INITIALIZED == imuHandle->imuSyncState)
447 {
448 return kStatus_HAL_ImumcSuccess;
449 }
450 else
451 {
452 return kStatus_HAL_ImumcError;
453 }
454 }
455
HAL_ImuResetWlanTxq(uint8_t imuLink)456 void HAL_ImuResetWlanTxq(uint8_t imuLink)
457 {
458 hal_imu_handle_t *imuHandle = NULL;
459
460 imuHandle = &imuHandleCh[imuLink];
461 imuHandle->wlanTxqCtl.writeIndex = 0;
462 imuHandle->wlanTxqCtl.readIndex = 0;
463 }
464
HAL_ImuSendMsgBlockingCommon(hal_imu_handle_t * imuHandle,uint8_t type,uint8_t subtype,uint8_t * data,uint32_t length,bool lockTxFifo)465 static hal_imumc_status_t HAL_ImuSendMsgBlockingCommon(
466 hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length, bool lockTxFifo)
467 {
468 IMU_Msg_t *imuMsg;
469 IMU_Msg_t localImuMsg;
470 OSA_SR_ALLOC();
471 int32_t ret = 0;
472
473 assert(NULL != imuHandle);
474 assert(IMU_PAYLOAD_SIZE >= length);
475
476 (void)memset((void *)&localImuMsg, 0, sizeof(IMU_Msg_t));
477
478 localImuMsg.Hdr.type = type;
479 localImuMsg.Hdr.sub_type = subtype;
480 localImuMsg.Hdr.seq_num = seq_num & (uint8_t)0xff;
481
482 switch ((imu_msg_type_t)type)
483 {
484 case IMU_MSG_CONTROL:
485 if (((uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR == subtype) ||
486 ((uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF == subtype) ||
487 ((uint8_t)IMU_MSG_CONTROL_CMD_BUF_ADDR == subtype) || ((uint8_t)IMU_MSG_CONTROL_EVT_ACK == subtype) ||
488 ((uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK == subtype) ||
489 ((uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY == subtype) ||
490 ((uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP == subtype) ||
491 ((uint8_t)IMU_MSG_CONTROL_IMUMC_BUF_FREE == subtype) ||
492 ((uint8_t)IMU_MSG_CONTROL_EVT_DUMP == subtype) || ((uint8_t)IMU_MSG_CONTROL_ERROR == subtype))
493 {
494 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
495 localImuMsg.Hdr.length = (uint8_t)length;
496 }
497 break;
498 case IMU_MSG_COMMAND:
499 if (imuHandle->cmd_buffer_available)
500 {
501 localImuMsg.Hdr.length = 1;
502 localImuMsg.PayloadPtr[0] = (uint32_t)imuHandle->cmd_buffer;
503 }
504 else
505 {
506 return kStatus_HAL_ImumcError;
507 }
508 break;
509 case IMU_MSG_TX_DATA:
510 localImuMsg.Hdr.length = 1;
511 localImuMsg.PayloadPtr[0] = (uint32_t)data;
512 break;
513 case IMU_MSG_MULTI_TX_DATA:
514 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], imuHandle->imuMsgBuf, (imuHandle->imuMsgBufIdx) << 2U);
515 localImuMsg.Hdr.length = imuHandle->imuMsgBufIdx;
516 imuHandle->imuMsgBufIdx = 0;
517 break;
518 case IMU_MSG_IMUMC:
519 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
520 localImuMsg.Hdr.length = length;
521 break;
522 default:
523 // Do nothing for the commands without expansion.
524 break;
525 }
526
527 /* Added at 02/18/2022, in case second task overwriting imuMsg*/
528 while (IMU_TX_FIFO_ALMOST_FULL((imu_link_t)imuHandle->imuLink))
529 {
530 }
531
532 OSA_ENTER_CRITICAL();
533 imuMsg = (IMU_Msg_t *)&((IMU_MSG_SND_Q(imuHandle->imuLink))[IMU_WR_PTR(imuHandle->imuLink)]);
534 (void)memcpy(imuMsg, &localImuMsg, sizeof(IMU_Hdr_t) + ((uint32_t)localImuMsg.Hdr.length << 2U));
535 ret = IMU_SendMsgPtrBlocking((imu_link_t)imuHandle->imuLink, (uint32_t)imuMsg, lockTxFifo);
536 OSA_EXIT_CRITICAL();
537
538 if (0 == ret)
539 {
540 return kStatus_HAL_ImumcSuccess;
541 }
542 else
543 {
544 return kStatus_HAL_ImumcError;
545 }
546 }
547
HAL_ImuSendMsgBlocking(hal_imu_handle_t * imuHandle,uint8_t type,uint8_t subtype,uint8_t * data,uint32_t length)548 static hal_imumc_status_t HAL_ImuSendMsgBlocking(
549 hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length)
550 {
551 return HAL_ImuSendMsgBlockingCommon(imuHandle, type, subtype, data, length, FALSE);
552 }
553
HAL_ImuSendSync(hal_imu_handle_t * imuHandle)554 static hal_imumc_status_t HAL_ImuSendSync(hal_imu_handle_t *imuHandle)
555 {
556 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
557 OSA_SR_ALLOC();
558 assert(NULL != imuHandle);
559
560 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = IMU_SYNC_MAGIC_PATTERN;
561 while (IMU_SYNC_MAGIC_PATTERN != (*IMU_MSG_CUR_MAGIC_P((imu_link_t)imuHandle->imuLink)))
562 {
563 }
564
565 OSA_ENTER_CRITICAL();
566 if (((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState) &&
567 (IMU_SYNC_MAGIC_PATTERN == (*IMU_MSG_PEER_MAGIC_P(imuHandle->imuLink))))
568 {
569 if (kStatus_HAL_ImumcSuccess ==
570 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC, NULL, 0))
571 {
572 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZING;
573 seq_num++;
574 }
575 else
576 {
577 imumcStatus = kStatus_HAL_ImumcError;
578 }
579 }
580 OSA_EXIT_CRITICAL();
581
582 return imumcStatus;
583 }
584
HAL_ImuSendImumcEptQuiry(hal_imu_handle_t * imuHandle,uint32_t addr)585 static hal_imumc_status_t HAL_ImuSendImumcEptQuiry(hal_imu_handle_t *imuHandle, uint32_t addr)
586 {
587 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
588 OSA_SR_ALLOC();
589 assert(NULL != imuHandle);
590
591 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
592 {
593 return kStatus_HAL_ImumcError;
594 }
595
596 OSA_ENTER_CRITICAL();
597 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
598 (uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY, (uint8_t *)&addr,
599 1))
600 {
601 seq_num++;
602 }
603 else
604 {
605 imumcStatus = kStatus_HAL_ImumcError;
606 }
607 OSA_EXIT_CRITICAL();
608
609 return imumcStatus;
610 }
611
HAL_ImuSendImumcEptQuiryRsp(hal_imu_handle_t * imuHandle,uint32_t addr,bool found)612 static hal_imumc_status_t HAL_ImuSendImumcEptQuiryRsp(hal_imu_handle_t *imuHandle, uint32_t addr, bool found)
613 {
614 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
615 uint32_t quiryRsp[2];
616 OSA_SR_ALLOC();
617
618 assert(NULL != imuHandle);
619
620 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
621 {
622 return kStatus_HAL_ImumcError;
623 }
624
625 OSA_ENTER_CRITICAL();
626 quiryRsp[0] = addr;
627 if (TRUE == found)
628 {
629 quiryRsp[1] = 1;
630 }
631 else
632 {
633 quiryRsp[1] = 0;
634 }
635
636 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
637 (uint8_t)IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP,
638 (uint8_t *)&quiryRsp[0], 2))
639 {
640 seq_num++;
641 }
642 else
643 {
644 imumcStatus = kStatus_HAL_ImumcError;
645 }
646 OSA_EXIT_CRITICAL();
647
648 return imumcStatus;
649 }
650
HAL_ImuSendImumcFreeBuf(hal_imu_handle_t * imuHandle,uint8_t * buf)651 static hal_imumc_status_t HAL_ImuSendImumcFreeBuf(hal_imu_handle_t *imuHandle, uint8_t *buf)
652 {
653 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
654 OSA_SR_ALLOC();
655 assert(NULL != imuHandle);
656
657 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
658 {
659 return kStatus_HAL_ImumcError;
660 }
661
662 OSA_ENTER_CRITICAL();
663 if (kStatus_HAL_ImumcSuccess ==
664 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_IMUMC_BUF_FREE, buf, 1U))
665 {
666 seq_num++;
667 }
668 else
669 {
670 imumcStatus = kStatus_HAL_ImumcError;
671 }
672 OSA_EXIT_CRITICAL();
673
674 return imumcStatus;
675 }
676
HAL_ImuSendEventAck(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)677 static hal_imumc_status_t HAL_ImuSendEventAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
678 {
679 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
680 OSA_SR_ALLOC();
681 assert(NULL != imuHandle);
682
683 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
684 {
685 return kStatus_HAL_ImumcError;
686 }
687
688 OSA_ENTER_CRITICAL();
689 if (kStatus_HAL_ImumcSuccess ==
690 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_ACK, rxBuf, length))
691 {
692 seq_num++;
693 }
694 else
695 {
696 imumcStatus = kStatus_HAL_ImumcError;
697 }
698 OSA_EXIT_CRITICAL();
699
700 return imumcStatus;
701 }
702
HAL_ImuSendEventDumpAck(imu_link_t link,uint8_t * rxBuf,uint8_t length)703 hal_imumc_status_t HAL_ImuSendEventDumpAck(imu_link_t link, uint8_t *rxBuf, uint8_t length)
704 {
705 hal_imu_handle_t *imuHandle;
706 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
707 OSA_SR_ALLOC();
708
709 assert(kIMU_LinkMax > link);
710 imuHandle = &imuHandleCh[link];
711
712 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
713 {
714 return kStatus_HAL_ImumcError;
715 }
716
717 OSA_ENTER_CRITICAL();
718 if (kStatus_HAL_ImumcSuccess ==
719 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_DUMP, rxBuf, length))
720 {
721 seq_num++;
722 }
723 else
724 {
725 imumcStatus = kStatus_HAL_ImumcError;
726 }
727
728 OSA_EXIT_CRITICAL();
729
730 return imumcStatus;
731 }
732
HAL_ImuSendCommandRspAck(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)733 static hal_imumc_status_t HAL_ImuSendCommandRspAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
734 {
735 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
736 OSA_SR_ALLOC();
737 assert(NULL != imuHandle);
738
739 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
740 {
741 return kStatus_HAL_ImumcError;
742 }
743
744 OSA_ENTER_CRITICAL();
745 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
746 (uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK, rxBuf, length))
747 {
748 seq_num++;
749 }
750 else
751 {
752 imumcStatus = kStatus_HAL_ImumcError;
753 }
754 OSA_EXIT_CRITICAL();
755
756 return imumcStatus;
757 }
758
HAL_ImuFreeRxBuf(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)759 static hal_imumc_status_t HAL_ImuFreeRxBuf(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
760 {
761 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
762 OSA_SR_ALLOC();
763 assert(NULL != imuHandle);
764
765 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
766 {
767 return kStatus_HAL_ImumcError;
768 }
769
770 OSA_ENTER_CRITICAL();
771 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
772 (uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF, rxBuf, length))
773 {
774 seq_num++;
775 }
776 else
777 {
778 imumcStatus = kStatus_HAL_ImumcError;
779 }
780 OSA_EXIT_CRITICAL();
781
782 return imumcStatus;
783 }
784
HAL_ImuSendCommand(uint8_t imuLink,uint8_t * cmdBuf,uint32_t length)785 hal_imumc_status_t HAL_ImuSendCommand(uint8_t imuLink, uint8_t *cmdBuf, uint32_t length)
786 {
787 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
788 hal_imu_handle_t *imuHandle;
789 OSA_SR_ALLOC();
790
791 assert((uint8_t)kIMU_LinkMax > imuLink);
792 imuHandle = &imuHandleCh[imuLink];
793
794 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink) || FALSE == imuHandle->cmd_buffer_available)
795 {
796 return kStatus_HAL_ImumcError;
797 }
798
799 if (length != 0U)
800 {
801 // To be DMAed
802 (void)HAL_IMU_MEMCPY((void *)imuHandle->cmd_buffer, cmdBuf, length);
803 }
804 else
805 {
806 return kStatus_HAL_ImumcError;
807 }
808
809 OSA_ENTER_CRITICAL();
810 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_COMMAND, 0U, NULL, 0))
811 {
812 seq_num++;
813 imuHandle->cmd_buffer_available = FALSE;
814 }
815 else
816 {
817 imumcStatus = kStatus_HAL_ImumcError;
818 }
819 OSA_EXIT_CRITICAL();
820
821 return imumcStatus;
822 }
823
HAL_ImuSendTxData(uint8_t imuLink,uint8_t * txBuf,uint32_t length)824 hal_imumc_status_t HAL_ImuSendTxData(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
825 {
826 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
827 hal_imu_handle_t *imuHandle;
828 uint8_t *wlan_tx_buf;
829 OSA_SR_ALLOC();
830
831 assert((uint8_t)kIMU_LinkMax > imuLink);
832 imuHandle = &imuHandleCh[imuLink];
833
834 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
835 {
836 return kStatus_HAL_ImumcError;
837 }
838
839 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
840 if ((wlan_tx_buf != NULL) && (length != 0U))
841 {
842 // To be DMAed
843 (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
844 }
845 else
846 {
847 return kStatus_HAL_ImumcError;
848 }
849
850 OSA_ENTER_CRITICAL();
851 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_TX_DATA, 0U, wlan_tx_buf, 1U))
852 {
853 seq_num++;
854 }
855 else
856 {
857 (void)HAL_ImuPutWlanTxBuf(imuHandle, wlan_tx_buf);
858 imumcStatus = kStatus_HAL_ImumcError;
859 }
860 OSA_EXIT_CRITICAL();
861
862 return imumcStatus;
863 }
864
HAL_ImuAddWlanTxPacket(uint8_t imuLink,uint8_t * txBuf,uint32_t length)865 hal_imumc_status_t HAL_ImuAddWlanTxPacket(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
866 {
867 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
868 hal_imu_handle_t *imuHandle;
869 uint8_t *wlan_tx_buf;
870
871 assert((uint8_t)kIMU_LinkMax > imuLink);
872 assert(NULL != txBuf);
873 assert(0U != length);
874 imuHandle = &imuHandleCh[imuLink];
875
876 if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
877 {
878 return kStatus_HAL_ImumcError;
879 }
880
881 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
882
883 if (NULL == wlan_tx_buf)
884 {
885 return kStatus_HAL_ImumcError;
886 }
887
888 // To be DMAed
889 (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
890
891 imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
892 imuHandle->imuMsgBufIdx++;
893
894 return imumcStatus;
895 }
896
HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,uint8_t * txBuf,uint32_t length,void (* cb)(void * destAddr,void * srcAddr,uint32_t len))897 hal_imumc_status_t HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,
898 uint8_t *txBuf,
899 uint32_t length,
900 void (*cb)(void *destAddr, void *srcAddr, uint32_t len))
901 {
902 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
903 hal_imu_handle_t *imuHandle;
904 uint8_t *wlan_tx_buf;
905
906 assert((uint8_t)kIMU_LinkMax > imuLink);
907 assert(NULL != txBuf);
908 assert(0U != length);
909 imuHandle = &imuHandleCh[imuLink];
910
911 if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
912 {
913 return kStatus_HAL_ImumcError;
914 }
915
916 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
917
918 if (NULL == wlan_tx_buf)
919 {
920 return kStatus_HAL_ImumcError;
921 }
922
923 // To be DMAed
924 cb(wlan_tx_buf, txBuf, length);
925
926 imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
927 imuHandle->imuMsgBufIdx++;
928
929 return imumcStatus;
930 }
931
HAL_ImuSendMultiTxData(uint8_t imuLink)932 hal_imumc_status_t HAL_ImuSendMultiTxData(uint8_t imuLink)
933 {
934 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
935 hal_imu_handle_t *imuHandle;
936 OSA_SR_ALLOC();
937
938 assert((uint8_t)kIMU_LinkMax > imuLink);
939 imuHandle = &imuHandleCh[imuLink];
940
941 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
942 {
943 return kStatus_HAL_ImumcError;
944 }
945
946 OSA_ENTER_CRITICAL();
947 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_MULTI_TX_DATA, 0U, NULL, 0U))
948 {
949 seq_num++;
950 imuHandle->imuMsgBufIdx = 0;
951 }
952 else
953 {
954 imumcStatus = kStatus_HAL_ImumcError;
955 }
956 OSA_EXIT_CRITICAL();
957
958 return imumcStatus;
959 }
960
HAL_ImuSendSyncAck(hal_imu_handle_t * imuHandle)961 static hal_imumc_status_t HAL_ImuSendSyncAck(hal_imu_handle_t *imuHandle)
962 {
963 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
964 OSA_SR_ALLOC();
965 assert(NULL != imuHandle);
966
967 OSA_ENTER_CRITICAL();
968 if (kStatus_HAL_ImumcSuccess ==
969 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC_ACK, NULL, 0U))
970 {
971 seq_num++;
972 }
973 else
974 {
975 imumcStatus = kStatus_HAL_ImumcError;
976 }
977 OSA_EXIT_CRITICAL();
978
979 return imumcStatus;
980 }
981
HAL_ImuSendUnlock(hal_imu_handle_t * imuHandle)982 static hal_imumc_status_t HAL_ImuSendUnlock(hal_imu_handle_t *imuHandle)
983 {
984 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
985 OSA_SR_ALLOC();
986 assert(NULL != imuHandle);
987
988 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
989 {
990 return kStatus_HAL_ImumcError;
991 }
992
993 OSA_ENTER_CRITICAL();
994 if (kStatus_HAL_ImumcSuccess ==
995 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_ACK_FOR_UNLOCK, NULL, 0U))
996 {
997 seq_num++;
998 }
999 else
1000 {
1001 imumcStatus = kStatus_HAL_ImumcError;
1002 }
1003 OSA_EXIT_CRITICAL();
1004
1005 return imumcStatus;
1006 }
1007
HAL_ImuReturnAllTxBuf(imu_link_t link)1008 hal_imumc_status_t HAL_ImuReturnAllTxBuf(imu_link_t link)
1009 {
1010 hal_imu_handle_t *imuHandle;
1011 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1012 uint8_t txBufCnt;
1013 uint8_t *wlan_tx_buf;
1014 OSA_SR_ALLOC();
1015
1016 assert(kIMU_LinkMax > link);
1017 imuHandle = &imuHandleCh[link];
1018
1019 txBufCnt = 0;
1020 while (TRUE)
1021 {
1022 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
1023 if (NULL == wlan_tx_buf) /*! all Tx buffers are consumed */
1024 {
1025 break;
1026 }
1027
1028 imuHandle->imuMsgBuf[txBufCnt] = (uint32_t)wlan_tx_buf;
1029 txBufCnt++;
1030
1031 if (IMU_PAYLOAD_SIZE == txBufCnt)
1032 {
1033 OSA_ENTER_CRITICAL();
1034 if (kStatus_HAL_ImumcSuccess !=
1035 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
1036 (uint8_t *)&imuHandle->imuMsgBuf[0], (uint32_t)IMU_PAYLOAD_SIZE))
1037 {
1038 OSA_EXIT_CRITICAL();
1039 return kStatus_HAL_ImumcError;
1040 }
1041 else
1042 {
1043 seq_num++;
1044 }
1045 txBufCnt = 0;
1046 OSA_EXIT_CRITICAL();
1047 }
1048 }
1049
1050 if (txBufCnt != 0U)
1051 {
1052 OSA_ENTER_CRITICAL();
1053 if (kStatus_HAL_ImumcSuccess != HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
1054 (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
1055 (uint8_t *)&imuHandle->imuMsgBuf[0], txBufCnt))
1056 {
1057 OSA_EXIT_CRITICAL();
1058 return kStatus_HAL_ImumcError;
1059 }
1060 else
1061 {
1062 seq_num++;
1063 }
1064 OSA_EXIT_CRITICAL();
1065 }
1066
1067 return imumcStatus;
1068 }
1069
HAL_ImuSendShutdown(hal_imu_handle_t * imuHandle)1070 static hal_imumc_status_t HAL_ImuSendShutdown(hal_imu_handle_t *imuHandle)
1071 {
1072 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1073 OSA_SR_ALLOC();
1074 assert(NULL != imuHandle);
1075
1076 if (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
1077 {
1078 return kStatus_HAL_ImumcError;
1079 }
1080
1081 OSA_ENTER_CRITICAL();
1082 if (kStatus_HAL_ImumcSuccess ==
1083 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SHUTDOWN, NULL, 0U))
1084 {
1085 seq_num++;
1086 }
1087 else
1088 {
1089 imumcStatus = kStatus_HAL_ImumcError;
1090 }
1091 OSA_EXIT_CRITICAL();
1092
1093 return imumcStatus;
1094 }
1095
HAL_ImuCtrlHandler(hal_imu_handle_t * imuHandle,IMU_Msg_t * data,uint32_t len)1096 static hal_imumc_status_t HAL_ImuCtrlHandler(hal_imu_handle_t *imuHandle, IMU_Msg_t *data, uint32_t len)
1097 {
1098 imu_ctrl_msg_subtype_t imuControlType;
1099 IMU_Msg_t *pImuMsg = data;
1100 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1101 hal_imumc_state_t *imumcHandle;
1102 OSA_SR_ALLOC();
1103 LIST_ELEM_st *cur;
1104 uint8_t eptQuiryRspAck;
1105
1106 assert(NULL != imuHandle);
1107 imuControlType = (imu_ctrl_msg_subtype_t)pImuMsg->Hdr.sub_type;
1108 OSA_ENTER_CRITICAL();
1109
1110 switch (imuControlType)
1111 {
1112 case IMU_MSG_CONTROL_ACK_FOR_UNLOCK:
1113 IMU_UNLOCK_TX_FIFO(imuHandle->imuLink);
1114 break;
1115 case IMU_MSG_CONTROL_SYNC:
1116 (void)HAL_ImuSendSyncAck(imuHandle);
1117 if ((uint8_t)kIMU_LinkCpu2Cpu3 == imuHandle->imuLink)
1118 {
1119 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1120 }
1121 (void)HAL_ImuSendSyncAck(imuHandle);
1122 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1123 break;
1124 case IMU_MSG_CONTROL_SYNC_ACK:
1125 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1126 break;
1127 case IMU_MSG_CONTROL_CMD_BUF_ADDR:
1128 imuHandle->cmd_buffer = (uint32_t *)pImuMsg->PayloadPtr[0];
1129 imuHandle->cmd_buffer_available = TRUE;
1130 if ((uint8_t)IMU_INITIALIZED != imuHandle->imuSyncState)
1131 {
1132 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1133 }
1134 break;
1135 case IMU_MSG_CONTROL_TX_BUF_ADDR:
1136 for (uint8_t i = 0; i < pImuMsg->Hdr.length; i++)
1137 {
1138 (void)HAL_ImuPutWlanTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[i]);
1139 }
1140 break;
1141 case IMU_MSG_CONTROL_ERROR:
1142 break;
1143 case IMU_MSG_CONTROL_SHUTDOWN:
1144 imuHandle->imuSyncState = (uint8_t)IMU_UNINITIALIZED;
1145 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1146 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
1147 (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1148 IMU_Deinit((imu_link_t)imuHandle->imuLink);
1149 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
1150 imuHandle->wlanTxqCtl.writeIndex = 0;
1151 imuHandle->wlanTxqCtl.readIndex = 0;
1152 break;
1153 case IMU_MSG_CONTROL_IMUMC_EPT_QUIRY:
1154 {
1155 hal_imumc_state_t *imumcHandle = HAL_ImumcGetEndpointFromAddr(imuHandle, pImuMsg->PayloadPtr[0]);
1156 if (imumcHandle != NULL)
1157 {
1158 /* The remote CPU is sending an endpoint query so it implies the imumc link is ready */
1159 imumcHandle->eptLinkIsReady = TRUE;
1160 /* Confirm the local endpoint is ready too */
1161 imumcStatus = HAL_ImuSendImumcEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], TRUE);
1162 /* Make sure to unblock the task calling HAL_ImumcInit */
1163 #ifdef __ZEPHYR__
1164 k_event_set(&imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1165 #else
1166 (void)OSA_EventSet((osa_event_handle_t)imumcQFlagsRef,
1167 IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1168 #endif
1169 }
1170 else
1171 {
1172 /* Local endpoint doesn't exist yet, the remote CPU needs to wait until the local CPU initializes
1173 * the targeted endpoint, a new query will be sent then to update the link status on both sides */
1174 imumcStatus = HAL_ImuSendImumcEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], FALSE);
1175 }
1176 }
1177 break;
1178 case IMU_MSG_CONTROL_IMUMC_EPT_QUIRY_RSP:
1179 eptQuiryRspAck = 0;
1180 list_for_each(cur, &imuHandle->eptList)
1181 {
1182 imumcHandle = (hal_imumc_state_t *)cur;
1183 if (imumcHandle->remote_addr == pImuMsg->PayloadPtr[0])
1184 {
1185 if (pImuMsg->PayloadPtr[1] != 0U)
1186 {
1187 eptQuiryRspAck = 1;
1188 imumcHandle->eptLinkIsReady = TRUE;
1189 }
1190 else
1191 {
1192 imumcHandle->eptLinkIsReady = FALSE;
1193 }
1194 }
1195 }
1196
1197 if (eptQuiryRspAck != 0U)
1198 {
1199 /* Make sure to unblock the task calling HAL_ImumcInit */
1200 #ifdef __ZEPHYR__
1201 k_event_set(&imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1202 #else
1203 (void)OSA_EventSet((osa_event_handle_t)imumcQFlagsRef,
1204 IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1205 #endif
1206 }
1207 break;
1208 case IMU_MSG_CONTROL_IMUMC_BUF_FREE:
1209 (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[0]);
1210 break;
1211 default:
1212 // Do nothing for the commands without header expansion.
1213 break;
1214 }
1215
1216 OSA_EXIT_CRITICAL();
1217 return imumcStatus;
1218 }
1219
HAL_ImuReceive(uint8_t imuLink)1220 hal_imumc_status_t HAL_ImuReceive(uint8_t imuLink)
1221 {
1222 IMU_Msg_t *pMsg = NULL, localImuMsg;
1223 IMU_Msg_t localImuMsgRx;
1224
1225 hal_imu_handle_t *imuHandle = NULL;
1226 imu_msg_type_t msg_type = IMU_MSG_MAX;
1227 bool isUnlockMsgReqd = FALSE;
1228 hal_imumc_state_t *ept;
1229 struct imumc_std_msg *imumc_msg;
1230 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1231
1232 assert((uint8_t)kIMU_LinkMax > imuLink);
1233 imuHandle = &imuHandleCh[imuLink];
1234
1235 while (TRUE)
1236 {
1237 if (IMU_RX_FIFO_EMPTY((imu_link_t)imuHandle->imuLink))
1238 {
1239 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1240 os_ClearPendingISR(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1241 #ifndef CPU2
1242 *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) |= (uint32_t)(1 << 0U);
1243 #endif
1244 break;
1245 }
1246 else
1247 {
1248 #ifndef CPU2
1249 *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) &= (uint32_t)(~(1 << 0U));
1250 #endif
1251
1252 /* Message buffer pMsg should be consumed (or copied for later
1253 * processing) in handler before call for next READ_ICC_MESSAGE
1254 * comes here again.
1255 * Otherwise other CPU may use same pMsg for next write,
1256 * when FIFO is almost full
1257 */
1258 pMsg = (IMU_Msg_t *)IMU_RD_MSG(imuHandle->imuLink);
1259 if ((pMsg != NULL) && (IMU_RX_FIFO_LOCKED(imuHandle->imuLink)))
1260 {
1261 isUnlockMsgReqd = TRUE;
1262 }
1263 }
1264
1265 /* release CPU access here because message processing may take time */
1266 if (pMsg != NULL)
1267 {
1268 (void)memcpy((uint8_t *)&localImuMsg, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
1269 pMsg = &localImuMsg;
1270 msg_type = (imu_msg_type_t)pMsg->Hdr.type;
1271
1272 switch (msg_type)
1273 {
1274 case IMU_MSG_CONTROL:
1275 imumcStatus = HAL_ImuCtrlHandler(imuHandle, pMsg, pMsg->Hdr.length);
1276 if (imuHandle->imuHandler[IMU_MSG_CONTROL] != NULL)
1277 {
1278 imumcStatus = imuHandle->imuHandler[IMU_MSG_CONTROL]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1279 }
1280 break;
1281 case IMU_MSG_COMMAND_RESPONSE:
1282 if (imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE] != NULL)
1283 {
1284 imumcStatus =
1285 imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1286 }
1287 assert(kStatus_HAL_ImumcSuccess == imumcStatus);
1288 imumcStatus = HAL_ImuSendCommandRspAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
1289 imuHandle->cmd_buffer_available = TRUE;
1290 break;
1291
1292 case IMU_MSG_EVENT:
1293 if (imuHandle->imuHandler[IMU_MSG_EVENT] != NULL)
1294 {
1295 imumcStatus = imuHandle->imuHandler[IMU_MSG_EVENT]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1296 }
1297 assert(kStatus_HAL_ImumcSuccess == imumcStatus);
1298 imumcStatus = HAL_ImuSendEventAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
1299 break;
1300
1301 case IMU_MSG_RX_DATA:
1302 case IMU_MSG_MULTI_RX_DATA:
1303 (void)memcpy((uint8_t *)&localImuMsgRx, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
1304 if (imuHandle->imuHandler[IMU_MSG_RX_DATA] != NULL)
1305 {
1306 imumcStatus = imuHandle->imuHandler[IMU_MSG_RX_DATA]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1307 }
1308 pMsg = &localImuMsgRx;
1309 imumcStatus = HAL_ImuFreeRxBuf(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], pMsg->Hdr.length);
1310 break;
1311 case IMU_MSG_IMUMC:
1312 imumc_msg = (struct imumc_std_msg *)&pMsg->PayloadPtr[0];
1313 ept = (hal_imumc_state_t *)HAL_ImumcGetEndpointFromAddr(imuHandle, imumc_msg->hdr.dst);
1314 if (NULL != ept)
1315 {
1316 if (ept->rx.callback != NULL)
1317 {
1318 imumcStatus = (hal_imumc_status_t)ept->rx.callback(
1319 ept->rx.param, (uint8_t *)imumc_msg->data, imumc_msg->hdr.len);
1320 }
1321 }
1322 if ((hal_imumc_return_status_t)imumcStatus == kStatus_HAL_RL_RELEASE)
1323 {
1324 imumcStatus = HAL_ImuSendImumcFreeBuf(imuHandle, (uint8_t *)&imumc_msg->data);
1325 }
1326 break;
1327
1328 default:
1329 // Do nothing for the commands without expansion.
1330 break;
1331 }
1332
1333 assert(kStatus_HAL_ImumcSuccess == imumcStatus);
1334 }
1335 }
1336
1337 if (isUnlockMsgReqd)
1338 {
1339 (void)HAL_ImuSendUnlock(imuHandle);
1340 }
1341
1342 (void)os_InterruptMaskSet(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1343 return (hal_imumc_status_t)imumcStatus;
1344 }
1345
1346 #if defined(CPU2)
HAL_ImuMain(void * argv)1347 static void HAL_ImuMain(void *argv)
1348 {
1349 uint32_t Events = 0;
1350 uint32_t imuLinkId;
1351
1352 while (TRUE)
1353 {
1354 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1355 (void)HAL_ImuPutTaskLock();
1356 #endif
1357 (void)OSA_EventWait((osa_event_handle_t)ImuQFlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1358 if (Events == 0U)
1359 {
1360 if (gUseRtos_c == 0U)
1361 {
1362 break;
1363 }
1364 else
1365 {
1366 continue;
1367 }
1368 }
1369 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1370 (void)HAL_ImuGetTaskLock();
1371 #endif
1372 /*! Check for all IMU links event/ISR has occured
1373 * Only MSG ready events considered
1374 */
1375 for (imuLinkId = 0; imuLinkId < (uint32_t)kIMU_LinkMax; imuLinkId++)
1376 {
1377 if ((Events & (1U << imuLinkId)) != 0U)
1378 {
1379 (void)HAL_ImuReceive((uint8_t)imuLinkId);
1380 }
1381 }
1382 if (gUseRtos_c == 0U)
1383 {
1384 break;
1385 }
1386 }
1387 }
1388 #else
1389
HAL_ImuMainCpu13(void * argv,void * argv2,void * argv3)1390 static void HAL_ImuMainCpu13(void *argv
1391 #ifdef __ZEPHYR__
1392 ,
1393 void *argv2,
1394 void *argv3
1395 #endif
1396 )
1397 {
1398 uint32_t Events = 0;
1399
1400 while (TRUE)
1401 {
1402 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1403 (void)HAL_ImuPutTaskLock();
1404 #endif
1405
1406 #ifdef __ZEPHYR__
1407 Events = k_event_wait(&ImuQ13FlagsRef, IMU_EVENT_TRIGGERS, 0, K_FOREVER);
1408 k_event_clear(&ImuQ13FlagsRef, (1U << kIMU_LinkCpu1Cpu3));
1409 #else
1410 (void)OSA_EventWait((osa_event_handle_t)ImuQ13FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1411 #endif
1412
1413 if (Events == 0U)
1414 {
1415 if (gUseRtos_c == 0U)
1416 {
1417 break;
1418 }
1419 else
1420 {
1421 continue;
1422 }
1423 }
1424 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1425 (void)HAL_ImuGetTaskLock();
1426 #endif
1427 /*! Check for CPU1 to CPU3 IMU links event/ISR has occured
1428 * Only MSG ready events considered
1429 */
1430 (void)HAL_ImuReceive(kIMU_LinkCpu1Cpu3);
1431
1432 if (gUseRtos_c == 0U)
1433 {
1434 break;
1435 }
1436 }
1437 }
1438
HAL_ImuMainCpu23(void * argv,void * argv2,void * argv3)1439 static void HAL_ImuMainCpu23(void *argv
1440 #ifdef __ZEPHYR__
1441 ,
1442 void *argv2,
1443 void *argv3
1444 #endif
1445 )
1446 {
1447 uint32_t Events = 0;
1448
1449 while (TRUE)
1450 {
1451 #if 0
1452 HAL_ImuPutTaskLock();
1453 #endif
1454
1455 #ifdef __ZEPHYR__
1456 Events = k_event_wait(&ImuQ23FlagsRef, IMU_EVENT_TRIGGERS, 0, K_FOREVER);
1457 k_event_clear(&ImuQ23FlagsRef, (1U << kIMU_LinkCpu2Cpu3));
1458 #else
1459 (void)OSA_EventWait((osa_event_handle_t)ImuQ23FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1460 #endif
1461
1462 if (Events == 0U)
1463 {
1464 if (gUseRtos_c == 0U)
1465 {
1466 break;
1467 }
1468 else
1469 {
1470 continue;
1471 }
1472 }
1473 #if 0
1474 HAL_ImuGetTaskLock();
1475 #endif
1476 /*! Check for CPU2 to CPU3 IMU links event/ISR has occured
1477 * Only MSG ready events considered
1478 */
1479
1480 (void)HAL_ImuReceive(kIMU_LinkCpu2Cpu3);
1481
1482 if (gUseRtos_c == 0U)
1483 {
1484 break;
1485 }
1486 }
1487 }
1488 #endif
1489
HAL_ImuTaskInit(uint8_t link)1490 static void HAL_ImuTaskInit(uint8_t link)
1491 {
1492 #if defined(CPU2)
1493 (void)link;
1494
1495 if (((imu_init_flag & ((1U << (uint8_t)kIMU_LinkMax) - 1U)) == 0U) && imu_task_flag == 0U)
1496 {
1497 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandle, OSA_TASK(HAL_ImuMain), NULL);
1498 (void)OSA_EventCreate((osa_event_handle_t)ImuQFlagsRef, 1U);
1499 imu_task_flag = 1;
1500 }
1501 #else
1502 if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) == 0)
1503 {
1504 #ifdef __ZEPHYR__
1505 ImuTaskCpu13 = k_thread_create(&ImuTaskHandleCpu13, ImuTaskStackCpu13, K_THREAD_STACK_SIZEOF(ImuTaskStackCpu13),
1506 HAL_ImuMainCpu13, NULL, NULL, NULL, IMU_TASK_PRIORITY, 0, K_NO_WAIT);
1507 k_thread_name_set(ImuTaskCpu13, "HAL_ImuMainCpu13");
1508 #else
1509 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu13, OSA_TASK(HAL_ImuMainCpu13), NULL);
1510 (void)OSA_EventCreate((osa_event_handle_t)ImuQ13FlagsRef, 1U);
1511 #endif
1512 imu_task_flag |= (1U << link);
1513 }
1514 else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) == 0)
1515 {
1516 #ifdef __ZEPHYR__
1517 ImuTaskCpu23 = k_thread_create(&ImuTaskHandleCpu23, ImuTaskStackCpu23, K_THREAD_STACK_SIZEOF(ImuTaskStackCpu23),
1518 HAL_ImuMainCpu23, NULL, NULL, NULL, IMU_TASK_PRIORITY, 0, K_NO_WAIT);
1519 k_thread_name_set(ImuTaskCpu23, "HAL_ImuMainCpu23");
1520 #else
1521 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu23, OSA_TASK(HAL_ImuMainCpu23), NULL);
1522 (void)OSA_EventCreate((osa_event_handle_t)ImuQ23FlagsRef, 1U);
1523 #endif
1524 imu_task_flag |= (1U << link);
1525 }
1526 else
1527 {
1528 ; /* No necessary actions. */
1529 }
1530 #endif
1531 }
1532
HAL_ImuTaskDeinit(uint8_t link)1533 static void HAL_ImuTaskDeinit(uint8_t link)
1534 {
1535 #if defined(CPU2)
1536 (void)link;
1537
1538 if (imu_init_flag == 0U && imu_task_flag != 0U)
1539 {
1540 (void)OSA_EventDestroy((osa_event_handle_t)ImuQFlagsRef);
1541 (void)OSA_TaskDestroy(ImuTaskHandle);
1542 imu_task_flag = 0;
1543 }
1544 #else
1545 if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) != 0)
1546 {
1547 #ifndef __ZEPHYR__
1548 (void)OSA_EventDestroy((osa_event_handle_t)ImuQ13FlagsRef);
1549 (void)OSA_TaskDestroy(ImuTaskHandleCpu13);
1550 imu_task_flag &= ~(1U << link);
1551 #endif
1552 }
1553 else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) != 0)
1554 {
1555 #ifndef __ZEPHYR__
1556 (void)OSA_EventDestroy((osa_event_handle_t)ImuQ23FlagsRef);
1557 (void)OSA_TaskDestroy(ImuTaskHandleCpu23);
1558 imu_task_flag &= ~(1U << link);
1559 #endif
1560 }
1561 else
1562 {
1563 ; /* No necessary actions. */
1564 }
1565 #endif
1566 }
1567
HAL_ImuInit(imu_link_t link)1568 hal_imumc_status_t HAL_ImuInit(imu_link_t link)
1569 {
1570 hal_imu_handle_t *imuHandle;
1571 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1572 uint8_t i;
1573 OSA_SR_ALLOC();
1574
1575 assert(kIMU_LinkMax > link);
1576 imuHandle = &imuHandleCh[link];
1577 imuHandle->imuLink = (uint8_t)link;
1578 OSA_ENTER_CRITICAL();
1579
1580 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
1581 if (0U == imu_init_flag)
1582 {
1583 HAL_InitGdma();
1584 }
1585 #endif
1586
1587 /*! IMU and its interrupt are initialized once for each IMU link */
1588 if ((imu_init_flag & (1U << imuHandle->imuLink)) == 0U)
1589 {
1590 HAL_ImuTaskInit(imuHandle->imuLink);
1591
1592 if (IMU_Init(link) != (int)kStatus_HAL_ImumcSuccess)
1593 {
1594 return kStatus_HAL_ImumcError;
1595 }
1596 IMU_ClearPendingInterrupts(link, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1597 os_ClearPendingISR(IMULINKID_TO_IRQID(link));
1598 /* Interrupt must be maskable by FreeRTOS critical section */
1599 NVIC_SetPriority(IMULINKID_TO_IRQID(link), IMU_ISR_PRIORITY);
1600 (void)os_InterruptMaskSet(IMULINKID_TO_IRQID(link));
1601 #if defined(CPU2)
1602 if (kIMU_LinkCpu2Cpu3 == link)
1603 {
1604 for (i = 0; i < IMUMC_TXQ23_BUFSIZE; i++)
1605 {
1606 (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf23[i]);
1607 }
1608 }
1609 #else
1610 imuHandle->wlanTxqCtl.writeIndex = 0;
1611 imuHandle->wlanTxqCtl.readIndex = 0;
1612 imuHandle->imuMsgBufIdx = 0;
1613 imuHandle->imumcTxqCtl.writeIndex = 0;
1614 imuHandle->imumcTxqCtl.readIndex = 0;
1615 if (kIMU_LinkCpu1Cpu3 == link)
1616 {
1617 for (i = 0; i < IMUMC_TXQ13_BUFSIZE; i++)
1618 {
1619 (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf13[i]);
1620 }
1621 }
1622 else if (kIMU_LinkCpu2Cpu3 == link)
1623 {
1624 for (i = 0; i < IMUMC_TXQ23_BUFSIZE; i++)
1625 {
1626 (void)HAL_ImumcPutTxBuf(imuHandle, (uint8_t *)imumcTxBuf23[i]);
1627 }
1628 }
1629 else
1630 {
1631 ; /* No necessary actions. */
1632 }
1633 #endif
1634 LIST_init(&imuHandle->eptList);
1635 imu_init_flag |= (1U << imuHandle->imuLink);
1636 }
1637
1638 /*! Could be moved out from imumc_init() */
1639 if (imu_init_flag == ((1U << kIMU_LinkMax) - 1U)) /*! All IMU links are initalized */
1640 {
1641 HAL_ImuSetCpuReadyFlag(1U /*! Set CPU1 state */);
1642 }
1643
1644 if ((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState)
1645 {
1646 state = HAL_ImuSendSync(imuHandle);
1647 }
1648
1649 OSA_EXIT_CRITICAL();
1650 (void)state;
1651 return kStatus_HAL_ImumcSuccess;
1652 }
1653
HAL_ImuDeinit(imu_link_t link,uint32_t flag)1654 hal_imumc_status_t HAL_ImuDeinit(imu_link_t link, uint32_t flag)
1655 {
1656 hal_imu_handle_t *imuHandle;
1657 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1658 OSA_SR_ALLOC();
1659
1660 assert(kIMU_LinkMax > link);
1661 imuHandle = &imuHandleCh[link];
1662 OSA_ENTER_CRITICAL();
1663
1664 if ((flag & (1U << 0U)) == 0U)
1665 {
1666 (void)HAL_ImuReturnAllTxBuf(link);
1667 state = HAL_ImuSendShutdown(imuHandle);
1668 if (kStatus_HAL_ImumcError == state)
1669 {
1670 OSA_EXIT_CRITICAL();
1671 return kStatus_HAL_ImumcError;
1672 }
1673 }
1674
1675 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1676 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
1677 (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1678 IMU_Deinit((imu_link_t)imuHandle->imuLink);
1679 imuHandle->imuSyncState = (uint8_t)IMU_UNINITIALIZED;
1680 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
1681 imu_init_flag &= ~(1U << imuHandle->imuLink);
1682 imuHandle->wlanTxqCtl.writeIndex = 0;
1683 imuHandle->wlanTxqCtl.readIndex = 0;
1684 imuHandle->imuMsgBufIdx = 0;
1685 imuHandle->cmd_buffer = NULL;
1686 imuHandle->cmd_buffer_available = 0;
1687 imuHandle->cmd_response_buffer_available = 0;
1688
1689 if ((flag & (1U << 0U)) == 0U)
1690 {
1691 while (*IMU_MSG_PEER_MAGIC_P((imu_link_t)imuHandle->imuLink) != 0)
1692 {
1693 }
1694 }
1695
1696 if ((flag & (1U << 1U)) == 0U)
1697 {
1698 HAL_ImuTaskDeinit(imuHandle->imuLink);
1699 }
1700
1701 OSA_EXIT_CRITICAL();
1702 return kStatus_HAL_ImumcSuccess;
1703 }
1704
HAL_ImumcInit(hal_imumc_handle_t handle,hal_imumc_config_t * config)1705 hal_imumc_status_t HAL_ImumcInit(hal_imumc_handle_t handle, hal_imumc_config_t *config)
1706 {
1707 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1708 hal_imumc_state_t *imumcHandle;
1709 hal_imu_handle_t *imuHandle;
1710 uint32_t Events;
1711 OSA_SR_ALLOC();
1712
1713 assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
1714 assert(NULL != handle);
1715 assert(NULL != config);
1716 assert((uint8_t)kIMU_LinkMax > config->imuLink);
1717 imumcHandle = (hal_imumc_state_t *)handle;
1718
1719 OSA_ENTER_CRITICAL();
1720
1721 if (imumc_init_flag == 0U)
1722 {
1723 #ifdef __ZEPHYR__
1724 k_event_init(&imumcQFlagsRef);
1725 #else
1726 (void)OSA_EventCreate((osa_event_handle_t)imumcQFlagsRef, 1U);
1727 #endif
1728 imumc_init_flag = 1U;
1729 }
1730
1731 state = HAL_ImuInit((imu_link_t)config->imuLink);
1732 if (kStatus_HAL_ImumcError == state)
1733 {
1734 OSA_EXIT_CRITICAL();
1735 return kStatus_HAL_ImumcError;
1736 }
1737
1738 imumcHandle->imuLink = config->imuLink;
1739 imumcHandle->local_addr = config->local_addr;
1740 imumcHandle->remote_addr = config->remote_addr;
1741 imumcHandle->rx.callback = config->callback;
1742 imumcHandle->rx.param = config->param;
1743 imumcHandle->eptLinkIsReady = FALSE;
1744 LIST_elemInit(&imumcHandle->eptLink);
1745
1746 if (NULL == HAL_ImumcCreateEndpoint(imumcHandle))
1747 {
1748 OSA_EXIT_CRITICAL();
1749 return kStatus_HAL_ImumcError;
1750 }
1751
1752 imuHandle = &imuHandleCh[imumcHandle->imuLink];
1753
1754 OSA_EXIT_CRITICAL();
1755
1756 while (kStatus_HAL_ImumcError == HAL_ImuLinkIsUp(imuHandle->imuLink))
1757 {
1758 #if defined(USE_RTOS) && (USE_RTOS == 1)
1759 OSA_TimeDelay(IMU_LINK_WAIT_DELAY_MS);
1760 #else
1761 (void)HAL_ImuReceive(imumcHandle->imuLink);
1762 #endif
1763 }
1764
1765 while (FALSE == imumcHandle->eptLinkIsReady)
1766 {
1767 OSA_ENTER_CRITICAL();
1768
1769 state = HAL_ImuSendImumcEptQuiry(imuHandle, imumcHandle->remote_addr);
1770
1771 OSA_EXIT_CRITICAL();
1772
1773 #if defined(USE_RTOS) && (USE_RTOS == 1U)
1774 #ifdef __ZEPHYR__
1775 Events = k_event_wait(&imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0, K_FOREVER);
1776 k_event_clear(&imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1777 #else
1778 (void)OSA_EventWait((osa_event_handle_t)imumcQFlagsRef, IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0,
1779 osaWaitForever_c, &Events);
1780 #endif
1781 #else
1782 while (TRUE) /* Wait for IMUMC_EVENT_ENDPOINT_QUERY_RSP */
1783 {
1784 (void)HAL_ImuReceive(imumcHandle->imuLink);
1785 (void)OSA_EventWait((osa_event_handle_t)imumcQFlagsRef,
1786 IMUMC_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0, osaWaitForever_c, &Events);
1787 if (Events != 0U)
1788 {
1789 break;
1790 }
1791 }
1792 #endif
1793 }
1794
1795 return state;
1796 }
1797
HAL_ImumcDeinit(hal_imumc_handle_t handle)1798 hal_imumc_status_t HAL_ImumcDeinit(hal_imumc_handle_t handle)
1799 {
1800 hal_imumc_state_t *imumcHandle;
1801 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1802 OSA_SR_ALLOC();
1803
1804 assert(NULL != handle);
1805 imumcHandle = (hal_imumc_state_t *)handle;
1806 OSA_ENTER_CRITICAL();
1807 state = HAL_ImumcDestroyEndpoint(imumcHandle);
1808
1809 OSA_EXIT_CRITICAL();
1810
1811 return state;
1812 }
1813
HAL_ImumcSend(hal_imumc_handle_t handle,uint8_t * data,uint32_t length)1814 hal_imumc_status_t HAL_ImumcSend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length)
1815 {
1816 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1817 hal_imumc_state_t *imumcHandle;
1818 hal_imu_handle_t *imuHandle;
1819 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1820 OSA_SR_ALLOC();
1821 uint8_t *imumc_tx_buf;
1822 struct imumc_std_msg localImumc;
1823
1824 assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
1825 assert(NULL != handle);
1826 assert(NULL != data);
1827
1828 imumcHandle = (hal_imumc_state_t *)handle;
1829 imuHandle = &imuHandleCh[imumcHandle->imuLink];
1830
1831 assert(kStatus_HAL_ImumcSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
1832 assert(imumcHandle->eptLinkIsReady == TRUE);
1833
1834 if (imumcHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
1835 {
1836 assert(IMUMC_TXQ23_BUFLENGTH >= length);
1837 }
1838 else
1839 {
1840 assert(IMUMC_TXQ13_BUFLENGTH >= length);
1841 }
1842
1843 imumc_tx_buf = HAL_ImumcAllocTxBuffer(handle, length);
1844
1845 if (NULL == imumc_tx_buf)
1846 {
1847 return kStatus_HAL_ImumcError;
1848 }
1849 else
1850 {
1851 OSA_ENTER_CRITICAL();
1852
1853 // To be DMAed
1854 (void)HAL_IMU_MEMCPY(imumc_tx_buf, data, length);
1855 localImumc.hdr.src = imumcHandle->local_addr;
1856 localImumc.hdr.dst = imumcHandle->remote_addr;
1857 localImumc.hdr.len = (uint16_t)length;
1858 localImumc.hdr.flags = 0;
1859 localImumc.data = (uint32_t)imumc_tx_buf;
1860
1861 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_IMUMC, 0U,
1862 (uint8_t *)&localImumc,
1863 (3U + sizeof(struct imumc_std_msg)) >> 2U))
1864 {
1865 seq_num++;
1866 }
1867 else
1868 {
1869 (void)HAL_ImumcPutTxBuf(imuHandle, imumc_tx_buf);
1870 imumcStatus = kStatus_HAL_ImumcError;
1871 }
1872
1873 OSA_EXIT_CRITICAL();
1874 }
1875
1876 (void)state;
1877 return imumcStatus;
1878 }
1879
HAL_ImumcNoCopySend(hal_imumc_handle_t handle,uint8_t * data,uint32_t length)1880 hal_imumc_status_t HAL_ImumcNoCopySend(hal_imumc_handle_t handle, uint8_t *data, uint32_t length)
1881 {
1882 hal_imumc_status_t state = kStatus_HAL_ImumcSuccess;
1883 hal_imumc_state_t *imumcHandle;
1884 hal_imu_handle_t *imuHandle;
1885 hal_imumc_status_t imumcStatus = kStatus_HAL_ImumcSuccess;
1886 OSA_SR_ALLOC();
1887
1888 struct imumc_std_msg localImumc;
1889
1890 assert(HAL_IMUMC_HANDLE_SIZE >= sizeof(hal_imumc_state_t));
1891 assert(NULL != handle);
1892 assert(NULL != data);
1893
1894 imumcHandle = (hal_imumc_state_t *)handle;
1895 imuHandle = &imuHandleCh[imumcHandle->imuLink];
1896
1897 assert(kStatus_HAL_ImumcSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
1898 assert(imumcHandle->eptLinkIsReady == TRUE);
1899
1900 OSA_ENTER_CRITICAL();
1901
1902 localImumc.hdr.src = imumcHandle->local_addr;
1903 localImumc.hdr.dst = imumcHandle->remote_addr;
1904 localImumc.hdr.len = (uint16_t)length;
1905 localImumc.hdr.flags = 0;
1906 localImumc.data = (uint32_t)data;
1907
1908 if (kStatus_HAL_ImumcSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_IMUMC, 0U,
1909 (uint8_t *)&localImumc,
1910 (3U + sizeof(struct imumc_std_msg)) >> 2U))
1911 {
1912 seq_num++;
1913 }
1914 else
1915 {
1916 imumcStatus = kStatus_HAL_ImumcError;
1917 }
1918
1919 OSA_EXIT_CRITICAL();
1920 (void)state;
1921 return imumcStatus;
1922 }
1923
HAL_ImuInstallCallback(uint8_t imuLink,imu_callback_t callback,uint8_t type)1924 hal_imumc_status_t HAL_ImuInstallCallback(uint8_t imuLink, imu_callback_t callback, uint8_t type)
1925 {
1926 hal_imu_handle_t *imuHandle;
1927
1928 assert((uint8_t)kIMU_LinkMax > imuLink);
1929 assert((uint8_t)IMU_MSG_MAX > type);
1930 imuHandle = &imuHandleCh[imuLink];
1931 imuHandle->imuHandler[type] = callback;
1932
1933 return kStatus_HAL_ImumcSuccess;
1934 }
1935
HAL_ImuInstallIrqCallback(uint8_t imuLink,imu_irq_callback_t callback)1936 hal_imumc_status_t HAL_ImuInstallIrqCallback(uint8_t imuLink, imu_irq_callback_t callback)
1937 {
1938 assert((uint8_t)kIMU_LinkMax > imuLink);
1939
1940 imuIrqCallback[imuLink] = callback;
1941
1942 return kStatus_HAL_ImumcSuccess;
1943 }
1944
HAL_ImumcInstallRxCallback(hal_imumc_handle_t handle,imumc_rx_callback_t callback,void * param)1945 hal_imumc_status_t HAL_ImumcInstallRxCallback(hal_imumc_handle_t handle, imumc_rx_callback_t callback, void *param)
1946 {
1947 hal_imumc_state_t *imumcHandle;
1948
1949 imumcHandle = (hal_imumc_state_t *)handle;
1950
1951 imumcHandle->rx.callback = callback;
1952 imumcHandle->rx.param = param;
1953
1954 return kStatus_HAL_ImumcSuccess;
1955 }
1956
HAL_ImumcEnterLowpower(hal_imumc_handle_t handle)1957 hal_imumc_status_t HAL_ImumcEnterLowpower(hal_imumc_handle_t handle)
1958 {
1959 return kStatus_HAL_ImumcError;
1960 }
1961
HAL_ImumcExitLowpower(hal_imumc_handle_t handle)1962 hal_imumc_status_t HAL_ImumcExitLowpower(hal_imumc_handle_t handle)
1963 {
1964 return kStatus_HAL_ImumcError;
1965 }
1966
HAL_ImumcSetEvent(uint32_t Event)1967 void HAL_ImumcSetEvent(uint32_t Event)
1968 {
1969 #if defined(CPU2)
1970 (void)OSA_EventSet((osa_event_handle_t)ImuQFlagsRef, Event);
1971 #else
1972 if ((Event & (1U << kIMU_LinkCpu1Cpu3)) != 0U)
1973 {
1974 #ifdef __ZEPHYR__
1975 k_event_post(&ImuQ13FlagsRef, Event);
1976 #else
1977 (void)OSA_EventSet((osa_event_handle_t)ImuQ13FlagsRef, Event);
1978 #endif
1979 }
1980 else
1981 {
1982 #ifdef __ZEPHYR__
1983 k_event_post(&ImuQ23FlagsRef, Event);
1984 #else
1985 (void)OSA_EventSet((osa_event_handle_t)ImuQ23FlagsRef, Event);
1986 #endif
1987 }
1988 #endif
1989 }
1990
1991 #if defined(CPU2)
CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)1992 void CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
1993 {
1994 uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu1Cpu2);
1995
1996 /* Mask IMU ICU interrupt */
1997 (void)os_InterruptMaskClear(irq_num);
1998
1999 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu2))
2000 {
2001 HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu2);
2002 }
2003 else
2004 {
2005 IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu2, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2006 (void)os_InterruptMaskSet(irq_num);
2007 }
2008 }
2009
CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)2010 void CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
2011 {
2012 uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu2Cpu3);
2013
2014 /* Mask IMU ICU interrupt */
2015 (void)os_InterruptMaskClear(irq_num);
2016
2017 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
2018 {
2019 HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
2020 }
2021 else
2022 {
2023 IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2024 (void)os_InterruptMaskSet(irq_num);
2025 }
2026 }
2027 #else
2028
WL_MCI_WAKEUP0_DriverIRQHandler(void)2029 void WL_MCI_WAKEUP0_DriverIRQHandler(void)
2030 {
2031 IRQn_Type irq_num;
2032 #if defined(CPU2)
2033 irq_num = IRQ_IMU_CPU32;
2034 #else
2035 irq_num = IRQ_IMU_CPU13;
2036 #endif
2037
2038 /* Mask IMU ICU interrupt */
2039 (void)os_InterruptMaskClear(irq_num);
2040
2041 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu3))
2042 {
2043 HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu3);
2044 }
2045 else
2046 {
2047 IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2048 (void)os_InterruptMaskSet(irq_num);
2049 }
2050 }
2051
BLE_MCI_WAKEUP0_DriverIRQHandler(void)2052 void BLE_MCI_WAKEUP0_DriverIRQHandler(void)
2053 {
2054 IRQn_Type irq_num;
2055 #if defined(CPU2)
2056 irq_num = IRQ_IMU_CPU12;
2057 #else
2058 irq_num = IRQ_IMU_CPU23;
2059 #endif
2060
2061 /* Mask IMU ICU interrupt */
2062 (void)os_InterruptMaskClear(irq_num);
2063
2064 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
2065 {
2066 HAL_ImumcSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
2067 }
2068 else
2069 {
2070 if (imuIrqCallback[kIMU_LinkCpu2Cpu3] != NULL)
2071 {
2072 imuIrqCallback[kIMU_LinkCpu2Cpu3]();
2073 }
2074
2075 IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2076 (void)os_InterruptMaskSet(irq_num);
2077 }
2078 }
2079 #endif
2080
HAL_ImumcAllocTxBuffer(hal_imumc_handle_t handle,uint32_t size)2081 void *HAL_ImumcAllocTxBuffer(hal_imumc_handle_t handle, uint32_t size)
2082 {
2083 hal_imumc_state_t *imumcHandle;
2084 hal_imu_handle_t *imuHandle;
2085 uint32_t retry = IMUMC_ALLOC_RETRY_COUNT;
2086 void *buf = NULL;
2087
2088 imumcHandle = (hal_imumc_state_t *)handle;
2089
2090 if (imumcHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
2091 {
2092 assert(IMUMC_TXQ23_BUFLENGTH >= size);
2093 }
2094 else
2095 {
2096 assert(IMUMC_TXQ13_BUFLENGTH >= size);
2097 }
2098
2099 assert(NULL != handle);
2100
2101 imuHandle = &imuHandleCh[imumcHandle->imuLink];
2102
2103 buf = HAL_ImumcGetTxBuf(imuHandle);
2104
2105 while ((buf == NULL) && (retry != 0U))
2106 {
2107 /* Sleep current thread, then try to allocate again */
2108 OSA_TimeDelay(IMUMC_ALLOC_FAILED_DELAY_MS);
2109 buf = HAL_ImumcGetTxBuf(imuHandle);
2110 retry--;
2111 }
2112
2113 return buf;
2114 }
2115
HAL_ImumcFreeRxBuffer(hal_imumc_handle_t handle,uint8_t * data)2116 hal_imumc_status_t HAL_ImumcFreeRxBuffer(hal_imumc_handle_t handle, uint8_t *data)
2117 {
2118 hal_imumc_state_t *imumcHandle;
2119 hal_imu_handle_t *imuHandle;
2120
2121 assert(NULL != handle);
2122
2123 imumcHandle = (hal_imumc_state_t *)handle;
2124 imuHandle = &imuHandleCh[imumcHandle->imuLink];
2125
2126 return HAL_ImuSendImumcFreeBuf(imuHandle, data);
2127 }
2128
HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink)2129 bool HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink)
2130 {
2131 hal_imu_handle_t *imuHandle;
2132 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
2133
2134 assert((uint8_t)kIMU_LinkMax > imuLink);
2135
2136 imuHandle = &imuHandleCh[imuLink];
2137 wlanTxqCtl = &imuHandle->wlanTxqCtl;
2138
2139 return (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl));
2140 }
2141
2142 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
HAL_ImuCreateTaskLock(void)2143 hal_imumc_status_t HAL_ImuCreateTaskLock(void)
2144 {
2145 #ifdef __ZEPHYR__
2146 k_mutex_init(&imu_task_lock);
2147 #else
2148 osa_status_t status;
2149
2150 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2151 {
2152 status = OSA_MutexCreate((osa_mutex_handle_t)imu_task_lock);
2153 if (status == KOSA_StatusError)
2154 {
2155 return kStatus_HAL_ImumcError;
2156 }
2157 }
2158 #endif
2159 return kStatus_HAL_ImumcSuccess;
2160 }
2161
HAL_ImuDeleteTaskLock(void)2162 void HAL_ImuDeleteTaskLock(void)
2163 {
2164 #ifndef __ZEPHYR__
2165 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) != 0)
2166 {
2167 (void)OSA_MutexDestroy((osa_mutex_handle_t)imu_task_lock);
2168 (*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) = 0;
2169 }
2170 #endif
2171 }
2172
HAL_ImuGetTaskLock(void)2173 hal_imumc_status_t HAL_ImuGetTaskLock(void)
2174 {
2175 #ifdef __ZEPHYR__
2176 int ret = k_mutex_lock(&imu_task_lock, K_FOREVER);
2177
2178 return (ret == 0) ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
2179 #else
2180 osa_status_t status;
2181
2182 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2183 {
2184 return kStatus_HAL_ImumcSuccess;
2185 }
2186
2187 status = OSA_MutexLock((osa_mutex_handle_t)imu_task_lock, osaWaitForever_c);
2188 return status == KOSA_StatusSuccess ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
2189 #endif
2190 }
2191
HAL_ImuPutTaskLock(void)2192 hal_imumc_status_t HAL_ImuPutTaskLock(void)
2193 {
2194 #ifdef __ZEPHYR__
2195 int ret = k_mutex_unlock(&imu_task_lock);
2196
2197 return (ret == 0) ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
2198 #else
2199
2200 osa_status_t status;
2201
2202 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2203 {
2204 return kStatus_HAL_ImumcSuccess;
2205 }
2206
2207 status = OSA_MutexUnlock((osa_mutex_handle_t)imu_task_lock);
2208 return status == KOSA_StatusSuccess ? kStatus_HAL_ImumcSuccess : kStatus_HAL_ImumcError;
2209 #endif
2210 }
2211 #endif
2212
