1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_SDRAM_H_ 10 #define _FSL_SDRAM_H_ 11 12 #include "fsl_sdramc.h" 13 14 /*! 15 * @addtogroup sdram_mt48lc4m16 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 23 /*! @brief SDRAM driver version. */ 24 #define FSL_SDRAM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ 25 /*! @brief Define the access value of the SDRAM location. */ 26 #define SDRAM_COMMAND_ACCESSVALUE 0xaaU 27 28 /*! @brief Define the right address line for the mrs register setting. */ 29 #define ADDR9 9U 30 #define ADDR10 10U 31 #define ADDR11 11U 32 #define ADDR12 12U 33 #define ADDR13 13U 34 #define ADDR14 14U 35 #define ADDR15 15U 36 #define ADDR16 16U 37 #define ADDR17 17U 38 #define ADDR18 18U 39 #define ADDR19 19U 40 #define ADDR20 20U 41 #define ADDR21 21U 42 #define ADDR22 22U 43 #define ADDR23 23U 44 45 /*! @brief Define the physical connection--16bit port 8 column. */ 46 #define SDRAM_A0 ADDR16 47 #define SDRAM_A1 ADDR15 48 #define SDRAM_A2 ADDR14 49 #define SDRAM_A3 ADDR13 50 #define SDRAM_A4 ADDR12 51 #define SDRAM_A5 ADDR11 52 #define SDRAM_A6 ADDR10 53 #define SDRAM_A7 ADDR9 54 #define SDRAM_A8 ADDR17 55 #define SDRAM_A9 ADDR18 56 #define SDRAM_A10 ADDR19 57 #define SDRAM_A11 ADDR20 58 #define SDRAM_A12 ADDR21 59 #define SDRAM_A13 ADDR22 60 #define SDRAM_A14 ADDR23 61 62 #define BURSTLENGTH 0U 63 #define BURSTTYPE 0U 64 #define CASLATENCY 2U 65 #define OPMODE 0U 66 #define WRITEBURSTMODE 0U 67 68 /*! @brief SDRAM Mode register write burst mode setting. */ 69 typedef enum _sdram_write_burst_mode 70 { 71 kSDRAM_MrsWriteBurst = 0x0U, /*!< Write burst mode. */ 72 kSDRAM_MrsWriteSingle /*!< Write single location mode. */ 73 } sdram_write_burst_mode_t; 74 75 /*! @brief SDRAM Mode register operation mode setting. */ 76 typedef enum _sdram_operation_mode 77 { 78 kSDRAM_MrsStandOperation = 0x0U, /*!< Standard operation mode. */ 79 kSDRAM_MrsAllOtherReserve /*!< All other states reserved. */ 80 } sdram_operation_mode_t; 81 82 /*! @brief SDRAM Mode register CAS latency setting. */ 83 typedef enum _sdram_cas_latency 84 { 85 kSDRAM_MrsLatencyOne = 0x1U, /*!< Latency one. */ 86 kSDRAM_MrsLatencyTwo, /*!< Latency two. */ 87 kSDRAM_MrsLatencyThree /*!< Latency three. */ 88 } sdram_cas_latency_t; 89 90 /*! @brief SDRAM Mode register burst type setting. */ 91 typedef enum _sdram_burst_type 92 { 93 kSDRAM_MrsSequential = 0x0U, /*!< Sequential. */ 94 kSDRAM_MrsInterleaved, /*!< Interleaved. */ 95 } sdram_burst_type_t; 96 97 /*! @brief SDRAM Mode register burst length setting. */ 98 typedef enum _sdram_burst_len 99 { 100 kSDRAM_MrsBurstLenOne = 0x0U, /*!< 1. */ 101 kSDRAM_MrsBurstLenTwo = 0x1U, /*!< 2. */ 102 kSDRAM_MrsBurstLenFour = 0x2U, /*!< 4. */ 103 kSDRAM_MrsBurstLenEight = 0x3U, /*!< 8. */ 104 kSDRAM_MrsBurstLenAllPage = 0x7U /*!< Full page only for sequential burst type. */ 105 } sdram_burst_len_t; 106 /******************************************************************************* 107 * API 108 ******************************************************************************/ 109 110 #if defined(__cplusplus) 111 extern "C" { 112 #endif 113 114 /*! 115 * @brief Initializes the SDRAM device. 116 * The function is used to initialize the MT48LC4M16A2 SDRAM external memory. 117 * @param base SDRAM controller peripheral base address. 118 * @param address The address of the sdram. 119 * @param busClock_Hz The bus clock frequency for SDRAM controller. 120 * @return the execution result. 121 * 122 */ 123 status_t SDRAM_Init(SDRAM_Type *base, uint32_t address, uint32_t busClock_Hz); 124 125 #if defined(__cplusplus) 126 } 127 #endif 128 129 /*! @} */ 130 131 #endif /*_FSL_SDRAM_H_*/ 132
