1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2017,2020,2021,2024 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_lpuart_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.lpuart_cmsis"
26 #endif
27
28 /* Re-mapping for LPUART & UART indexing. */
29 #if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && FSL_FEATURE_SOC_UART_COUNT
30
31 #ifdef RTE_USART0
32 #undef RTE_USART0
33 #endif
34 #ifdef RTE_USART0_DMA_EN
35 #undef RTE_USART0_DMA_EN
36 #endif
37 #ifdef RTE_USART0_DMA_TX_CH
38 #undef RTE_USART0_DMA_TX_CH
39 #endif
40 #ifdef RTE_USART0_DMA_TX_PERI_SEL
41 #undef RTE_USART0_DMA_TX_PERI_SEL
42 #endif
43 #ifdef RTE_USART0_DMA_TX_DMAMUX_BASE
44 #undef RTE_USART0_DMA_TX_DMAMUX_BASE
45 #endif
46 #ifdef RTE_USART0_DMA_TX_DMA_BASE
47 #undef RTE_USART0_DMA_TX_DMA_BASE
48 #endif
49 #ifdef RTE_USART0_DMA_RX_CH
50 #undef RTE_USART0_DMA_RX_CH
51 #endif
52 #ifdef RTE_USART0_DMA_RX_PERI_SEL
53 #undef RTE_USART0_DMA_RX_PERI_SEL
54 #endif
55 #ifdef RTE_USART0_DMA_RX_DMAMUX_BASE
56 #undef RTE_USART0_DMA_RX_DMAMUX_BASE
57 #endif
58 #ifdef RTE_USART0_DMA_RX_DMA_BASE
59 #undef RTE_USART0_DMA_RX_DMA_BASE
60 #endif
61 #ifdef USART0_RX_BUFFER_ENABLE
62 #undef USART0_RX_BUFFER_ENABLE
63 #endif
64
65 #if (FSL_FEATURE_SOC_UART_COUNT == 3)
66
67 #ifdef RTE_USART3
68 #define RTE_USART0 RTE_USART3
69 #endif
70 #ifdef RTE_USART3_DMA_EN
71 #define RTE_USART0_DMA_EN RTE_USART3_DMA_EN
72 #endif
73 #ifdef RTE_USART3_DMA_TX_CH
74 #define RTE_USART0_DMA_TX_CH RTE_USART3_DMA_TX_CH
75 #endif
76 #ifdef RTE_USART3_DMA_TX_PERI_SEL
77 #define RTE_USART0_DMA_TX_PERI_SEL RTE_USART3_DMA_TX_PERI_SEL
78 #endif
79 #ifdef RTE_USART3_DMA_TX_DMAMUX_BASE
80 #define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART3_DMA_TX_DMAMUX_BASE
81 #endif
82 #ifdef RTE_USART3_DMA_TX_DMA_BASE
83 #define RTE_USART0_DMA_TX_DMA_BASE RTE_USART3_DMA_TX_DMA_BASE
84 #endif
85 #ifdef RTE_USART3_DMA_RX_CH
86 #define RTE_USART0_DMA_RX_CH RTE_USART3_DMA_RX_CH
87 #endif
88 #ifdef RTE_USART3_DMA_RX_PERI_SEL
89 #define RTE_USART0_DMA_RX_PERI_SEL RTE_USART3_DMA_RX_PERI_SEL
90 #endif
91 #ifdef RTE_USART3_DMA_RX_DMAMUX_BASE
92 #define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART3_DMA_RX_DMAMUX_BASE
93 #endif
94 #ifdef RTE_USART3_DMA_RX_DMA_BASE
95 #define RTE_USART0_DMA_RX_DMA_BASE RTE_USART3_DMA_RX_DMA_BASE
96 #endif
97 #ifdef USART3_RX_BUFFER_ENABLE
98 #define USART0_RX_BUFFER_ENABLE USART3_RX_BUFFER_ENABLE
99 #endif
100 #ifdef RTE_USART3_PIN_INIT
101 #define RTE_USART0_PIN_INIT RTE_USART3_PIN_INIT
102 #endif
103 #ifdef RTE_USART3_PIN_DEINIT
104 #define RTE_USART0_PIN_DEINIT RTE_USART3_PIN_DEINIT
105 #endif
106
107 #endif /* FSL_FEATURE_SOC_UART_COUNT == 3 */
108
109 #if (FSL_FEATURE_SOC_UART_COUNT == 4)
110
111 #ifdef RTE_USART4
112 #define RTE_USART0 RTE_USART4
113 #endif
114 #ifdef RTE_USART4_DMA_EN
115 #define RTE_USART0_DMA_EN RTE_USART4_DMA_EN
116 #endif
117 #ifdef RTE_USART4_DMA_TX_CH
118 #define RTE_USART0_DMA_TX_CH RTE_USART4_DMA_TX_CH
119 #endif
120 #ifdef RTE_USART4_DMA_TX_PERI_SEL
121 #define RTE_USART0_DMA_TX_PERI_SEL RTE_USART4_DMA_TX_PERI_SEL
122 #endif
123 #ifdef RTE_USART4_DMA_TX_DMAMUX_BASE
124 #define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART4_DMA_TX_DMAMUX_BASE
125 #endif
126 #ifdef RTE_USART4_DMA_TX_DMA_BASE
127 #define RTE_USART0_DMA_TX_DMA_BASE RTE_USART4_DMA_TX_DMA_BASE
128 #endif
129 #ifdef RTE_USART4_DMA_RX_CH
130 #define RTE_USART0_DMA_RX_CH RTE_USART4_DMA_RX_CH
131 #endif
132 #ifdef RTE_USART4_DMA_RX_PERI_SEL
133 #define RTE_USART0_DMA_RX_PERI_SEL RTE_USART4_DMA_RX_PERI_SEL
134 #endif
135 #ifdef RTE_USART4_DMA_RX_DMAMUX_BASE
136 #define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART4_DMA_RX_DMAMUX_BASE
137 #endif
138 #ifdef RTE_USART4_DMA_RX_DMA_BASE
139 #define RTE_USART0_DMA_RX_DMA_BASE RTE_USART4_DMA_RX_DMA_BASE
140 #endif
141 #ifdef USART4_RX_BUFFER_ENABLE
142 #define USART0_RX_BUFFER_ENABLE USART4_RX_BUFFER_ENABLE
143 #endif
144 #ifdef RTE_USART4_PIN_INIT
145 #define RTE_USART0_PIN_INIT RTE_USART4_PIN_INIT
146 #endif
147 #ifdef RTE_USART4_PIN_DEINIT
148 #define RTE_USART0_PIN_DEINIT RTE_USART4_PIN_DEINIT
149 #endif
150
151 #endif /* FSL_FEATURE_SOC_UART_COUNT == 4 */
152
153 #if (FSL_FEATURE_SOC_UART_COUNT == 5)
154
155 #ifdef RTE_USART5
156 #define RTE_USART0 RTE_USART5
157 #endif
158 #ifdef RTE_USART5_DMA_EN
159 #define RTE_USART0_DMA_EN RTE_USART5_DMA_EN
160 #endif
161 #ifdef RTE_USART5_DMA_TX_CH
162 #define RTE_USART0_DMA_TX_CH RTE_USART5_DMA_TX_CH
163 #endif
164 #ifdef RTE_USART5_DMA_TX_PERI_SEL
165 #define RTE_USART0_DMA_TX_PERI_SEL RTE_USART5_DMA_TX_PERI_SEL
166 #endif
167 #ifdef RTE_USART5_DMA_TX_DMAMUX_BASE
168 #define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART5_DMA_TX_DMAMUX_BASE
169 #endif
170 #ifdef RTE_USART5_DMA_TX_DMA_BASE
171 #define RTE_USART0_DMA_TX_DMA_BASE RTE_USART5_DMA_TX_DMA_BASE
172 #endif
173 #ifdef RTE_USART5_DMA_RX_CH
174 #define RTE_USART0_DMA_RX_CH RTE_USART5_DMA_RX_CH
175 #endif
176 #ifdef RTE_USART5_DMA_RX_PERI_SEL
177 #define RTE_USART0_DMA_RX_PERI_SEL RTE_USART5_DMA_RX_PERI_SEL
178 #endif
179 #ifdef RTE_USART5_DMA_RX_DMAMUX_BASE
180 #define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART5_DMA_RX_DMAMUX_BASE
181 #endif
182 #ifdef RTE_USART5_DMA_RX_DMA_BASE
183 #define RTE_USART0_DMA_RX_DMA_BASE RTE_USART5_DMA_RX_DMA_BASE
184 #endif
185 #ifdef USART5_RX_BUFFER_ENABLE
186 #define USART0_RX_BUFFER_ENABLE USART5_RX_BUFFER_ENABLE
187 #endif
188 #ifdef RTE_USART5_PIN_INIT
189 #define RTE_USART0_PIN_INIT RTE_USART5_PIN_INIT
190 #endif
191 #ifdef RTE_USART5_PIN_DEINIT
192 #define RTE_USART0_PIN_DEINIT RTE_USART5_PIN_DEINIT
193 #endif
194
195 #endif /* FSL_FEATURE_SOC_UART_COUNT == 3 */
196
197 #endif /* (FSL_FEATURE_SOC_LPUART_COUNT == 1) && FSL_FEATURE_SOC_UART_COUNT */
198
199 #if ((defined(RTE_USART0) && RTE_USART0 && defined(LPUART0)) || \
200 (defined(RTE_USART1) && RTE_USART1 && defined(LPUART1)) || \
201 (defined(RTE_USART2) && RTE_USART2 && defined(LPUART2)) || \
202 (defined(RTE_USART3) && RTE_USART3 && defined(LPUART3)) || \
203 (defined(RTE_USART4) && RTE_USART4 && defined(LPUART4)) || \
204 (defined(RTE_USART5) && RTE_USART5 && defined(LPUART5)) || \
205 (defined(RTE_USART6) && RTE_USART6 && defined(LPUART6)) || \
206 (defined(RTE_USART7) && RTE_USART7 && defined(LPUART7)) || \
207 (defined(RTE_USART8) && RTE_USART8 && defined(LPUART8)) || \
208 (defined(RTE_USART9) && RTE_USART9 && defined(LPUART9)) || \
209 (defined(RTE_USART10) && RTE_USART10 && defined(LPUART10)) || \
210 (defined(RTE_USART11) && RTE_USART11 && defined(LPUART11)) || \
211 (defined(RTE_USART12) && RTE_USART12 && defined(LPUART12)) || \
212 (defined(RTE_USART13) && RTE_USART13 && defined(LPUART13)) || \
213 (defined(RTE_USART14) && RTE_USART14 && defined(LPUART14)) || \
214 (defined(RTE_USART15) && RTE_USART15 && defined(LPUART15)) || \
215 (defined(RTE_USART16) && RTE_USART16 && defined(LPUART16)) || \
216 (defined(RTE_USART17) && RTE_USART17 && defined(LPUART17)) || \
217 (defined(RTE_USART18) && RTE_USART18 && defined(LPUART18)) || \
218 (defined(RTE_USART19) && RTE_USART19 && defined(LPUART19)) || \
219 (defined(RTE_USART20) && RTE_USART10 && defined(LPUART20)))
220
221 #define ARM_LPUART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (6))
222
223 /*
224 * ARMCC does not support split the data section automatically, so the driver
225 * needs to split the data to separate sections explicitly, to reduce codesize.
226 */
227 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
228 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
229 #endif
230
231 typedef const struct _cmsis_lpuart_resource
232 {
233 LPUART_Type *base; /*!< LPUART peripheral base address. */
234 uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
235 } cmsis_lpuart_resource_t;
236
237 typedef struct _cmsis_lpuart_non_blocking_driver_state
238 {
239 cmsis_lpuart_resource_t *resource; /*!< Basic LPUART resource. */
240 lpuart_handle_t *handle; /*!< Interupt transfer handle. */
241 ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
242 uint8_t flags; /*!< Control and state flags. */
243 } cmsis_lpuart_non_blocking_driver_state_t;
244
245 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
246 typedef struct _cmsis_lpuart_dma_resource
247 {
248 DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */
249 uint32_t txDmaChannel; /*!< DMA channel for LPUART TX. */
250 uint8_t txDmaRequest; /*!< TX DMA request source. */
251
252 DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */
253 uint32_t rxDmaChannel; /*!< DMA channel for LPUART RX. */
254 uint8_t rxDmaRequest; /*!< RX DMA request source. */
255
256 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
257 DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */
258 DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */
259 #endif
260
261 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
262 uint32_t txDmamuxChannel; /*!< DMAMUX channel for LPUART TX. */
263 uint32_t rxDmamuxChannel; /*!< DMAMUX channel for LPUART TX. */
264 #endif
265 } cmsis_lpuart_dma_resource_t;
266
267 typedef struct _cmsis_lpuart_dma_driver_state
268 {
269 cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */
270 cmsis_lpuart_dma_resource_t *dmaResource; /*!< LPUART DMA resource. */
271 lpuart_dma_handle_t *handle; /*!< LPUART DMA transfer handle. */
272 dma_handle_t *rxHandle; /*!< DMA RX handle. */
273 dma_handle_t *txHandle; /*!< DMA TX handle. */
274 ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
275 uint8_t flags; /*!< Control and state flags. */
276 } cmsis_lpuart_dma_driver_state_t;
277 #endif
278
279 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
280 typedef struct _cmsis_lpuart_edma_resource
281 {
282 void *txEdmaBase; /*!< EDMA peripheral base address for TX. */
283 uint32_t txEdmaChannel; /*!< EDMA channel for LPUART TX. */
284 uint32_t txDmaRequest; /*!< TX EDMA request source. */
285
286 void *rxEdmaBase; /*!< EDMA peripheral base address for RX. */
287 uint32_t rxEdmaChannel; /*!< EDMA channel for LPUART RX. */
288 uint32_t rxDmaRequest; /*!< RX EDMA request source. */
289
290 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
291 DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */
292 DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */
293 #endif
294 } cmsis_lpuart_edma_resource_t;
295
296 typedef struct _cmsis_lpuart_edma_driver_state
297 {
298 cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */
299 cmsis_lpuart_edma_resource_t *dmaResource; /*!< LPUART EDMA resource. */
300 lpuart_edma_handle_t *handle; /*!< LPUART EDMA transfer handle. */
301 edma_handle_t *rxHandle; /*!< EDMA RX handle. */
302 edma_handle_t *txHandle; /*!< EDMA TX handle. */
303 ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
304 uint8_t flags; /*!< Control and state flags. */
305 } cmsis_lpuart_edma_driver_state_t;
306 #endif
307
308 enum _lpuart_transfer_states
309 {
310 kLPUART_TxIdle, /*!< TX idle. */
311 kLPUART_TxBusy, /*!< TX busy. */
312 kLPUART_RxIdle, /*!< RX idle. */
313 kLPUART_RxBusy /*!< RX busy. */
314 };
315
316 /* Driver Version */
317 static const ARM_DRIVER_VERSION s_lpuartDriverVersion = {ARM_USART_API_VERSION, ARM_LPUART_DRV_VERSION};
318
319 static const ARM_USART_CAPABILITIES s_lpuartDriverCapabilities = {
320 1, /* supports LPUART (Asynchronous) mode */
321 0, /* supports Synchronous Master mode */
322 0, /* supports Synchronous Slave mode */
323 0, /* supports LPUART Single-wire mode */
324 0, /* supports LPUART IrDA mode */
325 0, /* supports LPUART Smart Card mode */
326 0, /* Smart Card Clock generator */
327 0, /* RTS Flow Control available */
328 0, /* CTS Flow Control available */
329 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
330 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
331 0, /* RTS Line: 0=not available, 1=available */
332 0, /* CTS Line: 0=not available, 1=available */
333 0, /* DTR Line: 0=not available, 1=available */
334 0, /* DSR Line: 0=not available, 1=available */
335 0, /* DCD Line: 0=not available, 1=available */
336 0, /* RI Line: 0=not available, 1=available */
337 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
338 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
339 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
340 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */
341 };
342
343 /*
344 * Common control function used by LPUART_NonBlockingControl/LPUART_DmaControl/LPUART_EdmaControl
345 */
LPUART_CommonControl(uint32_t control,uint32_t arg,cmsis_lpuart_resource_t * resource,uint8_t * isConfigured)346 static int32_t LPUART_CommonControl(uint32_t control,
347 uint32_t arg,
348 cmsis_lpuart_resource_t *resource,
349 uint8_t *isConfigured)
350 {
351 lpuart_config_t config;
352 int32_t result = ARM_DRIVER_OK;
353 bool isContinue = false;
354
355 LPUART_GetDefaultConfig(&config);
356
357 switch (control & ARM_USART_CONTROL_Msk)
358 {
359 case ARM_USART_MODE_ASYNCHRONOUS:
360 /* USART Baudrate */
361 config.baudRate_Bps = arg;
362 isContinue = true;
363 break;
364
365 /* TX/RX IO is controlled in application layer. */
366 case ARM_USART_CONTROL_TX:
367 if (arg != 0U)
368 {
369 LPUART_EnableTx(resource->base, true);
370 }
371 else
372 {
373 LPUART_EnableTx(resource->base, false);
374 }
375 result = ARM_DRIVER_OK;
376 break;
377
378 case ARM_USART_CONTROL_RX:
379 if (arg != 0U)
380 {
381 LPUART_EnableRx(resource->base, true);
382 }
383 else
384 {
385 LPUART_EnableRx(resource->base, false);
386 }
387
388 result = ARM_DRIVER_OK;
389 break;
390
391 default:
392 result = ARM_DRIVER_ERROR_UNSUPPORTED;
393 break;
394 }
395
396 if (!isContinue)
397 {
398 return result;
399 }
400
401 switch (control & ARM_USART_DATA_BITS_Msk)
402 {
403 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
404 case ARM_USART_DATA_BITS_7:
405 config.dataBitsCount = kLPUART_SevenDataBits;
406 break;
407 #endif
408 case ARM_USART_DATA_BITS_8:
409 config.dataBitsCount = kLPUART_EightDataBits;
410 break;
411
412 default:
413 result = ARM_USART_ERROR_DATA_BITS;
414 break;
415 }
416
417 if (result == ARM_USART_ERROR_DATA_BITS)
418 {
419 return result;
420 }
421
422 switch (control & ARM_USART_PARITY_Msk)
423 {
424 case ARM_USART_PARITY_NONE:
425 config.parityMode = kLPUART_ParityDisabled;
426 break;
427 case ARM_USART_PARITY_EVEN:
428 config.parityMode = kLPUART_ParityEven;
429 break;
430 case ARM_USART_PARITY_ODD:
431 config.parityMode = kLPUART_ParityOdd;
432 break;
433 default:
434 result = ARM_USART_ERROR_PARITY;
435 break;
436 }
437
438 if (result == ARM_USART_ERROR_PARITY)
439 {
440 return result;
441 }
442
443 switch (control & ARM_USART_STOP_BITS_Msk)
444 {
445 case ARM_USART_STOP_BITS_1:
446 /* The GetDefaultConfig has already set for this case. */
447 break;
448 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
449 case ARM_USART_STOP_BITS_2:
450 config.stopBitCount = kLPUART_TwoStopBit;
451 break;
452 #endif
453 default:
454 result = ARM_USART_ERROR_STOP_BITS;
455 break;
456 }
457
458 if (result == ARM_USART_ERROR_STOP_BITS)
459 {
460 return result;
461 }
462
463 /* If LPUART is already configured, deinit it first. */
464 if (((*isConfigured) & (uint8_t)USART_FLAG_CONFIGURED) != 0U)
465 {
466 LPUART_Deinit(resource->base);
467 *isConfigured &= ~(uint8_t)USART_FLAG_CONFIGURED;
468 }
469
470 config.enableTx = true;
471 config.enableRx = true;
472
473 if (kStatus_LPUART_BaudrateNotSupport == LPUART_Init(resource->base, &config, resource->GetFreq()))
474 {
475 result = ARM_USART_ERROR_BAUDRATE;
476 }
477 else
478 {
479 *isConfigured |= (uint8_t)USART_FLAG_CONFIGURED;
480 }
481
482 return result;
483 }
484
LPUARTx_GetVersion(void)485 static ARM_DRIVER_VERSION LPUARTx_GetVersion(void)
486 {
487 return s_lpuartDriverVersion;
488 }
489
LPUARTx_GetCapabilities(void)490 static ARM_USART_CAPABILITIES LPUARTx_GetCapabilities(void)
491 {
492 return s_lpuartDriverCapabilities;
493 }
494
LPUARTx_SetModemControl(ARM_USART_MODEM_CONTROL control)495 static int32_t LPUARTx_SetModemControl(ARM_USART_MODEM_CONTROL control)
496 {
497 return ARM_DRIVER_ERROR_UNSUPPORTED;
498 }
499
LPUARTx_GetModemStatus(void)500 static ARM_USART_MODEM_STATUS LPUARTx_GetModemStatus(void)
501 {
502 ARM_USART_MODEM_STATUS modem_status = {0};
503
504 return modem_status;
505 }
506
507 #endif
508
509 #if ((defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN && defined(LPUART0)) || \
510 (defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN && defined(LPUART1)) || \
511 (defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN && defined(LPUART2)) || \
512 (defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN && defined(LPUART3)) || \
513 (defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN && defined(LPUART4)) || \
514 (defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN && defined(LPUART5)) || \
515 (defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN && defined(LPUART6)) || \
516 (defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN && defined(LPUART7)) || \
517 (defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN && defined(LPUART8)) || \
518 (defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN && defined(LPUART9)) || \
519 (defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN && defined(LPUART10)) || \
520 (defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN && defined(LPUART11)) || \
521 (defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN && defined(LPUART12)) || \
522 (defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN && defined(LPUART13)) || \
523 (defined(RTE_USART14_DMA_EN) && RTE_USART14_DMA_EN && defined(LPUART14)) || \
524 (defined(RTE_USART15_DMA_EN) && RTE_USART15_DMA_EN && defined(LPUART15)) || \
525 (defined(RTE_USART16_DMA_EN) && RTE_USART16_DMA_EN && defined(LPUART16)) || \
526 (defined(RTE_USART17_DMA_EN) && RTE_USART17_DMA_EN && defined(LPUART17)) || \
527 (defined(RTE_USART18_DMA_EN) && RTE_USART18_DMA_EN && defined(LPUART18)) || \
528 (defined(RTE_USART19_DMA_EN) && RTE_USART19_DMA_EN && defined(LPUART19)) || \
529 (defined(RTE_USART20_DMA_EN) && RTE_USART20_DMA_EN && defined(LPUART20)))
530
531 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
KSDK_LPUART_DmaCallback(LPUART_Type * base,lpuart_dma_handle_t * handle,status_t status,void * userData)532 static void KSDK_LPUART_DmaCallback(LPUART_Type *base, lpuart_dma_handle_t *handle, status_t status, void *userData)
533 {
534 uint32_t event = 0U;
535
536 if (kStatus_LPUART_TxIdle == status)
537 {
538 event = ARM_USART_EVENT_SEND_COMPLETE;
539 }
540 else if (kStatus_LPUART_RxIdle == status)
541 {
542 event = ARM_USART_EVENT_RECEIVE_COMPLETE;
543 }
544 else
545 {
546 /* Avoid MISRA 2012 15.7 violation */
547 }
548
549 /* User data is actually CMSIS driver callback. */
550 if ((0U != event) && (userData != NULL))
551 {
552 ((ARM_USART_SignalEvent_t)userData)(event);
553 }
554 }
555
LPUART_DmaInitialize(ARM_USART_SignalEvent_t cb_event,cmsis_lpuart_dma_driver_state_t * lpuart)556 static int32_t LPUART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_dma_driver_state_t *lpuart)
557 {
558 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_INIT))
559 {
560 lpuart->cb_event = cb_event;
561 lpuart->flags = (uint8_t)USART_FLAG_INIT;
562 }
563
564 return ARM_DRIVER_OK;
565 }
566
LPUART_DmaUninitialize(cmsis_lpuart_dma_driver_state_t * lpuart)567 static int32_t LPUART_DmaUninitialize(cmsis_lpuart_dma_driver_state_t *lpuart)
568 {
569 lpuart->flags = (uint8_t)USART_FLAG_UNINIT;
570 return ARM_DRIVER_OK;
571 }
572
LPUART_DmaPowerControl(ARM_POWER_STATE state,cmsis_lpuart_dma_driver_state_t * lpuart)573 static int32_t LPUART_DmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_dma_driver_state_t *lpuart)
574 {
575 lpuart_config_t config;
576 cmsis_lpuart_dma_resource_t *dmaResource;
577 int32_t result = ARM_DRIVER_OK;
578
579 switch (state)
580 {
581 case ARM_POWER_OFF:
582 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
583 {
584 LPUART_Deinit(lpuart->resource->base);
585 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
586 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
587 DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxDmamuxChannel);
588 DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txDmamuxChannel);
589 #else
590 DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxDmaChannel);
591 DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txDmaChannel);
592 #endif
593 #endif
594 lpuart->flags = (uint8_t)USART_FLAG_INIT;
595 }
596 break;
597 case ARM_POWER_LOW:
598 result = ARM_DRIVER_ERROR_UNSUPPORTED;
599 break;
600 case ARM_POWER_FULL:
601 /* Must be initialized first. */
602 if (lpuart->flags == (uint8_t)USART_FLAG_UNINIT)
603 {
604 result = ARM_DRIVER_ERROR;
605 break;
606 }
607
608 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
609 {
610 /* Driver already powered */
611 break;
612 }
613
614 LPUART_GetDefaultConfig(&config);
615 config.enableTx = true;
616 config.enableRx = true;
617
618 dmaResource = lpuart->dmaResource;
619
620 /* Set up DMA setting. */
621 DMA_CreateHandle(lpuart->rxHandle, dmaResource->rxDmaBase, dmaResource->rxDmaChannel);
622
623 DMA_CreateHandle(lpuart->txHandle, dmaResource->txDmaBase, dmaResource->txDmaChannel);
624 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
625 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
626 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxDmamuxChannel,
627 (int32_t)dmaResource->rxDmaRequest);
628 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxDmamuxChannel);
629
630 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txDmamuxChannel,
631 (int32_t)dmaResource->txDmaRequest);
632 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txDmamuxChannel);
633 #else
634 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel, (int32_t)dmaResource->rxDmaRequest);
635 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel);
636
637 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txDmaChannel, (int32_t)dmaResource->txDmaRequest);
638 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txDmaChannel);
639 #endif
640 #endif
641
642 /* Setup the LPUART. */
643 (void)LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq());
644 LPUART_TransferCreateHandleDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_DmaCallback,
645 (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle);
646
647 lpuart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED);
648 break;
649 default:
650 result = ARM_DRIVER_ERROR_UNSUPPORTED;
651 break;
652 }
653
654 return result;
655 }
656
LPUART_DmaSend(const void * data,uint32_t num,cmsis_lpuart_dma_driver_state_t * lpuart)657 static int32_t LPUART_DmaSend(const void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart)
658 {
659 int32_t ret;
660 status_t status;
661 lpuart_transfer_t xfer;
662
663 xfer.data = (uint8_t *)data;
664 xfer.dataSize = num;
665
666 status = LPUART_TransferSendDMA(lpuart->resource->base, lpuart->handle, &xfer);
667
668 switch (status)
669 {
670 case kStatus_Success:
671 ret = ARM_DRIVER_OK;
672 break;
673 case kStatus_InvalidArgument:
674 ret = ARM_DRIVER_ERROR_PARAMETER;
675 break;
676 case kStatus_LPUART_RxBusy:
677 ret = ARM_DRIVER_ERROR_BUSY;
678 break;
679 default:
680 ret = ARM_DRIVER_ERROR;
681 break;
682 }
683
684 return ret;
685 }
686
LPUART_DmaReceive(void * data,uint32_t num,cmsis_lpuart_dma_driver_state_t * lpuart)687 static int32_t LPUART_DmaReceive(void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart)
688 {
689 int32_t ret;
690 status_t status;
691 lpuart_transfer_t xfer;
692
693 xfer.data = (uint8_t *)data;
694 xfer.dataSize = num;
695
696 status = LPUART_TransferReceiveDMA(lpuart->resource->base, lpuart->handle, &xfer);
697
698 switch (status)
699 {
700 case kStatus_Success:
701 ret = ARM_DRIVER_OK;
702 break;
703 case kStatus_InvalidArgument:
704 ret = ARM_DRIVER_ERROR_PARAMETER;
705 break;
706 case kStatus_LPUART_TxBusy:
707 ret = ARM_DRIVER_ERROR_BUSY;
708 break;
709 default:
710 ret = ARM_DRIVER_ERROR;
711 break;
712 }
713
714 return ret;
715 }
716
LPUART_DmaTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_lpuart_dma_driver_state_t * lpuart)717 static int32_t LPUART_DmaTransfer(const void *data_out,
718 void *data_in,
719 uint32_t num,
720 cmsis_lpuart_dma_driver_state_t *lpuart)
721 {
722 /* Only in synchronous mode */
723 return ARM_DRIVER_ERROR;
724 }
725
LPUART_DmaGetTxCount(cmsis_lpuart_dma_driver_state_t * lpuart)726 static uint32_t LPUART_DmaGetTxCount(cmsis_lpuart_dma_driver_state_t *lpuart)
727 {
728 uint32_t cnt;
729
730 /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
731 if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountDMA(lpuart->resource->base, lpuart->handle, &cnt))
732 {
733 cnt = lpuart->handle->txDataSizeAll;
734 }
735
736 return cnt;
737 }
738
LPUART_DmaGetRxCount(cmsis_lpuart_dma_driver_state_t * lpuart)739 static uint32_t LPUART_DmaGetRxCount(cmsis_lpuart_dma_driver_state_t *lpuart)
740 {
741 uint32_t cnt;
742
743 if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCountDMA(lpuart->resource->base, lpuart->handle, &cnt))
744 {
745 cnt = lpuart->handle->rxDataSizeAll;
746 }
747
748 return cnt;
749 }
750
LPUART_DmaControl(uint32_t control,uint32_t arg,cmsis_lpuart_dma_driver_state_t * lpuart)751 static int32_t LPUART_DmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_dma_driver_state_t *lpuart)
752 {
753 int32_t result = ARM_DRIVER_OK;
754 bool isContinue = false;
755 /* Must be power on. */
756 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_POWER))
757 {
758 return ARM_DRIVER_ERROR;
759 }
760
761 /* Does not support these features. */
762 if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U)
763 {
764 return ARM_DRIVER_ERROR_UNSUPPORTED;
765 }
766
767 switch (control & ARM_USART_CONTROL_Msk)
768 {
769 /* Abort Send */
770 case ARM_USART_ABORT_SEND:
771 LPUART_TransferAbortSendDMA(lpuart->resource->base, lpuart->handle);
772 result = ARM_DRIVER_OK;
773 break;
774
775 /* Abort receive */
776 case ARM_USART_ABORT_RECEIVE:
777 LPUART_TransferAbortReceiveDMA(lpuart->resource->base, lpuart->handle);
778 result = ARM_DRIVER_OK;
779 break;
780
781 default:
782 isContinue = true;
783 break;
784 }
785
786 if (isContinue)
787 {
788 result = LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags);
789 }
790 return result;
791 }
792
LPUART_DmaGetStatus(cmsis_lpuart_dma_driver_state_t * lpuart)793 static ARM_USART_STATUS LPUART_DmaGetStatus(cmsis_lpuart_dma_driver_state_t *lpuart)
794 {
795 ARM_USART_STATUS stat = {0};
796 uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base);
797
798 stat.tx_busy = (((uint8_t)kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U));
799 stat.rx_busy = (((uint8_t)kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U));
800
801 stat.tx_underflow = 0U;
802 stat.rx_overflow = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_RxOverrunFlag)) != 0U);
803 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
804 stat.rx_break = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)) != 0U);
805 #else
806 stat.rx_break = 0U;
807 #endif
808 stat.rx_framing_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_FramingErrorFlag)) != 0U);
809 stat.rx_parity_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_ParityErrorFlag)) != 0U);
810 stat.reserved = 0U;
811
812 return stat;
813 }
814 #endif
815
816 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
KSDK_LPUART_EdmaCallback(LPUART_Type * base,lpuart_edma_handle_t * handle,status_t status,void * userData)817 static void KSDK_LPUART_EdmaCallback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)
818 {
819 uint32_t event = 0U;
820
821 if (kStatus_LPUART_TxIdle == status)
822 {
823 event = ARM_USART_EVENT_SEND_COMPLETE;
824 }
825 if (kStatus_LPUART_RxIdle == status)
826 {
827 event = ARM_USART_EVENT_RECEIVE_COMPLETE;
828 }
829
830 /* User data is actually CMSIS driver callback. */
831 if ((0U != event) && (userData != NULL))
832 {
833 ((ARM_USART_SignalEvent_t)userData)(event);
834 }
835 }
836
LPUART_EdmaInitialize(ARM_USART_SignalEvent_t cb_event,cmsis_lpuart_edma_driver_state_t * lpuart)837 static int32_t LPUART_EdmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_edma_driver_state_t *lpuart)
838 {
839 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_INIT))
840 {
841 lpuart->cb_event = cb_event;
842 lpuart->flags = (uint8_t)USART_FLAG_INIT;
843 }
844
845 return ARM_DRIVER_OK;
846 }
847
LPUART_EdmaUninitialize(cmsis_lpuart_edma_driver_state_t * lpuart)848 static int32_t LPUART_EdmaUninitialize(cmsis_lpuart_edma_driver_state_t *lpuart)
849 {
850 lpuart->flags = (uint8_t)USART_FLAG_UNINIT;
851 return ARM_DRIVER_OK;
852 }
853
LPUART_EdmaPowerControl(ARM_POWER_STATE state,cmsis_lpuart_edma_driver_state_t * lpuart)854 static int32_t LPUART_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_edma_driver_state_t *lpuart)
855 {
856 lpuart_config_t config;
857 cmsis_lpuart_edma_resource_t *dmaResource;
858 int32_t result = ARM_DRIVER_OK;
859 switch (state)
860 {
861 case ARM_POWER_OFF:
862 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
863 {
864 LPUART_Deinit(lpuart->resource->base);
865
866 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
867 DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxEdmaChannel);
868 DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txEdmaChannel);
869 #endif
870 lpuart->flags = (uint8_t)USART_FLAG_INIT;
871 }
872 break;
873 case ARM_POWER_LOW:
874 result = ARM_DRIVER_ERROR_UNSUPPORTED;
875 break;
876 case ARM_POWER_FULL:
877 /* Must be initialized first. */
878 if (lpuart->flags == (uint8_t)USART_FLAG_UNINIT)
879 {
880 result = ARM_DRIVER_ERROR;
881 break;
882 }
883
884 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
885 {
886 /* Driver already powered */
887 break;
888 }
889
890 LPUART_GetDefaultConfig(&config);
891 config.enableTx = true;
892 config.enableRx = true;
893
894 dmaResource = lpuart->dmaResource;
895
896 /* Set up EDMA setting. */
897 EDMA_CreateHandle(lpuart->rxHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel);
898 EDMA_CreateHandle(lpuart->txHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel);
899 #if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
900 EDMA_SetChannelMux(dmaResource->txEdmaBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest);
901 EDMA_SetChannelMux(dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
902 #endif
903
904 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
905 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
906 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel);
907
908 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest);
909 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel);
910 #endif
911
912 /* Setup the LPUART. */
913 (void)LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq());
914 LPUART_TransferCreateHandleEDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_EdmaCallback,
915 (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle);
916
917 lpuart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED);
918 break;
919 default:
920 result = ARM_DRIVER_ERROR_UNSUPPORTED;
921 break;
922 }
923
924 return result;
925 }
926
LPUART_EdmaSend(const void * data,uint32_t num,cmsis_lpuart_edma_driver_state_t * lpuart)927 static int32_t LPUART_EdmaSend(const void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart)
928 {
929 int32_t ret;
930 status_t status;
931 lpuart_transfer_t xfer;
932
933 xfer.data = (uint8_t *)data;
934 xfer.dataSize = num;
935
936 status = LPUART_SendEDMA(lpuart->resource->base, lpuart->handle, &xfer);
937
938 switch (status)
939 {
940 case kStatus_Success:
941 ret = ARM_DRIVER_OK;
942 break;
943 case kStatus_InvalidArgument:
944 ret = ARM_DRIVER_ERROR_PARAMETER;
945 break;
946 case kStatus_LPUART_RxBusy:
947 ret = ARM_DRIVER_ERROR_BUSY;
948 break;
949 default:
950 ret = ARM_DRIVER_ERROR;
951 break;
952 }
953
954 return ret;
955 }
956
LPUART_EdmaReceive(void * data,uint32_t num,cmsis_lpuart_edma_driver_state_t * lpuart)957 static int32_t LPUART_EdmaReceive(void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart)
958 {
959 int32_t ret;
960 status_t status;
961 lpuart_transfer_t xfer;
962
963 xfer.data = (uint8_t *)data;
964 xfer.dataSize = num;
965
966 status = LPUART_ReceiveEDMA(lpuart->resource->base, lpuart->handle, &xfer);
967
968 switch (status)
969 {
970 case kStatus_Success:
971 ret = ARM_DRIVER_OK;
972 break;
973 case kStatus_InvalidArgument:
974 ret = ARM_DRIVER_ERROR_PARAMETER;
975 break;
976 case kStatus_LPUART_TxBusy:
977 ret = ARM_DRIVER_ERROR_BUSY;
978 break;
979 default:
980 ret = ARM_DRIVER_ERROR;
981 break;
982 }
983
984 return ret;
985 }
986
LPUART_EdmaTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_lpuart_edma_driver_state_t * lpuart)987 static int32_t LPUART_EdmaTransfer(const void *data_out,
988 void *data_in,
989 uint32_t num,
990 cmsis_lpuart_edma_driver_state_t *lpuart)
991 {
992 /* Only in synchronous mode */
993 return ARM_DRIVER_ERROR;
994 }
995
LPUART_EdmaGetTxCount(cmsis_lpuart_edma_driver_state_t * lpuart)996 static uint32_t LPUART_EdmaGetTxCount(cmsis_lpuart_edma_driver_state_t *lpuart)
997 {
998 uint32_t cnt;
999
1000 if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountEDMA(lpuart->resource->base, lpuart->handle, &cnt))
1001 {
1002 cnt = lpuart->handle->txDataSizeAll;
1003 }
1004
1005 return cnt;
1006 }
1007
LPUART_EdmaGetRxCount(cmsis_lpuart_edma_driver_state_t * lpuart)1008 static uint32_t LPUART_EdmaGetRxCount(cmsis_lpuart_edma_driver_state_t *lpuart)
1009 {
1010 uint32_t cnt;
1011
1012 if (kStatus_NoTransferInProgress ==
1013 LPUART_TransferGetReceiveCountEDMA(lpuart->resource->base, lpuart->handle, &cnt))
1014 {
1015 cnt = lpuart->handle->rxDataSizeAll;
1016 }
1017
1018 return cnt;
1019 }
1020
LPUART_EdmaControl(uint32_t control,uint32_t arg,cmsis_lpuart_edma_driver_state_t * lpuart)1021 static int32_t LPUART_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_edma_driver_state_t *lpuart)
1022 {
1023 int32_t result = ARM_DRIVER_OK;
1024 bool isContinue = false;
1025 /* Must be power on. */
1026 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_POWER))
1027 {
1028 return ARM_DRIVER_ERROR;
1029 }
1030
1031 /* Does not support these features. */
1032 if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U)
1033 {
1034 return ARM_DRIVER_ERROR_UNSUPPORTED;
1035 }
1036
1037 switch (control & ARM_USART_CONTROL_Msk)
1038 {
1039 /* Abort Send */
1040 case ARM_USART_ABORT_SEND:
1041 LPUART_TransferAbortSendEDMA(lpuart->resource->base, lpuart->handle);
1042 result = ARM_DRIVER_OK;
1043 break;
1044
1045 /* Abort receive */
1046 case ARM_USART_ABORT_RECEIVE:
1047 LPUART_TransferAbortReceiveEDMA(lpuart->resource->base, lpuart->handle);
1048 result = ARM_DRIVER_OK;
1049 break;
1050
1051 default:
1052 isContinue = true;
1053 break;
1054 }
1055 if (isContinue)
1056 {
1057 result = LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags);
1058 }
1059 return result;
1060 }
1061
LPUART_EdmaGetStatus(cmsis_lpuart_edma_driver_state_t * lpuart)1062 static ARM_USART_STATUS LPUART_EdmaGetStatus(cmsis_lpuart_edma_driver_state_t *lpuart)
1063 {
1064 ARM_USART_STATUS stat = {0};
1065 uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base);
1066
1067 stat.tx_busy = (((uint8_t)kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U));
1068 stat.rx_busy = (((uint8_t)kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U));
1069
1070 stat.tx_underflow = 0U;
1071 stat.rx_overflow = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_RxOverrunFlag)) != 0U);
1072 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
1073 stat.rx_break = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)) != 0U);
1074 #else
1075 stat.rx_break = 0U;
1076 #endif
1077 stat.rx_framing_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_FramingErrorFlag)) != 0U);
1078 stat.rx_parity_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_ParityErrorFlag)) != 0U);
1079 stat.reserved = 0U;
1080
1081 return stat;
1082 }
1083 #endif
1084
1085 #endif
1086
1087 #if (((defined(RTE_USART0) && RTE_USART0 && !(defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN)) && \
1088 defined(LPUART0)) || \
1089 ((defined(RTE_USART1) && RTE_USART1 && !(defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN)) && \
1090 defined(LPUART1)) || \
1091 ((defined(RTE_USART2) && RTE_USART2 && !(defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN)) && \
1092 defined(LPUART2)) || \
1093 ((defined(RTE_USART3) && RTE_USART3 && !(defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN)) && \
1094 defined(LPUART3)) || \
1095 ((defined(RTE_USART4) && RTE_USART4 && !(defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN)) && \
1096 defined(LPUART4)) || \
1097 ((defined(RTE_USART5) && RTE_USART5 && !(defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN)) && \
1098 defined(LPUART5)) || \
1099 ((defined(RTE_USART6) && RTE_USART6 && !(defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN)) && \
1100 defined(LPUART6)) || \
1101 ((defined(RTE_USART7) && RTE_USART7 && !(defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN)) && \
1102 defined(LPUART7)) || \
1103 ((defined(RTE_USART8) && RTE_USART8 && !(defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN)) && \
1104 defined(LPUART8)) || \
1105 ((defined(RTE_USART9) && RTE_USART9 && !(defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN)) && \
1106 defined(LPUART9)) || \
1107 ((defined(RTE_USART10) && RTE_USART10 && !(defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN)) && \
1108 defined(LPUART10)) || \
1109 ((defined(RTE_USART11) && RTE_USART11 && !(defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN)) && \
1110 defined(LPUART11)) || \
1111 ((defined(RTE_USART12) && RTE_USART12 && !(defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN)) && \
1112 defined(LPUART12)) || \
1113 ((defined(RTE_USART13) && RTE_USART13 && !(defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN)) && \
1114 defined(LPUART13)) || \
1115 ((defined(RTE_USART14) && RTE_USART14 && !(defined(RTE_USART14_DMA_EN) && RTE_USART14_DMA_EN)) && \
1116 defined(LPUART14)) || \
1117 ((defined(RTE_USART15) && RTE_USART15 && !(defined(RTE_USART15_DMA_EN) && RTE_USART15_DMA_EN)) && \
1118 defined(LPUART15)) || \
1119 ((defined(RTE_USART16) && RTE_USART16 && !(defined(RTE_USART16_DMA_EN) && RTE_USART16_DMA_EN)) && \
1120 defined(LPUART16)) || \
1121 ((defined(RTE_USART17) && RTE_USART17 && !(defined(RTE_USART17_DMA_EN) && RTE_USART17_DMA_EN)) && \
1122 defined(LPUART17)) || \
1123 ((defined(RTE_USART18) && RTE_USART18 && !(defined(RTE_USART18_DMA_EN) && RTE_USART18_DMA_EN)) && \
1124 defined(LPUART18)) || \
1125 ((defined(RTE_USART19) && RTE_USART19 && !(defined(RTE_USART19_DMA_EN) && RTE_USART19_DMA_EN)) && \
1126 defined(LPUART19)) || \
1127 ((defined(RTE_USART20) && RTE_USART20 && !(defined(RTE_USART20_DMA_EN) && RTE_USART20_DMA_EN)) && \
1128 defined(LPUART20)))
1129
KSDK_LPUART_NonBlockingCallback(LPUART_Type * base,lpuart_handle_t * handle,status_t status,void * userData)1130 static void KSDK_LPUART_NonBlockingCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)
1131 {
1132 uint32_t event = 0U;
1133
1134 if (kStatus_LPUART_TxIdle == status)
1135 {
1136 event = ARM_USART_EVENT_SEND_COMPLETE;
1137 }
1138 if (kStatus_LPUART_RxIdle == status)
1139 {
1140 event = ARM_USART_EVENT_RECEIVE_COMPLETE;
1141 }
1142 if (kStatus_LPUART_RxHardwareOverrun == status)
1143 {
1144 event = ARM_USART_EVENT_RX_OVERFLOW;
1145 }
1146
1147 /* User data is actually CMSIS driver callback. */
1148 if ((0U != event) && (userData != NULL))
1149 {
1150 ((ARM_USART_SignalEvent_t)userData)(event);
1151 }
1152 }
1153
LPUART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1154 static int32_t LPUART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event,
1155 cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1156 {
1157 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_INIT))
1158 {
1159 lpuart->cb_event = cb_event;
1160 lpuart->flags = (uint8_t)USART_FLAG_INIT;
1161 }
1162
1163 return ARM_DRIVER_OK;
1164 }
1165
LPUART_NonBlockingUninitialize(cmsis_lpuart_non_blocking_driver_state_t * lpuart)1166 static int32_t LPUART_NonBlockingUninitialize(cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1167 {
1168 lpuart->flags = (uint8_t)USART_FLAG_UNINIT;
1169 return ARM_DRIVER_OK;
1170 }
1171
LPUART_NonBlockingPowerControl(ARM_POWER_STATE state,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1172 static int32_t LPUART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1173 {
1174 lpuart_config_t config;
1175 int32_t result = ARM_DRIVER_OK;
1176
1177 switch (state)
1178 {
1179 case ARM_POWER_OFF:
1180 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
1181 {
1182 LPUART_Deinit(lpuart->resource->base);
1183 lpuart->flags = (uint8_t)USART_FLAG_INIT;
1184 }
1185 break;
1186 case ARM_POWER_LOW:
1187 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1188 break;
1189 case ARM_POWER_FULL:
1190 /* Must be initialized first. */
1191 if (lpuart->flags == (uint8_t)USART_FLAG_UNINIT)
1192 {
1193 result = ARM_DRIVER_ERROR;
1194 break;
1195 }
1196
1197 if ((lpuart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
1198 {
1199 /* Driver already powered */
1200 break;
1201 }
1202
1203 LPUART_GetDefaultConfig(&config);
1204 config.enableTx = true;
1205 config.enableRx = true;
1206
1207 (void)LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq());
1208 LPUART_TransferCreateHandle(lpuart->resource->base, lpuart->handle, KSDK_LPUART_NonBlockingCallback,
1209 (void *)lpuart->cb_event);
1210 lpuart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED);
1211
1212 break;
1213 default:
1214 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1215 break;
1216 }
1217
1218 return result;
1219 }
1220
LPUART_NonBlockingSend(const void * data,uint32_t num,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1221 static int32_t LPUART_NonBlockingSend(const void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1222 {
1223 int32_t ret;
1224 status_t status;
1225 lpuart_transfer_t xfer;
1226
1227 xfer.data = (uint8_t *)data;
1228 xfer.dataSize = num;
1229
1230 status = LPUART_TransferSendNonBlocking(lpuart->resource->base, lpuart->handle, &xfer);
1231
1232 switch (status)
1233 {
1234 case kStatus_Success:
1235 ret = ARM_DRIVER_OK;
1236 break;
1237 case kStatus_InvalidArgument:
1238 ret = ARM_DRIVER_ERROR_PARAMETER;
1239 break;
1240 case kStatus_LPUART_RxBusy:
1241 ret = ARM_DRIVER_ERROR_BUSY;
1242 break;
1243 default:
1244 ret = ARM_DRIVER_ERROR;
1245 break;
1246 }
1247
1248 return ret;
1249 }
1250
LPUART_NonBlockingReceive(void * data,uint32_t num,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1251 static int32_t LPUART_NonBlockingReceive(void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1252 {
1253 int32_t ret;
1254 status_t status;
1255 lpuart_transfer_t xfer;
1256
1257 xfer.data = (uint8_t *)data;
1258 xfer.dataSize = num;
1259
1260 status = LPUART_TransferReceiveNonBlocking(lpuart->resource->base, lpuart->handle, &xfer, NULL);
1261
1262 switch (status)
1263 {
1264 case kStatus_Success:
1265 ret = ARM_DRIVER_OK;
1266 break;
1267 case kStatus_InvalidArgument:
1268 ret = ARM_DRIVER_ERROR_PARAMETER;
1269 break;
1270 case kStatus_LPUART_TxBusy:
1271 ret = ARM_DRIVER_ERROR_BUSY;
1272 break;
1273 default:
1274 ret = ARM_DRIVER_ERROR;
1275 break;
1276 }
1277
1278 return ret;
1279 }
1280
LPUART_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1281 static int32_t LPUART_NonBlockingTransfer(const void *data_out,
1282 void *data_in,
1283 uint32_t num,
1284 cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1285 {
1286 /* Only in synchronous mode */
1287 return ARM_DRIVER_ERROR;
1288 }
1289
LPUART_NonBlockingGetTxCount(cmsis_lpuart_non_blocking_driver_state_t * lpuart)1290 static uint32_t LPUART_NonBlockingGetTxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1291 {
1292 uint32_t cnt;
1293
1294 /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
1295 if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCount(lpuart->resource->base, lpuart->handle, &cnt))
1296 {
1297 cnt = lpuart->handle->txDataSizeAll;
1298 }
1299
1300 return cnt;
1301 }
1302
LPUART_NonBlockingGetRxCount(cmsis_lpuart_non_blocking_driver_state_t * lpuart)1303 static uint32_t LPUART_NonBlockingGetRxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1304 {
1305 uint32_t cnt;
1306
1307 if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCount(lpuart->resource->base, lpuart->handle, &cnt))
1308 {
1309 cnt = lpuart->handle->rxDataSizeAll;
1310 }
1311
1312 return cnt;
1313 }
1314
LPUART_NonBlockingControl(uint32_t control,uint32_t arg,cmsis_lpuart_non_blocking_driver_state_t * lpuart)1315 static int32_t LPUART_NonBlockingControl(uint32_t control,
1316 uint32_t arg,
1317 cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1318 {
1319 int32_t result = ARM_DRIVER_OK;
1320 bool isContinue = false;
1321 /* Must be power on. */
1322 if (0U == (lpuart->flags & (uint8_t)USART_FLAG_POWER))
1323 {
1324 return ARM_DRIVER_ERROR;
1325 }
1326
1327 /* Does not support these features. */
1328 if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U)
1329 {
1330 return ARM_DRIVER_ERROR_UNSUPPORTED;
1331 }
1332
1333 switch (control & ARM_USART_CONTROL_Msk)
1334 {
1335 /* Abort Send */
1336 case ARM_USART_ABORT_SEND:
1337 LPUART_TransferAbortSend(lpuart->resource->base, lpuart->handle);
1338 result = ARM_DRIVER_OK;
1339 break;
1340
1341 /* Abort receive */
1342 case ARM_USART_ABORT_RECEIVE:
1343 LPUART_TransferAbortReceive(lpuart->resource->base, lpuart->handle);
1344 result = ARM_DRIVER_OK;
1345 break;
1346
1347 default:
1348 isContinue = true;
1349 break;
1350 }
1351 if (isContinue)
1352 {
1353 result = LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags);
1354 }
1355 return result;
1356 }
1357
LPUART_NonBlockingGetStatus(cmsis_lpuart_non_blocking_driver_state_t * lpuart)1358 static ARM_USART_STATUS LPUART_NonBlockingGetStatus(cmsis_lpuart_non_blocking_driver_state_t *lpuart)
1359 {
1360 ARM_USART_STATUS stat = {0};
1361 uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base);
1362
1363 stat.tx_busy = (((uint8_t)kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U));
1364 stat.rx_busy = (((uint8_t)kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U));
1365
1366 stat.tx_underflow = 0U;
1367 stat.rx_overflow = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_RxOverrunFlag)) != 0U);
1368 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
1369 stat.rx_break = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)) != 0U);
1370 #else
1371 stat.rx_break = 0U;
1372 #endif
1373 stat.rx_framing_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_FramingErrorFlag)) != 0U);
1374 stat.rx_parity_error = (uint32_t)(((ksdk_lpuart_status & (uint32_t)kLPUART_ParityErrorFlag)) != 0U);
1375 stat.reserved = 0U;
1376
1377 return stat;
1378 }
1379
1380 #endif
1381
1382 #if defined(LPUART0) && defined(RTE_USART0) && RTE_USART0
1383
1384 /* User needs to provide the implementation for LPUART0_GetFreq/InitPins/DeinitPins
1385 in the application for enabling according instance. */
1386 extern uint32_t LPUART0_GetFreq(void);
1387
1388 static cmsis_lpuart_resource_t LPUART0_Resource = {LPUART0, LPUART0_GetFreq};
1389
1390 #if defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN
1391
1392 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1393
1394 static cmsis_lpuart_dma_resource_t LPUART0_DmaResource = {
1395 RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_PERI_SEL,
1396 RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_PERI_SEL,
1397
1398 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1399 RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_RX_DMAMUX_BASE,
1400 #endif
1401 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1402 RTE_USART0_DMAMUX_TX_CH, RTE_USART0_DMAMUX_RX_CH
1403 #endif
1404 };
1405
1406 static lpuart_dma_handle_t LPUART0_DmaHandle;
1407 static dma_handle_t LPUART0_DmaRxHandle;
1408 static dma_handle_t LPUART0_DmaTxHandle;
1409
1410 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1411 ARMCC_SECTION("lpuart0_dma_driver_state")
1412 static cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = {
1413 #else
1414 static cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = {
1415 #endif
1416 &LPUART0_Resource, &LPUART0_DmaResource, &LPUART0_DmaHandle, &LPUART0_DmaRxHandle, &LPUART0_DmaTxHandle,
1417 };
1418
LPUART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event)1419 static int32_t LPUART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
1420 {
1421 #ifdef RTE_USART0_PIN_INIT
1422 RTE_USART0_PIN_INIT();
1423 #endif
1424 return LPUART_DmaInitialize(cb_event, &LPUART0_DmaDriverState);
1425 }
1426
LPUART0_DmaUninitialize(void)1427 static int32_t LPUART0_DmaUninitialize(void)
1428 {
1429 #ifdef RTE_USART0_PIN_DEINIT
1430 RTE_USART0_PIN_DEINIT();
1431 #endif
1432 return LPUART_DmaUninitialize(&LPUART0_DmaDriverState);
1433 }
1434
LPUART0_DmaPowerControl(ARM_POWER_STATE state)1435 static int32_t LPUART0_DmaPowerControl(ARM_POWER_STATE state)
1436 {
1437 return LPUART_DmaPowerControl(state, &LPUART0_DmaDriverState);
1438 }
1439
LPUART0_DmaSend(const void * data,uint32_t num)1440 static int32_t LPUART0_DmaSend(const void *data, uint32_t num)
1441 {
1442 return LPUART_DmaSend(data, num, &LPUART0_DmaDriverState);
1443 }
1444
LPUART0_DmaReceive(void * data,uint32_t num)1445 static int32_t LPUART0_DmaReceive(void *data, uint32_t num)
1446 {
1447 return LPUART_DmaReceive(data, num, &LPUART0_DmaDriverState);
1448 }
1449
LPUART0_DmaTransfer(const void * data_out,void * data_in,uint32_t num)1450 static int32_t LPUART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
1451 {
1452 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART0_DmaDriverState);
1453 }
1454
LPUART0_DmaGetTxCount(void)1455 static uint32_t LPUART0_DmaGetTxCount(void)
1456 {
1457 return LPUART_DmaGetTxCount(&LPUART0_DmaDriverState);
1458 }
1459
LPUART0_DmaGetRxCount(void)1460 static uint32_t LPUART0_DmaGetRxCount(void)
1461 {
1462 return LPUART_DmaGetRxCount(&LPUART0_DmaDriverState);
1463 }
1464
LPUART0_DmaControl(uint32_t control,uint32_t arg)1465 static int32_t LPUART0_DmaControl(uint32_t control, uint32_t arg)
1466 {
1467 return LPUART_DmaControl(control, arg, &LPUART0_DmaDriverState);
1468 }
1469
LPUART0_DmaGetStatus(void)1470 static ARM_USART_STATUS LPUART0_DmaGetStatus(void)
1471 {
1472 return LPUART_DmaGetStatus(&LPUART0_DmaDriverState);
1473 }
1474
1475 #endif
1476
1477 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1478
1479 static cmsis_lpuart_edma_resource_t LPUART0_EdmaResource = {
1480 RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_PERI_SEL,
1481 RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_PERI_SEL,
1482
1483 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1484 RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_RX_DMAMUX_BASE,
1485 #endif
1486 };
1487
1488 static lpuart_edma_handle_t LPUART0_EdmaHandle;
1489 static edma_handle_t LPUART0_EdmaRxHandle;
1490 static edma_handle_t LPUART0_EdmaTxHandle;
1491
1492 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1493 ARMCC_SECTION("lpuart0_edma_driver_state")
1494 static cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = {
1495 #else
1496 static cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = {
1497 #endif
1498 &LPUART0_Resource, &LPUART0_EdmaResource, &LPUART0_EdmaHandle, &LPUART0_EdmaRxHandle, &LPUART0_EdmaTxHandle,
1499 };
1500
LPUART0_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)1501 static int32_t LPUART0_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
1502 {
1503 #ifdef RTE_USART0_PIN_INIT
1504 RTE_USART0_PIN_INIT();
1505 #endif
1506 return LPUART_EdmaInitialize(cb_event, &LPUART0_EdmaDriverState);
1507 }
1508
LPUART0_EdmaUninitialize(void)1509 static int32_t LPUART0_EdmaUninitialize(void)
1510 {
1511 #ifdef RTE_USART0_PIN_DEINIT
1512 RTE_USART0_PIN_DEINIT();
1513 #endif
1514 return LPUART_EdmaUninitialize(&LPUART0_EdmaDriverState);
1515 }
1516
LPUART0_EdmaPowerControl(ARM_POWER_STATE state)1517 static int32_t LPUART0_EdmaPowerControl(ARM_POWER_STATE state)
1518 {
1519 return LPUART_EdmaPowerControl(state, &LPUART0_EdmaDriverState);
1520 }
1521
LPUART0_EdmaSend(const void * data,uint32_t num)1522 static int32_t LPUART0_EdmaSend(const void *data, uint32_t num)
1523 {
1524 return LPUART_EdmaSend(data, num, &LPUART0_EdmaDriverState);
1525 }
1526
LPUART0_EdmaReceive(void * data,uint32_t num)1527 static int32_t LPUART0_EdmaReceive(void *data, uint32_t num)
1528 {
1529 return LPUART_EdmaReceive(data, num, &LPUART0_EdmaDriverState);
1530 }
1531
LPUART0_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1532 static int32_t LPUART0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1533 {
1534 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART0_EdmaDriverState);
1535 }
1536
LPUART0_EdmaGetTxCount(void)1537 static uint32_t LPUART0_EdmaGetTxCount(void)
1538 {
1539 return LPUART_EdmaGetTxCount(&LPUART0_EdmaDriverState);
1540 }
1541
LPUART0_EdmaGetRxCount(void)1542 static uint32_t LPUART0_EdmaGetRxCount(void)
1543 {
1544 return LPUART_EdmaGetRxCount(&LPUART0_EdmaDriverState);
1545 }
1546
LPUART0_EdmaControl(uint32_t control,uint32_t arg)1547 static int32_t LPUART0_EdmaControl(uint32_t control, uint32_t arg)
1548 {
1549 return LPUART_EdmaControl(control, arg, &LPUART0_EdmaDriverState);
1550 }
1551
LPUART0_EdmaGetStatus(void)1552 static ARM_USART_STATUS LPUART0_EdmaGetStatus(void)
1553 {
1554 return LPUART_EdmaGetStatus(&LPUART0_EdmaDriverState);
1555 }
1556
1557 #endif
1558
1559 #else
1560
1561 static lpuart_handle_t LPUART0_Handle;
1562
1563 #if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
1564 static uint8_t lpuart0_rxRingBuffer[USART_RX_BUFFER_LEN];
1565 #endif
1566
1567 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1568 ARMCC_SECTION("lpuart0_non_blocking_driver_state")
1569 static cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = {
1570 #else
1571 static cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = {
1572 #endif
1573 &LPUART0_Resource,
1574 &LPUART0_Handle,
1575 };
1576
LPUART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)1577 static int32_t LPUART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
1578 {
1579 #ifdef RTE_USART0_PIN_INIT
1580 RTE_USART0_PIN_INIT();
1581 #endif
1582 return LPUART_NonBlockingInitialize(cb_event, &LPUART0_NonBlockingDriverState);
1583 }
1584
LPUART0_NonBlockingUninitialize(void)1585 static int32_t LPUART0_NonBlockingUninitialize(void)
1586 {
1587 #ifdef RTE_USART0_PIN_DEINIT
1588 RTE_USART0_PIN_DEINIT();
1589 #endif
1590 return LPUART_NonBlockingUninitialize(&LPUART0_NonBlockingDriverState);
1591 }
1592
LPUART0_NonBlockingPowerControl(ARM_POWER_STATE state)1593 static int32_t LPUART0_NonBlockingPowerControl(ARM_POWER_STATE state)
1594 {
1595 int32_t result;
1596
1597 result = LPUART_NonBlockingPowerControl(state, &LPUART0_NonBlockingDriverState);
1598
1599 #if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
1600 if ((state == ARM_POWER_FULL) && (LPUART0_NonBlockingDriverState.handle->rxRingBuffer == NULL))
1601 {
1602 LPUART_TransferStartRingBuffer(LPUART0_NonBlockingDriverState.resource->base,
1603 LPUART0_NonBlockingDriverState.handle, lpuart0_rxRingBuffer,
1604 USART_RX_BUFFER_LEN);
1605 }
1606 #endif
1607
1608 return result;
1609 }
1610
LPUART0_NonBlockingSend(const void * data,uint32_t num)1611 static int32_t LPUART0_NonBlockingSend(const void *data, uint32_t num)
1612 {
1613 return LPUART_NonBlockingSend(data, num, &LPUART0_NonBlockingDriverState);
1614 }
1615
LPUART0_NonBlockingReceive(void * data,uint32_t num)1616 static int32_t LPUART0_NonBlockingReceive(void *data, uint32_t num)
1617 {
1618 return LPUART_NonBlockingReceive(data, num, &LPUART0_NonBlockingDriverState);
1619 }
1620
LPUART0_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)1621 static int32_t LPUART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
1622 {
1623 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART0_NonBlockingDriverState);
1624 }
1625
LPUART0_NonBlockingGetTxCount(void)1626 static uint32_t LPUART0_NonBlockingGetTxCount(void)
1627 {
1628 return LPUART_NonBlockingGetTxCount(&LPUART0_NonBlockingDriverState);
1629 }
1630
LPUART0_NonBlockingGetRxCount(void)1631 static uint32_t LPUART0_NonBlockingGetRxCount(void)
1632 {
1633 return LPUART_NonBlockingGetRxCount(&LPUART0_NonBlockingDriverState);
1634 }
1635
LPUART0_NonBlockingControl(uint32_t control,uint32_t arg)1636 static int32_t LPUART0_NonBlockingControl(uint32_t control, uint32_t arg)
1637 {
1638 int32_t result;
1639
1640 result = LPUART_NonBlockingControl(control, arg, &LPUART0_NonBlockingDriverState);
1641 if (ARM_DRIVER_OK != result)
1642 {
1643 return result;
1644 }
1645
1646 /* Enable the receive interrupts if ring buffer is used */
1647 if (LPUART0_NonBlockingDriverState.handle->rxRingBuffer != NULL)
1648 {
1649 LPUART_EnableInterrupts(
1650 LPUART0_NonBlockingDriverState.resource->base,
1651 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
1652 }
1653
1654 return ARM_DRIVER_OK;
1655 }
1656
LPUART0_NonBlockingGetStatus(void)1657 static ARM_USART_STATUS LPUART0_NonBlockingGetStatus(void)
1658 {
1659 return LPUART_NonBlockingGetStatus(&LPUART0_NonBlockingDriverState);
1660 }
1661
1662 #endif
1663
1664 #if (FSL_FEATURE_SOC_LPUART_COUNT == 1)
1665 #if (FSL_FEATURE_SOC_UART_COUNT == 3)
1666 ARM_DRIVER_USART Driver_USART3 = {
1667 #elif (FSL_FEATURE_SOC_UART_COUNT == 4)
1668 ARM_DRIVER_USART Driver_USART4 = {
1669 #elif (FSL_FEATURE_SOC_UART_COUNT == 5)
1670 ARM_DRIVER_USART Driver_USART5 = {
1671 #else
1672 ARM_DRIVER_USART Driver_USART0 = {
1673 #endif
1674 #else
1675 ARM_DRIVER_USART Driver_USART0 = {
1676 #endif
1677
1678 LPUARTx_GetVersion, LPUARTx_GetCapabilities,
1679 #if defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN
1680 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1681 LPUART0_EdmaInitialize, LPUART0_EdmaUninitialize, LPUART0_EdmaPowerControl, LPUART0_EdmaSend,
1682 LPUART0_EdmaReceive, LPUART0_EdmaTransfer, LPUART0_EdmaGetTxCount, LPUART0_EdmaGetRxCount,
1683 LPUART0_EdmaControl, LPUART0_EdmaGetStatus,
1684 #else
1685 LPUART0_DmaInitialize, LPUART0_DmaUninitialize, LPUART0_DmaPowerControl, LPUART0_DmaSend, LPUART0_DmaReceive,
1686 LPUART0_DmaTransfer, LPUART0_DmaGetTxCount, LPUART0_DmaGetRxCount, LPUART0_DmaControl, LPUART0_DmaGetStatus,
1687 #endif
1688 #else
1689 LPUART0_NonBlockingInitialize,
1690 LPUART0_NonBlockingUninitialize,
1691 LPUART0_NonBlockingPowerControl,
1692 LPUART0_NonBlockingSend,
1693 LPUART0_NonBlockingReceive,
1694 LPUART0_NonBlockingTransfer,
1695 LPUART0_NonBlockingGetTxCount,
1696 LPUART0_NonBlockingGetRxCount,
1697 LPUART0_NonBlockingControl,
1698 LPUART0_NonBlockingGetStatus,
1699 #endif
1700 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
1701
1702 #endif /* LPUART0 */
1703
1704 #if defined(LPUART1) && defined(RTE_USART1) && RTE_USART1
1705
1706 /* User needs to provide the implementation for LPUART1_GetFreq/InitPins/DeinitPins
1707 in the application for enabling according instance. */
1708 extern uint32_t LPUART1_GetFreq(void);
1709
1710 static cmsis_lpuart_resource_t LPUART1_Resource = {LPUART1, LPUART1_GetFreq};
1711
1712 #if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN
1713
1714 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1715
1716 static cmsis_lpuart_dma_resource_t LPUART1_DmaResource = {
1717 RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_PERI_SEL,
1718 RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_PERI_SEL,
1719
1720 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1721 RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_RX_DMAMUX_BASE,
1722 #endif
1723 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1724 RTE_USART1_DMAMUX_TX_CH, RTE_USART1_DMAMUX_RX_CH
1725 #endif
1726 };
1727
1728 static lpuart_dma_handle_t LPUART1_DmaHandle;
1729 static dma_handle_t LPUART1_DmaRxHandle;
1730 static dma_handle_t LPUART1_DmaTxHandle;
1731
1732 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1733 ARMCC_SECTION("lpuart1_dma_driver_state")
1734 static cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = {
1735 #else
1736 static cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = {
1737 #endif
1738 &LPUART1_Resource, &LPUART1_DmaResource, &LPUART1_DmaHandle, &LPUART1_DmaRxHandle, &LPUART1_DmaTxHandle,
1739 };
1740
LPUART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event)1741 static int32_t LPUART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
1742 {
1743 #ifdef RTE_USART1_PIN_INIT
1744 RTE_USART1_PIN_INIT();
1745 #endif
1746 return LPUART_DmaInitialize(cb_event, &LPUART1_DmaDriverState);
1747 }
1748
LPUART1_DmaUninitialize(void)1749 static int32_t LPUART1_DmaUninitialize(void)
1750 {
1751 #ifdef RTE_USART1_PIN_DEINIT
1752 RTE_USART1_PIN_DEINIT();
1753 #endif
1754 return LPUART_DmaUninitialize(&LPUART1_DmaDriverState);
1755 }
1756
LPUART1_DmaPowerControl(ARM_POWER_STATE state)1757 static int32_t LPUART1_DmaPowerControl(ARM_POWER_STATE state)
1758 {
1759 return LPUART_DmaPowerControl(state, &LPUART1_DmaDriverState);
1760 }
1761
LPUART1_DmaSend(const void * data,uint32_t num)1762 static int32_t LPUART1_DmaSend(const void *data, uint32_t num)
1763 {
1764 return LPUART_DmaSend(data, num, &LPUART1_DmaDriverState);
1765 }
1766
LPUART1_DmaReceive(void * data,uint32_t num)1767 static int32_t LPUART1_DmaReceive(void *data, uint32_t num)
1768 {
1769 return LPUART_DmaReceive(data, num, &LPUART1_DmaDriverState);
1770 }
1771
LPUART1_DmaTransfer(const void * data_out,void * data_in,uint32_t num)1772 static int32_t LPUART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
1773 {
1774 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART1_DmaDriverState);
1775 }
1776
LPUART1_DmaGetTxCount(void)1777 static uint32_t LPUART1_DmaGetTxCount(void)
1778 {
1779 return LPUART_DmaGetTxCount(&LPUART1_DmaDriverState);
1780 }
1781
LPUART1_DmaGetRxCount(void)1782 static uint32_t LPUART1_DmaGetRxCount(void)
1783 {
1784 return LPUART_DmaGetRxCount(&LPUART1_DmaDriverState);
1785 }
1786
LPUART1_DmaControl(uint32_t control,uint32_t arg)1787 static int32_t LPUART1_DmaControl(uint32_t control, uint32_t arg)
1788 {
1789 return LPUART_DmaControl(control, arg, &LPUART1_DmaDriverState);
1790 }
1791
LPUART1_DmaGetStatus(void)1792 static ARM_USART_STATUS LPUART1_DmaGetStatus(void)
1793 {
1794 return LPUART_DmaGetStatus(&LPUART1_DmaDriverState);
1795 }
1796
1797 #endif
1798
1799 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1800
1801 static cmsis_lpuart_edma_resource_t LPUART1_EdmaResource = {
1802 RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_PERI_SEL,
1803 RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_PERI_SEL,
1804
1805 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1806 RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_RX_DMAMUX_BASE,
1807 #endif
1808 };
1809
1810 static lpuart_edma_handle_t LPUART1_EdmaHandle;
1811 static edma_handle_t LPUART1_EdmaRxHandle;
1812 static edma_handle_t LPUART1_EdmaTxHandle;
1813
1814 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1815 ARMCC_SECTION("lpuart1_edma_driver_state")
1816 static cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = {
1817 #else
1818 static cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = {
1819 #endif
1820 &LPUART1_Resource, &LPUART1_EdmaResource, &LPUART1_EdmaHandle, &LPUART1_EdmaRxHandle, &LPUART1_EdmaTxHandle,
1821 };
1822
LPUART1_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)1823 static int32_t LPUART1_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
1824 {
1825 #ifdef RTE_USART1_PIN_INIT
1826 RTE_USART1_PIN_INIT();
1827 #endif
1828 return LPUART_EdmaInitialize(cb_event, &LPUART1_EdmaDriverState);
1829 }
1830
LPUART1_EdmaUninitialize(void)1831 static int32_t LPUART1_EdmaUninitialize(void)
1832 {
1833 #ifdef RTE_USART1_PIN_DEINIT
1834 RTE_USART1_PIN_DEINIT();
1835 #endif
1836 return LPUART_EdmaUninitialize(&LPUART1_EdmaDriverState);
1837 }
1838
LPUART1_EdmaPowerControl(ARM_POWER_STATE state)1839 static int32_t LPUART1_EdmaPowerControl(ARM_POWER_STATE state)
1840 {
1841 return LPUART_EdmaPowerControl(state, &LPUART1_EdmaDriverState);
1842 }
1843
LPUART1_EdmaSend(const void * data,uint32_t num)1844 static int32_t LPUART1_EdmaSend(const void *data, uint32_t num)
1845 {
1846 return LPUART_EdmaSend(data, num, &LPUART1_EdmaDriverState);
1847 }
1848
LPUART1_EdmaReceive(void * data,uint32_t num)1849 static int32_t LPUART1_EdmaReceive(void *data, uint32_t num)
1850 {
1851 return LPUART_EdmaReceive(data, num, &LPUART1_EdmaDriverState);
1852 }
1853
LPUART1_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1854 static int32_t LPUART1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1855 {
1856 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART1_EdmaDriverState);
1857 }
1858
LPUART1_EdmaGetTxCount(void)1859 static uint32_t LPUART1_EdmaGetTxCount(void)
1860 {
1861 return LPUART_EdmaGetTxCount(&LPUART1_EdmaDriverState);
1862 }
1863
LPUART1_EdmaGetRxCount(void)1864 static uint32_t LPUART1_EdmaGetRxCount(void)
1865 {
1866 return LPUART_EdmaGetRxCount(&LPUART1_EdmaDriverState);
1867 }
1868
LPUART1_EdmaControl(uint32_t control,uint32_t arg)1869 static int32_t LPUART1_EdmaControl(uint32_t control, uint32_t arg)
1870 {
1871 return LPUART_EdmaControl(control, arg, &LPUART1_EdmaDriverState);
1872 }
1873
LPUART1_EdmaGetStatus(void)1874 static ARM_USART_STATUS LPUART1_EdmaGetStatus(void)
1875 {
1876 return LPUART_EdmaGetStatus(&LPUART1_EdmaDriverState);
1877 }
1878
1879 #endif
1880
1881 #else
1882
1883 static lpuart_handle_t LPUART1_Handle;
1884
1885 #if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
1886 static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN];
1887 #endif
1888
1889 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1890 ARMCC_SECTION("lpuart1_non_blocking_driver_state")
1891 static cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = {
1892 #else
1893 static cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = {
1894 #endif
1895 &LPUART1_Resource,
1896 &LPUART1_Handle,
1897 };
1898
LPUART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)1899 static int32_t LPUART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
1900 {
1901 #ifdef RTE_USART1_PIN_INIT
1902 RTE_USART1_PIN_INIT();
1903 #endif
1904 return LPUART_NonBlockingInitialize(cb_event, &LPUART1_NonBlockingDriverState);
1905 }
1906
LPUART1_NonBlockingUninitialize(void)1907 static int32_t LPUART1_NonBlockingUninitialize(void)
1908 {
1909 #ifdef RTE_USART1_PIN_DEINIT
1910 RTE_USART1_PIN_DEINIT();
1911 #endif
1912 return LPUART_NonBlockingUninitialize(&LPUART1_NonBlockingDriverState);
1913 }
1914
LPUART1_NonBlockingPowerControl(ARM_POWER_STATE state)1915 static int32_t LPUART1_NonBlockingPowerControl(ARM_POWER_STATE state)
1916 {
1917 int32_t result;
1918
1919 result = LPUART_NonBlockingPowerControl(state, &LPUART1_NonBlockingDriverState);
1920
1921 #if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
1922 if ((state == ARM_POWER_FULL) && (LPUART1_NonBlockingDriverState.handle->rxRingBuffer == NULL))
1923 {
1924 LPUART_TransferStartRingBuffer(LPUART1_NonBlockingDriverState.resource->base,
1925 LPUART1_NonBlockingDriverState.handle, lpuart1_rxRingBuffer,
1926 USART_RX_BUFFER_LEN);
1927 }
1928 #endif
1929
1930 return result;
1931 }
1932
LPUART1_NonBlockingSend(const void * data,uint32_t num)1933 static int32_t LPUART1_NonBlockingSend(const void *data, uint32_t num)
1934 {
1935 return LPUART_NonBlockingSend(data, num, &LPUART1_NonBlockingDriverState);
1936 }
1937
LPUART1_NonBlockingReceive(void * data,uint32_t num)1938 static int32_t LPUART1_NonBlockingReceive(void *data, uint32_t num)
1939 {
1940 return LPUART_NonBlockingReceive(data, num, &LPUART1_NonBlockingDriverState);
1941 }
1942
LPUART1_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)1943 static int32_t LPUART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
1944 {
1945 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART1_NonBlockingDriverState);
1946 }
1947
LPUART1_NonBlockingGetTxCount(void)1948 static uint32_t LPUART1_NonBlockingGetTxCount(void)
1949 {
1950 return LPUART_NonBlockingGetTxCount(&LPUART1_NonBlockingDriverState);
1951 }
1952
LPUART1_NonBlockingGetRxCount(void)1953 static uint32_t LPUART1_NonBlockingGetRxCount(void)
1954 {
1955 return LPUART_NonBlockingGetRxCount(&LPUART1_NonBlockingDriverState);
1956 }
1957
LPUART1_NonBlockingControl(uint32_t control,uint32_t arg)1958 static int32_t LPUART1_NonBlockingControl(uint32_t control, uint32_t arg)
1959 {
1960 int32_t result;
1961
1962 result = LPUART_NonBlockingControl(control, arg, &LPUART1_NonBlockingDriverState);
1963 if (ARM_DRIVER_OK != result)
1964 {
1965 return result;
1966 }
1967
1968 /* Enable the receive interrupts if ring buffer is used */
1969 if (LPUART1_NonBlockingDriverState.handle->rxRingBuffer != NULL)
1970 {
1971 LPUART_EnableInterrupts(
1972 LPUART1_NonBlockingDriverState.resource->base,
1973 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
1974 }
1975
1976 return ARM_DRIVER_OK;
1977 }
1978
LPUART1_NonBlockingGetStatus(void)1979 static ARM_USART_STATUS LPUART1_NonBlockingGetStatus(void)
1980 {
1981 return LPUART_NonBlockingGetStatus(&LPUART1_NonBlockingDriverState);
1982 }
1983
1984 #endif
1985
1986 ARM_DRIVER_USART Driver_USART1 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
1987 #if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN
1988 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1989 LPUART1_EdmaInitialize, LPUART1_EdmaUninitialize, LPUART1_EdmaPowerControl,
1990 LPUART1_EdmaSend, LPUART1_EdmaReceive, LPUART1_EdmaTransfer,
1991 LPUART1_EdmaGetTxCount, LPUART1_EdmaGetRxCount, LPUART1_EdmaControl,
1992 LPUART1_EdmaGetStatus,
1993 #else
1994 LPUART1_DmaInitialize, LPUART1_DmaUninitialize, LPUART1_DmaPowerControl,
1995 LPUART1_DmaSend, LPUART1_DmaReceive, LPUART1_DmaTransfer,
1996 LPUART1_DmaGetTxCount, LPUART1_DmaGetRxCount, LPUART1_DmaControl,
1997 LPUART1_DmaGetStatus,
1998 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
1999 #else
2000 LPUART1_NonBlockingInitialize,
2001 LPUART1_NonBlockingUninitialize,
2002 LPUART1_NonBlockingPowerControl,
2003 LPUART1_NonBlockingSend,
2004 LPUART1_NonBlockingReceive,
2005 LPUART1_NonBlockingTransfer,
2006 LPUART1_NonBlockingGetTxCount,
2007 LPUART1_NonBlockingGetRxCount,
2008 LPUART1_NonBlockingControl,
2009 LPUART1_NonBlockingGetStatus,
2010 #endif /* RTE_USART1_DMA_EN */
2011 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
2012
2013 #endif /* LPUART1 */
2014
2015 #if defined(LPUART2) && defined(RTE_USART2) && RTE_USART2
2016
2017 /* User needs to provide the implementation for LPUART2_GetFreq/InitPins/DeinitPins
2018 in the application for enabling according instance. */
2019 extern uint32_t LPUART2_GetFreq(void);
2020
2021 static cmsis_lpuart_resource_t LPUART2_Resource = {LPUART2, LPUART2_GetFreq};
2022
2023 #if defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN
2024
2025 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2026
2027 static cmsis_lpuart_dma_resource_t LPUART2_DmaResource = {
2028 RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_PERI_SEL,
2029 RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_PERI_SEL,
2030
2031 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2032 RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_RX_DMAMUX_BASE,
2033 #endif
2034 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
2035 RTE_USART2_DMAMUX_TX_CH, RTE_USART2_DMAMUX_RX_CH
2036 #endif
2037 };
2038
2039 static lpuart_dma_handle_t LPUART2_DmaHandle;
2040 static dma_handle_t LPUART2_DmaRxHandle;
2041 static dma_handle_t LPUART2_DmaTxHandle;
2042
2043 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2044 ARMCC_SECTION("lpuart2_dma_driver_state")
2045 static cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = {
2046 #else
2047 static cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = {
2048 #endif
2049 &LPUART2_Resource, &LPUART2_DmaResource, &LPUART2_DmaHandle, &LPUART2_DmaRxHandle, &LPUART2_DmaTxHandle,
2050 };
2051
LPUART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event)2052 static int32_t LPUART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
2053 {
2054 #ifdef RTE_USART2_PIN_INIT
2055 RTE_USART2_PIN_INIT();
2056 #endif
2057 return LPUART_DmaInitialize(cb_event, &LPUART2_DmaDriverState);
2058 }
2059
LPUART2_DmaUninitialize(void)2060 static int32_t LPUART2_DmaUninitialize(void)
2061 {
2062 #ifdef RTE_USART2_PIN_DEINIT
2063 RTE_USART2_PIN_DEINIT();
2064 #endif
2065 return LPUART_DmaUninitialize(&LPUART2_DmaDriverState);
2066 }
2067
LPUART2_DmaPowerControl(ARM_POWER_STATE state)2068 static int32_t LPUART2_DmaPowerControl(ARM_POWER_STATE state)
2069 {
2070 return LPUART_DmaPowerControl(state, &LPUART2_DmaDriverState);
2071 }
2072
LPUART2_DmaSend(const void * data,uint32_t num)2073 static int32_t LPUART2_DmaSend(const void *data, uint32_t num)
2074 {
2075 return LPUART_DmaSend(data, num, &LPUART2_DmaDriverState);
2076 }
2077
LPUART2_DmaReceive(void * data,uint32_t num)2078 static int32_t LPUART2_DmaReceive(void *data, uint32_t num)
2079 {
2080 return LPUART_DmaReceive(data, num, &LPUART2_DmaDriverState);
2081 }
2082
LPUART2_DmaTransfer(const void * data_out,void * data_in,uint32_t num)2083 static int32_t LPUART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
2084 {
2085 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART2_DmaDriverState);
2086 }
2087
LPUART2_DmaGetTxCount(void)2088 static uint32_t LPUART2_DmaGetTxCount(void)
2089 {
2090 return LPUART_DmaGetTxCount(&LPUART2_DmaDriverState);
2091 }
2092
LPUART2_DmaGetRxCount(void)2093 static uint32_t LPUART2_DmaGetRxCount(void)
2094 {
2095 return LPUART_DmaGetRxCount(&LPUART2_DmaDriverState);
2096 }
2097
LPUART2_DmaControl(uint32_t control,uint32_t arg)2098 static int32_t LPUART2_DmaControl(uint32_t control, uint32_t arg)
2099 {
2100 return LPUART_DmaControl(control, arg, &LPUART2_DmaDriverState);
2101 }
2102
LPUART2_DmaGetStatus(void)2103 static ARM_USART_STATUS LPUART2_DmaGetStatus(void)
2104 {
2105 return LPUART_DmaGetStatus(&LPUART2_DmaDriverState);
2106 }
2107
2108 #endif
2109
2110 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2111
2112 static cmsis_lpuart_edma_resource_t LPUART2_EdmaResource = {
2113 RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_PERI_SEL,
2114 RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_PERI_SEL,
2115
2116 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2117 RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_RX_DMAMUX_BASE,
2118 #endif
2119 };
2120
2121 static lpuart_edma_handle_t LPUART2_EdmaHandle;
2122 static edma_handle_t LPUART2_EdmaRxHandle;
2123 static edma_handle_t LPUART2_EdmaTxHandle;
2124
2125 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2126 ARMCC_SECTION("lpuart2_edma_driver_state")
2127 static cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = {
2128 #else
2129 static cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = {
2130 #endif
2131 &LPUART2_Resource, &LPUART2_EdmaResource, &LPUART2_EdmaHandle, &LPUART2_EdmaRxHandle, &LPUART2_EdmaTxHandle,
2132 };
2133
LPUART2_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)2134 static int32_t LPUART2_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
2135 {
2136 #ifdef RTE_USART2_PIN_INIT
2137 RTE_USART2_PIN_INIT();
2138 #endif
2139 return LPUART_EdmaInitialize(cb_event, &LPUART2_EdmaDriverState);
2140 }
2141
LPUART2_EdmaUninitialize(void)2142 static int32_t LPUART2_EdmaUninitialize(void)
2143 {
2144 #ifdef RTE_USART2_PIN_DEINIT
2145 RTE_USART2_PIN_DEINIT();
2146 #endif
2147 return LPUART_EdmaUninitialize(&LPUART2_EdmaDriverState);
2148 }
2149
LPUART2_EdmaPowerControl(ARM_POWER_STATE state)2150 static int32_t LPUART2_EdmaPowerControl(ARM_POWER_STATE state)
2151 {
2152 return LPUART_EdmaPowerControl(state, &LPUART2_EdmaDriverState);
2153 }
2154
LPUART2_EdmaSend(const void * data,uint32_t num)2155 static int32_t LPUART2_EdmaSend(const void *data, uint32_t num)
2156 {
2157 return LPUART_EdmaSend(data, num, &LPUART2_EdmaDriverState);
2158 }
2159
LPUART2_EdmaReceive(void * data,uint32_t num)2160 static int32_t LPUART2_EdmaReceive(void *data, uint32_t num)
2161 {
2162 return LPUART_EdmaReceive(data, num, &LPUART2_EdmaDriverState);
2163 }
2164
LPUART2_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2165 static int32_t LPUART2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2166 {
2167 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART2_EdmaDriverState);
2168 }
2169
LPUART2_EdmaGetTxCount(void)2170 static uint32_t LPUART2_EdmaGetTxCount(void)
2171 {
2172 return LPUART_EdmaGetTxCount(&LPUART2_EdmaDriverState);
2173 }
2174
LPUART2_EdmaGetRxCount(void)2175 static uint32_t LPUART2_EdmaGetRxCount(void)
2176 {
2177 return LPUART_EdmaGetRxCount(&LPUART2_EdmaDriverState);
2178 }
2179
LPUART2_EdmaControl(uint32_t control,uint32_t arg)2180 static int32_t LPUART2_EdmaControl(uint32_t control, uint32_t arg)
2181 {
2182 return LPUART_EdmaControl(control, arg, &LPUART2_EdmaDriverState);
2183 }
2184
LPUART2_EdmaGetStatus(void)2185 static ARM_USART_STATUS LPUART2_EdmaGetStatus(void)
2186 {
2187 return LPUART_EdmaGetStatus(&LPUART2_EdmaDriverState);
2188 }
2189
2190 #endif
2191
2192 #else
2193
2194 static lpuart_handle_t LPUART2_Handle;
2195
2196 #if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
2197 static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN];
2198 #endif
2199
2200 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2201 ARMCC_SECTION("lpuart2_non_blocking_driver_state")
2202 static cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = {
2203 #else
2204 static cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = {
2205 #endif
2206 &LPUART2_Resource,
2207 &LPUART2_Handle,
2208 };
2209
LPUART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)2210 static int32_t LPUART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
2211 {
2212 #ifdef RTE_USART2_PIN_INIT
2213 RTE_USART2_PIN_INIT();
2214 #endif
2215 return LPUART_NonBlockingInitialize(cb_event, &LPUART2_NonBlockingDriverState);
2216 }
2217
LPUART2_NonBlockingUninitialize(void)2218 static int32_t LPUART2_NonBlockingUninitialize(void)
2219 {
2220 #ifdef RTE_USART2_PIN_DEINIT
2221 RTE_USART2_PIN_DEINIT();
2222 #endif
2223 return LPUART_NonBlockingUninitialize(&LPUART2_NonBlockingDriverState);
2224 }
2225
LPUART2_NonBlockingPowerControl(ARM_POWER_STATE state)2226 static int32_t LPUART2_NonBlockingPowerControl(ARM_POWER_STATE state)
2227 {
2228 int32_t result;
2229
2230 result = LPUART_NonBlockingPowerControl(state, &LPUART2_NonBlockingDriverState);
2231
2232 #if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
2233 if ((state == ARM_POWER_FULL) && (LPUART2_NonBlockingDriverState.handle->rxRingBuffer == NULL))
2234 {
2235 LPUART_TransferStartRingBuffer(LPUART2_NonBlockingDriverState.resource->base,
2236 LPUART2_NonBlockingDriverState.handle, lpuart2_rxRingBuffer,
2237 USART_RX_BUFFER_LEN);
2238 }
2239 #endif
2240
2241 return result;
2242 }
2243
LPUART2_NonBlockingSend(const void * data,uint32_t num)2244 static int32_t LPUART2_NonBlockingSend(const void *data, uint32_t num)
2245 {
2246 return LPUART_NonBlockingSend(data, num, &LPUART2_NonBlockingDriverState);
2247 }
2248
LPUART2_NonBlockingReceive(void * data,uint32_t num)2249 static int32_t LPUART2_NonBlockingReceive(void *data, uint32_t num)
2250 {
2251 return LPUART_NonBlockingReceive(data, num, &LPUART2_NonBlockingDriverState);
2252 }
2253
LPUART2_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)2254 static int32_t LPUART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
2255 {
2256 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART2_NonBlockingDriverState);
2257 }
2258
LPUART2_NonBlockingGetTxCount(void)2259 static uint32_t LPUART2_NonBlockingGetTxCount(void)
2260 {
2261 return LPUART_NonBlockingGetTxCount(&LPUART2_NonBlockingDriverState);
2262 }
2263
LPUART2_NonBlockingGetRxCount(void)2264 static uint32_t LPUART2_NonBlockingGetRxCount(void)
2265 {
2266 return LPUART_NonBlockingGetRxCount(&LPUART2_NonBlockingDriverState);
2267 }
2268
LPUART2_NonBlockingControl(uint32_t control,uint32_t arg)2269 static int32_t LPUART2_NonBlockingControl(uint32_t control, uint32_t arg)
2270 {
2271 int32_t result;
2272
2273 result = LPUART_NonBlockingControl(control, arg, &LPUART2_NonBlockingDriverState);
2274 if (ARM_DRIVER_OK != result)
2275 {
2276 return result;
2277 }
2278
2279 /* Enable the receive interrupts if ring buffer is used */
2280 if (LPUART2_NonBlockingDriverState.handle->rxRingBuffer != NULL)
2281 {
2282 LPUART_EnableInterrupts(
2283 LPUART2_NonBlockingDriverState.resource->base,
2284 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
2285 }
2286
2287 return ARM_DRIVER_OK;
2288 }
2289
LPUART2_NonBlockingGetStatus(void)2290 static ARM_USART_STATUS LPUART2_NonBlockingGetStatus(void)
2291 {
2292 return LPUART_NonBlockingGetStatus(&LPUART2_NonBlockingDriverState);
2293 }
2294
2295 #endif
2296
2297 ARM_DRIVER_USART Driver_USART2 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
2298 #if defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN
2299 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2300 LPUART2_EdmaInitialize, LPUART2_EdmaUninitialize, LPUART2_EdmaPowerControl,
2301 LPUART2_EdmaSend, LPUART2_EdmaReceive, LPUART2_EdmaTransfer,
2302 LPUART2_EdmaGetTxCount, LPUART2_EdmaGetRxCount, LPUART2_EdmaControl,
2303 LPUART2_EdmaGetStatus,
2304 #else
2305 LPUART2_DmaInitialize, LPUART2_DmaUninitialize, LPUART2_DmaPowerControl,
2306 LPUART2_DmaSend, LPUART2_DmaReceive, LPUART2_DmaTransfer,
2307 LPUART2_DmaGetTxCount, LPUART2_DmaGetRxCount, LPUART2_DmaControl,
2308 LPUART2_DmaGetStatus,
2309 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2310 #else
2311 LPUART2_NonBlockingInitialize,
2312 LPUART2_NonBlockingUninitialize,
2313 LPUART2_NonBlockingPowerControl,
2314 LPUART2_NonBlockingSend,
2315 LPUART2_NonBlockingReceive,
2316 LPUART2_NonBlockingTransfer,
2317 LPUART2_NonBlockingGetTxCount,
2318 LPUART2_NonBlockingGetRxCount,
2319 LPUART2_NonBlockingControl,
2320 LPUART2_NonBlockingGetStatus,
2321 #endif /* RTE_USART2_DMA_EN */
2322 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
2323
2324 #endif /* LPUART2 */
2325
2326 #if defined(LPUART3) && defined(RTE_USART3) && RTE_USART3
2327
2328 /* User needs to provide the implementation for LPUART3_GetFreq/InitPins/DeinitPins
2329 in the application for enabling according instance. */
2330 extern uint32_t LPUART3_GetFreq(void);
2331
2332 static cmsis_lpuart_resource_t LPUART3_Resource = {LPUART3, LPUART3_GetFreq};
2333
2334 #if defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN
2335
2336 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2337
2338 static cmsis_lpuart_dma_resource_t LPUART3_DmaResource = {
2339 RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_PERI_SEL,
2340 RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_PERI_SEL,
2341
2342 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2343 RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_RX_DMAMUX_BASE,
2344 #endif
2345 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
2346 RTE_USART3_DMAMUX_TX_CH, RTE_USART3_DMAMUX_RX_CH
2347 #endif
2348 };
2349
2350 static lpuart_dma_handle_t LPUART3_DmaHandle;
2351 static dma_handle_t LPUART3_DmaRxHandle;
2352 static dma_handle_t LPUART3_DmaTxHandle;
2353
2354 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2355 ARMCC_SECTION("lpuart3_dma_driver_state")
2356 static cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = {
2357 #else
2358 static cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = {
2359 #endif
2360 &LPUART3_Resource, &LPUART3_DmaResource, &LPUART3_DmaHandle, &LPUART3_DmaRxHandle, &LPUART3_DmaTxHandle,
2361 };
2362
LPUART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event)2363 static int32_t LPUART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
2364 {
2365 #ifdef RTE_USART3_PIN_INIT
2366 RTE_USART3_PIN_INIT();
2367 #endif
2368 return LPUART_DmaInitialize(cb_event, &LPUART3_DmaDriverState);
2369 }
2370
LPUART3_DmaUninitialize(void)2371 static int32_t LPUART3_DmaUninitialize(void)
2372 {
2373 #ifdef RTE_USART3_PIN_DEINIT
2374 RTE_USART3_PIN_DEINIT();
2375 #endif
2376 return LPUART_DmaUninitialize(&LPUART3_DmaDriverState);
2377 }
2378
LPUART3_DmaPowerControl(ARM_POWER_STATE state)2379 static int32_t LPUART3_DmaPowerControl(ARM_POWER_STATE state)
2380 {
2381 return LPUART_DmaPowerControl(state, &LPUART3_DmaDriverState);
2382 }
2383
LPUART3_DmaSend(const void * data,uint32_t num)2384 static int32_t LPUART3_DmaSend(const void *data, uint32_t num)
2385 {
2386 return LPUART_DmaSend(data, num, &LPUART3_DmaDriverState);
2387 }
2388
LPUART3_DmaReceive(void * data,uint32_t num)2389 static int32_t LPUART3_DmaReceive(void *data, uint32_t num)
2390 {
2391 return LPUART_DmaReceive(data, num, &LPUART3_DmaDriverState);
2392 }
2393
LPUART3_DmaTransfer(const void * data_out,void * data_in,uint32_t num)2394 static int32_t LPUART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
2395 {
2396 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART3_DmaDriverState);
2397 }
2398
LPUART3_DmaGetTxCount(void)2399 static uint32_t LPUART3_DmaGetTxCount(void)
2400 {
2401 return LPUART_DmaGetTxCount(&LPUART3_DmaDriverState);
2402 }
2403
LPUART3_DmaGetRxCount(void)2404 static uint32_t LPUART3_DmaGetRxCount(void)
2405 {
2406 return LPUART_DmaGetRxCount(&LPUART3_DmaDriverState);
2407 }
2408
LPUART3_DmaControl(uint32_t control,uint32_t arg)2409 static int32_t LPUART3_DmaControl(uint32_t control, uint32_t arg)
2410 {
2411 return LPUART_DmaControl(control, arg, &LPUART3_DmaDriverState);
2412 }
2413
LPUART3_DmaGetStatus(void)2414 static ARM_USART_STATUS LPUART3_DmaGetStatus(void)
2415 {
2416 return LPUART_DmaGetStatus(&LPUART3_DmaDriverState);
2417 }
2418
2419 #endif
2420
2421 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2422
2423 static cmsis_lpuart_edma_resource_t LPUART3_EdmaResource = {
2424 RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_PERI_SEL,
2425 RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_PERI_SEL,
2426
2427 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2428 RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_RX_DMAMUX_BASE,
2429 #endif
2430 };
2431
2432 static lpuart_edma_handle_t LPUART3_EdmaHandle;
2433 static edma_handle_t LPUART3_EdmaRxHandle;
2434 static edma_handle_t LPUART3_EdmaTxHandle;
2435
2436 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2437 ARMCC_SECTION("lpuart3_edma_driver_state")
2438 static cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = {
2439 #else
2440 static cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = {
2441 #endif
2442 &LPUART3_Resource, &LPUART3_EdmaResource, &LPUART3_EdmaHandle, &LPUART3_EdmaRxHandle, &LPUART3_EdmaTxHandle,
2443 };
2444
LPUART3_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)2445 static int32_t LPUART3_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
2446 {
2447 #ifdef RTE_USART3_PIN_INIT
2448 RTE_USART3_PIN_INIT();
2449 #endif
2450 return LPUART_EdmaInitialize(cb_event, &LPUART3_EdmaDriverState);
2451 }
2452
LPUART3_EdmaUninitialize(void)2453 static int32_t LPUART3_EdmaUninitialize(void)
2454 {
2455 #ifdef RTE_USART3_PIN_DEINIT
2456 RTE_USART3_PIN_DEINIT();
2457 #endif
2458 return LPUART_EdmaUninitialize(&LPUART3_EdmaDriverState);
2459 }
2460
LPUART3_EdmaPowerControl(ARM_POWER_STATE state)2461 static int32_t LPUART3_EdmaPowerControl(ARM_POWER_STATE state)
2462 {
2463 return LPUART_EdmaPowerControl(state, &LPUART3_EdmaDriverState);
2464 }
2465
LPUART3_EdmaSend(const void * data,uint32_t num)2466 static int32_t LPUART3_EdmaSend(const void *data, uint32_t num)
2467 {
2468 return LPUART_EdmaSend(data, num, &LPUART3_EdmaDriverState);
2469 }
2470
LPUART3_EdmaReceive(void * data,uint32_t num)2471 static int32_t LPUART3_EdmaReceive(void *data, uint32_t num)
2472 {
2473 return LPUART_EdmaReceive(data, num, &LPUART3_EdmaDriverState);
2474 }
2475
LPUART3_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2476 static int32_t LPUART3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2477 {
2478 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART3_EdmaDriverState);
2479 }
2480
LPUART3_EdmaGetTxCount(void)2481 static uint32_t LPUART3_EdmaGetTxCount(void)
2482 {
2483 return LPUART_EdmaGetTxCount(&LPUART3_EdmaDriverState);
2484 }
2485
LPUART3_EdmaGetRxCount(void)2486 static uint32_t LPUART3_EdmaGetRxCount(void)
2487 {
2488 return LPUART_EdmaGetRxCount(&LPUART3_EdmaDriverState);
2489 }
2490
LPUART3_EdmaControl(uint32_t control,uint32_t arg)2491 static int32_t LPUART3_EdmaControl(uint32_t control, uint32_t arg)
2492 {
2493 return LPUART_EdmaControl(control, arg, &LPUART3_EdmaDriverState);
2494 }
2495
LPUART3_EdmaGetStatus(void)2496 static ARM_USART_STATUS LPUART3_EdmaGetStatus(void)
2497 {
2498 return LPUART_EdmaGetStatus(&LPUART3_EdmaDriverState);
2499 }
2500
2501 #endif
2502
2503 #else
2504
2505 static lpuart_handle_t LPUART3_Handle;
2506
2507 #if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
2508 static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN];
2509 #endif
2510
2511 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2512 ARMCC_SECTION("lpuart3_non_blocking_driver_state")
2513 static cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = {
2514 #else
2515 static cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = {
2516 #endif
2517 &LPUART3_Resource,
2518 &LPUART3_Handle,
2519 };
2520
LPUART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)2521 static int32_t LPUART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
2522 {
2523 #ifdef RTE_USART3_PIN_INIT
2524 RTE_USART3_PIN_INIT();
2525 #endif
2526 return LPUART_NonBlockingInitialize(cb_event, &LPUART3_NonBlockingDriverState);
2527 }
2528
LPUART3_NonBlockingUninitialize(void)2529 static int32_t LPUART3_NonBlockingUninitialize(void)
2530 {
2531 #ifdef RTE_USART3_PIN_DEINIT
2532 RTE_USART3_PIN_DEINIT();
2533 #endif
2534 return LPUART_NonBlockingUninitialize(&LPUART3_NonBlockingDriverState);
2535 }
2536
LPUART3_NonBlockingPowerControl(ARM_POWER_STATE state)2537 static int32_t LPUART3_NonBlockingPowerControl(ARM_POWER_STATE state)
2538 {
2539 int32_t result;
2540
2541 result = LPUART_NonBlockingPowerControl(state, &LPUART3_NonBlockingDriverState);
2542
2543 #if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
2544 if ((state == ARM_POWER_FULL) && (LPUART3_NonBlockingDriverState.handle->rxRingBuffer == NULL))
2545 {
2546 LPUART_TransferStartRingBuffer(LPUART3_NonBlockingDriverState.resource->base,
2547 LPUART3_NonBlockingDriverState.handle, lpuart3_rxRingBuffer,
2548 USART_RX_BUFFER_LEN);
2549 }
2550 #endif
2551
2552 return result;
2553 }
2554
LPUART3_NonBlockingSend(const void * data,uint32_t num)2555 static int32_t LPUART3_NonBlockingSend(const void *data, uint32_t num)
2556 {
2557 return LPUART_NonBlockingSend(data, num, &LPUART3_NonBlockingDriverState);
2558 }
2559
LPUART3_NonBlockingReceive(void * data,uint32_t num)2560 static int32_t LPUART3_NonBlockingReceive(void *data, uint32_t num)
2561 {
2562 return LPUART_NonBlockingReceive(data, num, &LPUART3_NonBlockingDriverState);
2563 }
2564
LPUART3_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)2565 static int32_t LPUART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
2566 {
2567 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART3_NonBlockingDriverState);
2568 }
2569
LPUART3_NonBlockingGetTxCount(void)2570 static uint32_t LPUART3_NonBlockingGetTxCount(void)
2571 {
2572 return LPUART_NonBlockingGetTxCount(&LPUART3_NonBlockingDriverState);
2573 }
2574
LPUART3_NonBlockingGetRxCount(void)2575 static uint32_t LPUART3_NonBlockingGetRxCount(void)
2576 {
2577 return LPUART_NonBlockingGetRxCount(&LPUART3_NonBlockingDriverState);
2578 }
2579
LPUART3_NonBlockingControl(uint32_t control,uint32_t arg)2580 static int32_t LPUART3_NonBlockingControl(uint32_t control, uint32_t arg)
2581 {
2582 int32_t result;
2583
2584 result = LPUART_NonBlockingControl(control, arg, &LPUART3_NonBlockingDriverState);
2585 if (ARM_DRIVER_OK != result)
2586 {
2587 return result;
2588 }
2589
2590 /* Enable the receive interrupts if ring buffer is used */
2591 if (LPUART3_NonBlockingDriverState.handle->rxRingBuffer != NULL)
2592 {
2593 LPUART_EnableInterrupts(
2594 LPUART3_NonBlockingDriverState.resource->base,
2595 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
2596 }
2597
2598 return ARM_DRIVER_OK;
2599 }
2600
LPUART3_NonBlockingGetStatus(void)2601 static ARM_USART_STATUS LPUART3_NonBlockingGetStatus(void)
2602 {
2603 return LPUART_NonBlockingGetStatus(&LPUART3_NonBlockingDriverState);
2604 }
2605
2606 #endif
2607
2608 ARM_DRIVER_USART Driver_USART3 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
2609 #if defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN
2610 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2611 LPUART3_EdmaInitialize, LPUART3_EdmaUninitialize, LPUART3_EdmaPowerControl,
2612 LPUART3_EdmaSend, LPUART3_EdmaReceive, LPUART3_EdmaTransfer,
2613 LPUART3_EdmaGetTxCount, LPUART3_EdmaGetRxCount, LPUART3_EdmaControl,
2614 LPUART3_EdmaGetStatus,
2615 #else
2616 LPUART3_DmaInitialize, LPUART3_DmaUninitialize, LPUART3_DmaPowerControl,
2617 LPUART3_DmaSend, LPUART3_DmaReceive, LPUART3_DmaTransfer,
2618 LPUART3_DmaGetTxCount, LPUART3_DmaGetRxCount, LPUART3_DmaControl,
2619 LPUART3_DmaGetStatus,
2620 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2621 #else
2622 LPUART3_NonBlockingInitialize,
2623 LPUART3_NonBlockingUninitialize,
2624 LPUART3_NonBlockingPowerControl,
2625 LPUART3_NonBlockingSend,
2626 LPUART3_NonBlockingReceive,
2627 LPUART3_NonBlockingTransfer,
2628 LPUART3_NonBlockingGetTxCount,
2629 LPUART3_NonBlockingGetRxCount,
2630 LPUART3_NonBlockingControl,
2631 LPUART3_NonBlockingGetStatus,
2632 #endif /* RTE_USART3_DMA_EN */
2633 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
2634
2635 #endif /* LPUART3 */
2636
2637 #if defined(LPUART4) && defined(RTE_USART4) && RTE_USART4
2638
2639 /* User needs to provide the implementation for LPUART4_GetFreq/InitPins/DeinitPins
2640 in the application for enabling according instance. */
2641 extern uint32_t LPUART4_GetFreq(void);
2642
2643 static cmsis_lpuart_resource_t LPUART4_Resource = {LPUART4, LPUART4_GetFreq};
2644
2645 #if defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN
2646
2647 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2648
2649 static cmsis_lpuart_dma_resource_t LPUART4_DmaResource = {
2650 RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_PERI_SEL,
2651 RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_PERI_SEL,
2652
2653 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2654 RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_RX_DMAMUX_BASE,
2655 #endif
2656 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
2657 RTE_USART4_DMAMUX_TX_CH, RTE_USART4_DMAMUX_RX_CH
2658 #endif
2659 };
2660
2661 static lpuart_dma_handle_t LPUART4_DmaHandle;
2662 static dma_handle_t LPUART4_DmaRxHandle;
2663 static dma_handle_t LPUART4_DmaTxHandle;
2664
2665 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2666 ARMCC_SECTION("lpuart4_dma_driver_state")
2667 static cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = {
2668 #else
2669 static cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = {
2670 #endif
2671 &LPUART4_Resource, &LPUART4_DmaResource, &LPUART4_DmaHandle, &LPUART4_DmaRxHandle, &LPUART4_DmaTxHandle,
2672 };
2673
LPUART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event)2674 static int32_t LPUART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
2675 {
2676 #ifdef RTE_USART4_PIN_INIT
2677 RTE_USART4_PIN_INIT();
2678 #endif
2679 return LPUART_DmaInitialize(cb_event, &LPUART4_DmaDriverState);
2680 }
2681
LPUART4_DmaUninitialize(void)2682 static int32_t LPUART4_DmaUninitialize(void)
2683 {
2684 #ifdef RTE_USART4_PIN_DEINIT
2685 RTE_USART4_PIN_DEINIT();
2686 #endif
2687 return LPUART_DmaUninitialize(&LPUART4_DmaDriverState);
2688 }
2689
LPUART4_DmaPowerControl(ARM_POWER_STATE state)2690 static int32_t LPUART4_DmaPowerControl(ARM_POWER_STATE state)
2691 {
2692 return LPUART_DmaPowerControl(state, &LPUART4_DmaDriverState);
2693 }
2694
LPUART4_DmaSend(const void * data,uint32_t num)2695 static int32_t LPUART4_DmaSend(const void *data, uint32_t num)
2696 {
2697 return LPUART_DmaSend(data, num, &LPUART4_DmaDriverState);
2698 }
2699
LPUART4_DmaReceive(void * data,uint32_t num)2700 static int32_t LPUART4_DmaReceive(void *data, uint32_t num)
2701 {
2702 return LPUART_DmaReceive(data, num, &LPUART4_DmaDriverState);
2703 }
2704
LPUART4_DmaTransfer(const void * data_out,void * data_in,uint32_t num)2705 static int32_t LPUART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
2706 {
2707 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART4_DmaDriverState);
2708 }
2709
LPUART4_DmaGetTxCount(void)2710 static uint32_t LPUART4_DmaGetTxCount(void)
2711 {
2712 return LPUART_DmaGetTxCount(&LPUART4_DmaDriverState);
2713 }
2714
LPUART4_DmaGetRxCount(void)2715 static uint32_t LPUART4_DmaGetRxCount(void)
2716 {
2717 return LPUART_DmaGetRxCount(&LPUART4_DmaDriverState);
2718 }
2719
LPUART4_DmaControl(uint32_t control,uint32_t arg)2720 static int32_t LPUART4_DmaControl(uint32_t control, uint32_t arg)
2721 {
2722 return LPUART_DmaControl(control, arg, &LPUART4_DmaDriverState);
2723 }
2724
LPUART4_DmaGetStatus(void)2725 static ARM_USART_STATUS LPUART4_DmaGetStatus(void)
2726 {
2727 return LPUART_DmaGetStatus(&LPUART4_DmaDriverState);
2728 }
2729
2730 #endif
2731
2732 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2733
2734 static cmsis_lpuart_edma_resource_t LPUART4_EdmaResource = {
2735 RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_PERI_SEL,
2736 RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_PERI_SEL,
2737
2738 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2739 RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_RX_DMAMUX_BASE,
2740 #endif
2741 };
2742
2743 static lpuart_edma_handle_t LPUART4_EdmaHandle;
2744 static edma_handle_t LPUART4_EdmaRxHandle;
2745 static edma_handle_t LPUART4_EdmaTxHandle;
2746
2747 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2748 ARMCC_SECTION("lpuart4_edma_driver_state")
2749 static cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = {
2750 #else
2751 static cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = {
2752 #endif
2753 &LPUART4_Resource, &LPUART4_EdmaResource, &LPUART4_EdmaHandle, &LPUART4_EdmaRxHandle, &LPUART4_EdmaTxHandle,
2754 };
2755
LPUART4_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)2756 static int32_t LPUART4_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
2757 {
2758 #ifdef RTE_USART4_PIN_INIT
2759 RTE_USART4_PIN_INIT();
2760 #endif
2761 return LPUART_EdmaInitialize(cb_event, &LPUART4_EdmaDriverState);
2762 }
2763
LPUART4_EdmaUninitialize(void)2764 static int32_t LPUART4_EdmaUninitialize(void)
2765 {
2766 #ifdef RTE_USART4_PIN_DEINIT
2767 RTE_USART4_PIN_DEINIT();
2768 #endif
2769 return LPUART_EdmaUninitialize(&LPUART4_EdmaDriverState);
2770 }
2771
LPUART4_EdmaPowerControl(ARM_POWER_STATE state)2772 static int32_t LPUART4_EdmaPowerControl(ARM_POWER_STATE state)
2773 {
2774 return LPUART_EdmaPowerControl(state, &LPUART4_EdmaDriverState);
2775 }
2776
LPUART4_EdmaSend(const void * data,uint32_t num)2777 static int32_t LPUART4_EdmaSend(const void *data, uint32_t num)
2778 {
2779 return LPUART_EdmaSend(data, num, &LPUART4_EdmaDriverState);
2780 }
2781
LPUART4_EdmaReceive(void * data,uint32_t num)2782 static int32_t LPUART4_EdmaReceive(void *data, uint32_t num)
2783 {
2784 return LPUART_EdmaReceive(data, num, &LPUART4_EdmaDriverState);
2785 }
2786
LPUART4_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2787 static int32_t LPUART4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2788 {
2789 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART4_EdmaDriverState);
2790 }
2791
LPUART4_EdmaGetTxCount(void)2792 static uint32_t LPUART4_EdmaGetTxCount(void)
2793 {
2794 return LPUART_EdmaGetTxCount(&LPUART4_EdmaDriverState);
2795 }
2796
LPUART4_EdmaGetRxCount(void)2797 static uint32_t LPUART4_EdmaGetRxCount(void)
2798 {
2799 return LPUART_EdmaGetRxCount(&LPUART4_EdmaDriverState);
2800 }
2801
LPUART4_EdmaControl(uint32_t control,uint32_t arg)2802 static int32_t LPUART4_EdmaControl(uint32_t control, uint32_t arg)
2803 {
2804 return LPUART_EdmaControl(control, arg, &LPUART4_EdmaDriverState);
2805 }
2806
LPUART4_EdmaGetStatus(void)2807 static ARM_USART_STATUS LPUART4_EdmaGetStatus(void)
2808 {
2809 return LPUART_EdmaGetStatus(&LPUART4_EdmaDriverState);
2810 }
2811
2812 #endif
2813
2814 #else
2815
2816 static lpuart_handle_t LPUART4_Handle;
2817
2818 #if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
2819 static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN];
2820 #endif
2821
2822 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2823 ARMCC_SECTION("lpuart4_non_blocking_driver_state")
2824 static cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = {
2825 #else
2826 static cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = {
2827 #endif
2828 &LPUART4_Resource,
2829 &LPUART4_Handle,
2830 };
2831
LPUART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)2832 static int32_t LPUART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
2833 {
2834 #ifdef RTE_USART4_PIN_INIT
2835 RTE_USART4_PIN_INIT();
2836 #endif
2837 return LPUART_NonBlockingInitialize(cb_event, &LPUART4_NonBlockingDriverState);
2838 }
2839
LPUART4_NonBlockingUninitialize(void)2840 static int32_t LPUART4_NonBlockingUninitialize(void)
2841 {
2842 #ifdef RTE_USART4_PIN_DEINIT
2843 RTE_USART4_PIN_DEINIT();
2844 #endif
2845 return LPUART_NonBlockingUninitialize(&LPUART4_NonBlockingDriverState);
2846 }
2847
LPUART4_NonBlockingPowerControl(ARM_POWER_STATE state)2848 static int32_t LPUART4_NonBlockingPowerControl(ARM_POWER_STATE state)
2849 {
2850 int32_t result;
2851
2852 result = LPUART_NonBlockingPowerControl(state, &LPUART4_NonBlockingDriverState);
2853
2854 #if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
2855 if ((state == ARM_POWER_FULL) && (LPUART4_NonBlockingDriverState.handle->rxRingBuffer == NULL))
2856 {
2857 LPUART_TransferStartRingBuffer(LPUART4_NonBlockingDriverState.resource->base,
2858 LPUART4_NonBlockingDriverState.handle, lpuart4_rxRingBuffer,
2859 USART_RX_BUFFER_LEN);
2860 }
2861 #endif
2862
2863 return result;
2864 }
2865
LPUART4_NonBlockingSend(const void * data,uint32_t num)2866 static int32_t LPUART4_NonBlockingSend(const void *data, uint32_t num)
2867 {
2868 return LPUART_NonBlockingSend(data, num, &LPUART4_NonBlockingDriverState);
2869 }
2870
LPUART4_NonBlockingReceive(void * data,uint32_t num)2871 static int32_t LPUART4_NonBlockingReceive(void *data, uint32_t num)
2872 {
2873 return LPUART_NonBlockingReceive(data, num, &LPUART4_NonBlockingDriverState);
2874 }
2875
LPUART4_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)2876 static int32_t LPUART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
2877 {
2878 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART4_NonBlockingDriverState);
2879 }
2880
LPUART4_NonBlockingGetTxCount(void)2881 static uint32_t LPUART4_NonBlockingGetTxCount(void)
2882 {
2883 return LPUART_NonBlockingGetTxCount(&LPUART4_NonBlockingDriverState);
2884 }
2885
LPUART4_NonBlockingGetRxCount(void)2886 static uint32_t LPUART4_NonBlockingGetRxCount(void)
2887 {
2888 return LPUART_NonBlockingGetRxCount(&LPUART4_NonBlockingDriverState);
2889 }
2890
LPUART4_NonBlockingControl(uint32_t control,uint32_t arg)2891 static int32_t LPUART4_NonBlockingControl(uint32_t control, uint32_t arg)
2892 {
2893 int32_t result;
2894
2895 result = LPUART_NonBlockingControl(control, arg, &LPUART4_NonBlockingDriverState);
2896 if (ARM_DRIVER_OK != result)
2897 {
2898 return result;
2899 }
2900
2901 /* Enable the receive interrupts if ring buffer is used */
2902 if (LPUART4_NonBlockingDriverState.handle->rxRingBuffer != NULL)
2903 {
2904 LPUART_EnableInterrupts(
2905 LPUART4_NonBlockingDriverState.resource->base,
2906 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
2907 }
2908
2909 return ARM_DRIVER_OK;
2910 }
2911
LPUART4_NonBlockingGetStatus(void)2912 static ARM_USART_STATUS LPUART4_NonBlockingGetStatus(void)
2913 {
2914 return LPUART_NonBlockingGetStatus(&LPUART4_NonBlockingDriverState);
2915 }
2916
2917 #endif
2918
2919 ARM_DRIVER_USART Driver_USART4 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
2920 #if defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN
2921 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2922 LPUART4_EdmaInitialize, LPUART4_EdmaUninitialize, LPUART4_EdmaPowerControl,
2923 LPUART4_EdmaSend, LPUART4_EdmaReceive, LPUART4_EdmaTransfer,
2924 LPUART4_EdmaGetTxCount, LPUART4_EdmaGetRxCount, LPUART4_EdmaControl,
2925 LPUART4_EdmaGetStatus,
2926 #else
2927 LPUART4_DmaInitialize, LPUART4_DmaUninitialize, LPUART4_DmaPowerControl,
2928 LPUART4_DmaSend, LPUART4_DmaReceive, LPUART4_DmaTransfer,
2929 LPUART4_DmaGetTxCount, LPUART4_DmaGetRxCount, LPUART4_DmaControl,
2930 LPUART4_DmaGetStatus,
2931 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2932 #else
2933 LPUART4_NonBlockingInitialize,
2934 LPUART4_NonBlockingUninitialize,
2935 LPUART4_NonBlockingPowerControl,
2936 LPUART4_NonBlockingSend,
2937 LPUART4_NonBlockingReceive,
2938 LPUART4_NonBlockingTransfer,
2939 LPUART4_NonBlockingGetTxCount,
2940 LPUART4_NonBlockingGetRxCount,
2941 LPUART4_NonBlockingControl,
2942 LPUART4_NonBlockingGetStatus,
2943 #endif /* RTE_USART4_DMA_EN */
2944 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
2945
2946 #endif /* LPUART4 */
2947
2948 #if defined(LPUART5) && defined(RTE_USART5) && RTE_USART5
2949
2950 /* User needs to provide the implementation for LPUART5_GetFreq/InitPins/DeinitPins
2951 in the application for enabling according instance. */
2952 extern uint32_t LPUART5_GetFreq(void);
2953
2954 static cmsis_lpuart_resource_t LPUART5_Resource = {LPUART5, LPUART5_GetFreq};
2955
2956 #if defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN
2957
2958 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2959
2960 static cmsis_lpuart_dma_resource_t LPUART5_DmaResource = {
2961 RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_PERI_SEL,
2962 RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_PERI_SEL,
2963
2964 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2965 RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_RX_DMAMUX_BASE,
2966 #endif
2967 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
2968 RTE_USART5_DMAMUX_TX_CH, RTE_USART5_DMAMUX_RX_CH
2969 #endif
2970 };
2971
2972 static lpuart_dma_handle_t LPUART5_DmaHandle;
2973 static dma_handle_t LPUART5_DmaRxHandle;
2974 static dma_handle_t LPUART5_DmaTxHandle;
2975
2976 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2977 ARMCC_SECTION("lpuart5_dma_driver_state")
2978 static cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = {
2979 #else
2980 static cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = {
2981 #endif
2982 &LPUART5_Resource, &LPUART5_DmaResource, &LPUART5_DmaHandle, &LPUART5_DmaRxHandle, &LPUART5_DmaTxHandle,
2983 };
2984
LPUART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event)2985 static int32_t LPUART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
2986 {
2987 #ifdef RTE_USART5_PIN_INIT
2988 RTE_USART5_PIN_INIT();
2989 #endif
2990 return LPUART_DmaInitialize(cb_event, &LPUART5_DmaDriverState);
2991 }
2992
LPUART5_DmaUninitialize(void)2993 static int32_t LPUART5_DmaUninitialize(void)
2994 {
2995 #ifdef RTE_USART5_PIN_DEINIT
2996 RTE_USART5_PIN_DEINIT();
2997 #endif
2998 return LPUART_DmaUninitialize(&LPUART5_DmaDriverState);
2999 }
3000
LPUART5_DmaPowerControl(ARM_POWER_STATE state)3001 static int32_t LPUART5_DmaPowerControl(ARM_POWER_STATE state)
3002 {
3003 return LPUART_DmaPowerControl(state, &LPUART5_DmaDriverState);
3004 }
3005
LPUART5_DmaSend(const void * data,uint32_t num)3006 static int32_t LPUART5_DmaSend(const void *data, uint32_t num)
3007 {
3008 return LPUART_DmaSend(data, num, &LPUART5_DmaDriverState);
3009 }
3010
LPUART5_DmaReceive(void * data,uint32_t num)3011 static int32_t LPUART5_DmaReceive(void *data, uint32_t num)
3012 {
3013 return LPUART_DmaReceive(data, num, &LPUART5_DmaDriverState);
3014 }
3015
LPUART5_DmaTransfer(const void * data_out,void * data_in,uint32_t num)3016 static int32_t LPUART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
3017 {
3018 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART5_DmaDriverState);
3019 }
3020
LPUART5_DmaGetTxCount(void)3021 static uint32_t LPUART5_DmaGetTxCount(void)
3022 {
3023 return LPUART_DmaGetTxCount(&LPUART5_DmaDriverState);
3024 }
3025
LPUART5_DmaGetRxCount(void)3026 static uint32_t LPUART5_DmaGetRxCount(void)
3027 {
3028 return LPUART_DmaGetRxCount(&LPUART5_DmaDriverState);
3029 }
3030
LPUART5_DmaControl(uint32_t control,uint32_t arg)3031 static int32_t LPUART5_DmaControl(uint32_t control, uint32_t arg)
3032 {
3033 return LPUART_DmaControl(control, arg, &LPUART5_DmaDriverState);
3034 }
3035
LPUART5_DmaGetStatus(void)3036 static ARM_USART_STATUS LPUART5_DmaGetStatus(void)
3037 {
3038 return LPUART_DmaGetStatus(&LPUART5_DmaDriverState);
3039 }
3040
3041 /* LPUART5 Driver Control Block */
3042
3043 #endif
3044
3045 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3046
3047 static cmsis_lpuart_edma_resource_t LPUART5_EdmaResource = {
3048 RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_PERI_SEL,
3049 RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_PERI_SEL,
3050
3051 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3052 RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_RX_DMAMUX_BASE,
3053 #endif
3054 };
3055
3056 static lpuart_edma_handle_t LPUART5_EdmaHandle;
3057 static edma_handle_t LPUART5_EdmaRxHandle;
3058 static edma_handle_t LPUART5_EdmaTxHandle;
3059
3060 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3061 ARMCC_SECTION("lpuart5_edma_driver_state")
3062 static cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = {
3063 #else
3064 static cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = {
3065 #endif
3066 &LPUART5_Resource, &LPUART5_EdmaResource, &LPUART5_EdmaHandle, &LPUART5_EdmaRxHandle, &LPUART5_EdmaTxHandle,
3067 };
3068
LPUART5_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)3069 static int32_t LPUART5_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
3070 {
3071 #ifdef RTE_USART5_PIN_INIT
3072 RTE_USART5_PIN_INIT();
3073 #endif
3074 return LPUART_EdmaInitialize(cb_event, &LPUART5_EdmaDriverState);
3075 }
3076
LPUART5_EdmaUninitialize(void)3077 static int32_t LPUART5_EdmaUninitialize(void)
3078 {
3079 #ifdef RTE_USART5_PIN_DEINIT
3080 RTE_USART5_PIN_DEINIT();
3081 #endif
3082 return LPUART_EdmaUninitialize(&LPUART5_EdmaDriverState);
3083 }
3084
LPUART5_EdmaPowerControl(ARM_POWER_STATE state)3085 static int32_t LPUART5_EdmaPowerControl(ARM_POWER_STATE state)
3086 {
3087 return LPUART_EdmaPowerControl(state, &LPUART5_EdmaDriverState);
3088 }
3089
LPUART5_EdmaSend(const void * data,uint32_t num)3090 static int32_t LPUART5_EdmaSend(const void *data, uint32_t num)
3091 {
3092 return LPUART_EdmaSend(data, num, &LPUART5_EdmaDriverState);
3093 }
3094
LPUART5_EdmaReceive(void * data,uint32_t num)3095 static int32_t LPUART5_EdmaReceive(void *data, uint32_t num)
3096 {
3097 return LPUART_EdmaReceive(data, num, &LPUART5_EdmaDriverState);
3098 }
3099
LPUART5_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3100 static int32_t LPUART5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3101 {
3102 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART5_EdmaDriverState);
3103 }
3104
LPUART5_EdmaGetTxCount(void)3105 static uint32_t LPUART5_EdmaGetTxCount(void)
3106 {
3107 return LPUART_EdmaGetTxCount(&LPUART5_EdmaDriverState);
3108 }
3109
LPUART5_EdmaGetRxCount(void)3110 static uint32_t LPUART5_EdmaGetRxCount(void)
3111 {
3112 return LPUART_EdmaGetRxCount(&LPUART5_EdmaDriverState);
3113 }
3114
LPUART5_EdmaControl(uint32_t control,uint32_t arg)3115 static int32_t LPUART5_EdmaControl(uint32_t control, uint32_t arg)
3116 {
3117 return LPUART_EdmaControl(control, arg, &LPUART5_EdmaDriverState);
3118 }
3119
LPUART5_EdmaGetStatus(void)3120 static ARM_USART_STATUS LPUART5_EdmaGetStatus(void)
3121 {
3122 return LPUART_EdmaGetStatus(&LPUART5_EdmaDriverState);
3123 }
3124
3125 #endif
3126
3127 #else
3128
3129 static lpuart_handle_t LPUART5_Handle;
3130
3131 #if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
3132 static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN];
3133 #endif
3134
3135 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3136 ARMCC_SECTION("lpuart5_non_blocking_driver_state")
3137 static cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = {
3138 #else
3139 static cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = {
3140 #endif
3141 &LPUART5_Resource,
3142 &LPUART5_Handle,
3143 };
3144
LPUART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)3145 static int32_t LPUART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
3146 {
3147 #ifdef RTE_USART5_PIN_INIT
3148 RTE_USART5_PIN_INIT();
3149 #endif
3150 return LPUART_NonBlockingInitialize(cb_event, &LPUART5_NonBlockingDriverState);
3151 }
3152
LPUART5_NonBlockingUninitialize(void)3153 static int32_t LPUART5_NonBlockingUninitialize(void)
3154 {
3155 #ifdef RTE_USART5_PIN_DEINIT
3156 RTE_USART5_PIN_DEINIT();
3157 #endif
3158 return LPUART_NonBlockingUninitialize(&LPUART5_NonBlockingDriverState);
3159 }
3160
LPUART5_NonBlockingPowerControl(ARM_POWER_STATE state)3161 static int32_t LPUART5_NonBlockingPowerControl(ARM_POWER_STATE state)
3162 {
3163 int32_t result;
3164
3165 result = LPUART_NonBlockingPowerControl(state, &LPUART5_NonBlockingDriverState);
3166
3167 #if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
3168 if ((state == ARM_POWER_FULL) && (LPUART5_NonBlockingDriverState.handle->rxRingBuffer == NULL))
3169 {
3170 LPUART_TransferStartRingBuffer(LPUART5_NonBlockingDriverState.resource->base,
3171 LPUART5_NonBlockingDriverState.handle, lpuart5_rxRingBuffer,
3172 USART_RX_BUFFER_LEN);
3173 }
3174 #endif
3175
3176 return result;
3177 }
3178
LPUART5_NonBlockingSend(const void * data,uint32_t num)3179 static int32_t LPUART5_NonBlockingSend(const void *data, uint32_t num)
3180 {
3181 return LPUART_NonBlockingSend(data, num, &LPUART5_NonBlockingDriverState);
3182 }
3183
LPUART5_NonBlockingReceive(void * data,uint32_t num)3184 static int32_t LPUART5_NonBlockingReceive(void *data, uint32_t num)
3185 {
3186 return LPUART_NonBlockingReceive(data, num, &LPUART5_NonBlockingDriverState);
3187 }
3188
LPUART5_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)3189 static int32_t LPUART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
3190 {
3191 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART5_NonBlockingDriverState);
3192 }
3193
LPUART5_NonBlockingGetTxCount(void)3194 static uint32_t LPUART5_NonBlockingGetTxCount(void)
3195 {
3196 return LPUART_NonBlockingGetTxCount(&LPUART5_NonBlockingDriverState);
3197 }
3198
LPUART5_NonBlockingGetRxCount(void)3199 static uint32_t LPUART5_NonBlockingGetRxCount(void)
3200 {
3201 return LPUART_NonBlockingGetRxCount(&LPUART5_NonBlockingDriverState);
3202 }
3203
LPUART5_NonBlockingControl(uint32_t control,uint32_t arg)3204 static int32_t LPUART5_NonBlockingControl(uint32_t control, uint32_t arg)
3205 {
3206 int32_t result;
3207
3208 result = LPUART_NonBlockingControl(control, arg, &LPUART5_NonBlockingDriverState);
3209 if (ARM_DRIVER_OK != result)
3210 {
3211 return result;
3212 }
3213
3214 /* Enable the receive interrupts if ring buffer is used */
3215 if (LPUART5_NonBlockingDriverState.handle->rxRingBuffer != NULL)
3216 {
3217 LPUART_EnableInterrupts(
3218 LPUART5_NonBlockingDriverState.resource->base,
3219 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
3220 }
3221
3222 return ARM_DRIVER_OK;
3223 }
3224
LPUART5_NonBlockingGetStatus(void)3225 static ARM_USART_STATUS LPUART5_NonBlockingGetStatus(void)
3226 {
3227 return LPUART_NonBlockingGetStatus(&LPUART5_NonBlockingDriverState);
3228 }
3229
3230 #endif
3231
3232 ARM_DRIVER_USART Driver_USART5 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
3233 #if defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN
3234 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3235 LPUART5_EdmaInitialize, LPUART5_EdmaUninitialize, LPUART5_EdmaPowerControl,
3236 LPUART5_EdmaSend, LPUART5_EdmaReceive, LPUART5_EdmaTransfer,
3237 LPUART5_EdmaGetTxCount, LPUART5_EdmaGetRxCount, LPUART5_EdmaControl,
3238 LPUART5_EdmaGetStatus,
3239 #else
3240 LPUART5_DmaInitialize, LPUART5_DmaUninitialize, LPUART5_DmaPowerControl,
3241 LPUART5_DmaSend, LPUART5_DmaReceive, LPUART5_DmaTransfer,
3242 LPUART5_DmaGetTxCount, LPUART5_DmaGetRxCount, LPUART5_DmaControl,
3243 LPUART5_DmaGetStatus,
3244 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
3245 #else
3246 LPUART5_NonBlockingInitialize,
3247 LPUART5_NonBlockingUninitialize,
3248 LPUART5_NonBlockingPowerControl,
3249 LPUART5_NonBlockingSend,
3250 LPUART5_NonBlockingReceive,
3251 LPUART5_NonBlockingTransfer,
3252 LPUART5_NonBlockingGetTxCount,
3253 LPUART5_NonBlockingGetRxCount,
3254 LPUART5_NonBlockingControl,
3255 LPUART5_NonBlockingGetStatus,
3256 #endif /* RTE_USART5_DMA_EN */
3257 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
3258
3259 #endif /* LPUART5 */
3260
3261 #if defined(LPUART6) && defined(RTE_USART6) && RTE_USART6
3262
3263 /* User needs to provide the implementation for LPUART6_GetFreq/InitPins/DeinitPins
3264 in the application for enabling according instance. */
3265 extern uint32_t LPUART6_GetFreq(void);
3266
3267 static cmsis_lpuart_resource_t LPUART6_Resource = {LPUART6, LPUART6_GetFreq};
3268
3269 #if defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN
3270
3271 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3272
3273 static cmsis_lpuart_dma_resource_t LPUART6_DmaResource = {
3274 RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_TX_PERI_SEL,
3275 RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, RTE_USART6_DMA_RX_PERI_SEL,
3276
3277 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3278 RTE_USART6_DMA_TX_DMAMUX_BASE, RTE_USART6_DMA_RX_DMAMUX_BASE,
3279 #endif
3280 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
3281 RTE_USART6_DMAMUX_TX_CH, RTE_USART6_DMAMUX_RX_CH
3282 #endif
3283 };
3284
3285 static lpuart_dma_handle_t LPUART6_DmaHandle;
3286 static dma_handle_t LPUART6_DmaRxHandle;
3287 static dma_handle_t LPUART6_DmaTxHandle;
3288
3289 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3290 ARMCC_SECTION("lpuart6_dma_driver_state")
3291 static cmsis_lpuart_dma_driver_state_t LPUART6_DmaDriverState = {
3292 #else
3293 static cmsis_lpuart_dma_driver_state_t LPUART6_DmaDriverState = {
3294 #endif
3295 &LPUART6_Resource, &LPUART6_DmaResource, &LPUART6_DmaHandle, &LPUART6_DmaRxHandle, &LPUART6_DmaTxHandle,
3296 };
3297
LPUART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event)3298 static int32_t LPUART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
3299 {
3300 #ifdef RTE_USART6_PIN_INIT
3301 RTE_USART6_PIN_INIT();
3302 #endif
3303 return LPUART_DmaInitialize(cb_event, &LPUART6_DmaDriverState);
3304 }
3305
LPUART6_DmaUninitialize(void)3306 static int32_t LPUART6_DmaUninitialize(void)
3307 {
3308 #ifdef RTE_USART6_PIN_DEINIT
3309 RTE_USART6_PIN_DEINIT();
3310 #endif
3311 return LPUART_DmaUninitialize(&LPUART6_DmaDriverState);
3312 }
3313
LPUART6_DmaPowerControl(ARM_POWER_STATE state)3314 static int32_t LPUART6_DmaPowerControl(ARM_POWER_STATE state)
3315 {
3316 return LPUART_DmaPowerControl(state, &LPUART6_DmaDriverState);
3317 }
3318
LPUART6_DmaSend(const void * data,uint32_t num)3319 static int32_t LPUART6_DmaSend(const void *data, uint32_t num)
3320 {
3321 return LPUART_DmaSend(data, num, &LPUART6_DmaDriverState);
3322 }
3323
LPUART6_DmaReceive(void * data,uint32_t num)3324 static int32_t LPUART6_DmaReceive(void *data, uint32_t num)
3325 {
3326 return LPUART_DmaReceive(data, num, &LPUART6_DmaDriverState);
3327 }
3328
LPUART6_DmaTransfer(const void * data_out,void * data_in,uint32_t num)3329 static int32_t LPUART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
3330 {
3331 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART6_DmaDriverState);
3332 }
3333
LPUART6_DmaGetTxCount(void)3334 static uint32_t LPUART6_DmaGetTxCount(void)
3335 {
3336 return LPUART_DmaGetTxCount(&LPUART6_DmaDriverState);
3337 }
3338
LPUART6_DmaGetRxCount(void)3339 static uint32_t LPUART6_DmaGetRxCount(void)
3340 {
3341 return LPUART_DmaGetRxCount(&LPUART6_DmaDriverState);
3342 }
3343
LPUART6_DmaControl(uint32_t control,uint32_t arg)3344 static int32_t LPUART6_DmaControl(uint32_t control, uint32_t arg)
3345 {
3346 return LPUART_DmaControl(control, arg, &LPUART6_DmaDriverState);
3347 }
3348
LPUART6_DmaGetStatus(void)3349 static ARM_USART_STATUS LPUART6_DmaGetStatus(void)
3350 {
3351 return LPUART_DmaGetStatus(&LPUART6_DmaDriverState);
3352 }
3353
3354 /* LPUART6 Driver Control Block */
3355
3356 #endif
3357
3358 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3359
3360 static cmsis_lpuart_edma_resource_t LPUART6_EdmaResource = {
3361 RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_TX_PERI_SEL,
3362 RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, RTE_USART6_DMA_RX_PERI_SEL,
3363
3364 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3365 RTE_USART6_DMA_TX_DMAMUX_BASE, RTE_USART6_DMA_RX_DMAMUX_BASE,
3366 #endif
3367 };
3368
3369 static lpuart_edma_handle_t LPUART6_EdmaHandle;
3370 static edma_handle_t LPUART6_EdmaRxHandle;
3371 static edma_handle_t LPUART6_EdmaTxHandle;
3372
3373 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3374 ARMCC_SECTION("lpuart6_edma_driver_state")
3375 static cmsis_lpuart_edma_driver_state_t LPUART6_EdmaDriverState = {
3376 #else
3377 static cmsis_lpuart_edma_driver_state_t LPUART6_EdmaDriverState = {
3378 #endif
3379 &LPUART6_Resource, &LPUART6_EdmaResource, &LPUART6_EdmaHandle, &LPUART6_EdmaRxHandle, &LPUART6_EdmaTxHandle,
3380 };
3381
LPUART6_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)3382 static int32_t LPUART6_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
3383 {
3384 #ifdef RTE_USART6_PIN_INIT
3385 RTE_USART6_PIN_INIT();
3386 #endif
3387 return LPUART_EdmaInitialize(cb_event, &LPUART6_EdmaDriverState);
3388 }
3389
LPUART6_EdmaUninitialize(void)3390 static int32_t LPUART6_EdmaUninitialize(void)
3391 {
3392 #ifdef RTE_USART6_PIN_DEINIT
3393 RTE_USART6_PIN_DEINIT();
3394 #endif
3395 return LPUART_EdmaUninitialize(&LPUART6_EdmaDriverState);
3396 }
3397
LPUART6_EdmaPowerControl(ARM_POWER_STATE state)3398 static int32_t LPUART6_EdmaPowerControl(ARM_POWER_STATE state)
3399 {
3400 return LPUART_EdmaPowerControl(state, &LPUART6_EdmaDriverState);
3401 }
3402
LPUART6_EdmaSend(const void * data,uint32_t num)3403 static int32_t LPUART6_EdmaSend(const void *data, uint32_t num)
3404 {
3405 return LPUART_EdmaSend(data, num, &LPUART6_EdmaDriverState);
3406 }
3407
LPUART6_EdmaReceive(void * data,uint32_t num)3408 static int32_t LPUART6_EdmaReceive(void *data, uint32_t num)
3409 {
3410 return LPUART_EdmaReceive(data, num, &LPUART6_EdmaDriverState);
3411 }
3412
LPUART6_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3413 static int32_t LPUART6_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3414 {
3415 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART6_EdmaDriverState);
3416 }
3417
LPUART6_EdmaGetTxCount(void)3418 static uint32_t LPUART6_EdmaGetTxCount(void)
3419 {
3420 return LPUART_EdmaGetTxCount(&LPUART6_EdmaDriverState);
3421 }
3422
LPUART6_EdmaGetRxCount(void)3423 static uint32_t LPUART6_EdmaGetRxCount(void)
3424 {
3425 return LPUART_EdmaGetRxCount(&LPUART6_EdmaDriverState);
3426 }
3427
LPUART6_EdmaControl(uint32_t control,uint32_t arg)3428 static int32_t LPUART6_EdmaControl(uint32_t control, uint32_t arg)
3429 {
3430 return LPUART_EdmaControl(control, arg, &LPUART6_EdmaDriverState);
3431 }
3432
LPUART6_EdmaGetStatus(void)3433 static ARM_USART_STATUS LPUART6_EdmaGetStatus(void)
3434 {
3435 return LPUART_EdmaGetStatus(&LPUART6_EdmaDriverState);
3436 }
3437
3438 #endif
3439
3440 #else
3441
3442 static lpuart_handle_t LPUART6_Handle;
3443
3444 #if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1)
3445 static uint8_t lpuart6_rxRingBuffer[USART_RX_BUFFER_LEN];
3446 #endif
3447
3448 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3449 ARMCC_SECTION("lpuart6_non_blocking_driver_state")
3450 static cmsis_lpuart_non_blocking_driver_state_t LPUART6_NonBlockingDriverState = {
3451 #else
3452 static cmsis_lpuart_non_blocking_driver_state_t LPUART6_NonBlockingDriverState = {
3453 #endif
3454 &LPUART6_Resource,
3455 &LPUART6_Handle,
3456 };
3457
LPUART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)3458 static int32_t LPUART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
3459 {
3460 #ifdef RTE_USART6_PIN_INIT
3461 RTE_USART6_PIN_INIT();
3462 #endif
3463 return LPUART_NonBlockingInitialize(cb_event, &LPUART6_NonBlockingDriverState);
3464 }
3465
LPUART6_NonBlockingUninitialize(void)3466 static int32_t LPUART6_NonBlockingUninitialize(void)
3467 {
3468 #ifdef RTE_USART6_PIN_DEINIT
3469 RTE_USART6_PIN_DEINIT();
3470 #endif
3471 return LPUART_NonBlockingUninitialize(&LPUART6_NonBlockingDriverState);
3472 }
3473
LPUART6_NonBlockingPowerControl(ARM_POWER_STATE state)3474 static int32_t LPUART6_NonBlockingPowerControl(ARM_POWER_STATE state)
3475 {
3476 int32_t result;
3477
3478 result = LPUART_NonBlockingPowerControl(state, &LPUART6_NonBlockingDriverState);
3479
3480 #if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1)
3481 if ((state == ARM_POWER_FULL) && (LPUART6_NonBlockingDriverState.handle->rxRingBuffer == NULL))
3482 {
3483 LPUART_TransferStartRingBuffer(LPUART6_NonBlockingDriverState.resource->base,
3484 LPUART6_NonBlockingDriverState.handle, lpuart6_rxRingBuffer,
3485 USART_RX_BUFFER_LEN);
3486 }
3487 #endif
3488
3489 return result;
3490 }
3491
LPUART6_NonBlockingSend(const void * data,uint32_t num)3492 static int32_t LPUART6_NonBlockingSend(const void *data, uint32_t num)
3493 {
3494 return LPUART_NonBlockingSend(data, num, &LPUART6_NonBlockingDriverState);
3495 }
3496
LPUART6_NonBlockingReceive(void * data,uint32_t num)3497 static int32_t LPUART6_NonBlockingReceive(void *data, uint32_t num)
3498 {
3499 return LPUART_NonBlockingReceive(data, num, &LPUART6_NonBlockingDriverState);
3500 }
3501
LPUART6_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)3502 static int32_t LPUART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
3503 {
3504 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART6_NonBlockingDriverState);
3505 }
3506
LPUART6_NonBlockingGetTxCount(void)3507 static uint32_t LPUART6_NonBlockingGetTxCount(void)
3508 {
3509 return LPUART_NonBlockingGetTxCount(&LPUART6_NonBlockingDriverState);
3510 }
3511
LPUART6_NonBlockingGetRxCount(void)3512 static uint32_t LPUART6_NonBlockingGetRxCount(void)
3513 {
3514 return LPUART_NonBlockingGetRxCount(&LPUART6_NonBlockingDriverState);
3515 }
3516
LPUART6_NonBlockingControl(uint32_t control,uint32_t arg)3517 static int32_t LPUART6_NonBlockingControl(uint32_t control, uint32_t arg)
3518 {
3519 int32_t result;
3520
3521 result = LPUART_NonBlockingControl(control, arg, &LPUART6_NonBlockingDriverState);
3522 if (ARM_DRIVER_OK != result)
3523 {
3524 return result;
3525 }
3526
3527 /* Enable the receive interrupts if ring buffer is used */
3528 if (LPUART6_NonBlockingDriverState.handle->rxRingBuffer != NULL)
3529 {
3530 LPUART_EnableInterrupts(
3531 LPUART6_NonBlockingDriverState.resource->base,
3532 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
3533 }
3534
3535 return ARM_DRIVER_OK;
3536 }
3537
LPUART6_NonBlockingGetStatus(void)3538 static ARM_USART_STATUS LPUART6_NonBlockingGetStatus(void)
3539 {
3540 return LPUART_NonBlockingGetStatus(&LPUART6_NonBlockingDriverState);
3541 }
3542
3543 #endif
3544
3545 ARM_DRIVER_USART Driver_USART6 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
3546 #if defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN
3547 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3548 LPUART6_EdmaInitialize, LPUART6_EdmaUninitialize, LPUART6_EdmaPowerControl,
3549 LPUART6_EdmaSend, LPUART6_EdmaReceive, LPUART6_EdmaTransfer,
3550 LPUART6_EdmaGetTxCount, LPUART6_EdmaGetRxCount, LPUART6_EdmaControl,
3551 LPUART6_EdmaGetStatus,
3552 #else
3553 LPUART6_DmaInitialize, LPUART6_DmaUninitialize, LPUART6_DmaPowerControl,
3554 LPUART6_DmaSend, LPUART6_DmaReceive, LPUART6_DmaTransfer,
3555 LPUART6_DmaGetTxCount, LPUART6_DmaGetRxCount, LPUART6_DmaControl,
3556 LPUART6_DmaGetStatus,
3557 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
3558 #else
3559 LPUART6_NonBlockingInitialize,
3560 LPUART6_NonBlockingUninitialize,
3561 LPUART6_NonBlockingPowerControl,
3562 LPUART6_NonBlockingSend,
3563 LPUART6_NonBlockingReceive,
3564 LPUART6_NonBlockingTransfer,
3565 LPUART6_NonBlockingGetTxCount,
3566 LPUART6_NonBlockingGetRxCount,
3567 LPUART6_NonBlockingControl,
3568 LPUART6_NonBlockingGetStatus,
3569 #endif /* RTE_USART6_DMA_EN */
3570 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
3571
3572 #endif /* LPUART6 */
3573
3574 #if defined(LPUART7) && defined(RTE_USART7) && RTE_USART7
3575
3576 /* User needs to provide the implementation for LPUART7_GetFreq/InitPins/DeinitPins
3577 in the application for enabling according instance. */
3578 extern uint32_t LPUART7_GetFreq(void);
3579
3580 static cmsis_lpuart_resource_t LPUART7_Resource = {LPUART7, LPUART7_GetFreq};
3581
3582 #if defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN
3583
3584 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3585
3586 static cmsis_lpuart_dma_resource_t LPUART7_DmaResource = {
3587 RTE_USART7_DMA_TX_DMA_BASE, RTE_USART7_DMA_TX_CH, RTE_USART7_DMA_TX_PERI_SEL,
3588 RTE_USART7_DMA_RX_DMA_BASE, RTE_USART7_DMA_RX_CH, RTE_USART7_DMA_RX_PERI_SEL,
3589
3590 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3591 RTE_USART7_DMA_TX_DMAMUX_BASE, RTE_USART7_DMA_RX_DMAMUX_BASE,
3592 #endif
3593 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
3594 RTE_USART7_DMAMUX_TX_CH, RTE_USART7_DMAMUX_RX_CH
3595 #endif
3596 };
3597
3598 static lpuart_dma_handle_t LPUART7_DmaHandle;
3599 static dma_handle_t LPUART7_DmaRxHandle;
3600 static dma_handle_t LPUART7_DmaTxHandle;
3601
3602 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3603 ARMCC_SECTION("lpuart7_dma_driver_state")
3604 static cmsis_lpuart_dma_driver_state_t LPUART7_DmaDriverState = {
3605 #else
3606 static cmsis_lpuart_dma_driver_state_t LPUART7_DmaDriverState = {
3607 #endif
3608 &LPUART7_Resource, &LPUART7_DmaResource, &LPUART7_DmaHandle, &LPUART7_DmaRxHandle, &LPUART7_DmaTxHandle,
3609 };
3610
LPUART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event)3611 static int32_t LPUART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
3612 {
3613 #ifdef RTE_USART7_PIN_INIT
3614 RTE_USART7_PIN_INIT();
3615 #endif
3616 return LPUART_DmaInitialize(cb_event, &LPUART7_DmaDriverState);
3617 }
3618
LPUART7_DmaUninitialize(void)3619 static int32_t LPUART7_DmaUninitialize(void)
3620 {
3621 #ifdef RTE_USART7_PIN_DEINIT
3622 RTE_USART7_PIN_DEINIT();
3623 #endif
3624 return LPUART_DmaUninitialize(&LPUART7_DmaDriverState);
3625 }
3626
LPUART7_DmaPowerControl(ARM_POWER_STATE state)3627 static int32_t LPUART7_DmaPowerControl(ARM_POWER_STATE state)
3628 {
3629 return LPUART_DmaPowerControl(state, &LPUART7_DmaDriverState);
3630 }
3631
LPUART7_DmaSend(const void * data,uint32_t num)3632 static int32_t LPUART7_DmaSend(const void *data, uint32_t num)
3633 {
3634 return LPUART_DmaSend(data, num, &LPUART7_DmaDriverState);
3635 }
3636
LPUART7_DmaReceive(void * data,uint32_t num)3637 static int32_t LPUART7_DmaReceive(void *data, uint32_t num)
3638 {
3639 return LPUART_DmaReceive(data, num, &LPUART7_DmaDriverState);
3640 }
3641
LPUART7_DmaTransfer(const void * data_out,void * data_in,uint32_t num)3642 static int32_t LPUART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
3643 {
3644 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART7_DmaDriverState);
3645 }
3646
LPUART7_DmaGetTxCount(void)3647 static uint32_t LPUART7_DmaGetTxCount(void)
3648 {
3649 return LPUART_DmaGetTxCount(&LPUART7_DmaDriverState);
3650 }
3651
LPUART7_DmaGetRxCount(void)3652 static uint32_t LPUART7_DmaGetRxCount(void)
3653 {
3654 return LPUART_DmaGetRxCount(&LPUART7_DmaDriverState);
3655 }
3656
LPUART7_DmaControl(uint32_t control,uint32_t arg)3657 static int32_t LPUART7_DmaControl(uint32_t control, uint32_t arg)
3658 {
3659 return LPUART_DmaControl(control, arg, &LPUART7_DmaDriverState);
3660 }
3661
LPUART7_DmaGetStatus(void)3662 static ARM_USART_STATUS LPUART7_DmaGetStatus(void)
3663 {
3664 return LPUART_DmaGetStatus(&LPUART7_DmaDriverState);
3665 }
3666
3667 /* LPUART7 Driver Control Block */
3668
3669 #endif
3670
3671 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3672
3673 static cmsis_lpuart_edma_resource_t LPUART7_EdmaResource = {
3674 RTE_USART7_DMA_TX_DMA_BASE, RTE_USART7_DMA_TX_CH, RTE_USART7_DMA_TX_PERI_SEL,
3675 RTE_USART7_DMA_RX_DMA_BASE, RTE_USART7_DMA_RX_CH, RTE_USART7_DMA_RX_PERI_SEL,
3676
3677 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3678 RTE_USART7_DMA_TX_DMAMUX_BASE, RTE_USART7_DMA_RX_DMAMUX_BASE,
3679 #endif
3680 };
3681
3682 static lpuart_edma_handle_t LPUART7_EdmaHandle;
3683 static edma_handle_t LPUART7_EdmaRxHandle;
3684 static edma_handle_t LPUART7_EdmaTxHandle;
3685
3686 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3687 ARMCC_SECTION("lpuart7_edma_driver_state")
3688 static cmsis_lpuart_edma_driver_state_t LPUART7_EdmaDriverState = {
3689 #else
3690 static cmsis_lpuart_edma_driver_state_t LPUART7_EdmaDriverState = {
3691 #endif
3692 &LPUART7_Resource, &LPUART7_EdmaResource, &LPUART7_EdmaHandle, &LPUART7_EdmaRxHandle, &LPUART7_EdmaTxHandle,
3693 };
3694
LPUART7_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)3695 static int32_t LPUART7_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
3696 {
3697 #ifdef RTE_USART7_PIN_INIT
3698 RTE_USART7_PIN_INIT();
3699 #endif
3700 return LPUART_EdmaInitialize(cb_event, &LPUART7_EdmaDriverState);
3701 }
3702
LPUART7_EdmaUninitialize(void)3703 static int32_t LPUART7_EdmaUninitialize(void)
3704 {
3705 #ifdef RTE_USART7_PIN_DEINIT
3706 RTE_USART7_PIN_DEINIT();
3707 #endif
3708 return LPUART_EdmaUninitialize(&LPUART7_EdmaDriverState);
3709 }
3710
LPUART7_EdmaPowerControl(ARM_POWER_STATE state)3711 static int32_t LPUART7_EdmaPowerControl(ARM_POWER_STATE state)
3712 {
3713 return LPUART_EdmaPowerControl(state, &LPUART7_EdmaDriverState);
3714 }
3715
LPUART7_EdmaSend(const void * data,uint32_t num)3716 static int32_t LPUART7_EdmaSend(const void *data, uint32_t num)
3717 {
3718 return LPUART_EdmaSend(data, num, &LPUART7_EdmaDriverState);
3719 }
3720
LPUART7_EdmaReceive(void * data,uint32_t num)3721 static int32_t LPUART7_EdmaReceive(void *data, uint32_t num)
3722 {
3723 return LPUART_EdmaReceive(data, num, &LPUART7_EdmaDriverState);
3724 }
3725
LPUART7_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3726 static int32_t LPUART7_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3727 {
3728 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART7_EdmaDriverState);
3729 }
3730
LPUART7_EdmaGetTxCount(void)3731 static uint32_t LPUART7_EdmaGetTxCount(void)
3732 {
3733 return LPUART_EdmaGetTxCount(&LPUART7_EdmaDriverState);
3734 }
3735
LPUART7_EdmaGetRxCount(void)3736 static uint32_t LPUART7_EdmaGetRxCount(void)
3737 {
3738 return LPUART_EdmaGetRxCount(&LPUART7_EdmaDriverState);
3739 }
3740
LPUART7_EdmaControl(uint32_t control,uint32_t arg)3741 static int32_t LPUART7_EdmaControl(uint32_t control, uint32_t arg)
3742 {
3743 return LPUART_EdmaControl(control, arg, &LPUART7_EdmaDriverState);
3744 }
3745
LPUART7_EdmaGetStatus(void)3746 static ARM_USART_STATUS LPUART7_EdmaGetStatus(void)
3747 {
3748 return LPUART_EdmaGetStatus(&LPUART7_EdmaDriverState);
3749 }
3750
3751 #endif
3752
3753 #else
3754
3755 static lpuart_handle_t LPUART7_Handle;
3756
3757 #if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1)
3758 static uint8_t lpuart7_rxRingBuffer[USART_RX_BUFFER_LEN];
3759 #endif
3760
3761 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3762 ARMCC_SECTION("lpuart7_non_blocking_driver_state")
3763 static cmsis_lpuart_non_blocking_driver_state_t LPUART7_NonBlockingDriverState = {
3764 #else
3765 static cmsis_lpuart_non_blocking_driver_state_t LPUART7_NonBlockingDriverState = {
3766 #endif
3767 &LPUART7_Resource,
3768 &LPUART7_Handle,
3769 };
3770
LPUART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)3771 static int32_t LPUART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
3772 {
3773 #ifdef RTE_USART7_PIN_INIT
3774 RTE_USART7_PIN_INIT();
3775 #endif
3776 return LPUART_NonBlockingInitialize(cb_event, &LPUART7_NonBlockingDriverState);
3777 }
3778
LPUART7_NonBlockingUninitialize(void)3779 static int32_t LPUART7_NonBlockingUninitialize(void)
3780 {
3781 #ifdef RTE_USART7_PIN_DEINIT
3782 RTE_USART7_PIN_DEINIT();
3783 #endif
3784 return LPUART_NonBlockingUninitialize(&LPUART7_NonBlockingDriverState);
3785 }
3786
LPUART7_NonBlockingPowerControl(ARM_POWER_STATE state)3787 static int32_t LPUART7_NonBlockingPowerControl(ARM_POWER_STATE state)
3788 {
3789 int32_t result;
3790
3791 result = LPUART_NonBlockingPowerControl(state, &LPUART7_NonBlockingDriverState);
3792
3793 #if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1)
3794 if ((state == ARM_POWER_FULL) && (LPUART7_NonBlockingDriverState.handle->rxRingBuffer == NULL))
3795 {
3796 LPUART_TransferStartRingBuffer(LPUART7_NonBlockingDriverState.resource->base,
3797 LPUART7_NonBlockingDriverState.handle, lpuart7_rxRingBuffer,
3798 USART_RX_BUFFER_LEN);
3799 }
3800 #endif
3801
3802 return result;
3803 }
3804
LPUART7_NonBlockingSend(const void * data,uint32_t num)3805 static int32_t LPUART7_NonBlockingSend(const void *data, uint32_t num)
3806 {
3807 return LPUART_NonBlockingSend(data, num, &LPUART7_NonBlockingDriverState);
3808 }
3809
LPUART7_NonBlockingReceive(void * data,uint32_t num)3810 static int32_t LPUART7_NonBlockingReceive(void *data, uint32_t num)
3811 {
3812 return LPUART_NonBlockingReceive(data, num, &LPUART7_NonBlockingDriverState);
3813 }
3814
LPUART7_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)3815 static int32_t LPUART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
3816 {
3817 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART7_NonBlockingDriverState);
3818 }
3819
LPUART7_NonBlockingGetTxCount(void)3820 static uint32_t LPUART7_NonBlockingGetTxCount(void)
3821 {
3822 return LPUART_NonBlockingGetTxCount(&LPUART7_NonBlockingDriverState);
3823 }
3824
LPUART7_NonBlockingGetRxCount(void)3825 static uint32_t LPUART7_NonBlockingGetRxCount(void)
3826 {
3827 return LPUART_NonBlockingGetRxCount(&LPUART7_NonBlockingDriverState);
3828 }
3829
LPUART7_NonBlockingControl(uint32_t control,uint32_t arg)3830 static int32_t LPUART7_NonBlockingControl(uint32_t control, uint32_t arg)
3831 {
3832 int32_t result;
3833
3834 result = LPUART_NonBlockingControl(control, arg, &LPUART7_NonBlockingDriverState);
3835 if (ARM_DRIVER_OK != result)
3836 {
3837 return result;
3838 }
3839
3840 /* Enable the receive interrupts if ring buffer is used */
3841 if (LPUART7_NonBlockingDriverState.handle->rxRingBuffer != NULL)
3842 {
3843 LPUART_EnableInterrupts(
3844 LPUART7_NonBlockingDriverState.resource->base,
3845 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
3846 }
3847
3848 return ARM_DRIVER_OK;
3849 }
3850
LPUART7_NonBlockingGetStatus(void)3851 static ARM_USART_STATUS LPUART7_NonBlockingGetStatus(void)
3852 {
3853 return LPUART_NonBlockingGetStatus(&LPUART7_NonBlockingDriverState);
3854 }
3855
3856 #endif
3857
3858 ARM_DRIVER_USART Driver_USART7 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
3859 #if defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN
3860 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3861 LPUART7_EdmaInitialize, LPUART7_EdmaUninitialize, LPUART7_EdmaPowerControl,
3862 LPUART7_EdmaSend, LPUART7_EdmaReceive, LPUART7_EdmaTransfer,
3863 LPUART7_EdmaGetTxCount, LPUART7_EdmaGetRxCount, LPUART7_EdmaControl,
3864 LPUART7_EdmaGetStatus,
3865 #else
3866 LPUART7_DmaInitialize, LPUART7_DmaUninitialize, LPUART7_DmaPowerControl,
3867 LPUART7_DmaSend, LPUART7_DmaReceive, LPUART7_DmaTransfer,
3868 LPUART7_DmaGetTxCount, LPUART7_DmaGetRxCount, LPUART7_DmaControl,
3869 LPUART7_DmaGetStatus,
3870 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
3871 #else
3872 LPUART7_NonBlockingInitialize,
3873 LPUART7_NonBlockingUninitialize,
3874 LPUART7_NonBlockingPowerControl,
3875 LPUART7_NonBlockingSend,
3876 LPUART7_NonBlockingReceive,
3877 LPUART7_NonBlockingTransfer,
3878 LPUART7_NonBlockingGetTxCount,
3879 LPUART7_NonBlockingGetRxCount,
3880 LPUART7_NonBlockingControl,
3881 LPUART7_NonBlockingGetStatus,
3882 #endif /* RTE_USART7_DMA_EN */
3883 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
3884
3885 #endif /* LPUART7 */
3886
3887 #if defined(LPUART8) && defined(RTE_USART8) && RTE_USART8
3888
3889 /* User needs to provide the implementation for LPUART8_GetFreq/InitPins/DeinitPins
3890 in the application for enabling according instance. */
3891 extern uint32_t LPUART8_GetFreq(void);
3892
3893 static cmsis_lpuart_resource_t LPUART8_Resource = {LPUART8, LPUART8_GetFreq};
3894
3895 #if defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN
3896
3897 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3898
3899 static cmsis_lpuart_dma_resource_t LPUART8_DmaResource = {
3900 RTE_USART8_DMA_TX_DMA_BASE, RTE_USART8_DMA_TX_CH, RTE_USART8_DMA_TX_PERI_SEL,
3901 RTE_USART8_DMA_RX_DMA_BASE, RTE_USART8_DMA_RX_CH, RTE_USART8_DMA_RX_PERI_SEL,
3902
3903 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3904 RTE_USART8_DMA_TX_DMAMUX_BASE, RTE_USART8_DMA_RX_DMAMUX_BASE,
3905 #endif
3906 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
3907 RTE_USART8_DMAMUX_TX_CH, RTE_USART8_DMAMUX_RX_CH
3908 #endif
3909 };
3910
3911 static lpuart_dma_handle_t LPUART8_DmaHandle;
3912 static dma_handle_t LPUART8_DmaRxHandle;
3913 static dma_handle_t LPUART8_DmaTxHandle;
3914
3915 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3916 ARMCC_SECTION("lpuart8_dma_driver_state")
3917 static cmsis_lpuart_dma_driver_state_t LPUART8_DmaDriverState = {
3918 #else
3919 static cmsis_lpuart_dma_driver_state_t LPUART8_DmaDriverState = {
3920 #endif
3921 &LPUART8_Resource, &LPUART8_DmaResource, &LPUART8_DmaHandle, &LPUART8_DmaRxHandle, &LPUART8_DmaTxHandle,
3922 };
3923
LPUART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event)3924 static int32_t LPUART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
3925 {
3926 #ifdef RTE_USART8_PIN_INIT
3927 RTE_USART8_PIN_INIT();
3928 #endif
3929 return LPUART_DmaInitialize(cb_event, &LPUART8_DmaDriverState);
3930 }
3931
LPUART8_DmaUninitialize(void)3932 static int32_t LPUART8_DmaUninitialize(void)
3933 {
3934 #ifdef RTE_USART8_PIN_DEINIT
3935 RTE_USART8_PIN_DEINIT();
3936 #endif
3937 return LPUART_DmaUninitialize(&LPUART8_DmaDriverState);
3938 }
3939
LPUART8_DmaPowerControl(ARM_POWER_STATE state)3940 static int32_t LPUART8_DmaPowerControl(ARM_POWER_STATE state)
3941 {
3942 return LPUART_DmaPowerControl(state, &LPUART8_DmaDriverState);
3943 }
3944
LPUART8_DmaSend(const void * data,uint32_t num)3945 static int32_t LPUART8_DmaSend(const void *data, uint32_t num)
3946 {
3947 return LPUART_DmaSend(data, num, &LPUART8_DmaDriverState);
3948 }
3949
LPUART8_DmaReceive(void * data,uint32_t num)3950 static int32_t LPUART8_DmaReceive(void *data, uint32_t num)
3951 {
3952 return LPUART_DmaReceive(data, num, &LPUART8_DmaDriverState);
3953 }
3954
LPUART8_DmaTransfer(const void * data_out,void * data_in,uint32_t num)3955 static int32_t LPUART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
3956 {
3957 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART8_DmaDriverState);
3958 }
3959
LPUART8_DmaGetTxCount(void)3960 static uint32_t LPUART8_DmaGetTxCount(void)
3961 {
3962 return LPUART_DmaGetTxCount(&LPUART8_DmaDriverState);
3963 }
3964
LPUART8_DmaGetRxCount(void)3965 static uint32_t LPUART8_DmaGetRxCount(void)
3966 {
3967 return LPUART_DmaGetRxCount(&LPUART8_DmaDriverState);
3968 }
3969
LPUART8_DmaControl(uint32_t control,uint32_t arg)3970 static int32_t LPUART8_DmaControl(uint32_t control, uint32_t arg)
3971 {
3972 return LPUART_DmaControl(control, arg, &LPUART8_DmaDriverState);
3973 }
3974
LPUART8_DmaGetStatus(void)3975 static ARM_USART_STATUS LPUART8_DmaGetStatus(void)
3976 {
3977 return LPUART_DmaGetStatus(&LPUART8_DmaDriverState);
3978 }
3979
3980 /* LPUART8 Driver Control Block */
3981
3982 #endif
3983
3984 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3985
3986 static cmsis_lpuart_edma_resource_t LPUART8_EdmaResource = {
3987 RTE_USART8_DMA_TX_DMA_BASE, RTE_USART8_DMA_TX_CH, RTE_USART8_DMA_TX_PERI_SEL,
3988 RTE_USART8_DMA_RX_DMA_BASE, RTE_USART8_DMA_RX_CH, RTE_USART8_DMA_RX_PERI_SEL,
3989
3990 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3991 RTE_USART8_DMA_TX_DMAMUX_BASE, RTE_USART8_DMA_RX_DMAMUX_BASE,
3992 #endif
3993 };
3994
3995 static lpuart_edma_handle_t LPUART8_EdmaHandle;
3996 static edma_handle_t LPUART8_EdmaRxHandle;
3997 static edma_handle_t LPUART8_EdmaTxHandle;
3998
3999 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4000 ARMCC_SECTION("lpuart8_edma_driver_state")
4001 static cmsis_lpuart_edma_driver_state_t LPUART8_EdmaDriverState = {
4002 #else
4003 static cmsis_lpuart_edma_driver_state_t LPUART8_EdmaDriverState = {
4004 #endif
4005 &LPUART8_Resource, &LPUART8_EdmaResource, &LPUART8_EdmaHandle, &LPUART8_EdmaRxHandle, &LPUART8_EdmaTxHandle,
4006 };
4007
LPUART8_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)4008 static int32_t LPUART8_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
4009 {
4010 #ifdef RTE_USART8_PIN_INIT
4011 RTE_USART8_PIN_INIT();
4012 #endif
4013 return LPUART_EdmaInitialize(cb_event, &LPUART8_EdmaDriverState);
4014 }
4015
LPUART8_EdmaUninitialize(void)4016 static int32_t LPUART8_EdmaUninitialize(void)
4017 {
4018 #ifdef RTE_USART8_PIN_DEINIT
4019 RTE_USART8_PIN_DEINIT();
4020 #endif
4021 return LPUART_EdmaUninitialize(&LPUART8_EdmaDriverState);
4022 }
4023
LPUART8_EdmaPowerControl(ARM_POWER_STATE state)4024 static int32_t LPUART8_EdmaPowerControl(ARM_POWER_STATE state)
4025 {
4026 return LPUART_EdmaPowerControl(state, &LPUART8_EdmaDriverState);
4027 }
4028
LPUART8_EdmaSend(const void * data,uint32_t num)4029 static int32_t LPUART8_EdmaSend(const void *data, uint32_t num)
4030 {
4031 return LPUART_EdmaSend(data, num, &LPUART8_EdmaDriverState);
4032 }
4033
LPUART8_EdmaReceive(void * data,uint32_t num)4034 static int32_t LPUART8_EdmaReceive(void *data, uint32_t num)
4035 {
4036 return LPUART_EdmaReceive(data, num, &LPUART8_EdmaDriverState);
4037 }
4038
LPUART8_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4039 static int32_t LPUART8_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4040 {
4041 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART8_EdmaDriverState);
4042 }
4043
LPUART8_EdmaGetTxCount(void)4044 static uint32_t LPUART8_EdmaGetTxCount(void)
4045 {
4046 return LPUART_EdmaGetTxCount(&LPUART8_EdmaDriverState);
4047 }
4048
LPUART8_EdmaGetRxCount(void)4049 static uint32_t LPUART8_EdmaGetRxCount(void)
4050 {
4051 return LPUART_EdmaGetRxCount(&LPUART8_EdmaDriverState);
4052 }
4053
LPUART8_EdmaControl(uint32_t control,uint32_t arg)4054 static int32_t LPUART8_EdmaControl(uint32_t control, uint32_t arg)
4055 {
4056 return LPUART_EdmaControl(control, arg, &LPUART8_EdmaDriverState);
4057 }
4058
LPUART8_EdmaGetStatus(void)4059 static ARM_USART_STATUS LPUART8_EdmaGetStatus(void)
4060 {
4061 return LPUART_EdmaGetStatus(&LPUART8_EdmaDriverState);
4062 }
4063
4064 #endif
4065
4066 #else
4067
4068 static lpuart_handle_t LPUART8_Handle;
4069
4070 #if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1)
4071 static uint8_t lpuart8_rxRingBuffer[USART_RX_BUFFER_LEN];
4072 #endif
4073
4074 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4075 ARMCC_SECTION("lpuart8_non_blocking_driver_state")
4076 static cmsis_lpuart_non_blocking_driver_state_t LPUART8_NonBlockingDriverState = {
4077 #else
4078 static cmsis_lpuart_non_blocking_driver_state_t LPUART8_NonBlockingDriverState = {
4079 #endif
4080 &LPUART8_Resource,
4081 &LPUART8_Handle,
4082 };
4083
LPUART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)4084 static int32_t LPUART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
4085 {
4086 #ifdef RTE_USART8_PIN_INIT
4087 RTE_USART8_PIN_INIT();
4088 #endif
4089 return LPUART_NonBlockingInitialize(cb_event, &LPUART8_NonBlockingDriverState);
4090 }
4091
LPUART8_NonBlockingUninitialize(void)4092 static int32_t LPUART8_NonBlockingUninitialize(void)
4093 {
4094 #ifdef RTE_USART8_PIN_DEINIT
4095 RTE_USART8_PIN_DEINIT();
4096 #endif
4097 return LPUART_NonBlockingUninitialize(&LPUART8_NonBlockingDriverState);
4098 }
4099
LPUART8_NonBlockingPowerControl(ARM_POWER_STATE state)4100 static int32_t LPUART8_NonBlockingPowerControl(ARM_POWER_STATE state)
4101 {
4102 int32_t result;
4103
4104 result = LPUART_NonBlockingPowerControl(state, &LPUART8_NonBlockingDriverState);
4105
4106 #if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1)
4107 if ((state == ARM_POWER_FULL) && (LPUART8_NonBlockingDriverState.handle->rxRingBuffer == NULL))
4108 {
4109 LPUART_TransferStartRingBuffer(LPUART8_NonBlockingDriverState.resource->base,
4110 LPUART8_NonBlockingDriverState.handle, lpuart8_rxRingBuffer,
4111 USART_RX_BUFFER_LEN);
4112 }
4113 #endif
4114
4115 return result;
4116 }
4117
LPUART8_NonBlockingSend(const void * data,uint32_t num)4118 static int32_t LPUART8_NonBlockingSend(const void *data, uint32_t num)
4119 {
4120 return LPUART_NonBlockingSend(data, num, &LPUART8_NonBlockingDriverState);
4121 }
4122
LPUART8_NonBlockingReceive(void * data,uint32_t num)4123 static int32_t LPUART8_NonBlockingReceive(void *data, uint32_t num)
4124 {
4125 return LPUART_NonBlockingReceive(data, num, &LPUART8_NonBlockingDriverState);
4126 }
4127
LPUART8_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)4128 static int32_t LPUART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
4129 {
4130 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART8_NonBlockingDriverState);
4131 }
4132
LPUART8_NonBlockingGetTxCount(void)4133 static uint32_t LPUART8_NonBlockingGetTxCount(void)
4134 {
4135 return LPUART_NonBlockingGetTxCount(&LPUART8_NonBlockingDriverState);
4136 }
4137
LPUART8_NonBlockingGetRxCount(void)4138 static uint32_t LPUART8_NonBlockingGetRxCount(void)
4139 {
4140 return LPUART_NonBlockingGetRxCount(&LPUART8_NonBlockingDriverState);
4141 }
4142
LPUART8_NonBlockingControl(uint32_t control,uint32_t arg)4143 static int32_t LPUART8_NonBlockingControl(uint32_t control, uint32_t arg)
4144 {
4145 int32_t result;
4146
4147 result = LPUART_NonBlockingControl(control, arg, &LPUART8_NonBlockingDriverState);
4148 if (ARM_DRIVER_OK != result)
4149 {
4150 return result;
4151 }
4152
4153 /* Enable the receive interrupts if ring buffer is used */
4154 if (LPUART8_NonBlockingDriverState.handle->rxRingBuffer != NULL)
4155 {
4156 LPUART_EnableInterrupts(
4157 LPUART8_NonBlockingDriverState.resource->base,
4158 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
4159 }
4160
4161 return ARM_DRIVER_OK;
4162 }
4163
LPUART8_NonBlockingGetStatus(void)4164 static ARM_USART_STATUS LPUART8_NonBlockingGetStatus(void)
4165 {
4166 return LPUART_NonBlockingGetStatus(&LPUART8_NonBlockingDriverState);
4167 }
4168
4169 #endif
4170
4171 ARM_DRIVER_USART Driver_USART8 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
4172 #if defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN
4173 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4174 LPUART8_EdmaInitialize, LPUART8_EdmaUninitialize, LPUART8_EdmaPowerControl,
4175 LPUART8_EdmaSend, LPUART8_EdmaReceive, LPUART8_EdmaTransfer,
4176 LPUART8_EdmaGetTxCount, LPUART8_EdmaGetRxCount, LPUART8_EdmaControl,
4177 LPUART8_EdmaGetStatus,
4178 #else
4179 LPUART8_DmaInitialize, LPUART8_DmaUninitialize, LPUART8_DmaPowerControl,
4180 LPUART8_DmaSend, LPUART8_DmaReceive, LPUART8_DmaTransfer,
4181 LPUART8_DmaGetTxCount, LPUART8_DmaGetRxCount, LPUART8_DmaControl,
4182 LPUART8_DmaGetStatus,
4183 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
4184 #else
4185 LPUART8_NonBlockingInitialize,
4186 LPUART8_NonBlockingUninitialize,
4187 LPUART8_NonBlockingPowerControl,
4188 LPUART8_NonBlockingSend,
4189 LPUART8_NonBlockingReceive,
4190 LPUART8_NonBlockingTransfer,
4191 LPUART8_NonBlockingGetTxCount,
4192 LPUART8_NonBlockingGetRxCount,
4193 LPUART8_NonBlockingControl,
4194 LPUART8_NonBlockingGetStatus,
4195 #endif /* RTE_USART8_DMA_EN */
4196 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
4197
4198 #endif /* LPUART8 */
4199
4200 #if defined(LPUART9) && defined(RTE_USART9) && RTE_USART9
4201
4202 /* User needs to provide the implementation for LPUART9_GetFreq/InitPins/DeinitPins
4203 in the application for enabling according instance. */
4204 extern uint32_t LPUART9_GetFreq(void);
4205
4206 static cmsis_lpuart_resource_t LPUART9_Resource = {LPUART9, LPUART9_GetFreq};
4207
4208 #if defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN
4209
4210 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
4211
4212 static cmsis_lpuart_dma_resource_t LPUART9_DmaResource = {
4213 RTE_USART9_DMA_TX_DMA_BASE, RTE_USART9_DMA_TX_CH, RTE_USART9_DMA_TX_PERI_SEL,
4214 RTE_USART9_DMA_RX_DMA_BASE, RTE_USART9_DMA_RX_CH, RTE_USART9_DMA_RX_PERI_SEL,
4215
4216 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4217 RTE_USART9_DMA_TX_DMAMUX_BASE, RTE_USART9_DMA_RX_DMAMUX_BASE,
4218 #endif
4219 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
4220 RTE_USART9_DMAMUX_TX_CH, RTE_USART9_DMAMUX_RX_CH
4221 #endif
4222 };
4223
4224 static lpuart_dma_handle_t LPUART9_DmaHandle;
4225 static dma_handle_t LPUART9_DmaRxHandle;
4226 static dma_handle_t LPUART9_DmaTxHandle;
4227
4228 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4229 ARMCC_SECTION("lpuart9_dma_driver_state")
4230 static cmsis_lpuart_dma_driver_state_t LPUART9_DmaDriverState = {
4231 #else
4232 static cmsis_lpuart_dma_driver_state_t LPUART9_DmaDriverState = {
4233 #endif
4234 &LPUART9_Resource, &LPUART9_DmaResource, &LPUART9_DmaHandle, &LPUART9_DmaRxHandle, &LPUART9_DmaTxHandle,
4235 };
4236
LPUART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event)4237 static int32_t LPUART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
4238 {
4239 #ifdef RTE_USART9_PIN_INIT
4240 RTE_USART9_PIN_INIT();
4241 #endif
4242 return LPUART_DmaInitialize(cb_event, &LPUART9_DmaDriverState);
4243 }
4244
LPUART9_DmaUninitialize(void)4245 static int32_t LPUART9_DmaUninitialize(void)
4246 {
4247 #ifdef RTE_USART9_PIN_DEINIT
4248 RTE_USART9_PIN_DEINIT();
4249 #endif
4250 return LPUART_DmaUninitialize(&LPUART9_DmaDriverState);
4251 }
4252
LPUART9_DmaPowerControl(ARM_POWER_STATE state)4253 static int32_t LPUART9_DmaPowerControl(ARM_POWER_STATE state)
4254 {
4255 return LPUART_DmaPowerControl(state, &LPUART9_DmaDriverState);
4256 }
4257
LPUART9_DmaSend(const void * data,uint32_t num)4258 static int32_t LPUART9_DmaSend(const void *data, uint32_t num)
4259 {
4260 return LPUART_DmaSend(data, num, &LPUART9_DmaDriverState);
4261 }
4262
LPUART9_DmaReceive(void * data,uint32_t num)4263 static int32_t LPUART9_DmaReceive(void *data, uint32_t num)
4264 {
4265 return LPUART_DmaReceive(data, num, &LPUART9_DmaDriverState);
4266 }
4267
LPUART9_DmaTransfer(const void * data_out,void * data_in,uint32_t num)4268 static int32_t LPUART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
4269 {
4270 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART9_DmaDriverState);
4271 }
4272
LPUART9_DmaGetTxCount(void)4273 static uint32_t LPUART9_DmaGetTxCount(void)
4274 {
4275 return LPUART_DmaGetTxCount(&LPUART9_DmaDriverState);
4276 }
4277
LPUART9_DmaGetRxCount(void)4278 static uint32_t LPUART9_DmaGetRxCount(void)
4279 {
4280 return LPUART_DmaGetRxCount(&LPUART9_DmaDriverState);
4281 }
4282
LPUART9_DmaControl(uint32_t control,uint32_t arg)4283 static int32_t LPUART9_DmaControl(uint32_t control, uint32_t arg)
4284 {
4285 return LPUART_DmaControl(control, arg, &LPUART9_DmaDriverState);
4286 }
4287
LPUART9_DmaGetStatus(void)4288 static ARM_USART_STATUS LPUART9_DmaGetStatus(void)
4289 {
4290 return LPUART_DmaGetStatus(&LPUART9_DmaDriverState);
4291 }
4292
4293 /* LPUART9 Driver Control Block */
4294
4295 #endif
4296
4297 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4298
4299 static cmsis_lpuart_edma_resource_t LPUART9_EdmaResource = {
4300 RTE_USART9_DMA_TX_DMA_BASE, RTE_USART9_DMA_TX_CH, RTE_USART9_DMA_TX_PERI_SEL,
4301 RTE_USART9_DMA_RX_DMA_BASE, RTE_USART9_DMA_RX_CH, RTE_USART9_DMA_RX_PERI_SEL,
4302
4303 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4304 RTE_USART9_DMA_TX_DMAMUX_BASE, RTE_USART9_DMA_RX_DMAMUX_BASE,
4305 #endif
4306 };
4307
4308 static lpuart_edma_handle_t LPUART9_EdmaHandle;
4309 static edma_handle_t LPUART9_EdmaRxHandle;
4310 static edma_handle_t LPUART9_EdmaTxHandle;
4311
4312 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4313 ARMCC_SECTION("lpuart9_edma_driver_state")
4314 static cmsis_lpuart_edma_driver_state_t LPUART9_EdmaDriverState = {
4315 #else
4316 static cmsis_lpuart_edma_driver_state_t LPUART9_EdmaDriverState = {
4317 #endif
4318 &LPUART9_Resource, &LPUART9_EdmaResource, &LPUART9_EdmaHandle, &LPUART9_EdmaRxHandle, &LPUART9_EdmaTxHandle,
4319 };
4320
LPUART9_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)4321 static int32_t LPUART9_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
4322 {
4323 #ifdef RTE_USART9_PIN_INIT
4324 RTE_USART9_PIN_INIT();
4325 #endif
4326 return LPUART_EdmaInitialize(cb_event, &LPUART9_EdmaDriverState);
4327 }
4328
LPUART9_EdmaUninitialize(void)4329 static int32_t LPUART9_EdmaUninitialize(void)
4330 {
4331 #ifdef RTE_USART9_PIN_DEINIT
4332 RTE_USART9_PIN_DEINIT();
4333 #endif
4334 return LPUART_EdmaUninitialize(&LPUART9_EdmaDriverState);
4335 }
4336
LPUART9_EdmaPowerControl(ARM_POWER_STATE state)4337 static int32_t LPUART9_EdmaPowerControl(ARM_POWER_STATE state)
4338 {
4339 return LPUART_EdmaPowerControl(state, &LPUART9_EdmaDriverState);
4340 }
4341
LPUART9_EdmaSend(const void * data,uint32_t num)4342 static int32_t LPUART9_EdmaSend(const void *data, uint32_t num)
4343 {
4344 return LPUART_EdmaSend(data, num, &LPUART9_EdmaDriverState);
4345 }
4346
LPUART9_EdmaReceive(void * data,uint32_t num)4347 static int32_t LPUART9_EdmaReceive(void *data, uint32_t num)
4348 {
4349 return LPUART_EdmaReceive(data, num, &LPUART9_EdmaDriverState);
4350 }
4351
LPUART9_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4352 static int32_t LPUART9_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4353 {
4354 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART9_EdmaDriverState);
4355 }
4356
LPUART9_EdmaGetTxCount(void)4357 static uint32_t LPUART9_EdmaGetTxCount(void)
4358 {
4359 return LPUART_EdmaGetTxCount(&LPUART9_EdmaDriverState);
4360 }
4361
LPUART9_EdmaGetRxCount(void)4362 static uint32_t LPUART9_EdmaGetRxCount(void)
4363 {
4364 return LPUART_EdmaGetRxCount(&LPUART9_EdmaDriverState);
4365 }
4366
LPUART9_EdmaControl(uint32_t control,uint32_t arg)4367 static int32_t LPUART9_EdmaControl(uint32_t control, uint32_t arg)
4368 {
4369 return LPUART_EdmaControl(control, arg, &LPUART9_EdmaDriverState);
4370 }
4371
LPUART9_EdmaGetStatus(void)4372 static ARM_USART_STATUS LPUART9_EdmaGetStatus(void)
4373 {
4374 return LPUART_EdmaGetStatus(&LPUART9_EdmaDriverState);
4375 }
4376
4377 #endif
4378
4379 #else
4380
4381 static lpuart_handle_t LPUART9_Handle;
4382
4383 #if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1)
4384 static uint8_t lpuart9_rxRingBuffer[USART_RX_BUFFER_LEN];
4385 #endif
4386
4387 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4388 ARMCC_SECTION("lpuart9_non_blocking_driver_state")
4389 static cmsis_lpuart_non_blocking_driver_state_t LPUART9_NonBlockingDriverState = {
4390 #else
4391 static cmsis_lpuart_non_blocking_driver_state_t LPUART9_NonBlockingDriverState = {
4392 #endif
4393 &LPUART9_Resource,
4394 &LPUART9_Handle,
4395 };
4396
LPUART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)4397 static int32_t LPUART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
4398 {
4399 #ifdef RTE_USART9_PIN_INIT
4400 RTE_USART9_PIN_INIT();
4401 #endif
4402 return LPUART_NonBlockingInitialize(cb_event, &LPUART9_NonBlockingDriverState);
4403 }
4404
LPUART9_NonBlockingUninitialize(void)4405 static int32_t LPUART9_NonBlockingUninitialize(void)
4406 {
4407 #ifdef RTE_USART9_PIN_DEINIT
4408 RTE_USART9_PIN_DEINIT();
4409 #endif
4410 return LPUART_NonBlockingUninitialize(&LPUART9_NonBlockingDriverState);
4411 }
4412
LPUART9_NonBlockingPowerControl(ARM_POWER_STATE state)4413 static int32_t LPUART9_NonBlockingPowerControl(ARM_POWER_STATE state)
4414 {
4415 int32_t result;
4416
4417 result = LPUART_NonBlockingPowerControl(state, &LPUART9_NonBlockingDriverState);
4418
4419 #if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1)
4420 if ((state == ARM_POWER_FULL) && (LPUART9_NonBlockingDriverState.handle->rxRingBuffer == NULL))
4421 {
4422 LPUART_TransferStartRingBuffer(LPUART9_NonBlockingDriverState.resource->base,
4423 LPUART9_NonBlockingDriverState.handle, lpuart9_rxRingBuffer,
4424 USART_RX_BUFFER_LEN);
4425 }
4426 #endif
4427
4428 return result;
4429 }
4430
LPUART9_NonBlockingSend(const void * data,uint32_t num)4431 static int32_t LPUART9_NonBlockingSend(const void *data, uint32_t num)
4432 {
4433 return LPUART_NonBlockingSend(data, num, &LPUART9_NonBlockingDriverState);
4434 }
4435
LPUART9_NonBlockingReceive(void * data,uint32_t num)4436 static int32_t LPUART9_NonBlockingReceive(void *data, uint32_t num)
4437 {
4438 return LPUART_NonBlockingReceive(data, num, &LPUART9_NonBlockingDriverState);
4439 }
4440
LPUART9_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)4441 static int32_t LPUART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
4442 {
4443 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART9_NonBlockingDriverState);
4444 }
4445
LPUART9_NonBlockingGetTxCount(void)4446 static uint32_t LPUART9_NonBlockingGetTxCount(void)
4447 {
4448 return LPUART_NonBlockingGetTxCount(&LPUART9_NonBlockingDriverState);
4449 }
4450
LPUART9_NonBlockingGetRxCount(void)4451 static uint32_t LPUART9_NonBlockingGetRxCount(void)
4452 {
4453 return LPUART_NonBlockingGetRxCount(&LPUART9_NonBlockingDriverState);
4454 }
4455
LPUART9_NonBlockingControl(uint32_t control,uint32_t arg)4456 static int32_t LPUART9_NonBlockingControl(uint32_t control, uint32_t arg)
4457 {
4458 int32_t result;
4459
4460 result = LPUART_NonBlockingControl(control, arg, &LPUART9_NonBlockingDriverState);
4461 if (ARM_DRIVER_OK != result)
4462 {
4463 return result;
4464 }
4465
4466 /* Enable the receive interrupts if ring buffer is used */
4467 if (LPUART9_NonBlockingDriverState.handle->rxRingBuffer != NULL)
4468 {
4469 LPUART_EnableInterrupts(
4470 LPUART9_NonBlockingDriverState.resource->base,
4471 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
4472 }
4473
4474 return ARM_DRIVER_OK;
4475 }
4476
LPUART9_NonBlockingGetStatus(void)4477 static ARM_USART_STATUS LPUART9_NonBlockingGetStatus(void)
4478 {
4479 return LPUART_NonBlockingGetStatus(&LPUART9_NonBlockingDriverState);
4480 }
4481
4482 #endif
4483
4484 ARM_DRIVER_USART Driver_USART9 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
4485 #if defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN
4486 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4487 LPUART9_EdmaInitialize, LPUART9_EdmaUninitialize, LPUART9_EdmaPowerControl,
4488 LPUART9_EdmaSend, LPUART9_EdmaReceive, LPUART9_EdmaTransfer,
4489 LPUART9_EdmaGetTxCount, LPUART9_EdmaGetRxCount, LPUART9_EdmaControl,
4490 LPUART9_EdmaGetStatus,
4491 #else
4492 LPUART9_DmaInitialize, LPUART9_DmaUninitialize, LPUART9_DmaPowerControl,
4493 LPUART9_DmaSend, LPUART9_DmaReceive, LPUART9_DmaTransfer,
4494 LPUART9_DmaGetTxCount, LPUART9_DmaGetRxCount, LPUART9_DmaControl,
4495 LPUART9_DmaGetStatus,
4496 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
4497 #else
4498 LPUART9_NonBlockingInitialize,
4499 LPUART9_NonBlockingUninitialize,
4500 LPUART9_NonBlockingPowerControl,
4501 LPUART9_NonBlockingSend,
4502 LPUART9_NonBlockingReceive,
4503 LPUART9_NonBlockingTransfer,
4504 LPUART9_NonBlockingGetTxCount,
4505 LPUART9_NonBlockingGetRxCount,
4506 LPUART9_NonBlockingControl,
4507 LPUART9_NonBlockingGetStatus,
4508 #endif /* RTE_USART9_DMA_EN */
4509 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
4510
4511 #endif /* LPUART9 */
4512
4513 #if defined(LPUART10) && defined(RTE_USART10) && RTE_USART10
4514
4515 /* User needs to provide the implementation for LPUART10_GetFreq/InitPins/DeinitPins
4516 in the application for enabling according instance. */
4517 extern uint32_t LPUART10_GetFreq(void);
4518
4519 static cmsis_lpuart_resource_t LPUART10_Resource = {LPUART10, LPUART10_GetFreq};
4520
4521 #if defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN
4522
4523 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
4524
4525 static cmsis_lpuart_dma_resource_t LPUART10_DmaResource = {
4526 RTE_USART10_DMA_TX_DMA_BASE, RTE_USART10_DMA_TX_CH, RTE_USART10_DMA_TX_PERI_SEL,
4527 RTE_USART10_DMA_RX_DMA_BASE, RTE_USART10_DMA_RX_CH, RTE_USART10_DMA_RX_PERI_SEL,
4528
4529 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4530 RTE_USART10_DMA_TX_DMAMUX_BASE, RTE_USART10_DMA_RX_DMAMUX_BASE,
4531 #endif
4532 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
4533 RTE_USART10_DMAMUX_TX_CH, RTE_USART10_DMAMUX_RX_CH
4534 #endif
4535 };
4536
4537 static lpuart_dma_handle_t LPUART10_DmaHandle;
4538 static dma_handle_t LPUART10_DmaRxHandle;
4539 static dma_handle_t LPUART10_DmaTxHandle;
4540
4541 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4542 ARMCC_SECTION("lpuart10_dma_driver_state")
4543 static cmsis_lpuart_dma_driver_state_t LPUART10_DmaDriverState = {
4544 #else
4545 static cmsis_lpuart_dma_driver_state_t LPUART10_DmaDriverState = {
4546 #endif
4547 &LPUART10_Resource, &LPUART10_DmaResource, &LPUART10_DmaHandle, &LPUART10_DmaRxHandle, &LPUART10_DmaTxHandle,
4548 };
4549
LPUART10_DmaInitialize(ARM_USART_SignalEvent_t cb_event)4550 static int32_t LPUART10_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
4551 {
4552 #ifdef RTE_USART10_PIN_INIT
4553 RTE_USART10_PIN_INIT();
4554 #endif
4555 return LPUART_DmaInitialize(cb_event, &LPUART10_DmaDriverState);
4556 }
4557
LPUART10_DmaUninitialize(void)4558 static int32_t LPUART10_DmaUninitialize(void)
4559 {
4560 #ifdef RTE_USART10_PIN_DEINIT
4561 RTE_USART10_PIN_DEINIT();
4562 #endif
4563 return LPUART_DmaUninitialize(&LPUART10_DmaDriverState);
4564 }
4565
LPUART10_DmaPowerControl(ARM_POWER_STATE state)4566 static int32_t LPUART10_DmaPowerControl(ARM_POWER_STATE state)
4567 {
4568 return LPUART_DmaPowerControl(state, &LPUART10_DmaDriverState);
4569 }
4570
LPUART10_DmaSend(const void * data,uint32_t num)4571 static int32_t LPUART10_DmaSend(const void *data, uint32_t num)
4572 {
4573 return LPUART_DmaSend(data, num, &LPUART10_DmaDriverState);
4574 }
4575
LPUART10_DmaReceive(void * data,uint32_t num)4576 static int32_t LPUART10_DmaReceive(void *data, uint32_t num)
4577 {
4578 return LPUART_DmaReceive(data, num, &LPUART10_DmaDriverState);
4579 }
4580
LPUART10_DmaTransfer(const void * data_out,void * data_in,uint32_t num)4581 static int32_t LPUART10_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
4582 {
4583 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART10_DmaDriverState);
4584 }
4585
LPUART10_DmaGetTxCount(void)4586 static uint32_t LPUART10_DmaGetTxCount(void)
4587 {
4588 return LPUART_DmaGetTxCount(&LPUART10_DmaDriverState);
4589 }
4590
LPUART10_DmaGetRxCount(void)4591 static uint32_t LPUART10_DmaGetRxCount(void)
4592 {
4593 return LPUART_DmaGetRxCount(&LPUART10_DmaDriverState);
4594 }
4595
LPUART10_DmaControl(uint32_t control,uint32_t arg)4596 static int32_t LPUART10_DmaControl(uint32_t control, uint32_t arg)
4597 {
4598 return LPUART_DmaControl(control, arg, &LPUART10_DmaDriverState);
4599 }
4600
LPUART10_DmaGetStatus(void)4601 static ARM_USART_STATUS LPUART10_DmaGetStatus(void)
4602 {
4603 return LPUART_DmaGetStatus(&LPUART10_DmaDriverState);
4604 }
4605
4606 /* LPUART10 Driver Control Block */
4607
4608 #endif
4609
4610 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4611
4612 static cmsis_lpuart_edma_resource_t LPUART10_EdmaResource = {
4613 RTE_USART10_DMA_TX_DMA_BASE, RTE_USART10_DMA_TX_CH, RTE_USART10_DMA_TX_PERI_SEL,
4614 RTE_USART10_DMA_RX_DMA_BASE, RTE_USART10_DMA_RX_CH, RTE_USART10_DMA_RX_PERI_SEL,
4615
4616 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4617 RTE_USART10_DMA_TX_DMAMUX_BASE, RTE_USART10_DMA_RX_DMAMUX_BASE,
4618 #endif
4619 };
4620
4621 static lpuart_edma_handle_t LPUART10_EdmaHandle;
4622 static edma_handle_t LPUART10_EdmaRxHandle;
4623 static edma_handle_t LPUART10_EdmaTxHandle;
4624
4625 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4626 ARMCC_SECTION("lpuart10_edma_driver_state")
4627 static cmsis_lpuart_edma_driver_state_t LPUART10_EdmaDriverState = {
4628 #else
4629 static cmsis_lpuart_edma_driver_state_t LPUART10_EdmaDriverState = {
4630 #endif
4631 &LPUART10_Resource, &LPUART10_EdmaResource, &LPUART10_EdmaHandle, &LPUART10_EdmaRxHandle, &LPUART10_EdmaTxHandle,
4632 };
4633
LPUART10_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)4634 static int32_t LPUART10_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
4635 {
4636 #ifdef RTE_USART10_PIN_INIT
4637 RTE_USART10_PIN_INIT();
4638 #endif
4639 return LPUART_EdmaInitialize(cb_event, &LPUART10_EdmaDriverState);
4640 }
4641
LPUART10_EdmaUninitialize(void)4642 static int32_t LPUART10_EdmaUninitialize(void)
4643 {
4644 #ifdef RTE_USART10_PIN_DEINIT
4645 RTE_USART10_PIN_DEINIT();
4646 #endif
4647 return LPUART_EdmaUninitialize(&LPUART10_EdmaDriverState);
4648 }
4649
LPUART10_EdmaPowerControl(ARM_POWER_STATE state)4650 static int32_t LPUART10_EdmaPowerControl(ARM_POWER_STATE state)
4651 {
4652 return LPUART_EdmaPowerControl(state, &LPUART10_EdmaDriverState);
4653 }
4654
LPUART10_EdmaSend(const void * data,uint32_t num)4655 static int32_t LPUART10_EdmaSend(const void *data, uint32_t num)
4656 {
4657 return LPUART_EdmaSend(data, num, &LPUART10_EdmaDriverState);
4658 }
4659
LPUART10_EdmaReceive(void * data,uint32_t num)4660 static int32_t LPUART10_EdmaReceive(void *data, uint32_t num)
4661 {
4662 return LPUART_EdmaReceive(data, num, &LPUART10_EdmaDriverState);
4663 }
4664
LPUART10_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4665 static int32_t LPUART10_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4666 {
4667 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART10_EdmaDriverState);
4668 }
4669
LPUART10_EdmaGetTxCount(void)4670 static uint32_t LPUART10_EdmaGetTxCount(void)
4671 {
4672 return LPUART_EdmaGetTxCount(&LPUART10_EdmaDriverState);
4673 }
4674
LPUART10_EdmaGetRxCount(void)4675 static uint32_t LPUART10_EdmaGetRxCount(void)
4676 {
4677 return LPUART_EdmaGetRxCount(&LPUART10_EdmaDriverState);
4678 }
4679
LPUART10_EdmaControl(uint32_t control,uint32_t arg)4680 static int32_t LPUART10_EdmaControl(uint32_t control, uint32_t arg)
4681 {
4682 return LPUART_EdmaControl(control, arg, &LPUART10_EdmaDriverState);
4683 }
4684
LPUART10_EdmaGetStatus(void)4685 static ARM_USART_STATUS LPUART10_EdmaGetStatus(void)
4686 {
4687 return LPUART_EdmaGetStatus(&LPUART10_EdmaDriverState);
4688 }
4689
4690 #endif
4691
4692 #else
4693
4694 static lpuart_handle_t LPUART10_Handle;
4695
4696 #if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1)
4697 static uint8_t lpuart10_rxRingBuffer[USART_RX_BUFFER_LEN];
4698 #endif
4699
4700 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4701 ARMCC_SECTION("lpuart10_non_blocking_driver_state")
4702 static cmsis_lpuart_non_blocking_driver_state_t LPUART10_NonBlockingDriverState = {
4703 #else
4704 static cmsis_lpuart_non_blocking_driver_state_t LPUART10_NonBlockingDriverState = {
4705 #endif
4706 &LPUART10_Resource,
4707 &LPUART10_Handle,
4708 };
4709
LPUART10_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)4710 static int32_t LPUART10_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
4711 {
4712 #ifdef RTE_USART10_PIN_INIT
4713 RTE_USART10_PIN_INIT();
4714 #endif
4715 return LPUART_NonBlockingInitialize(cb_event, &LPUART10_NonBlockingDriverState);
4716 }
4717
LPUART10_NonBlockingUninitialize(void)4718 static int32_t LPUART10_NonBlockingUninitialize(void)
4719 {
4720 #ifdef RTE_USART10_PIN_DEINIT
4721 RTE_USART10_PIN_DEINIT();
4722 #endif
4723 return LPUART_NonBlockingUninitialize(&LPUART10_NonBlockingDriverState);
4724 }
4725
LPUART10_NonBlockingPowerControl(ARM_POWER_STATE state)4726 static int32_t LPUART10_NonBlockingPowerControl(ARM_POWER_STATE state)
4727 {
4728 int32_t result;
4729
4730 result = LPUART_NonBlockingPowerControl(state, &LPUART10_NonBlockingDriverState);
4731
4732 #if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1)
4733 if ((state == ARM_POWER_FULL) && (LPUART10_NonBlockingDriverState.handle->rxRingBuffer == NULL))
4734 {
4735 LPUART_TransferStartRingBuffer(LPUART10_NonBlockingDriverState.resource->base,
4736 LPUART10_NonBlockingDriverState.handle, lpuart10_rxRingBuffer,
4737 USART_RX_BUFFER_LEN);
4738 }
4739 #endif
4740
4741 return result;
4742 }
4743
LPUART10_NonBlockingSend(const void * data,uint32_t num)4744 static int32_t LPUART10_NonBlockingSend(const void *data, uint32_t num)
4745 {
4746 return LPUART_NonBlockingSend(data, num, &LPUART10_NonBlockingDriverState);
4747 }
4748
LPUART10_NonBlockingReceive(void * data,uint32_t num)4749 static int32_t LPUART10_NonBlockingReceive(void *data, uint32_t num)
4750 {
4751 return LPUART_NonBlockingReceive(data, num, &LPUART10_NonBlockingDriverState);
4752 }
4753
LPUART10_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)4754 static int32_t LPUART10_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
4755 {
4756 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART10_NonBlockingDriverState);
4757 }
4758
LPUART10_NonBlockingGetTxCount(void)4759 static uint32_t LPUART10_NonBlockingGetTxCount(void)
4760 {
4761 return LPUART_NonBlockingGetTxCount(&LPUART10_NonBlockingDriverState);
4762 }
4763
LPUART10_NonBlockingGetRxCount(void)4764 static uint32_t LPUART10_NonBlockingGetRxCount(void)
4765 {
4766 return LPUART_NonBlockingGetRxCount(&LPUART10_NonBlockingDriverState);
4767 }
4768
LPUART10_NonBlockingControl(uint32_t control,uint32_t arg)4769 static int32_t LPUART10_NonBlockingControl(uint32_t control, uint32_t arg)
4770 {
4771 int32_t result;
4772
4773 result = LPUART_NonBlockingControl(control, arg, &LPUART10_NonBlockingDriverState);
4774 if (ARM_DRIVER_OK != result)
4775 {
4776 return result;
4777 }
4778
4779 /* Enable the receive interrupts if ring buffer is used */
4780 if (LPUART10_NonBlockingDriverState.handle->rxRingBuffer != NULL)
4781 {
4782 LPUART_EnableInterrupts(
4783 LPUART10_NonBlockingDriverState.resource->base,
4784 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
4785 }
4786
4787 return ARM_DRIVER_OK;
4788 }
4789
LPUART10_NonBlockingGetStatus(void)4790 static ARM_USART_STATUS LPUART10_NonBlockingGetStatus(void)
4791 {
4792 return LPUART_NonBlockingGetStatus(&LPUART10_NonBlockingDriverState);
4793 }
4794
4795 #endif
4796
4797 ARM_DRIVER_USART Driver_USART10 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
4798 #if defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN
4799 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4800 LPUART10_EdmaInitialize, LPUART10_EdmaUninitialize, LPUART10_EdmaPowerControl,
4801 LPUART10_EdmaSend, LPUART10_EdmaReceive, LPUART10_EdmaTransfer,
4802 LPUART10_EdmaGetTxCount, LPUART10_EdmaGetRxCount, LPUART10_EdmaControl,
4803 LPUART10_EdmaGetStatus,
4804 #else
4805 LPUART10_DmaInitialize, LPUART10_DmaUninitialize, LPUART10_DmaPowerControl,
4806 LPUART10_DmaSend, LPUART10_DmaReceive, LPUART10_DmaTransfer,
4807 LPUART10_DmaGetTxCount, LPUART10_DmaGetRxCount, LPUART10_DmaControl,
4808 LPUART10_DmaGetStatus,
4809 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
4810 #else
4811 LPUART10_NonBlockingInitialize,
4812 LPUART10_NonBlockingUninitialize,
4813 LPUART10_NonBlockingPowerControl,
4814 LPUART10_NonBlockingSend,
4815 LPUART10_NonBlockingReceive,
4816 LPUART10_NonBlockingTransfer,
4817 LPUART10_NonBlockingGetTxCount,
4818 LPUART10_NonBlockingGetRxCount,
4819 LPUART10_NonBlockingControl,
4820 LPUART10_NonBlockingGetStatus,
4821 #endif /* RTE_USART10_DMA_EN */
4822 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
4823
4824 #endif /* LPUART10 */
4825
4826 #if defined(LPUART11) && defined(RTE_USART11) && RTE_USART11
4827
4828 /* User needs to provide the implementation for LPUART11_GetFreq/InitPins/DeinitPins
4829 in the application for enabling according instance. */
4830 extern uint32_t LPUART11_GetFreq(void);
4831
4832 static cmsis_lpuart_resource_t LPUART11_Resource = {LPUART11, LPUART11_GetFreq};
4833
4834 #if defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN
4835
4836 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
4837
4838 static cmsis_lpuart_dma_resource_t LPUART11_DmaResource = {
4839 RTE_USART11_DMA_TX_DMA_BASE, RTE_USART11_DMA_TX_CH, RTE_USART11_DMA_TX_PERI_SEL,
4840 RTE_USART11_DMA_RX_DMA_BASE, RTE_USART11_DMA_RX_CH, RTE_USART11_DMA_RX_PERI_SEL,
4841
4842 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4843 RTE_USART11_DMA_TX_DMAMUX_BASE, RTE_USART11_DMA_RX_DMAMUX_BASE,
4844 #endif
4845 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
4846 RTE_USART11_DMAMUX_TX_CH, RTE_USART11_DMAMUX_RX_CH
4847 #endif
4848 };
4849
4850 static lpuart_dma_handle_t LPUART11_DmaHandle;
4851 static dma_handle_t LPUART11_DmaRxHandle;
4852 static dma_handle_t LPUART11_DmaTxHandle;
4853
4854 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4855 ARMCC_SECTION("lpuart11_dma_driver_state")
4856 static cmsis_lpuart_dma_driver_state_t LPUART11_DmaDriverState = {
4857 #else
4858 static cmsis_lpuart_dma_driver_state_t LPUART11_DmaDriverState = {
4859 #endif
4860 &LPUART11_Resource, &LPUART11_DmaResource, &LPUART11_DmaHandle, &LPUART11_DmaRxHandle, &LPUART11_DmaTxHandle,
4861 };
4862
LPUART11_DmaInitialize(ARM_USART_SignalEvent_t cb_event)4863 static int32_t LPUART11_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
4864 {
4865 #ifdef RTE_USART11_PIN_INIT
4866 RTE_USART11_PIN_INIT();
4867 #endif
4868 return LPUART_DmaInitialize(cb_event, &LPUART11_DmaDriverState);
4869 }
4870
LPUART11_DmaUninitialize(void)4871 static int32_t LPUART11_DmaUninitialize(void)
4872 {
4873 #ifdef RTE_USART11_PIN_DEINIT
4874 RTE_USART11_PIN_DEINIT();
4875 #endif
4876 return LPUART_DmaUninitialize(&LPUART11_DmaDriverState);
4877 }
4878
LPUART11_DmaPowerControl(ARM_POWER_STATE state)4879 static int32_t LPUART11_DmaPowerControl(ARM_POWER_STATE state)
4880 {
4881 return LPUART_DmaPowerControl(state, &LPUART11_DmaDriverState);
4882 }
4883
LPUART11_DmaSend(const void * data,uint32_t num)4884 static int32_t LPUART11_DmaSend(const void *data, uint32_t num)
4885 {
4886 return LPUART_DmaSend(data, num, &LPUART11_DmaDriverState);
4887 }
4888
LPUART11_DmaReceive(void * data,uint32_t num)4889 static int32_t LPUART11_DmaReceive(void *data, uint32_t num)
4890 {
4891 return LPUART_DmaReceive(data, num, &LPUART11_DmaDriverState);
4892 }
4893
LPUART11_DmaTransfer(const void * data_out,void * data_in,uint32_t num)4894 static int32_t LPUART11_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
4895 {
4896 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART11_DmaDriverState);
4897 }
4898
LPUART11_DmaGetTxCount(void)4899 static uint32_t LPUART11_DmaGetTxCount(void)
4900 {
4901 return LPUART_DmaGetTxCount(&LPUART11_DmaDriverState);
4902 }
4903
LPUART11_DmaGetRxCount(void)4904 static uint32_t LPUART11_DmaGetRxCount(void)
4905 {
4906 return LPUART_DmaGetRxCount(&LPUART11_DmaDriverState);
4907 }
4908
LPUART11_DmaControl(uint32_t control,uint32_t arg)4909 static int32_t LPUART11_DmaControl(uint32_t control, uint32_t arg)
4910 {
4911 return LPUART_DmaControl(control, arg, &LPUART11_DmaDriverState);
4912 }
4913
LPUART11_DmaGetStatus(void)4914 static ARM_USART_STATUS LPUART11_DmaGetStatus(void)
4915 {
4916 return LPUART_DmaGetStatus(&LPUART11_DmaDriverState);
4917 }
4918
4919 /* LPUART11 Driver Control Block */
4920
4921 #endif
4922
4923 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4924
4925 static cmsis_lpuart_edma_resource_t LPUART11_EdmaResource = {
4926 RTE_USART11_DMA_TX_DMA_BASE, RTE_USART11_DMA_TX_CH, RTE_USART11_DMA_TX_PERI_SEL,
4927 RTE_USART11_DMA_RX_DMA_BASE, RTE_USART11_DMA_RX_CH, RTE_USART11_DMA_RX_PERI_SEL,
4928
4929 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4930 RTE_USART11_DMA_TX_DMAMUX_BASE, RTE_USART11_DMA_RX_DMAMUX_BASE,
4931 #endif
4932 };
4933
4934 static lpuart_edma_handle_t LPUART11_EdmaHandle;
4935 static edma_handle_t LPUART11_EdmaRxHandle;
4936 static edma_handle_t LPUART11_EdmaTxHandle;
4937
4938 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4939 ARMCC_SECTION("lpuart11_edma_driver_state")
4940 static cmsis_lpuart_edma_driver_state_t LPUART11_EdmaDriverState = {
4941 #else
4942 static cmsis_lpuart_edma_driver_state_t LPUART11_EdmaDriverState = {
4943 #endif
4944 &LPUART11_Resource, &LPUART11_EdmaResource, &LPUART11_EdmaHandle, &LPUART11_EdmaRxHandle, &LPUART11_EdmaTxHandle,
4945 };
4946
LPUART11_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)4947 static int32_t LPUART11_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
4948 {
4949 #ifdef RTE_USART11_PIN_INIT
4950 RTE_USART11_PIN_INIT();
4951 #endif
4952 return LPUART_EdmaInitialize(cb_event, &LPUART11_EdmaDriverState);
4953 }
4954
LPUART11_EdmaUninitialize(void)4955 static int32_t LPUART11_EdmaUninitialize(void)
4956 {
4957 #ifdef RTE_USART11_PIN_DEINIT
4958 RTE_USART11_PIN_DEINIT();
4959 #endif
4960 return LPUART_EdmaUninitialize(&LPUART11_EdmaDriverState);
4961 }
4962
LPUART11_EdmaPowerControl(ARM_POWER_STATE state)4963 static int32_t LPUART11_EdmaPowerControl(ARM_POWER_STATE state)
4964 {
4965 return LPUART_EdmaPowerControl(state, &LPUART11_EdmaDriverState);
4966 }
4967
LPUART11_EdmaSend(const void * data,uint32_t num)4968 static int32_t LPUART11_EdmaSend(const void *data, uint32_t num)
4969 {
4970 return LPUART_EdmaSend(data, num, &LPUART11_EdmaDriverState);
4971 }
4972
LPUART11_EdmaReceive(void * data,uint32_t num)4973 static int32_t LPUART11_EdmaReceive(void *data, uint32_t num)
4974 {
4975 return LPUART_EdmaReceive(data, num, &LPUART11_EdmaDriverState);
4976 }
4977
LPUART11_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4978 static int32_t LPUART11_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4979 {
4980 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART11_EdmaDriverState);
4981 }
4982
LPUART11_EdmaGetTxCount(void)4983 static uint32_t LPUART11_EdmaGetTxCount(void)
4984 {
4985 return LPUART_EdmaGetTxCount(&LPUART11_EdmaDriverState);
4986 }
4987
LPUART11_EdmaGetRxCount(void)4988 static uint32_t LPUART11_EdmaGetRxCount(void)
4989 {
4990 return LPUART_EdmaGetRxCount(&LPUART11_EdmaDriverState);
4991 }
4992
LPUART11_EdmaControl(uint32_t control,uint32_t arg)4993 static int32_t LPUART11_EdmaControl(uint32_t control, uint32_t arg)
4994 {
4995 return LPUART_EdmaControl(control, arg, &LPUART11_EdmaDriverState);
4996 }
4997
LPUART11_EdmaGetStatus(void)4998 static ARM_USART_STATUS LPUART11_EdmaGetStatus(void)
4999 {
5000 return LPUART_EdmaGetStatus(&LPUART11_EdmaDriverState);
5001 }
5002
5003 #endif
5004
5005 #else
5006
5007 static lpuart_handle_t LPUART11_Handle;
5008
5009 #if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1)
5010 static uint8_t lpuart11_rxRingBuffer[USART_RX_BUFFER_LEN];
5011 #endif
5012
5013 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5014 ARMCC_SECTION("lpuart11_non_blocking_driver_state")
5015 static cmsis_lpuart_non_blocking_driver_state_t LPUART11_NonBlockingDriverState = {
5016 #else
5017 static cmsis_lpuart_non_blocking_driver_state_t LPUART11_NonBlockingDriverState = {
5018 #endif
5019 &LPUART11_Resource,
5020 &LPUART11_Handle,
5021 };
5022
LPUART11_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)5023 static int32_t LPUART11_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
5024 {
5025 #ifdef RTE_USART11_PIN_INIT
5026 RTE_USART11_PIN_INIT();
5027 #endif
5028 return LPUART_NonBlockingInitialize(cb_event, &LPUART11_NonBlockingDriverState);
5029 }
5030
LPUART11_NonBlockingUninitialize(void)5031 static int32_t LPUART11_NonBlockingUninitialize(void)
5032 {
5033 #ifdef RTE_USART11_PIN_DEINIT
5034 RTE_USART11_PIN_DEINIT();
5035 #endif
5036 return LPUART_NonBlockingUninitialize(&LPUART11_NonBlockingDriverState);
5037 }
5038
LPUART11_NonBlockingPowerControl(ARM_POWER_STATE state)5039 static int32_t LPUART11_NonBlockingPowerControl(ARM_POWER_STATE state)
5040 {
5041 int32_t result;
5042
5043 result = LPUART_NonBlockingPowerControl(state, &LPUART11_NonBlockingDriverState);
5044
5045 #if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1)
5046 if ((state == ARM_POWER_FULL) && (LPUART11_NonBlockingDriverState.handle->rxRingBuffer == NULL))
5047 {
5048 LPUART_TransferStartRingBuffer(LPUART11_NonBlockingDriverState.resource->base,
5049 LPUART11_NonBlockingDriverState.handle, lpuart11_rxRingBuffer,
5050 USART_RX_BUFFER_LEN);
5051 }
5052 #endif
5053
5054 return result;
5055 }
5056
LPUART11_NonBlockingSend(const void * data,uint32_t num)5057 static int32_t LPUART11_NonBlockingSend(const void *data, uint32_t num)
5058 {
5059 return LPUART_NonBlockingSend(data, num, &LPUART11_NonBlockingDriverState);
5060 }
5061
LPUART11_NonBlockingReceive(void * data,uint32_t num)5062 static int32_t LPUART11_NonBlockingReceive(void *data, uint32_t num)
5063 {
5064 return LPUART_NonBlockingReceive(data, num, &LPUART11_NonBlockingDriverState);
5065 }
5066
LPUART11_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)5067 static int32_t LPUART11_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
5068 {
5069 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART11_NonBlockingDriverState);
5070 }
5071
LPUART11_NonBlockingGetTxCount(void)5072 static uint32_t LPUART11_NonBlockingGetTxCount(void)
5073 {
5074 return LPUART_NonBlockingGetTxCount(&LPUART11_NonBlockingDriverState);
5075 }
5076
LPUART11_NonBlockingGetRxCount(void)5077 static uint32_t LPUART11_NonBlockingGetRxCount(void)
5078 {
5079 return LPUART_NonBlockingGetRxCount(&LPUART11_NonBlockingDriverState);
5080 }
5081
LPUART11_NonBlockingControl(uint32_t control,uint32_t arg)5082 static int32_t LPUART11_NonBlockingControl(uint32_t control, uint32_t arg)
5083 {
5084 int32_t result;
5085
5086 result = LPUART_NonBlockingControl(control, arg, &LPUART11_NonBlockingDriverState);
5087 if (ARM_DRIVER_OK != result)
5088 {
5089 return result;
5090 }
5091
5092 /* Enable the receive interrupts if ring buffer is used */
5093 if (LPUART11_NonBlockingDriverState.handle->rxRingBuffer != NULL)
5094 {
5095 LPUART_EnableInterrupts(
5096 LPUART11_NonBlockingDriverState.resource->base,
5097 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
5098 }
5099
5100 return ARM_DRIVER_OK;
5101 }
5102
LPUART11_NonBlockingGetStatus(void)5103 static ARM_USART_STATUS LPUART11_NonBlockingGetStatus(void)
5104 {
5105 return LPUART_NonBlockingGetStatus(&LPUART11_NonBlockingDriverState);
5106 }
5107
5108 #endif
5109
5110 ARM_DRIVER_USART Driver_USART11 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
5111 #if defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN
5112 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5113 LPUART11_EdmaInitialize, LPUART11_EdmaUninitialize, LPUART11_EdmaPowerControl,
5114 LPUART11_EdmaSend, LPUART11_EdmaReceive, LPUART11_EdmaTransfer,
5115 LPUART11_EdmaGetTxCount, LPUART11_EdmaGetRxCount, LPUART11_EdmaControl,
5116 LPUART11_EdmaGetStatus,
5117 #else
5118 LPUART11_DmaInitialize, LPUART11_DmaUninitialize, LPUART11_DmaPowerControl,
5119 LPUART11_DmaSend, LPUART11_DmaReceive, LPUART11_DmaTransfer,
5120 LPUART11_DmaGetTxCount, LPUART11_DmaGetRxCount, LPUART11_DmaControl,
5121 LPUART11_DmaGetStatus,
5122 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
5123 #else
5124 LPUART11_NonBlockingInitialize,
5125 LPUART11_NonBlockingUninitialize,
5126 LPUART11_NonBlockingPowerControl,
5127 LPUART11_NonBlockingSend,
5128 LPUART11_NonBlockingReceive,
5129 LPUART11_NonBlockingTransfer,
5130 LPUART11_NonBlockingGetTxCount,
5131 LPUART11_NonBlockingGetRxCount,
5132 LPUART11_NonBlockingControl,
5133 LPUART11_NonBlockingGetStatus,
5134 #endif /* RTE_USART11_DMA_EN */
5135 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
5136
5137 #endif /* LPUART11 */
5138
5139 #if defined(LPUART12) && defined(RTE_USART12) && RTE_USART12
5140
5141 /* User needs to provide the implementation for LPUART12_GetFreq/InitPins/DeinitPins
5142 in the application for enabling according instance. */
5143 extern uint32_t LPUART12_GetFreq(void);
5144
5145 static cmsis_lpuart_resource_t LPUART12_Resource = {LPUART12, LPUART12_GetFreq};
5146
5147 #if defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN
5148
5149 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
5150
5151 static cmsis_lpuart_dma_resource_t LPUART12_DmaResource = {
5152 RTE_USART12_DMA_TX_DMA_BASE, RTE_USART12_DMA_TX_CH, RTE_USART12_DMA_TX_PERI_SEL,
5153 RTE_USART12_DMA_RX_DMA_BASE, RTE_USART12_DMA_RX_CH, RTE_USART12_DMA_RX_PERI_SEL,
5154
5155 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5156 RTE_USART12_DMA_TX_DMAMUX_BASE, RTE_USART12_DMA_RX_DMAMUX_BASE,
5157 #endif
5158 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
5159 RTE_USART12_DMAMUX_TX_CH, RTE_USART12_DMAMUX_RX_CH
5160 #endif
5161 };
5162
5163 static lpuart_dma_handle_t LPUART12_DmaHandle;
5164 static dma_handle_t LPUART12_DmaRxHandle;
5165 static dma_handle_t LPUART12_DmaTxHandle;
5166
5167 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5168 ARMCC_SECTION("lpuart12_dma_driver_state")
5169 static cmsis_lpuart_dma_driver_state_t LPUART12_DmaDriverState = {
5170 #else
5171 static cmsis_lpuart_dma_driver_state_t LPUART12_DmaDriverState = {
5172 #endif
5173 &LPUART12_Resource, &LPUART12_DmaResource, &LPUART12_DmaHandle, &LPUART12_DmaRxHandle, &LPUART12_DmaTxHandle,
5174 };
5175
LPUART12_DmaInitialize(ARM_USART_SignalEvent_t cb_event)5176 static int32_t LPUART12_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
5177 {
5178 #ifdef RTE_USART12_PIN_INIT
5179 RTE_USART12_PIN_INIT();
5180 #endif
5181 return LPUART_DmaInitialize(cb_event, &LPUART12_DmaDriverState);
5182 }
5183
LPUART12_DmaUninitialize(void)5184 static int32_t LPUART12_DmaUninitialize(void)
5185 {
5186 #ifdef RTE_USART12_PIN_DEINIT
5187 RTE_USART12_PIN_DEINIT();
5188 #endif
5189 return LPUART_DmaUninitialize(&LPUART12_DmaDriverState);
5190 }
5191
LPUART12_DmaPowerControl(ARM_POWER_STATE state)5192 static int32_t LPUART12_DmaPowerControl(ARM_POWER_STATE state)
5193 {
5194 return LPUART_DmaPowerControl(state, &LPUART12_DmaDriverState);
5195 }
5196
LPUART12_DmaSend(const void * data,uint32_t num)5197 static int32_t LPUART12_DmaSend(const void *data, uint32_t num)
5198 {
5199 return LPUART_DmaSend(data, num, &LPUART12_DmaDriverState);
5200 }
5201
LPUART12_DmaReceive(void * data,uint32_t num)5202 static int32_t LPUART12_DmaReceive(void *data, uint32_t num)
5203 {
5204 return LPUART_DmaReceive(data, num, &LPUART12_DmaDriverState);
5205 }
5206
LPUART12_DmaTransfer(const void * data_out,void * data_in,uint32_t num)5207 static int32_t LPUART12_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
5208 {
5209 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART12_DmaDriverState);
5210 }
5211
LPUART12_DmaGetTxCount(void)5212 static uint32_t LPUART12_DmaGetTxCount(void)
5213 {
5214 return LPUART_DmaGetTxCount(&LPUART12_DmaDriverState);
5215 }
5216
LPUART12_DmaGetRxCount(void)5217 static uint32_t LPUART12_DmaGetRxCount(void)
5218 {
5219 return LPUART_DmaGetRxCount(&LPUART12_DmaDriverState);
5220 }
5221
LPUART12_DmaControl(uint32_t control,uint32_t arg)5222 static int32_t LPUART12_DmaControl(uint32_t control, uint32_t arg)
5223 {
5224 return LPUART_DmaControl(control, arg, &LPUART12_DmaDriverState);
5225 }
5226
LPUART12_DmaGetStatus(void)5227 static ARM_USART_STATUS LPUART12_DmaGetStatus(void)
5228 {
5229 return LPUART_DmaGetStatus(&LPUART12_DmaDriverState);
5230 }
5231
5232 /* LPUART12 Driver Control Block */
5233
5234 #endif
5235
5236 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5237
5238 static cmsis_lpuart_edma_resource_t LPUART12_EdmaResource = {
5239 RTE_USART12_DMA_TX_DMA_BASE, RTE_USART12_DMA_TX_CH, RTE_USART12_DMA_TX_PERI_SEL,
5240 RTE_USART12_DMA_RX_DMA_BASE, RTE_USART12_DMA_RX_CH, RTE_USART12_DMA_RX_PERI_SEL,
5241
5242 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5243 RTE_USART12_DMA_TX_DMAMUX_BASE, RTE_USART12_DMA_RX_DMAMUX_BASE,
5244 #endif
5245 };
5246
5247 static lpuart_edma_handle_t LPUART12_EdmaHandle;
5248 static edma_handle_t LPUART12_EdmaRxHandle;
5249 static edma_handle_t LPUART12_EdmaTxHandle;
5250
5251 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5252 ARMCC_SECTION("lpuart12_edma_driver_state")
5253 static cmsis_lpuart_edma_driver_state_t LPUART12_EdmaDriverState = {
5254 #else
5255 static cmsis_lpuart_edma_driver_state_t LPUART12_EdmaDriverState = {
5256 #endif
5257 &LPUART12_Resource, &LPUART12_EdmaResource, &LPUART12_EdmaHandle, &LPUART12_EdmaRxHandle, &LPUART12_EdmaTxHandle,
5258 };
5259
LPUART12_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)5260 static int32_t LPUART12_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
5261 {
5262 #ifdef RTE_USART12_PIN_INIT
5263 RTE_USART12_PIN_INIT();
5264 #endif
5265 return LPUART_EdmaInitialize(cb_event, &LPUART12_EdmaDriverState);
5266 }
5267
LPUART12_EdmaUninitialize(void)5268 static int32_t LPUART12_EdmaUninitialize(void)
5269 {
5270 #ifdef RTE_USART12_PIN_DEINIT
5271 RTE_USART12_PIN_DEINIT();
5272 #endif
5273 return LPUART_EdmaUninitialize(&LPUART12_EdmaDriverState);
5274 }
5275
LPUART12_EdmaPowerControl(ARM_POWER_STATE state)5276 static int32_t LPUART12_EdmaPowerControl(ARM_POWER_STATE state)
5277 {
5278 return LPUART_EdmaPowerControl(state, &LPUART12_EdmaDriverState);
5279 }
5280
LPUART12_EdmaSend(const void * data,uint32_t num)5281 static int32_t LPUART12_EdmaSend(const void *data, uint32_t num)
5282 {
5283 return LPUART_EdmaSend(data, num, &LPUART12_EdmaDriverState);
5284 }
5285
LPUART12_EdmaReceive(void * data,uint32_t num)5286 static int32_t LPUART12_EdmaReceive(void *data, uint32_t num)
5287 {
5288 return LPUART_EdmaReceive(data, num, &LPUART12_EdmaDriverState);
5289 }
5290
LPUART12_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)5291 static int32_t LPUART12_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
5292 {
5293 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART12_EdmaDriverState);
5294 }
5295
LPUART12_EdmaGetTxCount(void)5296 static uint32_t LPUART12_EdmaGetTxCount(void)
5297 {
5298 return LPUART_EdmaGetTxCount(&LPUART12_EdmaDriverState);
5299 }
5300
LPUART12_EdmaGetRxCount(void)5301 static uint32_t LPUART12_EdmaGetRxCount(void)
5302 {
5303 return LPUART_EdmaGetRxCount(&LPUART12_EdmaDriverState);
5304 }
5305
LPUART12_EdmaControl(uint32_t control,uint32_t arg)5306 static int32_t LPUART12_EdmaControl(uint32_t control, uint32_t arg)
5307 {
5308 return LPUART_EdmaControl(control, arg, &LPUART12_EdmaDriverState);
5309 }
5310
LPUART12_EdmaGetStatus(void)5311 static ARM_USART_STATUS LPUART12_EdmaGetStatus(void)
5312 {
5313 return LPUART_EdmaGetStatus(&LPUART12_EdmaDriverState);
5314 }
5315
5316 #endif
5317
5318 #else
5319
5320 static lpuart_handle_t LPUART12_Handle;
5321
5322 #if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1)
5323 static uint8_t lpuart12_rxRingBuffer[USART_RX_BUFFER_LEN];
5324 #endif
5325
5326 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5327 ARMCC_SECTION("lpuart12_non_blocking_driver_state")
5328 static cmsis_lpuart_non_blocking_driver_state_t LPUART12_NonBlockingDriverState = {
5329 #else
5330 static cmsis_lpuart_non_blocking_driver_state_t LPUART12_NonBlockingDriverState = {
5331 #endif
5332 &LPUART12_Resource,
5333 &LPUART12_Handle,
5334 };
5335
LPUART12_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)5336 static int32_t LPUART12_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
5337 {
5338 #ifdef RTE_USART12_PIN_INIT
5339 RTE_USART12_PIN_INIT();
5340 #endif
5341 return LPUART_NonBlockingInitialize(cb_event, &LPUART12_NonBlockingDriverState);
5342 }
5343
LPUART12_NonBlockingUninitialize(void)5344 static int32_t LPUART12_NonBlockingUninitialize(void)
5345 {
5346 #ifdef RTE_USART12_PIN_DEINIT
5347 RTE_USART12_PIN_DEINIT();
5348 #endif
5349 return LPUART_NonBlockingUninitialize(&LPUART12_NonBlockingDriverState);
5350 }
5351
LPUART12_NonBlockingPowerControl(ARM_POWER_STATE state)5352 static int32_t LPUART12_NonBlockingPowerControl(ARM_POWER_STATE state)
5353 {
5354 int32_t result;
5355
5356 result = LPUART_NonBlockingPowerControl(state, &LPUART12_NonBlockingDriverState);
5357
5358 #if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1)
5359 if ((state == ARM_POWER_FULL) && (LPUART12_NonBlockingDriverState.handle->rxRingBuffer == NULL))
5360 {
5361 LPUART_TransferStartRingBuffer(LPUART12_NonBlockingDriverState.resource->base,
5362 LPUART12_NonBlockingDriverState.handle, lpuart12_rxRingBuffer,
5363 USART_RX_BUFFER_LEN);
5364 }
5365 #endif
5366
5367 return result;
5368 }
5369
LPUART12_NonBlockingSend(const void * data,uint32_t num)5370 static int32_t LPUART12_NonBlockingSend(const void *data, uint32_t num)
5371 {
5372 return LPUART_NonBlockingSend(data, num, &LPUART12_NonBlockingDriverState);
5373 }
5374
LPUART12_NonBlockingReceive(void * data,uint32_t num)5375 static int32_t LPUART12_NonBlockingReceive(void *data, uint32_t num)
5376 {
5377 return LPUART_NonBlockingReceive(data, num, &LPUART12_NonBlockingDriverState);
5378 }
5379
LPUART12_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)5380 static int32_t LPUART12_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
5381 {
5382 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART12_NonBlockingDriverState);
5383 }
5384
LPUART12_NonBlockingGetTxCount(void)5385 static uint32_t LPUART12_NonBlockingGetTxCount(void)
5386 {
5387 return LPUART_NonBlockingGetTxCount(&LPUART12_NonBlockingDriverState);
5388 }
5389
LPUART12_NonBlockingGetRxCount(void)5390 static uint32_t LPUART12_NonBlockingGetRxCount(void)
5391 {
5392 return LPUART_NonBlockingGetRxCount(&LPUART12_NonBlockingDriverState);
5393 }
5394
LPUART12_NonBlockingControl(uint32_t control,uint32_t arg)5395 static int32_t LPUART12_NonBlockingControl(uint32_t control, uint32_t arg)
5396 {
5397 int32_t result;
5398
5399 result = LPUART_NonBlockingControl(control, arg, &LPUART12_NonBlockingDriverState);
5400 if (ARM_DRIVER_OK != result)
5401 {
5402 return result;
5403 }
5404
5405 /* Enable the receive interrupts if ring buffer is used */
5406 if (LPUART12_NonBlockingDriverState.handle->rxRingBuffer != NULL)
5407 {
5408 LPUART_EnableInterrupts(
5409 LPUART12_NonBlockingDriverState.resource->base,
5410 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
5411 }
5412
5413 return ARM_DRIVER_OK;
5414 }
5415
LPUART12_NonBlockingGetStatus(void)5416 static ARM_USART_STATUS LPUART12_NonBlockingGetStatus(void)
5417 {
5418 return LPUART_NonBlockingGetStatus(&LPUART12_NonBlockingDriverState);
5419 }
5420
5421 #endif
5422
5423 ARM_DRIVER_USART Driver_USART12 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
5424 #if defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN
5425 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5426 LPUART12_EdmaInitialize, LPUART12_EdmaUninitialize, LPUART12_EdmaPowerControl,
5427 LPUART12_EdmaSend, LPUART12_EdmaReceive, LPUART12_EdmaTransfer,
5428 LPUART12_EdmaGetTxCount, LPUART12_EdmaGetRxCount, LPUART12_EdmaControl,
5429 LPUART12_EdmaGetStatus,
5430 #else
5431 LPUART12_DmaInitialize, LPUART12_DmaUninitialize, LPUART12_DmaPowerControl,
5432 LPUART12_DmaSend, LPUART12_DmaReceive, LPUART12_DmaTransfer,
5433 LPUART12_DmaGetTxCount, LPUART12_DmaGetRxCount, LPUART12_DmaControl,
5434 LPUART12_DmaGetStatus,
5435 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
5436 #else
5437 LPUART12_NonBlockingInitialize,
5438 LPUART12_NonBlockingUninitialize,
5439 LPUART12_NonBlockingPowerControl,
5440 LPUART12_NonBlockingSend,
5441 LPUART12_NonBlockingReceive,
5442 LPUART12_NonBlockingTransfer,
5443 LPUART12_NonBlockingGetTxCount,
5444 LPUART12_NonBlockingGetRxCount,
5445 LPUART12_NonBlockingControl,
5446 LPUART12_NonBlockingGetStatus,
5447 #endif /* RTE_USART12_DMA_EN */
5448 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
5449
5450 #endif /* LPUART12 */
5451
5452 #if defined(LPUART13) && defined(RTE_USART13) && RTE_USART13
5453
5454 /* User needs to provide the implementation for LPUART13_GetFreq/InitPins/DeinitPins
5455 in the application for enabling according instance. */
5456 extern uint32_t LPUART13_GetFreq(void);
5457
5458 static cmsis_lpuart_resource_t LPUART13_Resource = {LPUART13, LPUART13_GetFreq};
5459
5460 #if defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN
5461
5462 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
5463
5464 static cmsis_lpuart_dma_resource_t LPUART13_DmaResource = {
5465 RTE_USART13_DMA_TX_DMA_BASE, RTE_USART13_DMA_TX_CH, RTE_USART13_DMA_TX_PERI_SEL,
5466 RTE_USART13_DMA_RX_DMA_BASE, RTE_USART13_DMA_RX_CH, RTE_USART13_DMA_RX_PERI_SEL,
5467
5468 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5469 RTE_USART13_DMA_TX_DMAMUX_BASE, RTE_USART13_DMA_RX_DMAMUX_BASE,
5470 #endif
5471 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
5472 RTE_USART13_DMAMUX_TX_CH, RTE_USART13_DMAMUX_RX_CH
5473 #endif
5474 };
5475
5476 static lpuart_dma_handle_t LPUART13_DmaHandle;
5477 static dma_handle_t LPUART13_DmaRxHandle;
5478 static dma_handle_t LPUART13_DmaTxHandle;
5479
5480 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5481 ARMCC_SECTION("lpuart13_dma_driver_state")
5482 static cmsis_lpuart_dma_driver_state_t LPUART13_DmaDriverState = {
5483 #else
5484 static cmsis_lpuart_dma_driver_state_t LPUART13_DmaDriverState = {
5485 #endif
5486 &LPUART13_Resource, &LPUART13_DmaResource, &LPUART13_DmaHandle, &LPUART13_DmaRxHandle, &LPUART13_DmaTxHandle,
5487 };
5488
LPUART13_DmaInitialize(ARM_USART_SignalEvent_t cb_event)5489 static int32_t LPUART13_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
5490 {
5491 #ifdef RTE_USART13_PIN_INIT
5492 RTE_USART13_PIN_INIT();
5493 #endif
5494 return LPUART_DmaInitialize(cb_event, &LPUART13_DmaDriverState);
5495 }
5496
LPUART13_DmaUninitialize(void)5497 static int32_t LPUART13_DmaUninitialize(void)
5498 {
5499 #ifdef RTE_USART13_PIN_DEINIT
5500 RTE_USART13_PIN_DEINIT();
5501 #endif
5502 return LPUART_DmaUninitialize(&LPUART13_DmaDriverState);
5503 }
5504
LPUART13_DmaPowerControl(ARM_POWER_STATE state)5505 static int32_t LPUART13_DmaPowerControl(ARM_POWER_STATE state)
5506 {
5507 return LPUART_DmaPowerControl(state, &LPUART13_DmaDriverState);
5508 }
5509
LPUART13_DmaSend(const void * data,uint32_t num)5510 static int32_t LPUART13_DmaSend(const void *data, uint32_t num)
5511 {
5512 return LPUART_DmaSend(data, num, &LPUART13_DmaDriverState);
5513 }
5514
LPUART13_DmaReceive(void * data,uint32_t num)5515 static int32_t LPUART13_DmaReceive(void *data, uint32_t num)
5516 {
5517 return LPUART_DmaReceive(data, num, &LPUART13_DmaDriverState);
5518 }
5519
LPUART13_DmaTransfer(const void * data_out,void * data_in,uint32_t num)5520 static int32_t LPUART13_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
5521 {
5522 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART13_DmaDriverState);
5523 }
5524
LPUART13_DmaGetTxCount(void)5525 static uint32_t LPUART13_DmaGetTxCount(void)
5526 {
5527 return LPUART_DmaGetTxCount(&LPUART13_DmaDriverState);
5528 }
5529
LPUART13_DmaGetRxCount(void)5530 static uint32_t LPUART13_DmaGetRxCount(void)
5531 {
5532 return LPUART_DmaGetRxCount(&LPUART13_DmaDriverState);
5533 }
5534
LPUART13_DmaControl(uint32_t control,uint32_t arg)5535 static int32_t LPUART13_DmaControl(uint32_t control, uint32_t arg)
5536 {
5537 return LPUART_DmaControl(control, arg, &LPUART13_DmaDriverState);
5538 }
5539
LPUART13_DmaGetStatus(void)5540 static ARM_USART_STATUS LPUART13_DmaGetStatus(void)
5541 {
5542 return LPUART_DmaGetStatus(&LPUART13_DmaDriverState);
5543 }
5544
5545 /* LPUART13 Driver Control Block */
5546
5547 #endif
5548
5549 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5550
5551 static cmsis_lpuart_edma_resource_t LPUART13_EdmaResource = {
5552 RTE_USART13_DMA_TX_DMA_BASE, RTE_USART13_DMA_TX_CH, RTE_USART13_DMA_TX_PERI_SEL,
5553 RTE_USART13_DMA_RX_DMA_BASE, RTE_USART13_DMA_RX_CH, RTE_USART13_DMA_RX_PERI_SEL,
5554
5555 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5556 RTE_USART13_DMA_TX_DMAMUX_BASE, RTE_USART13_DMA_RX_DMAMUX_BASE,
5557 #endif
5558 };
5559
5560 static lpuart_edma_handle_t LPUART13_EdmaHandle;
5561 static edma_handle_t LPUART13_EdmaRxHandle;
5562 static edma_handle_t LPUART13_EdmaTxHandle;
5563
5564 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5565 ARMCC_SECTION("lpuart13_edma_driver_state")
5566 static cmsis_lpuart_edma_driver_state_t LPUART13_EdmaDriverState = {
5567 #else
5568 static cmsis_lpuart_edma_driver_state_t LPUART13_EdmaDriverState = {
5569 #endif
5570 &LPUART13_Resource, &LPUART13_EdmaResource, &LPUART13_EdmaHandle, &LPUART13_EdmaRxHandle, &LPUART13_EdmaTxHandle,
5571 };
5572
LPUART13_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)5573 static int32_t LPUART13_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
5574 {
5575 #ifdef RTE_USART13_PIN_INIT
5576 RTE_USART13_PIN_INIT();
5577 #endif
5578 return LPUART_EdmaInitialize(cb_event, &LPUART13_EdmaDriverState);
5579 }
5580
LPUART13_EdmaUninitialize(void)5581 static int32_t LPUART13_EdmaUninitialize(void)
5582 {
5583 #ifdef RTE_USART13_PIN_DEINIT
5584 RTE_USART13_PIN_DEINIT();
5585 #endif
5586 return LPUART_EdmaUninitialize(&LPUART13_EdmaDriverState);
5587 }
5588
LPUART13_EdmaPowerControl(ARM_POWER_STATE state)5589 static int32_t LPUART13_EdmaPowerControl(ARM_POWER_STATE state)
5590 {
5591 return LPUART_EdmaPowerControl(state, &LPUART13_EdmaDriverState);
5592 }
5593
LPUART13_EdmaSend(const void * data,uint32_t num)5594 static int32_t LPUART13_EdmaSend(const void *data, uint32_t num)
5595 {
5596 return LPUART_EdmaSend(data, num, &LPUART13_EdmaDriverState);
5597 }
5598
LPUART13_EdmaReceive(void * data,uint32_t num)5599 static int32_t LPUART13_EdmaReceive(void *data, uint32_t num)
5600 {
5601 return LPUART_EdmaReceive(data, num, &LPUART13_EdmaDriverState);
5602 }
5603
LPUART13_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)5604 static int32_t LPUART13_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
5605 {
5606 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART13_EdmaDriverState);
5607 }
5608
LPUART13_EdmaGetTxCount(void)5609 static uint32_t LPUART13_EdmaGetTxCount(void)
5610 {
5611 return LPUART_EdmaGetTxCount(&LPUART13_EdmaDriverState);
5612 }
5613
LPUART13_EdmaGetRxCount(void)5614 static uint32_t LPUART13_EdmaGetRxCount(void)
5615 {
5616 return LPUART_EdmaGetRxCount(&LPUART13_EdmaDriverState);
5617 }
5618
LPUART13_EdmaControl(uint32_t control,uint32_t arg)5619 static int32_t LPUART13_EdmaControl(uint32_t control, uint32_t arg)
5620 {
5621 return LPUART_EdmaControl(control, arg, &LPUART13_EdmaDriverState);
5622 }
5623
LPUART13_EdmaGetStatus(void)5624 static ARM_USART_STATUS LPUART13_EdmaGetStatus(void)
5625 {
5626 return LPUART_EdmaGetStatus(&LPUART13_EdmaDriverState);
5627 }
5628
5629 #endif
5630
5631 #else
5632
5633 static lpuart_handle_t LPUART13_Handle;
5634
5635 #if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1)
5636 static uint8_t lpuart13_rxRingBuffer[USART_RX_BUFFER_LEN];
5637 #endif
5638
5639 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5640 ARMCC_SECTION("lpuart13_non_blocking_driver_state")
5641 static cmsis_lpuart_non_blocking_driver_state_t LPUART13_NonBlockingDriverState = {
5642 #else
5643 static cmsis_lpuart_non_blocking_driver_state_t LPUART13_NonBlockingDriverState = {
5644 #endif
5645 &LPUART13_Resource,
5646 &LPUART13_Handle,
5647 };
5648
LPUART13_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)5649 static int32_t LPUART13_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
5650 {
5651 #ifdef RTE_USART13_PIN_INIT
5652 RTE_USART13_PIN_INIT();
5653 #endif
5654 return LPUART_NonBlockingInitialize(cb_event, &LPUART13_NonBlockingDriverState);
5655 }
5656
LPUART13_NonBlockingUninitialize(void)5657 static int32_t LPUART13_NonBlockingUninitialize(void)
5658 {
5659 #ifdef RTE_USART13_PIN_DEINIT
5660 RTE_USART13_PIN_DEINIT();
5661 #endif
5662 return LPUART_NonBlockingUninitialize(&LPUART13_NonBlockingDriverState);
5663 }
5664
LPUART13_NonBlockingPowerControl(ARM_POWER_STATE state)5665 static int32_t LPUART13_NonBlockingPowerControl(ARM_POWER_STATE state)
5666 {
5667 int32_t result;
5668
5669 result = LPUART_NonBlockingPowerControl(state, &LPUART13_NonBlockingDriverState);
5670
5671 #if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1)
5672 if ((state == ARM_POWER_FULL) && (LPUART13_NonBlockingDriverState.handle->rxRingBuffer == NULL))
5673 {
5674 LPUART_TransferStartRingBuffer(LPUART13_NonBlockingDriverState.resource->base,
5675 LPUART13_NonBlockingDriverState.handle, lpuart13_rxRingBuffer,
5676 USART_RX_BUFFER_LEN);
5677 }
5678 #endif
5679
5680 return result;
5681 }
5682
LPUART13_NonBlockingSend(const void * data,uint32_t num)5683 static int32_t LPUART13_NonBlockingSend(const void *data, uint32_t num)
5684 {
5685 return LPUART_NonBlockingSend(data, num, &LPUART13_NonBlockingDriverState);
5686 }
5687
LPUART13_NonBlockingReceive(void * data,uint32_t num)5688 static int32_t LPUART13_NonBlockingReceive(void *data, uint32_t num)
5689 {
5690 return LPUART_NonBlockingReceive(data, num, &LPUART13_NonBlockingDriverState);
5691 }
5692
LPUART13_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)5693 static int32_t LPUART13_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
5694 {
5695 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART13_NonBlockingDriverState);
5696 }
5697
LPUART13_NonBlockingGetTxCount(void)5698 static uint32_t LPUART13_NonBlockingGetTxCount(void)
5699 {
5700 return LPUART_NonBlockingGetTxCount(&LPUART13_NonBlockingDriverState);
5701 }
5702
LPUART13_NonBlockingGetRxCount(void)5703 static uint32_t LPUART13_NonBlockingGetRxCount(void)
5704 {
5705 return LPUART_NonBlockingGetRxCount(&LPUART13_NonBlockingDriverState);
5706 }
5707
LPUART13_NonBlockingControl(uint32_t control,uint32_t arg)5708 static int32_t LPUART13_NonBlockingControl(uint32_t control, uint32_t arg)
5709 {
5710 int32_t result;
5711
5712 result = LPUART_NonBlockingControl(control, arg, &LPUART13_NonBlockingDriverState);
5713 if (ARM_DRIVER_OK != result)
5714 {
5715 return result;
5716 }
5717
5718 /* Enable the receive interrupts if ring buffer is used */
5719 if (LPUART13_NonBlockingDriverState.handle->rxRingBuffer != NULL)
5720 {
5721 LPUART_EnableInterrupts(
5722 LPUART13_NonBlockingDriverState.resource->base,
5723 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
5724 }
5725
5726 return ARM_DRIVER_OK;
5727 }
5728
LPUART13_NonBlockingGetStatus(void)5729 static ARM_USART_STATUS LPUART13_NonBlockingGetStatus(void)
5730 {
5731 return LPUART_NonBlockingGetStatus(&LPUART13_NonBlockingDriverState);
5732 }
5733
5734 #endif
5735
5736 ARM_DRIVER_USART Driver_USART13 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
5737 #if defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN
5738 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5739 LPUART13_EdmaInitialize, LPUART13_EdmaUninitialize, LPUART13_EdmaPowerControl,
5740 LPUART13_EdmaSend, LPUART13_EdmaReceive, LPUART13_EdmaTransfer,
5741 LPUART13_EdmaGetTxCount, LPUART13_EdmaGetRxCount, LPUART13_EdmaControl,
5742 LPUART13_EdmaGetStatus,
5743 #else
5744 LPUART13_DmaInitialize, LPUART13_DmaUninitialize, LPUART13_DmaPowerControl,
5745 LPUART13_DmaSend, LPUART13_DmaReceive, LPUART13_DmaTransfer,
5746 LPUART13_DmaGetTxCount, LPUART13_DmaGetRxCount, LPUART13_DmaControl,
5747 LPUART13_DmaGetStatus,
5748 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
5749 #else
5750 LPUART13_NonBlockingInitialize,
5751 LPUART13_NonBlockingUninitialize,
5752 LPUART13_NonBlockingPowerControl,
5753 LPUART13_NonBlockingSend,
5754 LPUART13_NonBlockingReceive,
5755 LPUART13_NonBlockingTransfer,
5756 LPUART13_NonBlockingGetTxCount,
5757 LPUART13_NonBlockingGetRxCount,
5758 LPUART13_NonBlockingControl,
5759 LPUART13_NonBlockingGetStatus,
5760 #endif /* RTE_USART13_DMA_EN */
5761 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
5762
5763 #endif /* LPUART13 */
5764
5765 #if defined(LPUART14) && defined(RTE_USART14) && RTE_USART14
5766
5767 /* User needs to provide the implementation for LPUART14_GetFreq/InitPins/DeinitPins
5768 in the application for enabling according instance. */
5769 extern uint32_t LPUART14_GetFreq(void);
5770
5771 static cmsis_lpuart_resource_t LPUART14_Resource = {LPUART14, LPUART14_GetFreq};
5772
5773 #if defined(RTE_USART14_DMA_EN) && RTE_USART14_DMA_EN
5774
5775 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
5776
5777 static cmsis_lpuart_dma_resource_t LPUART14_DmaResource = {
5778 RTE_USART14_DMA_TX_DMA_BASE, RTE_USART14_DMA_TX_CH, RTE_USART14_DMA_TX_PERI_SEL,
5779 RTE_USART14_DMA_RX_DMA_BASE, RTE_USART14_DMA_RX_CH, RTE_USART14_DMA_RX_PERI_SEL,
5780
5781 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5782 RTE_USART14_DMA_TX_DMAMUX_BASE, RTE_USART14_DMA_RX_DMAMUX_BASE,
5783 #endif
5784 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
5785 RTE_USART14_DMAMUX_TX_CH, RTE_USART14_DMAMUX_RX_CH
5786 #endif
5787 };
5788
5789 static lpuart_dma_handle_t LPUART14_DmaHandle;
5790 static dma_handle_t LPUART14_DmaRxHandle;
5791 static dma_handle_t LPUART14_DmaTxHandle;
5792
5793 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5794 ARMCC_SECTION("lpuart14_dma_driver_state")
5795 static cmsis_lpuart_dma_driver_state_t LPUART14_DmaDriverState = {
5796 #else
5797 static cmsis_lpuart_dma_driver_state_t LPUART14_DmaDriverState = {
5798 #endif
5799 &LPUART14_Resource, &LPUART14_DmaResource, &LPUART14_DmaHandle, &LPUART14_DmaRxHandle, &LPUART14_DmaTxHandle,
5800 };
5801
LPUART14_DmaInitialize(ARM_USART_SignalEvent_t cb_event)5802 static int32_t LPUART14_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
5803 {
5804 #ifdef RTE_USART14_PIN_INIT
5805 RTE_USART14_PIN_INIT();
5806 #endif
5807 return LPUART_DmaInitialize(cb_event, &LPUART14_DmaDriverState);
5808 }
5809
LPUART14_DmaUninitialize(void)5810 static int32_t LPUART14_DmaUninitialize(void)
5811 {
5812 #ifdef RTE_USART14_PIN_DEINIT
5813 RTE_USART14_PIN_DEINIT();
5814 #endif
5815 return LPUART_DmaUninitialize(&LPUART14_DmaDriverState);
5816 }
5817
LPUART14_DmaPowerControl(ARM_POWER_STATE state)5818 static int32_t LPUART14_DmaPowerControl(ARM_POWER_STATE state)
5819 {
5820 return LPUART_DmaPowerControl(state, &LPUART14_DmaDriverState);
5821 }
5822
LPUART14_DmaSend(const void * data,uint32_t num)5823 static int32_t LPUART14_DmaSend(const void *data, uint32_t num)
5824 {
5825 return LPUART_DmaSend(data, num, &LPUART14_DmaDriverState);
5826 }
5827
LPUART14_DmaReceive(void * data,uint32_t num)5828 static int32_t LPUART14_DmaReceive(void *data, uint32_t num)
5829 {
5830 return LPUART_DmaReceive(data, num, &LPUART14_DmaDriverState);
5831 }
5832
LPUART14_DmaTransfer(const void * data_out,void * data_in,uint32_t num)5833 static int32_t LPUART14_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
5834 {
5835 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART14_DmaDriverState);
5836 }
5837
LPUART14_DmaGetTxCount(void)5838 static uint32_t LPUART14_DmaGetTxCount(void)
5839 {
5840 return LPUART_DmaGetTxCount(&LPUART14_DmaDriverState);
5841 }
5842
LPUART14_DmaGetRxCount(void)5843 static uint32_t LPUART14_DmaGetRxCount(void)
5844 {
5845 return LPUART_DmaGetRxCount(&LPUART14_DmaDriverState);
5846 }
5847
LPUART14_DmaControl(uint32_t control,uint32_t arg)5848 static int32_t LPUART14_DmaControl(uint32_t control, uint32_t arg)
5849 {
5850 return LPUART_DmaControl(control, arg, &LPUART14_DmaDriverState);
5851 }
5852
LPUART14_DmaGetStatus(void)5853 static ARM_USART_STATUS LPUART14_DmaGetStatus(void)
5854 {
5855 return LPUART_DmaGetStatus(&LPUART14_DmaDriverState);
5856 }
5857
5858 /* LPUART14 Driver Control Block */
5859
5860 #endif
5861
5862 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
5863
5864 static cmsis_lpuart_edma_resource_t LPUART14_EdmaResource = {
5865 RTE_USART14_DMA_TX_DMA_BASE, RTE_USART14_DMA_TX_CH, RTE_USART14_DMA_TX_PERI_SEL,
5866 RTE_USART14_DMA_RX_DMA_BASE, RTE_USART14_DMA_RX_CH, RTE_USART14_DMA_RX_PERI_SEL,
5867
5868 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
5869 RTE_USART14_DMA_TX_DMAMUX_BASE, RTE_USART14_DMA_RX_DMAMUX_BASE,
5870 #endif
5871 };
5872
5873 static lpuart_edma_handle_t LPUART14_EdmaHandle;
5874 static edma_handle_t LPUART14_EdmaRxHandle;
5875 static edma_handle_t LPUART14_EdmaTxHandle;
5876
5877 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5878 ARMCC_SECTION("lpuart14_edma_driver_state")
5879 static cmsis_lpuart_edma_driver_state_t LPUART14_EdmaDriverState = {
5880 #else
5881 static cmsis_lpuart_edma_driver_state_t LPUART14_EdmaDriverState = {
5882 #endif
5883 &LPUART14_Resource, &LPUART14_EdmaResource, &LPUART14_EdmaHandle, &LPUART14_EdmaRxHandle, &LPUART14_EdmaTxHandle,
5884 };
5885
LPUART14_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)5886 static int32_t LPUART14_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
5887 {
5888 #ifdef RTE_USART14_PIN_INIT
5889 RTE_USART14_PIN_INIT();
5890 #endif
5891 return LPUART_EdmaInitialize(cb_event, &LPUART14_EdmaDriverState);
5892 }
5893
LPUART14_EdmaUninitialize(void)5894 static int32_t LPUART14_EdmaUninitialize(void)
5895 {
5896 #ifdef RTE_USART14_PIN_DEINIT
5897 RTE_USART14_PIN_DEINIT();
5898 #endif
5899 return LPUART_EdmaUninitialize(&LPUART14_EdmaDriverState);
5900 }
5901
LPUART14_EdmaPowerControl(ARM_POWER_STATE state)5902 static int32_t LPUART14_EdmaPowerControl(ARM_POWER_STATE state)
5903 {
5904 return LPUART_EdmaPowerControl(state, &LPUART14_EdmaDriverState);
5905 }
5906
LPUART14_EdmaSend(const void * data,uint32_t num)5907 static int32_t LPUART14_EdmaSend(const void *data, uint32_t num)
5908 {
5909 return LPUART_EdmaSend(data, num, &LPUART14_EdmaDriverState);
5910 }
5911
LPUART14_EdmaReceive(void * data,uint32_t num)5912 static int32_t LPUART14_EdmaReceive(void *data, uint32_t num)
5913 {
5914 return LPUART_EdmaReceive(data, num, &LPUART14_EdmaDriverState);
5915 }
5916
LPUART14_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)5917 static int32_t LPUART14_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
5918 {
5919 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART14_EdmaDriverState);
5920 }
5921
LPUART14_EdmaGetTxCount(void)5922 static uint32_t LPUART14_EdmaGetTxCount(void)
5923 {
5924 return LPUART_EdmaGetTxCount(&LPUART14_EdmaDriverState);
5925 }
5926
LPUART14_EdmaGetRxCount(void)5927 static uint32_t LPUART14_EdmaGetRxCount(void)
5928 {
5929 return LPUART_EdmaGetRxCount(&LPUART14_EdmaDriverState);
5930 }
5931
LPUART14_EdmaControl(uint32_t control,uint32_t arg)5932 static int32_t LPUART14_EdmaControl(uint32_t control, uint32_t arg)
5933 {
5934 return LPUART_EdmaControl(control, arg, &LPUART14_EdmaDriverState);
5935 }
5936
LPUART14_EdmaGetStatus(void)5937 static ARM_USART_STATUS LPUART14_EdmaGetStatus(void)
5938 {
5939 return LPUART_EdmaGetStatus(&LPUART14_EdmaDriverState);
5940 }
5941
5942 #endif
5943
5944 #else
5945
5946 static lpuart_handle_t LPUART14_Handle;
5947
5948 #if defined(USART14_RX_BUFFER_ENABLE) && (USART14_RX_BUFFER_ENABLE == 1)
5949 static uint8_t lpuart14_rxRingBuffer[USART_RX_BUFFER_LEN];
5950 #endif
5951
5952 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
5953 ARMCC_SECTION("lpuart14_non_blocking_driver_state")
5954 static cmsis_lpuart_non_blocking_driver_state_t LPUART14_NonBlockingDriverState = {
5955 #else
5956 static cmsis_lpuart_non_blocking_driver_state_t LPUART14_NonBlockingDriverState = {
5957 #endif
5958 &LPUART14_Resource,
5959 &LPUART14_Handle,
5960 };
5961
LPUART14_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)5962 static int32_t LPUART14_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
5963 {
5964 #ifdef RTE_USART14_PIN_INIT
5965 RTE_USART14_PIN_INIT();
5966 #endif
5967 return LPUART_NonBlockingInitialize(cb_event, &LPUART14_NonBlockingDriverState);
5968 }
5969
LPUART14_NonBlockingUninitialize(void)5970 static int32_t LPUART14_NonBlockingUninitialize(void)
5971 {
5972 #ifdef RTE_USART14_PIN_DEINIT
5973 RTE_USART14_PIN_DEINIT();
5974 #endif
5975 return LPUART_NonBlockingUninitialize(&LPUART14_NonBlockingDriverState);
5976 }
5977
LPUART14_NonBlockingPowerControl(ARM_POWER_STATE state)5978 static int32_t LPUART14_NonBlockingPowerControl(ARM_POWER_STATE state)
5979 {
5980 int32_t result;
5981
5982 result = LPUART_NonBlockingPowerControl(state, &LPUART14_NonBlockingDriverState);
5983
5984 #if defined(USART14_RX_BUFFER_ENABLE) && (USART14_RX_BUFFER_ENABLE == 1)
5985 if ((state == ARM_POWER_FULL) && (LPUART14_NonBlockingDriverState.handle->rxRingBuffer == NULL))
5986 {
5987 LPUART_TransferStartRingBuffer(LPUART14_NonBlockingDriverState.resource->base,
5988 LPUART14_NonBlockingDriverState.handle, lpuart14_rxRingBuffer,
5989 USART_RX_BUFFER_LEN);
5990 }
5991 #endif
5992
5993 return result;
5994 }
5995
LPUART14_NonBlockingSend(const void * data,uint32_t num)5996 static int32_t LPUART14_NonBlockingSend(const void *data, uint32_t num)
5997 {
5998 return LPUART_NonBlockingSend(data, num, &LPUART14_NonBlockingDriverState);
5999 }
6000
LPUART14_NonBlockingReceive(void * data,uint32_t num)6001 static int32_t LPUART14_NonBlockingReceive(void *data, uint32_t num)
6002 {
6003 return LPUART_NonBlockingReceive(data, num, &LPUART14_NonBlockingDriverState);
6004 }
6005
LPUART14_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)6006 static int32_t LPUART14_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
6007 {
6008 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART14_NonBlockingDriverState);
6009 }
6010
LPUART14_NonBlockingGetTxCount(void)6011 static uint32_t LPUART14_NonBlockingGetTxCount(void)
6012 {
6013 return LPUART_NonBlockingGetTxCount(&LPUART14_NonBlockingDriverState);
6014 }
6015
LPUART14_NonBlockingGetRxCount(void)6016 static uint32_t LPUART14_NonBlockingGetRxCount(void)
6017 {
6018 return LPUART_NonBlockingGetRxCount(&LPUART14_NonBlockingDriverState);
6019 }
6020
LPUART14_NonBlockingControl(uint32_t control,uint32_t arg)6021 static int32_t LPUART14_NonBlockingControl(uint32_t control, uint32_t arg)
6022 {
6023 int32_t result;
6024
6025 result = LPUART_NonBlockingControl(control, arg, &LPUART14_NonBlockingDriverState);
6026 if (ARM_DRIVER_OK != result)
6027 {
6028 return result;
6029 }
6030
6031 /* Enable the receive interrupts if ring buffer is used */
6032 if (LPUART14_NonBlockingDriverState.handle->rxRingBuffer != NULL)
6033 {
6034 LPUART_EnableInterrupts(
6035 LPUART14_NonBlockingDriverState.resource->base,
6036 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
6037 }
6038
6039 return ARM_DRIVER_OK;
6040 }
6041
LPUART14_NonBlockingGetStatus(void)6042 static ARM_USART_STATUS LPUART14_NonBlockingGetStatus(void)
6043 {
6044 return LPUART_NonBlockingGetStatus(&LPUART14_NonBlockingDriverState);
6045 }
6046
6047 #endif
6048
6049 ARM_DRIVER_USART Driver_USART14 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
6050 #if defined(RTE_USART14_DMA_EN) && RTE_USART14_DMA_EN
6051 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6052 LPUART14_EdmaInitialize, LPUART14_EdmaUninitialize, LPUART14_EdmaPowerControl,
6053 LPUART14_EdmaSend, LPUART14_EdmaReceive, LPUART14_EdmaTransfer,
6054 LPUART14_EdmaGetTxCount, LPUART14_EdmaGetRxCount, LPUART14_EdmaControl,
6055 LPUART14_EdmaGetStatus,
6056 #else
6057 LPUART14_DmaInitialize, LPUART14_DmaUninitialize, LPUART14_DmaPowerControl,
6058 LPUART14_DmaSend, LPUART14_DmaReceive, LPUART14_DmaTransfer,
6059 LPUART14_DmaGetTxCount, LPUART14_DmaGetRxCount, LPUART14_DmaControl,
6060 LPUART14_DmaGetStatus,
6061 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
6062 #else
6063 LPUART14_NonBlockingInitialize,
6064 LPUART14_NonBlockingUninitialize,
6065 LPUART14_NonBlockingPowerControl,
6066 LPUART14_NonBlockingSend,
6067 LPUART14_NonBlockingReceive,
6068 LPUART14_NonBlockingTransfer,
6069 LPUART14_NonBlockingGetTxCount,
6070 LPUART14_NonBlockingGetRxCount,
6071 LPUART14_NonBlockingControl,
6072 LPUART14_NonBlockingGetStatus,
6073 #endif /* RTE_USART14_DMA_EN */
6074 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
6075
6076 #endif /* LPUART14 */
6077
6078 #if defined(LPUART15) && defined(RTE_USART15) && RTE_USART15
6079
6080 /* User needs to provide the implementation for LPUART15_GetFreq/InitPins/DeinitPins
6081 in the application for enabling according instance. */
6082 extern uint32_t LPUART15_GetFreq(void);
6083
6084 static cmsis_lpuart_resource_t LPUART15_Resource = {LPUART15, LPUART15_GetFreq};
6085
6086 #if defined(RTE_USART15_DMA_EN) && RTE_USART15_DMA_EN
6087
6088 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
6089
6090 static cmsis_lpuart_dma_resource_t LPUART15_DmaResource = {
6091 RTE_USART15_DMA_TX_DMA_BASE, RTE_USART15_DMA_TX_CH, RTE_USART15_DMA_TX_PERI_SEL,
6092 RTE_USART15_DMA_RX_DMA_BASE, RTE_USART15_DMA_RX_CH, RTE_USART15_DMA_RX_PERI_SEL,
6093
6094 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6095 RTE_USART15_DMA_TX_DMAMUX_BASE, RTE_USART15_DMA_RX_DMAMUX_BASE,
6096 #endif
6097 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
6098 RTE_USART15_DMAMUX_TX_CH, RTE_USART15_DMAMUX_RX_CH
6099 #endif
6100 };
6101
6102 static lpuart_dma_handle_t LPUART15_DmaHandle;
6103 static dma_handle_t LPUART15_DmaRxHandle;
6104 static dma_handle_t LPUART15_DmaTxHandle;
6105
6106 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6107 ARMCC_SECTION("lpuart15_dma_driver_state")
6108 static cmsis_lpuart_dma_driver_state_t LPUART15_DmaDriverState = {
6109 #else
6110 static cmsis_lpuart_dma_driver_state_t LPUART15_DmaDriverState = {
6111 #endif
6112 &LPUART15_Resource, &LPUART15_DmaResource, &LPUART15_DmaHandle, &LPUART15_DmaRxHandle, &LPUART15_DmaTxHandle,
6113 };
6114
LPUART15_DmaInitialize(ARM_USART_SignalEvent_t cb_event)6115 static int32_t LPUART15_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
6116 {
6117 #ifdef RTE_USART15_PIN_INIT
6118 RTE_USART15_PIN_INIT();
6119 #endif
6120 return LPUART_DmaInitialize(cb_event, &LPUART15_DmaDriverState);
6121 }
6122
LPUART15_DmaUninitialize(void)6123 static int32_t LPUART15_DmaUninitialize(void)
6124 {
6125 #ifdef RTE_USART15_PIN_DEINIT
6126 RTE_USART15_PIN_DEINIT();
6127 #endif
6128 return LPUART_DmaUninitialize(&LPUART15_DmaDriverState);
6129 }
6130
LPUART15_DmaPowerControl(ARM_POWER_STATE state)6131 static int32_t LPUART15_DmaPowerControl(ARM_POWER_STATE state)
6132 {
6133 return LPUART_DmaPowerControl(state, &LPUART15_DmaDriverState);
6134 }
6135
LPUART15_DmaSend(const void * data,uint32_t num)6136 static int32_t LPUART15_DmaSend(const void *data, uint32_t num)
6137 {
6138 return LPUART_DmaSend(data, num, &LPUART15_DmaDriverState);
6139 }
6140
LPUART15_DmaReceive(void * data,uint32_t num)6141 static int32_t LPUART15_DmaReceive(void *data, uint32_t num)
6142 {
6143 return LPUART_DmaReceive(data, num, &LPUART15_DmaDriverState);
6144 }
6145
LPUART15_DmaTransfer(const void * data_out,void * data_in,uint32_t num)6146 static int32_t LPUART15_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
6147 {
6148 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART15_DmaDriverState);
6149 }
6150
LPUART15_DmaGetTxCount(void)6151 static uint32_t LPUART15_DmaGetTxCount(void)
6152 {
6153 return LPUART_DmaGetTxCount(&LPUART15_DmaDriverState);
6154 }
6155
LPUART15_DmaGetRxCount(void)6156 static uint32_t LPUART15_DmaGetRxCount(void)
6157 {
6158 return LPUART_DmaGetRxCount(&LPUART15_DmaDriverState);
6159 }
6160
LPUART15_DmaControl(uint32_t control,uint32_t arg)6161 static int32_t LPUART15_DmaControl(uint32_t control, uint32_t arg)
6162 {
6163 return LPUART_DmaControl(control, arg, &LPUART15_DmaDriverState);
6164 }
6165
LPUART15_DmaGetStatus(void)6166 static ARM_USART_STATUS LPUART15_DmaGetStatus(void)
6167 {
6168 return LPUART_DmaGetStatus(&LPUART15_DmaDriverState);
6169 }
6170
6171 /* LPUART15 Driver Control Block */
6172
6173 #endif
6174
6175 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6176
6177 static cmsis_lpuart_edma_resource_t LPUART15_EdmaResource = {
6178 RTE_USART15_DMA_TX_DMA_BASE, RTE_USART15_DMA_TX_CH, RTE_USART15_DMA_TX_PERI_SEL,
6179 RTE_USART15_DMA_RX_DMA_BASE, RTE_USART15_DMA_RX_CH, RTE_USART15_DMA_RX_PERI_SEL,
6180
6181 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6182 RTE_USART15_DMA_TX_DMAMUX_BASE, RTE_USART15_DMA_RX_DMAMUX_BASE,
6183 #endif
6184 };
6185
6186 static lpuart_edma_handle_t LPUART15_EdmaHandle;
6187 static edma_handle_t LPUART15_EdmaRxHandle;
6188 static edma_handle_t LPUART15_EdmaTxHandle;
6189
6190 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6191 ARMCC_SECTION("lpuart15_edma_driver_state")
6192 static cmsis_lpuart_edma_driver_state_t LPUART15_EdmaDriverState = {
6193 #else
6194 static cmsis_lpuart_edma_driver_state_t LPUART15_EdmaDriverState = {
6195 #endif
6196 &LPUART15_Resource, &LPUART15_EdmaResource, &LPUART15_EdmaHandle, &LPUART15_EdmaRxHandle, &LPUART15_EdmaTxHandle,
6197 };
6198
LPUART15_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)6199 static int32_t LPUART15_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
6200 {
6201 #ifdef RTE_USART15_PIN_INIT
6202 RTE_USART15_PIN_INIT();
6203 #endif
6204 return LPUART_EdmaInitialize(cb_event, &LPUART15_EdmaDriverState);
6205 }
6206
LPUART15_EdmaUninitialize(void)6207 static int32_t LPUART15_EdmaUninitialize(void)
6208 {
6209 #ifdef RTE_USART15_PIN_DEINIT
6210 RTE_USART15_PIN_DEINIT();
6211 #endif
6212 return LPUART_EdmaUninitialize(&LPUART15_EdmaDriverState);
6213 }
6214
LPUART15_EdmaPowerControl(ARM_POWER_STATE state)6215 static int32_t LPUART15_EdmaPowerControl(ARM_POWER_STATE state)
6216 {
6217 return LPUART_EdmaPowerControl(state, &LPUART15_EdmaDriverState);
6218 }
6219
LPUART15_EdmaSend(const void * data,uint32_t num)6220 static int32_t LPUART15_EdmaSend(const void *data, uint32_t num)
6221 {
6222 return LPUART_EdmaSend(data, num, &LPUART15_EdmaDriverState);
6223 }
6224
LPUART15_EdmaReceive(void * data,uint32_t num)6225 static int32_t LPUART15_EdmaReceive(void *data, uint32_t num)
6226 {
6227 return LPUART_EdmaReceive(data, num, &LPUART15_EdmaDriverState);
6228 }
6229
LPUART15_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)6230 static int32_t LPUART15_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
6231 {
6232 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART15_EdmaDriverState);
6233 }
6234
LPUART15_EdmaGetTxCount(void)6235 static uint32_t LPUART15_EdmaGetTxCount(void)
6236 {
6237 return LPUART_EdmaGetTxCount(&LPUART15_EdmaDriverState);
6238 }
6239
LPUART15_EdmaGetRxCount(void)6240 static uint32_t LPUART15_EdmaGetRxCount(void)
6241 {
6242 return LPUART_EdmaGetRxCount(&LPUART15_EdmaDriverState);
6243 }
6244
LPUART15_EdmaControl(uint32_t control,uint32_t arg)6245 static int32_t LPUART15_EdmaControl(uint32_t control, uint32_t arg)
6246 {
6247 return LPUART_EdmaControl(control, arg, &LPUART15_EdmaDriverState);
6248 }
6249
LPUART15_EdmaGetStatus(void)6250 static ARM_USART_STATUS LPUART15_EdmaGetStatus(void)
6251 {
6252 return LPUART_EdmaGetStatus(&LPUART15_EdmaDriverState);
6253 }
6254
6255 #endif
6256
6257 #else
6258
6259 static lpuart_handle_t LPUART15_Handle;
6260
6261 #if defined(USART15_RX_BUFFER_ENABLE) && (USART15_RX_BUFFER_ENABLE == 1)
6262 static uint8_t lpuart15_rxRingBuffer[USART_RX_BUFFER_LEN];
6263 #endif
6264
6265 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6266 ARMCC_SECTION("lpuart15_non_blocking_driver_state")
6267 static cmsis_lpuart_non_blocking_driver_state_t LPUART15_NonBlockingDriverState = {
6268 #else
6269 static cmsis_lpuart_non_blocking_driver_state_t LPUART15_NonBlockingDriverState = {
6270 #endif
6271 &LPUART15_Resource,
6272 &LPUART15_Handle,
6273 };
6274
LPUART15_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)6275 static int32_t LPUART15_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
6276 {
6277 #ifdef RTE_USART15_PIN_INIT
6278 RTE_USART15_PIN_INIT();
6279 #endif
6280 return LPUART_NonBlockingInitialize(cb_event, &LPUART15_NonBlockingDriverState);
6281 }
6282
LPUART15_NonBlockingUninitialize(void)6283 static int32_t LPUART15_NonBlockingUninitialize(void)
6284 {
6285 #ifdef RTE_USART15_PIN_DEINIT
6286 RTE_USART15_PIN_DEINIT();
6287 #endif
6288 return LPUART_NonBlockingUninitialize(&LPUART15_NonBlockingDriverState);
6289 }
6290
LPUART15_NonBlockingPowerControl(ARM_POWER_STATE state)6291 static int32_t LPUART15_NonBlockingPowerControl(ARM_POWER_STATE state)
6292 {
6293 int32_t result;
6294
6295 result = LPUART_NonBlockingPowerControl(state, &LPUART15_NonBlockingDriverState);
6296
6297 #if defined(USART15_RX_BUFFER_ENABLE) && (USART15_RX_BUFFER_ENABLE == 1)
6298 if ((state == ARM_POWER_FULL) && (LPUART15_NonBlockingDriverState.handle->rxRingBuffer == NULL))
6299 {
6300 LPUART_TransferStartRingBuffer(LPUART15_NonBlockingDriverState.resource->base,
6301 LPUART15_NonBlockingDriverState.handle, lpuart15_rxRingBuffer,
6302 USART_RX_BUFFER_LEN);
6303 }
6304 #endif
6305
6306 return result;
6307 }
6308
LPUART15_NonBlockingSend(const void * data,uint32_t num)6309 static int32_t LPUART15_NonBlockingSend(const void *data, uint32_t num)
6310 {
6311 return LPUART_NonBlockingSend(data, num, &LPUART15_NonBlockingDriverState);
6312 }
6313
LPUART15_NonBlockingReceive(void * data,uint32_t num)6314 static int32_t LPUART15_NonBlockingReceive(void *data, uint32_t num)
6315 {
6316 return LPUART_NonBlockingReceive(data, num, &LPUART15_NonBlockingDriverState);
6317 }
6318
LPUART15_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)6319 static int32_t LPUART15_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
6320 {
6321 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART15_NonBlockingDriverState);
6322 }
6323
LPUART15_NonBlockingGetTxCount(void)6324 static uint32_t LPUART15_NonBlockingGetTxCount(void)
6325 {
6326 return LPUART_NonBlockingGetTxCount(&LPUART15_NonBlockingDriverState);
6327 }
6328
LPUART15_NonBlockingGetRxCount(void)6329 static uint32_t LPUART15_NonBlockingGetRxCount(void)
6330 {
6331 return LPUART_NonBlockingGetRxCount(&LPUART15_NonBlockingDriverState);
6332 }
6333
LPUART15_NonBlockingControl(uint32_t control,uint32_t arg)6334 static int32_t LPUART15_NonBlockingControl(uint32_t control, uint32_t arg)
6335 {
6336 int32_t result;
6337
6338 result = LPUART_NonBlockingControl(control, arg, &LPUART15_NonBlockingDriverState);
6339 if (ARM_DRIVER_OK != result)
6340 {
6341 return result;
6342 }
6343
6344 /* Enable the receive interrupts if ring buffer is used */
6345 if (LPUART15_NonBlockingDriverState.handle->rxRingBuffer != NULL)
6346 {
6347 LPUART_EnableInterrupts(
6348 LPUART15_NonBlockingDriverState.resource->base,
6349 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
6350 }
6351
6352 return ARM_DRIVER_OK;
6353 }
6354
LPUART15_NonBlockingGetStatus(void)6355 static ARM_USART_STATUS LPUART15_NonBlockingGetStatus(void)
6356 {
6357 return LPUART_NonBlockingGetStatus(&LPUART15_NonBlockingDriverState);
6358 }
6359
6360 #endif
6361
6362 ARM_DRIVER_USART Driver_USART15 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
6363 #if defined(RTE_USART15_DMA_EN) && RTE_USART15_DMA_EN
6364 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6365 LPUART15_EdmaInitialize, LPUART15_EdmaUninitialize, LPUART15_EdmaPowerControl,
6366 LPUART15_EdmaSend, LPUART15_EdmaReceive, LPUART15_EdmaTransfer,
6367 LPUART15_EdmaGetTxCount, LPUART15_EdmaGetRxCount, LPUART15_EdmaControl,
6368 LPUART15_EdmaGetStatus,
6369 #else
6370 LPUART15_DmaInitialize, LPUART15_DmaUninitialize, LPUART15_DmaPowerControl,
6371 LPUART15_DmaSend, LPUART15_DmaReceive, LPUART15_DmaTransfer,
6372 LPUART15_DmaGetTxCount, LPUART15_DmaGetRxCount, LPUART15_DmaControl,
6373 LPUART15_DmaGetStatus,
6374 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
6375 #else
6376 LPUART15_NonBlockingInitialize,
6377 LPUART15_NonBlockingUninitialize,
6378 LPUART15_NonBlockingPowerControl,
6379 LPUART15_NonBlockingSend,
6380 LPUART15_NonBlockingReceive,
6381 LPUART15_NonBlockingTransfer,
6382 LPUART15_NonBlockingGetTxCount,
6383 LPUART15_NonBlockingGetRxCount,
6384 LPUART15_NonBlockingControl,
6385 LPUART15_NonBlockingGetStatus,
6386 #endif /* RTE_USART15_DMA_EN */
6387 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
6388
6389 #endif /* LPUART15 */
6390
6391 #if defined(LPUART16) && defined(RTE_USART16) && RTE_USART16
6392
6393 /* User needs to provide the implementation for LPUART16_GetFreq/InitPins/DeinitPins
6394 in the application for enabling according instance. */
6395 extern uint32_t LPUART16_GetFreq(void);
6396
6397 static cmsis_lpuart_resource_t LPUART16_Resource = {LPUART16, LPUART16_GetFreq};
6398
6399 #if defined(RTE_USART16_DMA_EN) && RTE_USART16_DMA_EN
6400
6401 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
6402
6403 static cmsis_lpuart_dma_resource_t LPUART16_DmaResource = {
6404 RTE_USART16_DMA_TX_DMA_BASE, RTE_USART16_DMA_TX_CH, RTE_USART16_DMA_TX_PERI_SEL,
6405 RTE_USART16_DMA_RX_DMA_BASE, RTE_USART16_DMA_RX_CH, RTE_USART16_DMA_RX_PERI_SEL,
6406
6407 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6408 RTE_USART16_DMA_TX_DMAMUX_BASE, RTE_USART16_DMA_RX_DMAMUX_BASE,
6409 #endif
6410 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
6411 RTE_USART16_DMAMUX_TX_CH, RTE_USART16_DMAMUX_RX_CH
6412 #endif
6413 };
6414
6415 static lpuart_dma_handle_t LPUART16_DmaHandle;
6416 static dma_handle_t LPUART16_DmaRxHandle;
6417 static dma_handle_t LPUART16_DmaTxHandle;
6418
6419 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6420 ARMCC_SECTION("lpuart16_dma_driver_state")
6421 static cmsis_lpuart_dma_driver_state_t LPUART16_DmaDriverState = {
6422 #else
6423 static cmsis_lpuart_dma_driver_state_t LPUART16_DmaDriverState = {
6424 #endif
6425 &LPUART16_Resource, &LPUART16_DmaResource, &LPUART16_DmaHandle, &LPUART16_DmaRxHandle, &LPUART16_DmaTxHandle,
6426 };
6427
LPUART16_DmaInitialize(ARM_USART_SignalEvent_t cb_event)6428 static int32_t LPUART16_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
6429 {
6430 #ifdef RTE_USART16_PIN_INIT
6431 RTE_USART16_PIN_INIT();
6432 #endif
6433 return LPUART_DmaInitialize(cb_event, &LPUART16_DmaDriverState);
6434 }
6435
LPUART16_DmaUninitialize(void)6436 static int32_t LPUART16_DmaUninitialize(void)
6437 {
6438 #ifdef RTE_USART16_PIN_DEINIT
6439 RTE_USART16_PIN_DEINIT();
6440 #endif
6441 return LPUART_DmaUninitialize(&LPUART16_DmaDriverState);
6442 }
6443
LPUART16_DmaPowerControl(ARM_POWER_STATE state)6444 static int32_t LPUART16_DmaPowerControl(ARM_POWER_STATE state)
6445 {
6446 return LPUART_DmaPowerControl(state, &LPUART16_DmaDriverState);
6447 }
6448
LPUART16_DmaSend(const void * data,uint32_t num)6449 static int32_t LPUART16_DmaSend(const void *data, uint32_t num)
6450 {
6451 return LPUART_DmaSend(data, num, &LPUART16_DmaDriverState);
6452 }
6453
LPUART16_DmaReceive(void * data,uint32_t num)6454 static int32_t LPUART16_DmaReceive(void *data, uint32_t num)
6455 {
6456 return LPUART_DmaReceive(data, num, &LPUART16_DmaDriverState);
6457 }
6458
LPUART16_DmaTransfer(const void * data_out,void * data_in,uint32_t num)6459 static int32_t LPUART16_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
6460 {
6461 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART16_DmaDriverState);
6462 }
6463
LPUART16_DmaGetTxCount(void)6464 static uint32_t LPUART16_DmaGetTxCount(void)
6465 {
6466 return LPUART_DmaGetTxCount(&LPUART16_DmaDriverState);
6467 }
6468
LPUART16_DmaGetRxCount(void)6469 static uint32_t LPUART16_DmaGetRxCount(void)
6470 {
6471 return LPUART_DmaGetRxCount(&LPUART16_DmaDriverState);
6472 }
6473
LPUART16_DmaControl(uint32_t control,uint32_t arg)6474 static int32_t LPUART16_DmaControl(uint32_t control, uint32_t arg)
6475 {
6476 return LPUART_DmaControl(control, arg, &LPUART16_DmaDriverState);
6477 }
6478
LPUART16_DmaGetStatus(void)6479 static ARM_USART_STATUS LPUART16_DmaGetStatus(void)
6480 {
6481 return LPUART_DmaGetStatus(&LPUART16_DmaDriverState);
6482 }
6483
6484 /* LPUART16 Driver Control Block */
6485
6486 #endif
6487
6488 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6489
6490 static cmsis_lpuart_edma_resource_t LPUART16_EdmaResource = {
6491 RTE_USART16_DMA_TX_DMA_BASE, RTE_USART16_DMA_TX_CH, RTE_USART16_DMA_TX_PERI_SEL,
6492 RTE_USART16_DMA_RX_DMA_BASE, RTE_USART16_DMA_RX_CH, RTE_USART16_DMA_RX_PERI_SEL,
6493
6494 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6495 RTE_USART16_DMA_TX_DMAMUX_BASE, RTE_USART16_DMA_RX_DMAMUX_BASE,
6496 #endif
6497 };
6498
6499 static lpuart_edma_handle_t LPUART16_EdmaHandle;
6500 static edma_handle_t LPUART16_EdmaRxHandle;
6501 static edma_handle_t LPUART16_EdmaTxHandle;
6502
6503 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6504 ARMCC_SECTION("lpuart16_edma_driver_state")
6505 static cmsis_lpuart_edma_driver_state_t LPUART16_EdmaDriverState = {
6506 #else
6507 static cmsis_lpuart_edma_driver_state_t LPUART16_EdmaDriverState = {
6508 #endif
6509 &LPUART16_Resource, &LPUART16_EdmaResource, &LPUART16_EdmaHandle, &LPUART16_EdmaRxHandle, &LPUART16_EdmaTxHandle,
6510 };
6511
LPUART16_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)6512 static int32_t LPUART16_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
6513 {
6514 #ifdef RTE_USART16_PIN_INIT
6515 RTE_USART16_PIN_INIT();
6516 #endif
6517 return LPUART_EdmaInitialize(cb_event, &LPUART16_EdmaDriverState);
6518 }
6519
LPUART16_EdmaUninitialize(void)6520 static int32_t LPUART16_EdmaUninitialize(void)
6521 {
6522 #ifdef RTE_USART16_PIN_DEINIT
6523 RTE_USART16_PIN_DEINIT();
6524 #endif
6525 return LPUART_EdmaUninitialize(&LPUART16_EdmaDriverState);
6526 }
6527
LPUART16_EdmaPowerControl(ARM_POWER_STATE state)6528 static int32_t LPUART16_EdmaPowerControl(ARM_POWER_STATE state)
6529 {
6530 return LPUART_EdmaPowerControl(state, &LPUART16_EdmaDriverState);
6531 }
6532
LPUART16_EdmaSend(const void * data,uint32_t num)6533 static int32_t LPUART16_EdmaSend(const void *data, uint32_t num)
6534 {
6535 return LPUART_EdmaSend(data, num, &LPUART16_EdmaDriverState);
6536 }
6537
LPUART16_EdmaReceive(void * data,uint32_t num)6538 static int32_t LPUART16_EdmaReceive(void *data, uint32_t num)
6539 {
6540 return LPUART_EdmaReceive(data, num, &LPUART16_EdmaDriverState);
6541 }
6542
LPUART16_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)6543 static int32_t LPUART16_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
6544 {
6545 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART16_EdmaDriverState);
6546 }
6547
LPUART16_EdmaGetTxCount(void)6548 static uint32_t LPUART16_EdmaGetTxCount(void)
6549 {
6550 return LPUART_EdmaGetTxCount(&LPUART16_EdmaDriverState);
6551 }
6552
LPUART16_EdmaGetRxCount(void)6553 static uint32_t LPUART16_EdmaGetRxCount(void)
6554 {
6555 return LPUART_EdmaGetRxCount(&LPUART16_EdmaDriverState);
6556 }
6557
LPUART16_EdmaControl(uint32_t control,uint32_t arg)6558 static int32_t LPUART16_EdmaControl(uint32_t control, uint32_t arg)
6559 {
6560 return LPUART_EdmaControl(control, arg, &LPUART16_EdmaDriverState);
6561 }
6562
LPUART16_EdmaGetStatus(void)6563 static ARM_USART_STATUS LPUART16_EdmaGetStatus(void)
6564 {
6565 return LPUART_EdmaGetStatus(&LPUART16_EdmaDriverState);
6566 }
6567
6568 #endif
6569
6570 #else
6571
6572 static lpuart_handle_t LPUART16_Handle;
6573
6574 #if defined(USART16_RX_BUFFER_ENABLE) && (USART16_RX_BUFFER_ENABLE == 1)
6575 static uint8_t lpuart16_rxRingBuffer[USART_RX_BUFFER_LEN];
6576 #endif
6577
6578 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6579 ARMCC_SECTION("lpuart16_non_blocking_driver_state")
6580 static cmsis_lpuart_non_blocking_driver_state_t LPUART16_NonBlockingDriverState = {
6581 #else
6582 static cmsis_lpuart_non_blocking_driver_state_t LPUART16_NonBlockingDriverState = {
6583 #endif
6584 &LPUART16_Resource,
6585 &LPUART16_Handle,
6586 };
6587
LPUART16_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)6588 static int32_t LPUART16_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
6589 {
6590 #ifdef RTE_USART16_PIN_INIT
6591 RTE_USART16_PIN_INIT();
6592 #endif
6593 return LPUART_NonBlockingInitialize(cb_event, &LPUART16_NonBlockingDriverState);
6594 }
6595
LPUART16_NonBlockingUninitialize(void)6596 static int32_t LPUART16_NonBlockingUninitialize(void)
6597 {
6598 #ifdef RTE_USART16_PIN_DEINIT
6599 RTE_USART16_PIN_DEINIT();
6600 #endif
6601 return LPUART_NonBlockingUninitialize(&LPUART16_NonBlockingDriverState);
6602 }
6603
LPUART16_NonBlockingPowerControl(ARM_POWER_STATE state)6604 static int32_t LPUART16_NonBlockingPowerControl(ARM_POWER_STATE state)
6605 {
6606 int32_t result;
6607
6608 result = LPUART_NonBlockingPowerControl(state, &LPUART16_NonBlockingDriverState);
6609
6610 #if defined(USART16_RX_BUFFER_ENABLE) && (USART16_RX_BUFFER_ENABLE == 1)
6611 if ((state == ARM_POWER_FULL) && (LPUART16_NonBlockingDriverState.handle->rxRingBuffer == NULL))
6612 {
6613 LPUART_TransferStartRingBuffer(LPUART16_NonBlockingDriverState.resource->base,
6614 LPUART16_NonBlockingDriverState.handle, lpuart16_rxRingBuffer,
6615 USART_RX_BUFFER_LEN);
6616 }
6617 #endif
6618
6619 return result;
6620 }
6621
LPUART16_NonBlockingSend(const void * data,uint32_t num)6622 static int32_t LPUART16_NonBlockingSend(const void *data, uint32_t num)
6623 {
6624 return LPUART_NonBlockingSend(data, num, &LPUART16_NonBlockingDriverState);
6625 }
6626
LPUART16_NonBlockingReceive(void * data,uint32_t num)6627 static int32_t LPUART16_NonBlockingReceive(void *data, uint32_t num)
6628 {
6629 return LPUART_NonBlockingReceive(data, num, &LPUART16_NonBlockingDriverState);
6630 }
6631
LPUART16_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)6632 static int32_t LPUART16_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
6633 {
6634 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART16_NonBlockingDriverState);
6635 }
6636
LPUART16_NonBlockingGetTxCount(void)6637 static uint32_t LPUART16_NonBlockingGetTxCount(void)
6638 {
6639 return LPUART_NonBlockingGetTxCount(&LPUART16_NonBlockingDriverState);
6640 }
6641
LPUART16_NonBlockingGetRxCount(void)6642 static uint32_t LPUART16_NonBlockingGetRxCount(void)
6643 {
6644 return LPUART_NonBlockingGetRxCount(&LPUART16_NonBlockingDriverState);
6645 }
6646
LPUART16_NonBlockingControl(uint32_t control,uint32_t arg)6647 static int32_t LPUART16_NonBlockingControl(uint32_t control, uint32_t arg)
6648 {
6649 int32_t result;
6650
6651 result = LPUART_NonBlockingControl(control, arg, &LPUART16_NonBlockingDriverState);
6652 if (ARM_DRIVER_OK != result)
6653 {
6654 return result;
6655 }
6656
6657 /* Enable the receive interrupts if ring buffer is used */
6658 if (LPUART16_NonBlockingDriverState.handle->rxRingBuffer != NULL)
6659 {
6660 LPUART_EnableInterrupts(
6661 LPUART16_NonBlockingDriverState.resource->base,
6662 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
6663 }
6664
6665 return ARM_DRIVER_OK;
6666 }
6667
LPUART16_NonBlockingGetStatus(void)6668 static ARM_USART_STATUS LPUART16_NonBlockingGetStatus(void)
6669 {
6670 return LPUART_NonBlockingGetStatus(&LPUART16_NonBlockingDriverState);
6671 }
6672
6673 #endif
6674
6675 ARM_DRIVER_USART Driver_USART16 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
6676 #if defined(RTE_USART16_DMA_EN) && RTE_USART16_DMA_EN
6677 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6678 LPUART16_EdmaInitialize, LPUART16_EdmaUninitialize, LPUART16_EdmaPowerControl,
6679 LPUART16_EdmaSend, LPUART16_EdmaReceive, LPUART16_EdmaTransfer,
6680 LPUART16_EdmaGetTxCount, LPUART16_EdmaGetRxCount, LPUART16_EdmaControl,
6681 LPUART16_EdmaGetStatus,
6682 #else
6683 LPUART16_DmaInitialize, LPUART16_DmaUninitialize, LPUART16_DmaPowerControl,
6684 LPUART16_DmaSend, LPUART16_DmaReceive, LPUART16_DmaTransfer,
6685 LPUART16_DmaGetTxCount, LPUART16_DmaGetRxCount, LPUART16_DmaControl,
6686 LPUART16_DmaGetStatus,
6687 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
6688 #else
6689 LPUART16_NonBlockingInitialize,
6690 LPUART16_NonBlockingUninitialize,
6691 LPUART16_NonBlockingPowerControl,
6692 LPUART16_NonBlockingSend,
6693 LPUART16_NonBlockingReceive,
6694 LPUART16_NonBlockingTransfer,
6695 LPUART16_NonBlockingGetTxCount,
6696 LPUART16_NonBlockingGetRxCount,
6697 LPUART16_NonBlockingControl,
6698 LPUART16_NonBlockingGetStatus,
6699 #endif /* RTE_USART16_DMA_EN */
6700 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
6701
6702 #endif /* LPUART16 */
6703
6704 #if defined(LPUART17) && defined(RTE_USART17) && RTE_USART17
6705
6706 /* User needs to provide the implementation for LPUART17_GetFreq/InitPins/DeinitPins
6707 in the application for enabling according instance. */
6708 extern uint32_t LPUART17_GetFreq(void);
6709
6710 static cmsis_lpuart_resource_t LPUART17_Resource = {LPUART17, LPUART17_GetFreq};
6711
6712 #if defined(RTE_USART17_DMA_EN) && RTE_USART17_DMA_EN
6713
6714 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
6715
6716 static cmsis_lpuart_dma_resource_t LPUART17_DmaResource = {
6717 RTE_USART17_DMA_TX_DMA_BASE, RTE_USART17_DMA_TX_CH, RTE_USART17_DMA_TX_PERI_SEL,
6718 RTE_USART17_DMA_RX_DMA_BASE, RTE_USART17_DMA_RX_CH, RTE_USART17_DMA_RX_PERI_SEL,
6719
6720 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6721 RTE_USART17_DMA_TX_DMAMUX_BASE, RTE_USART17_DMA_RX_DMAMUX_BASE,
6722 #endif
6723 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
6724 RTE_USART17_DMAMUX_TX_CH, RTE_USART17_DMAMUX_RX_CH
6725 #endif
6726 };
6727
6728 static lpuart_dma_handle_t LPUART17_DmaHandle;
6729 static dma_handle_t LPUART17_DmaRxHandle;
6730 static dma_handle_t LPUART17_DmaTxHandle;
6731
6732 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6733 ARMCC_SECTION("lpuart17_dma_driver_state")
6734 static cmsis_lpuart_dma_driver_state_t LPUART17_DmaDriverState = {
6735 #else
6736 static cmsis_lpuart_dma_driver_state_t LPUART17_DmaDriverState = {
6737 #endif
6738 &LPUART17_Resource, &LPUART17_DmaResource, &LPUART17_DmaHandle, &LPUART17_DmaRxHandle, &LPUART17_DmaTxHandle,
6739 };
6740
LPUART17_DmaInitialize(ARM_USART_SignalEvent_t cb_event)6741 static int32_t LPUART17_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
6742 {
6743 #ifdef RTE_USART17_PIN_INIT
6744 RTE_USART17_PIN_INIT();
6745 #endif
6746 return LPUART_DmaInitialize(cb_event, &LPUART17_DmaDriverState);
6747 }
6748
LPUART17_DmaUninitialize(void)6749 static int32_t LPUART17_DmaUninitialize(void)
6750 {
6751 #ifdef RTE_USART17_PIN_DEINIT
6752 RTE_USART17_PIN_DEINIT();
6753 #endif
6754 return LPUART_DmaUninitialize(&LPUART17_DmaDriverState);
6755 }
6756
LPUART17_DmaPowerControl(ARM_POWER_STATE state)6757 static int32_t LPUART17_DmaPowerControl(ARM_POWER_STATE state)
6758 {
6759 return LPUART_DmaPowerControl(state, &LPUART17_DmaDriverState);
6760 }
6761
LPUART17_DmaSend(const void * data,uint32_t num)6762 static int32_t LPUART17_DmaSend(const void *data, uint32_t num)
6763 {
6764 return LPUART_DmaSend(data, num, &LPUART17_DmaDriverState);
6765 }
6766
LPUART17_DmaReceive(void * data,uint32_t num)6767 static int32_t LPUART17_DmaReceive(void *data, uint32_t num)
6768 {
6769 return LPUART_DmaReceive(data, num, &LPUART17_DmaDriverState);
6770 }
6771
LPUART17_DmaTransfer(const void * data_out,void * data_in,uint32_t num)6772 static int32_t LPUART17_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
6773 {
6774 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART17_DmaDriverState);
6775 }
6776
LPUART17_DmaGetTxCount(void)6777 static uint32_t LPUART17_DmaGetTxCount(void)
6778 {
6779 return LPUART_DmaGetTxCount(&LPUART17_DmaDriverState);
6780 }
6781
LPUART17_DmaGetRxCount(void)6782 static uint32_t LPUART17_DmaGetRxCount(void)
6783 {
6784 return LPUART_DmaGetRxCount(&LPUART17_DmaDriverState);
6785 }
6786
LPUART17_DmaControl(uint32_t control,uint32_t arg)6787 static int32_t LPUART17_DmaControl(uint32_t control, uint32_t arg)
6788 {
6789 return LPUART_DmaControl(control, arg, &LPUART17_DmaDriverState);
6790 }
6791
LPUART17_DmaGetStatus(void)6792 static ARM_USART_STATUS LPUART17_DmaGetStatus(void)
6793 {
6794 return LPUART_DmaGetStatus(&LPUART17_DmaDriverState);
6795 }
6796
6797 /* LPUART17 Driver Control Block */
6798
6799 #endif
6800
6801 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6802
6803 static cmsis_lpuart_edma_resource_t LPUART17_EdmaResource = {
6804 RTE_USART17_DMA_TX_DMA_BASE, RTE_USART17_DMA_TX_CH, RTE_USART17_DMA_TX_PERI_SEL,
6805 RTE_USART17_DMA_RX_DMA_BASE, RTE_USART17_DMA_RX_CH, RTE_USART17_DMA_RX_PERI_SEL,
6806
6807 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
6808 RTE_USART17_DMA_TX_DMAMUX_BASE, RTE_USART17_DMA_RX_DMAMUX_BASE,
6809 #endif
6810 };
6811
6812 static lpuart_edma_handle_t LPUART17_EdmaHandle;
6813 static edma_handle_t LPUART17_EdmaRxHandle;
6814 static edma_handle_t LPUART17_EdmaTxHandle;
6815
6816 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6817 ARMCC_SECTION("lpuart17_edma_driver_state")
6818 static cmsis_lpuart_edma_driver_state_t LPUART17_EdmaDriverState = {
6819 #else
6820 static cmsis_lpuart_edma_driver_state_t LPUART17_EdmaDriverState = {
6821 #endif
6822 &LPUART17_Resource, &LPUART17_EdmaResource, &LPUART17_EdmaHandle, &LPUART17_EdmaRxHandle, &LPUART17_EdmaTxHandle,
6823 };
6824
LPUART17_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)6825 static int32_t LPUART17_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
6826 {
6827 #ifdef RTE_USART17_PIN_INIT
6828 RTE_USART17_PIN_INIT();
6829 #endif
6830 return LPUART_EdmaInitialize(cb_event, &LPUART17_EdmaDriverState);
6831 }
6832
LPUART17_EdmaUninitialize(void)6833 static int32_t LPUART17_EdmaUninitialize(void)
6834 {
6835 #ifdef RTE_USART17_PIN_DEINIT
6836 RTE_USART17_PIN_DEINIT();
6837 #endif
6838 return LPUART_EdmaUninitialize(&LPUART17_EdmaDriverState);
6839 }
6840
LPUART17_EdmaPowerControl(ARM_POWER_STATE state)6841 static int32_t LPUART17_EdmaPowerControl(ARM_POWER_STATE state)
6842 {
6843 return LPUART_EdmaPowerControl(state, &LPUART17_EdmaDriverState);
6844 }
6845
LPUART17_EdmaSend(const void * data,uint32_t num)6846 static int32_t LPUART17_EdmaSend(const void *data, uint32_t num)
6847 {
6848 return LPUART_EdmaSend(data, num, &LPUART17_EdmaDriverState);
6849 }
6850
LPUART17_EdmaReceive(void * data,uint32_t num)6851 static int32_t LPUART17_EdmaReceive(void *data, uint32_t num)
6852 {
6853 return LPUART_EdmaReceive(data, num, &LPUART17_EdmaDriverState);
6854 }
6855
LPUART17_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)6856 static int32_t LPUART17_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
6857 {
6858 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART17_EdmaDriverState);
6859 }
6860
LPUART17_EdmaGetTxCount(void)6861 static uint32_t LPUART17_EdmaGetTxCount(void)
6862 {
6863 return LPUART_EdmaGetTxCount(&LPUART17_EdmaDriverState);
6864 }
6865
LPUART17_EdmaGetRxCount(void)6866 static uint32_t LPUART17_EdmaGetRxCount(void)
6867 {
6868 return LPUART_EdmaGetRxCount(&LPUART17_EdmaDriverState);
6869 }
6870
LPUART17_EdmaControl(uint32_t control,uint32_t arg)6871 static int32_t LPUART17_EdmaControl(uint32_t control, uint32_t arg)
6872 {
6873 return LPUART_EdmaControl(control, arg, &LPUART17_EdmaDriverState);
6874 }
6875
LPUART17_EdmaGetStatus(void)6876 static ARM_USART_STATUS LPUART17_EdmaGetStatus(void)
6877 {
6878 return LPUART_EdmaGetStatus(&LPUART17_EdmaDriverState);
6879 }
6880
6881 #endif
6882
6883 #else
6884
6885 static lpuart_handle_t LPUART17_Handle;
6886
6887 #if defined(USART17_RX_BUFFER_ENABLE) && (USART17_RX_BUFFER_ENABLE == 1)
6888 static uint8_t lpuart17_rxRingBuffer[USART_RX_BUFFER_LEN];
6889 #endif
6890
6891 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
6892 ARMCC_SECTION("lpuart17_non_blocking_driver_state")
6893 static cmsis_lpuart_non_blocking_driver_state_t LPUART17_NonBlockingDriverState = {
6894 #else
6895 static cmsis_lpuart_non_blocking_driver_state_t LPUART17_NonBlockingDriverState = {
6896 #endif
6897 &LPUART17_Resource,
6898 &LPUART17_Handle,
6899 };
6900
LPUART17_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)6901 static int32_t LPUART17_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
6902 {
6903 #ifdef RTE_USART17_PIN_INIT
6904 RTE_USART17_PIN_INIT();
6905 #endif
6906 return LPUART_NonBlockingInitialize(cb_event, &LPUART17_NonBlockingDriverState);
6907 }
6908
LPUART17_NonBlockingUninitialize(void)6909 static int32_t LPUART17_NonBlockingUninitialize(void)
6910 {
6911 #ifdef RTE_USART17_PIN_DEINIT
6912 RTE_USART17_PIN_DEINIT();
6913 #endif
6914 return LPUART_NonBlockingUninitialize(&LPUART17_NonBlockingDriverState);
6915 }
6916
LPUART17_NonBlockingPowerControl(ARM_POWER_STATE state)6917 static int32_t LPUART17_NonBlockingPowerControl(ARM_POWER_STATE state)
6918 {
6919 int32_t result;
6920
6921 result = LPUART_NonBlockingPowerControl(state, &LPUART17_NonBlockingDriverState);
6922
6923 #if defined(USART17_RX_BUFFER_ENABLE) && (USART17_RX_BUFFER_ENABLE == 1)
6924 if ((state == ARM_POWER_FULL) && (LPUART17_NonBlockingDriverState.handle->rxRingBuffer == NULL))
6925 {
6926 LPUART_TransferStartRingBuffer(LPUART17_NonBlockingDriverState.resource->base,
6927 LPUART17_NonBlockingDriverState.handle, lpuart17_rxRingBuffer,
6928 USART_RX_BUFFER_LEN);
6929 }
6930 #endif
6931
6932 return result;
6933 }
6934
LPUART17_NonBlockingSend(const void * data,uint32_t num)6935 static int32_t LPUART17_NonBlockingSend(const void *data, uint32_t num)
6936 {
6937 return LPUART_NonBlockingSend(data, num, &LPUART17_NonBlockingDriverState);
6938 }
6939
LPUART17_NonBlockingReceive(void * data,uint32_t num)6940 static int32_t LPUART17_NonBlockingReceive(void *data, uint32_t num)
6941 {
6942 return LPUART_NonBlockingReceive(data, num, &LPUART17_NonBlockingDriverState);
6943 }
6944
LPUART17_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)6945 static int32_t LPUART17_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
6946 {
6947 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART17_NonBlockingDriverState);
6948 }
6949
LPUART17_NonBlockingGetTxCount(void)6950 static uint32_t LPUART17_NonBlockingGetTxCount(void)
6951 {
6952 return LPUART_NonBlockingGetTxCount(&LPUART17_NonBlockingDriverState);
6953 }
6954
LPUART17_NonBlockingGetRxCount(void)6955 static uint32_t LPUART17_NonBlockingGetRxCount(void)
6956 {
6957 return LPUART_NonBlockingGetRxCount(&LPUART17_NonBlockingDriverState);
6958 }
6959
LPUART17_NonBlockingControl(uint32_t control,uint32_t arg)6960 static int32_t LPUART17_NonBlockingControl(uint32_t control, uint32_t arg)
6961 {
6962 int32_t result;
6963
6964 result = LPUART_NonBlockingControl(control, arg, &LPUART17_NonBlockingDriverState);
6965 if (ARM_DRIVER_OK != result)
6966 {
6967 return result;
6968 }
6969
6970 /* Enable the receive interrupts if ring buffer is used */
6971 if (LPUART17_NonBlockingDriverState.handle->rxRingBuffer != NULL)
6972 {
6973 LPUART_EnableInterrupts(
6974 LPUART17_NonBlockingDriverState.resource->base,
6975 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
6976 }
6977
6978 return ARM_DRIVER_OK;
6979 }
6980
LPUART17_NonBlockingGetStatus(void)6981 static ARM_USART_STATUS LPUART17_NonBlockingGetStatus(void)
6982 {
6983 return LPUART_NonBlockingGetStatus(&LPUART17_NonBlockingDriverState);
6984 }
6985
6986 #endif
6987
6988 ARM_DRIVER_USART Driver_USART17 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
6989 #if defined(RTE_USART17_DMA_EN) && RTE_USART17_DMA_EN
6990 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
6991 LPUART17_EdmaInitialize, LPUART17_EdmaUninitialize, LPUART17_EdmaPowerControl,
6992 LPUART17_EdmaSend, LPUART17_EdmaReceive, LPUART17_EdmaTransfer,
6993 LPUART17_EdmaGetTxCount, LPUART17_EdmaGetRxCount, LPUART17_EdmaControl,
6994 LPUART17_EdmaGetStatus,
6995 #else
6996 LPUART17_DmaInitialize, LPUART17_DmaUninitialize, LPUART17_DmaPowerControl,
6997 LPUART17_DmaSend, LPUART17_DmaReceive, LPUART17_DmaTransfer,
6998 LPUART17_DmaGetTxCount, LPUART17_DmaGetRxCount, LPUART17_DmaControl,
6999 LPUART17_DmaGetStatus,
7000 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
7001 #else
7002 LPUART17_NonBlockingInitialize,
7003 LPUART17_NonBlockingUninitialize,
7004 LPUART17_NonBlockingPowerControl,
7005 LPUART17_NonBlockingSend,
7006 LPUART17_NonBlockingReceive,
7007 LPUART17_NonBlockingTransfer,
7008 LPUART17_NonBlockingGetTxCount,
7009 LPUART17_NonBlockingGetRxCount,
7010 LPUART17_NonBlockingControl,
7011 LPUART17_NonBlockingGetStatus,
7012 #endif /* RTE_USART17_DMA_EN */
7013 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
7014
7015 #endif /* LPUART17 */
7016
7017 #if defined(LPUART18) && defined(RTE_USART18) && RTE_USART18
7018
7019 /* User needs to provide the implementation for LPUART18_GetFreq/InitPins/DeinitPins
7020 in the application for enabling according instance. */
7021 extern uint32_t LPUART18_GetFreq(void);
7022
7023 static cmsis_lpuart_resource_t LPUART18_Resource = {LPUART18, LPUART18_GetFreq};
7024
7025 #if defined(RTE_USART18_DMA_EN) && RTE_USART18_DMA_EN
7026
7027 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
7028
7029 static cmsis_lpuart_dma_resource_t LPUART18_DmaResource = {
7030 RTE_USART18_DMA_TX_DMA_BASE, RTE_USART18_DMA_TX_CH, RTE_USART18_DMA_TX_PERI_SEL,
7031 RTE_USART18_DMA_RX_DMA_BASE, RTE_USART18_DMA_RX_CH, RTE_USART18_DMA_RX_PERI_SEL,
7032
7033 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7034 RTE_USART18_DMA_TX_DMAMUX_BASE, RTE_USART18_DMA_RX_DMAMUX_BASE,
7035 #endif
7036 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
7037 RTE_USART18_DMAMUX_TX_CH, RTE_USART18_DMAMUX_RX_CH
7038 #endif
7039 };
7040
7041 static lpuart_dma_handle_t LPUART18_DmaHandle;
7042 static dma_handle_t LPUART18_DmaRxHandle;
7043 static dma_handle_t LPUART18_DmaTxHandle;
7044
7045 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7046 ARMCC_SECTION("lpuart18_dma_driver_state")
7047 static cmsis_lpuart_dma_driver_state_t LPUART18_DmaDriverState = {
7048 #else
7049 static cmsis_lpuart_dma_driver_state_t LPUART18_DmaDriverState = {
7050 #endif
7051 &LPUART18_Resource, &LPUART18_DmaResource, &LPUART18_DmaHandle, &LPUART18_DmaRxHandle, &LPUART18_DmaTxHandle,
7052 };
7053
LPUART18_DmaInitialize(ARM_USART_SignalEvent_t cb_event)7054 static int32_t LPUART18_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
7055 {
7056 #ifdef RTE_USART18_PIN_INIT
7057 RTE_USART18_PIN_INIT();
7058 #endif
7059 return LPUART_DmaInitialize(cb_event, &LPUART18_DmaDriverState);
7060 }
7061
LPUART18_DmaUninitialize(void)7062 static int32_t LPUART18_DmaUninitialize(void)
7063 {
7064 #ifdef RTE_USART18_PIN_DEINIT
7065 RTE_USART18_PIN_DEINIT();
7066 #endif
7067 return LPUART_DmaUninitialize(&LPUART18_DmaDriverState);
7068 }
7069
LPUART18_DmaPowerControl(ARM_POWER_STATE state)7070 static int32_t LPUART18_DmaPowerControl(ARM_POWER_STATE state)
7071 {
7072 return LPUART_DmaPowerControl(state, &LPUART18_DmaDriverState);
7073 }
7074
LPUART18_DmaSend(const void * data,uint32_t num)7075 static int32_t LPUART18_DmaSend(const void *data, uint32_t num)
7076 {
7077 return LPUART_DmaSend(data, num, &LPUART18_DmaDriverState);
7078 }
7079
LPUART18_DmaReceive(void * data,uint32_t num)7080 static int32_t LPUART18_DmaReceive(void *data, uint32_t num)
7081 {
7082 return LPUART_DmaReceive(data, num, &LPUART18_DmaDriverState);
7083 }
7084
LPUART18_DmaTransfer(const void * data_out,void * data_in,uint32_t num)7085 static int32_t LPUART18_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
7086 {
7087 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART18_DmaDriverState);
7088 }
7089
LPUART18_DmaGetTxCount(void)7090 static uint32_t LPUART18_DmaGetTxCount(void)
7091 {
7092 return LPUART_DmaGetTxCount(&LPUART18_DmaDriverState);
7093 }
7094
LPUART18_DmaGetRxCount(void)7095 static uint32_t LPUART18_DmaGetRxCount(void)
7096 {
7097 return LPUART_DmaGetRxCount(&LPUART18_DmaDriverState);
7098 }
7099
LPUART18_DmaControl(uint32_t control,uint32_t arg)7100 static int32_t LPUART18_DmaControl(uint32_t control, uint32_t arg)
7101 {
7102 return LPUART_DmaControl(control, arg, &LPUART18_DmaDriverState);
7103 }
7104
LPUART18_DmaGetStatus(void)7105 static ARM_USART_STATUS LPUART18_DmaGetStatus(void)
7106 {
7107 return LPUART_DmaGetStatus(&LPUART18_DmaDriverState);
7108 }
7109
7110 /* LPUART18 Driver Control Block */
7111
7112 #endif
7113
7114 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7115
7116 static cmsis_lpuart_edma_resource_t LPUART18_EdmaResource = {
7117 RTE_USART18_DMA_TX_DMA_BASE, RTE_USART18_DMA_TX_CH, RTE_USART18_DMA_TX_PERI_SEL,
7118 RTE_USART18_DMA_RX_DMA_BASE, RTE_USART18_DMA_RX_CH, RTE_USART18_DMA_RX_PERI_SEL,
7119
7120 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7121 RTE_USART18_DMA_TX_DMAMUX_BASE, RTE_USART18_DMA_RX_DMAMUX_BASE,
7122 #endif
7123 };
7124
7125 static lpuart_edma_handle_t LPUART18_EdmaHandle;
7126 static edma_handle_t LPUART18_EdmaRxHandle;
7127 static edma_handle_t LPUART18_EdmaTxHandle;
7128
7129 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7130 ARMCC_SECTION("lpuart18_edma_driver_state")
7131 static cmsis_lpuart_edma_driver_state_t LPUART18_EdmaDriverState = {
7132 #else
7133 static cmsis_lpuart_edma_driver_state_t LPUART18_EdmaDriverState = {
7134 #endif
7135 &LPUART18_Resource, &LPUART18_EdmaResource, &LPUART18_EdmaHandle, &LPUART18_EdmaRxHandle, &LPUART18_EdmaTxHandle,
7136 };
7137
LPUART18_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)7138 static int32_t LPUART18_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
7139 {
7140 #ifdef RTE_USART18_PIN_INIT
7141 RTE_USART18_PIN_INIT();
7142 #endif
7143 return LPUART_EdmaInitialize(cb_event, &LPUART18_EdmaDriverState);
7144 }
7145
LPUART18_EdmaUninitialize(void)7146 static int32_t LPUART18_EdmaUninitialize(void)
7147 {
7148 #ifdef RTE_USART18_PIN_DEINIT
7149 RTE_USART18_PIN_DEINIT();
7150 #endif
7151 return LPUART_EdmaUninitialize(&LPUART18_EdmaDriverState);
7152 }
7153
LPUART18_EdmaPowerControl(ARM_POWER_STATE state)7154 static int32_t LPUART18_EdmaPowerControl(ARM_POWER_STATE state)
7155 {
7156 return LPUART_EdmaPowerControl(state, &LPUART18_EdmaDriverState);
7157 }
7158
LPUART18_EdmaSend(const void * data,uint32_t num)7159 static int32_t LPUART18_EdmaSend(const void *data, uint32_t num)
7160 {
7161 return LPUART_EdmaSend(data, num, &LPUART18_EdmaDriverState);
7162 }
7163
LPUART18_EdmaReceive(void * data,uint32_t num)7164 static int32_t LPUART18_EdmaReceive(void *data, uint32_t num)
7165 {
7166 return LPUART_EdmaReceive(data, num, &LPUART18_EdmaDriverState);
7167 }
7168
LPUART18_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)7169 static int32_t LPUART18_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
7170 {
7171 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART18_EdmaDriverState);
7172 }
7173
LPUART18_EdmaGetTxCount(void)7174 static uint32_t LPUART18_EdmaGetTxCount(void)
7175 {
7176 return LPUART_EdmaGetTxCount(&LPUART18_EdmaDriverState);
7177 }
7178
LPUART18_EdmaGetRxCount(void)7179 static uint32_t LPUART18_EdmaGetRxCount(void)
7180 {
7181 return LPUART_EdmaGetRxCount(&LPUART18_EdmaDriverState);
7182 }
7183
LPUART18_EdmaControl(uint32_t control,uint32_t arg)7184 static int32_t LPUART18_EdmaControl(uint32_t control, uint32_t arg)
7185 {
7186 return LPUART_EdmaControl(control, arg, &LPUART18_EdmaDriverState);
7187 }
7188
LPUART18_EdmaGetStatus(void)7189 static ARM_USART_STATUS LPUART18_EdmaGetStatus(void)
7190 {
7191 return LPUART_EdmaGetStatus(&LPUART18_EdmaDriverState);
7192 }
7193
7194 #endif
7195
7196 #else
7197
7198 static lpuart_handle_t LPUART18_Handle;
7199
7200 #if defined(USART18_RX_BUFFER_ENABLE) && (USART18_RX_BUFFER_ENABLE == 1)
7201 static uint8_t lpuart18_rxRingBuffer[USART_RX_BUFFER_LEN];
7202 #endif
7203
7204 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7205 ARMCC_SECTION("lpuart18_non_blocking_driver_state")
7206 static cmsis_lpuart_non_blocking_driver_state_t LPUART18_NonBlockingDriverState = {
7207 #else
7208 static cmsis_lpuart_non_blocking_driver_state_t LPUART18_NonBlockingDriverState = {
7209 #endif
7210 &LPUART18_Resource,
7211 &LPUART18_Handle,
7212 };
7213
LPUART18_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)7214 static int32_t LPUART18_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
7215 {
7216 #ifdef RTE_USART18_PIN_INIT
7217 RTE_USART18_PIN_INIT();
7218 #endif
7219 return LPUART_NonBlockingInitialize(cb_event, &LPUART18_NonBlockingDriverState);
7220 }
7221
LPUART18_NonBlockingUninitialize(void)7222 static int32_t LPUART18_NonBlockingUninitialize(void)
7223 {
7224 #ifdef RTE_USART18_PIN_DEINIT
7225 RTE_USART18_PIN_DEINIT();
7226 #endif
7227 return LPUART_NonBlockingUninitialize(&LPUART18_NonBlockingDriverState);
7228 }
7229
LPUART18_NonBlockingPowerControl(ARM_POWER_STATE state)7230 static int32_t LPUART18_NonBlockingPowerControl(ARM_POWER_STATE state)
7231 {
7232 int32_t result;
7233
7234 result = LPUART_NonBlockingPowerControl(state, &LPUART18_NonBlockingDriverState);
7235
7236 #if defined(USART18_RX_BUFFER_ENABLE) && (USART18_RX_BUFFER_ENABLE == 1)
7237 if ((state == ARM_POWER_FULL) && (LPUART18_NonBlockingDriverState.handle->rxRingBuffer == NULL))
7238 {
7239 LPUART_TransferStartRingBuffer(LPUART18_NonBlockingDriverState.resource->base,
7240 LPUART18_NonBlockingDriverState.handle, lpuart18_rxRingBuffer,
7241 USART_RX_BUFFER_LEN);
7242 }
7243 #endif
7244
7245 return result;
7246 }
7247
LPUART18_NonBlockingSend(const void * data,uint32_t num)7248 static int32_t LPUART18_NonBlockingSend(const void *data, uint32_t num)
7249 {
7250 return LPUART_NonBlockingSend(data, num, &LPUART18_NonBlockingDriverState);
7251 }
7252
LPUART18_NonBlockingReceive(void * data,uint32_t num)7253 static int32_t LPUART18_NonBlockingReceive(void *data, uint32_t num)
7254 {
7255 return LPUART_NonBlockingReceive(data, num, &LPUART18_NonBlockingDriverState);
7256 }
7257
LPUART18_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)7258 static int32_t LPUART18_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
7259 {
7260 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART18_NonBlockingDriverState);
7261 }
7262
LPUART18_NonBlockingGetTxCount(void)7263 static uint32_t LPUART18_NonBlockingGetTxCount(void)
7264 {
7265 return LPUART_NonBlockingGetTxCount(&LPUART18_NonBlockingDriverState);
7266 }
7267
LPUART18_NonBlockingGetRxCount(void)7268 static uint32_t LPUART18_NonBlockingGetRxCount(void)
7269 {
7270 return LPUART_NonBlockingGetRxCount(&LPUART18_NonBlockingDriverState);
7271 }
7272
LPUART18_NonBlockingControl(uint32_t control,uint32_t arg)7273 static int32_t LPUART18_NonBlockingControl(uint32_t control, uint32_t arg)
7274 {
7275 int32_t result;
7276
7277 result = LPUART_NonBlockingControl(control, arg, &LPUART18_NonBlockingDriverState);
7278 if (ARM_DRIVER_OK != result)
7279 {
7280 return result;
7281 }
7282
7283 /* Enable the receive interrupts if ring buffer is used */
7284 if (LPUART18_NonBlockingDriverState.handle->rxRingBuffer != NULL)
7285 {
7286 LPUART_EnableInterrupts(
7287 LPUART18_NonBlockingDriverState.resource->base,
7288 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
7289 }
7290
7291 return ARM_DRIVER_OK;
7292 }
7293
LPUART18_NonBlockingGetStatus(void)7294 static ARM_USART_STATUS LPUART18_NonBlockingGetStatus(void)
7295 {
7296 return LPUART_NonBlockingGetStatus(&LPUART18_NonBlockingDriverState);
7297 }
7298
7299 #endif
7300
7301 ARM_DRIVER_USART Driver_USART18 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
7302 #if defined(RTE_USART18_DMA_EN) && RTE_USART18_DMA_EN
7303 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7304 LPUART18_EdmaInitialize, LPUART18_EdmaUninitialize, LPUART18_EdmaPowerControl,
7305 LPUART18_EdmaSend, LPUART18_EdmaReceive, LPUART18_EdmaTransfer,
7306 LPUART18_EdmaGetTxCount, LPUART18_EdmaGetRxCount, LPUART18_EdmaControl,
7307 LPUART18_EdmaGetStatus,
7308 #else
7309 LPUART18_DmaInitialize, LPUART18_DmaUninitialize, LPUART18_DmaPowerControl,
7310 LPUART18_DmaSend, LPUART18_DmaReceive, LPUART18_DmaTransfer,
7311 LPUART18_DmaGetTxCount, LPUART18_DmaGetRxCount, LPUART18_DmaControl,
7312 LPUART18_DmaGetStatus,
7313 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
7314 #else
7315 LPUART18_NonBlockingInitialize,
7316 LPUART18_NonBlockingUninitialize,
7317 LPUART18_NonBlockingPowerControl,
7318 LPUART18_NonBlockingSend,
7319 LPUART18_NonBlockingReceive,
7320 LPUART18_NonBlockingTransfer,
7321 LPUART18_NonBlockingGetTxCount,
7322 LPUART18_NonBlockingGetRxCount,
7323 LPUART18_NonBlockingControl,
7324 LPUART18_NonBlockingGetStatus,
7325 #endif /* RTE_USART18_DMA_EN */
7326 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
7327
7328 #endif /* LPUART18 */
7329
7330 #if defined(LPUART19) && defined(RTE_USART19) && RTE_USART19
7331
7332 /* User needs to provide the implementation for LPUART19_GetFreq/InitPins/DeinitPins
7333 in the application for enabling according instance. */
7334 extern uint32_t LPUART19_GetFreq(void);
7335
7336 static cmsis_lpuart_resource_t LPUART19_Resource = {LPUART19, LPUART19_GetFreq};
7337
7338 #if defined(RTE_USART19_DMA_EN) && RTE_USART19_DMA_EN
7339
7340 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
7341
7342 static cmsis_lpuart_dma_resource_t LPUART19_DmaResource = {
7343 RTE_USART19_DMA_TX_DMA_BASE, RTE_USART19_DMA_TX_CH, RTE_USART19_DMA_TX_PERI_SEL,
7344 RTE_USART19_DMA_RX_DMA_BASE, RTE_USART19_DMA_RX_CH, RTE_USART19_DMA_RX_PERI_SEL,
7345
7346 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7347 RTE_USART19_DMA_TX_DMAMUX_BASE, RTE_USART19_DMA_RX_DMAMUX_BASE,
7348 #endif
7349 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
7350 RTE_USART19_DMAMUX_TX_CH, RTE_USART19_DMAMUX_RX_CH
7351 #endif
7352 };
7353
7354 static lpuart_dma_handle_t LPUART19_DmaHandle;
7355 static dma_handle_t LPUART19_DmaRxHandle;
7356 static dma_handle_t LPUART19_DmaTxHandle;
7357
7358 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7359 ARMCC_SECTION("lpuart19_dma_driver_state")
7360 static cmsis_lpuart_dma_driver_state_t LPUART19_DmaDriverState = {
7361 #else
7362 static cmsis_lpuart_dma_driver_state_t LPUART19_DmaDriverState = {
7363 #endif
7364 &LPUART19_Resource, &LPUART19_DmaResource, &LPUART19_DmaHandle, &LPUART19_DmaRxHandle, &LPUART19_DmaTxHandle,
7365 };
7366
LPUART19_DmaInitialize(ARM_USART_SignalEvent_t cb_event)7367 static int32_t LPUART19_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
7368 {
7369 #ifdef RTE_USART19_PIN_INIT
7370 RTE_USART19_PIN_INIT();
7371 #endif
7372 return LPUART_DmaInitialize(cb_event, &LPUART19_DmaDriverState);
7373 }
7374
LPUART19_DmaUninitialize(void)7375 static int32_t LPUART19_DmaUninitialize(void)
7376 {
7377 #ifdef RTE_USART19_PIN_DEINIT
7378 RTE_USART19_PIN_DEINIT();
7379 #endif
7380 return LPUART_DmaUninitialize(&LPUART19_DmaDriverState);
7381 }
7382
LPUART19_DmaPowerControl(ARM_POWER_STATE state)7383 static int32_t LPUART19_DmaPowerControl(ARM_POWER_STATE state)
7384 {
7385 return LPUART_DmaPowerControl(state, &LPUART19_DmaDriverState);
7386 }
7387
LPUART19_DmaSend(const void * data,uint32_t num)7388 static int32_t LPUART19_DmaSend(const void *data, uint32_t num)
7389 {
7390 return LPUART_DmaSend(data, num, &LPUART19_DmaDriverState);
7391 }
7392
LPUART19_DmaReceive(void * data,uint32_t num)7393 static int32_t LPUART19_DmaReceive(void *data, uint32_t num)
7394 {
7395 return LPUART_DmaReceive(data, num, &LPUART19_DmaDriverState);
7396 }
7397
LPUART19_DmaTransfer(const void * data_out,void * data_in,uint32_t num)7398 static int32_t LPUART19_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
7399 {
7400 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART19_DmaDriverState);
7401 }
7402
LPUART19_DmaGetTxCount(void)7403 static uint32_t LPUART19_DmaGetTxCount(void)
7404 {
7405 return LPUART_DmaGetTxCount(&LPUART19_DmaDriverState);
7406 }
7407
LPUART19_DmaGetRxCount(void)7408 static uint32_t LPUART19_DmaGetRxCount(void)
7409 {
7410 return LPUART_DmaGetRxCount(&LPUART19_DmaDriverState);
7411 }
7412
LPUART19_DmaControl(uint32_t control,uint32_t arg)7413 static int32_t LPUART19_DmaControl(uint32_t control, uint32_t arg)
7414 {
7415 return LPUART_DmaControl(control, arg, &LPUART19_DmaDriverState);
7416 }
7417
LPUART19_DmaGetStatus(void)7418 static ARM_USART_STATUS LPUART19_DmaGetStatus(void)
7419 {
7420 return LPUART_DmaGetStatus(&LPUART19_DmaDriverState);
7421 }
7422
7423 /* LPUART19 Driver Control Block */
7424
7425 #endif
7426
7427 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7428
7429 static cmsis_lpuart_edma_resource_t LPUART19_EdmaResource = {
7430 RTE_USART19_DMA_TX_DMA_BASE, RTE_USART19_DMA_TX_CH, RTE_USART19_DMA_TX_PERI_SEL,
7431 RTE_USART19_DMA_RX_DMA_BASE, RTE_USART19_DMA_RX_CH, RTE_USART19_DMA_RX_PERI_SEL,
7432
7433 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7434 RTE_USART19_DMA_TX_DMAMUX_BASE, RTE_USART19_DMA_RX_DMAMUX_BASE,
7435 #endif
7436 };
7437
7438 static lpuart_edma_handle_t LPUART19_EdmaHandle;
7439 static edma_handle_t LPUART19_EdmaRxHandle;
7440 static edma_handle_t LPUART19_EdmaTxHandle;
7441
7442 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7443 ARMCC_SECTION("lpuart19_edma_driver_state")
7444 static cmsis_lpuart_edma_driver_state_t LPUART19_EdmaDriverState = {
7445 #else
7446 static cmsis_lpuart_edma_driver_state_t LPUART19_EdmaDriverState = {
7447 #endif
7448 &LPUART19_Resource, &LPUART19_EdmaResource, &LPUART19_EdmaHandle, &LPUART19_EdmaRxHandle, &LPUART19_EdmaTxHandle,
7449 };
7450
LPUART19_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)7451 static int32_t LPUART19_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
7452 {
7453 #ifdef RTE_USART19_PIN_INIT
7454 RTE_USART19_PIN_INIT();
7455 #endif
7456 return LPUART_EdmaInitialize(cb_event, &LPUART19_EdmaDriverState);
7457 }
7458
LPUART19_EdmaUninitialize(void)7459 static int32_t LPUART19_EdmaUninitialize(void)
7460 {
7461 #ifdef RTE_USART19_PIN_DEINIT
7462 RTE_USART19_PIN_DEINIT();
7463 #endif
7464 return LPUART_EdmaUninitialize(&LPUART19_EdmaDriverState);
7465 }
7466
LPUART19_EdmaPowerControl(ARM_POWER_STATE state)7467 static int32_t LPUART19_EdmaPowerControl(ARM_POWER_STATE state)
7468 {
7469 return LPUART_EdmaPowerControl(state, &LPUART19_EdmaDriverState);
7470 }
7471
LPUART19_EdmaSend(const void * data,uint32_t num)7472 static int32_t LPUART19_EdmaSend(const void *data, uint32_t num)
7473 {
7474 return LPUART_EdmaSend(data, num, &LPUART19_EdmaDriverState);
7475 }
7476
LPUART19_EdmaReceive(void * data,uint32_t num)7477 static int32_t LPUART19_EdmaReceive(void *data, uint32_t num)
7478 {
7479 return LPUART_EdmaReceive(data, num, &LPUART19_EdmaDriverState);
7480 }
7481
LPUART19_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)7482 static int32_t LPUART19_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
7483 {
7484 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART19_EdmaDriverState);
7485 }
7486
LPUART19_EdmaGetTxCount(void)7487 static uint32_t LPUART19_EdmaGetTxCount(void)
7488 {
7489 return LPUART_EdmaGetTxCount(&LPUART19_EdmaDriverState);
7490 }
7491
LPUART19_EdmaGetRxCount(void)7492 static uint32_t LPUART19_EdmaGetRxCount(void)
7493 {
7494 return LPUART_EdmaGetRxCount(&LPUART19_EdmaDriverState);
7495 }
7496
LPUART19_EdmaControl(uint32_t control,uint32_t arg)7497 static int32_t LPUART19_EdmaControl(uint32_t control, uint32_t arg)
7498 {
7499 return LPUART_EdmaControl(control, arg, &LPUART19_EdmaDriverState);
7500 }
7501
LPUART19_EdmaGetStatus(void)7502 static ARM_USART_STATUS LPUART19_EdmaGetStatus(void)
7503 {
7504 return LPUART_EdmaGetStatus(&LPUART19_EdmaDriverState);
7505 }
7506
7507 #endif
7508
7509 #else
7510
7511 static lpuart_handle_t LPUART19_Handle;
7512
7513 #if defined(USART19_RX_BUFFER_ENABLE) && (USART19_RX_BUFFER_ENABLE == 1)
7514 static uint8_t lpuart19_rxRingBuffer[USART_RX_BUFFER_LEN];
7515 #endif
7516
7517 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7518 ARMCC_SECTION("lpuart19_non_blocking_driver_state")
7519 static cmsis_lpuart_non_blocking_driver_state_t LPUART19_NonBlockingDriverState = {
7520 #else
7521 static cmsis_lpuart_non_blocking_driver_state_t LPUART19_NonBlockingDriverState = {
7522 #endif
7523 &LPUART19_Resource,
7524 &LPUART19_Handle,
7525 };
7526
LPUART19_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)7527 static int32_t LPUART19_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
7528 {
7529 #ifdef RTE_USART19_PIN_INIT
7530 RTE_USART19_PIN_INIT();
7531 #endif
7532 return LPUART_NonBlockingInitialize(cb_event, &LPUART19_NonBlockingDriverState);
7533 }
7534
LPUART19_NonBlockingUninitialize(void)7535 static int32_t LPUART19_NonBlockingUninitialize(void)
7536 {
7537 #ifdef RTE_USART19_PIN_DEINIT
7538 RTE_USART19_PIN_DEINIT();
7539 #endif
7540 return LPUART_NonBlockingUninitialize(&LPUART19_NonBlockingDriverState);
7541 }
7542
LPUART19_NonBlockingPowerControl(ARM_POWER_STATE state)7543 static int32_t LPUART19_NonBlockingPowerControl(ARM_POWER_STATE state)
7544 {
7545 int32_t result;
7546
7547 result = LPUART_NonBlockingPowerControl(state, &LPUART19_NonBlockingDriverState);
7548
7549 #if defined(USART19_RX_BUFFER_ENABLE) && (USART19_RX_BUFFER_ENABLE == 1)
7550 if ((state == ARM_POWER_FULL) && (LPUART19_NonBlockingDriverState.handle->rxRingBuffer == NULL))
7551 {
7552 LPUART_TransferStartRingBuffer(LPUART19_NonBlockingDriverState.resource->base,
7553 LPUART19_NonBlockingDriverState.handle, lpuart19_rxRingBuffer,
7554 USART_RX_BUFFER_LEN);
7555 }
7556 #endif
7557
7558 return result;
7559 }
7560
LPUART19_NonBlockingSend(const void * data,uint32_t num)7561 static int32_t LPUART19_NonBlockingSend(const void *data, uint32_t num)
7562 {
7563 return LPUART_NonBlockingSend(data, num, &LPUART19_NonBlockingDriverState);
7564 }
7565
LPUART19_NonBlockingReceive(void * data,uint32_t num)7566 static int32_t LPUART19_NonBlockingReceive(void *data, uint32_t num)
7567 {
7568 return LPUART_NonBlockingReceive(data, num, &LPUART19_NonBlockingDriverState);
7569 }
7570
LPUART19_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)7571 static int32_t LPUART19_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
7572 {
7573 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART19_NonBlockingDriverState);
7574 }
7575
LPUART19_NonBlockingGetTxCount(void)7576 static uint32_t LPUART19_NonBlockingGetTxCount(void)
7577 {
7578 return LPUART_NonBlockingGetTxCount(&LPUART19_NonBlockingDriverState);
7579 }
7580
LPUART19_NonBlockingGetRxCount(void)7581 static uint32_t LPUART19_NonBlockingGetRxCount(void)
7582 {
7583 return LPUART_NonBlockingGetRxCount(&LPUART19_NonBlockingDriverState);
7584 }
7585
LPUART19_NonBlockingControl(uint32_t control,uint32_t arg)7586 static int32_t LPUART19_NonBlockingControl(uint32_t control, uint32_t arg)
7587 {
7588 int32_t result;
7589
7590 result = LPUART_NonBlockingControl(control, arg, &LPUART19_NonBlockingDriverState);
7591 if (ARM_DRIVER_OK != result)
7592 {
7593 return result;
7594 }
7595
7596 /* Enable the receive interrupts if ring buffer is used */
7597 if (LPUART19_NonBlockingDriverState.handle->rxRingBuffer != NULL)
7598 {
7599 LPUART_EnableInterrupts(
7600 LPUART19_NonBlockingDriverState.resource->base,
7601 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
7602 }
7603
7604 return ARM_DRIVER_OK;
7605 }
7606
LPUART19_NonBlockingGetStatus(void)7607 static ARM_USART_STATUS LPUART19_NonBlockingGetStatus(void)
7608 {
7609 return LPUART_NonBlockingGetStatus(&LPUART19_NonBlockingDriverState);
7610 }
7611
7612 #endif
7613
7614 ARM_DRIVER_USART Driver_USART19 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
7615 #if defined(RTE_USART19_DMA_EN) && RTE_USART19_DMA_EN
7616 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7617 LPUART19_EdmaInitialize, LPUART19_EdmaUninitialize, LPUART19_EdmaPowerControl,
7618 LPUART19_EdmaSend, LPUART19_EdmaReceive, LPUART19_EdmaTransfer,
7619 LPUART19_EdmaGetTxCount, LPUART19_EdmaGetRxCount, LPUART19_EdmaControl,
7620 LPUART19_EdmaGetStatus,
7621 #else
7622 LPUART19_DmaInitialize, LPUART19_DmaUninitialize, LPUART19_DmaPowerControl,
7623 LPUART19_DmaSend, LPUART19_DmaReceive, LPUART19_DmaTransfer,
7624 LPUART19_DmaGetTxCount, LPUART19_DmaGetRxCount, LPUART19_DmaControl,
7625 LPUART19_DmaGetStatus,
7626 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
7627 #else
7628 LPUART19_NonBlockingInitialize,
7629 LPUART19_NonBlockingUninitialize,
7630 LPUART19_NonBlockingPowerControl,
7631 LPUART19_NonBlockingSend,
7632 LPUART19_NonBlockingReceive,
7633 LPUART19_NonBlockingTransfer,
7634 LPUART19_NonBlockingGetTxCount,
7635 LPUART19_NonBlockingGetRxCount,
7636 LPUART19_NonBlockingControl,
7637 LPUART19_NonBlockingGetStatus,
7638 #endif /* RTE_USART19_DMA_EN */
7639 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
7640
7641 #endif /* LPUART19 */
7642
7643 #if defined(LPUART20) && defined(RTE_USART20) && RTE_USART20
7644
7645 /* User needs to provide the implementation for LPUART20_GetFreq/InitPins/DeinitPins
7646 in the application for enabling according instance. */
7647 extern uint32_t LPUART20_GetFreq(void);
7648
7649 static cmsis_lpuart_resource_t LPUART20_Resource = {LPUART20, LPUART20_GetFreq};
7650
7651 #if defined(RTE_USART20_DMA_EN) && RTE_USART20_DMA_EN
7652
7653 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
7654
7655 static cmsis_lpuart_dma_resource_t LPUART20_DmaResource = {
7656 RTE_USART20_DMA_TX_DMA_BASE, RTE_USART20_DMA_TX_CH, RTE_USART20_DMA_TX_PERI_SEL,
7657 RTE_USART20_DMA_RX_DMA_BASE, RTE_USART20_DMA_RX_CH, RTE_USART20_DMA_RX_PERI_SEL,
7658
7659 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7660 RTE_USART20_DMA_TX_DMAMUX_BASE, RTE_USART20_DMA_RX_DMAMUX_BASE,
7661 #endif
7662 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
7663 RTE_USART20_DMAMUX_TX_CH, RTE_USART20_DMAMUX_RX_CH
7664 #endif
7665 };
7666
7667 static lpuart_dma_handle_t LPUART20_DmaHandle;
7668 static dma_handle_t LPUART20_DmaRxHandle;
7669 static dma_handle_t LPUART20_DmaTxHandle;
7670
7671 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7672 ARMCC_SECTION("lpuart20_dma_driver_state")
7673 static cmsis_lpuart_dma_driver_state_t LPUART20_DmaDriverState = {
7674 #else
7675 static cmsis_lpuart_dma_driver_state_t LPUART20_DmaDriverState = {
7676 #endif
7677 &LPUART20_Resource, &LPUART20_DmaResource, &LPUART20_DmaHandle, &LPUART20_DmaRxHandle, &LPUART20_DmaTxHandle,
7678 };
7679
LPUART20_DmaInitialize(ARM_USART_SignalEvent_t cb_event)7680 static int32_t LPUART20_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
7681 {
7682 #ifdef RTE_USART20_PIN_INIT
7683 RTE_USART20_PIN_INIT();
7684 #endif
7685 return LPUART_DmaInitialize(cb_event, &LPUART20_DmaDriverState);
7686 }
7687
LPUART20_DmaUninitialize(void)7688 static int32_t LPUART20_DmaUninitialize(void)
7689 {
7690 #ifdef RTE_USART20_PIN_DEINIT
7691 RTE_USART20_PIN_DEINIT();
7692 #endif
7693 return LPUART_DmaUninitialize(&LPUART20_DmaDriverState);
7694 }
7695
LPUART20_DmaPowerControl(ARM_POWER_STATE state)7696 static int32_t LPUART20_DmaPowerControl(ARM_POWER_STATE state)
7697 {
7698 return LPUART_DmaPowerControl(state, &LPUART20_DmaDriverState);
7699 }
7700
LPUART20_DmaSend(const void * data,uint32_t num)7701 static int32_t LPUART20_DmaSend(const void *data, uint32_t num)
7702 {
7703 return LPUART_DmaSend(data, num, &LPUART20_DmaDriverState);
7704 }
7705
LPUART20_DmaReceive(void * data,uint32_t num)7706 static int32_t LPUART20_DmaReceive(void *data, uint32_t num)
7707 {
7708 return LPUART_DmaReceive(data, num, &LPUART20_DmaDriverState);
7709 }
7710
LPUART20_DmaTransfer(const void * data_out,void * data_in,uint32_t num)7711 static int32_t LPUART20_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
7712 {
7713 return LPUART_DmaTransfer(data_out, data_in, num, &LPUART20_DmaDriverState);
7714 }
7715
LPUART20_DmaGetTxCount(void)7716 static uint32_t LPUART20_DmaGetTxCount(void)
7717 {
7718 return LPUART_DmaGetTxCount(&LPUART20_DmaDriverState);
7719 }
7720
LPUART20_DmaGetRxCount(void)7721 static uint32_t LPUART20_DmaGetRxCount(void)
7722 {
7723 return LPUART_DmaGetRxCount(&LPUART20_DmaDriverState);
7724 }
7725
LPUART20_DmaControl(uint32_t control,uint32_t arg)7726 static int32_t LPUART20_DmaControl(uint32_t control, uint32_t arg)
7727 {
7728 return LPUART_DmaControl(control, arg, &LPUART20_DmaDriverState);
7729 }
7730
LPUART20_DmaGetStatus(void)7731 static ARM_USART_STATUS LPUART20_DmaGetStatus(void)
7732 {
7733 return LPUART_DmaGetStatus(&LPUART20_DmaDriverState);
7734 }
7735
7736 /* LPUART20 Driver Control Block */
7737
7738 #endif
7739
7740 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7741
7742 static cmsis_lpuart_edma_resource_t LPUART20_EdmaResource = {
7743 RTE_USART20_DMA_TX_DMA_BASE, RTE_USART20_DMA_TX_CH, RTE_USART20_DMA_TX_PERI_SEL,
7744 RTE_USART20_DMA_RX_DMA_BASE, RTE_USART20_DMA_RX_CH, RTE_USART20_DMA_RX_PERI_SEL,
7745
7746 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
7747 RTE_USART20_DMA_TX_DMAMUX_BASE, RTE_USART20_DMA_RX_DMAMUX_BASE,
7748 #endif
7749 };
7750
7751 static lpuart_edma_handle_t LPUART20_EdmaHandle;
7752 static edma_handle_t LPUART20_EdmaRxHandle;
7753 static edma_handle_t LPUART20_EdmaTxHandle;
7754
7755 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7756 ARMCC_SECTION("lpuart20_edma_driver_state")
7757 static cmsis_lpuart_edma_driver_state_t LPUART20_EdmaDriverState = {
7758 #else
7759 static cmsis_lpuart_edma_driver_state_t LPUART20_EdmaDriverState = {
7760 #endif
7761 &LPUART20_Resource, &LPUART20_EdmaResource, &LPUART20_EdmaHandle, &LPUART20_EdmaRxHandle, &LPUART20_EdmaTxHandle,
7762 };
7763
LPUART20_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)7764 static int32_t LPUART20_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
7765 {
7766 #ifdef RTE_USART20_PIN_INIT
7767 RTE_USART20_PIN_INIT();
7768 #endif
7769 return LPUART_EdmaInitialize(cb_event, &LPUART20_EdmaDriverState);
7770 }
7771
LPUART20_EdmaUninitialize(void)7772 static int32_t LPUART20_EdmaUninitialize(void)
7773 {
7774 #ifdef RTE_USART20_PIN_DEINIT
7775 RTE_USART20_PIN_DEINIT();
7776 #endif
7777 return LPUART_EdmaUninitialize(&LPUART20_EdmaDriverState);
7778 }
7779
LPUART20_EdmaPowerControl(ARM_POWER_STATE state)7780 static int32_t LPUART20_EdmaPowerControl(ARM_POWER_STATE state)
7781 {
7782 return LPUART_EdmaPowerControl(state, &LPUART20_EdmaDriverState);
7783 }
7784
LPUART20_EdmaSend(const void * data,uint32_t num)7785 static int32_t LPUART20_EdmaSend(const void *data, uint32_t num)
7786 {
7787 return LPUART_EdmaSend(data, num, &LPUART20_EdmaDriverState);
7788 }
7789
LPUART20_EdmaReceive(void * data,uint32_t num)7790 static int32_t LPUART20_EdmaReceive(void *data, uint32_t num)
7791 {
7792 return LPUART_EdmaReceive(data, num, &LPUART20_EdmaDriverState);
7793 }
7794
LPUART20_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)7795 static int32_t LPUART20_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
7796 {
7797 return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART20_EdmaDriverState);
7798 }
7799
LPUART20_EdmaGetTxCount(void)7800 static uint32_t LPUART20_EdmaGetTxCount(void)
7801 {
7802 return LPUART_EdmaGetTxCount(&LPUART20_EdmaDriverState);
7803 }
7804
LPUART20_EdmaGetRxCount(void)7805 static uint32_t LPUART20_EdmaGetRxCount(void)
7806 {
7807 return LPUART_EdmaGetRxCount(&LPUART20_EdmaDriverState);
7808 }
7809
LPUART20_EdmaControl(uint32_t control,uint32_t arg)7810 static int32_t LPUART20_EdmaControl(uint32_t control, uint32_t arg)
7811 {
7812 return LPUART_EdmaControl(control, arg, &LPUART20_EdmaDriverState);
7813 }
7814
LPUART20_EdmaGetStatus(void)7815 static ARM_USART_STATUS LPUART20_EdmaGetStatus(void)
7816 {
7817 return LPUART_EdmaGetStatus(&LPUART20_EdmaDriverState);
7818 }
7819
7820 #endif
7821
7822 #else
7823
7824 static lpuart_handle_t LPUART20_Handle;
7825
7826 #if defined(USART20_RX_BUFFER_ENABLE) && (USART20_RX_BUFFER_ENABLE == 1)
7827 static uint8_t lpuart20_rxRingBuffer[USART_RX_BUFFER_LEN];
7828 #endif
7829
7830 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
7831 ARMCC_SECTION("lpuart20_non_blocking_driver_state")
7832 static cmsis_lpuart_non_blocking_driver_state_t LPUART20_NonBlockingDriverState = {
7833 #else
7834 static cmsis_lpuart_non_blocking_driver_state_t LPUART20_NonBlockingDriverState = {
7835 #endif
7836 &LPUART20_Resource,
7837 &LPUART20_Handle,
7838 };
7839
LPUART20_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)7840 static int32_t LPUART20_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
7841 {
7842 #ifdef RTE_USART20_PIN_INIT
7843 RTE_USART20_PIN_INIT();
7844 #endif
7845 return LPUART_NonBlockingInitialize(cb_event, &LPUART20_NonBlockingDriverState);
7846 }
7847
LPUART20_NonBlockingUninitialize(void)7848 static int32_t LPUART20_NonBlockingUninitialize(void)
7849 {
7850 #ifdef RTE_USART20_PIN_DEINIT
7851 RTE_USART20_PIN_DEINIT();
7852 #endif
7853 return LPUART_NonBlockingUninitialize(&LPUART20_NonBlockingDriverState);
7854 }
7855
LPUART20_NonBlockingPowerControl(ARM_POWER_STATE state)7856 static int32_t LPUART20_NonBlockingPowerControl(ARM_POWER_STATE state)
7857 {
7858 int32_t result;
7859
7860 result = LPUART_NonBlockingPowerControl(state, &LPUART20_NonBlockingDriverState);
7861
7862 #if defined(USART20_RX_BUFFER_ENABLE) && (USART20_RX_BUFFER_ENABLE == 1)
7863 if ((state == ARM_POWER_FULL) && (LPUART20_NonBlockingDriverState.handle->rxRingBuffer == NULL))
7864 {
7865 LPUART_TransferStartRingBuffer(LPUART20_NonBlockingDriverState.resource->base,
7866 LPUART20_NonBlockingDriverState.handle, lpuart20_rxRingBuffer,
7867 USART_RX_BUFFER_LEN);
7868 }
7869 #endif
7870
7871 return result;
7872 }
7873
LPUART20_NonBlockingSend(const void * data,uint32_t num)7874 static int32_t LPUART20_NonBlockingSend(const void *data, uint32_t num)
7875 {
7876 return LPUART_NonBlockingSend(data, num, &LPUART20_NonBlockingDriverState);
7877 }
7878
LPUART20_NonBlockingReceive(void * data,uint32_t num)7879 static int32_t LPUART20_NonBlockingReceive(void *data, uint32_t num)
7880 {
7881 return LPUART_NonBlockingReceive(data, num, &LPUART20_NonBlockingDriverState);
7882 }
7883
LPUART20_NonBlockingTransfer(const void * data_out,void * data_in,uint32_t num)7884 static int32_t LPUART20_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
7885 {
7886 return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART20_NonBlockingDriverState);
7887 }
7888
LPUART20_NonBlockingGetTxCount(void)7889 static uint32_t LPUART20_NonBlockingGetTxCount(void)
7890 {
7891 return LPUART_NonBlockingGetTxCount(&LPUART20_NonBlockingDriverState);
7892 }
7893
LPUART20_NonBlockingGetRxCount(void)7894 static uint32_t LPUART20_NonBlockingGetRxCount(void)
7895 {
7896 return LPUART_NonBlockingGetRxCount(&LPUART20_NonBlockingDriverState);
7897 }
7898
LPUART20_NonBlockingControl(uint32_t control,uint32_t arg)7899 static int32_t LPUART20_NonBlockingControl(uint32_t control, uint32_t arg)
7900 {
7901 int32_t result;
7902
7903 result = LPUART_NonBlockingControl(control, arg, &LPUART20_NonBlockingDriverState);
7904 if (ARM_DRIVER_OK != result)
7905 {
7906 return result;
7907 }
7908
7909 /* Enable the receive interrupts if ring buffer is used */
7910 if (LPUART20_NonBlockingDriverState.handle->rxRingBuffer != NULL)
7911 {
7912 LPUART_EnableInterrupts(
7913 LPUART20_NonBlockingDriverState.resource->base,
7914 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
7915 }
7916
7917 return ARM_DRIVER_OK;
7918 }
7919
LPUART20_NonBlockingGetStatus(void)7920 static ARM_USART_STATUS LPUART20_NonBlockingGetStatus(void)
7921 {
7922 return LPUART_NonBlockingGetStatus(&LPUART20_NonBlockingDriverState);
7923 }
7924
7925 #endif
7926
7927 ARM_DRIVER_USART Driver_USART20 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities,
7928 #if defined(RTE_USART20_DMA_EN) && RTE_USART20_DMA_EN
7929 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
7930 LPUART20_EdmaInitialize, LPUART20_EdmaUninitialize, LPUART20_EdmaPowerControl,
7931 LPUART20_EdmaSend, LPUART20_EdmaReceive, LPUART20_EdmaTransfer,
7932 LPUART20_EdmaGetTxCount, LPUART20_EdmaGetRxCount, LPUART20_EdmaControl,
7933 LPUART20_EdmaGetStatus,
7934 #else
7935 LPUART20_DmaInitialize, LPUART20_DmaUninitialize, LPUART20_DmaPowerControl,
7936 LPUART20_DmaSend, LPUART20_DmaReceive, LPUART20_DmaTransfer,
7937 LPUART20_DmaGetTxCount, LPUART20_DmaGetRxCount, LPUART20_DmaControl,
7938 LPUART20_DmaGetStatus,
7939 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
7940 #else
7941 LPUART20_NonBlockingInitialize,
7942 LPUART20_NonBlockingUninitialize,
7943 LPUART20_NonBlockingPowerControl,
7944 LPUART20_NonBlockingSend,
7945 LPUART20_NonBlockingReceive,
7946 LPUART20_NonBlockingTransfer,
7947 LPUART20_NonBlockingGetTxCount,
7948 LPUART20_NonBlockingGetRxCount,
7949 LPUART20_NonBlockingControl,
7950 LPUART20_NonBlockingGetStatus,
7951 #endif /* RTE_USART20_DMA_EN */
7952 LPUARTx_SetModemControl, LPUARTx_GetModemStatus};
7953
7954 #endif /* LPUART20 */
7955
