1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /*
10 * How to setup clock using clock driver functions:
11 *
12 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
13 * and flash clock are in allowed range during clock mode switch.
14 *
15 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
16 *
17 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
18 * internal reference clock(MCGIRCLK). Follow the steps to setup:
19 *
20 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
21 *
22 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
23 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
24 * explicitly to setup MCGIRCLK.
25 *
26 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
27 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
28 * if the target mode is not FLL mode, the FLL is disabled.
29 *
30 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
31 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
32 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
33 *
34 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
35 */
36
37 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
38 !!ClocksProfile
39 product: Clocks v1.0
40 processor: MKV58F1M0xxx24
41 package_id: MKV58F1M0VLQ24
42 mcu_data: ksdk2_0
43 processor_version: 1.1.0
44 board: TWR-KV58F220M
45 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
46
47 #include "fsl_smc.h"
48 #include "clock_config.h"
49
50 /*******************************************************************************
51 * Definitions
52 ******************************************************************************/
53 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
54 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
55 #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
56 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
57 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
58
59 #define SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV 1U /*!< SIM CLKDIV1 maximum run mode core/system divider configurations */
60 #define SIM_CLKDIV1_RUN_MODE_MAX_FAST_PERIPHERAL_DIV 3U /*!< SIM CLKDIV1 maximum run mode bus divider configuration */
61 #define SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV 3U /*!< SIM CLKDIV1 maximum run mode flexbus divider configurations */
62 #define SIM_CLKDIV1_RUN_MODE_MAX_BUS_FLASH_DIV 9U /*!< SIM CLKDIV1 maximum run mode flash divider configurations */
63
64 /*******************************************************************************
65 * Variables
66 ******************************************************************************/
67 /* System clock frequency. */
68 extern uint32_t SystemCoreClock;
69
70 /*******************************************************************************
71 * Code
72 ******************************************************************************/
73 /*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_SetSimSafeDivs
76 * Description : This function sets the system clock dividers in SIM to safe
77 * value.
78 *
79 *END**************************************************************************/
CLOCK_CONFIG_SetSimSafeDivs(void)80 static void CLOCK_CONFIG_SetSimSafeDivs(void)
81 {
82 SIM->CLKDIV1 = 0x01170000U;
83 }
84
85 /*FUNCTION**********************************************************************
86 *
87 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
88 * Description : Configure FLL external reference divider (FRDIV).
89 * Param frdiv : The value to set FRDIV.
90 *
91 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)92 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
93 {
94 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
95 }
96
97 /*******************************************************************************
98 ********************** Configuration BOARD_BootClockRUN ***********************
99 ******************************************************************************/
100 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
101 !!Configuration
102 name: BOARD_BootClockRUN
103 outputs:
104 - {id: Bus_clock.outFreq, value: 72 MHz}
105 - {id: Core_clock.outFreq, value: 144 MHz}
106 - {id: ERCLK32K.outFreq, value: 1 kHz}
107 - {id: Flash_clock.outFreq, value: 14.4 MHz}
108 - {id: FlexBus_clock.outFreq, value: 36 MHz}
109 - {id: LPO_clock.outFreq, value: 1 kHz}
110 - {id: MCGFFCLK.outFreq, value: 1.5 MHz}
111 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
112 - {id: OSCERCLK.outFreq, value: 48 MHz}
113 - {id: OSCERCLK_UNDIV.outFreq, value: 48 MHz}
114 - {id: PLLFLLCLK.outFreq, value: 144 MHz}
115 - {id: System_clock.outFreq, value: 144 MHz}
116 settings:
117 - {id: MCGMode, value: PEE}
118 - {id: MCG.FCRDIV.scale, value: '1'}
119 - {id: MCG.FLL_mul.scale, value: '2560', locked: true}
120 - {id: MCG.FRDIV.scale, value: '32'}
121 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
122 - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
123 - {id: MCG.PRDIV.scale, value: '4', locked: true}
124 - {id: MCG.VDIV.scale, value: '24', locked: true}
125 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
126 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
127 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
128 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
129 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
130 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
131 - {id: SIM.OUTDIV2.scale, value: '2', locked: true}
132 - {id: SIM.OUTDIV3.scale, value: '4', locked: true}
133 - {id: SIM.OUTDIV4.scale, value: '10', locked: true}
134 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
135 - {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT}
136 - {id: SIM.TIMESRCSEL.sel, value: SIM.ENET_1588_CLK_EXT}
137 sources:
138 - {id: OSC.OSC.outFreq, value: 48 MHz, enabled: true}
139 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
140
141 /*******************************************************************************
142 * Variables for BOARD_BootClockRUN configuration
143 ******************************************************************************/
144 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
145 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
146 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
147 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
148 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
149 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
150 .drs = kMCG_DrsHigh, /* High frequency range */
151 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
152 .pll0Config =
153 {
154 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
155 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
156 .vdiv = 0x8U, /* VCO divider: multiplied by 24 */
157 },
158 };
159 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
160 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
161 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
162 .clkdiv1 = 0x01150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
163 };
164 const osc_config_t oscConfig_BOARD_BootClockRUN = {
165 .freq = 50000000U, /* Oscillator frequency: 48000000Hz */
166 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
167 .workMode = kOSC_ModeExt, /* Use external clock */
168 .oscerConfig = {
169 .enableMode =
170 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
171 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
172 }};
173
174 /*******************************************************************************
175 * Code for BOARD_BootClockRUN configuration
176 ******************************************************************************/
BOARD_BootClockRUN(void)177 void BOARD_BootClockRUN(void)
178 {
179 /* Set the system clock dividers in SIM to safe value. */
180 CLOCK_CONFIG_SetSimSafeDivs();
181 /* Initializes OSC0 according to board configuration. */
182 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
183 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
184 /* Configure FLL external reference divider (FRDIV). */
185 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
186 /* Set MCG to PEE mode. */
187 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockRUN.pll0Config);
188 /* Configure the Internal Reference clock (MCGIRCLK). */
189 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
190 mcgConfig_BOARD_BootClockRUN.fcrdiv);
191 /* Set the clock configuration in SIM module. */
192 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
193 /* Set SystemCoreClock variable. */
194 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
195 }
196
197 /*******************************************************************************
198 ********************* Configuration BOARD_BootClockVLPR ***********************
199 ******************************************************************************/
200 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
201 !!Configuration
202 name: BOARD_BootClockVLPR
203 outputs:
204 - {id: Bus_clock.outFreq, value: 4 MHz}
205 - {id: Core_clock.outFreq, value: 4 MHz}
206 - {id: ERCLK32K.outFreq, value: 1 kHz}
207 - {id: Flash_clock.outFreq, value: 500 kHz}
208 - {id: FlexBus_clock.outFreq, value: 4 MHz}
209 - {id: LPO_clock.outFreq, value: 1 kHz}
210 - {id: MCGIRCLK.outFreq, value: 4 MHz}
211 - {id: System_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
212 settings:
213 - {id: MCGMode, value: BLPI}
214 - {id: powerMode, value: VLPR}
215 - {id: MCG.CLKS.sel, value: MCG.IRCS}
216 - {id: MCG.FCRDIV.scale, value: '1'}
217 - {id: MCG.FRDIV.scale, value: '32'}
218 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
219 - {id: MCG.PRDIV.scale, value: '4'}
220 - {id: MCG.VDIV.scale, value: '32'}
221 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
222 - {id: MCG_C2_RANGE0_CFG, value: High}
223 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
224 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
225 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
226 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
227 - {id: SIM.OUTDIV4.scale, value: '8'}
228 - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
229 - {id: SIM.TRACECLKSEL.sel, value: MCG.MCGOUTCLK}
230 sources:
231 - {id: OSC.OSC.outFreq, value: 50 MHz}
232 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
233
234 /*******************************************************************************
235 * Variables for BOARD_BootClockVLPR configuration
236 ******************************************************************************/
237 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
238 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
239 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
240 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
241 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
242 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
243 .drs = kMCG_DrsLow, /* Low frequency range */
244 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
245 .pll0Config =
246 {
247 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
248 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
249 .vdiv = 0x10U, /* VCO divider: multiplied by 32 */
250 },
251 };
252 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
253 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
254 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
255 .clkdiv1 = 0x70000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /8 */
256 };
257 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
258 .freq = 0U, /* Oscillator frequency: 0Hz */
259 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
260 .workMode = kOSC_ModeExt, /* Use external clock */
261 .oscerConfig = {
262 .enableMode =
263 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
264 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
265 }};
266
267 /*******************************************************************************
268 * Code for BOARD_BootClockVLPR configuration
269 ******************************************************************************/
BOARD_BootClockVLPR(void)270 void BOARD_BootClockVLPR(void)
271 {
272 /* Set the system clock dividers in SIM to safe value. */
273 CLOCK_CONFIG_SetSimSafeDivs();
274 /* Set MCG to BLPI mode. */
275 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
276 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
277 /* Set the clock configuration in SIM module. */
278 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
279 /* Set VLPR power mode. */
280 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
281 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
282 SMC_SetPowerModeVlpr(SMC, false);
283 #else
284 SMC_SetPowerModeVlpr(SMC);
285 #endif
286 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
287 {
288 }
289 /* Set SystemCoreClock variable. */
290 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
291 }
292
293 /*******************************************************************************
294 ********************* Configuration BOARD_BootClockHSRUN **********************
295 ******************************************************************************/
296 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
297 !!Configuration
298 name: BOARD_BootClockHSRUN
299 outputs:
300 - {id: Bus_clock.outFreq, value: 114 MHz}
301 - {id: Core_clock.outFreq, value: 228 MHz}
302 - {id: ERCLK32K.outFreq, value: 1 kHz}
303 - {id: Flash_clock.outFreq, value: 22.8 MHz}
304 - {id: FlexBus_clock.outFreq, value: 57 MHz}
305 - {id: LPO_clock.outFreq, value: 1 kHz}
306 - {id: MCGFFCLK.outFreq, value: 1.5 MHz}
307 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
308 - {id: OSCERCLK.outFreq, value: 48 MHz}
309 - {id: OSCERCLK_UNDIV.outFreq, value: 48 MHz}
310 - {id: PLLFLLCLK.outFreq, value: 228 MHz}
311 - {id: System_clock.outFreq, value: 228 MHz}
312 settings:
313 - {id: MCGMode, value: PEE}
314 - {id: powerMode, value: HSRUN}
315 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
316 - {id: MCG.FRDIV.scale, value: '32'}
317 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
318 - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
319 - {id: MCG.PRDIV.scale, value: '4', locked: true}
320 - {id: MCG.VDIV.scale, value: '38', locked: true}
321 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
322 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
323 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
324 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
325 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
326 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
327 - {id: SIM.OUTDIV2.scale, value: '2', locked: true}
328 - {id: SIM.OUTDIV3.scale, value: '4', locked: true}
329 - {id: SIM.OUTDIV4.scale, value: '10', locked: true}
330 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
331 sources:
332 - {id: OSC.OSC.outFreq, value: 48 MHz, enabled: true}
333 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
334
335 /*******************************************************************************
336 * Variables for BOARD_BootClockHSRUN configuration
337 ******************************************************************************/
338 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
339 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
340 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
341 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
342 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
343 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
344 .drs = kMCG_DrsLow, /* Low frequency range */
345 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
346 .pll0Config =
347 {
348 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
349 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
350 .vdiv = 0x16U, /* VCO divider: multiplied by 38 */
351 },
352 };
353 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
354 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
355 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
356 .clkdiv1 = 0x1390000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /10 */
357 };
358 const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
359 .freq = 50000000U, /* Oscillator frequency: 48000000Hz */
360 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
361 .workMode = kOSC_ModeExt, /* Use external clock */
362 .oscerConfig = {
363 .enableMode =
364 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
365 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
366 }};
367
368 /*******************************************************************************
369 * Code for BOARD_BootClockHSRUN configuration
370 ******************************************************************************/
BOARD_BootClockHSRUN(void)371 void BOARD_BootClockHSRUN(void)
372 {
373 /* In HSRUN mode, the maximum allowable change in frequency of the system/bus/core/flash is
374 * restricted to x2, to follow this restriction, enter HSRUN mode should follow:
375 * 1.set CLKDIV1 to safe divider value.
376 * 2.set the PLL or FLL output target frequency for HSRUN mode.
377 * 3.switch to HSRUN mode.
378 * 4.switch to HSRUN mode target requency value.
379 */
380
381 /* Set the system clock dividers in SIM to safe value. */
382 CLOCK_SetOutDiv(SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV, SIM_CLKDIV1_RUN_MODE_MAX_FAST_PERIPHERAL_DIV,
383 SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV, SIM_CLKDIV1_RUN_MODE_MAX_BUS_FLASH_DIV);
384
385 /* Initializes OSC0 according to board configuration. */
386 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
387 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
388 /* Configure FLL external reference divider (FRDIV). */
389 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
390 /* Set MCG to PEE mode. */
391 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
392 /* Configure the Internal Reference clock (MCGIRCLK). */
393 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
394 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
395
396 /* Set HSRUN power mode */
397 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
398 SMC_SetPowerModeHsrun(SMC);
399 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
400 {
401 }
402
403 /* Set the clock configuration in SIM module. */
404 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
405 /* Set SystemCoreClock variable. */
406 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
407 }
408
