1 /*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include "clock_config.h"
8
9 /*******************************************************************************
10 ************************ BOARD_InitBootClocks function ************************
11 ******************************************************************************/
BOARD_InitBootClocks(void)12 void BOARD_InitBootClocks(void)
13 {
14 BOARD_BootClockRUN();
15 }
16
17 /*******************************************************************************
18 * Variables
19 ******************************************************************************/
20 /* clang-format off */
21 /*
22 * SYSTEM_PLL1
23 *
24 * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz
25 * Output = VCO / odiv = 1000MHz
26 */
27 const fracn_pll_init_t g_sysPllCfg = {
28 .rdiv = 1,
29 .mfi = 166,
30 .mfn = 2,
31 .mfd = 3,
32 .odiv = 4
33 };
34
35 /* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */
36 const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = {
37 .mfi = 4,
38 .mfn = 0,
39 .div2_en = true
40 };
41
42 /*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */
43 const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = {
44 .mfi = 5,
45 .mfn = 0,
46 .div2_en = true
47 };
48
49 /* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */
50 const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = {
51 .mfi = 6,
52 .mfn = 2,
53 .div2_en = true
54 };
55
56
57 /*
58 * AUDIOPLL1/AUDIOPLL1OUT
59 *
60 * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz
61 * Output = VCO / odiv = 393.216 MHz
62 */
63 const fracn_pll_init_t g_audioPllCfg = {
64 .rdiv = 1,
65 .mfi = 163,
66 .mfn = 84,
67 .mfd = 100,
68 .odiv = 10
69 };
70
71
72 /* clang-format on */
73
74 /*******************************************************************************
75 * Code
76 ******************************************************************************/
77
BOARD_InitClock(void)78 static void BOARD_InitClock(void)
79 {
80 g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U;
81 g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U;
82 g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U;
83 g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U;
84 g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U;
85 g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U;
86 g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U;
87 g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U;
88 g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U;
89 g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U;
90 }
91
BOARD_BootClockRUN(void)92 void BOARD_BootClockRUN(void)
93 {
94 BOARD_InitClock();
95
96 /* ROM has already initialized PLL */
97 CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg);
98 #if 0
99 CLOCK_PllInit(SYSPLL, &g_sysPllCfg);
100 CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg);
101 CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg);
102 CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg);
103 #endif
104 }
105
