1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MKV31F512xxx12
46 package_id: MKV31F512VLL12
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 board: FRDM-KV31F
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
51 /* clang-format on */
52
53 #include "fsl_smc.h"
54 #include "clock_config.h"
55
56 /*******************************************************************************
57 * Definitions
58 ******************************************************************************/
59 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
60 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
61 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
62 #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
63 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
64 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69 /* System clock frequency. */
70 extern uint32_t SystemCoreClock;
71
72 /*******************************************************************************
73 * Code
74 ******************************************************************************/
75 /*FUNCTION**********************************************************************
76 *
77 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
78 * Description : Configure FLL external reference divider (FRDIV).
79 * Param frdiv : The value to set FRDIV.
80 *
81 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)82 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
83 {
84 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
85 }
86
87 /*******************************************************************************
88 ************************ BOARD_InitBootClocks function ************************
89 ******************************************************************************/
BOARD_InitBootClocks(void)90 void BOARD_InitBootClocks(void)
91 {
92 BOARD_BootClockRUN();
93 }
94
95 /*******************************************************************************
96 ********************* Configuration BOARD_BootClockHSRUN **********************
97 ******************************************************************************/
98 /* clang-format off */
99 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
100 !!Configuration
101 name: BOARD_BootClockHSRUN
102 outputs:
103 - {id: Bus_clock.outFreq, value: 60 MHz}
104 - {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
105 - {id: ERCLK32K.outFreq, value: 1 kHz}
106 - {id: Flash_clock.outFreq, value: 24 MHz}
107 - {id: FlexBus_clock.outFreq, value: 30 MHz}
108 - {id: LPO_clock.outFreq, value: 1 kHz}
109 - {id: MCGFFCLK.outFreq, value: 250 kHz}
110 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
111 - {id: OSCERCLK.outFreq, value: 8 MHz}
112 - {id: OSCERCLK_UNDIV.outFreq, value: 8 MHz}
113 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
114 - {id: System_clock.outFreq, value: 120 MHz}
115 settings:
116 - {id: MCGMode, value: PEE}
117 - {id: powerMode, value: HSRUN}
118 - {id: MCG.FCRDIV.scale, value: '1'}
119 - {id: MCG.FRDIV.scale, value: '32'}
120 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
121 - {id: MCG.PLLS.sel, value: MCG.PLL}
122 - {id: MCG.PRDIV.scale, value: '2'}
123 - {id: MCG.VDIV.scale, value: '30'}
124 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
125 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
126 - {id: MCG_C2_RANGE0_CFG, value: High}
127 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
128 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
129 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
130 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
131 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
132 - {id: SIM.OUTDIV2.scale, value: '2'}
133 - {id: SIM.OUTDIV3.scale, value: '4'}
134 - {id: SIM.OUTDIV4.scale, value: '5'}
135 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
136 sources:
137 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
138 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
139 /* clang-format on */
140
141 /*******************************************************************************
142 * Variables for BOARD_BootClockHSRUN configuration
143 ******************************************************************************/
144 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
145 {
146 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
147 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
148 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
149 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
150 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
151 .drs = kMCG_DrsLow, /* Low frequency range */
152 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
153 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
154 .pll0Config =
155 {
156 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
157 .prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
158 .vdiv = 0x6U, /* VCO divider: multiplied by 30 */
159 },
160 };
161 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
162 {
163 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
164 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
165 .clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */
166 };
167 const osc_config_t oscConfig_BOARD_BootClockHSRUN =
168 {
169 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
170 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
171 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
172 .oscerConfig =
173 {
174 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
175 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
176 }
177 };
178
179 /*******************************************************************************
180 * Code for BOARD_BootClockHSRUN configuration
181 ******************************************************************************/
BOARD_BootClockHSRUN(void)182 void BOARD_BootClockHSRUN(void)
183 {
184 /* Set HSRUN power mode */
185 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
186 SMC_SetPowerModeHsrun(SMC);
187 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
188 {
189 }
190 /* Set the system clock dividers in SIM to safe value. */
191 CLOCK_SetSimSafeDivs();
192 /* Initializes OSC0 according to board configuration. */
193 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
194 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
195 /* Configure the Internal Reference clock (MCGIRCLK). */
196 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
197 mcgConfig_BOARD_BootClockHSRUN.ircs,
198 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
199 /* Configure FLL external reference divider (FRDIV). */
200 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
201 /* Set MCG to PEE mode. */
202 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
203 kMCG_PllClkSelPll0,
204 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
205 /* Set the clock configuration in SIM module. */
206 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
207 /* Set SystemCoreClock variable. */
208 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
209 }
210
211 /*******************************************************************************
212 ********************* Configuration BOARD_BootClockVLPR ***********************
213 ******************************************************************************/
214 /* clang-format off */
215 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
216 !!Configuration
217 name: BOARD_BootClockVLPR
218 outputs:
219 - {id: Bus_clock.outFreq, value: 4 MHz}
220 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
221 - {id: ERCLK32K.outFreq, value: 1 kHz}
222 - {id: Flash_clock.outFreq, value: 800 kHz}
223 - {id: FlexBus_clock.outFreq, value: 4 MHz}
224 - {id: LPO_clock.outFreq, value: 1 kHz}
225 - {id: MCGIRCLK.outFreq, value: 4 MHz}
226 - {id: System_clock.outFreq, value: 4 MHz}
227 settings:
228 - {id: MCGMode, value: BLPI}
229 - {id: powerMode, value: VLPR}
230 - {id: MCG.CLKS.sel, value: MCG.IRCS}
231 - {id: MCG.FCRDIV.scale, value: '1'}
232 - {id: MCG.FRDIV.scale, value: '32'}
233 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
234 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
235 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
236 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
237 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
238 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
239 - {id: SIM.OUTDIV3.scale, value: '1', locked: true}
240 - {id: SIM.OUTDIV4.scale, value: '5'}
241 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
242 sources:
243 - {id: OSC.OSC.outFreq, value: 8 MHz}
244 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
245 /* clang-format on */
246
247 /*******************************************************************************
248 * Variables for BOARD_BootClockVLPR configuration
249 ******************************************************************************/
250 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
251 {
252 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
253 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
254 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
255 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
256 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
257 .drs = kMCG_DrsLow, /* Low frequency range */
258 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
259 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
260 .pll0Config =
261 {
262 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
263 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
264 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
265 },
266 };
267 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
268 {
269 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
270 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
271 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
272 };
273 const osc_config_t oscConfig_BOARD_BootClockVLPR =
274 {
275 .freq = 0U, /* Oscillator frequency: 0Hz */
276 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
277 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
278 .oscerConfig =
279 {
280 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
281 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
282 }
283 };
284
285 /*******************************************************************************
286 * Code for BOARD_BootClockVLPR configuration
287 ******************************************************************************/
BOARD_BootClockVLPR(void)288 void BOARD_BootClockVLPR(void)
289 {
290 /* Set the system clock dividers in SIM to safe value. */
291 CLOCK_SetSimSafeDivs();
292 /* Set MCG to BLPI mode. */
293 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
294 mcgConfig_BOARD_BootClockVLPR.ircs,
295 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
296 /* Set the clock configuration in SIM module. */
297 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
298 /* Set VLPR power mode. */
299 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
300 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
301 SMC_SetPowerModeVlpr(SMC, false);
302 #else
303 SMC_SetPowerModeVlpr(SMC);
304 #endif
305 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
306 {
307 }
308 /* Set SystemCoreClock variable. */
309 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
310 }
311
312 /*******************************************************************************
313 ********************** Configuration BOARD_BootClockRUN ***********************
314 ******************************************************************************/
315 /* clang-format off */
316 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
317 !!Configuration
318 name: BOARD_BootClockRUN
319 called_from_default_init: true
320 outputs:
321 - {id: Bus_clock.outFreq, value: 40 MHz}
322 - {id: Core_clock.outFreq, value: 80 MHz}
323 - {id: ERCLK32K.outFreq, value: 1 kHz}
324 - {id: Flash_clock.outFreq, value: 20 MHz}
325 - {id: FlexBus_clock.outFreq, value: 80/3 MHz}
326 - {id: LPO_clock.outFreq, value: 1 kHz}
327 - {id: MCGFFCLK.outFreq, value: 250 kHz}
328 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
329 - {id: OSCERCLK.outFreq, value: 8 MHz}
330 - {id: OSCERCLK_UNDIV.outFreq, value: 8 MHz}
331 - {id: PLLFLLCLK.outFreq, value: 80 MHz}
332 - {id: System_clock.outFreq, value: 80 MHz}
333 settings:
334 - {id: MCGMode, value: PEE}
335 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
336 - {id: MCG.FRDIV.scale, value: '32'}
337 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
338 - {id: MCG.PLLS.sel, value: MCG.PLL}
339 - {id: MCG.PRDIV.scale, value: '4', locked: true}
340 - {id: MCG.VDIV.scale, value: '40', locked: true}
341 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
342 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
343 - {id: MCG_C2_RANGE0_CFG, value: High}
344 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
345 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
346 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
347 - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
348 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
349 - {id: SIM.OUTDIV2.scale, value: '2'}
350 - {id: SIM.OUTDIV3.scale, value: '3'}
351 - {id: SIM.OUTDIV4.scale, value: '4', locked: true}
352 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
353 sources:
354 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
355 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
356 /* clang-format on */
357
358 /*******************************************************************************
359 * Variables for BOARD_BootClockRUN configuration
360 ******************************************************************************/
361 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
362 {
363 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
364 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
365 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
366 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
367 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
368 .drs = kMCG_DrsLow, /* Low frequency range */
369 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
370 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
371 .pll0Config =
372 {
373 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
374 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
375 .vdiv = 0x10U, /* VCO divider: multiplied by 40 */
376 },
377 };
378 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
379 {
380 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
381 .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
382 .clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
383 };
384 const osc_config_t oscConfig_BOARD_BootClockRUN =
385 {
386 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
387 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
388 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
389 .oscerConfig =
390 {
391 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
392 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
393 }
394 };
395
396 /*******************************************************************************
397 * Code for BOARD_BootClockRUN configuration
398 ******************************************************************************/
BOARD_BootClockRUN(void)399 void BOARD_BootClockRUN(void)
400 {
401 /* Set the system clock dividers in SIM to safe value. */
402 CLOCK_SetSimSafeDivs();
403 /* Initializes OSC0 according to board configuration. */
404 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
405 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
406 /* Configure the Internal Reference clock (MCGIRCLK). */
407 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
408 mcgConfig_BOARD_BootClockRUN.ircs,
409 mcgConfig_BOARD_BootClockRUN.fcrdiv);
410 /* Configure FLL external reference divider (FRDIV). */
411 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
412 /* Set MCG to PEE mode. */
413 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
414 kMCG_PllClkSelPll0,
415 &mcgConfig_BOARD_BootClockRUN.pll0Config);
416 /* Set the clock configuration in SIM module. */
417 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
418 /* Set SystemCoreClock variable. */
419 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
420 }
421
422
