1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MK66FN2M0xxx18
46 package_id: MK66FN2M0VMD18
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 board: FRDM-K66F
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
51 /* clang-format on */
52
53 #include "fsl_smc.h"
54 #include "clock_config.h"
55
56 /*******************************************************************************
57 * Definitions
58 ******************************************************************************/
59 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
60 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
61 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
62 #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
63 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
64 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69 /* System clock frequency. */
70 extern uint32_t SystemCoreClock;
71
72 /*******************************************************************************
73 * Code
74 ******************************************************************************/
75 /*FUNCTION**********************************************************************
76 *
77 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
78 * Description : Configure FLL external reference divider (FRDIV).
79 * Param frdiv : The value to set FRDIV.
80 *
81 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)82 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
83 {
84 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
85 }
86
87 /*******************************************************************************
88 ************************ BOARD_InitBootClocks function ************************
89 ******************************************************************************/
BOARD_InitBootClocks(void)90 void BOARD_InitBootClocks(void)
91 {
92 BOARD_BootClockRUN();
93 }
94
95 /*******************************************************************************
96 ********************* Configuration BOARD_BootClockHSRUN **********************
97 ******************************************************************************/
98 /* clang-format off */
99 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
100 !!Configuration
101 name: BOARD_BootClockHSRUN
102 outputs:
103 - {id: Bus_clock.outFreq, value: 60 MHz}
104 - {id: Core_clock.outFreq, value: 180 MHz, locked: true, accuracy: '0.001'}
105 - {id: Flash_clock.outFreq, value: 180/7 MHz}
106 - {id: FlexBus_clock.outFreq, value: 60 MHz}
107 - {id: LPO_clock.outFreq, value: 1 kHz}
108 - {id: MCGFFCLK.outFreq, value: 375 kHz}
109 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
110 - {id: OSCERCLK.outFreq, value: 12 MHz}
111 - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
112 - {id: PLLFLLCLK.outFreq, value: 180 MHz}
113 - {id: System_clock.outFreq, value: 180 MHz}
114 settings:
115 - {id: MCGMode, value: PEE}
116 - {id: powerMode, value: HSRUN}
117 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
118 - {id: MCG.FRDIV.scale, value: '32'}
119 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
120 - {id: MCG.PLLS.sel, value: MCG.PLLCS}
121 - {id: MCG.VDIV.scale, value: '30'}
122 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
123 - {id: MCG_C1_IREFSTEN_CFG, value: Enabled}
124 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
125 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
126 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
127 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
128 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
129 - {id: RTC_CR_CLKO_CFG, value: Disabled}
130 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
131 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
132 - {id: SIM.OUTDIV2.scale, value: '3', locked: true}
133 - {id: SIM.OUTDIV3.scale, value: '3', locked: true}
134 - {id: SIM.OUTDIV4.scale, value: '7', locked: true}
135 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
136 - {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT}
137 - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
138 - {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLDIV}
139 - {id: SIM.TRACECLKSEL.sel, value: SIM.TRACEDIV}
140 - {id: SIM.TRACEDIV.scale, value: '2'}
141 - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
142 - {id: USBPHY.DIV.scale, value: '40'}
143 - {id: USBPHY.PFD_CLK_SEL.sel, value: USBPHY.PFD_CLK_DIV2}
144 - {id: USBPHY.PFD_FRAC_DIV.scale, value: '24', locked: true}
145 sources:
146 - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
147 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
148 /* clang-format on */
149
150 /*******************************************************************************
151 * Variables for BOARD_BootClockHSRUN configuration
152 ******************************************************************************/
153 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
154 {
155 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
156 .irclkEnableMode = kMCG_IrclkEnable | kMCG_IrclkEnableInStop,/* MCGIRCLK enabled as well as in STOP mode */
157 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
158 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
159 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
160 .drs = kMCG_DrsLow, /* Low frequency range */
161 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
162 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
163 .pll0Config =
164 {
165 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
166 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
167 .vdiv = 0xeU, /* VCO divider: multiplied by 30 */
168 },
169 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
170 };
171 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
172 {
173 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
174 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
175 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
176 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
177 .clkdiv1 = 0x2260000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /3, OUTDIV3: /3, OUTDIV4: /7 */
178 };
179 const osc_config_t oscConfig_BOARD_BootClockHSRUN =
180 {
181 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
182 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
183 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
184 .oscerConfig =
185 {
186 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
187 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
188 }
189 };
190
191 /*******************************************************************************
192 * Code for BOARD_BootClockHSRUN configuration
193 ******************************************************************************/
BOARD_BootClockHSRUN(void)194 void BOARD_BootClockHSRUN(void)
195 {
196 /* Set HSRUN power mode */
197 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
198 SMC_SetPowerModeHsrun(SMC);
199 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
200 {
201 }
202 /* Set the system clock dividers in SIM to safe value. */
203 CLOCK_SetSimSafeDivs();
204 /* Initializes OSC0 according to board configuration. */
205 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
206 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
207 /* Configure the Internal Reference clock (MCGIRCLK). */
208 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
209 mcgConfig_BOARD_BootClockHSRUN.ircs,
210 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
211 /* Configure FLL external reference divider (FRDIV). */
212 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
213 /* Set MCG to PEE mode. */
214 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
215 mcgConfig_BOARD_BootClockHSRUN.pllcs,
216 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
217 /* Set the clock configuration in SIM module. */
218 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
219 /* Set SystemCoreClock variable. */
220 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
221 }
222
223 /*******************************************************************************
224 ********************* Configuration BOARD_BootClockVLPR ***********************
225 ******************************************************************************/
226 /* clang-format off */
227 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
228 !!Configuration
229 name: BOARD_BootClockVLPR
230 outputs:
231 - {id: Bus_clock.outFreq, value: 4 MHz}
232 - {id: Core_clock.outFreq, value: 4 MHz}
233 - {id: Flash_clock.outFreq, value: 800 kHz}
234 - {id: FlexBus_clock.outFreq, value: 4 MHz}
235 - {id: LPO_clock.outFreq, value: 1 kHz}
236 - {id: MCGIRCLK.outFreq, value: 4 MHz}
237 - {id: System_clock.outFreq, value: 4 MHz}
238 settings:
239 - {id: MCGMode, value: BLPI}
240 - {id: powerMode, value: VLPR}
241 - {id: MCG.CLKS.sel, value: MCG.IRCS}
242 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
243 - {id: MCG.FRDIV.scale, value: '32'}
244 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
245 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
246 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
247 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
248 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
249 - {id: RTC_CR_CLKO_CFG, value: Disabled}
250 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
251 - {id: SIM.OUTDIV3.scale, value: '1'}
252 - {id: SIM.OUTDIV4.scale, value: '5'}
253 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
254 sources:
255 - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
256 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
257 /* clang-format on */
258
259 /*******************************************************************************
260 * Variables for BOARD_BootClockVLPR configuration
261 ******************************************************************************/
262 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
263 {
264 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
265 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
266 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
267 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
268 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
269 .drs = kMCG_DrsLow, /* Low frequency range */
270 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
271 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
272 .pll0Config =
273 {
274 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
275 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
276 .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
277 },
278 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
279 };
280 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
281 {
282 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
283 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
284 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
285 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
286 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
287 };
288 const osc_config_t oscConfig_BOARD_BootClockVLPR =
289 {
290 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
291 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
292 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
293 .oscerConfig =
294 {
295 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
296 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
297 }
298 };
299
300 /*******************************************************************************
301 * Code for BOARD_BootClockVLPR configuration
302 ******************************************************************************/
BOARD_BootClockVLPR(void)303 void BOARD_BootClockVLPR(void)
304 {
305 /* Set the system clock dividers in SIM to safe value. */
306 CLOCK_SetSimSafeDivs();
307 /* Initializes OSC0 according to board configuration. */
308 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockVLPR);
309 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockVLPR.freq);
310 /* Set MCG to BLPI mode. */
311 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
312 mcgConfig_BOARD_BootClockVLPR.ircs,
313 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
314 /* Select the MCG external reference clock. */
315 CLOCK_SetExternalRefClkConfig(mcgConfig_BOARD_BootClockVLPR.oscsel);
316 /* Set the clock configuration in SIM module. */
317 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
318 /* Set VLPR power mode. */
319 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
320 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
321 SMC_SetPowerModeVlpr(SMC, false);
322 #else
323 SMC_SetPowerModeVlpr(SMC);
324 #endif
325 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
326 {
327 }
328 /* Set SystemCoreClock variable. */
329 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
330 }
331
332 /*******************************************************************************
333 ********************** Configuration BOARD_BootClockRUN ***********************
334 ******************************************************************************/
335 /* clang-format off */
336 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
337 !!Configuration
338 name: BOARD_BootClockRUN
339 called_from_default_init: true
340 outputs:
341 - {id: Bus_clock.outFreq, value: 60 MHz}
342 - {id: Core_clock.outFreq, value: 120 MHz}
343 - {id: Flash_clock.outFreq, value: 24 MHz}
344 - {id: FlexBus_clock.outFreq, value: 60 MHz}
345 - {id: LPO_clock.outFreq, value: 1 kHz}
346 - {id: MCGFFCLK.outFreq, value: 375 kHz}
347 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
348 - {id: OSCERCLK.outFreq, value: 12 MHz}
349 - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
350 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
351 - {id: System_clock.outFreq, value: 120 MHz}
352 settings:
353 - {id: MCGMode, value: PEE}
354 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
355 - {id: MCG.FRDIV.scale, value: '32'}
356 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
357 - {id: MCG.PLLS.sel, value: MCG.PLLCS}
358 - {id: MCG.PRDIV.scale, value: '1', locked: true}
359 - {id: MCG.VDIV.scale, value: '20', locked: true}
360 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
361 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
362 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
363 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
364 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
365 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
366 - {id: RTC_CR_CLKO_CFG, value: Disabled}
367 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
368 - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
369 - {id: SIM.OUTDIV2.scale, value: '2'}
370 - {id: SIM.OUTDIV4.scale, value: '5'}
371 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
372 sources:
373 - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
374 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
375 /* clang-format on */
376
377 /*******************************************************************************
378 * Variables for BOARD_BootClockRUN configuration
379 ******************************************************************************/
380 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
381 {
382 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
383 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
384 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
385 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
386 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
387 .drs = kMCG_DrsLow, /* Low frequency range */
388 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
389 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
390 .pll0Config =
391 {
392 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
393 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
394 .vdiv = 0x4U, /* VCO divider: multiplied by 20 */
395 },
396 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
397 };
398 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
399 {
400 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
401 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
402 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
403 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
404 .clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
405 };
406 const osc_config_t oscConfig_BOARD_BootClockRUN =
407 {
408 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
409 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
410 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
411 .oscerConfig =
412 {
413 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
414 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
415 }
416 };
417
418 /*******************************************************************************
419 * Code for BOARD_BootClockRUN configuration
420 ******************************************************************************/
BOARD_BootClockRUN(void)421 void BOARD_BootClockRUN(void)
422 {
423 /* Set the system clock dividers in SIM to safe value. */
424 CLOCK_SetSimSafeDivs();
425 /* Initializes OSC0 according to board configuration. */
426 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
427 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
428 /* Configure the Internal Reference clock (MCGIRCLK). */
429 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
430 mcgConfig_BOARD_BootClockRUN.ircs,
431 mcgConfig_BOARD_BootClockRUN.fcrdiv);
432 /* Configure FLL external reference divider (FRDIV). */
433 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
434 /* Set MCG to PEE mode. */
435 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
436 mcgConfig_BOARD_BootClockRUN.pllcs,
437 &mcgConfig_BOARD_BootClockRUN.pll0Config);
438 /* Set the clock configuration in SIM module. */
439 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
440 /* Set SystemCoreClock variable. */
441 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
442 }
443
444
