1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MK64FN1M0xxx12
46 package_id: MK64FN1M0VLL12
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 board: FRDM-K64F
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
51 /* clang-format on */
52
53 #include "fsl_smc.h"
54 #include "clock_config.h"
55
56 /*******************************************************************************
57 * Definitions
58 ******************************************************************************/
59 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
60 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
61 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
62 #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
63 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
64 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69 /* System clock frequency. */
70 extern uint32_t SystemCoreClock;
71
72 /*******************************************************************************
73 * Code
74 ******************************************************************************/
75 /*FUNCTION**********************************************************************
76 *
77 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
78 * Description : Configure FLL external reference divider (FRDIV).
79 * Param frdiv : The value to set FRDIV.
80 *
81 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)82 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
83 {
84 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
85 }
86
87 /*******************************************************************************
88 ************************ BOARD_InitBootClocks function ************************
89 ******************************************************************************/
BOARD_InitBootClocks(void)90 void BOARD_InitBootClocks(void)
91 {
92 BOARD_BootClockRUN();
93 }
94
95 /*******************************************************************************
96 ********************** Configuration BOARD_BootClockRUN ***********************
97 ******************************************************************************/
98 /* clang-format off */
99 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
100 !!Configuration
101 name: BOARD_BootClockRUN
102 called_from_default_init: true
103 outputs:
104 - {id: Bus_clock.outFreq, value: 60 MHz}
105 - {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
106 - {id: Flash_clock.outFreq, value: 24 MHz}
107 - {id: FlexBus_clock.outFreq, value: 40 MHz}
108 - {id: LPO_clock.outFreq, value: 1 kHz}
109 - {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
110 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
111 - {id: OSCERCLK.outFreq, value: 50 MHz}
112 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
113 - {id: System_clock.outFreq, value: 120 MHz}
114 settings:
115 - {id: MCGMode, value: PEE}
116 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
117 - {id: MCG.FRDIV.scale, value: '32'}
118 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
119 - {id: MCG.PLLS.sel, value: MCG.PLL}
120 - {id: MCG.PRDIV.scale, value: '20', locked: true}
121 - {id: MCG.VDIV.scale, value: '48', locked: true}
122 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
123 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
124 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
125 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
126 - {id: RTCCLKOUTConfig, value: 'yes'}
127 - {id: RTC_CR_OSCE_CFG, value: Enabled}
128 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
129 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
130 - {id: SIM.OUTDIV2.scale, value: '2'}
131 - {id: SIM.OUTDIV3.scale, value: '3'}
132 - {id: SIM.OUTDIV4.scale, value: '5'}
133 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
134 - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
135 - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
136 - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
137 - {id: SIM.USBDIV.scale, value: '5'}
138 - {id: SIM.USBFRAC.scale, value: '2'}
139 - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
140 sources:
141 - {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
142 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
143 /* clang-format on */
144
145 /*******************************************************************************
146 * Variables for BOARD_BootClockRUN configuration
147 ******************************************************************************/
148 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
149 {
150 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
151 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
152 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
153 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
154 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
155 .drs = kMCG_DrsLow, /* Low frequency range */
156 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
157 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
158 .pll0Config =
159 {
160 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
161 .prdiv = 0x13U, /* PLL Reference divider: divided by 20 */
162 .vdiv = 0x18U, /* VCO divider: multiplied by 48 */
163 },
164 };
165 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
166 {
167 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
168 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
169 .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
170 };
171 const osc_config_t oscConfig_BOARD_BootClockRUN =
172 {
173 .freq = 50000000U, /* Oscillator frequency: 50000000Hz */
174 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
175 .workMode = kOSC_ModeExt, /* Use external clock */
176 .oscerConfig =
177 {
178 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
179 }
180 };
181
182 /*******************************************************************************
183 * Code for BOARD_BootClockRUN configuration
184 ******************************************************************************/
BOARD_BootClockRUN(void)185 void BOARD_BootClockRUN(void)
186 {
187 /* Set the system clock dividers in SIM to safe value. */
188 CLOCK_SetSimSafeDivs();
189 /* Initializes OSC0 according to board configuration. */
190 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
191 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
192 /* Configure the Internal Reference clock (MCGIRCLK). */
193 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
194 mcgConfig_BOARD_BootClockRUN.ircs,
195 mcgConfig_BOARD_BootClockRUN.fcrdiv);
196 /* Configure FLL external reference divider (FRDIV). */
197 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
198 /* Set MCG to PEE mode. */
199 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
200 kMCG_PllClkSelPll0,
201 &mcgConfig_BOARD_BootClockRUN.pll0Config);
202 /* Set the clock configuration in SIM module. */
203 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
204 /* Set SystemCoreClock variable. */
205 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
206 }
207
208 /*******************************************************************************
209 ********************* Configuration BOARD_BootClockVLPR ***********************
210 ******************************************************************************/
211 /* clang-format off */
212 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
213 !!Configuration
214 name: BOARD_BootClockVLPR
215 outputs:
216 - {id: Bus_clock.outFreq, value: 4 MHz}
217 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
218 - {id: Flash_clock.outFreq, value: 800 kHz}
219 - {id: FlexBus_clock.outFreq, value: 4 MHz}
220 - {id: LPO_clock.outFreq, value: 1 kHz}
221 - {id: MCGIRCLK.outFreq, value: 4 MHz}
222 - {id: System_clock.outFreq, value: 4 MHz}
223 settings:
224 - {id: MCGMode, value: BLPI}
225 - {id: powerMode, value: VLPR}
226 - {id: MCG.CLKS.sel, value: MCG.IRCS}
227 - {id: MCG.FCRDIV.scale, value: '1'}
228 - {id: MCG.FRDIV.scale, value: '32'}
229 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
230 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
231 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
232 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
233 - {id: RTC_CR_OSCE_CFG, value: Enabled}
234 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
235 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
236 - {id: SIM.OUTDIV3.scale, value: '1'}
237 - {id: SIM.OUTDIV4.scale, value: '5'}
238 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
239 - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
240 sources:
241 - {id: OSC.OSC.outFreq, value: 50 MHz}
242 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
243 /* clang-format on */
244
245 /*******************************************************************************
246 * Variables for BOARD_BootClockVLPR configuration
247 ******************************************************************************/
248 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
249 {
250 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
251 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
252 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
253 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
254 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
255 .drs = kMCG_DrsLow, /* Low frequency range */
256 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
257 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
258 .pll0Config =
259 {
260 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
261 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
262 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
263 },
264 };
265 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
266 {
267 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
268 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
269 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
270 };
271 const osc_config_t oscConfig_BOARD_BootClockVLPR =
272 {
273 .freq = 0U, /* Oscillator frequency: 0Hz */
274 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
275 .workMode = kOSC_ModeExt, /* Use external clock */
276 .oscerConfig =
277 {
278 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
279 }
280 };
281
282 /*******************************************************************************
283 * Code for BOARD_BootClockVLPR configuration
284 ******************************************************************************/
BOARD_BootClockVLPR(void)285 void BOARD_BootClockVLPR(void)
286 {
287 /* Set the system clock dividers in SIM to safe value. */
288 CLOCK_SetSimSafeDivs();
289 /* Set MCG to BLPI mode. */
290 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
291 mcgConfig_BOARD_BootClockVLPR.ircs,
292 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
293 /* Set the clock configuration in SIM module. */
294 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
295 /* Set VLPR power mode. */
296 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
297 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
298 SMC_SetPowerModeVlpr(SMC, false);
299 #else
300 SMC_SetPowerModeVlpr(SMC);
301 #endif
302 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
303 {
304 }
305 /* Set SystemCoreClock variable. */
306 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
307 }
308
309
