1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40 /* clang-format off */
41 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42 !!GlobalInfo
43 product: Clocks v7.0
44 processor: MK28FN2M0Axxx15
45 package_id: MK28FN2M0AVMI15
46 mcu_data: ksdk2_0
47 processor_version: 0.7.1
48 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
49 /* clang-format on */
50
51 #include "fsl_smc.h"
52 #include "clock_config.h"
53
54 /*******************************************************************************
55 * Definitions
56 ******************************************************************************/
57 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
58 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
59 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
60 #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
61 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
62 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
63
64 /*******************************************************************************
65 * Variables
66 ******************************************************************************/
67 /* System clock frequency. */
68 extern uint32_t SystemCoreClock;
69
70 /*******************************************************************************
71 * Code
72 ******************************************************************************/
73 /*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
76 * Description : Configure FLL external reference divider (FRDIV).
77 * Param frdiv : The value to set FRDIV.
78 *
79 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)80 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
81 {
82 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
83 }
84
85 /*******************************************************************************
86 ************************ BOARD_InitBootClocks function ************************
87 ******************************************************************************/
BOARD_InitBootClocks(void)88 void BOARD_InitBootClocks(void)
89 {
90 BOARD_BootClockRUN();
91 }
92
93 /*******************************************************************************
94 ********************** Configuration BOARD_BootClockRUN ***********************
95 ******************************************************************************/
96 /* clang-format off */
97 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
98 !!Configuration
99 name: BOARD_BootClockRUN
100 called_from_default_init: true
101 outputs:
102 - {id: Bus_clock.outFreq, value: 60 MHz}
103 - {id: Core_clock.outFreq, value: 120 MHz}
104 - {id: Flash_clock.outFreq, value: 24 MHz}
105 - {id: FlexBus_clock.outFreq, value: 60 MHz}
106 - {id: LPO_clock.outFreq, value: 1 kHz}
107 - {id: MCGFFCLK.outFreq, value: 375 kHz}
108 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
109 - {id: MCGPLLCLK.outFreq, value: 120 MHz}
110 - {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
111 - {id: OSCERCLK.outFreq, value: 12 MHz}
112 - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
113 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
114 - {id: System_clock.outFreq, value: 120 MHz}
115 settings:
116 - {id: MCGMode, value: PEE}
117 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
118 - {id: MCG.FRDIV.scale, value: '32'}
119 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
120 - {id: MCG.PLLS.sel, value: MCG.PLLCS}
121 - {id: MCG.PRDIV.scale, value: '1', locked: true}
122 - {id: MCG.VDIV.scale, value: '20', locked: true}
123 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
124 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
125 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
126 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
127 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
128 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
129 - {id: RTC_CR_OSCE_CFG, value: Enabled}
130 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
131 - {id: SIM.OUTDIV2.scale, value: '2'}
132 - {id: SIM.OUTDIV3.scale, value: '2'}
133 - {id: SIM.OUTDIV4.scale, value: '5'}
134 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
135 sources:
136 - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
137 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
138 /* clang-format on */
139
140 /*******************************************************************************
141 * Variables for BOARD_BootClockRUN configuration
142 ******************************************************************************/
143 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
144 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
145 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
146 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
147 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
148 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
149 .drs = kMCG_DrsLow, /* Low frequency range */
150 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
151 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
152 .pll0Config =
153 {
154 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
155 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
156 .vdiv = 0x4U, /* VCO divider: multiplied by 20 */
157 },
158 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
159 };
160 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
161 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
162 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
163 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
164 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
165 .clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
166 };
167 const osc_config_t oscConfig_BOARD_BootClockRUN = {
168 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
169 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
170 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
171 .oscerConfig = {
172 .enableMode =
173 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
174 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
175 }};
176
177 /*******************************************************************************
178 * Code for BOARD_BootClockRUN configuration
179 ******************************************************************************/
BOARD_BootClockRUN(void)180 void BOARD_BootClockRUN(void)
181 {
182 /* Set the system clock dividers in SIM to safe value. */
183 CLOCK_SetSimSafeDivs();
184 /* Initializes OSC0 according to board configuration. */
185 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
186 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
187 /* Configure the Internal Reference clock (MCGIRCLK). */
188 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
189 mcgConfig_BOARD_BootClockRUN.fcrdiv);
190 /* Configure FLL external reference divider (FRDIV). */
191 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
192 /* Set MCG to PEE mode. */
193 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, mcgConfig_BOARD_BootClockRUN.pllcs,
194 &mcgConfig_BOARD_BootClockRUN.pll0Config);
195 /* Set the clock configuration in SIM module. */
196 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
197 /* Set SystemCoreClock variable. */
198 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
199 }
200
201 /*******************************************************************************
202 ********************* Configuration BOARD_BootClockVLPR ***********************
203 ******************************************************************************/
204 /* clang-format off */
205 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
206 !!Configuration
207 name: BOARD_BootClockVLPR
208 outputs:
209 - {id: Bus_clock.outFreq, value: 4 MHz}
210 - {id: Core_clock.outFreq, value: 4 MHz}
211 - {id: Flash_clock.outFreq, value: 800 kHz}
212 - {id: FlexBus_clock.outFreq, value: 4 MHz}
213 - {id: LPO_clock.outFreq, value: 1 kHz}
214 - {id: MCGIRCLK.outFreq, value: 4 MHz}
215 - {id: System_clock.outFreq, value: 4 MHz}
216 settings:
217 - {id: MCGMode, value: BLPI}
218 - {id: powerMode, value: VLPR}
219 - {id: MCG.CLKS.sel, value: MCG.IRCS}
220 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
221 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
222 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
223 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
224 - {id: SIM.OUTDIV2.scale, value: '1', locked: true}
225 - {id: SIM.OUTDIV3.scale, value: '1', locked: true}
226 - {id: SIM.OUTDIV4.scale, value: '5', locked: true}
227 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
228 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
229 /* clang-format on */
230
231 /*******************************************************************************
232 * Variables for BOARD_BootClockVLPR configuration
233 ******************************************************************************/
234 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
235 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
236 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
237 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
238 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
239 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
240 .drs = kMCG_DrsLow, /* Low frequency range */
241 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
242 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
243 .pll0Config =
244 {
245 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
246 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
247 .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
248 },
249 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
250 };
251 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
252 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
253 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
254 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
255 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
256 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
257 };
258 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
259 .freq = 0U, /* Oscillator frequency: 0Hz */
260 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
261 .workMode = kOSC_ModeExt, /* Use external clock */
262 .oscerConfig = {
263 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
264 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
265 }};
266
267 /*******************************************************************************
268 * Code for BOARD_BootClockVLPR configuration
269 ******************************************************************************/
BOARD_BootClockVLPR(void)270 void BOARD_BootClockVLPR(void)
271 {
272 /* Set the system clock dividers in SIM to safe value. */
273 CLOCK_SetSimSafeDivs();
274 /* Set MCG to BLPI mode. */
275 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
276 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
277 /* Set the clock configuration in SIM module. */
278 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
279 /* Set VLPR power mode. */
280 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
281 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
282 SMC_SetPowerModeVlpr(SMC, false);
283 #else
284 SMC_SetPowerModeVlpr(SMC);
285 #endif
286 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
287 {
288 }
289 /* Set SystemCoreClock variable. */
290 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
291 }
292
293 /*******************************************************************************
294 ********************* Configuration BOARD_BootClockHSRUN **********************
295 ******************************************************************************/
296 /* clang-format off */
297 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
298 !!Configuration
299 name: BOARD_BootClockHSRUN
300 outputs:
301 - {id: Bus_clock.outFreq, value: 75 MHz}
302 - {id: Core_clock.outFreq, value: 150 MHz}
303 - {id: Flash_clock.outFreq, value: 25 MHz}
304 - {id: FlexBus_clock.outFreq, value: 75 MHz}
305 - {id: LPO_clock.outFreq, value: 1 kHz}
306 - {id: MCGFFCLK.outFreq, value: 375 kHz}
307 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
308 - {id: MCGPLLCLK.outFreq, value: 150 MHz}
309 - {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
310 - {id: OSCERCLK.outFreq, value: 12 MHz}
311 - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
312 - {id: PLLFLLCLK.outFreq, value: 150 MHz}
313 - {id: System_clock.outFreq, value: 150 MHz}
314 settings:
315 - {id: MCGMode, value: PEE}
316 - {id: powerMode, value: HSRUN}
317 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
318 - {id: MCG.FRDIV.scale, value: '32'}
319 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
320 - {id: MCG.PLLS.sel, value: MCG.PLLCS}
321 - {id: MCG.PRDIV.scale, value: '1', locked: true}
322 - {id: MCG.VDIV.scale, value: '25', locked: true}
323 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
324 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
325 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
326 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
327 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
328 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
329 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
330 - {id: SIM.OUTDIV2.scale, value: '2'}
331 - {id: SIM.OUTDIV3.scale, value: '2', locked: true}
332 - {id: SIM.OUTDIV4.scale, value: '6'}
333 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
334 sources:
335 - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
336 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
337 /* clang-format on */
338
339 /*******************************************************************************
340 * Variables for BOARD_BootClockHSRUN configuration
341 ******************************************************************************/
342 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
343 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
344 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
345 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
346 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
347 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
348 .drs = kMCG_DrsLow, /* Low frequency range */
349 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
350 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
351 .pll0Config =
352 {
353 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
354 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
355 .vdiv = 0x9U, /* VCO divider: multiplied by 25 */
356 },
357 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
358 };
359 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
360 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
361 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
362 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
363 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
364 .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
365 };
366 const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
367 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
368 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
369 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
370 .oscerConfig = {
371 .enableMode =
372 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
373 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
374 }};
375
376 /*******************************************************************************
377 * Code for BOARD_BootClockHSRUN configuration
378 ******************************************************************************/
BOARD_BootClockHSRUN(void)379 void BOARD_BootClockHSRUN(void)
380 {
381 /* Set HSRUN power mode */
382 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
383 SMC_SetPowerModeHsrun(SMC);
384 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
385 {
386 }
387 /* Set the system clock dividers in SIM to safe value. */
388 CLOCK_SetSimSafeDivs();
389 /* Initializes OSC0 according to board configuration. */
390 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
391 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
392 /* Configure the Internal Reference clock (MCGIRCLK). */
393 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
394 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
395 /* Configure FLL external reference divider (FRDIV). */
396 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
397 /* Set MCG to PEE mode. */
398 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, mcgConfig_BOARD_BootClockHSRUN.pllcs,
399 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
400 /* Set the clock configuration in SIM module. */
401 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
402 /* Set SystemCoreClock variable. */
403 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
404 }
405
