1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 ,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
17 * and flash clock are in allowed range during clock mode switch.
18 *
19 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
20 *
21 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
22 * internal reference clock(MCGIRCLK). Follow the steps to setup:
23 *
24 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
25 *
26 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
27 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
28 * explicitly to setup MCGIRCLK.
29 *
30 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
31 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
32 * if the target mode is not FLL mode, the FLL is disabled.
33 *
34 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
35 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
36 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
37 *
38 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
39 */
40
41 /* clang-format off */
42 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43 !!GlobalInfo
44 product: Clocks v7.0
45 processor: MK22FN512xxx12
46 package_id: MK22FN512VLH12
47 mcu_data: ksdk2_0
48 processor_version: 9.0.0
49 board: FRDM-K22F
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
51 /* clang-format on */
52
53 #include "fsl_smc.h"
54 #include "clock_config.h"
55
56 /*******************************************************************************
57 * Definitions
58 ******************************************************************************/
59 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
60 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
61 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
62 #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
63 #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
64 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69 /* System clock frequency. */
70 extern uint32_t SystemCoreClock;
71
72 /*******************************************************************************
73 * Code
74 ******************************************************************************/
75 /*FUNCTION**********************************************************************
76 *
77 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
78 * Description : Configure FLL external reference divider (FRDIV).
79 * Param frdiv : The value to set FRDIV.
80 *
81 *END**************************************************************************/
CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)82 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
83 {
84 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
85 }
86
87 /*******************************************************************************
88 ************************ BOARD_InitBootClocks function ************************
89 ******************************************************************************/
BOARD_InitBootClocks(void)90 void BOARD_InitBootClocks(void)
91 {
92 BOARD_BootClockRUN();
93 }
94
95 /*******************************************************************************
96 ********************** Configuration BOARD_BootClockRUN ***********************
97 ******************************************************************************/
98 /* clang-format off */
99 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
100 !!Configuration
101 name: BOARD_BootClockRUN
102 called_from_default_init: true
103 outputs:
104 - {id: Bus_clock.outFreq, value: 40 MHz}
105 - {id: Core_clock.outFreq, value: 80 MHz}
106 - {id: Flash_clock.outFreq, value: 20 MHz}
107 - {id: FlexBus_clock.outFreq, value: 80/3 MHz}
108 - {id: LPO_clock.outFreq, value: 1 kHz}
109 - {id: MCGFFCLK.outFreq, value: 250 kHz}
110 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
111 - {id: OSCERCLK.outFreq, value: 8 MHz}
112 - {id: OSCERCLK_UNDIV.outFreq, value: 8 MHz}
113 - {id: PLLFLLCLK.outFreq, value: 80 MHz}
114 - {id: System_clock.outFreq, value: 80 MHz}
115 settings:
116 - {id: MCGMode, value: PEE}
117 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
118 - {id: MCG.FRDIV.scale, value: '32'}
119 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
120 - {id: MCG.PLLS.sel, value: MCG.PLL}
121 - {id: MCG.PRDIV.scale, value: '4', locked: true}
122 - {id: MCG.VDIV.scale, value: '40', locked: true}
123 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
124 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
125 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
126 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
127 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
128 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
129 - {id: RTC_CR_OSCE_CFG, value: Enabled}
130 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC12PF}
131 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
132 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
133 - {id: SIM.OUTDIV2.scale, value: '2'}
134 - {id: SIM.OUTDIV3.scale, value: '3'}
135 - {id: SIM.OUTDIV4.scale, value: '4', locked: true}
136 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
137 sources:
138 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
139 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
140 /* clang-format on */
141
142 /*******************************************************************************
143 * Variables for BOARD_BootClockRUN configuration
144 ******************************************************************************/
145 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
146 {
147 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
148 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
149 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
150 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
151 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
152 .drs = kMCG_DrsLow, /* Low frequency range */
153 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
154 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
155 .pll0Config =
156 {
157 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
158 .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
159 .vdiv = 0x10U, /* VCO divider: multiplied by 40 */
160 },
161 };
162 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
163 {
164 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
165 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
166 .clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
167 };
168 const osc_config_t oscConfig_BOARD_BootClockRUN =
169 {
170 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
171 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
172 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
173 .oscerConfig =
174 {
175 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
176 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
177 }
178 };
179
180 /*******************************************************************************
181 * Code for BOARD_BootClockRUN configuration
182 ******************************************************************************/
BOARD_BootClockRUN(void)183 void BOARD_BootClockRUN(void)
184 {
185 /* Set the system clock dividers in SIM to safe value. */
186 CLOCK_SetSimSafeDivs();
187 /* Initializes OSC0 according to board configuration. */
188 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
189 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
190 /* Configure the Internal Reference clock (MCGIRCLK). */
191 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
192 mcgConfig_BOARD_BootClockRUN.ircs,
193 mcgConfig_BOARD_BootClockRUN.fcrdiv);
194 /* Configure FLL external reference divider (FRDIV). */
195 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
196 /* Set MCG to PEE mode. */
197 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
198 kMCG_PllClkSelPll0,
199 &mcgConfig_BOARD_BootClockRUN.pll0Config);
200 /* Set the clock configuration in SIM module. */
201 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
202 /* Set SystemCoreClock variable. */
203 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
204 }
205
206 /*******************************************************************************
207 ********************* Configuration BOARD_BootClockVLPR ***********************
208 ******************************************************************************/
209 /* clang-format off */
210 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
211 !!Configuration
212 name: BOARD_BootClockVLPR
213 outputs:
214 - {id: Bus_clock.outFreq, value: 4 MHz}
215 - {id: Core_clock.outFreq, value: 4 MHz}
216 - {id: Flash_clock.outFreq, value: 800 kHz}
217 - {id: FlexBus_clock.outFreq, value: 4 MHz}
218 - {id: LPO_clock.outFreq, value: 1 kHz}
219 - {id: MCGIRCLK.outFreq, value: 4 MHz}
220 - {id: System_clock.outFreq, value: 4 MHz}
221 settings:
222 - {id: MCGMode, value: BLPI}
223 - {id: powerMode, value: VLPR}
224 - {id: MCG.CLKS.sel, value: MCG.IRCS}
225 - {id: MCG.FCRDIV.scale, value: '1'}
226 - {id: MCG.FRDIV.scale, value: '32'}
227 - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
228 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
229 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
230 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
231 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
232 - {id: RTCCLKOUTConfig, value: 'yes'}
233 - {id: RTC_CR_OSCE_CFG, value: Enabled}
234 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC12PF}
235 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
236 - {id: SIM.OUTDIV3.scale, value: '1', locked: true}
237 - {id: SIM.OUTDIV4.scale, value: '5'}
238 - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
239 sources:
240 - {id: OSC.OSC.outFreq, value: 8 MHz}
241 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
242 /* clang-format on */
243
244 /*******************************************************************************
245 * Variables for BOARD_BootClockVLPR configuration
246 ******************************************************************************/
247 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
248 {
249 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
250 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
251 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
252 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
253 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
254 .drs = kMCG_DrsLow, /* Low frequency range */
255 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
256 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
257 .pll0Config =
258 {
259 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
260 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
261 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
262 },
263 };
264 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
265 {
266 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
267 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
268 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
269 };
270 const osc_config_t oscConfig_BOARD_BootClockVLPR =
271 {
272 .freq = 0U, /* Oscillator frequency: 0Hz */
273 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
274 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
275 .oscerConfig =
276 {
277 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
278 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
279 }
280 };
281
282 /*******************************************************************************
283 * Code for BOARD_BootClockVLPR configuration
284 ******************************************************************************/
BOARD_BootClockVLPR(void)285 void BOARD_BootClockVLPR(void)
286 {
287 /* Set the system clock dividers in SIM to safe value. */
288 CLOCK_SetSimSafeDivs();
289 /* Set MCG to BLPI mode. */
290 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
291 mcgConfig_BOARD_BootClockVLPR.ircs,
292 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
293 /* Set the clock configuration in SIM module. */
294 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
295 /* Set VLPR power mode. */
296 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
297 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
298 SMC_SetPowerModeVlpr(SMC, false);
299 #else
300 SMC_SetPowerModeVlpr(SMC);
301 #endif
302 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
303 {
304 }
305 /* Set SystemCoreClock variable. */
306 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
307 }
308
309 /*******************************************************************************
310 ********************* Configuration BOARD_BootClockHSRUN **********************
311 ******************************************************************************/
312 /* clang-format off */
313 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
314 !!Configuration
315 name: BOARD_BootClockHSRUN
316 outputs:
317 - {id: Bus_clock.outFreq, value: 60 MHz}
318 - {id: Core_clock.outFreq, value: 120 MHz}
319 - {id: Flash_clock.outFreq, value: 24 MHz}
320 - {id: FlexBus_clock.outFreq, value: 30 MHz}
321 - {id: LPO_clock.outFreq, value: 1 kHz}
322 - {id: MCGFFCLK.outFreq, value: 250 kHz}
323 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
324 - {id: OSCERCLK.outFreq, value: 8 MHz}
325 - {id: OSCERCLK_UNDIV.outFreq, value: 8 MHz}
326 - {id: PLLFLLCLK.outFreq, value: 120 MHz}
327 - {id: System_clock.outFreq, value: 120 MHz}
328 settings:
329 - {id: MCGMode, value: PEE}
330 - {id: powerMode, value: HSRUN}
331 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
332 - {id: MCG.FRDIV.scale, value: '32'}
333 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
334 - {id: MCG.PLLS.sel, value: MCG.PLL}
335 - {id: MCG.PRDIV.scale, value: '2', locked: true}
336 - {id: MCG.VDIV.scale, value: '30', locked: true}
337 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
338 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
339 - {id: MCG_C2_RANGE0_CFG, value: Very_high}
340 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
341 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
342 - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
343 - {id: RTC_CR_OSCE_CFG, value: Enabled}
344 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC12PF}
345 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
346 - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
347 - {id: SIM.OUTDIV2.scale, value: '2'}
348 - {id: SIM.OUTDIV3.scale, value: '4'}
349 - {id: SIM.OUTDIV4.scale, value: '5'}
350 - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
351 - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
352 - {id: SIM.USBDIV.scale, value: '5'}
353 - {id: SIM.USBFRAC.scale, value: '2'}
354 - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
355 sources:
356 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
357 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
358 /* clang-format on */
359
360 /*******************************************************************************
361 * Variables for BOARD_BootClockHSRUN configuration
362 ******************************************************************************/
363 const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
364 {
365 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
366 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
367 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
368 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
369 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
370 .drs = kMCG_DrsLow, /* Low frequency range */
371 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
372 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
373 .pll0Config =
374 {
375 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
376 .prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
377 .vdiv = 0x6U, /* VCO divider: multiplied by 30 */
378 },
379 };
380 const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
381 {
382 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
383 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
384 .clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */
385 };
386 const osc_config_t oscConfig_BOARD_BootClockHSRUN =
387 {
388 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
389 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
390 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
391 .oscerConfig =
392 {
393 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
394 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
395 }
396 };
397
398 /*******************************************************************************
399 * Code for BOARD_BootClockHSRUN configuration
400 ******************************************************************************/
BOARD_BootClockHSRUN(void)401 void BOARD_BootClockHSRUN(void)
402 {
403 /* Set HSRUN power mode */
404 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
405 SMC_SetPowerModeHsrun(SMC);
406 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
407 {
408 }
409 /* Set the system clock dividers in SIM to safe value. */
410 CLOCK_SetSimSafeDivs();
411 /* Initializes OSC0 according to board configuration. */
412 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
413 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
414 /* Configure the Internal Reference clock (MCGIRCLK). */
415 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
416 mcgConfig_BOARD_BootClockHSRUN.ircs,
417 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
418 /* Configure FLL external reference divider (FRDIV). */
419 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
420 /* Set MCG to PEE mode. */
421 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
422 kMCG_PllClkSelPll0,
423 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
424 /* Set the clock configuration in SIM module. */
425 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
426 /* Set SystemCoreClock variable. */
427 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
428 }
429
430
