1 /*
2  * Copyright 2022-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _CLOCK_CONFIG_H_
8 #define _CLOCK_CONFIG_H_
9 
10 #include "fsl_common.h"
11 
12 /*******************************************************************************
13  * Definitions
14  ******************************************************************************/
15 
16 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17 
18 #define BOARD_XTAL32K_CLK_HZ 32768U  /*!< Board xtal32k frequency in Hz */
19 
20 /*******************************************************************************
21  ************************ BOARD_InitBootClocks function ************************
22  ******************************************************************************/
23 
24 #if defined(__cplusplus)
25 extern "C" {
26 #endif /* __cplusplus*/
27 
28 /*!
29  * @brief This function executes default configuration of clocks.
30  *
31  */
32 void BOARD_InitBootClocks(void);
33 
34 #if defined(__cplusplus)
35 }
36 #endif /* __cplusplus*/
37 
38 /*******************************************************************************
39  ********************** Configuration BOARD_BootClockRUN ***********************
40  ******************************************************************************/
41 /*******************************************************************************
42  * Definitions for BOARD_BootClockRUN configuration
43  ******************************************************************************/
44 #if __CORTEX_M == 7
45     #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000UL /*!< CM7 Core clock frequency: 600000000Hz */
46 #else
47     #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */
48 #endif
49 
50 /* Clock outputs (values are in Hz): */
51 #define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT              24000000UL     /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
52 #define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT              24000000UL     /* Clock consumers of ADC1_CLK_ROOT output : LPADC1 */
53 #define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT              24000000UL     /* Clock consumers of ADC2_CLK_ROOT output : LPADC2 */
54 #define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK                600000000UL    /* Clock consumers of ARM_PLL_CLK output : N/A */
55 #define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT              24000000UL     /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
56 #define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT               600000000UL    /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
57 #define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT               198000000UL    /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
58 #define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT          120000000UL    /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
59 #define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT              24000000UL     /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
60 #define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT              24000000UL     /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */
61 #define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT              24000000UL     /* Clock consumers of CAN3_CLK_ROOT output : CAN3 */
62 #define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT         24000000UL     /* Clock consumers of CCM_CLKO1_CLK_ROOT output : N/A */
63 #define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT         24000000UL     /* Clock consumers of CCM_CLKO2_CLK_ROOT output : N/A */
64 #define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG3, RTWDOG4 */
65 #define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT              24000000UL     /* Clock consumers of CSI2_CLK_ROOT output : MIPI_CSI2RX */
66 #define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT          24000000UL     /* Clock consumers of CSI2_ESC_CLK_ROOT output : MIPI_CSI2RX */
67 #define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT           24000000UL     /* Clock consumers of CSI2_UI_CLK_ROOT output : MIPI_CSI2RX */
68 #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               24000000UL     /* Clock consumers of CSI_CLK_ROOT output : N/A */
69 #define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT             24000000UL     /* Clock consumers of CSSYS_CLK_ROOT output : ARM */
70 #define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT           132000000UL    /* Clock consumers of CSTRACE_CLK_ROOT output : ARM */
71 #define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT            24000000UL     /* Clock consumers of ELCDIF_CLK_ROOT output : LCDIF */
72 #define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT              24000000UL     /* Clock consumers of EMV1_CLK_ROOT output : EMVSIM1 */
73 #define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT              24000000UL     /* Clock consumers of EMV2_CLK_ROOT output : EMVSIM2 */
74 #define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT             24000000UL     /* Clock consumers of ENET1_CLK_ROOT output : N/A */
75 #define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT             24000000UL     /* Clock consumers of ENET2_CLK_ROOT output : N/A */
76 #define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK            0UL            /* Clock consumers of ENET_1G_REF_CLK output : ENET_1G */
77 #define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK             24000000UL     /* Clock consumers of ENET_1G_TX_CLK output : ENET_1G */
78 #define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT          24000000UL     /* Clock consumers of ENET_25M_CLK_ROOT output : N/A */
79 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL            /* Clock consumers of ENET_REF_CLK output : ENET */
80 #define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT       24000000UL     /* Clock consumers of ENET_TIMER1_CLK_ROOT output : ENET */
81 #define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT       24000000UL     /* Clock consumers of ENET_TIMER2_CLK_ROOT output : ENET_1G */
82 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL            /* Clock consumers of ENET_TX_CLK output : N/A */
83 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           24000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
84 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           24000000UL     /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
85 #define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT          24000000UL     /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
86 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          24000000UL     /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
87 #define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT             492000012UL    /* Clock consumers of GC355_CLK_ROOT output : N/A */
88 #define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT              24000000UL     /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
89 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : N/A */
90 #define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT              24000000UL     /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
91 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : N/A */
92 #define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT              24000000UL     /* Clock consumers of GPT3_CLK_ROOT output : GPT3 */
93 #define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT3_ipg_clk_highfreq output : N/A */
94 #define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT              24000000UL     /* Clock consumers of GPT4_CLK_ROOT output : GPT4 */
95 #define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT4_ipg_clk_highfreq output : N/A */
96 #define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT              24000000UL     /* Clock consumers of GPT5_CLK_ROOT output : GPT5 */
97 #define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT5_ipg_clk_highfreq output : N/A */
98 #define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT              24000000UL     /* Clock consumers of GPT6_CLK_ROOT output : GPT6 */
99 #define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ      24000000UL     /* Clock consumers of GPT6_ipg_clk_highfreq output : N/A */
100 #define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT           24000000UL     /* Clock consumers of LCDIFV2_CLK_ROOT output : LCDIFV2 */
101 #define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C1_CLK_ROOT output : LPI2C1 */
102 #define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C2_CLK_ROOT output : LPI2C2 */
103 #define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C3_CLK_ROOT output : LPI2C3 */
104 #define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C4_CLK_ROOT output : LPI2C4 */
105 #define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C5_CLK_ROOT output : LPI2C5 */
106 #define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT            24000000UL     /* Clock consumers of LPI2C6_CLK_ROOT output : LPI2C6 */
107 #define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI1_CLK_ROOT output : LPSPI1 */
108 #define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI2_CLK_ROOT output : LPSPI2 */
109 #define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI3_CLK_ROOT output : LPSPI3 */
110 #define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI4_CLK_ROOT output : LPSPI4 */
111 #define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI5_CLK_ROOT output : LPSPI5 */
112 #define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT            24000000UL     /* Clock consumers of LPSPI6_CLK_ROOT output : LPSPI6 */
113 #define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT          24000000UL     /* Clock consumers of LPUART10_CLK_ROOT output : LPUART10 */
114 #define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT          24000000UL     /* Clock consumers of LPUART11_CLK_ROOT output : LPUART11 */
115 #define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT          24000000UL     /* Clock consumers of LPUART12_CLK_ROOT output : LPUART12 */
116 #define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT           24000000UL     /* Clock consumers of LPUART1_CLK_ROOT output : LPUART1 */
117 #define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT           24000000UL     /* Clock consumers of LPUART2_CLK_ROOT output : LPUART2 */
118 #define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT           24000000UL     /* Clock consumers of LPUART3_CLK_ROOT output : LPUART3 */
119 #define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT           24000000UL     /* Clock consumers of LPUART4_CLK_ROOT output : LPUART4 */
120 #define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT           24000000UL     /* Clock consumers of LPUART5_CLK_ROOT output : LPUART5 */
121 #define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT           24000000UL     /* Clock consumers of LPUART6_CLK_ROOT output : LPUART6 */
122 #define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT           24000000UL     /* Clock consumers of LPUART7_CLK_ROOT output : LPUART7 */
123 #define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT           24000000UL     /* Clock consumers of LPUART8_CLK_ROOT output : LPUART8 */
124 #define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT           24000000UL     /* Clock consumers of LPUART9_CLK_ROOT output : LPUART9 */
125 #define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT                240000000UL    /* Clock consumers of M4_CLK_ROOT output : ARM, DMA1, DMAMUX1, SSARC_HP, SSARC_LP, XRDC2_D0, XRDC2_D1 */
126 #define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT        24000000UL     /* Clock consumers of M4_SYSTICK_CLK_ROOT output : N/A */
127 #define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT                600000000UL    /* Clock consumers of M7_CLK_ROOT output : ARM */
128 #define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT        100000UL       /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
129 #define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT               24000000UL     /* Clock consumers of MIC_CLK_ROOT output : ASRC, PDM, SPDIF */
130 #define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT   24000000UL     /* Clock consumers of MIPI_DSI_TX_CLK_ESC_ROOT output : N/A */
131 #define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT          24000000UL     /* Clock consumers of MIPI_ESC_CLK_ROOT output : DSI_HOST */
132 #define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT          24000000UL     /* Clock consumers of MIPI_REF_CLK_ROOT output : DSI_HOST */
133 #define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT               24000000UL     /* Clock consumers of MQS_CLK_ROOT output : ASRC */
134 #define BOARD_BOOTCLOCKRUN_MQS_MCLK                   24000000UL     /* Clock consumers of MQS_MCLK output : N/A */
135 #define BOARD_BOOTCLOCKRUN_OSC_24M                    24000000UL     /* Clock consumers of OSC_24M output : SPDIF, TMPSNS, USBPHY1, USBPHY2 */
136 #define BOARD_BOOTCLOCKRUN_OSC_32K                    32768UL        /* Clock consumers of OSC_32K output : GPIO13, RTWDOG3, RTWDOG4 */
137 #define BOARD_BOOTCLOCKRUN_OSC_RC_16M                 16000000UL     /* Clock consumers of OSC_RC_16M output : CCM, DCDC, EWM, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6, SSARC_LP */
138 #define BOARD_BOOTCLOCKRUN_OSC_RC_400M                400000000UL    /* Clock consumers of OSC_RC_400M output : N/A */
139 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M                 48000000UL     /* Clock consumers of OSC_RC_48M output : N/A */
140 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2            24000000UL     /* Clock consumers of OSC_RC_48M_DIV2 output : N/A */
141 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK              0UL            /* Clock consumers of PLL_AUDIO_CLK output : N/A */
142 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION    0UL            /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
143 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE         0UL            /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
144 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK              984000025UL    /* Clock consumers of PLL_VIDEO_CLK output : N/A */
145 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION    0UL            /* Clock consumers of PLL_VIDEO_SS_MODULATION output : N/A */
146 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE         0UL            /* Clock consumers of PLL_VIDEO_SS_RANGE output : N/A */
147 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              24000000UL     /* Clock consumers of SAI1_CLK_ROOT output : SPDIF */
148 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 24000000UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
149 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 0UL            /* Clock consumers of SAI1_MCLK2 output : SAI1 */
150 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 24000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
151 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              24000000UL     /* Clock consumers of SAI2_CLK_ROOT output : ASRC */
152 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 24000000UL     /* Clock consumers of SAI2_MCLK1 output : SAI2 */
153 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL            /* Clock consumers of SAI2_MCLK2 output : SAI2 */
154 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 24000000UL     /* Clock consumers of SAI2_MCLK3 output : SAI2 */
155 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              24000000UL     /* Clock consumers of SAI3_CLK_ROOT output : ASRC, SPDIF */
156 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 24000000UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
157 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
158 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 24000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
159 #define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT              24000000UL     /* Clock consumers of SAI4_CLK_ROOT output : ASRC, SPDIF */
160 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK1                 24000000UL     /* Clock consumers of SAI4_MCLK1 output : SAI4 */
161 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK2                 0UL            /* Clock consumers of SAI4_MCLK2 output : SAI4 */
162 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              198000000UL    /* Clock consumers of SEMC_CLK_ROOT output : SEMC, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
163 #define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT             24000000UL     /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
164 #define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT           0UL            /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
165 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK               0UL            /* Clock consumers of SYS_PLL1_CLK output : N/A */
166 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK          0UL            /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
167 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK          0UL            /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
168 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION     0UL            /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
169 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE          0UL            /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
170 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK               528000000UL    /* Clock consumers of SYS_PLL2_CLK output : N/A */
171 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK          352000000UL    /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
172 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK          594000000UL    /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
173 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK          396000000UL    /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
174 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK          396000000UL    /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
175 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION     0UL            /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
176 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE          0UL            /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
177 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK               480000000UL    /* Clock consumers of SYS_PLL3_CLK output : N/A */
178 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK          240000000UL    /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
179 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK          664615384UL    /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
180 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK          508235294UL    /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
181 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK          270000000UL    /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
182 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK          392727272UL    /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
183 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            24000000UL     /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
184 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            24000000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
185 
186 
187 /*******************************************************************************
188  * API for BOARD_BootClockRUN configuration
189  ******************************************************************************/
190 #if defined(__cplusplus)
191 extern "C" {
192 #endif /* __cplusplus*/
193 
194 /*!
195  * @brief This function executes configuration of clocks.
196  *
197  */
198 void BOARD_BootClockRUN(void);
199 
200 #if defined(__cplusplus)
201 }
202 #endif /* __cplusplus*/
203 
204 /*******************************************************************************
205  ******************* Configuration BOARD_BootClockRUN_500M *********************
206  ******************************************************************************/
207 /*******************************************************************************
208  * Definitions for BOARD_BootClockRUN_500M configuration
209  ******************************************************************************/
210 #if __CORTEX_M == 7
211     #define BOARD_BOOTCLOCKRUN_500M_CORE_CLOCK 498000000UL /*!< CM7 Core clock frequency: 498000000Hz */
212 #else
213     #define BOARD_BOOTCLOCKRUN_500M_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */
214 #endif
215 
216 /* Clock outputs (values are in Hz): */
217 #define BOARD_BOOTCLOCKRUN_500M_ACMP_CLK_ROOT         24000000UL     /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
218 #define BOARD_BOOTCLOCKRUN_500M_ADC1_CLK_ROOT         24000000UL     /* Clock consumers of ADC1_CLK_ROOT output : LPADC1 */
219 #define BOARD_BOOTCLOCKRUN_500M_ADC2_CLK_ROOT         24000000UL     /* Clock consumers of ADC2_CLK_ROOT output : LPADC2 */
220 #define BOARD_BOOTCLOCKRUN_500M_ARM_PLL_CLK           498000000UL    /* Clock consumers of ARM_PLL_CLK output : N/A */
221 #define BOARD_BOOTCLOCKRUN_500M_ASRC_CLK_ROOT         24000000UL     /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
222 #define BOARD_BOOTCLOCKRUN_500M_AXI_CLK_ROOT          498000000UL    /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
223 #define BOARD_BOOTCLOCKRUN_500M_BUS_CLK_ROOT          198000000UL    /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
224 #define BOARD_BOOTCLOCKRUN_500M_BUS_LPSR_CLK_ROOT     120000000UL    /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
225 #define BOARD_BOOTCLOCKRUN_500M_CAN1_CLK_ROOT         24000000UL     /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
226 #define BOARD_BOOTCLOCKRUN_500M_CAN2_CLK_ROOT         24000000UL     /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */
227 #define BOARD_BOOTCLOCKRUN_500M_CAN3_CLK_ROOT         24000000UL     /* Clock consumers of CAN3_CLK_ROOT output : CAN3 */
228 #define BOARD_BOOTCLOCKRUN_500M_CCM_CLKO1_CLK_ROOT    24000000UL     /* Clock consumers of CCM_CLKO1_CLK_ROOT output : N/A */
229 #define BOARD_BOOTCLOCKRUN_500M_CCM_CLKO2_CLK_ROOT    24000000UL     /* Clock consumers of CCM_CLKO2_CLK_ROOT output : N/A */
230 #define BOARD_BOOTCLOCKRUN_500M_CLK_1M                1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG3, RTWDOG4 */
231 #define BOARD_BOOTCLOCKRUN_500M_CSI2_CLK_ROOT         24000000UL     /* Clock consumers of CSI2_CLK_ROOT output : MIPI_CSI2RX */
232 #define BOARD_BOOTCLOCKRUN_500M_CSI2_ESC_CLK_ROOT     24000000UL     /* Clock consumers of CSI2_ESC_CLK_ROOT output : MIPI_CSI2RX */
233 #define BOARD_BOOTCLOCKRUN_500M_CSI2_UI_CLK_ROOT      24000000UL     /* Clock consumers of CSI2_UI_CLK_ROOT output : MIPI_CSI2RX */
234 #define BOARD_BOOTCLOCKRUN_500M_CSI_CLK_ROOT          24000000UL     /* Clock consumers of CSI_CLK_ROOT output : N/A */
235 #define BOARD_BOOTCLOCKRUN_500M_CSSYS_CLK_ROOT        24000000UL     /* Clock consumers of CSSYS_CLK_ROOT output : ARM */
236 #define BOARD_BOOTCLOCKRUN_500M_CSTRACE_CLK_ROOT      132000000UL    /* Clock consumers of CSTRACE_CLK_ROOT output : ARM */
237 #define BOARD_BOOTCLOCKRUN_500M_ELCDIF_CLK_ROOT       24000000UL     /* Clock consumers of ELCDIF_CLK_ROOT output : LCDIF */
238 #define BOARD_BOOTCLOCKRUN_500M_EMV1_CLK_ROOT         24000000UL     /* Clock consumers of EMV1_CLK_ROOT output : EMVSIM1 */
239 #define BOARD_BOOTCLOCKRUN_500M_EMV2_CLK_ROOT         24000000UL     /* Clock consumers of EMV2_CLK_ROOT output : EMVSIM2 */
240 #define BOARD_BOOTCLOCKRUN_500M_ENET1_CLK_ROOT        24000000UL     /* Clock consumers of ENET1_CLK_ROOT output : N/A */
241 #define BOARD_BOOTCLOCKRUN_500M_ENET2_CLK_ROOT        24000000UL     /* Clock consumers of ENET2_CLK_ROOT output : N/A */
242 #define BOARD_BOOTCLOCKRUN_500M_ENET_1G_REF_CLK       0UL            /* Clock consumers of ENET_1G_REF_CLK output : ENET_1G */
243 #define BOARD_BOOTCLOCKRUN_500M_ENET_1G_TX_CLK        24000000UL     /* Clock consumers of ENET_1G_TX_CLK output : ENET_1G */
244 #define BOARD_BOOTCLOCKRUN_500M_ENET_25M_CLK_ROOT     24000000UL     /* Clock consumers of ENET_25M_CLK_ROOT output : N/A */
245 #define BOARD_BOOTCLOCKRUN_500M_ENET_REF_CLK          0UL            /* Clock consumers of ENET_REF_CLK output : ENET */
246 #define BOARD_BOOTCLOCKRUN_500M_ENET_TIMER1_CLK_ROOT  24000000UL     /* Clock consumers of ENET_TIMER1_CLK_ROOT output : ENET */
247 #define BOARD_BOOTCLOCKRUN_500M_ENET_TIMER2_CLK_ROOT  24000000UL     /* Clock consumers of ENET_TIMER2_CLK_ROOT output : ENET_1G */
248 #define BOARD_BOOTCLOCKRUN_500M_ENET_TX_CLK           0UL            /* Clock consumers of ENET_TX_CLK output : N/A */
249 #define BOARD_BOOTCLOCKRUN_500M_FLEXIO1_CLK_ROOT      24000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
250 #define BOARD_BOOTCLOCKRUN_500M_FLEXIO2_CLK_ROOT      24000000UL     /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
251 #define BOARD_BOOTCLOCKRUN_500M_FLEXSPI1_CLK_ROOT     24000000UL     /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
252 #define BOARD_BOOTCLOCKRUN_500M_FLEXSPI2_CLK_ROOT     24000000UL     /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
253 #define BOARD_BOOTCLOCKRUN_500M_GC355_CLK_ROOT        492000012UL    /* Clock consumers of GC355_CLK_ROOT output : N/A */
254 #define BOARD_BOOTCLOCKRUN_500M_GPT1_CLK_ROOT         24000000UL     /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
255 #define BOARD_BOOTCLOCKRUN_500M_GPT1_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : N/A */
256 #define BOARD_BOOTCLOCKRUN_500M_GPT2_CLK_ROOT         24000000UL     /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
257 #define BOARD_BOOTCLOCKRUN_500M_GPT2_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : N/A */
258 #define BOARD_BOOTCLOCKRUN_500M_GPT3_CLK_ROOT         24000000UL     /* Clock consumers of GPT3_CLK_ROOT output : GPT3 */
259 #define BOARD_BOOTCLOCKRUN_500M_GPT3_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT3_ipg_clk_highfreq output : N/A */
260 #define BOARD_BOOTCLOCKRUN_500M_GPT4_CLK_ROOT         24000000UL     /* Clock consumers of GPT4_CLK_ROOT output : GPT4 */
261 #define BOARD_BOOTCLOCKRUN_500M_GPT4_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT4_ipg_clk_highfreq output : N/A */
262 #define BOARD_BOOTCLOCKRUN_500M_GPT5_CLK_ROOT         24000000UL     /* Clock consumers of GPT5_CLK_ROOT output : GPT5 */
263 #define BOARD_BOOTCLOCKRUN_500M_GPT5_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT5_ipg_clk_highfreq output : N/A */
264 #define BOARD_BOOTCLOCKRUN_500M_GPT6_CLK_ROOT         24000000UL     /* Clock consumers of GPT6_CLK_ROOT output : GPT6 */
265 #define BOARD_BOOTCLOCKRUN_500M_GPT6_IPG_CLK_HIGHFREQ 24000000UL     /* Clock consumers of GPT6_ipg_clk_highfreq output : N/A */
266 #define BOARD_BOOTCLOCKRUN_500M_LCDIFV2_CLK_ROOT      24000000UL     /* Clock consumers of LCDIFV2_CLK_ROOT output : LCDIFV2 */
267 #define BOARD_BOOTCLOCKRUN_500M_LPI2C1_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C1_CLK_ROOT output : LPI2C1 */
268 #define BOARD_BOOTCLOCKRUN_500M_LPI2C2_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C2_CLK_ROOT output : LPI2C2 */
269 #define BOARD_BOOTCLOCKRUN_500M_LPI2C3_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C3_CLK_ROOT output : LPI2C3 */
270 #define BOARD_BOOTCLOCKRUN_500M_LPI2C4_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C4_CLK_ROOT output : LPI2C4 */
271 #define BOARD_BOOTCLOCKRUN_500M_LPI2C5_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C5_CLK_ROOT output : LPI2C5 */
272 #define BOARD_BOOTCLOCKRUN_500M_LPI2C6_CLK_ROOT       24000000UL     /* Clock consumers of LPI2C6_CLK_ROOT output : LPI2C6 */
273 #define BOARD_BOOTCLOCKRUN_500M_LPSPI1_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI1_CLK_ROOT output : LPSPI1 */
274 #define BOARD_BOOTCLOCKRUN_500M_LPSPI2_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI2_CLK_ROOT output : LPSPI2 */
275 #define BOARD_BOOTCLOCKRUN_500M_LPSPI3_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI3_CLK_ROOT output : LPSPI3 */
276 #define BOARD_BOOTCLOCKRUN_500M_LPSPI4_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI4_CLK_ROOT output : LPSPI4 */
277 #define BOARD_BOOTCLOCKRUN_500M_LPSPI5_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI5_CLK_ROOT output : LPSPI5 */
278 #define BOARD_BOOTCLOCKRUN_500M_LPSPI6_CLK_ROOT       24000000UL     /* Clock consumers of LPSPI6_CLK_ROOT output : LPSPI6 */
279 #define BOARD_BOOTCLOCKRUN_500M_LPUART10_CLK_ROOT     24000000UL     /* Clock consumers of LPUART10_CLK_ROOT output : LPUART10 */
280 #define BOARD_BOOTCLOCKRUN_500M_LPUART11_CLK_ROOT     24000000UL     /* Clock consumers of LPUART11_CLK_ROOT output : LPUART11 */
281 #define BOARD_BOOTCLOCKRUN_500M_LPUART12_CLK_ROOT     24000000UL     /* Clock consumers of LPUART12_CLK_ROOT output : LPUART12 */
282 #define BOARD_BOOTCLOCKRUN_500M_LPUART1_CLK_ROOT      24000000UL     /* Clock consumers of LPUART1_CLK_ROOT output : LPUART1 */
283 #define BOARD_BOOTCLOCKRUN_500M_LPUART2_CLK_ROOT      24000000UL     /* Clock consumers of LPUART2_CLK_ROOT output : LPUART2 */
284 #define BOARD_BOOTCLOCKRUN_500M_LPUART3_CLK_ROOT      24000000UL     /* Clock consumers of LPUART3_CLK_ROOT output : LPUART3 */
285 #define BOARD_BOOTCLOCKRUN_500M_LPUART4_CLK_ROOT      24000000UL     /* Clock consumers of LPUART4_CLK_ROOT output : LPUART4 */
286 #define BOARD_BOOTCLOCKRUN_500M_LPUART5_CLK_ROOT      24000000UL     /* Clock consumers of LPUART5_CLK_ROOT output : LPUART5 */
287 #define BOARD_BOOTCLOCKRUN_500M_LPUART6_CLK_ROOT      24000000UL     /* Clock consumers of LPUART6_CLK_ROOT output : LPUART6 */
288 #define BOARD_BOOTCLOCKRUN_500M_LPUART7_CLK_ROOT      24000000UL     /* Clock consumers of LPUART7_CLK_ROOT output : LPUART7 */
289 #define BOARD_BOOTCLOCKRUN_500M_LPUART8_CLK_ROOT      24000000UL     /* Clock consumers of LPUART8_CLK_ROOT output : LPUART8 */
290 #define BOARD_BOOTCLOCKRUN_500M_LPUART9_CLK_ROOT      24000000UL     /* Clock consumers of LPUART9_CLK_ROOT output : LPUART9 */
291 #define BOARD_BOOTCLOCKRUN_500M_M4_CLK_ROOT           240000000UL    /* Clock consumers of M4_CLK_ROOT output : ARM, DMA1, DMAMUX1, SSARC_HP, SSARC_LP, XRDC2_D0, XRDC2_D1 */
292 #define BOARD_BOOTCLOCKRUN_500M_M4_SYSTICK_CLK_ROOT   24000000UL     /* Clock consumers of M4_SYSTICK_CLK_ROOT output : N/A */
293 #define BOARD_BOOTCLOCKRUN_500M_M7_CLK_ROOT           498000000UL    /* Clock consumers of M7_CLK_ROOT output : ARM */
294 #define BOARD_BOOTCLOCKRUN_500M_M7_SYSTICK_CLK_ROOT   100000UL       /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
295 #define BOARD_BOOTCLOCKRUN_500M_MIC_CLK_ROOT          24000000UL     /* Clock consumers of MIC_CLK_ROOT output : ASRC, PDM, SPDIF */
296 #define BOARD_BOOTCLOCKRUN_500M_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL  /* Clock consumers of MIPI_DSI_TX_CLK_ESC_ROOT output : N/A */
297 #define BOARD_BOOTCLOCKRUN_500M_MIPI_ESC_CLK_ROOT     24000000UL     /* Clock consumers of MIPI_ESC_CLK_ROOT output : DSI_HOST */
298 #define BOARD_BOOTCLOCKRUN_500M_MIPI_REF_CLK_ROOT     24000000UL     /* Clock consumers of MIPI_REF_CLK_ROOT output : DSI_HOST */
299 #define BOARD_BOOTCLOCKRUN_500M_MQS_CLK_ROOT          24000000UL     /* Clock consumers of MQS_CLK_ROOT output : ASRC */
300 #define BOARD_BOOTCLOCKRUN_500M_MQS_MCLK              24000000UL     /* Clock consumers of MQS_MCLK output : N/A */
301 #define BOARD_BOOTCLOCKRUN_500M_OSC_24M               24000000UL     /* Clock consumers of OSC_24M output : SPDIF, TMPSNS, USBPHY1, USBPHY2 */
302 #define BOARD_BOOTCLOCKRUN_500M_OSC_32K               32768UL        /* Clock consumers of OSC_32K output : GPIO13, RTWDOG3, RTWDOG4 */
303 #define BOARD_BOOTCLOCKRUN_500M_OSC_RC_16M            16000000UL     /* Clock consumers of OSC_RC_16M output : CCM, DCDC, EWM, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6, SSARC_LP */
304 #define BOARD_BOOTCLOCKRUN_500M_OSC_RC_400M           400000000UL    /* Clock consumers of OSC_RC_400M output : N/A */
305 #define BOARD_BOOTCLOCKRUN_500M_OSC_RC_48M            48000000UL     /* Clock consumers of OSC_RC_48M output : N/A */
306 #define BOARD_BOOTCLOCKRUN_500M_OSC_RC_48M_DIV2       24000000UL     /* Clock consumers of OSC_RC_48M_DIV2 output : N/A */
307 #define BOARD_BOOTCLOCKRUN_500M_PLL_AUDIO_CLK         0UL            /* Clock consumers of PLL_AUDIO_CLK output : N/A */
308 #define BOARD_BOOTCLOCKRUN_500M_PLL_AUDIO_SS_MODULATION 0UL          /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
309 #define BOARD_BOOTCLOCKRUN_500M_PLL_AUDIO_SS_RANGE    0UL            /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
310 #define BOARD_BOOTCLOCKRUN_500M_PLL_VIDEO_CLK         984000025UL    /* Clock consumers of PLL_VIDEO_CLK output : N/A */
311 #define BOARD_BOOTCLOCKRUN_500M_PLL_VIDEO_SS_MODULATION 0UL          /* Clock consumers of PLL_VIDEO_SS_MODULATION output : N/A */
312 #define BOARD_BOOTCLOCKRUN_500M_PLL_VIDEO_SS_RANGE    0UL            /* Clock consumers of PLL_VIDEO_SS_RANGE output : N/A */
313 #define BOARD_BOOTCLOCKRUN_500M_SAI1_CLK_ROOT         24000000UL     /* Clock consumers of SAI1_CLK_ROOT output : SPDIF */
314 #define BOARD_BOOTCLOCKRUN_500M_SAI1_MCLK1            24000000UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
315 #define BOARD_BOOTCLOCKRUN_500M_SAI1_MCLK2            0UL            /* Clock consumers of SAI1_MCLK2 output : SAI1 */
316 #define BOARD_BOOTCLOCKRUN_500M_SAI1_MCLK3            24000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
317 #define BOARD_BOOTCLOCKRUN_500M_SAI2_CLK_ROOT         24000000UL     /* Clock consumers of SAI2_CLK_ROOT output : ASRC */
318 #define BOARD_BOOTCLOCKRUN_500M_SAI2_MCLK1            24000000UL     /* Clock consumers of SAI2_MCLK1 output : SAI2 */
319 #define BOARD_BOOTCLOCKRUN_500M_SAI2_MCLK2            0UL            /* Clock consumers of SAI2_MCLK2 output : SAI2 */
320 #define BOARD_BOOTCLOCKRUN_500M_SAI2_MCLK3            24000000UL     /* Clock consumers of SAI2_MCLK3 output : SAI2 */
321 #define BOARD_BOOTCLOCKRUN_500M_SAI3_CLK_ROOT         24000000UL     /* Clock consumers of SAI3_CLK_ROOT output : ASRC, SPDIF */
322 #define BOARD_BOOTCLOCKRUN_500M_SAI3_MCLK1            24000000UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
323 #define BOARD_BOOTCLOCKRUN_500M_SAI3_MCLK2            0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
324 #define BOARD_BOOTCLOCKRUN_500M_SAI3_MCLK3            24000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
325 #define BOARD_BOOTCLOCKRUN_500M_SAI4_CLK_ROOT         24000000UL     /* Clock consumers of SAI4_CLK_ROOT output : ASRC, SPDIF */
326 #define BOARD_BOOTCLOCKRUN_500M_SAI4_MCLK1            24000000UL     /* Clock consumers of SAI4_MCLK1 output : SAI4 */
327 #define BOARD_BOOTCLOCKRUN_500M_SAI4_MCLK2            0UL            /* Clock consumers of SAI4_MCLK2 output : SAI4 */
328 #define BOARD_BOOTCLOCKRUN_500M_SEMC_CLK_ROOT         198000000UL    /* Clock consumers of SEMC_CLK_ROOT output : SEMC, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
329 #define BOARD_BOOTCLOCKRUN_500M_SPDIF_CLK_ROOT        24000000UL     /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
330 #define BOARD_BOOTCLOCKRUN_500M_SPDIF_EXTCLK_OUT      0UL            /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
331 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL1_CLK          0UL            /* Clock consumers of SYS_PLL1_CLK output : N/A */
332 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL1_DIV2_CLK     0UL            /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
333 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL1_DIV5_CLK     0UL            /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
334 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL1_SS_MODULATION0UL            /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
335 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL1_SS_RANGE     0UL            /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
336 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_CLK          528000000UL    /* Clock consumers of SYS_PLL2_CLK output : N/A */
337 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_PFD0_CLK     352000000UL    /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
338 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_PFD1_CLK     594000000UL    /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
339 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_PFD2_CLK     396000000UL    /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
340 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_PFD3_CLK     396000000UL    /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
341 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_SS_MODULATION0UL            /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
342 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL2_SS_RANGE     0UL            /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
343 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_CLK          480000000UL    /* Clock consumers of SYS_PLL3_CLK output : N/A */
344 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_DIV2_CLK     240000000UL    /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
345 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_PFD0_CLK     664615384UL    /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
346 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_PFD1_CLK     508235294UL    /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
347 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_PFD2_CLK     270000000UL    /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
348 #define BOARD_BOOTCLOCKRUN_500M_SYS_PLL3_PFD3_CLK     392727272UL    /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
349 #define BOARD_BOOTCLOCKRUN_500M_USDHC1_CLK_ROOT       24000000UL     /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
350 #define BOARD_BOOTCLOCKRUN_500M_USDHC2_CLK_ROOT       24000000UL     /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
351 
352 
353 /*******************************************************************************
354  * API for BOARD_BootClockRUN_500M configuration
355  ******************************************************************************/
356 #if defined(__cplusplus)
357 extern "C" {
358 #endif /* __cplusplus*/
359 
360 /*!
361  * @brief This function executes configuration of clocks.
362  *
363  */
364 void BOARD_BootClockRUN_500M(void);
365 
366 #if defined(__cplusplus)
367 }
368 #endif /* __cplusplus*/
369 
370 #endif /* _CLOCK_CONFIG_H_ */
371 
372