1 /*
2  * Copyright 2020, 2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef _CLOCK_CONFIG_H_
8 #define _CLOCK_CONFIG_H_
9 
10 #include "fsl_common.h"
11 #include "fsl_upower.h"
12 
13 /*!
14  * @brief This function executes default configuration of clocks.
15  *
16  */
17 void BOARD_InitBootClocks(void);
18 
19 
20 /*******************************************************************************
21  * DEFINITION
22  ******************************************************************************/
23 #define BOARD_XTAL0_CLK_HZ 24000000U
24 #define BOARD_XTAL32K_CLK_HZ 32768U
25 #define SWITCH_DRIVE_MODE_INIT_STATE (0)
26 #define SWITCH_DRIVE_MODE_FROM_ND_TO_OD (1)
27 #define SWITCH_DRIVE_MODE_FROM_ND_TO_UD (2)
28 #define SWITCH_DRIVE_MODE_FROM_UD_TO_ND (3)
29 #define SWITCH_DRIVE_MODE_FROM_OD_TO_ND (4)
30 
31 /* clock freqeuncy */
32 #define FREQ_12_5_MHZ (125000000U)
33 #define FREQ_20_MHZ (20000000U)
34 #define FREQ_24_MHZ (24000000U)
35 #define FREQ_38_4_MHZ (38400000U)
36 #define FREQ_65_MHZ (65000000U)
37 #define FREQ_108_MHZ (108000000U)
38 #define FREQ_160_MHZ (160000000U)
39 #define FREQ_216_MHZ (216000000U)
40 
41 /*
42  * m33 core frequency
43  * OD: Over Drive Mode(1.1 V)
44  * ND: Nominal Drive Mode(1.0 V)
45  * UD: Under Drive Mode(0.9 V)
46  */
47 #define CM33_CORE_MAX_FREQ_OD     (FREQ_216_MHZ)
48 #define CM33_CORE_MAX_FREQ_ND     (FREQ_160_MHZ)
49 #define CM33_CORE_MAX_FREQ_UD     (FREQ_38_4_MHZ)
50 #define CM33_BUS_MAX_FREQ_OD      (FREQ_108_MHZ)
51 #define CM33_BUS_MAX_FREQ_ND      (FREQ_65_MHZ)
52 #define CM33_BUS_MAX_FREQ_UD      (FREQ_20_MHZ)
53 #define CM33_SLOW_MAX_FREQ_OD     (FREQ_24_MHZ)
54 #define CM33_SLOW_MAX_FREQ_ND     (FREQ_20_MHZ)
55 #define CM33_SLOW_MAX_FREQ_UD     (FREQ_12_5_MHZ)
56 
57 typedef struct
58 {
59     cgc_rtd_sys_clk_src_t clk_src;
60     clock_name_t clk_name;
61 } rtd_sys_clk_src_and_clk_name_t;
62 
63 typedef struct
64 {
65     drive_mode_e drive_mode;
66     uint32_t max_core_clk_freq;
67     uint32_t max_bus_clk_freq;
68     uint32_t max_slow_clk_freq;
69 } drive_mode_and_clk_t;
70 
71 /*******************************************************************************
72  * API
73  ******************************************************************************/
74 #if defined(__cplusplus)
75 extern "C" {
76 #endif /* __cplusplus*/
77 
78 void BOARD_InitClock(void);
79 
80 void BOARD_BootClockRUN(void);
81 
82 void BOARD_ResumeClockInit(void);
83 
84 void BOARD_CalculateDivider(uint32_t src_freq, uint32_t dest_freq, int * divider);
85 
86 drive_mode_e BOARD_CalculateCoreClkDivider(cgc_rtd_sys_clk_src_t clk_src, int *core_clk_divider, int *bus_clk_divider, int *slow_clk_divider, drive_mode_e drive_mode);
87 
88 
89 void BOARD_InitPlls(void);
90 drive_mode_e BOARD_SwitchToFROClk(drive_mode_e drive_mode);
91 void BOARD_DisablePlls(void);
92 drive_mode_e BOARD_GetRtdDriveMode(void);
93 drive_mode_e BOARD_GetDriveModeByCoreFreq(uint32_t freq);
94 int32_t BOARD_UpdateM33CoreFreq(cgc_rtd_sys_clk_config_t *config);
95 void BOARD_SwitchDriveMode(void);
96 #if defined(__cplusplus)
97 }
98 #endif /* __cplusplus*/
99 
100 #endif /* _CLOCK_CONFIG_H_ */
101