1 /*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "clock_config.h"
10
11 /*******************************************************************************
12 ************************ BOARD_InitBootClocks function ************************
13 ******************************************************************************/
BOARD_InitBootClocks(void)14 void BOARD_InitBootClocks(void)
15 {
16 BOARD_BootClockRUN();
17 }
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22 /* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
23 /* AUDIO PLL1 configuration */
24 const ccm_analog_frac_pll_config_t g_audioPll1Config = {
25 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
26 .mainDiv = 262U,
27 .dsm = 9437U,
28 .preDiv = 2U,
29 .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393215996HZ */
30 };
31
32 /* AUDIO PLL2 configuration */
33 const ccm_analog_frac_pll_config_t g_audioPll2Config = {
34 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
35 .mainDiv = 361U,
36 .dsm = 17511U,
37 .preDiv = 3U,
38 .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267197HZ */
39 };
40
41 /* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
42 /* SYSTEM PLL1 configuration */
43 const ccm_analog_integer_pll_config_t g_sysPll1Config = {
44 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
45 .mainDiv = 400U,
46 .preDiv = 3U,
47 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
48 };
49
50 /* SYSTEM PLL2 configuration */
51 const ccm_analog_integer_pll_config_t g_sysPll2Config = {
52 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
53 .mainDiv = 250U,
54 .preDiv = 3U,
55 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
56 };
57
58 /* SYSTEM PLL3 configuration */
59 const ccm_analog_integer_pll_config_t g_sysPll3Config = {
60 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
61 .mainDiv = 300,
62 .preDiv = 3U,
63 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
64 };
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69
70 /*******************************************************************************
71 * Code
72 ******************************************************************************/
BOARD_BootClockRUN(void)73 void BOARD_BootClockRUN(void)
74 {
75 /* * The following steps just show how to configure the PLL clock sources using the clock driver on M7 core side .
76 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
77 * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
78 * Therefore, there is no need to configure the system PLL again on M7 side, otherwise it would have a risk to make
79 * the SOC hang.
80 */
81
82 /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
83 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
84
85 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL3. */
86 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxOsc24M);
87
88 /* Init Audio PLL1/Audio PLL2 */
89 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393215996HZ */
90 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267197HZ */
91
92 /* As ROM not enables PLL3 by default, enable PLL3 to 600M if A core not set it. */
93 if (CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl) == 1)
94 {
95 CLOCK_InitSysPll3(&g_sysPll3Config);
96 }
97 CLOCK_SetRootDivider(kCLOCK_RootM7, 1U, 1U); /* Set M7 root clock freq to 600M / 1 = 600M */
98 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxSysPll3); /* switch cortex-m7 to SYSTEM PLL3 */
99
100 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); /* Set root clock freq to 133M / 1= 133MHZ */
101 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 */
102
103 CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock freq to 800MHZ/ 2= 400MHZ*/
104 CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
105
106 CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U); /* Set root clock freq to 80MHZ/ 1= 80MHZ */
107 CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
108
109 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
110 CLOCK_EnableClock(kCLOCK_Ocram); /* Enable Ocram clock */
111
112 /* The purpose to enable the following modules clock is to make sure the M7 core could work normally when A53 core
113 * enters the low power status.*/
114 CLOCK_EnableClock(kCLOCK_Sim_display);
115 CLOCK_EnableClock(kCLOCK_Sim_m);
116 CLOCK_EnableClock(kCLOCK_Sim_main);
117 CLOCK_EnableClock(kCLOCK_Sim_s);
118 CLOCK_EnableClock(kCLOCK_Sim_wakeup);
119 CLOCK_EnableClock(kCLOCK_Debug);
120 CLOCK_EnableClock(kCLOCK_Dram);
121 CLOCK_EnableClock(kCLOCK_Sec_Debug);
122
123 /* Update core clock */
124 SystemCoreClockUpdate();
125 }
126
