1 /* 2 * Copyright 2018-2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _BOARD_H_ 9 #define _BOARD_H_ 10 #include "clock_config.h" 11 #include "fsl_clock.h" 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 /*! @brief The board name */ 16 #define BOARD_NAME "MIMX8MM-EVK" 17 #define MANUFACTURER_NAME "NXP" 18 #define BOARD_DOMAIN_ID (1) 19 /* The UART to use for debug messages. */ 20 #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart 21 #define BOARD_DEBUG_UART_BAUDRATE 115200u 22 #define BOARD_DEBUG_UART_BASEADDR UART4_BASE 23 #define BOARD_DEBUG_UART_INSTANCE 4U 24 #define BOARD_DEBUG_UART_CLK_FREQ \ 25 CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) / \ 26 (CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) / 10 27 #define BOARD_UART_IRQ UART4_IRQn 28 #define BOARD_UART_IRQ_HANDLER UART4_IRQHandler 29 30 #define GPV5_BASE_ADDR (0x32500000) 31 #define FORCE_INCR_OFFSET (0x4044) 32 #define FORCE_INCR_BIT_MASK (0x2) 33 #define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */ 34 #define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */ 35 36 #define BOARD_GPC_BASEADDR GPC 37 #define BOARD_MU_IRQ_NUM MU_M4_IRQn 38 39 /* Shared memory base for RPMsg communication. */ 40 #define VDEV0_VRING_BASE (0xB8000000U) 41 #define RESOURCE_TABLE_OFFSET (0xFF000) 42 43 #if defined(__cplusplus) 44 extern "C" { 45 #endif /* __cplusplus */ 46 47 /******************************************************************************* 48 * API 49 ******************************************************************************/ 50 51 void BOARD_InitDebugConsole(void); 52 void BOARD_InitMemory(void); 53 void BOARD_RdcInit(void); 54 55 #if defined(__cplusplus) 56 } 57 #endif /* __cplusplus */ 58 59 #endif /* _BOARD_H_ */ 60
