1 /**************************************************************************//**
2 * @file cmsis_gcc.h
3 * @brief CMSIS compiler GCC header file
4 * @version V5.4.1
5 * @date 27. May 2021
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_GCC_H
26 #define __CMSIS_GCC_H
27
28 /* ignore some GCC warnings */
29 #pragma GCC diagnostic push
30 #pragma GCC diagnostic ignored "-Wsign-conversion"
31 #pragma GCC diagnostic ignored "-Wconversion"
32 #pragma GCC diagnostic ignored "-Wunused-parameter"
33
34 /* Fallback for __has_builtin */
35 #ifndef __has_builtin
36 #define __has_builtin(x) (0)
37 #endif
38
39 /* CMSIS compiler specific defines */
40 #ifndef __ASM
41 #define __ASM __asm
42 #endif
43 #ifndef __INLINE
44 #define __INLINE inline
45 #endif
46 #ifndef __STATIC_INLINE
47 #define __STATIC_INLINE static inline
48 #endif
49 #ifndef __STATIC_FORCEINLINE
50 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51 #endif
52 #ifndef __NO_RETURN
53 #define __NO_RETURN __attribute__((__noreturn__))
54 #endif
55 #ifndef __USED
56 #define __USED __attribute__((used))
57 #endif
58 #ifndef __WEAK
59 #define __WEAK __attribute__((weak))
60 #endif
61 #ifndef __PACKED
62 #define __PACKED __attribute__((packed, aligned(1)))
63 #endif
64 #ifndef __PACKED_STRUCT
65 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66 #endif
67 #ifndef __PACKED_UNION
68 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69 #endif
70 #ifndef __UNALIGNED_UINT32 /* deprecated */
71 #pragma GCC diagnostic push
72 #pragma GCC diagnostic ignored "-Wpacked"
73 #pragma GCC diagnostic ignored "-Wattributes"
74 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75 #pragma GCC diagnostic pop
76 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77 #endif
78 #ifndef __UNALIGNED_UINT16_WRITE
79 #pragma GCC diagnostic push
80 #pragma GCC diagnostic ignored "-Wpacked"
81 #pragma GCC diagnostic ignored "-Wattributes"
82 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83 #pragma GCC diagnostic pop
84 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
85 #endif
86 #ifndef __UNALIGNED_UINT16_READ
87 #pragma GCC diagnostic push
88 #pragma GCC diagnostic ignored "-Wpacked"
89 #pragma GCC diagnostic ignored "-Wattributes"
90 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91 #pragma GCC diagnostic pop
92 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
93 #endif
94 #ifndef __UNALIGNED_UINT32_WRITE
95 #pragma GCC diagnostic push
96 #pragma GCC diagnostic ignored "-Wpacked"
97 #pragma GCC diagnostic ignored "-Wattributes"
98 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99 #pragma GCC diagnostic pop
100 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
101 #endif
102 #ifndef __UNALIGNED_UINT32_READ
103 #pragma GCC diagnostic push
104 #pragma GCC diagnostic ignored "-Wpacked"
105 #pragma GCC diagnostic ignored "-Wattributes"
106 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107 #pragma GCC diagnostic pop
108 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
109 #endif
110 #ifndef __ALIGNED
111 #define __ALIGNED(x) __attribute__((aligned(x)))
112 #endif
113 #ifndef __RESTRICT
114 #define __RESTRICT __restrict
115 #endif
116 #ifndef __COMPILER_BARRIER
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118 #endif
119
120 /* ######################### Startup and Lowlevel Init ######################## */
121
122 #ifndef __PROGRAM_START
123
124 /**
125 \brief Initializes data and bss sections
126 \details This default implementations initialized all data and additional bss
127 sections relying on .copy.table and .zero.table specified properly
128 in the used linker script.
129
130 */
__cmsis_start(void)131 __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132 {
133 extern void _start(void) __NO_RETURN;
134
135 typedef struct {
136 uint32_t const* src;
137 uint32_t* dest;
138 uint32_t wlen;
139 } __copy_table_t;
140
141 typedef struct {
142 uint32_t* dest;
143 uint32_t wlen;
144 } __zero_table_t;
145
146 extern const __copy_table_t __copy_table_start__;
147 extern const __copy_table_t __copy_table_end__;
148 extern const __zero_table_t __zero_table_start__;
149 extern const __zero_table_t __zero_table_end__;
150
151 for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
152 for(uint32_t i=0u; i<pTable->wlen; ++i) {
153 pTable->dest[i] = pTable->src[i];
154 }
155 }
156
157 for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
158 for(uint32_t i=0u; i<pTable->wlen; ++i) {
159 pTable->dest[i] = 0u;
160 }
161 }
162
163 _start();
164 }
165
166 #define __PROGRAM_START __cmsis_start
167 #endif
168
169 #ifndef __INITIAL_SP
170 #define __INITIAL_SP __StackTop
171 #endif
172
173 #ifndef __STACK_LIMIT
174 #define __STACK_LIMIT __StackLimit
175 #endif
176
177 #ifndef __VECTOR_TABLE
178 #define __VECTOR_TABLE __Vectors
179 #endif
180
181 #ifndef __VECTOR_TABLE_ATTRIBUTE
182 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
183 #endif
184
185 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
186 #ifndef __STACK_SEAL
187 #define __STACK_SEAL __StackSeal
188 #endif
189
190 #ifndef __TZ_STACK_SEAL_SIZE
191 #define __TZ_STACK_SEAL_SIZE 8U
192 #endif
193
194 #ifndef __TZ_STACK_SEAL_VALUE
195 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
196 #endif
197
198
__TZ_set_STACKSEAL_S(uint32_t * stackTop)199 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
200 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
201 }
202 #endif
203
204
205 /* ########################## Core Instruction Access ######################### */
206 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
207 Access to dedicated instructions
208 @{
209 */
210
211 /* Define macros for porting to both thumb1 and thumb2.
212 * For thumb1, use low register (r0-r7), specified by constraint "l"
213 * Otherwise, use general registers, specified by constraint "r" */
214 #if defined (__thumb__) && !defined (__thumb2__)
215 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
216 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
217 #define __CMSIS_GCC_USE_REG(r) "l" (r)
218 #else
219 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
220 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
221 #define __CMSIS_GCC_USE_REG(r) "r" (r)
222 #endif
223
224 /**
225 \brief No Operation
226 \details No Operation does nothing. This instruction can be used for code alignment purposes.
227 */
228 #define __NOP() __ASM volatile ("nop")
229
230 /**
231 \brief Wait For Interrupt
232 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
233 */
234 #define __WFI() __ASM volatile ("wfi":::"memory")
235
236
237 /**
238 \brief Wait For Event
239 \details Wait For Event is a hint instruction that permits the processor to enter
240 a low-power state until one of a number of events occurs.
241 */
242 #define __WFE() __ASM volatile ("wfe":::"memory")
243
244
245 /**
246 \brief Send Event
247 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
248 */
249 #define __SEV() __ASM volatile ("sev")
250
251
252 /**
253 \brief Instruction Synchronization Barrier
254 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
255 so that all instructions following the ISB are fetched from cache or memory,
256 after the instruction has been completed.
257 */
__ISB(void)258 __STATIC_FORCEINLINE void __ISB(void)
259 {
260 __ASM volatile ("isb 0xF":::"memory");
261 }
262
263
264 /**
265 \brief Data Synchronization Barrier
266 \details Acts as a special kind of Data Memory Barrier.
267 It completes when all explicit memory accesses before this instruction complete.
268 */
__DSB(void)269 __STATIC_FORCEINLINE void __DSB(void)
270 {
271 __ASM volatile ("dsb 0xF":::"memory");
272 }
273
274
275 /**
276 \brief Data Memory Barrier
277 \details Ensures the apparent order of the explicit memory operations before
278 and after the instruction, without ensuring their completion.
279 */
__DMB(void)280 __STATIC_FORCEINLINE void __DMB(void)
281 {
282 __ASM volatile ("dmb 0xF":::"memory");
283 }
284
285
286 /**
287 \brief Reverse byte order (32 bit)
288 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
289 \param [in] value Value to reverse
290 \return Reversed value
291 */
__REV(uint32_t value)292 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
293 {
294 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
295 return __builtin_bswap32(value);
296 #else
297 uint32_t result;
298
299 __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
300 return result;
301 #endif
302 }
303
304
305 /**
306 \brief Reverse byte order (16 bit)
307 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
308 \param [in] value Value to reverse
309 \return Reversed value
310 */
__REV16(uint32_t value)311 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
312 {
313 uint32_t result;
314
315 __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
316 return result;
317 }
318
319
320 /**
321 \brief Reverse byte order (16 bit)
322 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
323 \param [in] value Value to reverse
324 \return Reversed value
325 */
__REVSH(int16_t value)326 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
327 {
328 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
329 return (int16_t)__builtin_bswap16(value);
330 #else
331 int16_t result;
332
333 __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
334 return result;
335 #endif
336 }
337
338
339 /**
340 \brief Rotate Right in unsigned value (32 bit)
341 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
342 \param [in] op1 Value to rotate
343 \param [in] op2 Number of Bits to rotate
344 \return Rotated value
345 */
__ROR(uint32_t op1,uint32_t op2)346 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
347 {
348 op2 %= 32U;
349 if (op2 == 0U)
350 {
351 return op1;
352 }
353 return (op1 >> op2) | (op1 << (32U - op2));
354 }
355
356
357 /**
358 \brief Breakpoint
359 \details Causes the processor to enter Debug state.
360 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
361 \param [in] value is ignored by the processor.
362 If required, a debugger can use it to store additional information about the breakpoint.
363 */
364 #define __BKPT(value) __ASM volatile ("bkpt "#value)
365
366
367 /**
368 \brief Reverse bit order of value
369 \details Reverses the bit order of the given value.
370 \param [in] value Value to reverse
371 \return Reversed value
372 */
__RBIT(uint32_t value)373 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
374 {
375 uint32_t result;
376
377 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
378 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
379 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
380 __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
381 #else
382 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
383
384 result = value; /* r will be reversed bits of v; first get LSB of v */
385 for (value >>= 1U; value != 0U; value >>= 1U)
386 {
387 result <<= 1U;
388 result |= value & 1U;
389 s--;
390 }
391 result <<= s; /* shift when v's highest bits are zero */
392 #endif
393 return result;
394 }
395
396
397 /**
398 \brief Count leading zeros
399 \details Counts the number of leading zeros of a data value.
400 \param [in] value Value to count the leading zeros
401 \return number of leading zeros in value
402 */
__CLZ(uint32_t value)403 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
404 {
405 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
406 __builtin_clz(0) is undefined behaviour, so handle this case specially.
407 This guarantees ARM-compatible results if happening to compile on a non-ARM
408 target, and ensures the compiler doesn't decide to activate any
409 optimisations using the logic "value was passed to __builtin_clz, so it
410 is non-zero".
411 ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
412 single CLZ instruction.
413 */
414 if (value == 0U)
415 {
416 return 32U;
417 }
418 return __builtin_clz(value);
419 }
420
421
422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
425 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
426 /**
427 \brief LDR Exclusive (8 bit)
428 \details Executes a exclusive LDR instruction for 8 bit value.
429 \param [in] ptr Pointer to data
430 \return value of type uint8_t at (*ptr)
431 */
__LDREXB(volatile uint8_t * addr)432 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
433 {
434 uint32_t result;
435
436 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
437 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
438 #else
439 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
440 accepted by assembler. So has to use following less efficient pattern.
441 */
442 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
443 #endif
444 return ((uint8_t) result); /* Add explicit type cast here */
445 }
446
447
448 /**
449 \brief LDR Exclusive (16 bit)
450 \details Executes a exclusive LDR instruction for 16 bit values.
451 \param [in] ptr Pointer to data
452 \return value of type uint16_t at (*ptr)
453 */
__LDREXH(volatile uint16_t * addr)454 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
455 {
456 uint32_t result;
457
458 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
459 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
460 #else
461 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
462 accepted by assembler. So has to use following less efficient pattern.
463 */
464 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
465 #endif
466 return ((uint16_t) result); /* Add explicit type cast here */
467 }
468
469
470 /**
471 \brief LDR Exclusive (32 bit)
472 \details Executes a exclusive LDR instruction for 32 bit values.
473 \param [in] ptr Pointer to data
474 \return value of type uint32_t at (*ptr)
475 */
__LDREXW(volatile uint32_t * addr)476 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
477 {
478 uint32_t result;
479
480 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
481 return(result);
482 }
483
484
485 /**
486 \brief STR Exclusive (8 bit)
487 \details Executes a exclusive STR instruction for 8 bit values.
488 \param [in] value Value to store
489 \param [in] ptr Pointer to location
490 \return 0 Function succeeded
491 \return 1 Function failed
492 */
__STREXB(uint8_t value,volatile uint8_t * addr)493 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
494 {
495 uint32_t result;
496
497 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
498 return(result);
499 }
500
501
502 /**
503 \brief STR Exclusive (16 bit)
504 \details Executes a exclusive STR instruction for 16 bit values.
505 \param [in] value Value to store
506 \param [in] ptr Pointer to location
507 \return 0 Function succeeded
508 \return 1 Function failed
509 */
__STREXH(uint16_t value,volatile uint16_t * addr)510 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
511 {
512 uint32_t result;
513
514 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
515 return(result);
516 }
517
518
519 /**
520 \brief STR Exclusive (32 bit)
521 \details Executes a exclusive STR instruction for 32 bit values.
522 \param [in] value Value to store
523 \param [in] ptr Pointer to location
524 \return 0 Function succeeded
525 \return 1 Function failed
526 */
__STREXW(uint32_t value,volatile uint32_t * addr)527 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
528 {
529 uint32_t result;
530
531 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
532 return(result);
533 }
534
535
536 /**
537 \brief Remove the exclusive lock
538 \details Removes the exclusive lock which is created by LDREX.
539 */
__CLREX(void)540 __STATIC_FORCEINLINE void __CLREX(void)
541 {
542 __ASM volatile ("clrex" ::: "memory");
543 }
544
545 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
546 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
547 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
548 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
549
550
551 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
552 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
553 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
554 /**
555 \brief Signed Saturate
556 \details Saturates a signed value.
557 \param [in] ARG1 Value to be saturated
558 \param [in] ARG2 Bit position to saturate to (1..32)
559 \return Saturated value
560 */
561 #define __SSAT(ARG1, ARG2) \
562 __extension__ \
563 ({ \
564 int32_t __RES, __ARG1 = (ARG1); \
565 __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
566 __RES; \
567 })
568
569
570 /**
571 \brief Unsigned Saturate
572 \details Saturates an unsigned value.
573 \param [in] ARG1 Value to be saturated
574 \param [in] ARG2 Bit position to saturate to (0..31)
575 \return Saturated value
576 */
577 #define __USAT(ARG1, ARG2) \
578 __extension__ \
579 ({ \
580 uint32_t __RES, __ARG1 = (ARG1); \
581 __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
582 __RES; \
583 })
584
585
586 /**
587 \brief Rotate Right with Extend (32 bit)
588 \details Moves each bit of a bitstring right by one bit.
589 The carry input is shifted in at the left end of the bitstring.
590 \param [in] value Value to rotate
591 \return Rotated value
592 */
__RRX(uint32_t value)593 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
594 {
595 uint32_t result;
596
597 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
598 return(result);
599 }
600
601
602 /**
603 \brief LDRT Unprivileged (8 bit)
604 \details Executes a Unprivileged LDRT instruction for 8 bit value.
605 \param [in] ptr Pointer to data
606 \return value of type uint8_t at (*ptr)
607 */
__LDRBT(volatile uint8_t * ptr)608 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
609 {
610 uint32_t result;
611
612 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
613 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
614 #else
615 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
616 accepted by assembler. So has to use following less efficient pattern.
617 */
618 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
619 #endif
620 return ((uint8_t) result); /* Add explicit type cast here */
621 }
622
623
624 /**
625 \brief LDRT Unprivileged (16 bit)
626 \details Executes a Unprivileged LDRT instruction for 16 bit values.
627 \param [in] ptr Pointer to data
628 \return value of type uint16_t at (*ptr)
629 */
__LDRHT(volatile uint16_t * ptr)630 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
631 {
632 uint32_t result;
633
634 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
635 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
636 #else
637 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
638 accepted by assembler. So has to use following less efficient pattern.
639 */
640 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
641 #endif
642 return ((uint16_t) result); /* Add explicit type cast here */
643 }
644
645
646 /**
647 \brief LDRT Unprivileged (32 bit)
648 \details Executes a Unprivileged LDRT instruction for 32 bit values.
649 \param [in] ptr Pointer to data
650 \return value of type uint32_t at (*ptr)
651 */
__LDRT(volatile uint32_t * ptr)652 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
653 {
654 uint32_t result;
655
656 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
657 return(result);
658 }
659
660
661 /**
662 \brief STRT Unprivileged (8 bit)
663 \details Executes a Unprivileged STRT instruction for 8 bit values.
664 \param [in] value Value to store
665 \param [in] ptr Pointer to location
666 */
__STRBT(uint8_t value,volatile uint8_t * ptr)667 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
668 {
669 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
670 }
671
672
673 /**
674 \brief STRT Unprivileged (16 bit)
675 \details Executes a Unprivileged STRT instruction for 16 bit values.
676 \param [in] value Value to store
677 \param [in] ptr Pointer to location
678 */
__STRHT(uint16_t value,volatile uint16_t * ptr)679 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
680 {
681 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
682 }
683
684
685 /**
686 \brief STRT Unprivileged (32 bit)
687 \details Executes a Unprivileged STRT instruction for 32 bit values.
688 \param [in] value Value to store
689 \param [in] ptr Pointer to location
690 */
__STRT(uint32_t value,volatile uint32_t * ptr)691 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
692 {
693 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
694 }
695
696 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
697 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
698 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
699
700 /**
701 \brief Signed Saturate
702 \details Saturates a signed value.
703 \param [in] value Value to be saturated
704 \param [in] sat Bit position to saturate to (1..32)
705 \return Saturated value
706 */
__SSAT(int32_t val,uint32_t sat)707 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
708 {
709 if ((sat >= 1U) && (sat <= 32U))
710 {
711 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
712 const int32_t min = -1 - max ;
713 if (val > max)
714 {
715 return max;
716 }
717 else if (val < min)
718 {
719 return min;
720 }
721 }
722 return val;
723 }
724
725 /**
726 \brief Unsigned Saturate
727 \details Saturates an unsigned value.
728 \param [in] value Value to be saturated
729 \param [in] sat Bit position to saturate to (0..31)
730 \return Saturated value
731 */
__USAT(int32_t val,uint32_t sat)732 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
733 {
734 if (sat <= 31U)
735 {
736 const uint32_t max = ((1U << sat) - 1U);
737 if (val > (int32_t)max)
738 {
739 return max;
740 }
741 else if (val < 0)
742 {
743 return 0U;
744 }
745 }
746 return (uint32_t)val;
747 }
748
749 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
750 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
751 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
752
753
754 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
755 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
756 /**
757 \brief Load-Acquire (8 bit)
758 \details Executes a LDAB instruction for 8 bit value.
759 \param [in] ptr Pointer to data
760 \return value of type uint8_t at (*ptr)
761 */
__LDAB(volatile uint8_t * ptr)762 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
763 {
764 uint32_t result;
765
766 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
767 return ((uint8_t) result);
768 }
769
770
771 /**
772 \brief Load-Acquire (16 bit)
773 \details Executes a LDAH instruction for 16 bit values.
774 \param [in] ptr Pointer to data
775 \return value of type uint16_t at (*ptr)
776 */
__LDAH(volatile uint16_t * ptr)777 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
778 {
779 uint32_t result;
780
781 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
782 return ((uint16_t) result);
783 }
784
785
786 /**
787 \brief Load-Acquire (32 bit)
788 \details Executes a LDA instruction for 32 bit values.
789 \param [in] ptr Pointer to data
790 \return value of type uint32_t at (*ptr)
791 */
__LDA(volatile uint32_t * ptr)792 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
793 {
794 uint32_t result;
795
796 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
797 return(result);
798 }
799
800
801 /**
802 \brief Store-Release (8 bit)
803 \details Executes a STLB instruction for 8 bit values.
804 \param [in] value Value to store
805 \param [in] ptr Pointer to location
806 */
__STLB(uint8_t value,volatile uint8_t * ptr)807 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
808 {
809 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
810 }
811
812
813 /**
814 \brief Store-Release (16 bit)
815 \details Executes a STLH instruction for 16 bit values.
816 \param [in] value Value to store
817 \param [in] ptr Pointer to location
818 */
__STLH(uint16_t value,volatile uint16_t * ptr)819 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
820 {
821 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
822 }
823
824
825 /**
826 \brief Store-Release (32 bit)
827 \details Executes a STL instruction for 32 bit values.
828 \param [in] value Value to store
829 \param [in] ptr Pointer to location
830 */
__STL(uint32_t value,volatile uint32_t * ptr)831 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
832 {
833 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
834 }
835
836
837 /**
838 \brief Load-Acquire Exclusive (8 bit)
839 \details Executes a LDAB exclusive instruction for 8 bit value.
840 \param [in] ptr Pointer to data
841 \return value of type uint8_t at (*ptr)
842 */
__LDAEXB(volatile uint8_t * ptr)843 __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
844 {
845 uint32_t result;
846
847 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
848 return ((uint8_t) result);
849 }
850
851
852 /**
853 \brief Load-Acquire Exclusive (16 bit)
854 \details Executes a LDAH exclusive instruction for 16 bit values.
855 \param [in] ptr Pointer to data
856 \return value of type uint16_t at (*ptr)
857 */
__LDAEXH(volatile uint16_t * ptr)858 __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
859 {
860 uint32_t result;
861
862 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
863 return ((uint16_t) result);
864 }
865
866
867 /**
868 \brief Load-Acquire Exclusive (32 bit)
869 \details Executes a LDA exclusive instruction for 32 bit values.
870 \param [in] ptr Pointer to data
871 \return value of type uint32_t at (*ptr)
872 */
__LDAEX(volatile uint32_t * ptr)873 __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
874 {
875 uint32_t result;
876
877 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
878 return(result);
879 }
880
881
882 /**
883 \brief Store-Release Exclusive (8 bit)
884 \details Executes a STLB exclusive instruction for 8 bit values.
885 \param [in] value Value to store
886 \param [in] ptr Pointer to location
887 \return 0 Function succeeded
888 \return 1 Function failed
889 */
__STLEXB(uint8_t value,volatile uint8_t * ptr)890 __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
891 {
892 uint32_t result;
893
894 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
895 return(result);
896 }
897
898
899 /**
900 \brief Store-Release Exclusive (16 bit)
901 \details Executes a STLH exclusive instruction for 16 bit values.
902 \param [in] value Value to store
903 \param [in] ptr Pointer to location
904 \return 0 Function succeeded
905 \return 1 Function failed
906 */
__STLEXH(uint16_t value,volatile uint16_t * ptr)907 __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
908 {
909 uint32_t result;
910
911 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
912 return(result);
913 }
914
915
916 /**
917 \brief Store-Release Exclusive (32 bit)
918 \details Executes a STL exclusive instruction for 32 bit values.
919 \param [in] value Value to store
920 \param [in] ptr Pointer to location
921 \return 0 Function succeeded
922 \return 1 Function failed
923 */
__STLEX(uint32_t value,volatile uint32_t * ptr)924 __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
925 {
926 uint32_t result;
927
928 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
929 return(result);
930 }
931
932 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
933 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
934
935 /**
936 \brief likely/unlikely() branch prediction
937 \details Gives hints to the compiler to favor either side of a jump instruction
938 \param [in] expr Boolean expression under evaluation
939 \return The same boolean value
940 */
941 #ifndef unlikely
unlikely(long expr)942 __STATIC_FORCEINLINE long unlikely(long expr)
943 {
944 return __builtin_expect(expr, 0L);
945 }
946 #endif
947
948 #ifndef likely
likely(long expr)949 __STATIC_FORCEINLINE long likely(long expr)
950 {
951 return __builtin_expect(expr, 1L);
952 }
953 #endif
954
955 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
956
957
958 /* ########################### Core Function Access ########################### */
959 /** \ingroup CMSIS_Core_FunctionInterface
960 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
961 @{
962 */
963
964 /**
965 \brief Enable IRQ Interrupts
966 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
967 Can only be executed in Privileged modes.
968 */
__enable_irq(void)969 __STATIC_FORCEINLINE void __enable_irq(void)
970 {
971 __ASM volatile ("cpsie i" : : : "memory");
972 }
973
974
975 /**
976 \brief Disable IRQ Interrupts
977 \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
978 Can only be executed in Privileged modes.
979 */
__disable_irq(void)980 __STATIC_FORCEINLINE void __disable_irq(void)
981 {
982 __ASM volatile ("cpsid i" : : : "memory");
983 }
984
985
986 /**
987 \brief Get Control Register
988 \details Returns the content of the Control Register.
989 \return Control Register value
990 */
__get_CONTROL(void)991 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
992 {
993 uint32_t result;
994
995 __ASM volatile ("MRS %0, control" : "=r" (result) );
996 return(result);
997 }
998
999
1000 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1001 /**
1002 \brief Get Control Register (non-secure)
1003 \details Returns the content of the non-secure Control Register when in secure mode.
1004 \return non-secure Control Register value
1005 */
__TZ_get_CONTROL_NS(void)1006 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
1007 {
1008 uint32_t result;
1009
1010 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
1011 return(result);
1012 }
1013 #endif
1014
1015
1016 /**
1017 \brief Set Control Register
1018 \details Writes the given value to the Control Register.
1019 \param [in] control Control Register value to set
1020 */
__set_CONTROL(uint32_t control)1021 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1022 {
1023 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1024 __ISB();
1025 }
1026
1027
1028 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1029 /**
1030 \brief Set Control Register (non-secure)
1031 \details Writes the given value to the non-secure Control Register when in secure state.
1032 \param [in] control Control Register value to set
1033 */
__TZ_set_CONTROL_NS(uint32_t control)1034 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1035 {
1036 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1037 __ISB();
1038 }
1039 #endif
1040
1041
1042 /**
1043 \brief Get IPSR Register
1044 \details Returns the content of the IPSR Register.
1045 \return IPSR Register value
1046 */
__get_IPSR(void)1047 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1048 {
1049 uint32_t result;
1050
1051 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1052 return(result);
1053 }
1054
1055
1056 /**
1057 \brief Get APSR Register
1058 \details Returns the content of the APSR Register.
1059 \return APSR Register value
1060 */
__get_APSR(void)1061 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1062 {
1063 uint32_t result;
1064
1065 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1066 return(result);
1067 }
1068
1069
1070 /**
1071 \brief Get xPSR Register
1072 \details Returns the content of the xPSR Register.
1073 \return xPSR Register value
1074 */
__get_xPSR(void)1075 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1076 {
1077 uint32_t result;
1078
1079 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1080 return(result);
1081 }
1082
1083
1084 /**
1085 \brief Get Process Stack Pointer
1086 \details Returns the current value of the Process Stack Pointer (PSP).
1087 \return PSP Register value
1088 */
__get_PSP(void)1089 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1090 {
1091 uint32_t result;
1092
1093 __ASM volatile ("MRS %0, psp" : "=r" (result) );
1094 return(result);
1095 }
1096
1097
1098 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1099 /**
1100 \brief Get Process Stack Pointer (non-secure)
1101 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
1102 \return PSP Register value
1103 */
__TZ_get_PSP_NS(void)1104 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1105 {
1106 uint32_t result;
1107
1108 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
1109 return(result);
1110 }
1111 #endif
1112
1113
1114 /**
1115 \brief Set Process Stack Pointer
1116 \details Assigns the given value to the Process Stack Pointer (PSP).
1117 \param [in] topOfProcStack Process Stack Pointer value to set
1118 */
__set_PSP(uint32_t topOfProcStack)1119 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1120 {
1121 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1122 }
1123
1124
1125 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1126 /**
1127 \brief Set Process Stack Pointer (non-secure)
1128 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
1129 \param [in] topOfProcStack Process Stack Pointer value to set
1130 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)1131 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1132 {
1133 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1134 }
1135 #endif
1136
1137
1138 /**
1139 \brief Get Main Stack Pointer
1140 \details Returns the current value of the Main Stack Pointer (MSP).
1141 \return MSP Register value
1142 */
__get_MSP(void)1143 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1144 {
1145 uint32_t result;
1146
1147 __ASM volatile ("MRS %0, msp" : "=r" (result) );
1148 return(result);
1149 }
1150
1151
1152 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1153 /**
1154 \brief Get Main Stack Pointer (non-secure)
1155 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
1156 \return MSP Register value
1157 */
__TZ_get_MSP_NS(void)1158 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1159 {
1160 uint32_t result;
1161
1162 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1163 return(result);
1164 }
1165 #endif
1166
1167
1168 /**
1169 \brief Set Main Stack Pointer
1170 \details Assigns the given value to the Main Stack Pointer (MSP).
1171 \param [in] topOfMainStack Main Stack Pointer value to set
1172 */
__set_MSP(uint32_t topOfMainStack)1173 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1174 {
1175 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1176 }
1177
1178
1179 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1180 /**
1181 \brief Set Main Stack Pointer (non-secure)
1182 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1183 \param [in] topOfMainStack Main Stack Pointer value to set
1184 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)1185 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1186 {
1187 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1188 }
1189 #endif
1190
1191
1192 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1193 /**
1194 \brief Get Stack Pointer (non-secure)
1195 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1196 \return SP Register value
1197 */
__TZ_get_SP_NS(void)1198 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1199 {
1200 uint32_t result;
1201
1202 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1203 return(result);
1204 }
1205
1206
1207 /**
1208 \brief Set Stack Pointer (non-secure)
1209 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1210 \param [in] topOfStack Stack Pointer value to set
1211 */
__TZ_set_SP_NS(uint32_t topOfStack)1212 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1213 {
1214 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1215 }
1216 #endif
1217
1218
1219 /**
1220 \brief Get Priority Mask
1221 \details Returns the current state of the priority mask bit from the Priority Mask Register.
1222 \return Priority Mask value
1223 */
__get_PRIMASK(void)1224 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
1225 {
1226 uint32_t result;
1227
1228 __ASM volatile ("MRS %0, primask" : "=r" (result) );
1229 return(result);
1230 }
1231
1232
1233 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1234 /**
1235 \brief Get Priority Mask (non-secure)
1236 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
1237 \return Priority Mask value
1238 */
__TZ_get_PRIMASK_NS(void)1239 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1240 {
1241 uint32_t result;
1242
1243 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1244 return(result);
1245 }
1246 #endif
1247
1248
1249 /**
1250 \brief Set Priority Mask
1251 \details Assigns the given value to the Priority Mask Register.
1252 \param [in] priMask Priority Mask
1253 */
__set_PRIMASK(uint32_t priMask)1254 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1255 {
1256 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1257 }
1258
1259
1260 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1261 /**
1262 \brief Set Priority Mask (non-secure)
1263 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1264 \param [in] priMask Priority Mask
1265 */
__TZ_set_PRIMASK_NS(uint32_t priMask)1266 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1267 {
1268 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1269 }
1270 #endif
1271
1272
1273 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1274 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1275 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1276 /**
1277 \brief Enable FIQ
1278 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1279 Can only be executed in Privileged modes.
1280 */
__enable_fault_irq(void)1281 __STATIC_FORCEINLINE void __enable_fault_irq(void)
1282 {
1283 __ASM volatile ("cpsie f" : : : "memory");
1284 }
1285
1286
1287 /**
1288 \brief Disable FIQ
1289 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1290 Can only be executed in Privileged modes.
1291 */
__disable_fault_irq(void)1292 __STATIC_FORCEINLINE void __disable_fault_irq(void)
1293 {
1294 __ASM volatile ("cpsid f" : : : "memory");
1295 }
1296
1297
1298 /**
1299 \brief Get Base Priority
1300 \details Returns the current value of the Base Priority register.
1301 \return Base Priority register value
1302 */
__get_BASEPRI(void)1303 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1304 {
1305 uint32_t result;
1306
1307 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1308 return(result);
1309 }
1310
1311
1312 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1313 /**
1314 \brief Get Base Priority (non-secure)
1315 \details Returns the current value of the non-secure Base Priority register when in secure state.
1316 \return Base Priority register value
1317 */
__TZ_get_BASEPRI_NS(void)1318 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1319 {
1320 uint32_t result;
1321
1322 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1323 return(result);
1324 }
1325 #endif
1326
1327
1328 /**
1329 \brief Set Base Priority
1330 \details Assigns the given value to the Base Priority register.
1331 \param [in] basePri Base Priority value to set
1332 */
__set_BASEPRI(uint32_t basePri)1333 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1334 {
1335 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1336 }
1337
1338
1339 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1340 /**
1341 \brief Set Base Priority (non-secure)
1342 \details Assigns the given value to the non-secure Base Priority register when in secure state.
1343 \param [in] basePri Base Priority value to set
1344 */
__TZ_set_BASEPRI_NS(uint32_t basePri)1345 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1346 {
1347 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1348 }
1349 #endif
1350
1351
1352 /**
1353 \brief Set Base Priority with condition
1354 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1355 or the new value increases the BASEPRI priority level.
1356 \param [in] basePri Base Priority value to set
1357 */
__set_BASEPRI_MAX(uint32_t basePri)1358 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1359 {
1360 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1361 }
1362
1363
1364 /**
1365 \brief Get Fault Mask
1366 \details Returns the current value of the Fault Mask register.
1367 \return Fault Mask register value
1368 */
__get_FAULTMASK(void)1369 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1370 {
1371 uint32_t result;
1372
1373 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1374 return(result);
1375 }
1376
1377
1378 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1379 /**
1380 \brief Get Fault Mask (non-secure)
1381 \details Returns the current value of the non-secure Fault Mask register when in secure state.
1382 \return Fault Mask register value
1383 */
__TZ_get_FAULTMASK_NS(void)1384 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1385 {
1386 uint32_t result;
1387
1388 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1389 return(result);
1390 }
1391 #endif
1392
1393
1394 /**
1395 \brief Set Fault Mask
1396 \details Assigns the given value to the Fault Mask register.
1397 \param [in] faultMask Fault Mask value to set
1398 */
__set_FAULTMASK(uint32_t faultMask)1399 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1400 {
1401 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1402 }
1403
1404
1405 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1406 /**
1407 \brief Set Fault Mask (non-secure)
1408 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1409 \param [in] faultMask Fault Mask value to set
1410 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)1411 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1412 {
1413 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1414 }
1415 #endif
1416
1417 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1418 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1419 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1420
1421
1422 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1423 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1424
1425 /**
1426 \brief Get Process Stack Pointer Limit
1427 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1428 Stack Pointer Limit register hence zero is returned always in non-secure
1429 mode.
1430
1431 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1432 \return PSPLIM Register value
1433 */
__get_PSPLIM(void)1434 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1435 {
1436 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1437 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1438 // without main extensions, the non-secure PSPLIM is RAZ/WI
1439 return 0U;
1440 #else
1441 uint32_t result;
1442 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1443 return result;
1444 #endif
1445 }
1446
1447 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1448 /**
1449 \brief Get Process Stack Pointer Limit (non-secure)
1450 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1451 Stack Pointer Limit register hence zero is returned always.
1452
1453 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1454 \return PSPLIM Register value
1455 */
__TZ_get_PSPLIM_NS(void)1456 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1457 {
1458 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1459 // without main extensions, the non-secure PSPLIM is RAZ/WI
1460 return 0U;
1461 #else
1462 uint32_t result;
1463 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1464 return result;
1465 #endif
1466 }
1467 #endif
1468
1469
1470 /**
1471 \brief Set Process Stack Pointer Limit
1472 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1473 Stack Pointer Limit register hence the write is silently ignored in non-secure
1474 mode.
1475
1476 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1477 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1478 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)1479 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1480 {
1481 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1482 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1483 // without main extensions, the non-secure PSPLIM is RAZ/WI
1484 (void)ProcStackPtrLimit;
1485 #else
1486 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1487 #endif
1488 }
1489
1490
1491 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1492 /**
1493 \brief Set Process Stack Pointer (non-secure)
1494 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1495 Stack Pointer Limit register hence the write is silently ignored.
1496
1497 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1498 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1499 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)1500 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1501 {
1502 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1503 // without main extensions, the non-secure PSPLIM is RAZ/WI
1504 (void)ProcStackPtrLimit;
1505 #else
1506 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1507 #endif
1508 }
1509 #endif
1510
1511
1512 /**
1513 \brief Get Main Stack Pointer Limit
1514 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1515 Stack Pointer Limit register hence zero is returned always in non-secure
1516 mode.
1517
1518 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1519 \return MSPLIM Register value
1520 */
__get_MSPLIM(void)1521 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1522 {
1523 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1524 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1525 // without main extensions, the non-secure MSPLIM is RAZ/WI
1526 return 0U;
1527 #else
1528 uint32_t result;
1529 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1530 return result;
1531 #endif
1532 }
1533
1534
1535 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1536 /**
1537 \brief Get Main Stack Pointer Limit (non-secure)
1538 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1539 Stack Pointer Limit register hence zero is returned always.
1540
1541 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1542 \return MSPLIM Register value
1543 */
__TZ_get_MSPLIM_NS(void)1544 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1545 {
1546 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1547 // without main extensions, the non-secure MSPLIM is RAZ/WI
1548 return 0U;
1549 #else
1550 uint32_t result;
1551 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1552 return result;
1553 #endif
1554 }
1555 #endif
1556
1557
1558 /**
1559 \brief Set Main Stack Pointer Limit
1560 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1561 Stack Pointer Limit register hence the write is silently ignored in non-secure
1562 mode.
1563
1564 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1565 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1566 */
__set_MSPLIM(uint32_t MainStackPtrLimit)1567 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1568 {
1569 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1570 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1571 // without main extensions, the non-secure MSPLIM is RAZ/WI
1572 (void)MainStackPtrLimit;
1573 #else
1574 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1575 #endif
1576 }
1577
1578
1579 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1580 /**
1581 \brief Set Main Stack Pointer Limit (non-secure)
1582 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1583 Stack Pointer Limit register hence the write is silently ignored.
1584
1585 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1586 \param [in] MainStackPtrLimit Main Stack Pointer value to set
1587 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)1588 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1589 {
1590 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1591 // without main extensions, the non-secure MSPLIM is RAZ/WI
1592 (void)MainStackPtrLimit;
1593 #else
1594 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1595 #endif
1596 }
1597 #endif
1598
1599 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1600 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1601
1602
1603 /**
1604 \brief Get FPSCR
1605 \details Returns the current value of the Floating Point Status/Control register.
1606 \return Floating Point Status/Control register value
1607 */
__get_FPSCR(void)1608 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
1609 {
1610 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1611 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1612 #if __has_builtin(__builtin_arm_get_fpscr)
1613 // Re-enable using built-in when GCC has been fixed
1614 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
1615 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
1616 return __builtin_arm_get_fpscr();
1617 #else
1618 uint32_t result;
1619
1620 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
1621 return(result);
1622 #endif
1623 #else
1624 return(0U);
1625 #endif
1626 }
1627
1628
1629 /**
1630 \brief Set FPSCR
1631 \details Assigns the given value to the Floating Point Status/Control register.
1632 \param [in] fpscr Floating Point Status/Control value to set
1633 */
__set_FPSCR(uint32_t fpscr)1634 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
1635 {
1636 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1637 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1638 #if __has_builtin(__builtin_arm_set_fpscr)
1639 // Re-enable using built-in when GCC has been fixed
1640 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
1641 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
1642 __builtin_arm_set_fpscr(fpscr);
1643 #else
1644 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
1645 #endif
1646 #else
1647 (void)fpscr;
1648 #endif
1649 }
1650
1651
1652 /*@} end of CMSIS_Core_RegAccFunctions */
1653
1654
1655 /* ################### Compiler specific Intrinsics ########################### */
1656 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1657 Access to dedicated SIMD instructions
1658 @{
1659 */
1660
1661 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1662
__SADD8(uint32_t op1,uint32_t op2)1663 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1664 {
1665 uint32_t result;
1666
1667 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1668 return(result);
1669 }
1670
__QADD8(uint32_t op1,uint32_t op2)1671 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1672 {
1673 uint32_t result;
1674
1675 __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1676 return(result);
1677 }
1678
__SHADD8(uint32_t op1,uint32_t op2)1679 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1680 {
1681 uint32_t result;
1682
1683 __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1684 return(result);
1685 }
1686
__UADD8(uint32_t op1,uint32_t op2)1687 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1688 {
1689 uint32_t result;
1690
1691 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1692 return(result);
1693 }
1694
__UQADD8(uint32_t op1,uint32_t op2)1695 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1696 {
1697 uint32_t result;
1698
1699 __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1700 return(result);
1701 }
1702
__UHADD8(uint32_t op1,uint32_t op2)1703 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1704 {
1705 uint32_t result;
1706
1707 __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1708 return(result);
1709 }
1710
1711
__SSUB8(uint32_t op1,uint32_t op2)1712 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1713 {
1714 uint32_t result;
1715
1716 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1717 return(result);
1718 }
1719
__QSUB8(uint32_t op1,uint32_t op2)1720 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1721 {
1722 uint32_t result;
1723
1724 __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1725 return(result);
1726 }
1727
__SHSUB8(uint32_t op1,uint32_t op2)1728 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1729 {
1730 uint32_t result;
1731
1732 __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1733 return(result);
1734 }
1735
__USUB8(uint32_t op1,uint32_t op2)1736 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1737 {
1738 uint32_t result;
1739
1740 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1741 return(result);
1742 }
1743
__UQSUB8(uint32_t op1,uint32_t op2)1744 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1745 {
1746 uint32_t result;
1747
1748 __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1749 return(result);
1750 }
1751
__UHSUB8(uint32_t op1,uint32_t op2)1752 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1753 {
1754 uint32_t result;
1755
1756 __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1757 return(result);
1758 }
1759
1760
__SADD16(uint32_t op1,uint32_t op2)1761 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1762 {
1763 uint32_t result;
1764
1765 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1766 return(result);
1767 }
1768
__QADD16(uint32_t op1,uint32_t op2)1769 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1770 {
1771 uint32_t result;
1772
1773 __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1774 return(result);
1775 }
1776
__SHADD16(uint32_t op1,uint32_t op2)1777 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1778 {
1779 uint32_t result;
1780
1781 __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1782 return(result);
1783 }
1784
__UADD16(uint32_t op1,uint32_t op2)1785 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1786 {
1787 uint32_t result;
1788
1789 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1790 return(result);
1791 }
1792
__UQADD16(uint32_t op1,uint32_t op2)1793 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1794 {
1795 uint32_t result;
1796
1797 __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1798 return(result);
1799 }
1800
__UHADD16(uint32_t op1,uint32_t op2)1801 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1802 {
1803 uint32_t result;
1804
1805 __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1806 return(result);
1807 }
1808
__SSUB16(uint32_t op1,uint32_t op2)1809 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1810 {
1811 uint32_t result;
1812
1813 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1814 return(result);
1815 }
1816
__QSUB16(uint32_t op1,uint32_t op2)1817 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1818 {
1819 uint32_t result;
1820
1821 __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1822 return(result);
1823 }
1824
__SHSUB16(uint32_t op1,uint32_t op2)1825 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1826 {
1827 uint32_t result;
1828
1829 __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1830 return(result);
1831 }
1832
__USUB16(uint32_t op1,uint32_t op2)1833 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1834 {
1835 uint32_t result;
1836
1837 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1838 return(result);
1839 }
1840
__UQSUB16(uint32_t op1,uint32_t op2)1841 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1842 {
1843 uint32_t result;
1844
1845 __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1846 return(result);
1847 }
1848
__UHSUB16(uint32_t op1,uint32_t op2)1849 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1850 {
1851 uint32_t result;
1852
1853 __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1854 return(result);
1855 }
1856
__SASX(uint32_t op1,uint32_t op2)1857 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1858 {
1859 uint32_t result;
1860
1861 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1862 return(result);
1863 }
1864
__QASX(uint32_t op1,uint32_t op2)1865 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1866 {
1867 uint32_t result;
1868
1869 __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1870 return(result);
1871 }
1872
__SHASX(uint32_t op1,uint32_t op2)1873 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1874 {
1875 uint32_t result;
1876
1877 __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1878 return(result);
1879 }
1880
__UASX(uint32_t op1,uint32_t op2)1881 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1882 {
1883 uint32_t result;
1884
1885 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1886 return(result);
1887 }
1888
__UQASX(uint32_t op1,uint32_t op2)1889 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1890 {
1891 uint32_t result;
1892
1893 __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1894 return(result);
1895 }
1896
__UHASX(uint32_t op1,uint32_t op2)1897 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1898 {
1899 uint32_t result;
1900
1901 __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1902 return(result);
1903 }
1904
__SSAX(uint32_t op1,uint32_t op2)1905 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1906 {
1907 uint32_t result;
1908
1909 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1910 return(result);
1911 }
1912
__QSAX(uint32_t op1,uint32_t op2)1913 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1914 {
1915 uint32_t result;
1916
1917 __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1918 return(result);
1919 }
1920
__SHSAX(uint32_t op1,uint32_t op2)1921 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1922 {
1923 uint32_t result;
1924
1925 __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1926 return(result);
1927 }
1928
__USAX(uint32_t op1,uint32_t op2)1929 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1930 {
1931 uint32_t result;
1932
1933 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1934 return(result);
1935 }
1936
__UQSAX(uint32_t op1,uint32_t op2)1937 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1938 {
1939 uint32_t result;
1940
1941 __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1942 return(result);
1943 }
1944
__UHSAX(uint32_t op1,uint32_t op2)1945 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1946 {
1947 uint32_t result;
1948
1949 __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1950 return(result);
1951 }
1952
__USAD8(uint32_t op1,uint32_t op2)1953 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1954 {
1955 uint32_t result;
1956
1957 __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1958 return(result);
1959 }
1960
__USADA8(uint32_t op1,uint32_t op2,uint32_t op3)1961 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1962 {
1963 uint32_t result;
1964
1965 __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1966 return(result);
1967 }
1968
1969 #define __SSAT16(ARG1, ARG2) \
1970 __extension__ \
1971 ({ \
1972 int32_t __RES, __ARG1 = (ARG1); \
1973 __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1974 __RES; \
1975 })
1976
1977 #define __USAT16(ARG1, ARG2) \
1978 __extension__ \
1979 ({ \
1980 uint32_t __RES, __ARG1 = (ARG1); \
1981 __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1982 __RES; \
1983 })
1984
__UXTB16(uint32_t op1)1985 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1986 {
1987 uint32_t result;
1988
1989 __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1990 return(result);
1991 }
1992
__UXTAB16(uint32_t op1,uint32_t op2)1993 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1994 {
1995 uint32_t result;
1996
1997 __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1998 return(result);
1999 }
2000
__SXTB16(uint32_t op1)2001 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
2002 {
2003 uint32_t result;
2004
2005 __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
2006 return(result);
2007 }
2008
__SXTB16_RORn(uint32_t op1,uint32_t rotate)2009 __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
2010 {
2011 uint32_t result;
2012 if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
2013 __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
2014 } else {
2015 result = __SXTB16(__ROR(op1, rotate)) ;
2016 }
2017 return result;
2018 }
2019
__SXTAB16(uint32_t op1,uint32_t op2)2020 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
2021 {
2022 uint32_t result;
2023
2024 __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2025 return(result);
2026 }
2027
__SXTAB16_RORn(uint32_t op1,uint32_t op2,uint32_t rotate)2028 __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
2029 {
2030 uint32_t result;
2031 if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
2032 __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
2033 } else {
2034 result = __SXTAB16(op1, __ROR(op2, rotate));
2035 }
2036 return result;
2037 }
2038
2039
__SMUAD(uint32_t op1,uint32_t op2)2040 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
2041 {
2042 uint32_t result;
2043
2044 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2045 return(result);
2046 }
2047
__SMUADX(uint32_t op1,uint32_t op2)2048 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
2049 {
2050 uint32_t result;
2051
2052 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2053 return(result);
2054 }
2055
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)2056 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
2057 {
2058 uint32_t result;
2059
2060 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2061 return(result);
2062 }
2063
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)2064 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
2065 {
2066 uint32_t result;
2067
2068 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2069 return(result);
2070 }
2071
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)2072 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
2073 {
2074 union llreg_u{
2075 uint32_t w32[2];
2076 uint64_t w64;
2077 } llr;
2078 llr.w64 = acc;
2079
2080 #ifndef __ARMEB__ /* Little endian */
2081 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2082 #else /* Big endian */
2083 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2084 #endif
2085
2086 return(llr.w64);
2087 }
2088
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)2089 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
2090 {
2091 union llreg_u{
2092 uint32_t w32[2];
2093 uint64_t w64;
2094 } llr;
2095 llr.w64 = acc;
2096
2097 #ifndef __ARMEB__ /* Little endian */
2098 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2099 #else /* Big endian */
2100 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2101 #endif
2102
2103 return(llr.w64);
2104 }
2105
__SMUSD(uint32_t op1,uint32_t op2)2106 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
2107 {
2108 uint32_t result;
2109
2110 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2111 return(result);
2112 }
2113
__SMUSDX(uint32_t op1,uint32_t op2)2114 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
2115 {
2116 uint32_t result;
2117
2118 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2119 return(result);
2120 }
2121
__SMLSD(uint32_t op1,uint32_t op2,uint32_t op3)2122 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
2123 {
2124 uint32_t result;
2125
2126 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2127 return(result);
2128 }
2129
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)2130 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
2131 {
2132 uint32_t result;
2133
2134 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2135 return(result);
2136 }
2137
__SMLSLD(uint32_t op1,uint32_t op2,uint64_t acc)2138 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
2139 {
2140 union llreg_u{
2141 uint32_t w32[2];
2142 uint64_t w64;
2143 } llr;
2144 llr.w64 = acc;
2145
2146 #ifndef __ARMEB__ /* Little endian */
2147 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2148 #else /* Big endian */
2149 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2150 #endif
2151
2152 return(llr.w64);
2153 }
2154
__SMLSLDX(uint32_t op1,uint32_t op2,uint64_t acc)2155 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
2156 {
2157 union llreg_u{
2158 uint32_t w32[2];
2159 uint64_t w64;
2160 } llr;
2161 llr.w64 = acc;
2162
2163 #ifndef __ARMEB__ /* Little endian */
2164 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2165 #else /* Big endian */
2166 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2167 #endif
2168
2169 return(llr.w64);
2170 }
2171
__SEL(uint32_t op1,uint32_t op2)2172 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
2173 {
2174 uint32_t result;
2175
2176 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2177 return(result);
2178 }
2179
__QADD(int32_t op1,int32_t op2)2180 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
2181 {
2182 int32_t result;
2183
2184 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2185 return(result);
2186 }
2187
__QSUB(int32_t op1,int32_t op2)2188 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
2189 {
2190 int32_t result;
2191
2192 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2193 return(result);
2194 }
2195
2196
2197 #define __PKHBT(ARG1,ARG2,ARG3) \
2198 __extension__ \
2199 ({ \
2200 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2201 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2202 __RES; \
2203 })
2204
2205 #define __PKHTB(ARG1,ARG2,ARG3) \
2206 __extension__ \
2207 ({ \
2208 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2209 if (ARG3 == 0) \
2210 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
2211 else \
2212 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2213 __RES; \
2214 })
2215
2216
__SMMLA(int32_t op1,int32_t op2,int32_t op3)2217 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
2218 {
2219 int32_t result;
2220
2221 __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
2222 return(result);
2223 }
2224
2225 #endif /* (__ARM_FEATURE_DSP == 1) */
2226 /*@} end of group CMSIS_SIMD_intrinsics */
2227
2228
2229 #pragma GCC diagnostic pop
2230
2231 #endif /* __CMSIS_GCC_H */
2232
