1 /*
2 ** ###################################################################
3 **     Processors:          MCIMX6X_M4
4 **
5 **     Compilers:           Keil ARM C/C++ Compiler
6 **                          Freescale C/C++ for Embedded ARM
7 **                          GNU C Compiler
8 **                          GNU C Compiler - CodeSourcery Sourcery G++
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **
11 **     Reference manual:
12 **     Version:             rev. 1.0, 2015-07-17
13 **     Build:               b150707
14 **
15 **     Abstract:
16 **         CMSIS Peripheral Access Layer for MCIMX6X_M4
17 **
18 **     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
19 **     All rights reserved.
20 **
21 **     Redistribution and use in source and binary forms, with or without modification,
22 **     are permitted provided that the following conditions are met:
23 **
24 **     o Redistributions of source code must retain the above copyright notice, this list
25 **       of conditions and the following disclaimer.
26 **
27 **     o Redistributions in binary form must reproduce the above copyright notice, this
28 **       list of conditions and the following disclaimer in the documentation and/or
29 **       other materials provided with the distribution.
30 **
31 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
32 **       contributors may be used to endorse or promote products derived from this
33 **       software without specific prior written permission.
34 **
35 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
39 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
44 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 **
46 **     http:                 www.freescale.com
47 **     mail:                 support@freescale.com
48 **
49 **     Revisions:
50 **     - rev. 1.0 (2015-07-17)
51 **         Initial version .
52 **
53 ** ###################################################################
54 */
55 
56 /*!
57  * @file MCIMX6X_M4.h
58  * @version 1.0
59  * @date 2015-07-17
60  * @brief CMSIS Peripheral Access Layer for MCIMX6X_M4
61  *
62  * CMSIS Peripheral Access Layer for MCIMX6X_M4
63  */
64 
65 /* ----------------------------------------------------------------------------
66    -- MCU activation
67    ---------------------------------------------------------------------------- */
68 
69 /* Prevention from multiple including the same memory map */
70 #if !defined(MCIMX6X_M4_H_)  /* Check if memory map has not been already included */
71 #define MCIMX6X_M4_H_
72 #define MCU_MCIMX6X_M4
73 
74 /* Check if another memory map has not been also included */
75 #if (defined(MCU_ACTIVE))
76     #error MCIMX6X_M4 memory map: There is already included another memory map. Only one memory map can be included.
77 #endif /* (defined(MCU_ACTIVE)) */
78 #define MCU_ACTIVE
79 
80 #include <stdint.h>
81 
82 /** Memory map major version (memory maps with equal major version number are
83  * compatible) */
84 #define MCU_MEM_MAP_VERSION 0x0100u
85 /** Memory map minor version */
86 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
87 
88 /* ----------------------------------------------------------------------------
89    -- Interrupt vector numbers
90    ---------------------------------------------------------------------------- */
91 
92 /*!
93  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
94  * @{
95  */
96 
97 /** Interrupt Number Definitions */
98 #define NUMBER_OF_INT_VECTORS 144                  /**< Number of interrupts in the Vector table */
99 
100 typedef enum IRQn {
101   /* Auxiliary constants */
102   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
103 
104   /* Core interrupts */
105   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
106   HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
107   MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
108   BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
109   UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
110   SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
111   DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
112   PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
113   SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
114 
115   /* Device specific interrupts */
116   Cortex_M4_IRQn               = 0,                /**<  Cache Controller interrupt */
117   DAP_IRQn                     = 1,                /**<  Debug Access Port interrupt request. */
118   SDMA_IRQn                    = 2,                /**<  SDMA interrupt request from all channels. */
119   Reserved0_IRQn               = 3,                /**<  Reserved */
120   SNVS_IRQn                    = 4,                /**<  PMIC power off request. */
121   LCDIF1_IRQn                  = 5,                /**<  LCDIF1 Sync Interrupt */
122   LCDIF2_IRQn                  = 6,                /**<  LCDIF2 Sync Interrupt */
123   CSI1_IRQn                    = 7,                /**<  CMOS Sensor Interface interrupt request */
124   PXP_IRQn                     = 8,                /**<  PXP interrupt */
125   Reserved1_IRQn               = 9,                /**<  Reserved */
126   GPU_IRQn                     = 10,               /**<  GPU general interrupt request */
127   WDOG3_IRQn                   = 11,               /**<  WDOG3 interrupt request */
128   SEMA4_CP1_IRQn               = 12,               /**<  SEMA4 CP1 interrupt request. */
129   APBHDMA_IRQn                 = 13,               /**<  Logical OR of APBH DMA channels 0-3 completion and error interrupts. */
130   EIM_IRQn                     = 14,               /**<  EIM interrupt request. */
131   BCH_IRQn                     = 15,               /**<  BCH operation complete interrupt. */
132   GPMI_IRQn                    = 16,               /**<  GPMI operation timeout error interrupt. */
133   UART6_IRQn                   = 17,               /**<  UART6 interrupt request. */
134   eCSPI5_IRQn                  = 18,               /**<  eCSPI5 interrupt request. */
135   SNVS_CONSOLIDATED_IRQn       = 19,               /**<  SNVS consolidated interrupt. */
136   SNVS_SECURITY_IRQn           = 20,               /**<  SNVS security interrupt. */
137   CSU_IRQn                     = 21,               /**<  CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */
138   USDHC1_IRQn                  = 22,               /**<  uSDHC1 (Enhanced SDHC) interrupt request */
139   USDHC2_IRQn                  = 23,               /**<  uSDHC2 (Enhanced SDHC) interrupt request. */
140   USDHC3_IRQn                  = 24,               /**<  uSDHC3 (Enhanced SDHC) interrupt request. */
141   USDHC4_IRQn                  = 25,               /**<  uSDHC4 (Enhanced SDHC) interrupt request. */
142   UART1_IRQn                   = 26,               /**<  UART1 interrupt request. */
143   UART2_IRQn                   = 27,               /**<  UART2 interrupt request. */
144   UART3_IRQn                   = 28,               /**<  UART3 interrupt request. */
145   UART4_IRQn                   = 29,               /**<  UART4 interrupt request. */
146   UART5_IRQn                   = 30,               /**<  UART5 interrupt request. */
147   eCSPI1_IRQn                  = 31,               /**<  eCSPI1 interrupt request. */
148   eCSPI2_IRQn                  = 32,               /**<  eCSPI2 interrupt request. */
149   eCSPI3_IRQn                  = 33,               /**<  eCSPI3 interrupt request. */
150   eCSPI4_IRQn                  = 34,               /**<  eCSPI4 interrupt request. */
151   I2C4_IRQn                    = 35,               /**<  I2C4 interrupt request */
152   I2C1_IRQn                    = 36,               /**<  I2C1 interrupt request. */
153   I2C2_IRQn                    = 37,               /**<  I2C2 interrupt request. */
154   I2C3_IRQn                    = 38,               /**<  I2C3 interrupt request. */
155   RDC_IRQn                     = 39,               /**<  RDC interrupt request. */
156   USB_IRQn                     = 40,               /**<  USB HISC Host interrupt request. */
157   CSI2_IRQn                    = 41,               /**<  CSI interrupt */
158   USB_OTG2_IRQn                = 42,               /**<  USB OTG 2 interrupt request. */
159   USB_OTG1_IRQn                = 43,               /**<  USB OTG 1 interrupt request. */
160   USB_PHY1_IRQn                = 44,               /**<  UTMI0 interrupt request. */
161   USB_PHY2_IRQn                = 45,               /**<  UTMI1 interrupt request. */
162   SSI1_IRQn                    = 46,               /**<  SSI1 interrupt request. */
163   SSI2_IRQn                    = 47,               /**<  SSI2 interrupt request. */
164   SSI3_IRQn                    = 48,               /**<  SSI3 interrupt request. */
165   Temperature_Monitor_IRQn     = 49,               /**<  Temperature Sensor (temp. greater than threshold) interrupt request. */
166   ASRC_IRQn                    = 50,               /**<  ASRC interrupt request. */
167   ESAI_IRQn                    = 51,               /**<  ESAI interrupt request */
168   SPDIF_IRQn                   = 52,               /**<  SPDIF Rx/Tx interrupt. */
169   MLB_ERROR_IRQn               = 53,               /**<  MLB error interrupt request. */
170   PMU1_IRQn                    = 54,               /**<  Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */
171   GPT_IRQn                     = 55,               /**<  Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines. */
172   EPIT1_IRQn                   = 56,               /**<  EPIT1 output compare interrupt. */
173   EPIT2_IRQn                   = 57,               /**<  EPIT2 output compare interrupt. */
174   GPIO1_INT7_IRQn              = 58,               /**<  INT7 interrupt request. */
175   GPIO1_INT6_IRQn              = 59,               /**<  INT6 interrupt request. */
176   GPIO1_INT5_IRQn              = 60,               /**<  INT5 interrupt request. */
177   GPIO1_INT4_IRQn              = 61,               /**<  INT4 interrupt request. */
178   GPIO1_INT3_IRQn              = 62,               /**<  INT3 interrupt request. */
179   GPIO1_INT2_IRQn              = 63,               /**<  INT2 interrupt request. */
180   GPIO1_INT1_IRQn              = 64,               /**<  INT1 interrupt request. */
181   GPIO1_INT0_IRQn              = 65,               /**<  INT0 interrupt request. */
182   GPIO1_INT15_0_IRQn           = 66,               /**<  Combined interrupt indication for GPIO1 signals 0 - 15. */
183   GPIO1_INT31_16_IRQn          = 67,               /**<  Combined interrupt indication for GPIO1 signals 16 - 31. */
184   GPIO2_INT15_0_IRQn           = 68,               /**<  Combined interrupt indication for GPIO2 signals 0 - 15. */
185   GPIO2_INT31_16_IRQn          = 69,               /**<  Combined interrupt indication for GPIO2 signals 16 - 31. */
186   GPIO3_INT15_0_IRQn           = 70,               /**<  Combined interrupt indication for GPIO3 signals 0 - 15. */
187   GPIO3_INT31_16_IRQn          = 71,               /**<  Combined interrupt indication for GPIO3 signals 16 - 31. */
188   GPIO4_INT15_0_IRQn           = 72,               /**<  Combined interrupt indication for GPIO4 signals 0 - 15. */
189   GPIO4_INT31_16_IRQn          = 73,               /**<  Combined interrupt indication for GPIO4 signals 16 - 31. */
190   GPIO5_INT15_0_IRQn           = 74,               /**<  Combined interrupt indication for GPIO5 signals 0 - 15. */
191   GPIO5_INT31_16_IRQn          = 75,               /**<  Combined interrupt indication for GPIO5 signals 16 - 31. */
192   GPIO6_INT15_0_IRQn           = 76,               /**<  Combined interrupt indication for GPIO6 signals 0 - 15. */
193   GPIO6_INT31_16_IRQn          = 77,               /**<  Combined interrupt indication for GPIO6 signals 16 - 31. */
194   GPIO7_INT15_0_IRQn           = 78,               /**<  Combined interrupt indication for GPIO7 signals 0 - 15. */
195   GPIO7_INT31_16_IRQn          = 79,               /**<  Combined interrupt indication for GPIO7 signals 16 - 31. */
196   WDOG1_IRQn                   = 80,               /**<  WDOG1 timer reset interrupt request. */
197   WDOG2_IRQn                   = 81,               /**<  WDOG2 timer reset interrupt request. */
198   KPP_IRQn                     = 82,               /**<  Key Pad interrupt request */
199   PWM1_PWM5_IRQn               = 83,               /**<  Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */
200   PWM2_PWM6_IRQn               = 84,               /**<  Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */
201   PWM3_PWM7_IRQn               = 85,               /**<  Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */
202   PWM4_PWM8_IRQn               = 86,               /**<  Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */
203   CCM1_IRQn                    = 87,               /**<  CCM interrupt request 1. */
204   CCM2_IRQn                    = 88,               /**<  CCM interrupt request 2. */
205   GPC_IRQn                     = 89,               /**<  GPC interrupt request 1. */
206   MU_A9_IRQn                   = 90,               /**<  Message unit interrupt to A9 core */
207   SRC_IRQn                     = 91,               /**<  SRC interrupt request. */
208   CPU_L2I_IRQn                 = 92,               /**<  L2 interrupt request. */
209   CPU_PCEI_IRQn                = 93,               /**<  Parity Check error interrupt request. */
210   CPU_PUI_IRQn                 = 94,               /**<  Performance Unit interrupt. */
211   CPU_CTI_IRQn                 = 95,               /**<  CTI trigger outputs interrupt. */
212   SRC_CPU_WDOG_IRQn            = 96,               /**<  Combined CPU wdog interrupts (4x) out of SRC. */
213   SAI1_IRQn                    = 97,               /**<  SAI1 interrupt request. */
214   SAI2_IRQn                    = 98,               /**<  SAI2 interrupt request. */
215   MU_M4_IRQn                   = 99,               /**<  Message unit Interrupt to M4 core */
216   ADC1_IRQn                    = 100,              /**<  ADC1 interrupt request. */
217   ADC2_IRQn                    = 101,              /**<  ADC2 interrupt request. */
218   ENET2_IRQn                   = 102,              /**<  ENET2 Interrupt Request. */
219   ENET2_TI_IRQn                = 103,              /**<  ENET2 1588 Timer interrupt [synchronous] request. */
220   SJC_IRQn                     = 104,              /**<  SJC interrupt from General Purpose register. */
221   CAAM1_IRQn                   = 105,              /**<  CAAM job ring 0 interrupt. */
222   CAAM2_IRQn                   = 106,              /**<  CAAM job ring 1 interrupt. */
223   QSPI1_IRQn                   = 107,              /**<  QSPI1 interrupt request. */
224   TZASC_IRQn                   = 108,              /**<  TZASC (PL380) interrupt request. */
225   QSPI2_IRQn                   = 109,              /**<  QSPI2 interrupt request. */
226   FLEXCAN1_IRQn                = 110,              /**<  FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */
227   FLEXCAN2_IRQn                = 111,              /**<  FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */
228   Reserved2_IRQn               = 112,              /**<  Reserved */
229   Reserved3_IRQn               = 113,              /**<  Reserved */
230   Reserved4_IRQn               = 114,              /**<  Reserved */
231   Reserved5_IRQn               = 115,              /**<  Reserved */
232   SEMA4_CP0_IRQn               = 116,              /**<  SEMA4 CP0 interrupt request */
233   MLB_IRCI_IRQn                = 117,              /**<  Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158. */
234   ENET1_IRQn                   = 118,              /**<  ENET1 Interrupt Request. */
235   ENET1_TI_IRQn                = 119,              /**<  ENET1 1588 Timer interrupt [synchronous] request. */
236   PCIe1_IRQn                   = 120,              /**<  PCIe interrupt request 1. */
237   PCIe2_IRQn                   = 121,              /**<  PCIe interrupt request 2. */
238   PCIe3_IRQn                   = 122,              /**<  PCIe interrupt request 3. */
239   PCIe4_IRQn                   = 123,              /**<  PCIe interrupt request 4. */
240   DCIC1_IRQn                   = 124,              /**<  DCIC1 interrupt request. */
241   DCIC2_IRQn                   = 125,              /**<  DCIC2 interrupt request. */
242   MLB_LOCI_IRQn                = 126,              /**<  Logical OR of channel[63:32] interrupt requests. */
243   PMU2_IRQn                    = 127,              /**<  Brown out of core, gpu, and chip digital regulators occurred. */
244 } IRQn_Type;
245 
246 /*!
247  * @}
248  */ /* end of group Interrupt_vector_numbers */
249 
250 /* ----------------------------------------------------------------------------
251    -- Cortex M4 Core Configuration
252    ---------------------------------------------------------------------------- */
253 
254 /*!
255  * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
256  * @{
257  */
258 
259 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
260 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
261 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
262 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
263 
264 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
265 
266 /*!
267  * @}
268  */ /* end of group Cortex_Core_Configuration */
269 
270 /* ----------------------------------------------------------------------------
271    -- Device Peripheral Access Layer
272    ---------------------------------------------------------------------------- */
273 
274 /*!
275  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
276  * @{
277  */
278 
279 /*
280 ** Start of section using anonymous unions
281 */
282 
283 #if defined(__ARMCC_VERSION)
284   #pragma push
285   #pragma anon_unions
286 #elif defined(__GNUC__)
287   /* anonymous unions are enabled by default */
288 #elif defined(__IAR_SYSTEMS_ICC__)
289   #pragma language=extended
290 #else
291   #error Not supported compiler type
292 #endif
293 
294 /* ----------------------------------------------------------------------------
295    -- ADC Peripheral Access Layer
296    ---------------------------------------------------------------------------- */
297 
298 /*!
299  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
300  * @{
301  */
302 
303 /** ADC - Register Layout Typedef */
304 typedef struct {
305   __IO  uint32_t HC0;                                    /**< Control register for hardware triggers, offset: 0x0 */
306   __IO  uint32_t HC1;                                    /**< Control register for hardware triggers, offset: 0x4 */
307   __I   uint32_t HS;                                     /**< Status register for HW triggers, offset: 0x8 */
308   __IO  uint32_t R0;                                     /**< Data result register for HW triggers, offset: 0xC */
309   __IO  uint32_t R1;                                     /**< Data result register for HW triggers, offset: 0x10 */
310   __IO  uint32_t CFG;                                    /**< Configuration register, offset: 0x14 */
311   __IO  uint32_t GC;                                     /**< General control register, offset: 0x18 */
312   __IO  uint32_t GS;                                     /**< General status register, offset: 0x1C */
313   __IO  uint32_t CV;                                     /**< Compare value register, offset: 0x20 */
314   __IO  uint32_t OFS;                                    /**< Offset correction value register, offset: 0x24 */
315   __IO  uint32_t CAL;                                    /**< Calibration value register, offset: 0x28 */
316 } ADC_Type, *ADC_MemMapPtr;
317 
318 /* ----------------------------------------------------------------------------
319    -- ADC - Register accessor macros
320    ---------------------------------------------------------------------------- */
321 
322 /*!
323  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
324  * @{
325  */
326 
327 /* ADC - Register accessors */
328 #define ADC_HC0_REG(base)                        ((base)->HC0)
329 #define ADC_HC1_REG(base)                        ((base)->HC1)
330 #define ADC_HS_REG(base)                         ((base)->HS)
331 #define ADC_R0_REG(base)                         ((base)->R0)
332 #define ADC_R1_REG(base)                         ((base)->R1)
333 #define ADC_CFG_REG(base)                        ((base)->CFG)
334 #define ADC_GC_REG(base)                         ((base)->GC)
335 #define ADC_GS_REG(base)                         ((base)->GS)
336 #define ADC_CV_REG(base)                         ((base)->CV)
337 #define ADC_OFS_REG(base)                        ((base)->OFS)
338 #define ADC_CAL_REG(base)                        ((base)->CAL)
339 
340 /*!
341  * @}
342  */ /* end of group ADC_Register_Accessor_Macros */
343 
344 /* ----------------------------------------------------------------------------
345    -- ADC Register Masks
346    ---------------------------------------------------------------------------- */
347 
348 /*!
349  * @addtogroup ADC_Register_Masks ADC Register Masks
350  * @{
351  */
352 
353 /* HC0 Bit Fields */
354 #define ADC_HC0_ADCH_MASK                        0x1Fu
355 #define ADC_HC0_ADCH_SHIFT                       0
356 #define ADC_HC0_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_HC0_ADCH_SHIFT))&ADC_HC0_ADCH_MASK)
357 #define ADC_HC0_AIEN_MASK                        0x80u
358 #define ADC_HC0_AIEN_SHIFT                       7
359 /* HC1 Bit Fields */
360 #define ADC_HC1_ADCH_MASK                        0x1Fu
361 #define ADC_HC1_ADCH_SHIFT                       0
362 #define ADC_HC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_HC1_ADCH_SHIFT))&ADC_HC1_ADCH_MASK)
363 #define ADC_HC1_AIEN_MASK                        0x80u
364 #define ADC_HC1_AIEN_SHIFT                       7
365 /* HS Bit Fields */
366 #define ADC_HS_COCO0_MASK                        0x1u
367 #define ADC_HS_COCO0_SHIFT                       0
368 #define ADC_HS_COCO1_MASK                        0x2u
369 #define ADC_HS_COCO1_SHIFT                       1
370 /* R0 Bit Fields */
371 #define ADC_R0_D_MASK                            0xFFFu
372 #define ADC_R0_D_SHIFT                           0
373 #define ADC_R0_D(x)                              (((uint32_t)(((uint32_t)(x))<<ADC_R0_D_SHIFT))&ADC_R0_D_MASK)
374 /* R1 Bit Fields */
375 #define ADC_R1_D_MASK                            0xFFFu
376 #define ADC_R1_D_SHIFT                           0
377 #define ADC_R1_D(x)                              (((uint32_t)(((uint32_t)(x))<<ADC_R1_D_SHIFT))&ADC_R1_D_MASK)
378 /* CFG Bit Fields */
379 #define ADC_CFG_ADICLK_MASK                      0x3u
380 #define ADC_CFG_ADICLK_SHIFT                     0
381 #define ADC_CFG_ADICLK(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADICLK_SHIFT))&ADC_CFG_ADICLK_MASK)
382 #define ADC_CFG_MODE_MASK                        0xCu
383 #define ADC_CFG_MODE_SHIFT                       2
384 #define ADC_CFG_MODE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_MODE_SHIFT))&ADC_CFG_MODE_MASK)
385 #define ADC_CFG_ADLSMP_MASK                      0x10u
386 #define ADC_CFG_ADLSMP_SHIFT                     4
387 #define ADC_CFG_ADIV_MASK                        0x60u
388 #define ADC_CFG_ADIV_SHIFT                       5
389 #define ADC_CFG_ADIV(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADIV_SHIFT))&ADC_CFG_ADIV_MASK)
390 #define ADC_CFG_ADLPC_MASK                       0x80u
391 #define ADC_CFG_ADLPC_SHIFT                      7
392 #define ADC_CFG_ADSTS_MASK                       0x300u
393 #define ADC_CFG_ADSTS_SHIFT                      8
394 #define ADC_CFG_ADSTS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADSTS_SHIFT))&ADC_CFG_ADSTS_MASK)
395 #define ADC_CFG_ADHSC_MASK                       0x400u
396 #define ADC_CFG_ADHSC_SHIFT                      10
397 #define ADC_CFG_REFSEL_MASK                      0x1800u
398 #define ADC_CFG_REFSEL_SHIFT                     11
399 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG_REFSEL_SHIFT))&ADC_CFG_REFSEL_MASK)
400 #define ADC_CFG_ADTRG_MASK                       0x2000u
401 #define ADC_CFG_ADTRG_SHIFT                      13
402 #define ADC_CFG_AVGS_MASK                        0xC000u
403 #define ADC_CFG_AVGS_SHIFT                       14
404 #define ADC_CFG_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_AVGS_SHIFT))&ADC_CFG_AVGS_MASK)
405 #define ADC_CFG_OVWREN_MASK                      0x10000u
406 #define ADC_CFG_OVWREN_SHIFT                     16
407 /* GC Bit Fields */
408 #define ADC_GC_ADACKEN_MASK                      0x1u
409 #define ADC_GC_ADACKEN_SHIFT                     0
410 #define ADC_GC_DMAEN_MASK                        0x2u
411 #define ADC_GC_DMAEN_SHIFT                       1
412 #define ADC_GC_ACREN_MASK                        0x4u
413 #define ADC_GC_ACREN_SHIFT                       2
414 #define ADC_GC_ACFGT_MASK                        0x8u
415 #define ADC_GC_ACFGT_SHIFT                       3
416 #define ADC_GC_ACFE_MASK                         0x10u
417 #define ADC_GC_ACFE_SHIFT                        4
418 #define ADC_GC_AVGE_MASK                         0x20u
419 #define ADC_GC_AVGE_SHIFT                        5
420 #define ADC_GC_ADCO_MASK                         0x40u
421 #define ADC_GC_ADCO_SHIFT                        6
422 #define ADC_GC_CAL_MASK                          0x80u
423 #define ADC_GC_CAL_SHIFT                         7
424 /* GS Bit Fields */
425 #define ADC_GS_ADACT_MASK                        0x1u
426 #define ADC_GS_ADACT_SHIFT                       0
427 #define ADC_GS_CALF_MASK                         0x2u
428 #define ADC_GS_CALF_SHIFT                        1
429 #define ADC_GS_AWKST_MASK                        0x4u
430 #define ADC_GS_AWKST_SHIFT                       2
431 /* CV Bit Fields */
432 #define ADC_CV_CV1_MASK                          0xFFFu
433 #define ADC_CV_CV1_SHIFT                         0
434 #define ADC_CV_CV1(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV1_SHIFT))&ADC_CV_CV1_MASK)
435 #define ADC_CV_CV2_MASK                          0xFFF0000u
436 #define ADC_CV_CV2_SHIFT                         16
437 #define ADC_CV_CV2(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV2_SHIFT))&ADC_CV_CV2_MASK)
438 /* OFS Bit Fields */
439 #define ADC_OFS_OFS_MASK                         0xFFFu
440 #define ADC_OFS_OFS_SHIFT                        0
441 #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
442 #define ADC_OFS_SIGN_MASK                        0x1000u
443 #define ADC_OFS_SIGN_SHIFT                       12
444 /* CAL Bit Fields */
445 #define ADC_CAL_CAL_CODE_MASK                    0xFu
446 #define ADC_CAL_CAL_CODE_SHIFT                   0
447 #define ADC_CAL_CAL_CODE(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CAL_CAL_CODE_SHIFT))&ADC_CAL_CAL_CODE_MASK)
448 
449 /*!
450  * @}
451  */ /* end of group ADC_Register_Masks */
452 
453 /* ADC - Peripheral instance base addresses */
454 /** Peripheral ADC1 base address */
455 #define ADC1_BASE                                (0x42280000u)
456 /** Peripheral ADC1 base pointer */
457 #define ADC1                                     ((ADC_Type *)ADC1_BASE)
458 #define ADC1_BASE_PTR                            (ADC1)
459 /** Peripheral ADC2 base address */
460 #define ADC2_BASE                                (0x42284000u)
461 /** Peripheral ADC2 base pointer */
462 #define ADC2                                     ((ADC_Type *)ADC2_BASE)
463 #define ADC2_BASE_PTR                            (ADC2)
464 /** Array initializer of ADC peripheral base addresses */
465 #define ADC_BASE_ADDRS                           { ADC1_BASE, ADC2_BASE }
466 /** Array initializer of ADC peripheral base pointers */
467 #define ADC_BASE_PTRS                            { ADC1, ADC2 }
468 /** Interrupt vectors for the ADC peripheral type */
469 #define ADC_IRQS                                 { ADC1_IRQn, ADC2_IRQn }
470 
471 /* ----------------------------------------------------------------------------
472    -- ADC - Register accessor macros
473    ---------------------------------------------------------------------------- */
474 
475 /*!
476  * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
477  * @{
478  */
479 
480 /* ADC - Register instance definitions */
481 /* ADC1 */
482 #define ADC1_HC0                                 ADC_HC0_REG(ADC1_BASE_PTR)
483 #define ADC1_HC1                                 ADC_HC1_REG(ADC1_BASE_PTR)
484 #define ADC1_HS                                  ADC_HS_REG(ADC1_BASE_PTR)
485 #define ADC1_R0                                  ADC_R0_REG(ADC1_BASE_PTR)
486 #define ADC1_R1                                  ADC_R1_REG(ADC1_BASE_PTR)
487 #define ADC1_CFG                                 ADC_CFG_REG(ADC1_BASE_PTR)
488 #define ADC1_GC                                  ADC_GC_REG(ADC1_BASE_PTR)
489 #define ADC1_GS                                  ADC_GS_REG(ADC1_BASE_PTR)
490 #define ADC1_CV                                  ADC_CV_REG(ADC1_BASE_PTR)
491 #define ADC1_OFS                                 ADC_OFS_REG(ADC1_BASE_PTR)
492 #define ADC1_CAL                                 ADC_CAL_REG(ADC1_BASE_PTR)
493 /* ADC2 */
494 #define ADC2_HC0                                 ADC_HC0_REG(ADC2_BASE_PTR)
495 #define ADC2_HC1                                 ADC_HC1_REG(ADC2_BASE_PTR)
496 #define ADC2_HS                                  ADC_HS_REG(ADC2_BASE_PTR)
497 #define ADC2_R0                                  ADC_R0_REG(ADC2_BASE_PTR)
498 #define ADC2_R1                                  ADC_R1_REG(ADC2_BASE_PTR)
499 #define ADC2_CFG                                 ADC_CFG_REG(ADC2_BASE_PTR)
500 #define ADC2_GC                                  ADC_GC_REG(ADC2_BASE_PTR)
501 #define ADC2_GS                                  ADC_GS_REG(ADC2_BASE_PTR)
502 #define ADC2_CV                                  ADC_CV_REG(ADC2_BASE_PTR)
503 #define ADC2_OFS                                 ADC_OFS_REG(ADC2_BASE_PTR)
504 #define ADC2_CAL                                 ADC_CAL_REG(ADC2_BASE_PTR)
505 
506 /*!
507  * @}
508  */ /* end of group ADC_Register_Accessor_Macros */
509 
510 /*!
511  * @}
512  */ /* end of group ADC_Peripheral */
513 
514 /* ----------------------------------------------------------------------------
515    -- AFE Peripheral Access Layer
516    ---------------------------------------------------------------------------- */
517 
518 /*!
519  * @addtogroup AFE_Peripheral_Access_Layer AFE Peripheral Access Layer
520  * @{
521  */
522 
523 /** AFE - Register Layout Typedef */
524 typedef struct {
525   __I   uint32_t BLOCK_ID;                               /**< , offset: 0x0 */
526   __IO  uint32_t PDBUF;                                  /**< Power Down Buffers, offset: 0x4 */
527   __IO  uint32_t SWRST;                                  /**< Software Reset, offset: 0x8 */
528   uint8_t RESERVED_0[12];
529   __IO  uint32_t BGREG;                                  /**< Band Gap, offset: 0x18 */
530   uint8_t RESERVED_1[996];
531   __IO  uint32_t ACCESSAR_ID;                            /**< Accessar ID, offset: 0x400 */
532   __IO  uint32_t PDADC;                                  /**< Power Down ADC, offset: 0x404 */
533   __IO  uint32_t PDSARH;                                 /**< Power Down SAR High, offset: 0x408 */
534   __IO  uint32_t PDSARL;                                 /**< Power Down SAR Low, offset: 0x40C */
535   __IO  uint32_t PDADCRFH;                               /**< Power Down ADC Ref. High, offset: 0x410 */
536   __IO  uint32_t PDADCRFL;                               /**< Power Down ADC Ref. Low, offset: 0x414 */
537   uint8_t RESERVED_2[4];
538   __IO  uint32_t ADCGN;                                  /**< ADC Gain, offset: 0x41C */
539   uint8_t RESERVED_3[20];
540   __IO  uint32_t REFTRIML;                               /**< ADC Ref Trim Low, offset: 0x434 */
541   __IO  uint32_t REFTRIMH;                               /**< ADC Ref Trim High, offset: 0x438 */
542   uint8_t RESERVED_4[16];
543   __IO  uint32_t DACAMP;                                 /**< Clamp DAC Trim, offset: 0x44C */
544   uint8_t RESERVED_5[4];
545   __IO  uint32_t CLMPDAT;                                /**< Clamp DAC Data, offset: 0x454 */
546   __IO  uint32_t CLMPAMP;                                /**< Clamp DAC Control, offset: 0x458 */
547   __IO  uint32_t CLAMP;                                  /**< Clamp Control, offset: 0x45C */
548   __IO  uint32_t INPBUF;                                 /**< Input Buffer, offset: 0x460 */
549   __IO  uint32_t INPFLT;                                 /**< Analog Input Filter, offset: 0x464 */
550   __IO  uint32_t ADCDGN;                                 /**< ADC Digital Gain, offset: 0x468 */
551   __IO  uint32_t OFFDRV;                                 /**< Off-Chip Drive, offset: 0x46C */
552   __IO  uint32_t INPCONFIG;                              /**< VADC INPUT CONFIG, offset: 0x470 */
553   __IO  uint32_t PROGDELAY;                              /**< VADC PROG DELAY, offset: 0x474 */
554   __IO  uint32_t ADCOMT;                                 /**< ADC COMPARATOR TIMING, offset: 0x478 */
555   __IO  uint32_t ALGDELAY;                               /**< ALGORITHM DELAY, offset: 0x47C */
556   uint8_t RESERVED_6[896];
557   __I   uint32_t ACC_ID;                                 /**< Acc ID, offset: 0x800 */
558   __IO  uint32_t ACCSTA;                                 /**< ACC STATUS, offset: 0x804 */
559   __IO  uint32_t ACCNOSLI;                               /**< ACC NUMBER OF SLICE, offset: 0x808 */
560   __IO  uint32_t ACCCALCON;                              /**< ACC CALIBRATE CONTROL, offset: 0x80C */
561   __IO  uint32_t BWEWRICTRL;                             /**< ACC BWE WRITE CONTROL, offset: 0x810 */
562   __IO  uint32_t SELSLI;                                 /**< ACC SELECT SLICE, offset: 0x814 */
563   __IO  uint32_t SELBYT;                                 /**< ACC SELECT BYTE, offset: 0x818 */
564   uint8_t RESERVED_7[4];
565   __IO  uint32_t REDVAL;                                 /**< ACC READ VALUE, offset: 0x820 */
566   __IO  uint32_t WRIBYT;                                 /**< ACC WRITE BYTE, offset: 0x824 */
567 } AFE_Type, *AFE_MemMapPtr;
568 
569 /* ----------------------------------------------------------------------------
570    -- AFE - Register accessor macros
571    ---------------------------------------------------------------------------- */
572 
573 /*!
574  * @addtogroup AFE_Register_Accessor_Macros AFE - Register accessor macros
575  * @{
576  */
577 
578 /* AFE - Register accessors */
579 #define AFE_BLOCK_ID_REG(base)                   ((base)->BLOCK_ID)
580 #define AFE_PDBUF_REG(base)                      ((base)->PDBUF)
581 #define AFE_SWRST_REG(base)                      ((base)->SWRST)
582 #define AFE_BGREG_REG(base)                      ((base)->BGREG)
583 #define AFE_ACCESSAR_ID_REG(base)                ((base)->ACCESSAR_ID)
584 #define AFE_PDADC_REG(base)                      ((base)->PDADC)
585 #define AFE_PDSARH_REG(base)                     ((base)->PDSARH)
586 #define AFE_PDSARL_REG(base)                     ((base)->PDSARL)
587 #define AFE_PDADCRFH_REG(base)                   ((base)->PDADCRFH)
588 #define AFE_PDADCRFL_REG(base)                   ((base)->PDADCRFL)
589 #define AFE_ADCGN_REG(base)                      ((base)->ADCGN)
590 #define AFE_REFTRIML_REG(base)                   ((base)->REFTRIML)
591 #define AFE_REFTRIMH_REG(base)                   ((base)->REFTRIMH)
592 #define AFE_DACAMP_REG(base)                     ((base)->DACAMP)
593 #define AFE_CLMPDAT_REG(base)                    ((base)->CLMPDAT)
594 #define AFE_CLMPAMP_REG(base)                    ((base)->CLMPAMP)
595 #define AFE_CLAMP_REG(base)                      ((base)->CLAMP)
596 #define AFE_INPBUF_REG(base)                     ((base)->INPBUF)
597 #define AFE_INPFLT_REG(base)                     ((base)->INPFLT)
598 #define AFE_ADCDGN_REG(base)                     ((base)->ADCDGN)
599 #define AFE_OFFDRV_REG(base)                     ((base)->OFFDRV)
600 #define AFE_INPCONFIG_REG(base)                  ((base)->INPCONFIG)
601 #define AFE_PROGDELAY_REG(base)                  ((base)->PROGDELAY)
602 #define AFE_ADCOMT_REG(base)                     ((base)->ADCOMT)
603 #define AFE_ALGDELAY_REG(base)                   ((base)->ALGDELAY)
604 #define AFE_ACC_ID_REG(base)                     ((base)->ACC_ID)
605 #define AFE_ACCSTA_REG(base)                     ((base)->ACCSTA)
606 #define AFE_ACCNOSLI_REG(base)                   ((base)->ACCNOSLI)
607 #define AFE_ACCCALCON_REG(base)                  ((base)->ACCCALCON)
608 #define AFE_BWEWRICTRL_REG(base)                 ((base)->BWEWRICTRL)
609 #define AFE_SELSLI_REG(base)                     ((base)->SELSLI)
610 #define AFE_SELBYT_REG(base)                     ((base)->SELBYT)
611 #define AFE_REDVAL_REG(base)                     ((base)->REDVAL)
612 #define AFE_WRIBYT_REG(base)                     ((base)->WRIBYT)
613 
614 /*!
615  * @}
616  */ /* end of group AFE_Register_Accessor_Macros */
617 
618 /* ----------------------------------------------------------------------------
619    -- AFE Register Masks
620    ---------------------------------------------------------------------------- */
621 
622 /*!
623  * @addtogroup AFE_Register_Masks AFE Register Masks
624  * @{
625  */
626 
627 /* BLOCK_ID Bit Fields */
628 #define AFE_BLOCK_ID_BLOCK_ID_MASK               0xFFu
629 #define AFE_BLOCK_ID_BLOCK_ID_SHIFT              0
630 #define AFE_BLOCK_ID_BLOCK_ID(x)                 (((uint32_t)(((uint32_t)(x))<<AFE_BLOCK_ID_BLOCK_ID_SHIFT))&AFE_BLOCK_ID_BLOCK_ID_MASK)
631 /* PDBUF Bit Fields */
632 #define AFE_PDBUF_ACAFE_PD_N_MASK                0x1u
633 #define AFE_PDBUF_ACAFE_PD_N_SHIFT               0
634 #define AFE_PDBUF_BGR_BGR_PD_N_MASK              0x2u
635 #define AFE_PDBUF_BGR_BGR_PD_N_SHIFT             1
636 #define AFE_PDBUF_BGR_PD_N_MASK                  0x4u
637 #define AFE_PDBUF_BGR_PD_N_SHIFT                 2
638 #define AFE_PDBUF_TESTBUFFERS_PD_N_MASK          0x18u
639 #define AFE_PDBUF_TESTBUFFERS_PD_N_SHIFT         3
640 #define AFE_PDBUF_TESTBUFFERS_PD_N(x)            (((uint32_t)(((uint32_t)(x))<<AFE_PDBUF_TESTBUFFERS_PD_N_SHIFT))&AFE_PDBUF_TESTBUFFERS_PD_N_MASK)
641 /* SWRST Bit Fields */
642 #define AFE_SWRST_SYSCLK_SW_RST_N_MASK           0x1u
643 #define AFE_SWRST_SYSCLK_SW_RST_N_SHIFT          0
644 #define AFE_SWRST_ADC_PROC_CLK_SW_RST_N_MASK     0x2u
645 #define AFE_SWRST_ADC_PROC_CLK_SW_RST_N_SHIFT    1
646 #define AFE_SWRST_ACAFE_SW_RST_N_MASK            0x4u
647 #define AFE_SWRST_ACAFE_SW_RST_N_SHIFT           2
648 /* BGREG Bit Fields */
649 #define AFE_BGREG_BGR_TRIMLEVEL_MASK             0xFu
650 #define AFE_BGREG_BGR_TRIMLEVEL_SHIFT            0
651 #define AFE_BGREG_BGR_TRIMLEVEL(x)               (((uint32_t)(((uint32_t)(x))<<AFE_BGREG_BGR_TRIMLEVEL_SHIFT))&AFE_BGREG_BGR_TRIMLEVEL_MASK)
652 #define AFE_BGREG_BGR_EN_EXT_CURRENT_MASK        0x10u
653 #define AFE_BGREG_BGR_EN_EXT_CURRENT_SHIFT       4
654 /* ACCESSAR_ID Bit Fields */
655 #define AFE_ACCESSAR_ID_ACCESSAR_ID_MASK         0xFFu
656 #define AFE_ACCESSAR_ID_ACCESSAR_ID_SHIFT        0
657 #define AFE_ACCESSAR_ID_ACCESSAR_ID(x)           (((uint32_t)(((uint32_t)(x))<<AFE_ACCESSAR_ID_ACCESSAR_ID_SHIFT))&AFE_ACCESSAR_ID_ACCESSAR_ID_MASK)
658 /* PDADC Bit Fields */
659 #define AFE_PDADC_ACCESSAR_PD_N_MASK             0x1u
660 #define AFE_PDADC_ACCESSAR_PD_N_SHIFT            0
661 #define AFE_PDADC_DLYLOOP_PD_N_MASK              0x2u
662 #define AFE_PDADC_DLYLOOP_PD_N_SHIFT             1
663 #define AFE_PDADC_ADC_IREF_PD_N_MASK             0x4u
664 #define AFE_PDADC_ADC_IREF_PD_N_SHIFT            2
665 #define AFE_PDADC_CLAMP_PD_N_MASK                0x8u
666 #define AFE_PDADC_CLAMP_PD_N_SHIFT               3
667 /* PDSARH Bit Fields */
668 #define AFE_PDSARH_ADC_PD_N_MASK                 0x1u
669 #define AFE_PDSARH_ADC_PD_N_SHIFT                0
670 /* PDSARL Bit Fields */
671 #define AFE_PDSARL_ADC_PD_N_MASK                 0xFFu
672 #define AFE_PDSARL_ADC_PD_N_SHIFT                0
673 #define AFE_PDSARL_ADC_PD_N(x)                   (((uint32_t)(((uint32_t)(x))<<AFE_PDSARL_ADC_PD_N_SHIFT))&AFE_PDSARL_ADC_PD_N_MASK)
674 /* PDADCRFH Bit Fields */
675 #define AFE_PDADCRFH_ADCREF_REFBUFSLICE_PD_N_MASK 0x1u
676 #define AFE_PDADCRFH_ADCREF_REFBUFSLICE_PD_N_SHIFT 0
677 /* PDADCRFL Bit Fields */
678 #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_MASK 0xFFu
679 #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_SHIFT 0
680 #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N(x)  (((uint32_t)(((uint32_t)(x))<<AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_SHIFT))&AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_MASK)
681 /* ADCGN Bit Fields */
682 #define AFE_ADCGN_ADC_GAIN_MASK                  0xFu
683 #define AFE_ADCGN_ADC_GAIN_SHIFT                 0
684 #define AFE_ADCGN_ADC_GAIN(x)                    (((uint32_t)(((uint32_t)(x))<<AFE_ADCGN_ADC_GAIN_SHIFT))&AFE_ADCGN_ADC_GAIN_MASK)
685 /* REFTRIML Bit Fields */
686 #define AFE_REFTRIML_ADCREF_REFTRIM08_MASK       0x3u
687 #define AFE_REFTRIML_ADCREF_REFTRIM08_SHIFT      0
688 #define AFE_REFTRIML_ADCREF_REFTRIM08(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM08_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM08_MASK)
689 #define AFE_REFTRIML_ADCREF_REFTRIM04_MASK       0xCu
690 #define AFE_REFTRIML_ADCREF_REFTRIM04_SHIFT      2
691 #define AFE_REFTRIML_ADCREF_REFTRIM04(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM04_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM04_MASK)
692 #define AFE_REFTRIML_ADCREF_REFTRIM02_MASK       0x30u
693 #define AFE_REFTRIML_ADCREF_REFTRIM02_SHIFT      4
694 #define AFE_REFTRIML_ADCREF_REFTRIM02(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM02_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM02_MASK)
695 #define AFE_REFTRIML_ADCREF_REFTRIMOP_MASK       0xC0u
696 #define AFE_REFTRIML_ADCREF_REFTRIMOP_SHIFT      6
697 #define AFE_REFTRIML_ADCREF_REFTRIMOP(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIMOP_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIMOP_MASK)
698 /* REFTRIMH Bit Fields */
699 #define AFE_REFTRIMH_ADCREF_REFTRIM_MASK         0xFu
700 #define AFE_REFTRIMH_ADCREF_REFTRIM_SHIFT        0
701 #define AFE_REFTRIMH_ADCREF_REFTRIM(x)           (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIMH_ADCREF_REFTRIM_SHIFT))&AFE_REFTRIMH_ADCREF_REFTRIM_MASK)
702 /* DACAMP Bit Fields */
703 #define AFE_DACAMP_CLAMPDAC_TRIM_MASK            0xFu
704 #define AFE_DACAMP_CLAMPDAC_TRIM_SHIFT           0
705 #define AFE_DACAMP_CLAMPDAC_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<AFE_DACAMP_CLAMPDAC_TRIM_SHIFT))&AFE_DACAMP_CLAMPDAC_TRIM_MASK)
706 /* CLMPDAT Bit Fields */
707 #define AFE_CLMPDAT_CLAMPDAC_DATA_MASK           0xFFu
708 #define AFE_CLMPDAT_CLAMPDAC_DATA_SHIFT          0
709 #define AFE_CLMPDAT_CLAMPDAC_DATA(x)             (((uint32_t)(((uint32_t)(x))<<AFE_CLMPDAT_CLAMPDAC_DATA_SHIFT))&AFE_CLMPDAT_CLAMPDAC_DATA_MASK)
710 /* CLMPAMP Bit Fields */
711 #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_MASK     0x7u
712 #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_SHIFT    0
713 #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA(x)       (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_SHIFT))&AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_MASK)
714 #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_MASK    0x18u
715 #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_SHIFT   3
716 #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT(x)      (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_SHIFT))&AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_MASK)
717 #define AFE_CLMPAMP_CLAMP_UPDN_REG_OVERRIDE_MASK 0x20u
718 #define AFE_CLMPAMP_CLAMP_UPDN_REG_OVERRIDE_SHIFT 5
719 #define AFE_CLMPAMP_CLAMP_CURRENT_REG_OVERRIDE_MASK 0x40u
720 #define AFE_CLMPAMP_CLAMP_CURRENT_REG_OVERRIDE_SHIFT 6
721 /* CLAMP Bit Fields */
722 #define AFE_CLAMP_NCLAMP_POWERSAVE_MASK          0x1u
723 #define AFE_CLAMP_NCLAMP_POWERSAVE_SHIFT         0
724 #define AFE_CLAMP_CLAMP_VN_MASK                  0x2u
725 #define AFE_CLAMP_CLAMP_VN_SHIFT                 1
726 #define AFE_CLAMP_CLAMP_IPEN_REG_MASK            0x4u
727 #define AFE_CLAMP_CLAMP_IPEN_REG_SHIFT           2
728 #define AFE_CLAMP_CLAMP_INEN_REG_MASK            0x8u
729 #define AFE_CLAMP_CLAMP_INEN_REG_SHIFT           3
730 #define AFE_CLAMP_CLAMP_LOWCURRMODE_MASK         0x10u
731 #define AFE_CLAMP_CLAMP_LOWCURRMODE_SHIFT        4
732 #define AFE_CLAMP_DIV_PROC_CLK_MASK              0x20u
733 #define AFE_CLAMP_DIV_PROC_CLK_SHIFT             5
734 #define AFE_CLAMP_CLAMP_UP_DOWN_POLARITY_MASK    0x40u
735 #define AFE_CLAMP_CLAMP_UP_DOWN_POLARITY_SHIFT   6
736 #define AFE_CLAMP_CLAMP_PWN_MODE_MASK            0x80u
737 #define AFE_CLAMP_CLAMP_PWN_MODE_SHIFT           7
738 /* INPBUF Bit Fields */
739 #define AFE_INPBUF_BUFF_EN_RI_MASK               0x1u
740 #define AFE_INPBUF_BUFF_EN_RI_SHIFT              0
741 #define AFE_INPBUF_BUFF_EN_DI_MASK               0x2u
742 #define AFE_INPBUF_BUFF_EN_DI_SHIFT              1
743 #define AFE_INPBUF_BUFF_EN_CM_MASK               0x4u
744 #define AFE_INPBUF_BUFF_EN_CM_SHIFT              2
745 #define AFE_INPBUF_MUX_BUFFER_BP_EN_MASK         0x8u
746 #define AFE_INPBUF_MUX_BUFFER_BP_EN_SHIFT        3
747 #define AFE_INPBUF_MUX_BUFFER_15M_EN_MASK        0x10u
748 #define AFE_INPBUF_MUX_BUFFER_15M_EN_SHIFT       4
749 #define AFE_INPBUF_MUX_CLAMPEN_MASK              0x20u
750 #define AFE_INPBUF_MUX_CLAMPEN_SHIFT             5
751 /* INPFLT Bit Fields */
752 #define AFE_INPFLT_MUX_PDCURRENTMIRROR_MASK      0x1u
753 #define AFE_INPFLT_MUX_PDCURRENTMIRROR_SHIFT     0
754 #define AFE_INPFLT_MUX_FILTER_15M_EN_MASK        0x2u
755 #define AFE_INPFLT_MUX_FILTER_15M_EN_SHIFT       1
756 #define AFE_INPFLT_MUX_FILTERBYPASS_MASK         0x4u
757 #define AFE_INPFLT_MUX_FILTERBYPASS_SHIFT        2
758 /* ADCDGN Bit Fields */
759 #define AFE_ADCDGN_ADC_DIGITAL_GAIN_MASK         0x3Fu
760 #define AFE_ADCDGN_ADC_DIGITAL_GAIN_SHIFT        0
761 #define AFE_ADCDGN_ADC_DIGITAL_GAIN(x)           (((uint32_t)(((uint32_t)(x))<<AFE_ADCDGN_ADC_DIGITAL_GAIN_SHIFT))&AFE_ADCDGN_ADC_DIGITAL_GAIN_MASK)
762 #define AFE_ADCDGN_ADC_DIGITAL_GAIN_BYPASS_MASK  0x40u
763 #define AFE_ADCDGN_ADC_DIGITAL_GAIN_BYPASS_SHIFT 6
764 /* OFFDRV Bit Fields */
765 #define AFE_OFFDRV_ENOFFCHIPDRIVE_MASK           0x3u
766 #define AFE_OFFDRV_ENOFFCHIPDRIVE_SHIFT          0
767 #define AFE_OFFDRV_ENOFFCHIPDRIVE(x)             (((uint32_t)(((uint32_t)(x))<<AFE_OFFDRV_ENOFFCHIPDRIVE_SHIFT))&AFE_OFFDRV_ENOFFCHIPDRIVE_MASK)
768 #define AFE_OFFDRV_SH_TRIM_MASK                  0xCu
769 #define AFE_OFFDRV_SH_TRIM_SHIFT                 2
770 #define AFE_OFFDRV_SH_TRIM(x)                    (((uint32_t)(((uint32_t)(x))<<AFE_OFFDRV_SH_TRIM_SHIFT))&AFE_OFFDRV_SH_TRIM_MASK)
771 /* INPCONFIG Bit Fields */
772 #define AFE_INPCONFIG_INPUT_PULLDOWN_EN_MASK     0xFu
773 #define AFE_INPCONFIG_INPUT_PULLDOWN_EN_SHIFT    0
774 #define AFE_INPCONFIG_INPUT_PULLDOWN_EN(x)       (((uint32_t)(((uint32_t)(x))<<AFE_INPCONFIG_INPUT_PULLDOWN_EN_SHIFT))&AFE_INPCONFIG_INPUT_PULLDOWN_EN_MASK)
775 #define AFE_INPCONFIG_MUX_ENLF_MASK              0xF0u
776 #define AFE_INPCONFIG_MUX_ENLF_SHIFT             4
777 #define AFE_INPCONFIG_MUX_ENLF(x)                (((uint32_t)(((uint32_t)(x))<<AFE_INPCONFIG_MUX_ENLF_SHIFT))&AFE_INPCONFIG_MUX_ENLF_MASK)
778 /* PROGDELAY Bit Fields */
779 #define AFE_PROGDELAY_PROG_DELAY_MASK            0xFFu
780 #define AFE_PROGDELAY_PROG_DELAY_SHIFT           0
781 #define AFE_PROGDELAY_PROG_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<AFE_PROGDELAY_PROG_DELAY_SHIFT))&AFE_PROGDELAY_PROG_DELAY_MASK)
782 /* ADCOMT Bit Fields */
783 #define AFE_ADCOMT_OVERRIDE_MASK                 0x1u
784 #define AFE_ADCOMT_OVERRIDE_SHIFT                0
785 #define AFE_ADCOMT_WAIT_TIME_MASK                0x3Eu
786 #define AFE_ADCOMT_WAIT_TIME_SHIFT               1
787 #define AFE_ADCOMT_WAIT_TIME(x)                  (((uint32_t)(((uint32_t)(x))<<AFE_ADCOMT_WAIT_TIME_SHIFT))&AFE_ADCOMT_WAIT_TIME_MASK)
788 #define AFE_ADCOMT_MEASURE_TIMING_MASK           0xC0u
789 #define AFE_ADCOMT_MEASURE_TIMING_SHIFT          6
790 #define AFE_ADCOMT_MEASURE_TIMING(x)             (((uint32_t)(((uint32_t)(x))<<AFE_ADCOMT_MEASURE_TIMING_SHIFT))&AFE_ADCOMT_MEASURE_TIMING_MASK)
791 /* ALGDELAY Bit Fields */
792 #define AFE_ALGDELAY_ALGORITHM_DELAY_MASK        0xFFu
793 #define AFE_ALGDELAY_ALGORITHM_DELAY_SHIFT       0
794 #define AFE_ALGDELAY_ALGORITHM_DELAY(x)          (((uint32_t)(((uint32_t)(x))<<AFE_ALGDELAY_ALGORITHM_DELAY_SHIFT))&AFE_ALGDELAY_ALGORITHM_DELAY_MASK)
795 /* ACC_ID Bit Fields */
796 #define AFE_ACC_ID_BLOCK_ID_MASK                 0xFFu
797 #define AFE_ACC_ID_BLOCK_ID_SHIFT                0
798 #define AFE_ACC_ID_BLOCK_ID(x)                   (((uint32_t)(((uint32_t)(x))<<AFE_ACC_ID_BLOCK_ID_SHIFT))&AFE_ACC_ID_BLOCK_ID_MASK)
799 /* ACCSTA Bit Fields */
800 #define AFE_ACCSTA_STATUS_MASK                   0x1Fu
801 #define AFE_ACCSTA_STATUS_SHIFT                  0
802 #define AFE_ACCSTA_STATUS(x)                     (((uint32_t)(((uint32_t)(x))<<AFE_ACCSTA_STATUS_SHIFT))&AFE_ACCSTA_STATUS_MASK)
803 /* ACCNOSLI Bit Fields */
804 #define AFE_ACCNOSLI_NO_OF_SLICES_MASK           0x3Fu
805 #define AFE_ACCNOSLI_NO_OF_SLICES_SHIFT          0
806 #define AFE_ACCNOSLI_NO_OF_SLICES(x)             (((uint32_t)(((uint32_t)(x))<<AFE_ACCNOSLI_NO_OF_SLICES_SHIFT))&AFE_ACCNOSLI_NO_OF_SLICES_MASK)
807 /* ACCCALCON Bit Fields */
808 #define AFE_ACCCALCON_CALIBRATE_START_MASK       0x1u
809 #define AFE_ACCCALCON_CALIBRATE_START_SHIFT      0
810 #define AFE_ACCCALCON_BYPASS_MASK                0x2u
811 #define AFE_ACCCALCON_BYPASS_SHIFT               1
812 #define AFE_ACCCALCON_BYPASS_CALIB_MASK          0x4u
813 #define AFE_ACCCALCON_BYPASS_CALIB_SHIFT         2
814 #define AFE_ACCCALCON_OFFSET_COMP_EN_MASK        0x8u
815 #define AFE_ACCCALCON_OFFSET_COMP_EN_SHIFT       3
816 #define AFE_ACCCALCON_ANA_OFFSET_COMP_EN_MASK    0x10u
817 #define AFE_ACCCALCON_ANA_OFFSET_COMP_EN_SHIFT   4
818 /* BWEWRICTRL Bit Fields */
819 #define AFE_BWEWRICTRL_BWE_CTRL_MASK             0x3u
820 #define AFE_BWEWRICTRL_BWE_CTRL_SHIFT            0
821 #define AFE_BWEWRICTRL_BWE_CTRL(x)               (((uint32_t)(((uint32_t)(x))<<AFE_BWEWRICTRL_BWE_CTRL_SHIFT))&AFE_BWEWRICTRL_BWE_CTRL_MASK)
822 #define AFE_BWEWRICTRL_BWE_WRITE_CTRL_MASK       0x4u
823 #define AFE_BWEWRICTRL_BWE_WRITE_CTRL_SHIFT      2
824 /* SELSLI Bit Fields */
825 #define AFE_SELSLI_SELECT_SLICE_MASK             0xFFu
826 #define AFE_SELSLI_SELECT_SLICE_SHIFT            0
827 #define AFE_SELSLI_SELECT_SLICE(x)               (((uint32_t)(((uint32_t)(x))<<AFE_SELSLI_SELECT_SLICE_SHIFT))&AFE_SELSLI_SELECT_SLICE_MASK)
828 /* SELBYT Bit Fields */
829 #define AFE_SELBYT_SELECT_BYTE_MASK              0xFFu
830 #define AFE_SELBYT_SELECT_BYTE_SHIFT             0
831 #define AFE_SELBYT_SELECT_BYTE(x)                (((uint32_t)(((uint32_t)(x))<<AFE_SELBYT_SELECT_BYTE_SHIFT))&AFE_SELBYT_SELECT_BYTE_MASK)
832 /* REDVAL Bit Fields */
833 #define AFE_REDVAL_READ_VALUE_MASK               0xFFu
834 #define AFE_REDVAL_READ_VALUE_SHIFT              0
835 #define AFE_REDVAL_READ_VALUE(x)                 (((uint32_t)(((uint32_t)(x))<<AFE_REDVAL_READ_VALUE_SHIFT))&AFE_REDVAL_READ_VALUE_MASK)
836 /* WRIBYT Bit Fields */
837 #define AFE_WRIBYT_WRITE_BYTE_MASK               0xFFu
838 #define AFE_WRIBYT_WRITE_BYTE_SHIFT              0
839 #define AFE_WRIBYT_WRITE_BYTE(x)                 (((uint32_t)(((uint32_t)(x))<<AFE_WRIBYT_WRITE_BYTE_SHIFT))&AFE_WRIBYT_WRITE_BYTE_MASK)
840 
841 /*!
842  * @}
843  */ /* end of group AFE_Register_Masks */
844 
845 /* AFE - Peripheral instance base addresses */
846 /** Peripheral AFE base address */
847 #define AFE_BASE                                 (0x42228000u)
848 /** Peripheral AFE base pointer */
849 #define AFE                                      ((AFE_Type *)AFE_BASE)
850 #define AFE_BASE_PTR                             (AFE)
851 /** Array initializer of AFE peripheral base addresses */
852 #define AFE_BASE_ADDRS                           { AFE_BASE }
853 /** Array initializer of AFE peripheral base pointers */
854 #define AFE_BASE_PTRS                            { AFE }
855 
856 /* ----------------------------------------------------------------------------
857    -- AFE - Register accessor macros
858    ---------------------------------------------------------------------------- */
859 
860 /*!
861  * @addtogroup AFE_Register_Accessor_Macros AFE - Register accessor macros
862  * @{
863  */
864 
865 /* AFE - Register instance definitions */
866 /* AFE */
867 #define AFE_BLOCK_ID                             AFE_BLOCK_ID_REG(AFE_BASE_PTR)
868 #define AFE_PDBUF                                AFE_PDBUF_REG(AFE_BASE_PTR)
869 #define AFE_SWRST                                AFE_SWRST_REG(AFE_BASE_PTR)
870 #define AFE_BGREG                                AFE_BGREG_REG(AFE_BASE_PTR)
871 #define AFE_ACCESSAR_ID                          AFE_ACCESSAR_ID_REG(AFE_BASE_PTR)
872 #define AFE_PDADC                                AFE_PDADC_REG(AFE_BASE_PTR)
873 #define AFE_PDSARH                               AFE_PDSARH_REG(AFE_BASE_PTR)
874 #define AFE_PDSARL                               AFE_PDSARL_REG(AFE_BASE_PTR)
875 #define AFE_PDADCRFH                             AFE_PDADCRFH_REG(AFE_BASE_PTR)
876 #define AFE_PDADCRFL                             AFE_PDADCRFL_REG(AFE_BASE_PTR)
877 #define AFE_ADCGN                                AFE_ADCGN_REG(AFE_BASE_PTR)
878 #define AFE_REFTRIML                             AFE_REFTRIML_REG(AFE_BASE_PTR)
879 #define AFE_REFTRIMH                             AFE_REFTRIMH_REG(AFE_BASE_PTR)
880 #define AFE_DACAMP                               AFE_DACAMP_REG(AFE_BASE_PTR)
881 #define AFE_CLMPDAT                              AFE_CLMPDAT_REG(AFE_BASE_PTR)
882 #define AFE_CLMPAMP                              AFE_CLMPAMP_REG(AFE_BASE_PTR)
883 #define AFE_CLAMP                                AFE_CLAMP_REG(AFE_BASE_PTR)
884 #define AFE_INPBUF                               AFE_INPBUF_REG(AFE_BASE_PTR)
885 #define AFE_INPFLT                               AFE_INPFLT_REG(AFE_BASE_PTR)
886 #define AFE_ADCDGN                               AFE_ADCDGN_REG(AFE_BASE_PTR)
887 #define AFE_OFFDRV                               AFE_OFFDRV_REG(AFE_BASE_PTR)
888 #define AFE_INPCONFIG                            AFE_INPCONFIG_REG(AFE_BASE_PTR)
889 #define AFE_PROGDELAY                            AFE_PROGDELAY_REG(AFE_BASE_PTR)
890 #define AFE_ADCOMT                               AFE_ADCOMT_REG(AFE_BASE_PTR)
891 #define AFE_ALGDELAY                             AFE_ALGDELAY_REG(AFE_BASE_PTR)
892 #define AFE_ACC_ID                               AFE_ACC_ID_REG(AFE_BASE_PTR)
893 #define AFE_ACCSTA                               AFE_ACCSTA_REG(AFE_BASE_PTR)
894 #define AFE_ACCNOSLI                             AFE_ACCNOSLI_REG(AFE_BASE_PTR)
895 #define AFE_ACCCALCON                            AFE_ACCCALCON_REG(AFE_BASE_PTR)
896 #define AFE_BWEWRICTRL                           AFE_BWEWRICTRL_REG(AFE_BASE_PTR)
897 #define AFE_SELSLI                               AFE_SELSLI_REG(AFE_BASE_PTR)
898 #define AFE_SELBYT                               AFE_SELBYT_REG(AFE_BASE_PTR)
899 #define AFE_REDVAL                               AFE_REDVAL_REG(AFE_BASE_PTR)
900 #define AFE_WRIBYT                               AFE_WRIBYT_REG(AFE_BASE_PTR)
901 
902 /*!
903  * @}
904  */ /* end of group AFE_Register_Accessor_Macros */
905 
906 /*!
907  * @}
908  */ /* end of group AFE_Peripheral */
909 
910 /* ----------------------------------------------------------------------------
911    -- ASRC Peripheral Access Layer
912    ---------------------------------------------------------------------------- */
913 
914 /*!
915  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
916  * @{
917  */
918 
919 /** ASRC - Register Layout Typedef */
920 typedef struct {
921   __IO  uint32_t ASRCTR;                                 /**< ASRC Control Register, offset: 0x0 */
922   __IO  uint32_t ASRIER;                                 /**< ASRC Interrupt Enable Register, offset: 0x4 */
923   uint8_t RESERVED_0[4];
924   __IO  uint32_t ASRCNCR;                                /**< ASRC Channel Number Configuration Register, offset: 0xC */
925   __IO  uint32_t ASRCFG;                                 /**< ASRC Filter Configuration Status Register, offset: 0x10 */
926   __IO  uint32_t ASRCSR;                                 /**< ASRC Clock Source Register, offset: 0x14 */
927   __IO  uint32_t ASRCDR1;                                /**< ASRC Clock Divider Register 1, offset: 0x18 */
928   __IO  uint32_t ASRCDR2;                                /**< ASRC Clock Divider Register 2, offset: 0x1C */
929   __I   uint32_t ASRSTR;                                 /**< ASRC Status Register, offset: 0x20 */
930   uint8_t RESERVED_1[28];
931   __IO  uint32_t ASRPMn[5];                              /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
932   __IO  uint32_t ASRTFR1;                                /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
933   uint8_t RESERVED_2[4];
934   __IO  uint32_t ASRCCR;                                 /**< ASRC Channel Counter Register, offset: 0x5C */
935   struct {                                         /* offset: 0x60, array step: 0x-8 */
936   __O     uint32_t ASRDI;                                  /**< ASRC Data Input Register for Pair , array offset: 0x60, array step: 0x-8 */
937   __I     uint32_t ASRDO;                                  /**< ASRC Data Output Register for Pair , array offset: 0x64, array step: 0x-8 */
938  } ASRD[3];
939   uint8_t RESERVED_3[8];
940   __IO  uint32_t ASRIDRHA;                               /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
941   __IO  uint32_t ASRIDRLA;                               /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
942   __IO  uint32_t ASRIDRHB;                               /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
943   __IO  uint32_t ASRIDRLB;                               /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
944   __IO  uint32_t ASRIDRHC;                               /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
945   __IO  uint32_t ASRIDRLC;                               /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
946   __IO  uint32_t ASR76K;                                 /**< ASRC 76kHz Period in terms of ASRC processing clock, offset: 0x98 */
947   __IO  uint32_t ASR56K;                                 /**< ASRC 56kHz Period in terms of ASRC processing clock, offset: 0x9C */
948   __IO  uint32_t ASRMCRA;                                /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
949   __I   uint32_t ASRFSTA;                                /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
950   __IO  uint32_t ASRMCRB;                                /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
951   __I   uint32_t ASRFSTB;                                /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
952   __IO  uint32_t ASRMCRC;                                /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
953   __I   uint32_t ASRFSTC;                                /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
954   uint8_t RESERVED_4[8];
955   __IO  uint32_t ASRMCR1[3];                             /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x0 */
956 } ASRC_Type, *ASRC_MemMapPtr;
957 
958 /* ----------------------------------------------------------------------------
959    -- ASRC - Register accessor macros
960    ---------------------------------------------------------------------------- */
961 
962 /*!
963  * @addtogroup ASRC_Register_Accessor_Macros ASRC - Register accessor macros
964  * @{
965  */
966 
967 /* ASRC - Register accessors */
968 #define ASRC_ASRCTR_REG(base)                    ((base)->ASRCTR)
969 #define ASRC_ASRIER_REG(base)                    ((base)->ASRIER)
970 #define ASRC_ASRCNCR_REG(base)                   ((base)->ASRCNCR)
971 #define ASRC_ASRCFG_REG(base)                    ((base)->ASRCFG)
972 #define ASRC_ASRCSR_REG(base)                    ((base)->ASRCSR)
973 #define ASRC_ASRCDR1_REG(base)                   ((base)->ASRCDR1)
974 #define ASRC_ASRCDR2_REG(base)                   ((base)->ASRCDR2)
975 #define ASRC_ASRSTR_REG(base)                    ((base)->ASRSTR)
976 #define ASRC_ASRPMn_REG(base,index)              ((base)->ASRPMn[index])
977 #define ASRC_ASRTFR1_REG(base)                   ((base)->ASRTFR1)
978 #define ASRC_ASRCCR_REG(base)                    ((base)->ASRCCR)
979 #define ASRC_ASRDI_REG(base,index)               ((base)->ASRD[index].ASRDI)
980 #define ASRC_ASRDO_REG(base,index)               ((base)->ASRD[index].ASRDO)
981 #define ASRC_ASRIDRHA_REG(base)                  ((base)->ASRIDRHA)
982 #define ASRC_ASRIDRLA_REG(base)                  ((base)->ASRIDRLA)
983 #define ASRC_ASRIDRHB_REG(base)                  ((base)->ASRIDRHB)
984 #define ASRC_ASRIDRLB_REG(base)                  ((base)->ASRIDRLB)
985 #define ASRC_ASRIDRHC_REG(base)                  ((base)->ASRIDRHC)
986 #define ASRC_ASRIDRLC_REG(base)                  ((base)->ASRIDRLC)
987 #define ASRC_ASR76K_REG(base)                    ((base)->ASR76K)
988 #define ASRC_ASR56K_REG(base)                    ((base)->ASR56K)
989 #define ASRC_ASRMCRA_REG(base)                   ((base)->ASRMCRA)
990 #define ASRC_ASRFSTA_REG(base)                   ((base)->ASRFSTA)
991 #define ASRC_ASRMCRB_REG(base)                   ((base)->ASRMCRB)
992 #define ASRC_ASRFSTB_REG(base)                   ((base)->ASRFSTB)
993 #define ASRC_ASRMCRC_REG(base)                   ((base)->ASRMCRC)
994 #define ASRC_ASRFSTC_REG(base)                   ((base)->ASRFSTC)
995 #define ASRC_ASRMCR1_REG(base,index)             ((base)->ASRMCR1[index])
996 
997 /*!
998  * @}
999  */ /* end of group ASRC_Register_Accessor_Macros */
1000 
1001 /* ----------------------------------------------------------------------------
1002    -- ASRC Register Masks
1003    ---------------------------------------------------------------------------- */
1004 
1005 /*!
1006  * @addtogroup ASRC_Register_Masks ASRC Register Masks
1007  * @{
1008  */
1009 
1010 /* ASRCTR Bit Fields */
1011 #define ASRC_ASRCTR_ASRCEN_MASK                  0x1u
1012 #define ASRC_ASRCTR_ASRCEN_SHIFT                 0
1013 #define ASRC_ASRCTR_ASREA_MASK                   0x2u
1014 #define ASRC_ASRCTR_ASREA_SHIFT                  1
1015 #define ASRC_ASRCTR_ASREB_MASK                   0x4u
1016 #define ASRC_ASRCTR_ASREB_SHIFT                  2
1017 #define ASRC_ASRCTR_ASREC_MASK                   0x8u
1018 #define ASRC_ASRCTR_ASREC_SHIFT                  3
1019 #define ASRC_ASRCTR_SRST_MASK                    0x10u
1020 #define ASRC_ASRCTR_SRST_SHIFT                   4
1021 #define ASRC_ASRCTR_IDRA_MASK                    0x2000u
1022 #define ASRC_ASRCTR_IDRA_SHIFT                   13
1023 #define ASRC_ASRCTR_USRA_MASK                    0x4000u
1024 #define ASRC_ASRCTR_USRA_SHIFT                   14
1025 #define ASRC_ASRCTR_IDRB_MASK                    0x8000u
1026 #define ASRC_ASRCTR_IDRB_SHIFT                   15
1027 #define ASRC_ASRCTR_USRB_MASK                    0x10000u
1028 #define ASRC_ASRCTR_USRB_SHIFT                   16
1029 #define ASRC_ASRCTR_IDRC_MASK                    0x20000u
1030 #define ASRC_ASRCTR_IDRC_SHIFT                   17
1031 #define ASRC_ASRCTR_USRC_MASK                    0x40000u
1032 #define ASRC_ASRCTR_USRC_SHIFT                   18
1033 #define ASRC_ASRCTR_ATSA_MASK                    0x100000u
1034 #define ASRC_ASRCTR_ATSA_SHIFT                   20
1035 #define ASRC_ASRCTR_ATSB_MASK                    0x200000u
1036 #define ASRC_ASRCTR_ATSB_SHIFT                   21
1037 #define ASRC_ASRCTR_ATSC_MASK                    0x400000u
1038 #define ASRC_ASRCTR_ATSC_SHIFT                   22
1039 /* ASRIER Bit Fields */
1040 #define ASRC_ASRIER_ADIEA_MASK                   0x1u
1041 #define ASRC_ASRIER_ADIEA_SHIFT                  0
1042 #define ASRC_ASRIER_ADIEB_MASK                   0x2u
1043 #define ASRC_ASRIER_ADIEB_SHIFT                  1
1044 #define ASRC_ASRIER_ADIEC_MASK                   0x4u
1045 #define ASRC_ASRIER_ADIEC_SHIFT                  2
1046 #define ASRC_ASRIER_ADOEA_MASK                   0x8u
1047 #define ASRC_ASRIER_ADOEA_SHIFT                  3
1048 #define ASRC_ASRIER_ADOEB_MASK                   0x10u
1049 #define ASRC_ASRIER_ADOEB_SHIFT                  4
1050 #define ASRC_ASRIER_ADOEC_MASK                   0x20u
1051 #define ASRC_ASRIER_ADOEC_SHIFT                  5
1052 #define ASRC_ASRIER_AOLIE_MASK                   0x40u
1053 #define ASRC_ASRIER_AOLIE_SHIFT                  6
1054 #define ASRC_ASRIER_AFPWE_MASK                   0x80u
1055 #define ASRC_ASRIER_AFPWE_SHIFT                  7
1056 /* ASRCNCR Bit Fields */
1057 #define ASRC_ASRCNCR_ANCA_MASK                   0xFu
1058 #define ASRC_ASRCNCR_ANCA_SHIFT                  0
1059 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCA_SHIFT))&ASRC_ASRCNCR_ANCA_MASK)
1060 #define ASRC_ASRCNCR_ANCB_MASK                   0xF0u
1061 #define ASRC_ASRCNCR_ANCB_SHIFT                  4
1062 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCB_SHIFT))&ASRC_ASRCNCR_ANCB_MASK)
1063 #define ASRC_ASRCNCR_ANCC_MASK                   0xF00u
1064 #define ASRC_ASRCNCR_ANCC_SHIFT                  8
1065 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCC_SHIFT))&ASRC_ASRCNCR_ANCC_MASK)
1066 /* ASRCFG Bit Fields */
1067 #define ASRC_ASRCFG_PREMODA_MASK                 0xC0u
1068 #define ASRC_ASRCFG_PREMODA_SHIFT                6
1069 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODA_SHIFT))&ASRC_ASRCFG_PREMODA_MASK)
1070 #define ASRC_ASRCFG_POSTMODA_MASK                0x300u
1071 #define ASRC_ASRCFG_POSTMODA_SHIFT               8
1072 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODA_SHIFT))&ASRC_ASRCFG_POSTMODA_MASK)
1073 #define ASRC_ASRCFG_PREMODB_MASK                 0xC00u
1074 #define ASRC_ASRCFG_PREMODB_SHIFT                10
1075 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODB_SHIFT))&ASRC_ASRCFG_PREMODB_MASK)
1076 #define ASRC_ASRCFG_POSTMODB_MASK                0x3000u
1077 #define ASRC_ASRCFG_POSTMODB_SHIFT               12
1078 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODB_SHIFT))&ASRC_ASRCFG_POSTMODB_MASK)
1079 #define ASRC_ASRCFG_PREMODC_MASK                 0xC000u
1080 #define ASRC_ASRCFG_PREMODC_SHIFT                14
1081 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODC_SHIFT))&ASRC_ASRCFG_PREMODC_MASK)
1082 #define ASRC_ASRCFG_POSTMODC_MASK                0x30000u
1083 #define ASRC_ASRCFG_POSTMODC_SHIFT               16
1084 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODC_SHIFT))&ASRC_ASRCFG_POSTMODC_MASK)
1085 #define ASRC_ASRCFG_NDPRA_MASK                   0x40000u
1086 #define ASRC_ASRCFG_NDPRA_SHIFT                  18
1087 #define ASRC_ASRCFG_NDPRB_MASK                   0x80000u
1088 #define ASRC_ASRCFG_NDPRB_SHIFT                  19
1089 #define ASRC_ASRCFG_NDPRC_MASK                   0x100000u
1090 #define ASRC_ASRCFG_NDPRC_SHIFT                  20
1091 #define ASRC_ASRCFG_INIRQA_MASK                  0x200000u
1092 #define ASRC_ASRCFG_INIRQA_SHIFT                 21
1093 #define ASRC_ASRCFG_INIRQB_MASK                  0x400000u
1094 #define ASRC_ASRCFG_INIRQB_SHIFT                 22
1095 #define ASRC_ASRCFG_INIRQC_MASK                  0x800000u
1096 #define ASRC_ASRCFG_INIRQC_SHIFT                 23
1097 /* ASRCSR Bit Fields */
1098 #define ASRC_ASRCSR_AICSA_MASK                   0xFu
1099 #define ASRC_ASRCSR_AICSA_SHIFT                  0
1100 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSA_SHIFT))&ASRC_ASRCSR_AICSA_MASK)
1101 #define ASRC_ASRCSR_AICSB_MASK                   0xF0u
1102 #define ASRC_ASRCSR_AICSB_SHIFT                  4
1103 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSB_SHIFT))&ASRC_ASRCSR_AICSB_MASK)
1104 #define ASRC_ASRCSR_AICSC_MASK                   0xF00u
1105 #define ASRC_ASRCSR_AICSC_SHIFT                  8
1106 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSC_SHIFT))&ASRC_ASRCSR_AICSC_MASK)
1107 #define ASRC_ASRCSR_AOCSA_MASK                   0xF000u
1108 #define ASRC_ASRCSR_AOCSA_SHIFT                  12
1109 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSA_SHIFT))&ASRC_ASRCSR_AOCSA_MASK)
1110 #define ASRC_ASRCSR_AOCSB_MASK                   0xF0000u
1111 #define ASRC_ASRCSR_AOCSB_SHIFT                  16
1112 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSB_SHIFT))&ASRC_ASRCSR_AOCSB_MASK)
1113 #define ASRC_ASRCSR_AOCSC_MASK                   0xF00000u
1114 #define ASRC_ASRCSR_AOCSC_SHIFT                  20
1115 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSC_SHIFT))&ASRC_ASRCSR_AOCSC_MASK)
1116 /* ASRCDR1 Bit Fields */
1117 #define ASRC_ASRCDR1_AICPA_MASK                  0x7u
1118 #define ASRC_ASRCDR1_AICPA_SHIFT                 0
1119 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPA_SHIFT))&ASRC_ASRCDR1_AICPA_MASK)
1120 #define ASRC_ASRCDR1_AICDA_MASK                  0x38u
1121 #define ASRC_ASRCDR1_AICDA_SHIFT                 3
1122 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDA_SHIFT))&ASRC_ASRCDR1_AICDA_MASK)
1123 #define ASRC_ASRCDR1_AICPB_MASK                  0x1C0u
1124 #define ASRC_ASRCDR1_AICPB_SHIFT                 6
1125 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPB_SHIFT))&ASRC_ASRCDR1_AICPB_MASK)
1126 #define ASRC_ASRCDR1_AICDB_MASK                  0xE00u
1127 #define ASRC_ASRCDR1_AICDB_SHIFT                 9
1128 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDB_SHIFT))&ASRC_ASRCDR1_AICDB_MASK)
1129 #define ASRC_ASRCDR1_AOCPA_MASK                  0x7000u
1130 #define ASRC_ASRCDR1_AOCPA_SHIFT                 12
1131 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPA_SHIFT))&ASRC_ASRCDR1_AOCPA_MASK)
1132 #define ASRC_ASRCDR1_AOCDA_MASK                  0x38000u
1133 #define ASRC_ASRCDR1_AOCDA_SHIFT                 15
1134 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDA_SHIFT))&ASRC_ASRCDR1_AOCDA_MASK)
1135 #define ASRC_ASRCDR1_AOCPB_MASK                  0x1C0000u
1136 #define ASRC_ASRCDR1_AOCPB_SHIFT                 18
1137 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPB_SHIFT))&ASRC_ASRCDR1_AOCPB_MASK)
1138 #define ASRC_ASRCDR1_AOCDB_MASK                  0xE00000u
1139 #define ASRC_ASRCDR1_AOCDB_SHIFT                 21
1140 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDB_SHIFT))&ASRC_ASRCDR1_AOCDB_MASK)
1141 /* ASRCDR2 Bit Fields */
1142 #define ASRC_ASRCDR2_AICPC_MASK                  0x7u
1143 #define ASRC_ASRCDR2_AICPC_SHIFT                 0
1144 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICPC_SHIFT))&ASRC_ASRCDR2_AICPC_MASK)
1145 #define ASRC_ASRCDR2_AICDC_MASK                  0x38u
1146 #define ASRC_ASRCDR2_AICDC_SHIFT                 3
1147 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICDC_SHIFT))&ASRC_ASRCDR2_AICDC_MASK)
1148 #define ASRC_ASRCDR2_AOCPC_MASK                  0x1C0u
1149 #define ASRC_ASRCDR2_AOCPC_SHIFT                 6
1150 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCPC_SHIFT))&ASRC_ASRCDR2_AOCPC_MASK)
1151 #define ASRC_ASRCDR2_AOCDC_MASK                  0xE00u
1152 #define ASRC_ASRCDR2_AOCDC_SHIFT                 9
1153 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCDC_SHIFT))&ASRC_ASRCDR2_AOCDC_MASK)
1154 /* ASRSTR Bit Fields */
1155 #define ASRC_ASRSTR_AIDEA_MASK                   0x1u
1156 #define ASRC_ASRSTR_AIDEA_SHIFT                  0
1157 #define ASRC_ASRSTR_AIDEB_MASK                   0x2u
1158 #define ASRC_ASRSTR_AIDEB_SHIFT                  1
1159 #define ASRC_ASRSTR_AIDEC_MASK                   0x4u
1160 #define ASRC_ASRSTR_AIDEC_SHIFT                  2
1161 #define ASRC_ASRSTR_AODFA_MASK                   0x8u
1162 #define ASRC_ASRSTR_AODFA_SHIFT                  3
1163 #define ASRC_ASRSTR_AODFB_MASK                   0x10u
1164 #define ASRC_ASRSTR_AODFB_SHIFT                  4
1165 #define ASRC_ASRSTR_AODFC_MASK                   0x20u
1166 #define ASRC_ASRSTR_AODFC_SHIFT                  5
1167 #define ASRC_ASRSTR_AOLE_MASK                    0x40u
1168 #define ASRC_ASRSTR_AOLE_SHIFT                   6
1169 #define ASRC_ASRSTR_FPWT_MASK                    0x80u
1170 #define ASRC_ASRSTR_FPWT_SHIFT                   7
1171 #define ASRC_ASRSTR_AIDUA_MASK                   0x100u
1172 #define ASRC_ASRSTR_AIDUA_SHIFT                  8
1173 #define ASRC_ASRSTR_AIDUB_MASK                   0x200u
1174 #define ASRC_ASRSTR_AIDUB_SHIFT                  9
1175 #define ASRC_ASRSTR_AIDUC_MASK                   0x400u
1176 #define ASRC_ASRSTR_AIDUC_SHIFT                  10
1177 #define ASRC_ASRSTR_AODOA_MASK                   0x800u
1178 #define ASRC_ASRSTR_AODOA_SHIFT                  11
1179 #define ASRC_ASRSTR_AODOB_MASK                   0x1000u
1180 #define ASRC_ASRSTR_AODOB_SHIFT                  12
1181 #define ASRC_ASRSTR_AODOC_MASK                   0x2000u
1182 #define ASRC_ASRSTR_AODOC_SHIFT                  13
1183 #define ASRC_ASRSTR_AIOLA_MASK                   0x4000u
1184 #define ASRC_ASRSTR_AIOLA_SHIFT                  14
1185 #define ASRC_ASRSTR_AIOLB_MASK                   0x8000u
1186 #define ASRC_ASRSTR_AIOLB_SHIFT                  15
1187 #define ASRC_ASRSTR_AIOLC_MASK                   0x10000u
1188 #define ASRC_ASRSTR_AIOLC_SHIFT                  16
1189 #define ASRC_ASRSTR_AOOLA_MASK                   0x20000u
1190 #define ASRC_ASRSTR_AOOLA_SHIFT                  17
1191 #define ASRC_ASRSTR_AOOLB_MASK                   0x40000u
1192 #define ASRC_ASRSTR_AOOLB_SHIFT                  18
1193 #define ASRC_ASRSTR_AOOLC_MASK                   0x80000u
1194 #define ASRC_ASRSTR_AOOLC_SHIFT                  19
1195 #define ASRC_ASRSTR_ATQOL_MASK                   0x100000u
1196 #define ASRC_ASRSTR_ATQOL_SHIFT                  20
1197 #define ASRC_ASRSTR_DSLCNT_MASK                  0x200000u
1198 #define ASRC_ASRSTR_DSLCNT_SHIFT                 21
1199 /* ASRPMn Bit Fields */
1200 #define ASRC_ASRPMn_PARAMETER_VALUE_MASK         0xFFFFFFu
1201 #define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT        0
1202 #define ASRC_ASRPMn_PARAMETER_VALUE(x)           (((uint32_t)(((uint32_t)(x))<<ASRC_ASRPMn_PARAMETER_VALUE_SHIFT))&ASRC_ASRPMn_PARAMETER_VALUE_MASK)
1203 /* ASRTFR1 Bit Fields */
1204 #define ASRC_ASRTFR1_TF_BASE_MASK                0x1FC0u
1205 #define ASRC_ASRTFR1_TF_BASE_SHIFT               6
1206 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_BASE_SHIFT))&ASRC_ASRTFR1_TF_BASE_MASK)
1207 #define ASRC_ASRTFR1_TF_FILL_MASK                0xFE000u
1208 #define ASRC_ASRTFR1_TF_FILL_SHIFT               13
1209 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_FILL_SHIFT))&ASRC_ASRTFR1_TF_FILL_MASK)
1210 /* ASRCCR Bit Fields */
1211 #define ASRC_ASRCCR_ACIA_MASK                    0xFu
1212 #define ASRC_ASRCCR_ACIA_SHIFT                   0
1213 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIA_SHIFT))&ASRC_ASRCCR_ACIA_MASK)
1214 #define ASRC_ASRCCR_ACIB_MASK                    0xF0u
1215 #define ASRC_ASRCCR_ACIB_SHIFT                   4
1216 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIB_SHIFT))&ASRC_ASRCCR_ACIB_MASK)
1217 #define ASRC_ASRCCR_ACIC_MASK                    0xF00u
1218 #define ASRC_ASRCCR_ACIC_SHIFT                   8
1219 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIC_SHIFT))&ASRC_ASRCCR_ACIC_MASK)
1220 #define ASRC_ASRCCR_ACOA_MASK                    0xF000u
1221 #define ASRC_ASRCCR_ACOA_SHIFT                   12
1222 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOA_SHIFT))&ASRC_ASRCCR_ACOA_MASK)
1223 #define ASRC_ASRCCR_ACOB_MASK                    0xF0000u
1224 #define ASRC_ASRCCR_ACOB_SHIFT                   16
1225 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOB_SHIFT))&ASRC_ASRCCR_ACOB_MASK)
1226 #define ASRC_ASRCCR_ACOC_MASK                    0xF00000u
1227 #define ASRC_ASRCCR_ACOC_SHIFT                   20
1228 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOC_SHIFT))&ASRC_ASRCCR_ACOC_MASK)
1229 /* ASRDI Bit Fields */
1230 #define ASRC_ASRDI_DATA_MASK                     0xFFFFFFu
1231 #define ASRC_ASRDI_DATA_SHIFT                    0
1232 #define ASRC_ASRDI_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDI_DATA_SHIFT))&ASRC_ASRDI_DATA_MASK)
1233 /* ASRDO Bit Fields */
1234 #define ASRC_ASRDO_DATA_MASK                     0xFFFFFFu
1235 #define ASRC_ASRDO_DATA_SHIFT                    0
1236 #define ASRC_ASRDO_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDO_DATA_SHIFT))&ASRC_ASRDO_DATA_MASK)
1237 /* ASRIDRHA Bit Fields */
1238 #define ASRC_ASRIDRHA_IDRATIOA_MASK              0xFFu
1239 #define ASRC_ASRIDRHA_IDRATIOA_SHIFT             0
1240 #define ASRC_ASRIDRHA_IDRATIOA(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHA_IDRATIOA_SHIFT))&ASRC_ASRIDRHA_IDRATIOA_MASK)
1241 /* ASRIDRLA Bit Fields */
1242 #define ASRC_ASRIDRLA_IDRATIOA_MASK              0xFFFFFFu
1243 #define ASRC_ASRIDRLA_IDRATIOA_SHIFT             0
1244 #define ASRC_ASRIDRLA_IDRATIOA(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLA_IDRATIOA_SHIFT))&ASRC_ASRIDRLA_IDRATIOA_MASK)
1245 /* ASRIDRHB Bit Fields */
1246 #define ASRC_ASRIDRHB_IDRATIOB_MASK              0xFFu
1247 #define ASRC_ASRIDRHB_IDRATIOB_SHIFT             0
1248 #define ASRC_ASRIDRHB_IDRATIOB(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHB_IDRATIOB_SHIFT))&ASRC_ASRIDRHB_IDRATIOB_MASK)
1249 /* ASRIDRLB Bit Fields */
1250 #define ASRC_ASRIDRLB_IDRATIOB_MASK              0xFFFFFFu
1251 #define ASRC_ASRIDRLB_IDRATIOB_SHIFT             0
1252 #define ASRC_ASRIDRLB_IDRATIOB(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLB_IDRATIOB_SHIFT))&ASRC_ASRIDRLB_IDRATIOB_MASK)
1253 /* ASRIDRHC Bit Fields */
1254 #define ASRC_ASRIDRHC_IDRATIOC_MASK              0xFFu
1255 #define ASRC_ASRIDRHC_IDRATIOC_SHIFT             0
1256 #define ASRC_ASRIDRHC_IDRATIOC(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHC_IDRATIOC_SHIFT))&ASRC_ASRIDRHC_IDRATIOC_MASK)
1257 /* ASRIDRLC Bit Fields */
1258 #define ASRC_ASRIDRLC_IDRATIOC_MASK              0xFFFFFFu
1259 #define ASRC_ASRIDRLC_IDRATIOC_SHIFT             0
1260 #define ASRC_ASRIDRLC_IDRATIOC(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLC_IDRATIOC_SHIFT))&ASRC_ASRIDRLC_IDRATIOC_MASK)
1261 /* ASR76K Bit Fields */
1262 #define ASRC_ASR76K_ASR76K_MASK                  0x1FFFFu
1263 #define ASRC_ASR76K_ASR76K_SHIFT                 0
1264 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASR76K_ASR76K_SHIFT))&ASRC_ASR76K_ASR76K_MASK)
1265 /* ASR56K Bit Fields */
1266 #define ASRC_ASR56K_ASR56K_MASK                  0x1FFFFu
1267 #define ASRC_ASR56K_ASR56K_SHIFT                 0
1268 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASR56K_ASR56K_SHIFT))&ASRC_ASR56K_ASR56K_MASK)
1269 /* ASRMCRA Bit Fields */
1270 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      0x3Fu
1271 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     0
1272 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
1273 #define ASRC_ASRMCRA_RSYNOFA_MASK                0x400u
1274 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               10
1275 #define ASRC_ASRMCRA_RSYNIFA_MASK                0x800u
1276 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               11
1277 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     0x3F000u
1278 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    12
1279 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
1280 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            0x100000u
1281 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           20
1282 #define ASRC_ASRMCRA_BUFSTALLA_MASK              0x200000u
1283 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             21
1284 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              0x400000u
1285 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             22
1286 #define ASRC_ASRMCRA_ZEROBUFA_MASK               0x800000u
1287 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              23
1288 /* ASRFSTA Bit Fields */
1289 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           0x7Fu
1290 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          0
1291 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_INFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_INFIFO_FILLA_MASK)
1292 #define ASRC_ASRFSTA_IAEA_MASK                   0x800u
1293 #define ASRC_ASRFSTA_IAEA_SHIFT                  11
1294 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          0x7F000u
1295 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         12
1296 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
1297 #define ASRC_ASRFSTA_OAFA_MASK                   0x800000u
1298 #define ASRC_ASRFSTA_OAFA_SHIFT                  23
1299 /* ASRMCRB Bit Fields */
1300 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      0x3Fu
1301 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     0
1302 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
1303 #define ASRC_ASRMCRB_RSYNOFB_MASK                0x400u
1304 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               10
1305 #define ASRC_ASRMCRB_RSYNIFB_MASK                0x800u
1306 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               11
1307 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     0x3F000u
1308 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    12
1309 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
1310 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            0x100000u
1311 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           20
1312 #define ASRC_ASRMCRB_BUFSTALLB_MASK              0x200000u
1313 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             21
1314 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              0x400000u
1315 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             22
1316 #define ASRC_ASRMCRB_ZEROBUFB_MASK               0x800000u
1317 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              23
1318 /* ASRFSTB Bit Fields */
1319 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           0x7Fu
1320 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          0
1321 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_INFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_INFIFO_FILLB_MASK)
1322 #define ASRC_ASRFSTB_IAEB_MASK                   0x800u
1323 #define ASRC_ASRFSTB_IAEB_SHIFT                  11
1324 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          0x7F000u
1325 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         12
1326 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
1327 #define ASRC_ASRFSTB_OAFB_MASK                   0x800000u
1328 #define ASRC_ASRFSTB_OAFB_SHIFT                  23
1329 /* ASRMCRC Bit Fields */
1330 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      0x3Fu
1331 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     0
1332 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
1333 #define ASRC_ASRMCRC_RSYNOFC_MASK                0x400u
1334 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               10
1335 #define ASRC_ASRMCRC_RSYNIFC_MASK                0x800u
1336 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               11
1337 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     0x3F000u
1338 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    12
1339 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
1340 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            0x100000u
1341 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           20
1342 #define ASRC_ASRMCRC_BUFSTALLC_MASK              0x200000u
1343 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             21
1344 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              0x400000u
1345 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             22
1346 #define ASRC_ASRMCRC_ZEROBUFC_MASK               0x800000u
1347 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              23
1348 /* ASRFSTC Bit Fields */
1349 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           0x7Fu
1350 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          0
1351 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_INFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_INFIFO_FILLC_MASK)
1352 #define ASRC_ASRFSTC_IAEC_MASK                   0x800u
1353 #define ASRC_ASRFSTC_IAEC_SHIFT                  11
1354 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          0x7F000u
1355 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         12
1356 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
1357 #define ASRC_ASRFSTC_OAFC_MASK                   0x800000u
1358 #define ASRC_ASRFSTC_OAFC_SHIFT                  23
1359 /* ASRMCR1 Bit Fields */
1360 #define ASRC_ASRMCR1_OW16_MASK                   0x1u
1361 #define ASRC_ASRMCR1_OW16_SHIFT                  0
1362 #define ASRC_ASRMCR1_OSGN_MASK                   0x2u
1363 #define ASRC_ASRMCR1_OSGN_SHIFT                  1
1364 #define ASRC_ASRMCR1_OMSB_MASK                   0x4u
1365 #define ASRC_ASRMCR1_OMSB_SHIFT                  2
1366 #define ASRC_ASRMCR1_IMSB_MASK                   0x100u
1367 #define ASRC_ASRMCR1_IMSB_SHIFT                  8
1368 #define ASRC_ASRMCR1_IWD_MASK                    0xE00u
1369 #define ASRC_ASRMCR1_IWD_SHIFT                   9
1370 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCR1_IWD_SHIFT))&ASRC_ASRMCR1_IWD_MASK)
1371 
1372 /*!
1373  * @}
1374  */ /* end of group ASRC_Register_Masks */
1375 
1376 /* ASRC - Peripheral instance base addresses */
1377 /** Peripheral ASRC base address */
1378 #define ASRC_BASE                                (0x42034000u)
1379 /** Peripheral ASRC base pointer */
1380 #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
1381 #define ASRC_BASE_PTR                            (ASRC)
1382 /** Array initializer of ASRC peripheral base addresses */
1383 #define ASRC_BASE_ADDRS                          { ASRC_BASE }
1384 /** Array initializer of ASRC peripheral base pointers */
1385 #define ASRC_BASE_PTRS                           { ASRC }
1386 /** Interrupt vectors for the ASRC peripheral type */
1387 #define ASRC_IRQS                                { ASRC_IRQn }
1388 
1389 /* ----------------------------------------------------------------------------
1390    -- ASRC - Register accessor macros
1391    ---------------------------------------------------------------------------- */
1392 
1393 /*!
1394  * @addtogroup ASRC_Register_Accessor_Macros ASRC - Register accessor macros
1395  * @{
1396  */
1397 
1398 /* ASRC - Register instance definitions */
1399 /* ASRC */
1400 #define ASRC_ASRCTR                              ASRC_ASRCTR_REG(ASRC_BASE_PTR)
1401 #define ASRC_ASRIER                              ASRC_ASRIER_REG(ASRC_BASE_PTR)
1402 #define ASRC_ASRCNCR                             ASRC_ASRCNCR_REG(ASRC_BASE_PTR)
1403 #define ASRC_ASRCFG                              ASRC_ASRCFG_REG(ASRC_BASE_PTR)
1404 #define ASRC_ASRCSR                              ASRC_ASRCSR_REG(ASRC_BASE_PTR)
1405 #define ASRC_ASRCDR1                             ASRC_ASRCDR1_REG(ASRC_BASE_PTR)
1406 #define ASRC_ASRCDR2                             ASRC_ASRCDR2_REG(ASRC_BASE_PTR)
1407 #define ASRC_ASRSTR                              ASRC_ASRSTR_REG(ASRC_BASE_PTR)
1408 #define ASRC_ASRPMn1                             ASRC_ASRPMn_REG(ASRC_BASE_PTR,0)
1409 #define ASRC_ASRPMn2                             ASRC_ASRPMn_REG(ASRC_BASE_PTR,1)
1410 #define ASRC_ASRPMn3                             ASRC_ASRPMn_REG(ASRC_BASE_PTR,2)
1411 #define ASRC_ASRPMn4                             ASRC_ASRPMn_REG(ASRC_BASE_PTR,3)
1412 #define ASRC_ASRPMn5                             ASRC_ASRPMn_REG(ASRC_BASE_PTR,4)
1413 #define ASRC_ASRTFR1                             ASRC_ASRTFR1_REG(ASRC_BASE_PTR)
1414 #define ASRC_ASRCCR                              ASRC_ASRCCR_REG(ASRC_BASE_PTR)
1415 #define ASRC_ASRDIA                              ASRC_ASRDI_REG(ASRC_BASE_PTR,0)
1416 #define ASRC_ASRDOA                              ASRC_ASRDO_REG(ASRC_BASE_PTR,0)
1417 #define ASRC_ASRDIB                              ASRC_ASRDI_REG(ASRC_BASE_PTR,1)
1418 #define ASRC_ASRDOB                              ASRC_ASRDO_REG(ASRC_BASE_PTR,1)
1419 #define ASRC_ASRDIC                              ASRC_ASRDI_REG(ASRC_BASE_PTR,2)
1420 #define ASRC_ASRDOC                              ASRC_ASRDO_REG(ASRC_BASE_PTR,2)
1421 #define ASRC_ASRIDRHA                            ASRC_ASRIDRHA_REG(ASRC_BASE_PTR)
1422 #define ASRC_ASRIDRLA                            ASRC_ASRIDRLA_REG(ASRC_BASE_PTR)
1423 #define ASRC_ASRIDRHB                            ASRC_ASRIDRHB_REG(ASRC_BASE_PTR)
1424 #define ASRC_ASRIDRLB                            ASRC_ASRIDRLB_REG(ASRC_BASE_PTR)
1425 #define ASRC_ASRIDRHC                            ASRC_ASRIDRHC_REG(ASRC_BASE_PTR)
1426 #define ASRC_ASRIDRLC                            ASRC_ASRIDRLC_REG(ASRC_BASE_PTR)
1427 #define ASRC_ASR76K                              ASRC_ASR76K_REG(ASRC_BASE_PTR)
1428 #define ASRC_ASR56K                              ASRC_ASR56K_REG(ASRC_BASE_PTR)
1429 #define ASRC_ASRMCRA                             ASRC_ASRMCRA_REG(ASRC_BASE_PTR)
1430 #define ASRC_ASRFSTA                             ASRC_ASRFSTA_REG(ASRC_BASE_PTR)
1431 #define ASRC_ASRMCRB                             ASRC_ASRMCRB_REG(ASRC_BASE_PTR)
1432 #define ASRC_ASRFSTB                             ASRC_ASRFSTB_REG(ASRC_BASE_PTR)
1433 #define ASRC_ASRMCRC                             ASRC_ASRMCRC_REG(ASRC_BASE_PTR)
1434 #define ASRC_ASRFSTC                             ASRC_ASRFSTC_REG(ASRC_BASE_PTR)
1435 #define ASRC_ASRMCR1A                            ASRC_ASRMCR1_REG(ASRC_BASE_PTR,0)
1436 #define ASRC_ASRMCR1B                            ASRC_ASRMCR1_REG(ASRC_BASE_PTR,1)
1437 #define ASRC_ASRMCR1C                            ASRC_ASRMCR1_REG(ASRC_BASE_PTR,2)
1438 /* ASRC - Register array accessors */
1439 #define ASRC_ASRPMn(index)                       ASRC_ASRPMn_REG(ASRC_BASE_PTR,index)
1440 #define ASRC_ASRDI(index)                        ASRC_ASRDI_REG(ASRC_BASE_PTR,index)
1441 #define ASRC_ASRDO(index)                        ASRC_ASRDO_REG(ASRC_BASE_PTR,index)
1442 #define ASRC_ASRMCR1(index)                      ASRC_ASRMCR1_REG(ASRC_BASE_PTR,index)
1443 
1444 /*!
1445  * @}
1446  */ /* end of group ASRC_Register_Accessor_Macros */
1447 
1448 /*!
1449  * @}
1450  */ /* end of group ASRC_Peripheral */
1451 
1452 /* ----------------------------------------------------------------------------
1453    -- AUDMUX Peripheral Access Layer
1454    ---------------------------------------------------------------------------- */
1455 
1456 /*!
1457  * @addtogroup AUDMUX_Peripheral_Access_Layer AUDMUX Peripheral Access Layer
1458  * @{
1459  */
1460 
1461 /** AUDMUX - Register Layout Typedef */
1462 typedef struct {
1463   __IO  uint32_t PTCR1;                                  /**< Port Timing Control Register 1, offset: 0x0 */
1464   __IO  uint32_t PDCR1;                                  /**< Port Data Control Register 1, offset: 0x4 */
1465   __IO  uint32_t PTCR2;                                  /**< Port Timing Control Register 2, offset: 0x8 */
1466   __IO  uint32_t PDCR2;                                  /**< Port Data Control Register 2, offset: 0xC */
1467   __IO  uint32_t PTCR3;                                  /**< Port Timing Control Register 3, offset: 0x10 */
1468   __IO  uint32_t PDCR3;                                  /**< Port Data Control Register 3, offset: 0x14 */
1469   __IO  uint32_t PTCR4;                                  /**< Port Timing Control Register 4, offset: 0x18 */
1470   __IO  uint32_t PDCR4;                                  /**< Port Data Control Register 4, offset: 0x1C */
1471   __IO  uint32_t PTCR5;                                  /**< Port Timing Control Register 5, offset: 0x20 */
1472   __IO  uint32_t PDCR5;                                  /**< Port Data Control Register 5, offset: 0x24 */
1473   __IO  uint32_t PTCR6;                                  /**< Port Timing Control Register 6, offset: 0x28 */
1474   __IO  uint32_t PDCR6;                                  /**< Port Data Control Register 6, offset: 0x2C */
1475   __IO  uint32_t PTCR7;                                  /**< Port Timing Control Register 7, offset: 0x30 */
1476   __IO  uint32_t PDCR7;                                  /**< Port Data Control Register 7, offset: 0x34 */
1477 } AUDMUX_Type, *AUDMUX_MemMapPtr;
1478 
1479 /* ----------------------------------------------------------------------------
1480    -- AUDMUX - Register accessor macros
1481    ---------------------------------------------------------------------------- */
1482 
1483 /*!
1484  * @addtogroup AUDMUX_Register_Accessor_Macros AUDMUX - Register accessor macros
1485  * @{
1486  */
1487 
1488 /* AUDMUX - Register accessors */
1489 #define AUDMUX_PTCR1_REG(base)                   ((base)->PTCR1)
1490 #define AUDMUX_PDCR1_REG(base)                   ((base)->PDCR1)
1491 #define AUDMUX_PTCR2_REG(base)                   ((base)->PTCR2)
1492 #define AUDMUX_PDCR2_REG(base)                   ((base)->PDCR2)
1493 #define AUDMUX_PTCR3_REG(base)                   ((base)->PTCR3)
1494 #define AUDMUX_PDCR3_REG(base)                   ((base)->PDCR3)
1495 #define AUDMUX_PTCR4_REG(base)                   ((base)->PTCR4)
1496 #define AUDMUX_PDCR4_REG(base)                   ((base)->PDCR4)
1497 #define AUDMUX_PTCR5_REG(base)                   ((base)->PTCR5)
1498 #define AUDMUX_PDCR5_REG(base)                   ((base)->PDCR5)
1499 #define AUDMUX_PTCR6_REG(base)                   ((base)->PTCR6)
1500 #define AUDMUX_PDCR6_REG(base)                   ((base)->PDCR6)
1501 #define AUDMUX_PTCR7_REG(base)                   ((base)->PTCR7)
1502 #define AUDMUX_PDCR7_REG(base)                   ((base)->PDCR7)
1503 
1504 /*!
1505  * @}
1506  */ /* end of group AUDMUX_Register_Accessor_Macros */
1507 
1508 /* ----------------------------------------------------------------------------
1509    -- AUDMUX Register Masks
1510    ---------------------------------------------------------------------------- */
1511 
1512 /*!
1513  * @addtogroup AUDMUX_Register_Masks AUDMUX Register Masks
1514  * @{
1515  */
1516 
1517 /* PTCR1 Bit Fields */
1518 #define AUDMUX_PTCR1_SYN_MASK                    0x800u
1519 #define AUDMUX_PTCR1_SYN_SHIFT                   11
1520 #define AUDMUX_PTCR1_RCSEL_MASK                  0xF000u
1521 #define AUDMUX_PTCR1_RCSEL_SHIFT                 12
1522 #define AUDMUX_PTCR1_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_RCSEL_SHIFT))&AUDMUX_PTCR1_RCSEL_MASK)
1523 #define AUDMUX_PTCR1_RCLKDIR_MASK                0x10000u
1524 #define AUDMUX_PTCR1_RCLKDIR_SHIFT               16
1525 #define AUDMUX_PTCR1_RFSEL_MASK                  0x1E0000u
1526 #define AUDMUX_PTCR1_RFSEL_SHIFT                 17
1527 #define AUDMUX_PTCR1_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_RFSEL_SHIFT))&AUDMUX_PTCR1_RFSEL_MASK)
1528 #define AUDMUX_PTCR1_RFS_DIR_MASK                0x200000u
1529 #define AUDMUX_PTCR1_RFS_DIR_SHIFT               21
1530 #define AUDMUX_PTCR1_TCSEL_MASK                  0x3C00000u
1531 #define AUDMUX_PTCR1_TCSEL_SHIFT                 22
1532 #define AUDMUX_PTCR1_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_TCSEL_SHIFT))&AUDMUX_PTCR1_TCSEL_MASK)
1533 #define AUDMUX_PTCR1_TCLKDIR_MASK                0x4000000u
1534 #define AUDMUX_PTCR1_TCLKDIR_SHIFT               26
1535 #define AUDMUX_PTCR1_TFSEL_MASK                  0x78000000u
1536 #define AUDMUX_PTCR1_TFSEL_SHIFT                 27
1537 #define AUDMUX_PTCR1_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_TFSEL_SHIFT))&AUDMUX_PTCR1_TFSEL_MASK)
1538 #define AUDMUX_PTCR1_TFS_DIR_MASK                0x80000000u
1539 #define AUDMUX_PTCR1_TFS_DIR_SHIFT               31
1540 /* PDCR1 Bit Fields */
1541 #define AUDMUX_PDCR1_INMMASK_MASK                0xFFu
1542 #define AUDMUX_PDCR1_INMMASK_SHIFT               0
1543 #define AUDMUX_PDCR1_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR1_INMMASK_SHIFT))&AUDMUX_PDCR1_INMMASK_MASK)
1544 #define AUDMUX_PDCR1_MODE_MASK                   0x100u
1545 #define AUDMUX_PDCR1_MODE_SHIFT                  8
1546 #define AUDMUX_PDCR1_TXRXEN_MASK                 0x1000u
1547 #define AUDMUX_PDCR1_TXRXEN_SHIFT                12
1548 #define AUDMUX_PDCR1_RXDSEL_MASK                 0xE000u
1549 #define AUDMUX_PDCR1_RXDSEL_SHIFT                13
1550 #define AUDMUX_PDCR1_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR1_RXDSEL_SHIFT))&AUDMUX_PDCR1_RXDSEL_MASK)
1551 /* PTCR2 Bit Fields */
1552 #define AUDMUX_PTCR2_SYN_MASK                    0x800u
1553 #define AUDMUX_PTCR2_SYN_SHIFT                   11
1554 #define AUDMUX_PTCR2_RCSEL_MASK                  0xF000u
1555 #define AUDMUX_PTCR2_RCSEL_SHIFT                 12
1556 #define AUDMUX_PTCR2_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_RCSEL_SHIFT))&AUDMUX_PTCR2_RCSEL_MASK)
1557 #define AUDMUX_PTCR2_RCLKDIR_MASK                0x10000u
1558 #define AUDMUX_PTCR2_RCLKDIR_SHIFT               16
1559 #define AUDMUX_PTCR2_RFSEL_MASK                  0x1E0000u
1560 #define AUDMUX_PTCR2_RFSEL_SHIFT                 17
1561 #define AUDMUX_PTCR2_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_RFSEL_SHIFT))&AUDMUX_PTCR2_RFSEL_MASK)
1562 #define AUDMUX_PTCR2_RFS_DIR_MASK                0x200000u
1563 #define AUDMUX_PTCR2_RFS_DIR_SHIFT               21
1564 #define AUDMUX_PTCR2_TCSEL_MASK                  0x3C00000u
1565 #define AUDMUX_PTCR2_TCSEL_SHIFT                 22
1566 #define AUDMUX_PTCR2_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_TCSEL_SHIFT))&AUDMUX_PTCR2_TCSEL_MASK)
1567 #define AUDMUX_PTCR2_TCLKDIR_MASK                0x4000000u
1568 #define AUDMUX_PTCR2_TCLKDIR_SHIFT               26
1569 #define AUDMUX_PTCR2_TFSEL_MASK                  0x78000000u
1570 #define AUDMUX_PTCR2_TFSEL_SHIFT                 27
1571 #define AUDMUX_PTCR2_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_TFSEL_SHIFT))&AUDMUX_PTCR2_TFSEL_MASK)
1572 #define AUDMUX_PTCR2_TFS_DIR_MASK                0x80000000u
1573 #define AUDMUX_PTCR2_TFS_DIR_SHIFT               31
1574 /* PDCR2 Bit Fields */
1575 #define AUDMUX_PDCR2_INMMASK_MASK                0xFFu
1576 #define AUDMUX_PDCR2_INMMASK_SHIFT               0
1577 #define AUDMUX_PDCR2_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR2_INMMASK_SHIFT))&AUDMUX_PDCR2_INMMASK_MASK)
1578 #define AUDMUX_PDCR2_MODE_MASK                   0x100u
1579 #define AUDMUX_PDCR2_MODE_SHIFT                  8
1580 #define AUDMUX_PDCR2_TXRXEN_MASK                 0x1000u
1581 #define AUDMUX_PDCR2_TXRXEN_SHIFT                12
1582 #define AUDMUX_PDCR2_RXDSEL_MASK                 0xE000u
1583 #define AUDMUX_PDCR2_RXDSEL_SHIFT                13
1584 #define AUDMUX_PDCR2_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR2_RXDSEL_SHIFT))&AUDMUX_PDCR2_RXDSEL_MASK)
1585 /* PTCR3 Bit Fields */
1586 #define AUDMUX_PTCR3_SYN_MASK                    0x800u
1587 #define AUDMUX_PTCR3_SYN_SHIFT                   11
1588 #define AUDMUX_PTCR3_RCSEL_MASK                  0xF000u
1589 #define AUDMUX_PTCR3_RCSEL_SHIFT                 12
1590 #define AUDMUX_PTCR3_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_RCSEL_SHIFT))&AUDMUX_PTCR3_RCSEL_MASK)
1591 #define AUDMUX_PTCR3_RCLKDIR_MASK                0x10000u
1592 #define AUDMUX_PTCR3_RCLKDIR_SHIFT               16
1593 #define AUDMUX_PTCR3_RFSEL_MASK                  0x1E0000u
1594 #define AUDMUX_PTCR3_RFSEL_SHIFT                 17
1595 #define AUDMUX_PTCR3_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_RFSEL_SHIFT))&AUDMUX_PTCR3_RFSEL_MASK)
1596 #define AUDMUX_PTCR3_RFS_DIR_MASK                0x200000u
1597 #define AUDMUX_PTCR3_RFS_DIR_SHIFT               21
1598 #define AUDMUX_PTCR3_TCSEL_MASK                  0x3C00000u
1599 #define AUDMUX_PTCR3_TCSEL_SHIFT                 22
1600 #define AUDMUX_PTCR3_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_TCSEL_SHIFT))&AUDMUX_PTCR3_TCSEL_MASK)
1601 #define AUDMUX_PTCR3_TCLKDIR_MASK                0x4000000u
1602 #define AUDMUX_PTCR3_TCLKDIR_SHIFT               26
1603 #define AUDMUX_PTCR3_TFSEL_MASK                  0x78000000u
1604 #define AUDMUX_PTCR3_TFSEL_SHIFT                 27
1605 #define AUDMUX_PTCR3_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_TFSEL_SHIFT))&AUDMUX_PTCR3_TFSEL_MASK)
1606 #define AUDMUX_PTCR3_TFS_DIR_MASK                0x80000000u
1607 #define AUDMUX_PTCR3_TFS_DIR_SHIFT               31
1608 /* PDCR3 Bit Fields */
1609 #define AUDMUX_PDCR3_INMMASK_MASK                0xFFu
1610 #define AUDMUX_PDCR3_INMMASK_SHIFT               0
1611 #define AUDMUX_PDCR3_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR3_INMMASK_SHIFT))&AUDMUX_PDCR3_INMMASK_MASK)
1612 #define AUDMUX_PDCR3_MODE_MASK                   0x100u
1613 #define AUDMUX_PDCR3_MODE_SHIFT                  8
1614 #define AUDMUX_PDCR3_TXRXEN_MASK                 0x1000u
1615 #define AUDMUX_PDCR3_TXRXEN_SHIFT                12
1616 #define AUDMUX_PDCR3_RXDSEL_MASK                 0xE000u
1617 #define AUDMUX_PDCR3_RXDSEL_SHIFT                13
1618 #define AUDMUX_PDCR3_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR3_RXDSEL_SHIFT))&AUDMUX_PDCR3_RXDSEL_MASK)
1619 /* PTCR4 Bit Fields */
1620 #define AUDMUX_PTCR4_SYN_MASK                    0x800u
1621 #define AUDMUX_PTCR4_SYN_SHIFT                   11
1622 #define AUDMUX_PTCR4_RCSEL_MASK                  0xF000u
1623 #define AUDMUX_PTCR4_RCSEL_SHIFT                 12
1624 #define AUDMUX_PTCR4_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_RCSEL_SHIFT))&AUDMUX_PTCR4_RCSEL_MASK)
1625 #define AUDMUX_PTCR4_RCLKDIR_MASK                0x10000u
1626 #define AUDMUX_PTCR4_RCLKDIR_SHIFT               16
1627 #define AUDMUX_PTCR4_RFSEL_MASK                  0x1E0000u
1628 #define AUDMUX_PTCR4_RFSEL_SHIFT                 17
1629 #define AUDMUX_PTCR4_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_RFSEL_SHIFT))&AUDMUX_PTCR4_RFSEL_MASK)
1630 #define AUDMUX_PTCR4_RFS_DIR_MASK                0x200000u
1631 #define AUDMUX_PTCR4_RFS_DIR_SHIFT               21
1632 #define AUDMUX_PTCR4_TCSEL_MASK                  0x3C00000u
1633 #define AUDMUX_PTCR4_TCSEL_SHIFT                 22
1634 #define AUDMUX_PTCR4_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_TCSEL_SHIFT))&AUDMUX_PTCR4_TCSEL_MASK)
1635 #define AUDMUX_PTCR4_TCLKDIR_MASK                0x4000000u
1636 #define AUDMUX_PTCR4_TCLKDIR_SHIFT               26
1637 #define AUDMUX_PTCR4_TFSEL_MASK                  0x78000000u
1638 #define AUDMUX_PTCR4_TFSEL_SHIFT                 27
1639 #define AUDMUX_PTCR4_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_TFSEL_SHIFT))&AUDMUX_PTCR4_TFSEL_MASK)
1640 #define AUDMUX_PTCR4_TFS_DIR_MASK                0x80000000u
1641 #define AUDMUX_PTCR4_TFS_DIR_SHIFT               31
1642 /* PDCR4 Bit Fields */
1643 #define AUDMUX_PDCR4_INMMASK_MASK                0xFFu
1644 #define AUDMUX_PDCR4_INMMASK_SHIFT               0
1645 #define AUDMUX_PDCR4_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR4_INMMASK_SHIFT))&AUDMUX_PDCR4_INMMASK_MASK)
1646 #define AUDMUX_PDCR4_MODE_MASK                   0x100u
1647 #define AUDMUX_PDCR4_MODE_SHIFT                  8
1648 #define AUDMUX_PDCR4_TXRXEN_MASK                 0x1000u
1649 #define AUDMUX_PDCR4_TXRXEN_SHIFT                12
1650 #define AUDMUX_PDCR4_RXDSEL_MASK                 0xE000u
1651 #define AUDMUX_PDCR4_RXDSEL_SHIFT                13
1652 #define AUDMUX_PDCR4_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR4_RXDSEL_SHIFT))&AUDMUX_PDCR4_RXDSEL_MASK)
1653 /* PTCR5 Bit Fields */
1654 #define AUDMUX_PTCR5_SYN_MASK                    0x800u
1655 #define AUDMUX_PTCR5_SYN_SHIFT                   11
1656 #define AUDMUX_PTCR5_RCSEL_MASK                  0xF000u
1657 #define AUDMUX_PTCR5_RCSEL_SHIFT                 12
1658 #define AUDMUX_PTCR5_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_RCSEL_SHIFT))&AUDMUX_PTCR5_RCSEL_MASK)
1659 #define AUDMUX_PTCR5_RCLKDIR_MASK                0x10000u
1660 #define AUDMUX_PTCR5_RCLKDIR_SHIFT               16
1661 #define AUDMUX_PTCR5_RFSEL_MASK                  0x1E0000u
1662 #define AUDMUX_PTCR5_RFSEL_SHIFT                 17
1663 #define AUDMUX_PTCR5_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_RFSEL_SHIFT))&AUDMUX_PTCR5_RFSEL_MASK)
1664 #define AUDMUX_PTCR5_RFS_DIR_MASK                0x200000u
1665 #define AUDMUX_PTCR5_RFS_DIR_SHIFT               21
1666 #define AUDMUX_PTCR5_TCSEL_MASK                  0x3C00000u
1667 #define AUDMUX_PTCR5_TCSEL_SHIFT                 22
1668 #define AUDMUX_PTCR5_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_TCSEL_SHIFT))&AUDMUX_PTCR5_TCSEL_MASK)
1669 #define AUDMUX_PTCR5_TCLKDIR_MASK                0x4000000u
1670 #define AUDMUX_PTCR5_TCLKDIR_SHIFT               26
1671 #define AUDMUX_PTCR5_TFSEL_MASK                  0x78000000u
1672 #define AUDMUX_PTCR5_TFSEL_SHIFT                 27
1673 #define AUDMUX_PTCR5_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_TFSEL_SHIFT))&AUDMUX_PTCR5_TFSEL_MASK)
1674 #define AUDMUX_PTCR5_TFS_DIR_MASK                0x80000000u
1675 #define AUDMUX_PTCR5_TFS_DIR_SHIFT               31
1676 /* PDCR5 Bit Fields */
1677 #define AUDMUX_PDCR5_INMMASK_MASK                0xFFu
1678 #define AUDMUX_PDCR5_INMMASK_SHIFT               0
1679 #define AUDMUX_PDCR5_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR5_INMMASK_SHIFT))&AUDMUX_PDCR5_INMMASK_MASK)
1680 #define AUDMUX_PDCR5_MODE_MASK                   0x100u
1681 #define AUDMUX_PDCR5_MODE_SHIFT                  8
1682 #define AUDMUX_PDCR5_TXRXEN_MASK                 0x1000u
1683 #define AUDMUX_PDCR5_TXRXEN_SHIFT                12
1684 #define AUDMUX_PDCR5_RXDSEL_MASK                 0xE000u
1685 #define AUDMUX_PDCR5_RXDSEL_SHIFT                13
1686 #define AUDMUX_PDCR5_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR5_RXDSEL_SHIFT))&AUDMUX_PDCR5_RXDSEL_MASK)
1687 /* PTCR6 Bit Fields */
1688 #define AUDMUX_PTCR6_SYN_MASK                    0x800u
1689 #define AUDMUX_PTCR6_SYN_SHIFT                   11
1690 #define AUDMUX_PTCR6_RCSEL_MASK                  0xF000u
1691 #define AUDMUX_PTCR6_RCSEL_SHIFT                 12
1692 #define AUDMUX_PTCR6_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_RCSEL_SHIFT))&AUDMUX_PTCR6_RCSEL_MASK)
1693 #define AUDMUX_PTCR6_RCLKDIR_MASK                0x10000u
1694 #define AUDMUX_PTCR6_RCLKDIR_SHIFT               16
1695 #define AUDMUX_PTCR6_RFSEL_MASK                  0x1E0000u
1696 #define AUDMUX_PTCR6_RFSEL_SHIFT                 17
1697 #define AUDMUX_PTCR6_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_RFSEL_SHIFT))&AUDMUX_PTCR6_RFSEL_MASK)
1698 #define AUDMUX_PTCR6_RFS_DIR_MASK                0x200000u
1699 #define AUDMUX_PTCR6_RFS_DIR_SHIFT               21
1700 #define AUDMUX_PTCR6_TCSEL_MASK                  0x3C00000u
1701 #define AUDMUX_PTCR6_TCSEL_SHIFT                 22
1702 #define AUDMUX_PTCR6_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_TCSEL_SHIFT))&AUDMUX_PTCR6_TCSEL_MASK)
1703 #define AUDMUX_PTCR6_TCLKDIR_MASK                0x4000000u
1704 #define AUDMUX_PTCR6_TCLKDIR_SHIFT               26
1705 #define AUDMUX_PTCR6_TFSEL_MASK                  0x78000000u
1706 #define AUDMUX_PTCR6_TFSEL_SHIFT                 27
1707 #define AUDMUX_PTCR6_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_TFSEL_SHIFT))&AUDMUX_PTCR6_TFSEL_MASK)
1708 #define AUDMUX_PTCR6_TFS_DIR_MASK                0x80000000u
1709 #define AUDMUX_PTCR6_TFS_DIR_SHIFT               31
1710 /* PDCR6 Bit Fields */
1711 #define AUDMUX_PDCR6_INMMASK_MASK                0xFFu
1712 #define AUDMUX_PDCR6_INMMASK_SHIFT               0
1713 #define AUDMUX_PDCR6_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR6_INMMASK_SHIFT))&AUDMUX_PDCR6_INMMASK_MASK)
1714 #define AUDMUX_PDCR6_MODE_MASK                   0x100u
1715 #define AUDMUX_PDCR6_MODE_SHIFT                  8
1716 #define AUDMUX_PDCR6_TXRXEN_MASK                 0x1000u
1717 #define AUDMUX_PDCR6_TXRXEN_SHIFT                12
1718 #define AUDMUX_PDCR6_RXDSEL_MASK                 0xE000u
1719 #define AUDMUX_PDCR6_RXDSEL_SHIFT                13
1720 #define AUDMUX_PDCR6_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR6_RXDSEL_SHIFT))&AUDMUX_PDCR6_RXDSEL_MASK)
1721 /* PTCR7 Bit Fields */
1722 #define AUDMUX_PTCR7_SYN_MASK                    0x800u
1723 #define AUDMUX_PTCR7_SYN_SHIFT                   11
1724 #define AUDMUX_PTCR7_RCSEL_MASK                  0xF000u
1725 #define AUDMUX_PTCR7_RCSEL_SHIFT                 12
1726 #define AUDMUX_PTCR7_RCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_RCSEL_SHIFT))&AUDMUX_PTCR7_RCSEL_MASK)
1727 #define AUDMUX_PTCR7_RCLKDIR_MASK                0x10000u
1728 #define AUDMUX_PTCR7_RCLKDIR_SHIFT               16
1729 #define AUDMUX_PTCR7_RFSEL_MASK                  0x1E0000u
1730 #define AUDMUX_PTCR7_RFSEL_SHIFT                 17
1731 #define AUDMUX_PTCR7_RFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_RFSEL_SHIFT))&AUDMUX_PTCR7_RFSEL_MASK)
1732 #define AUDMUX_PTCR7_RFS_DIR_MASK                0x200000u
1733 #define AUDMUX_PTCR7_RFS_DIR_SHIFT               21
1734 #define AUDMUX_PTCR7_TCSEL_MASK                  0x3C00000u
1735 #define AUDMUX_PTCR7_TCSEL_SHIFT                 22
1736 #define AUDMUX_PTCR7_TCSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_TCSEL_SHIFT))&AUDMUX_PTCR7_TCSEL_MASK)
1737 #define AUDMUX_PTCR7_TCLKDIR_MASK                0x4000000u
1738 #define AUDMUX_PTCR7_TCLKDIR_SHIFT               26
1739 #define AUDMUX_PTCR7_TFSEL_MASK                  0x78000000u
1740 #define AUDMUX_PTCR7_TFSEL_SHIFT                 27
1741 #define AUDMUX_PTCR7_TFSEL(x)                    (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_TFSEL_SHIFT))&AUDMUX_PTCR7_TFSEL_MASK)
1742 #define AUDMUX_PTCR7_TFS_DIR_MASK                0x80000000u
1743 #define AUDMUX_PTCR7_TFS_DIR_SHIFT               31
1744 /* PDCR7 Bit Fields */
1745 #define AUDMUX_PDCR7_INMMASK_MASK                0xFFu
1746 #define AUDMUX_PDCR7_INMMASK_SHIFT               0
1747 #define AUDMUX_PDCR7_INMMASK(x)                  (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR7_INMMASK_SHIFT))&AUDMUX_PDCR7_INMMASK_MASK)
1748 #define AUDMUX_PDCR7_MODE_MASK                   0x100u
1749 #define AUDMUX_PDCR7_MODE_SHIFT                  8
1750 #define AUDMUX_PDCR7_TXRXEN_MASK                 0x1000u
1751 #define AUDMUX_PDCR7_TXRXEN_SHIFT                12
1752 #define AUDMUX_PDCR7_RXDSEL_MASK                 0xE000u
1753 #define AUDMUX_PDCR7_RXDSEL_SHIFT                13
1754 #define AUDMUX_PDCR7_RXDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR7_RXDSEL_SHIFT))&AUDMUX_PDCR7_RXDSEL_MASK)
1755 
1756 /*!
1757  * @}
1758  */ /* end of group AUDMUX_Register_Masks */
1759 
1760 /* AUDMUX - Peripheral instance base addresses */
1761 /** Peripheral AUDMUX base address */
1762 #define AUDMUX_BASE                              (0x421D8000u)
1763 /** Peripheral AUDMUX base pointer */
1764 #define AUDMUX                                   ((AUDMUX_Type *)AUDMUX_BASE)
1765 #define AUDMUX_BASE_PTR                          (AUDMUX)
1766 /** Array initializer of AUDMUX peripheral base addresses */
1767 #define AUDMUX_BASE_ADDRS                        { AUDMUX_BASE }
1768 /** Array initializer of AUDMUX peripheral base pointers */
1769 #define AUDMUX_BASE_PTRS                         { AUDMUX }
1770 
1771 /* ----------------------------------------------------------------------------
1772    -- AUDMUX - Register accessor macros
1773    ---------------------------------------------------------------------------- */
1774 
1775 /*!
1776  * @addtogroup AUDMUX_Register_Accessor_Macros AUDMUX - Register accessor macros
1777  * @{
1778  */
1779 
1780 /* AUDMUX - Register instance definitions */
1781 /* AUDMUX */
1782 #define AUDMUX_PTCR1                             AUDMUX_PTCR1_REG(AUDMUX_BASE_PTR)
1783 #define AUDMUX_PDCR1                             AUDMUX_PDCR1_REG(AUDMUX_BASE_PTR)
1784 #define AUDMUX_PTCR2                             AUDMUX_PTCR2_REG(AUDMUX_BASE_PTR)
1785 #define AUDMUX_PDCR2                             AUDMUX_PDCR2_REG(AUDMUX_BASE_PTR)
1786 #define AUDMUX_PTCR3                             AUDMUX_PTCR3_REG(AUDMUX_BASE_PTR)
1787 #define AUDMUX_PDCR3                             AUDMUX_PDCR3_REG(AUDMUX_BASE_PTR)
1788 #define AUDMUX_PTCR4                             AUDMUX_PTCR4_REG(AUDMUX_BASE_PTR)
1789 #define AUDMUX_PDCR4                             AUDMUX_PDCR4_REG(AUDMUX_BASE_PTR)
1790 #define AUDMUX_PTCR5                             AUDMUX_PTCR5_REG(AUDMUX_BASE_PTR)
1791 #define AUDMUX_PDCR5                             AUDMUX_PDCR5_REG(AUDMUX_BASE_PTR)
1792 #define AUDMUX_PTCR6                             AUDMUX_PTCR6_REG(AUDMUX_BASE_PTR)
1793 #define AUDMUX_PDCR6                             AUDMUX_PDCR6_REG(AUDMUX_BASE_PTR)
1794 #define AUDMUX_PTCR7                             AUDMUX_PTCR7_REG(AUDMUX_BASE_PTR)
1795 #define AUDMUX_PDCR7                             AUDMUX_PDCR7_REG(AUDMUX_BASE_PTR)
1796 
1797 /*!
1798  * @}
1799  */ /* end of group AUDMUX_Register_Accessor_Macros */
1800 
1801 /*!
1802  * @}
1803  */ /* end of group AUDMUX_Peripheral */
1804 
1805 /* ----------------------------------------------------------------------------
1806    -- BCH Peripheral Access Layer
1807    ---------------------------------------------------------------------------- */
1808 
1809 /*!
1810  * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
1811  * @{
1812  */
1813 
1814 /** BCH - Register Layout Typedef */
1815 typedef struct {
1816   __IO  uint32_t CTRL;                                   /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
1817   __IO  uint32_t CTRL_SET;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
1818   __IO  uint32_t CTRL_CLR;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
1819   __IO  uint32_t CTRL_TOG;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
1820   __I   uint32_t STATUS0;                                /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
1821   __I   uint32_t STATUS0_SET;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
1822   __I   uint32_t STATUS0_CLR;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
1823   __I   uint32_t STATUS0_TOG;                            /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
1824   __IO  uint32_t MODE;                                   /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
1825   __IO  uint32_t MODE_SET;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
1826   __IO  uint32_t MODE_CLR;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
1827   __IO  uint32_t MODE_TOG;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
1828   __IO  uint32_t ENCODEPTR;                              /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
1829   __IO  uint32_t ENCODEPTR_SET;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
1830   __IO  uint32_t ENCODEPTR_CLR;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
1831   __IO  uint32_t ENCODEPTR_TOG;                          /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
1832   __IO  uint32_t DATAPTR;                                /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
1833   __IO  uint32_t DATAPTR_SET;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
1834   __IO  uint32_t DATAPTR_CLR;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
1835   __IO  uint32_t DATAPTR_TOG;                            /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
1836   __IO  uint32_t METAPTR;                                /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
1837   __IO  uint32_t METAPTR_SET;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
1838   __IO  uint32_t METAPTR_CLR;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
1839   __IO  uint32_t METAPTR_TOG;                            /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
1840   uint8_t RESERVED_0[16];
1841   __IO  uint32_t LAYOUTSELECT;                           /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
1842   __IO  uint32_t LAYOUTSELECT_SET;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
1843   __IO  uint32_t LAYOUTSELECT_CLR;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
1844   __IO  uint32_t LAYOUTSELECT_TOG;                       /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
1845   __IO  uint32_t FLASH0LAYOUT0;                          /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
1846   __IO  uint32_t FLASH0LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
1847   __IO  uint32_t FLASH0LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
1848   __IO  uint32_t FLASH0LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
1849   __IO  uint32_t FLASH0LAYOUT1;                          /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
1850   __IO  uint32_t FLASH0LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
1851   __IO  uint32_t FLASH0LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
1852   __IO  uint32_t FLASH0LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
1853   __IO  uint32_t FLASH1LAYOUT0;                          /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
1854   __IO  uint32_t FLASH1LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
1855   __IO  uint32_t FLASH1LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
1856   __IO  uint32_t FLASH1LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
1857   __IO  uint32_t FLASH1LAYOUT1;                          /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
1858   __IO  uint32_t FLASH1LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
1859   __IO  uint32_t FLASH1LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
1860   __IO  uint32_t FLASH1LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
1861   __IO  uint32_t FLASH2LAYOUT0;                          /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
1862   __IO  uint32_t FLASH2LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
1863   __IO  uint32_t FLASH2LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
1864   __IO  uint32_t FLASH2LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
1865   __IO  uint32_t FLASH2LAYOUT1;                          /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
1866   __IO  uint32_t FLASH2LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
1867   __IO  uint32_t FLASH2LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
1868   __IO  uint32_t FLASH2LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
1869   __IO  uint32_t FLASH3LAYOUT0;                          /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
1870   __IO  uint32_t FLASH3LAYOUT0_SET;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
1871   __IO  uint32_t FLASH3LAYOUT0_CLR;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
1872   __IO  uint32_t FLASH3LAYOUT0_TOG;                      /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
1873   __IO  uint32_t FLASH3LAYOUT1;                          /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
1874   __IO  uint32_t FLASH3LAYOUT1_SET;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
1875   __IO  uint32_t FLASH3LAYOUT1_CLR;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
1876   __IO  uint32_t FLASH3LAYOUT1_TOG;                      /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
1877   __IO  uint32_t DEBUG0;                                 /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
1878   __IO  uint32_t DEBUG0_SET;                             /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
1879   __IO  uint32_t DEBUG0_CLR;                             /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
1880   __IO  uint32_t DEBUG0_TOG;                             /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
1881   __I   uint32_t DBGKESREAD;                             /**< KES Debug Read Register, offset: 0x110 */
1882   __I   uint32_t DBGKESREAD_SET;                         /**< KES Debug Read Register, offset: 0x114 */
1883   __I   uint32_t DBGKESREAD_CLR;                         /**< KES Debug Read Register, offset: 0x118 */
1884   __I   uint32_t DBGKESREAD_TOG;                         /**< KES Debug Read Register, offset: 0x11C */
1885   __I   uint32_t DBGCSFEREAD;                            /**< Chien Search Debug Read Register, offset: 0x120 */
1886   __I   uint32_t DBGCSFEREAD_SET;                        /**< Chien Search Debug Read Register, offset: 0x124 */
1887   __I   uint32_t DBGCSFEREAD_CLR;                        /**< Chien Search Debug Read Register, offset: 0x128 */
1888   __I   uint32_t DBGCSFEREAD_TOG;                        /**< Chien Search Debug Read Register, offset: 0x12C */
1889   __I   uint32_t DBGSYNDGENREAD;                         /**< Syndrome Generator Debug Read Register, offset: 0x130 */
1890   __I   uint32_t DBGSYNDGENREAD_SET;                     /**< Syndrome Generator Debug Read Register, offset: 0x134 */
1891   __I   uint32_t DBGSYNDGENREAD_CLR;                     /**< Syndrome Generator Debug Read Register, offset: 0x138 */
1892   __I   uint32_t DBGSYNDGENREAD_TOG;                     /**< Syndrome Generator Debug Read Register, offset: 0x13C */
1893   __I   uint32_t DBGAHBMREAD;                            /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
1894   __I   uint32_t DBGAHBMREAD_SET;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
1895   __I   uint32_t DBGAHBMREAD_CLR;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
1896   __I   uint32_t DBGAHBMREAD_TOG;                        /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
1897   __I   uint32_t BLOCKNAME;                              /**< Block Name Register, offset: 0x150 */
1898   __I   uint32_t BLOCKNAME_SET;                          /**< Block Name Register, offset: 0x154 */
1899   __I   uint32_t BLOCKNAME_CLR;                          /**< Block Name Register, offset: 0x158 */
1900   __I   uint32_t BLOCKNAME_TOG;                          /**< Block Name Register, offset: 0x15C */
1901   __I   uint32_t VERSION;                                /**< BCH Version Register, offset: 0x160 */
1902   __I   uint32_t VERSION_SET;                            /**< BCH Version Register, offset: 0x164 */
1903   __I   uint32_t VERSION_CLR;                            /**< BCH Version Register, offset: 0x168 */
1904   __I   uint32_t VERSION_TOG;                            /**< BCH Version Register, offset: 0x16C */
1905   __IO  uint32_t DEBUG1;                                 /**< Hardware BCH ECC Debug Register 1 , offset: 0x170 */
1906   __IO  uint32_t DEBUG1_SET;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x174 */
1907   __IO  uint32_t DEBUG1_CLR;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x178 */
1908   __IO  uint32_t DEBUG1_TOG;                             /**< Hardware BCH ECC Debug Register 1 , offset: 0x17C */
1909 } BCH_Type, *BCH_MemMapPtr;
1910 
1911 /* ----------------------------------------------------------------------------
1912    -- BCH - Register accessor macros
1913    ---------------------------------------------------------------------------- */
1914 
1915 /*!
1916  * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros
1917  * @{
1918  */
1919 
1920 /* BCH - Register accessors */
1921 #define BCH_CTRL_REG(base)                       ((base)->CTRL)
1922 #define BCH_CTRL_SET_REG(base)                   ((base)->CTRL_SET)
1923 #define BCH_CTRL_CLR_REG(base)                   ((base)->CTRL_CLR)
1924 #define BCH_CTRL_TOG_REG(base)                   ((base)->CTRL_TOG)
1925 #define BCH_STATUS0_REG(base)                    ((base)->STATUS0)
1926 #define BCH_STATUS0_SET_REG(base)                ((base)->STATUS0_SET)
1927 #define BCH_STATUS0_CLR_REG(base)                ((base)->STATUS0_CLR)
1928 #define BCH_STATUS0_TOG_REG(base)                ((base)->STATUS0_TOG)
1929 #define BCH_MODE_REG(base)                       ((base)->MODE)
1930 #define BCH_MODE_SET_REG(base)                   ((base)->MODE_SET)
1931 #define BCH_MODE_CLR_REG(base)                   ((base)->MODE_CLR)
1932 #define BCH_MODE_TOG_REG(base)                   ((base)->MODE_TOG)
1933 #define BCH_ENCODEPTR_REG(base)                  ((base)->ENCODEPTR)
1934 #define BCH_ENCODEPTR_SET_REG(base)              ((base)->ENCODEPTR_SET)
1935 #define BCH_ENCODEPTR_CLR_REG(base)              ((base)->ENCODEPTR_CLR)
1936 #define BCH_ENCODEPTR_TOG_REG(base)              ((base)->ENCODEPTR_TOG)
1937 #define BCH_DATAPTR_REG(base)                    ((base)->DATAPTR)
1938 #define BCH_DATAPTR_SET_REG(base)                ((base)->DATAPTR_SET)
1939 #define BCH_DATAPTR_CLR_REG(base)                ((base)->DATAPTR_CLR)
1940 #define BCH_DATAPTR_TOG_REG(base)                ((base)->DATAPTR_TOG)
1941 #define BCH_METAPTR_REG(base)                    ((base)->METAPTR)
1942 #define BCH_METAPTR_SET_REG(base)                ((base)->METAPTR_SET)
1943 #define BCH_METAPTR_CLR_REG(base)                ((base)->METAPTR_CLR)
1944 #define BCH_METAPTR_TOG_REG(base)                ((base)->METAPTR_TOG)
1945 #define BCH_LAYOUTSELECT_REG(base)               ((base)->LAYOUTSELECT)
1946 #define BCH_LAYOUTSELECT_SET_REG(base)           ((base)->LAYOUTSELECT_SET)
1947 #define BCH_LAYOUTSELECT_CLR_REG(base)           ((base)->LAYOUTSELECT_CLR)
1948 #define BCH_LAYOUTSELECT_TOG_REG(base)           ((base)->LAYOUTSELECT_TOG)
1949 #define BCH_FLASH0LAYOUT0_REG(base)              ((base)->FLASH0LAYOUT0)
1950 #define BCH_FLASH0LAYOUT0_SET_REG(base)          ((base)->FLASH0LAYOUT0_SET)
1951 #define BCH_FLASH0LAYOUT0_CLR_REG(base)          ((base)->FLASH0LAYOUT0_CLR)
1952 #define BCH_FLASH0LAYOUT0_TOG_REG(base)          ((base)->FLASH0LAYOUT0_TOG)
1953 #define BCH_FLASH0LAYOUT1_REG(base)              ((base)->FLASH0LAYOUT1)
1954 #define BCH_FLASH0LAYOUT1_SET_REG(base)          ((base)->FLASH0LAYOUT1_SET)
1955 #define BCH_FLASH0LAYOUT1_CLR_REG(base)          ((base)->FLASH0LAYOUT1_CLR)
1956 #define BCH_FLASH0LAYOUT1_TOG_REG(base)          ((base)->FLASH0LAYOUT1_TOG)
1957 #define BCH_FLASH1LAYOUT0_REG(base)              ((base)->FLASH1LAYOUT0)
1958 #define BCH_FLASH1LAYOUT0_SET_REG(base)          ((base)->FLASH1LAYOUT0_SET)
1959 #define BCH_FLASH1LAYOUT0_CLR_REG(base)          ((base)->FLASH1LAYOUT0_CLR)
1960 #define BCH_FLASH1LAYOUT0_TOG_REG(base)          ((base)->FLASH1LAYOUT0_TOG)
1961 #define BCH_FLASH1LAYOUT1_REG(base)              ((base)->FLASH1LAYOUT1)
1962 #define BCH_FLASH1LAYOUT1_SET_REG(base)          ((base)->FLASH1LAYOUT1_SET)
1963 #define BCH_FLASH1LAYOUT1_CLR_REG(base)          ((base)->FLASH1LAYOUT1_CLR)
1964 #define BCH_FLASH1LAYOUT1_TOG_REG(base)          ((base)->FLASH1LAYOUT1_TOG)
1965 #define BCH_FLASH2LAYOUT0_REG(base)              ((base)->FLASH2LAYOUT0)
1966 #define BCH_FLASH2LAYOUT0_SET_REG(base)          ((base)->FLASH2LAYOUT0_SET)
1967 #define BCH_FLASH2LAYOUT0_CLR_REG(base)          ((base)->FLASH2LAYOUT0_CLR)
1968 #define BCH_FLASH2LAYOUT0_TOG_REG(base)          ((base)->FLASH2LAYOUT0_TOG)
1969 #define BCH_FLASH2LAYOUT1_REG(base)              ((base)->FLASH2LAYOUT1)
1970 #define BCH_FLASH2LAYOUT1_SET_REG(base)          ((base)->FLASH2LAYOUT1_SET)
1971 #define BCH_FLASH2LAYOUT1_CLR_REG(base)          ((base)->FLASH2LAYOUT1_CLR)
1972 #define BCH_FLASH2LAYOUT1_TOG_REG(base)          ((base)->FLASH2LAYOUT1_TOG)
1973 #define BCH_FLASH3LAYOUT0_REG(base)              ((base)->FLASH3LAYOUT0)
1974 #define BCH_FLASH3LAYOUT0_SET_REG(base)          ((base)->FLASH3LAYOUT0_SET)
1975 #define BCH_FLASH3LAYOUT0_CLR_REG(base)          ((base)->FLASH3LAYOUT0_CLR)
1976 #define BCH_FLASH3LAYOUT0_TOG_REG(base)          ((base)->FLASH3LAYOUT0_TOG)
1977 #define BCH_FLASH3LAYOUT1_REG(base)              ((base)->FLASH3LAYOUT1)
1978 #define BCH_FLASH3LAYOUT1_SET_REG(base)          ((base)->FLASH3LAYOUT1_SET)
1979 #define BCH_FLASH3LAYOUT1_CLR_REG(base)          ((base)->FLASH3LAYOUT1_CLR)
1980 #define BCH_FLASH3LAYOUT1_TOG_REG(base)          ((base)->FLASH3LAYOUT1_TOG)
1981 #define BCH_DEBUG0_REG(base)                     ((base)->DEBUG0)
1982 #define BCH_DEBUG0_SET_REG(base)                 ((base)->DEBUG0_SET)
1983 #define BCH_DEBUG0_CLR_REG(base)                 ((base)->DEBUG0_CLR)
1984 #define BCH_DEBUG0_TOG_REG(base)                 ((base)->DEBUG0_TOG)
1985 #define BCH_DBGKESREAD_REG(base)                 ((base)->DBGKESREAD)
1986 #define BCH_DBGKESREAD_SET_REG(base)             ((base)->DBGKESREAD_SET)
1987 #define BCH_DBGKESREAD_CLR_REG(base)             ((base)->DBGKESREAD_CLR)
1988 #define BCH_DBGKESREAD_TOG_REG(base)             ((base)->DBGKESREAD_TOG)
1989 #define BCH_DBGCSFEREAD_REG(base)                ((base)->DBGCSFEREAD)
1990 #define BCH_DBGCSFEREAD_SET_REG(base)            ((base)->DBGCSFEREAD_SET)
1991 #define BCH_DBGCSFEREAD_CLR_REG(base)            ((base)->DBGCSFEREAD_CLR)
1992 #define BCH_DBGCSFEREAD_TOG_REG(base)            ((base)->DBGCSFEREAD_TOG)
1993 #define BCH_DBGSYNDGENREAD_REG(base)             ((base)->DBGSYNDGENREAD)
1994 #define BCH_DBGSYNDGENREAD_SET_REG(base)         ((base)->DBGSYNDGENREAD_SET)
1995 #define BCH_DBGSYNDGENREAD_CLR_REG(base)         ((base)->DBGSYNDGENREAD_CLR)
1996 #define BCH_DBGSYNDGENREAD_TOG_REG(base)         ((base)->DBGSYNDGENREAD_TOG)
1997 #define BCH_DBGAHBMREAD_REG(base)                ((base)->DBGAHBMREAD)
1998 #define BCH_DBGAHBMREAD_SET_REG(base)            ((base)->DBGAHBMREAD_SET)
1999 #define BCH_DBGAHBMREAD_CLR_REG(base)            ((base)->DBGAHBMREAD_CLR)
2000 #define BCH_DBGAHBMREAD_TOG_REG(base)            ((base)->DBGAHBMREAD_TOG)
2001 #define BCH_BLOCKNAME_REG(base)                  ((base)->BLOCKNAME)
2002 #define BCH_BLOCKNAME_SET_REG(base)              ((base)->BLOCKNAME_SET)
2003 #define BCH_BLOCKNAME_CLR_REG(base)              ((base)->BLOCKNAME_CLR)
2004 #define BCH_BLOCKNAME_TOG_REG(base)              ((base)->BLOCKNAME_TOG)
2005 #define BCH_VERSION_REG(base)                    ((base)->VERSION)
2006 #define BCH_VERSION_SET_REG(base)                ((base)->VERSION_SET)
2007 #define BCH_VERSION_CLR_REG(base)                ((base)->VERSION_CLR)
2008 #define BCH_VERSION_TOG_REG(base)                ((base)->VERSION_TOG)
2009 #define BCH_DEBUG1_REG(base)                     ((base)->DEBUG1)
2010 #define BCH_DEBUG1_SET_REG(base)                 ((base)->DEBUG1_SET)
2011 #define BCH_DEBUG1_CLR_REG(base)                 ((base)->DEBUG1_CLR)
2012 #define BCH_DEBUG1_TOG_REG(base)                 ((base)->DEBUG1_TOG)
2013 
2014 /*!
2015  * @}
2016  */ /* end of group BCH_Register_Accessor_Macros */
2017 
2018 /* ----------------------------------------------------------------------------
2019    -- BCH Register Masks
2020    ---------------------------------------------------------------------------- */
2021 
2022 /*!
2023  * @addtogroup BCH_Register_Masks BCH Register Masks
2024  * @{
2025  */
2026 
2027 /* CTRL Bit Fields */
2028 #define BCH_CTRL_COMPLETE_IRQ_MASK               0x1u
2029 #define BCH_CTRL_COMPLETE_IRQ_SHIFT              0
2030 #define BCH_CTRL_RSVD0_MASK                      0x2u
2031 #define BCH_CTRL_RSVD0_SHIFT                     1
2032 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK            0x4u
2033 #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           2
2034 #define BCH_CTRL_BM_ERROR_IRQ_MASK               0x8u
2035 #define BCH_CTRL_BM_ERROR_IRQ_SHIFT              3
2036 #define BCH_CTRL_RSVD1_MASK                      0xF0u
2037 #define BCH_CTRL_RSVD1_SHIFT                     4
2038 #define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD1_SHIFT))&BCH_CTRL_RSVD1_MASK)
2039 #define BCH_CTRL_COMPLETE_IRQ_EN_MASK            0x100u
2040 #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           8
2041 #define BCH_CTRL_RSVD2_MASK                      0x200u
2042 #define BCH_CTRL_RSVD2_SHIFT                     9
2043 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         0x400u
2044 #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        10
2045 #define BCH_CTRL_RSVD3_MASK                      0xF800u
2046 #define BCH_CTRL_RSVD3_SHIFT                     11
2047 #define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD3_SHIFT))&BCH_CTRL_RSVD3_MASK)
2048 #define BCH_CTRL_M2M_ENABLE_MASK                 0x10000u
2049 #define BCH_CTRL_M2M_ENABLE_SHIFT                16
2050 #define BCH_CTRL_M2M_ENCODE_MASK                 0x20000u
2051 #define BCH_CTRL_M2M_ENCODE_SHIFT                17
2052 #define BCH_CTRL_M2M_LAYOUT_MASK                 0xC0000u
2053 #define BCH_CTRL_M2M_LAYOUT_SHIFT                18
2054 #define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_M2M_LAYOUT_SHIFT))&BCH_CTRL_M2M_LAYOUT_MASK)
2055 #define BCH_CTRL_RSVD4_MASK                      0x300000u
2056 #define BCH_CTRL_RSVD4_SHIFT                     20
2057 #define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD4_SHIFT))&BCH_CTRL_RSVD4_MASK)
2058 #define BCH_CTRL_DEBUGSYNDROME_MASK              0x400000u
2059 #define BCH_CTRL_DEBUGSYNDROME_SHIFT             22
2060 #define BCH_CTRL_RSVD5_MASK                      0x3F800000u
2061 #define BCH_CTRL_RSVD5_SHIFT                     23
2062 #define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD5_SHIFT))&BCH_CTRL_RSVD5_MASK)
2063 #define BCH_CTRL_CLKGATE_MASK                    0x40000000u
2064 #define BCH_CTRL_CLKGATE_SHIFT                   30
2065 #define BCH_CTRL_SFTRST_MASK                     0x80000000u
2066 #define BCH_CTRL_SFTRST_SHIFT                    31
2067 /* CTRL_SET Bit Fields */
2068 #define BCH_CTRL_SET_COMPLETE_IRQ_MASK           0x1u
2069 #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT          0
2070 #define BCH_CTRL_SET_RSVD0_MASK                  0x2u
2071 #define BCH_CTRL_SET_RSVD0_SHIFT                 1
2072 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK        0x4u
2073 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT       2
2074 #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK           0x8u
2075 #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT          3
2076 #define BCH_CTRL_SET_RSVD1_MASK                  0xF0u
2077 #define BCH_CTRL_SET_RSVD1_SHIFT                 4
2078 #define BCH_CTRL_SET_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD1_SHIFT))&BCH_CTRL_SET_RSVD1_MASK)
2079 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK        0x100u
2080 #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT       8
2081 #define BCH_CTRL_SET_RSVD2_MASK                  0x200u
2082 #define BCH_CTRL_SET_RSVD2_SHIFT                 9
2083 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK     0x400u
2084 #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT    10
2085 #define BCH_CTRL_SET_RSVD3_MASK                  0xF800u
2086 #define BCH_CTRL_SET_RSVD3_SHIFT                 11
2087 #define BCH_CTRL_SET_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD3_SHIFT))&BCH_CTRL_SET_RSVD3_MASK)
2088 #define BCH_CTRL_SET_M2M_ENABLE_MASK             0x10000u
2089 #define BCH_CTRL_SET_M2M_ENABLE_SHIFT            16
2090 #define BCH_CTRL_SET_M2M_ENCODE_MASK             0x20000u
2091 #define BCH_CTRL_SET_M2M_ENCODE_SHIFT            17
2092 #define BCH_CTRL_SET_M2M_LAYOUT_MASK             0xC0000u
2093 #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT            18
2094 #define BCH_CTRL_SET_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_M2M_LAYOUT_SHIFT))&BCH_CTRL_SET_M2M_LAYOUT_MASK)
2095 #define BCH_CTRL_SET_RSVD4_MASK                  0x300000u
2096 #define BCH_CTRL_SET_RSVD4_SHIFT                 20
2097 #define BCH_CTRL_SET_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD4_SHIFT))&BCH_CTRL_SET_RSVD4_MASK)
2098 #define BCH_CTRL_SET_DEBUGSYNDROME_MASK          0x400000u
2099 #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT         22
2100 #define BCH_CTRL_SET_RSVD5_MASK                  0x3F800000u
2101 #define BCH_CTRL_SET_RSVD5_SHIFT                 23
2102 #define BCH_CTRL_SET_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD5_SHIFT))&BCH_CTRL_SET_RSVD5_MASK)
2103 #define BCH_CTRL_SET_CLKGATE_MASK                0x40000000u
2104 #define BCH_CTRL_SET_CLKGATE_SHIFT               30
2105 #define BCH_CTRL_SET_SFTRST_MASK                 0x80000000u
2106 #define BCH_CTRL_SET_SFTRST_SHIFT                31
2107 /* CTRL_CLR Bit Fields */
2108 #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK           0x1u
2109 #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT          0
2110 #define BCH_CTRL_CLR_RSVD0_MASK                  0x2u
2111 #define BCH_CTRL_CLR_RSVD0_SHIFT                 1
2112 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK        0x4u
2113 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT       2
2114 #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK           0x8u
2115 #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT          3
2116 #define BCH_CTRL_CLR_RSVD1_MASK                  0xF0u
2117 #define BCH_CTRL_CLR_RSVD1_SHIFT                 4
2118 #define BCH_CTRL_CLR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD1_SHIFT))&BCH_CTRL_CLR_RSVD1_MASK)
2119 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK        0x100u
2120 #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT       8
2121 #define BCH_CTRL_CLR_RSVD2_MASK                  0x200u
2122 #define BCH_CTRL_CLR_RSVD2_SHIFT                 9
2123 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK     0x400u
2124 #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT    10
2125 #define BCH_CTRL_CLR_RSVD3_MASK                  0xF800u
2126 #define BCH_CTRL_CLR_RSVD3_SHIFT                 11
2127 #define BCH_CTRL_CLR_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD3_SHIFT))&BCH_CTRL_CLR_RSVD3_MASK)
2128 #define BCH_CTRL_CLR_M2M_ENABLE_MASK             0x10000u
2129 #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT            16
2130 #define BCH_CTRL_CLR_M2M_ENCODE_MASK             0x20000u
2131 #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT            17
2132 #define BCH_CTRL_CLR_M2M_LAYOUT_MASK             0xC0000u
2133 #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT            18
2134 #define BCH_CTRL_CLR_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_M2M_LAYOUT_SHIFT))&BCH_CTRL_CLR_M2M_LAYOUT_MASK)
2135 #define BCH_CTRL_CLR_RSVD4_MASK                  0x300000u
2136 #define BCH_CTRL_CLR_RSVD4_SHIFT                 20
2137 #define BCH_CTRL_CLR_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD4_SHIFT))&BCH_CTRL_CLR_RSVD4_MASK)
2138 #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK          0x400000u
2139 #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT         22
2140 #define BCH_CTRL_CLR_RSVD5_MASK                  0x3F800000u
2141 #define BCH_CTRL_CLR_RSVD5_SHIFT                 23
2142 #define BCH_CTRL_CLR_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD5_SHIFT))&BCH_CTRL_CLR_RSVD5_MASK)
2143 #define BCH_CTRL_CLR_CLKGATE_MASK                0x40000000u
2144 #define BCH_CTRL_CLR_CLKGATE_SHIFT               30
2145 #define BCH_CTRL_CLR_SFTRST_MASK                 0x80000000u
2146 #define BCH_CTRL_CLR_SFTRST_SHIFT                31
2147 /* CTRL_TOG Bit Fields */
2148 #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK           0x1u
2149 #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT          0
2150 #define BCH_CTRL_TOG_RSVD0_MASK                  0x2u
2151 #define BCH_CTRL_TOG_RSVD0_SHIFT                 1
2152 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK        0x4u
2153 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT       2
2154 #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK           0x8u
2155 #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT          3
2156 #define BCH_CTRL_TOG_RSVD1_MASK                  0xF0u
2157 #define BCH_CTRL_TOG_RSVD1_SHIFT                 4
2158 #define BCH_CTRL_TOG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD1_SHIFT))&BCH_CTRL_TOG_RSVD1_MASK)
2159 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK        0x100u
2160 #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT       8
2161 #define BCH_CTRL_TOG_RSVD2_MASK                  0x200u
2162 #define BCH_CTRL_TOG_RSVD2_SHIFT                 9
2163 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK     0x400u
2164 #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT    10
2165 #define BCH_CTRL_TOG_RSVD3_MASK                  0xF800u
2166 #define BCH_CTRL_TOG_RSVD3_SHIFT                 11
2167 #define BCH_CTRL_TOG_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD3_SHIFT))&BCH_CTRL_TOG_RSVD3_MASK)
2168 #define BCH_CTRL_TOG_M2M_ENABLE_MASK             0x10000u
2169 #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT            16
2170 #define BCH_CTRL_TOG_M2M_ENCODE_MASK             0x20000u
2171 #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT            17
2172 #define BCH_CTRL_TOG_M2M_LAYOUT_MASK             0xC0000u
2173 #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT            18
2174 #define BCH_CTRL_TOG_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_M2M_LAYOUT_SHIFT))&BCH_CTRL_TOG_M2M_LAYOUT_MASK)
2175 #define BCH_CTRL_TOG_RSVD4_MASK                  0x300000u
2176 #define BCH_CTRL_TOG_RSVD4_SHIFT                 20
2177 #define BCH_CTRL_TOG_RSVD4(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD4_SHIFT))&BCH_CTRL_TOG_RSVD4_MASK)
2178 #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK          0x400000u
2179 #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT         22
2180 #define BCH_CTRL_TOG_RSVD5_MASK                  0x3F800000u
2181 #define BCH_CTRL_TOG_RSVD5_SHIFT                 23
2182 #define BCH_CTRL_TOG_RSVD5(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD5_SHIFT))&BCH_CTRL_TOG_RSVD5_MASK)
2183 #define BCH_CTRL_TOG_CLKGATE_MASK                0x40000000u
2184 #define BCH_CTRL_TOG_CLKGATE_SHIFT               30
2185 #define BCH_CTRL_TOG_SFTRST_MASK                 0x80000000u
2186 #define BCH_CTRL_TOG_SFTRST_SHIFT                31
2187 /* STATUS0 Bit Fields */
2188 #define BCH_STATUS0_RSVD0_MASK                   0x3u
2189 #define BCH_STATUS0_RSVD0_SHIFT                  0
2190 #define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD0_SHIFT))&BCH_STATUS0_RSVD0_MASK)
2191 #define BCH_STATUS0_UNCORRECTABLE_MASK           0x4u
2192 #define BCH_STATUS0_UNCORRECTABLE_SHIFT          2
2193 #define BCH_STATUS0_CORRECTED_MASK               0x8u
2194 #define BCH_STATUS0_CORRECTED_SHIFT              3
2195 #define BCH_STATUS0_ALLONES_MASK                 0x10u
2196 #define BCH_STATUS0_ALLONES_SHIFT                4
2197 #define BCH_STATUS0_RSVD1_MASK                   0xE0u
2198 #define BCH_STATUS0_RSVD1_SHIFT                  5
2199 #define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD1_SHIFT))&BCH_STATUS0_RSVD1_MASK)
2200 #define BCH_STATUS0_STATUS_BLK0_MASK             0xFF00u
2201 #define BCH_STATUS0_STATUS_BLK0_SHIFT            8
2202 #define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_STATUS_BLK0_SHIFT))&BCH_STATUS0_STATUS_BLK0_MASK)
2203 #define BCH_STATUS0_COMPLETED_CE_MASK            0xF0000u
2204 #define BCH_STATUS0_COMPLETED_CE_SHIFT           16
2205 #define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_COMPLETED_CE_SHIFT))&BCH_STATUS0_COMPLETED_CE_MASK)
2206 #define BCH_STATUS0_HANDLE_MASK                  0xFFF00000u
2207 #define BCH_STATUS0_HANDLE_SHIFT                 20
2208 #define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_HANDLE_SHIFT))&BCH_STATUS0_HANDLE_MASK)
2209 /* STATUS0_SET Bit Fields */
2210 #define BCH_STATUS0_SET_RSVD0_MASK               0x3u
2211 #define BCH_STATUS0_SET_RSVD0_SHIFT              0
2212 #define BCH_STATUS0_SET_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD0_SHIFT))&BCH_STATUS0_SET_RSVD0_MASK)
2213 #define BCH_STATUS0_SET_UNCORRECTABLE_MASK       0x4u
2214 #define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT      2
2215 #define BCH_STATUS0_SET_CORRECTED_MASK           0x8u
2216 #define BCH_STATUS0_SET_CORRECTED_SHIFT          3
2217 #define BCH_STATUS0_SET_ALLONES_MASK             0x10u
2218 #define BCH_STATUS0_SET_ALLONES_SHIFT            4
2219 #define BCH_STATUS0_SET_RSVD1_MASK               0xE0u
2220 #define BCH_STATUS0_SET_RSVD1_SHIFT              5
2221 #define BCH_STATUS0_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD1_SHIFT))&BCH_STATUS0_SET_RSVD1_MASK)
2222 #define BCH_STATUS0_SET_STATUS_BLK0_MASK         0xFF00u
2223 #define BCH_STATUS0_SET_STATUS_BLK0_SHIFT        8
2224 #define BCH_STATUS0_SET_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_STATUS_BLK0_SHIFT))&BCH_STATUS0_SET_STATUS_BLK0_MASK)
2225 #define BCH_STATUS0_SET_COMPLETED_CE_MASK        0xF0000u
2226 #define BCH_STATUS0_SET_COMPLETED_CE_SHIFT       16
2227 #define BCH_STATUS0_SET_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_COMPLETED_CE_SHIFT))&BCH_STATUS0_SET_COMPLETED_CE_MASK)
2228 #define BCH_STATUS0_SET_HANDLE_MASK              0xFFF00000u
2229 #define BCH_STATUS0_SET_HANDLE_SHIFT             20
2230 #define BCH_STATUS0_SET_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_HANDLE_SHIFT))&BCH_STATUS0_SET_HANDLE_MASK)
2231 /* STATUS0_CLR Bit Fields */
2232 #define BCH_STATUS0_CLR_RSVD0_MASK               0x3u
2233 #define BCH_STATUS0_CLR_RSVD0_SHIFT              0
2234 #define BCH_STATUS0_CLR_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK)
2235 #define BCH_STATUS0_CLR_UNCORRECTABLE_MASK       0x4u
2236 #define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT      2
2237 #define BCH_STATUS0_CLR_CORRECTED_MASK           0x8u
2238 #define BCH_STATUS0_CLR_CORRECTED_SHIFT          3
2239 #define BCH_STATUS0_CLR_ALLONES_MASK             0x10u
2240 #define BCH_STATUS0_CLR_ALLONES_SHIFT            4
2241 #define BCH_STATUS0_CLR_RSVD1_MASK               0xE0u
2242 #define BCH_STATUS0_CLR_RSVD1_SHIFT              5
2243 #define BCH_STATUS0_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD1_SHIFT))&BCH_STATUS0_CLR_RSVD1_MASK)
2244 #define BCH_STATUS0_CLR_STATUS_BLK0_MASK         0xFF00u
2245 #define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT        8
2246 #define BCH_STATUS0_CLR_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_STATUS_BLK0_SHIFT))&BCH_STATUS0_CLR_STATUS_BLK0_MASK)
2247 #define BCH_STATUS0_CLR_COMPLETED_CE_MASK        0xF0000u
2248 #define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT       16
2249 #define BCH_STATUS0_CLR_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_COMPLETED_CE_SHIFT))&BCH_STATUS0_CLR_COMPLETED_CE_MASK)
2250 #define BCH_STATUS0_CLR_HANDLE_MASK              0xFFF00000u
2251 #define BCH_STATUS0_CLR_HANDLE_SHIFT             20
2252 #define BCH_STATUS0_CLR_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_HANDLE_SHIFT))&BCH_STATUS0_CLR_HANDLE_MASK)
2253 /* STATUS0_TOG Bit Fields */
2254 #define BCH_STATUS0_TOG_RSVD0_MASK               0x3u
2255 #define BCH_STATUS0_TOG_RSVD0_SHIFT              0
2256 #define BCH_STATUS0_TOG_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD0_SHIFT))&BCH_STATUS0_TOG_RSVD0_MASK)
2257 #define BCH_STATUS0_TOG_UNCORRECTABLE_MASK       0x4u
2258 #define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT      2
2259 #define BCH_STATUS0_TOG_CORRECTED_MASK           0x8u
2260 #define BCH_STATUS0_TOG_CORRECTED_SHIFT          3
2261 #define BCH_STATUS0_TOG_ALLONES_MASK             0x10u
2262 #define BCH_STATUS0_TOG_ALLONES_SHIFT            4
2263 #define BCH_STATUS0_TOG_RSVD1_MASK               0xE0u
2264 #define BCH_STATUS0_TOG_RSVD1_SHIFT              5
2265 #define BCH_STATUS0_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD1_SHIFT))&BCH_STATUS0_TOG_RSVD1_MASK)
2266 #define BCH_STATUS0_TOG_STATUS_BLK0_MASK         0xFF00u
2267 #define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT        8
2268 #define BCH_STATUS0_TOG_STATUS_BLK0(x)           (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_STATUS_BLK0_SHIFT))&BCH_STATUS0_TOG_STATUS_BLK0_MASK)
2269 #define BCH_STATUS0_TOG_COMPLETED_CE_MASK        0xF0000u
2270 #define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT       16
2271 #define BCH_STATUS0_TOG_COMPLETED_CE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_COMPLETED_CE_SHIFT))&BCH_STATUS0_TOG_COMPLETED_CE_MASK)
2272 #define BCH_STATUS0_TOG_HANDLE_MASK              0xFFF00000u
2273 #define BCH_STATUS0_TOG_HANDLE_SHIFT             20
2274 #define BCH_STATUS0_TOG_HANDLE(x)                (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_HANDLE_SHIFT))&BCH_STATUS0_TOG_HANDLE_MASK)
2275 /* MODE Bit Fields */
2276 #define BCH_MODE_ERASE_THRESHOLD_MASK            0xFFu
2277 #define BCH_MODE_ERASE_THRESHOLD_SHIFT           0
2278 #define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x))<<BCH_MODE_ERASE_THRESHOLD_SHIFT))&BCH_MODE_ERASE_THRESHOLD_MASK)
2279 #define BCH_MODE_RSVD_MASK                       0xFFFFFF00u
2280 #define BCH_MODE_RSVD_SHIFT                      8
2281 #define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x))<<BCH_MODE_RSVD_SHIFT))&BCH_MODE_RSVD_MASK)
2282 /* MODE_SET Bit Fields */
2283 #define BCH_MODE_SET_ERASE_THRESHOLD_MASK        0xFFu
2284 #define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT       0
2285 #define BCH_MODE_SET_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_ERASE_THRESHOLD_SHIFT))&BCH_MODE_SET_ERASE_THRESHOLD_MASK)
2286 #define BCH_MODE_SET_RSVD_MASK                   0xFFFFFF00u
2287 #define BCH_MODE_SET_RSVD_SHIFT                  8
2288 #define BCH_MODE_SET_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_RSVD_SHIFT))&BCH_MODE_SET_RSVD_MASK)
2289 /* MODE_CLR Bit Fields */
2290 #define BCH_MODE_CLR_ERASE_THRESHOLD_MASK        0xFFu
2291 #define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT       0
2292 #define BCH_MODE_CLR_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT))&BCH_MODE_CLR_ERASE_THRESHOLD_MASK)
2293 #define BCH_MODE_CLR_RSVD_MASK                   0xFFFFFF00u
2294 #define BCH_MODE_CLR_RSVD_SHIFT                  8
2295 #define BCH_MODE_CLR_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_RSVD_SHIFT))&BCH_MODE_CLR_RSVD_MASK)
2296 /* MODE_TOG Bit Fields */
2297 #define BCH_MODE_TOG_ERASE_THRESHOLD_MASK        0xFFu
2298 #define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT       0
2299 #define BCH_MODE_TOG_ERASE_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT))&BCH_MODE_TOG_ERASE_THRESHOLD_MASK)
2300 #define BCH_MODE_TOG_RSVD_MASK                   0xFFFFFF00u
2301 #define BCH_MODE_TOG_RSVD_SHIFT                  8
2302 #define BCH_MODE_TOG_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_RSVD_SHIFT))&BCH_MODE_TOG_RSVD_MASK)
2303 /* ENCODEPTR Bit Fields */
2304 #define BCH_ENCODEPTR_ADDR_MASK                  0xFFFFFFFFu
2305 #define BCH_ENCODEPTR_ADDR_SHIFT                 0
2306 #define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_ADDR_SHIFT))&BCH_ENCODEPTR_ADDR_MASK)
2307 /* ENCODEPTR_SET Bit Fields */
2308 #define BCH_ENCODEPTR_SET_ADDR_MASK              0xFFFFFFFFu
2309 #define BCH_ENCODEPTR_SET_ADDR_SHIFT             0
2310 #define BCH_ENCODEPTR_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_SET_ADDR_SHIFT))&BCH_ENCODEPTR_SET_ADDR_MASK)
2311 /* ENCODEPTR_CLR Bit Fields */
2312 #define BCH_ENCODEPTR_CLR_ADDR_MASK              0xFFFFFFFFu
2313 #define BCH_ENCODEPTR_CLR_ADDR_SHIFT             0
2314 #define BCH_ENCODEPTR_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_CLR_ADDR_SHIFT))&BCH_ENCODEPTR_CLR_ADDR_MASK)
2315 /* ENCODEPTR_TOG Bit Fields */
2316 #define BCH_ENCODEPTR_TOG_ADDR_MASK              0xFFFFFFFFu
2317 #define BCH_ENCODEPTR_TOG_ADDR_SHIFT             0
2318 #define BCH_ENCODEPTR_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_TOG_ADDR_SHIFT))&BCH_ENCODEPTR_TOG_ADDR_MASK)
2319 /* DATAPTR Bit Fields */
2320 #define BCH_DATAPTR_ADDR_MASK                    0xFFFFFFFFu
2321 #define BCH_DATAPTR_ADDR_SHIFT                   0
2322 #define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_ADDR_SHIFT))&BCH_DATAPTR_ADDR_MASK)
2323 /* DATAPTR_SET Bit Fields */
2324 #define BCH_DATAPTR_SET_ADDR_MASK                0xFFFFFFFFu
2325 #define BCH_DATAPTR_SET_ADDR_SHIFT               0
2326 #define BCH_DATAPTR_SET_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_SET_ADDR_SHIFT))&BCH_DATAPTR_SET_ADDR_MASK)
2327 /* DATAPTR_CLR Bit Fields */
2328 #define BCH_DATAPTR_CLR_ADDR_MASK                0xFFFFFFFFu
2329 #define BCH_DATAPTR_CLR_ADDR_SHIFT               0
2330 #define BCH_DATAPTR_CLR_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_CLR_ADDR_SHIFT))&BCH_DATAPTR_CLR_ADDR_MASK)
2331 /* DATAPTR_TOG Bit Fields */
2332 #define BCH_DATAPTR_TOG_ADDR_MASK                0xFFFFFFFFu
2333 #define BCH_DATAPTR_TOG_ADDR_SHIFT               0
2334 #define BCH_DATAPTR_TOG_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_TOG_ADDR_SHIFT))&BCH_DATAPTR_TOG_ADDR_MASK)
2335 /* METAPTR Bit Fields */
2336 #define BCH_METAPTR_ADDR_MASK                    0xFFFFFFFFu
2337 #define BCH_METAPTR_ADDR_SHIFT                   0
2338 #define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_ADDR_SHIFT))&BCH_METAPTR_ADDR_MASK)
2339 /* METAPTR_SET Bit Fields */
2340 #define BCH_METAPTR_SET_ADDR_MASK                0xFFFFFFFFu
2341 #define BCH_METAPTR_SET_ADDR_SHIFT               0
2342 #define BCH_METAPTR_SET_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_SET_ADDR_SHIFT))&BCH_METAPTR_SET_ADDR_MASK)
2343 /* METAPTR_CLR Bit Fields */
2344 #define BCH_METAPTR_CLR_ADDR_MASK                0xFFFFFFFFu
2345 #define BCH_METAPTR_CLR_ADDR_SHIFT               0
2346 #define BCH_METAPTR_CLR_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_CLR_ADDR_SHIFT))&BCH_METAPTR_CLR_ADDR_MASK)
2347 /* METAPTR_TOG Bit Fields */
2348 #define BCH_METAPTR_TOG_ADDR_MASK                0xFFFFFFFFu
2349 #define BCH_METAPTR_TOG_ADDR_SHIFT               0
2350 #define BCH_METAPTR_TOG_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_TOG_ADDR_SHIFT))&BCH_METAPTR_TOG_ADDR_MASK)
2351 /* LAYOUTSELECT Bit Fields */
2352 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK         0x3u
2353 #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        0
2354 #define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS0_SELECT_MASK)
2355 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK         0xCu
2356 #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        2
2357 #define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS1_SELECT_MASK)
2358 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK         0x30u
2359 #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        4
2360 #define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS2_SELECT_MASK)
2361 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK         0xC0u
2362 #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        6
2363 #define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS3_SELECT_MASK)
2364 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK         0x300u
2365 #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        8
2366 #define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS4_SELECT_MASK)
2367 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK         0xC00u
2368 #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        10
2369 #define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS5_SELECT_MASK)
2370 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK         0x3000u
2371 #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        12
2372 #define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS6_SELECT_MASK)
2373 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK         0xC000u
2374 #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        14
2375 #define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS7_SELECT_MASK)
2376 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK         0x30000u
2377 #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        16
2378 #define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS8_SELECT_MASK)
2379 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK         0xC0000u
2380 #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        18
2381 #define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS9_SELECT_MASK)
2382 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK        0x300000u
2383 #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       20
2384 #define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS10_SELECT_MASK)
2385 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK        0xC00000u
2386 #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       22
2387 #define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS11_SELECT_MASK)
2388 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK        0x3000000u
2389 #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       24
2390 #define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS12_SELECT_MASK)
2391 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK        0xC000000u
2392 #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       26
2393 #define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS13_SELECT_MASK)
2394 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK        0x30000000u
2395 #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       28
2396 #define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS14_SELECT_MASK)
2397 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK        0xC0000000u
2398 #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       30
2399 #define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS15_SELECT_MASK)
2400 /* LAYOUTSELECT_SET Bit Fields */
2401 #define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK     0x3u
2402 #define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT    0
2403 #define BCH_LAYOUTSELECT_SET_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK)
2404 #define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK     0xCu
2405 #define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT    2
2406 #define BCH_LAYOUTSELECT_SET_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK)
2407 #define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK     0x30u
2408 #define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT    4
2409 #define BCH_LAYOUTSELECT_SET_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK)
2410 #define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK     0xC0u
2411 #define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT    6
2412 #define BCH_LAYOUTSELECT_SET_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK)
2413 #define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK     0x300u
2414 #define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT    8
2415 #define BCH_LAYOUTSELECT_SET_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK)
2416 #define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK     0xC00u
2417 #define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT    10
2418 #define BCH_LAYOUTSELECT_SET_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK)
2419 #define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK     0x3000u
2420 #define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT    12
2421 #define BCH_LAYOUTSELECT_SET_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK)
2422 #define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK     0xC000u
2423 #define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT    14
2424 #define BCH_LAYOUTSELECT_SET_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK)
2425 #define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK     0x30000u
2426 #define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT    16
2427 #define BCH_LAYOUTSELECT_SET_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK)
2428 #define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK     0xC0000u
2429 #define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT    18
2430 #define BCH_LAYOUTSELECT_SET_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK)
2431 #define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK    0x300000u
2432 #define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT   20
2433 #define BCH_LAYOUTSELECT_SET_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK)
2434 #define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK    0xC00000u
2435 #define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT   22
2436 #define BCH_LAYOUTSELECT_SET_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK)
2437 #define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK    0x3000000u
2438 #define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT   24
2439 #define BCH_LAYOUTSELECT_SET_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK)
2440 #define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK    0xC000000u
2441 #define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT   26
2442 #define BCH_LAYOUTSELECT_SET_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK)
2443 #define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK    0x30000000u
2444 #define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT   28
2445 #define BCH_LAYOUTSELECT_SET_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK)
2446 #define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK    0xC0000000u
2447 #define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT   30
2448 #define BCH_LAYOUTSELECT_SET_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK)
2449 /* LAYOUTSELECT_CLR Bit Fields */
2450 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK     0x3u
2451 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT    0
2452 #define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK)
2453 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK     0xCu
2454 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT    2
2455 #define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK)
2456 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK     0x30u
2457 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT    4
2458 #define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK)
2459 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK     0xC0u
2460 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT    6
2461 #define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK)
2462 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK     0x300u
2463 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT    8
2464 #define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK)
2465 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK     0xC00u
2466 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT    10
2467 #define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK)
2468 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK     0x3000u
2469 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT    12
2470 #define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK)
2471 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK     0xC000u
2472 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT    14
2473 #define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK)
2474 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK     0x30000u
2475 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT    16
2476 #define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK)
2477 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK     0xC0000u
2478 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT    18
2479 #define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK)
2480 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK    0x300000u
2481 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT   20
2482 #define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK)
2483 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK    0xC00000u
2484 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT   22
2485 #define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK)
2486 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK    0x3000000u
2487 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT   24
2488 #define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK)
2489 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK    0xC000000u
2490 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT   26
2491 #define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK)
2492 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK    0x30000000u
2493 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT   28
2494 #define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK)
2495 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK    0xC0000000u
2496 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT   30
2497 #define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK)
2498 /* LAYOUTSELECT_TOG Bit Fields */
2499 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK     0x3u
2500 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT    0
2501 #define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK)
2502 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK     0xCu
2503 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT    2
2504 #define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK)
2505 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK     0x30u
2506 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT    4
2507 #define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK)
2508 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK     0xC0u
2509 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT    6
2510 #define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK)
2511 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK     0x300u
2512 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT    8
2513 #define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK)
2514 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK     0xC00u
2515 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT    10
2516 #define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK)
2517 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK     0x3000u
2518 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT    12
2519 #define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK)
2520 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK     0xC000u
2521 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT    14
2522 #define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK)
2523 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK     0x30000u
2524 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT    16
2525 #define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK)
2526 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK     0xC0000u
2527 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT    18
2528 #define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK)
2529 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK    0x300000u
2530 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT   20
2531 #define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK)
2532 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK    0xC00000u
2533 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT   22
2534 #define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK)
2535 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK    0x3000000u
2536 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT   24
2537 #define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK)
2538 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK    0xC000000u
2539 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT   26
2540 #define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK)
2541 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK    0x30000000u
2542 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT   28
2543 #define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK)
2544 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK    0xC0000000u
2545 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT   30
2546 #define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK)
2547 /* FLASH0LAYOUT0 Bit Fields */
2548 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2549 #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       0
2550 #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
2551 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2552 #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    10
2553 #define BCH_FLASH0LAYOUT0_ECC0_MASK              0xF800u
2554 #define BCH_FLASH0LAYOUT0_ECC0_SHIFT             11
2555 #define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_ECC0_MASK)
2556 #define BCH_FLASH0LAYOUT0_META_SIZE_MASK         0xFF0000u
2557 #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        16
2558 #define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_META_SIZE_MASK)
2559 #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           0xFF000000u
2560 #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          24
2561 #define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
2562 /* FLASH0LAYOUT0_SET Bit Fields */
2563 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2564 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2565 #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK)
2566 #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2567 #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2568 #define BCH_FLASH0LAYOUT0_SET_ECC0_MASK          0xF800u
2569 #define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT         11
2570 #define BCH_FLASH0LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_SET_ECC0_MASK)
2571 #define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2572 #define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT    16
2573 #define BCH_FLASH0LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK)
2574 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2575 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT      24
2576 #define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK)
2577 /* FLASH0LAYOUT0_CLR Bit Fields */
2578 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2579 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2580 #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK)
2581 #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2582 #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2583 #define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK          0xF800u
2584 #define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT         11
2585 #define BCH_FLASH0LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_CLR_ECC0_MASK)
2586 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2587 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT    16
2588 #define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK)
2589 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2590 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT      24
2591 #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK)
2592 /* FLASH0LAYOUT0_TOG Bit Fields */
2593 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2594 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2595 #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK)
2596 #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2597 #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2598 #define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK          0xF800u
2599 #define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT         11
2600 #define BCH_FLASH0LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_TOG_ECC0_MASK)
2601 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2602 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT    16
2603 #define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK)
2604 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2605 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT      24
2606 #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK)
2607 /* FLASH0LAYOUT1 Bit Fields */
2608 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2609 #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       0
2610 #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
2611 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2612 #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    10
2613 #define BCH_FLASH0LAYOUT1_ECCN_MASK              0xF800u
2614 #define BCH_FLASH0LAYOUT1_ECCN_SHIFT             11
2615 #define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_ECCN_MASK)
2616 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2617 #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        16
2618 #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
2619 /* FLASH0LAYOUT1_SET Bit Fields */
2620 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2621 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2622 #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK)
2623 #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2624 #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2625 #define BCH_FLASH0LAYOUT1_SET_ECCN_MASK          0xF800u
2626 #define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT         11
2627 #define BCH_FLASH0LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_SET_ECCN_MASK)
2628 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2629 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2630 #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK)
2631 /* FLASH0LAYOUT1_CLR Bit Fields */
2632 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2633 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2634 #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK)
2635 #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2636 #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2637 #define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK          0xF800u
2638 #define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT         11
2639 #define BCH_FLASH0LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_CLR_ECCN_MASK)
2640 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2641 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2642 #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK)
2643 /* FLASH0LAYOUT1_TOG Bit Fields */
2644 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2645 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2646 #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK)
2647 #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2648 #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2649 #define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK          0xF800u
2650 #define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT         11
2651 #define BCH_FLASH0LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_TOG_ECCN_MASK)
2652 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2653 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2654 #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK)
2655 /* FLASH1LAYOUT0 Bit Fields */
2656 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2657 #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       0
2658 #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
2659 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2660 #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    10
2661 #define BCH_FLASH1LAYOUT0_ECC0_MASK              0xF800u
2662 #define BCH_FLASH1LAYOUT0_ECC0_SHIFT             11
2663 #define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_ECC0_MASK)
2664 #define BCH_FLASH1LAYOUT0_META_SIZE_MASK         0xFF0000u
2665 #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        16
2666 #define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_META_SIZE_MASK)
2667 #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           0xFF000000u
2668 #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          24
2669 #define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
2670 /* FLASH1LAYOUT0_SET Bit Fields */
2671 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2672 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2673 #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK)
2674 #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2675 #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2676 #define BCH_FLASH1LAYOUT0_SET_ECC0_MASK          0xF800u
2677 #define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT         11
2678 #define BCH_FLASH1LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_SET_ECC0_MASK)
2679 #define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2680 #define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT    16
2681 #define BCH_FLASH1LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK)
2682 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2683 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT      24
2684 #define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK)
2685 /* FLASH1LAYOUT0_CLR Bit Fields */
2686 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2687 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2688 #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK)
2689 #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2690 #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2691 #define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK          0xF800u
2692 #define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT         11
2693 #define BCH_FLASH1LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_CLR_ECC0_MASK)
2694 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2695 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT    16
2696 #define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK)
2697 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2698 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT      24
2699 #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK)
2700 /* FLASH1LAYOUT0_TOG Bit Fields */
2701 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2702 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2703 #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK)
2704 #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2705 #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2706 #define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK          0xF800u
2707 #define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT         11
2708 #define BCH_FLASH1LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_TOG_ECC0_MASK)
2709 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2710 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT    16
2711 #define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK)
2712 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2713 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT      24
2714 #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK)
2715 /* FLASH1LAYOUT1 Bit Fields */
2716 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2717 #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       0
2718 #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
2719 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2720 #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    10
2721 #define BCH_FLASH1LAYOUT1_ECCN_MASK              0xF800u
2722 #define BCH_FLASH1LAYOUT1_ECCN_SHIFT             11
2723 #define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_ECCN_MASK)
2724 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2725 #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        16
2726 #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
2727 /* FLASH1LAYOUT1_SET Bit Fields */
2728 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2729 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2730 #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK)
2731 #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2732 #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2733 #define BCH_FLASH1LAYOUT1_SET_ECCN_MASK          0xF800u
2734 #define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT         11
2735 #define BCH_FLASH1LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_SET_ECCN_MASK)
2736 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2737 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2738 #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK)
2739 /* FLASH1LAYOUT1_CLR Bit Fields */
2740 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2741 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2742 #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK)
2743 #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2744 #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2745 #define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK          0xF800u
2746 #define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT         11
2747 #define BCH_FLASH1LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_CLR_ECCN_MASK)
2748 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2749 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2750 #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK)
2751 /* FLASH1LAYOUT1_TOG Bit Fields */
2752 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2753 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2754 #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK)
2755 #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2756 #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2757 #define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK          0xF800u
2758 #define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT         11
2759 #define BCH_FLASH1LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_TOG_ECCN_MASK)
2760 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2761 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2762 #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK)
2763 /* FLASH2LAYOUT0 Bit Fields */
2764 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2765 #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       0
2766 #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
2767 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2768 #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    10
2769 #define BCH_FLASH2LAYOUT0_ECC0_MASK              0xF800u
2770 #define BCH_FLASH2LAYOUT0_ECC0_SHIFT             11
2771 #define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_ECC0_MASK)
2772 #define BCH_FLASH2LAYOUT0_META_SIZE_MASK         0xFF0000u
2773 #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        16
2774 #define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_META_SIZE_MASK)
2775 #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           0xFF000000u
2776 #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          24
2777 #define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
2778 /* FLASH2LAYOUT0_SET Bit Fields */
2779 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2780 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2781 #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK)
2782 #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2783 #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2784 #define BCH_FLASH2LAYOUT0_SET_ECC0_MASK          0xF800u
2785 #define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT         11
2786 #define BCH_FLASH2LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_SET_ECC0_MASK)
2787 #define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2788 #define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT    16
2789 #define BCH_FLASH2LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK)
2790 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2791 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT      24
2792 #define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK)
2793 /* FLASH2LAYOUT0_CLR Bit Fields */
2794 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2795 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2796 #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK)
2797 #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2798 #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2799 #define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK          0xF800u
2800 #define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT         11
2801 #define BCH_FLASH2LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_CLR_ECC0_MASK)
2802 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2803 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT    16
2804 #define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK)
2805 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2806 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT      24
2807 #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK)
2808 /* FLASH2LAYOUT0_TOG Bit Fields */
2809 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2810 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2811 #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK)
2812 #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2813 #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2814 #define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK          0xF800u
2815 #define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT         11
2816 #define BCH_FLASH2LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_TOG_ECC0_MASK)
2817 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2818 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT    16
2819 #define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK)
2820 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2821 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT      24
2822 #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK)
2823 /* FLASH2LAYOUT1 Bit Fields */
2824 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2825 #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       0
2826 #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
2827 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2828 #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    10
2829 #define BCH_FLASH2LAYOUT1_ECCN_MASK              0xF800u
2830 #define BCH_FLASH2LAYOUT1_ECCN_SHIFT             11
2831 #define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_ECCN_MASK)
2832 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2833 #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        16
2834 #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
2835 /* FLASH2LAYOUT1_SET Bit Fields */
2836 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2837 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2838 #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK)
2839 #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2840 #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2841 #define BCH_FLASH2LAYOUT1_SET_ECCN_MASK          0xF800u
2842 #define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT         11
2843 #define BCH_FLASH2LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_SET_ECCN_MASK)
2844 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2845 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2846 #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK)
2847 /* FLASH2LAYOUT1_CLR Bit Fields */
2848 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2849 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2850 #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK)
2851 #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2852 #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2853 #define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK          0xF800u
2854 #define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT         11
2855 #define BCH_FLASH2LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_CLR_ECCN_MASK)
2856 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2857 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2858 #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK)
2859 /* FLASH2LAYOUT1_TOG Bit Fields */
2860 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2861 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2862 #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK)
2863 #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2864 #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2865 #define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK          0xF800u
2866 #define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT         11
2867 #define BCH_FLASH2LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_TOG_ECCN_MASK)
2868 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2869 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2870 #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK)
2871 /* FLASH3LAYOUT0 Bit Fields */
2872 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        0x3FFu
2873 #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       0
2874 #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
2875 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     0x400u
2876 #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    10
2877 #define BCH_FLASH3LAYOUT0_ECC0_MASK              0xF800u
2878 #define BCH_FLASH3LAYOUT0_ECC0_SHIFT             11
2879 #define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_ECC0_MASK)
2880 #define BCH_FLASH3LAYOUT0_META_SIZE_MASK         0xFF0000u
2881 #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        16
2882 #define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_META_SIZE_MASK)
2883 #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           0xFF000000u
2884 #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          24
2885 #define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
2886 /* FLASH3LAYOUT0_SET Bit Fields */
2887 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK    0x3FFu
2888 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT   0
2889 #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK)
2890 #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u
2891 #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10
2892 #define BCH_FLASH3LAYOUT0_SET_ECC0_MASK          0xF800u
2893 #define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT         11
2894 #define BCH_FLASH3LAYOUT0_SET_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_SET_ECC0_MASK)
2895 #define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK     0xFF0000u
2896 #define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT    16
2897 #define BCH_FLASH3LAYOUT0_SET_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK)
2898 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK       0xFF000000u
2899 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT      24
2900 #define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK)
2901 /* FLASH3LAYOUT0_CLR Bit Fields */
2902 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK    0x3FFu
2903 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT   0
2904 #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK)
2905 #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u
2906 #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10
2907 #define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK          0xF800u
2908 #define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT         11
2909 #define BCH_FLASH3LAYOUT0_CLR_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_CLR_ECC0_MASK)
2910 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK     0xFF0000u
2911 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT    16
2912 #define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK)
2913 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK       0xFF000000u
2914 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT      24
2915 #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK)
2916 /* FLASH3LAYOUT0_TOG Bit Fields */
2917 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK    0x3FFu
2918 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT   0
2919 #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK)
2920 #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u
2921 #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10
2922 #define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK          0xF800u
2923 #define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT         11
2924 #define BCH_FLASH3LAYOUT0_TOG_ECC0(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_TOG_ECC0_MASK)
2925 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK     0xFF0000u
2926 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT    16
2927 #define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK)
2928 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK       0xFF000000u
2929 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT      24
2930 #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x)         (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK)
2931 /* FLASH3LAYOUT1 Bit Fields */
2932 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        0x3FFu
2933 #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       0
2934 #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
2935 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     0x400u
2936 #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    10
2937 #define BCH_FLASH3LAYOUT1_ECCN_MASK              0xF800u
2938 #define BCH_FLASH3LAYOUT1_ECCN_SHIFT             11
2939 #define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_ECCN_MASK)
2940 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         0xFFFF0000u
2941 #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        16
2942 #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
2943 /* FLASH3LAYOUT1_SET Bit Fields */
2944 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK    0x3FFu
2945 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT   0
2946 #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK)
2947 #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u
2948 #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10
2949 #define BCH_FLASH3LAYOUT1_SET_ECCN_MASK          0xF800u
2950 #define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT         11
2951 #define BCH_FLASH3LAYOUT1_SET_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_SET_ECCN_MASK)
2952 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK     0xFFFF0000u
2953 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT    16
2954 #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK)
2955 /* FLASH3LAYOUT1_CLR Bit Fields */
2956 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK    0x3FFu
2957 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT   0
2958 #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK)
2959 #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u
2960 #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10
2961 #define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK          0xF800u
2962 #define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT         11
2963 #define BCH_FLASH3LAYOUT1_CLR_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_CLR_ECCN_MASK)
2964 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK     0xFFFF0000u
2965 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT    16
2966 #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK)
2967 /* FLASH3LAYOUT1_TOG Bit Fields */
2968 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK    0x3FFu
2969 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT   0
2970 #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x)      (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK)
2971 #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u
2972 #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10
2973 #define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK          0xF800u
2974 #define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT         11
2975 #define BCH_FLASH3LAYOUT1_TOG_ECCN(x)            (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_TOG_ECCN_MASK)
2976 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK     0xFFFF0000u
2977 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT    16
2978 #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK)
2979 /* DEBUG0 Bit Fields */
2980 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         0x3Fu
2981 #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        0
2982 #define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
2983 #define BCH_DEBUG0_RSVD0_MASK                    0xC0u
2984 #define BCH_DEBUG0_RSVD0_SHIFT                   6
2985 #define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD0_SHIFT))&BCH_DEBUG0_RSVD0_MASK)
2986 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       0x100u
2987 #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      8
2988 #define BCH_DEBUG0_KES_DEBUG_STALL_MASK          0x200u
2989 #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         9
2990 #define BCH_DEBUG0_KES_DEBUG_STEP_MASK           0x400u
2991 #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          10
2992 #define BCH_DEBUG0_KES_STANDALONE_MASK           0x800u
2993 #define BCH_DEBUG0_KES_STANDALONE_SHIFT          11
2994 #define BCH_DEBUG0_KES_DEBUG_KICK_MASK           0x1000u
2995 #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          12
2996 #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         0x2000u
2997 #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        13
2998 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   0x4000u
2999 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  14
3000 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     0x8000u
3001 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    15
3002 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3003 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3004 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3005 #define BCH_DEBUG0_RSVD1_MASK                    0xFE000000u
3006 #define BCH_DEBUG0_RSVD1_SHIFT                   25
3007 #define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD1_SHIFT))&BCH_DEBUG0_RSVD1_MASK)
3008 /* DEBUG0_SET Bit Fields */
3009 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK     0x3Fu
3010 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT    0
3011 #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
3012 #define BCH_DEBUG0_SET_RSVD0_MASK                0xC0u
3013 #define BCH_DEBUG0_SET_RSVD0_SHIFT               6
3014 #define BCH_DEBUG0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD0_SHIFT))&BCH_DEBUG0_SET_RSVD0_MASK)
3015 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK   0x100u
3016 #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT  8
3017 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK      0x200u
3018 #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT     9
3019 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK       0x400u
3020 #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT      10
3021 #define BCH_DEBUG0_SET_KES_STANDALONE_MASK       0x800u
3022 #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT      11
3023 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK       0x1000u
3024 #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT      12
3025 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK     0x2000u
3026 #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT    13
3027 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3028 #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3029 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3030 #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT 15
3031 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3032 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3033 #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3034 #define BCH_DEBUG0_SET_RSVD1_MASK                0xFE000000u
3035 #define BCH_DEBUG0_SET_RSVD1_SHIFT               25
3036 #define BCH_DEBUG0_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD1_SHIFT))&BCH_DEBUG0_SET_RSVD1_MASK)
3037 /* DEBUG0_CLR Bit Fields */
3038 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK     0x3Fu
3039 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT    0
3040 #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
3041 #define BCH_DEBUG0_CLR_RSVD0_MASK                0xC0u
3042 #define BCH_DEBUG0_CLR_RSVD0_SHIFT               6
3043 #define BCH_DEBUG0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD0_SHIFT))&BCH_DEBUG0_CLR_RSVD0_MASK)
3044 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK   0x100u
3045 #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT  8
3046 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK      0x200u
3047 #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT     9
3048 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK       0x400u
3049 #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT      10
3050 #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK       0x800u
3051 #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT      11
3052 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK       0x1000u
3053 #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT      12
3054 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK     0x2000u
3055 #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT    13
3056 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3057 #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3058 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3059 #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT 15
3060 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3061 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3062 #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3063 #define BCH_DEBUG0_CLR_RSVD1_MASK                0xFE000000u
3064 #define BCH_DEBUG0_CLR_RSVD1_SHIFT               25
3065 #define BCH_DEBUG0_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD1_SHIFT))&BCH_DEBUG0_CLR_RSVD1_MASK)
3066 /* DEBUG0_TOG Bit Fields */
3067 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK     0x3Fu
3068 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT    0
3069 #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
3070 #define BCH_DEBUG0_TOG_RSVD0_MASK                0xC0u
3071 #define BCH_DEBUG0_TOG_RSVD0_SHIFT               6
3072 #define BCH_DEBUG0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD0_SHIFT))&BCH_DEBUG0_TOG_RSVD0_MASK)
3073 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK   0x100u
3074 #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT  8
3075 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK      0x200u
3076 #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT     9
3077 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK       0x400u
3078 #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT      10
3079 #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK       0x800u
3080 #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT      11
3081 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK       0x1000u
3082 #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT      12
3083 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK     0x2000u
3084 #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT    13
3085 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u
3086 #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14
3087 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK 0x8000u
3088 #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT 15
3089 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u
3090 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16
3091 #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3092 #define BCH_DEBUG0_TOG_RSVD1_MASK                0xFE000000u
3093 #define BCH_DEBUG0_TOG_RSVD1_SHIFT               25
3094 #define BCH_DEBUG0_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD1_SHIFT))&BCH_DEBUG0_TOG_RSVD1_MASK)
3095 /* DBGKESREAD Bit Fields */
3096 #define BCH_DBGKESREAD_VALUES_MASK               0xFFFFFFFFu
3097 #define BCH_DBGKESREAD_VALUES_SHIFT              0
3098 #define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_VALUES_SHIFT))&BCH_DBGKESREAD_VALUES_MASK)
3099 /* DBGKESREAD_SET Bit Fields */
3100 #define BCH_DBGKESREAD_SET_VALUES_MASK           0xFFFFFFFFu
3101 #define BCH_DBGKESREAD_SET_VALUES_SHIFT          0
3102 #define BCH_DBGKESREAD_SET_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_SET_VALUES_SHIFT))&BCH_DBGKESREAD_SET_VALUES_MASK)
3103 /* DBGKESREAD_CLR Bit Fields */
3104 #define BCH_DBGKESREAD_CLR_VALUES_MASK           0xFFFFFFFFu
3105 #define BCH_DBGKESREAD_CLR_VALUES_SHIFT          0
3106 #define BCH_DBGKESREAD_CLR_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_CLR_VALUES_SHIFT))&BCH_DBGKESREAD_CLR_VALUES_MASK)
3107 /* DBGKESREAD_TOG Bit Fields */
3108 #define BCH_DBGKESREAD_TOG_VALUES_MASK           0xFFFFFFFFu
3109 #define BCH_DBGKESREAD_TOG_VALUES_SHIFT          0
3110 #define BCH_DBGKESREAD_TOG_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_TOG_VALUES_SHIFT))&BCH_DBGKESREAD_TOG_VALUES_MASK)
3111 /* DBGCSFEREAD Bit Fields */
3112 #define BCH_DBGCSFEREAD_VALUES_MASK              0xFFFFFFFFu
3113 #define BCH_DBGCSFEREAD_VALUES_SHIFT             0
3114 #define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_VALUES_SHIFT))&BCH_DBGCSFEREAD_VALUES_MASK)
3115 /* DBGCSFEREAD_SET Bit Fields */
3116 #define BCH_DBGCSFEREAD_SET_VALUES_MASK          0xFFFFFFFFu
3117 #define BCH_DBGCSFEREAD_SET_VALUES_SHIFT         0
3118 #define BCH_DBGCSFEREAD_SET_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_SET_VALUES_SHIFT))&BCH_DBGCSFEREAD_SET_VALUES_MASK)
3119 /* DBGCSFEREAD_CLR Bit Fields */
3120 #define BCH_DBGCSFEREAD_CLR_VALUES_MASK          0xFFFFFFFFu
3121 #define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT         0
3122 #define BCH_DBGCSFEREAD_CLR_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_CLR_VALUES_SHIFT))&BCH_DBGCSFEREAD_CLR_VALUES_MASK)
3123 /* DBGCSFEREAD_TOG Bit Fields */
3124 #define BCH_DBGCSFEREAD_TOG_VALUES_MASK          0xFFFFFFFFu
3125 #define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT         0
3126 #define BCH_DBGCSFEREAD_TOG_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_TOG_VALUES_SHIFT))&BCH_DBGCSFEREAD_TOG_VALUES_MASK)
3127 /* DBGSYNDGENREAD Bit Fields */
3128 #define BCH_DBGSYNDGENREAD_VALUES_MASK           0xFFFFFFFFu
3129 #define BCH_DBGSYNDGENREAD_VALUES_SHIFT          0
3130 #define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_VALUES_MASK)
3131 /* DBGSYNDGENREAD_SET Bit Fields */
3132 #define BCH_DBGSYNDGENREAD_SET_VALUES_MASK       0xFFFFFFFFu
3133 #define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT      0
3134 #define BCH_DBGSYNDGENREAD_SET_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_SET_VALUES_MASK)
3135 /* DBGSYNDGENREAD_CLR Bit Fields */
3136 #define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK       0xFFFFFFFFu
3137 #define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT      0
3138 #define BCH_DBGSYNDGENREAD_CLR_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_CLR_VALUES_MASK)
3139 /* DBGSYNDGENREAD_TOG Bit Fields */
3140 #define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK       0xFFFFFFFFu
3141 #define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT      0
3142 #define BCH_DBGSYNDGENREAD_TOG_VALUES(x)         (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_TOG_VALUES_MASK)
3143 /* DBGAHBMREAD Bit Fields */
3144 #define BCH_DBGAHBMREAD_VALUES_MASK              0xFFFFFFFFu
3145 #define BCH_DBGAHBMREAD_VALUES_SHIFT             0
3146 #define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_VALUES_SHIFT))&BCH_DBGAHBMREAD_VALUES_MASK)
3147 /* DBGAHBMREAD_SET Bit Fields */
3148 #define BCH_DBGAHBMREAD_SET_VALUES_MASK          0xFFFFFFFFu
3149 #define BCH_DBGAHBMREAD_SET_VALUES_SHIFT         0
3150 #define BCH_DBGAHBMREAD_SET_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_SET_VALUES_SHIFT))&BCH_DBGAHBMREAD_SET_VALUES_MASK)
3151 /* DBGAHBMREAD_CLR Bit Fields */
3152 #define BCH_DBGAHBMREAD_CLR_VALUES_MASK          0xFFFFFFFFu
3153 #define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT         0
3154 #define BCH_DBGAHBMREAD_CLR_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_CLR_VALUES_SHIFT))&BCH_DBGAHBMREAD_CLR_VALUES_MASK)
3155 /* DBGAHBMREAD_TOG Bit Fields */
3156 #define BCH_DBGAHBMREAD_TOG_VALUES_MASK          0xFFFFFFFFu
3157 #define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT         0
3158 #define BCH_DBGAHBMREAD_TOG_VALUES(x)            (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_TOG_VALUES_SHIFT))&BCH_DBGAHBMREAD_TOG_VALUES_MASK)
3159 /* BLOCKNAME Bit Fields */
3160 #define BCH_BLOCKNAME_NAME_MASK                  0xFFFFFFFFu
3161 #define BCH_BLOCKNAME_NAME_SHIFT                 0
3162 #define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_NAME_SHIFT))&BCH_BLOCKNAME_NAME_MASK)
3163 /* BLOCKNAME_SET Bit Fields */
3164 #define BCH_BLOCKNAME_SET_NAME_MASK              0xFFFFFFFFu
3165 #define BCH_BLOCKNAME_SET_NAME_SHIFT             0
3166 #define BCH_BLOCKNAME_SET_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_SET_NAME_SHIFT))&BCH_BLOCKNAME_SET_NAME_MASK)
3167 /* BLOCKNAME_CLR Bit Fields */
3168 #define BCH_BLOCKNAME_CLR_NAME_MASK              0xFFFFFFFFu
3169 #define BCH_BLOCKNAME_CLR_NAME_SHIFT             0
3170 #define BCH_BLOCKNAME_CLR_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_CLR_NAME_SHIFT))&BCH_BLOCKNAME_CLR_NAME_MASK)
3171 /* BLOCKNAME_TOG Bit Fields */
3172 #define BCH_BLOCKNAME_TOG_NAME_MASK              0xFFFFFFFFu
3173 #define BCH_BLOCKNAME_TOG_NAME_SHIFT             0
3174 #define BCH_BLOCKNAME_TOG_NAME(x)                (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_TOG_NAME_SHIFT))&BCH_BLOCKNAME_TOG_NAME_MASK)
3175 /* VERSION Bit Fields */
3176 #define BCH_VERSION_STEP_MASK                    0xFFFFu
3177 #define BCH_VERSION_STEP_SHIFT                   0
3178 #define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_STEP_SHIFT))&BCH_VERSION_STEP_MASK)
3179 #define BCH_VERSION_MINOR_MASK                   0xFF0000u
3180 #define BCH_VERSION_MINOR_SHIFT                  16
3181 #define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MINOR_SHIFT))&BCH_VERSION_MINOR_MASK)
3182 #define BCH_VERSION_MAJOR_MASK                   0xFF000000u
3183 #define BCH_VERSION_MAJOR_SHIFT                  24
3184 #define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MAJOR_SHIFT))&BCH_VERSION_MAJOR_MASK)
3185 /* VERSION_SET Bit Fields */
3186 #define BCH_VERSION_SET_STEP_MASK                0xFFFFu
3187 #define BCH_VERSION_SET_STEP_SHIFT               0
3188 #define BCH_VERSION_SET_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_STEP_SHIFT))&BCH_VERSION_SET_STEP_MASK)
3189 #define BCH_VERSION_SET_MINOR_MASK               0xFF0000u
3190 #define BCH_VERSION_SET_MINOR_SHIFT              16
3191 #define BCH_VERSION_SET_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MINOR_SHIFT))&BCH_VERSION_SET_MINOR_MASK)
3192 #define BCH_VERSION_SET_MAJOR_MASK               0xFF000000u
3193 #define BCH_VERSION_SET_MAJOR_SHIFT              24
3194 #define BCH_VERSION_SET_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MAJOR_SHIFT))&BCH_VERSION_SET_MAJOR_MASK)
3195 /* VERSION_CLR Bit Fields */
3196 #define BCH_VERSION_CLR_STEP_MASK                0xFFFFu
3197 #define BCH_VERSION_CLR_STEP_SHIFT               0
3198 #define BCH_VERSION_CLR_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_STEP_SHIFT))&BCH_VERSION_CLR_STEP_MASK)
3199 #define BCH_VERSION_CLR_MINOR_MASK               0xFF0000u
3200 #define BCH_VERSION_CLR_MINOR_SHIFT              16
3201 #define BCH_VERSION_CLR_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MINOR_SHIFT))&BCH_VERSION_CLR_MINOR_MASK)
3202 #define BCH_VERSION_CLR_MAJOR_MASK               0xFF000000u
3203 #define BCH_VERSION_CLR_MAJOR_SHIFT              24
3204 #define BCH_VERSION_CLR_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MAJOR_SHIFT))&BCH_VERSION_CLR_MAJOR_MASK)
3205 /* VERSION_TOG Bit Fields */
3206 #define BCH_VERSION_TOG_STEP_MASK                0xFFFFu
3207 #define BCH_VERSION_TOG_STEP_SHIFT               0
3208 #define BCH_VERSION_TOG_STEP(x)                  (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_STEP_SHIFT))&BCH_VERSION_TOG_STEP_MASK)
3209 #define BCH_VERSION_TOG_MINOR_MASK               0xFF0000u
3210 #define BCH_VERSION_TOG_MINOR_SHIFT              16
3211 #define BCH_VERSION_TOG_MINOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MINOR_SHIFT))&BCH_VERSION_TOG_MINOR_MASK)
3212 #define BCH_VERSION_TOG_MAJOR_MASK               0xFF000000u
3213 #define BCH_VERSION_TOG_MAJOR_SHIFT              24
3214 #define BCH_VERSION_TOG_MAJOR(x)                 (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MAJOR_SHIFT))&BCH_VERSION_TOG_MAJOR_MASK)
3215 /* DEBUG1 Bit Fields */
3216 #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        0x1FFu
3217 #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       0
3218 #define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
3219 #define BCH_DEBUG1_RSVD_MASK                     0x7FFFFE00u
3220 #define BCH_DEBUG1_RSVD_SHIFT                    9
3221 #define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_RSVD_SHIFT))&BCH_DEBUG1_RSVD_MASK)
3222 #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       0x80000000u
3223 #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      31
3224 /* DEBUG1_SET Bit Fields */
3225 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK    0x1FFu
3226 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT   0
3227 #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK)
3228 #define BCH_DEBUG1_SET_RSVD_MASK                 0x7FFFFE00u
3229 #define BCH_DEBUG1_SET_RSVD_SHIFT                9
3230 #define BCH_DEBUG1_SET_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_RSVD_SHIFT))&BCH_DEBUG1_SET_RSVD_MASK)
3231 #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK   0x80000000u
3232 #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT  31
3233 /* DEBUG1_CLR Bit Fields */
3234 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK    0x1FFu
3235 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT   0
3236 #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK)
3237 #define BCH_DEBUG1_CLR_RSVD_MASK                 0x7FFFFE00u
3238 #define BCH_DEBUG1_CLR_RSVD_SHIFT                9
3239 #define BCH_DEBUG1_CLR_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_RSVD_SHIFT))&BCH_DEBUG1_CLR_RSVD_MASK)
3240 #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK   0x80000000u
3241 #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT  31
3242 /* DEBUG1_TOG Bit Fields */
3243 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK    0x1FFu
3244 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT   0
3245 #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x)      (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK)
3246 #define BCH_DEBUG1_TOG_RSVD_MASK                 0x7FFFFE00u
3247 #define BCH_DEBUG1_TOG_RSVD_SHIFT                9
3248 #define BCH_DEBUG1_TOG_RSVD(x)                   (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_RSVD_SHIFT))&BCH_DEBUG1_TOG_RSVD_MASK)
3249 #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK   0x80000000u
3250 #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT  31
3251 
3252 /*!
3253  * @}
3254  */ /* end of group BCH_Register_Masks */
3255 
3256 /* BCH - Peripheral instance base addresses */
3257 /** Peripheral BCH base address */
3258 #define BCH_BASE                                 (0x41808000u)
3259 /** Peripheral BCH base pointer */
3260 #define BCH                                      ((BCH_Type *)BCH_BASE)
3261 #define BCH_BASE_PTR                             (BCH)
3262 /** Array initializer of BCH peripheral base addresses */
3263 #define BCH_BASE_ADDRS                           { BCH_BASE }
3264 /** Array initializer of BCH peripheral base pointers */
3265 #define BCH_BASE_PTRS                            { BCH }
3266 /** Interrupt vectors for the BCH peripheral type */
3267 #define BCH_IRQS                                 { BCH_IRQn }
3268 
3269 /* ----------------------------------------------------------------------------
3270    -- BCH - Register accessor macros
3271    ---------------------------------------------------------------------------- */
3272 
3273 /*!
3274  * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros
3275  * @{
3276  */
3277 
3278 /* BCH - Register instance definitions */
3279 /* BCH */
3280 #define BCH_CTRL                                 BCH_CTRL_REG(BCH_BASE_PTR)
3281 #define BCH_CTRL_SET                             BCH_CTRL_SET_REG(BCH_BASE_PTR)
3282 #define BCH_CTRL_CLR                             BCH_CTRL_CLR_REG(BCH_BASE_PTR)
3283 #define BCH_CTRL_TOG                             BCH_CTRL_TOG_REG(BCH_BASE_PTR)
3284 #define BCH_STATUS0                              BCH_STATUS0_REG(BCH_BASE_PTR)
3285 #define BCH_STATUS0_SET                          BCH_STATUS0_SET_REG(BCH_BASE_PTR)
3286 #define BCH_STATUS0_CLR                          BCH_STATUS0_CLR_REG(BCH_BASE_PTR)
3287 #define BCH_STATUS0_TOG                          BCH_STATUS0_TOG_REG(BCH_BASE_PTR)
3288 #define BCH_MODE                                 BCH_MODE_REG(BCH_BASE_PTR)
3289 #define BCH_MODE_SET                             BCH_MODE_SET_REG(BCH_BASE_PTR)
3290 #define BCH_MODE_CLR                             BCH_MODE_CLR_REG(BCH_BASE_PTR)
3291 #define BCH_MODE_TOG                             BCH_MODE_TOG_REG(BCH_BASE_PTR)
3292 #define BCH_ENCODEPTR                            BCH_ENCODEPTR_REG(BCH_BASE_PTR)
3293 #define BCH_ENCODEPTR_SET                        BCH_ENCODEPTR_SET_REG(BCH_BASE_PTR)
3294 #define BCH_ENCODEPTR_CLR                        BCH_ENCODEPTR_CLR_REG(BCH_BASE_PTR)
3295 #define BCH_ENCODEPTR_TOG                        BCH_ENCODEPTR_TOG_REG(BCH_BASE_PTR)
3296 #define BCH_DATAPTR                              BCH_DATAPTR_REG(BCH_BASE_PTR)
3297 #define BCH_DATAPTR_SET                          BCH_DATAPTR_SET_REG(BCH_BASE_PTR)
3298 #define BCH_DATAPTR_CLR                          BCH_DATAPTR_CLR_REG(BCH_BASE_PTR)
3299 #define BCH_DATAPTR_TOG                          BCH_DATAPTR_TOG_REG(BCH_BASE_PTR)
3300 #define BCH_METAPTR                              BCH_METAPTR_REG(BCH_BASE_PTR)
3301 #define BCH_METAPTR_SET                          BCH_METAPTR_SET_REG(BCH_BASE_PTR)
3302 #define BCH_METAPTR_CLR                          BCH_METAPTR_CLR_REG(BCH_BASE_PTR)
3303 #define BCH_METAPTR_TOG                          BCH_METAPTR_TOG_REG(BCH_BASE_PTR)
3304 #define BCH_LAYOUTSELECT                         BCH_LAYOUTSELECT_REG(BCH_BASE_PTR)
3305 #define BCH_LAYOUTSELECT_SET                     BCH_LAYOUTSELECT_SET_REG(BCH_BASE_PTR)
3306 #define BCH_LAYOUTSELECT_CLR                     BCH_LAYOUTSELECT_CLR_REG(BCH_BASE_PTR)
3307 #define BCH_LAYOUTSELECT_TOG                     BCH_LAYOUTSELECT_TOG_REG(BCH_BASE_PTR)
3308 #define BCH_FLASH0LAYOUT0                        BCH_FLASH0LAYOUT0_REG(BCH_BASE_PTR)
3309 #define BCH_FLASH0LAYOUT0_SET                    BCH_FLASH0LAYOUT0_SET_REG(BCH_BASE_PTR)
3310 #define BCH_FLASH0LAYOUT0_CLR                    BCH_FLASH0LAYOUT0_CLR_REG(BCH_BASE_PTR)
3311 #define BCH_FLASH0LAYOUT0_TOG                    BCH_FLASH0LAYOUT0_TOG_REG(BCH_BASE_PTR)
3312 #define BCH_FLASH0LAYOUT1                        BCH_FLASH0LAYOUT1_REG(BCH_BASE_PTR)
3313 #define BCH_FLASH0LAYOUT1_SET                    BCH_FLASH0LAYOUT1_SET_REG(BCH_BASE_PTR)
3314 #define BCH_FLASH0LAYOUT1_CLR                    BCH_FLASH0LAYOUT1_CLR_REG(BCH_BASE_PTR)
3315 #define BCH_FLASH0LAYOUT1_TOG                    BCH_FLASH0LAYOUT1_TOG_REG(BCH_BASE_PTR)
3316 #define BCH_FLASH1LAYOUT0                        BCH_FLASH1LAYOUT0_REG(BCH_BASE_PTR)
3317 #define BCH_FLASH1LAYOUT0_SET                    BCH_FLASH1LAYOUT0_SET_REG(BCH_BASE_PTR)
3318 #define BCH_FLASH1LAYOUT0_CLR                    BCH_FLASH1LAYOUT0_CLR_REG(BCH_BASE_PTR)
3319 #define BCH_FLASH1LAYOUT0_TOG                    BCH_FLASH1LAYOUT0_TOG_REG(BCH_BASE_PTR)
3320 #define BCH_FLASH1LAYOUT1                        BCH_FLASH1LAYOUT1_REG(BCH_BASE_PTR)
3321 #define BCH_FLASH1LAYOUT1_SET                    BCH_FLASH1LAYOUT1_SET_REG(BCH_BASE_PTR)
3322 #define BCH_FLASH1LAYOUT1_CLR                    BCH_FLASH1LAYOUT1_CLR_REG(BCH_BASE_PTR)
3323 #define BCH_FLASH1LAYOUT1_TOG                    BCH_FLASH1LAYOUT1_TOG_REG(BCH_BASE_PTR)
3324 #define BCH_FLASH2LAYOUT0                        BCH_FLASH2LAYOUT0_REG(BCH_BASE_PTR)
3325 #define BCH_FLASH2LAYOUT0_SET                    BCH_FLASH2LAYOUT0_SET_REG(BCH_BASE_PTR)
3326 #define BCH_FLASH2LAYOUT0_CLR                    BCH_FLASH2LAYOUT0_CLR_REG(BCH_BASE_PTR)
3327 #define BCH_FLASH2LAYOUT0_TOG                    BCH_FLASH2LAYOUT0_TOG_REG(BCH_BASE_PTR)
3328 #define BCH_FLASH2LAYOUT1                        BCH_FLASH2LAYOUT1_REG(BCH_BASE_PTR)
3329 #define BCH_FLASH2LAYOUT1_SET                    BCH_FLASH2LAYOUT1_SET_REG(BCH_BASE_PTR)
3330 #define BCH_FLASH2LAYOUT1_CLR                    BCH_FLASH2LAYOUT1_CLR_REG(BCH_BASE_PTR)
3331 #define BCH_FLASH2LAYOUT1_TOG                    BCH_FLASH2LAYOUT1_TOG_REG(BCH_BASE_PTR)
3332 #define BCH_FLASH3LAYOUT0                        BCH_FLASH3LAYOUT0_REG(BCH_BASE_PTR)
3333 #define BCH_FLASH3LAYOUT0_SET                    BCH_FLASH3LAYOUT0_SET_REG(BCH_BASE_PTR)
3334 #define BCH_FLASH3LAYOUT0_CLR                    BCH_FLASH3LAYOUT0_CLR_REG(BCH_BASE_PTR)
3335 #define BCH_FLASH3LAYOUT0_TOG                    BCH_FLASH3LAYOUT0_TOG_REG(BCH_BASE_PTR)
3336 #define BCH_FLASH3LAYOUT1                        BCH_FLASH3LAYOUT1_REG(BCH_BASE_PTR)
3337 #define BCH_FLASH3LAYOUT1_SET                    BCH_FLASH3LAYOUT1_SET_REG(BCH_BASE_PTR)
3338 #define BCH_FLASH3LAYOUT1_CLR                    BCH_FLASH3LAYOUT1_CLR_REG(BCH_BASE_PTR)
3339 #define BCH_FLASH3LAYOUT1_TOG                    BCH_FLASH3LAYOUT1_TOG_REG(BCH_BASE_PTR)
3340 #define BCH_DEBUG0                               BCH_DEBUG0_REG(BCH_BASE_PTR)
3341 #define BCH_DEBUG0_SET                           BCH_DEBUG0_SET_REG(BCH_BASE_PTR)
3342 #define BCH_DEBUG0_CLR                           BCH_DEBUG0_CLR_REG(BCH_BASE_PTR)
3343 #define BCH_DEBUG0_TOG                           BCH_DEBUG0_TOG_REG(BCH_BASE_PTR)
3344 #define BCH_DBGKESREAD                           BCH_DBGKESREAD_REG(BCH_BASE_PTR)
3345 #define BCH_DBGKESREAD_SET                       BCH_DBGKESREAD_SET_REG(BCH_BASE_PTR)
3346 #define BCH_DBGKESREAD_CLR                       BCH_DBGKESREAD_CLR_REG(BCH_BASE_PTR)
3347 #define BCH_DBGKESREAD_TOG                       BCH_DBGKESREAD_TOG_REG(BCH_BASE_PTR)
3348 #define BCH_DBGCSFEREAD                          BCH_DBGCSFEREAD_REG(BCH_BASE_PTR)
3349 #define BCH_DBGCSFEREAD_SET                      BCH_DBGCSFEREAD_SET_REG(BCH_BASE_PTR)
3350 #define BCH_DBGCSFEREAD_CLR                      BCH_DBGCSFEREAD_CLR_REG(BCH_BASE_PTR)
3351 #define BCH_DBGCSFEREAD_TOG                      BCH_DBGCSFEREAD_TOG_REG(BCH_BASE_PTR)
3352 #define BCH_DBGSYNDGENREAD                       BCH_DBGSYNDGENREAD_REG(BCH_BASE_PTR)
3353 #define BCH_DBGSYNDGENREAD_SET                   BCH_DBGSYNDGENREAD_SET_REG(BCH_BASE_PTR)
3354 #define BCH_DBGSYNDGENREAD_CLR                   BCH_DBGSYNDGENREAD_CLR_REG(BCH_BASE_PTR)
3355 #define BCH_DBGSYNDGENREAD_TOG                   BCH_DBGSYNDGENREAD_TOG_REG(BCH_BASE_PTR)
3356 #define BCH_DBGAHBMREAD                          BCH_DBGAHBMREAD_REG(BCH_BASE_PTR)
3357 #define BCH_DBGAHBMREAD_SET                      BCH_DBGAHBMREAD_SET_REG(BCH_BASE_PTR)
3358 #define BCH_DBGAHBMREAD_CLR                      BCH_DBGAHBMREAD_CLR_REG(BCH_BASE_PTR)
3359 #define BCH_DBGAHBMREAD_TOG                      BCH_DBGAHBMREAD_TOG_REG(BCH_BASE_PTR)
3360 #define BCH_BLOCKNAME                            BCH_BLOCKNAME_REG(BCH_BASE_PTR)
3361 #define BCH_BLOCKNAME_SET                        BCH_BLOCKNAME_SET_REG(BCH_BASE_PTR)
3362 #define BCH_BLOCKNAME_CLR                        BCH_BLOCKNAME_CLR_REG(BCH_BASE_PTR)
3363 #define BCH_BLOCKNAME_TOG                        BCH_BLOCKNAME_TOG_REG(BCH_BASE_PTR)
3364 #define BCH_VERSION                              BCH_VERSION_REG(BCH_BASE_PTR)
3365 #define BCH_VERSION_SET                          BCH_VERSION_SET_REG(BCH_BASE_PTR)
3366 #define BCH_VERSION_CLR                          BCH_VERSION_CLR_REG(BCH_BASE_PTR)
3367 #define BCH_VERSION_TOG                          BCH_VERSION_TOG_REG(BCH_BASE_PTR)
3368 #define BCH_DEBUG1                               BCH_DEBUG1_REG(BCH_BASE_PTR)
3369 #define BCH_DEBUG1_SET                           BCH_DEBUG1_SET_REG(BCH_BASE_PTR)
3370 #define BCH_DEBUG1_CLR                           BCH_DEBUG1_CLR_REG(BCH_BASE_PTR)
3371 #define BCH_DEBUG1_TOG                           BCH_DEBUG1_TOG_REG(BCH_BASE_PTR)
3372 
3373 /*!
3374  * @}
3375  */ /* end of group BCH_Register_Accessor_Macros */
3376 
3377 /*!
3378  * @}
3379  */ /* end of group BCH_Peripheral */
3380 
3381 /* ----------------------------------------------------------------------------
3382    -- CAN Peripheral Access Layer
3383    ---------------------------------------------------------------------------- */
3384 
3385 /*!
3386  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3387  * @{
3388  */
3389 
3390 /** CAN - Register Layout Typedef */
3391 typedef struct {
3392   __IO  uint32_t MCR;                                    /**< Module Configuration Register, offset: 0x0 */
3393   __IO  uint32_t CTRL1;                                  /**< Control 1 Register, offset: 0x4 */
3394   __IO  uint32_t TIMER;                                  /**< Free Running Timer Register, offset: 0x8 */
3395   uint8_t RESERVED_0[4];
3396   __IO  uint32_t RXMGMASK;                               /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
3397   __IO  uint32_t RX14MASK;                               /**< Rx Buffer 14 Mask Register, offset: 0x14 */
3398   __IO  uint32_t RX15MASK;                               /**< Rx Buffer 15 Mask Register, offset: 0x18 */
3399   __IO  uint32_t ECR;                                    /**< Error Counter Register, offset: 0x1C */
3400   __IO  uint32_t ESR1;                                   /**< Error and Status 1 Register, offset: 0x20 */
3401   __IO  uint32_t IMASK2;                                 /**< Interrupt Masks 2 Register, offset: 0x24 */
3402   __IO  uint32_t IMASK1;                                 /**< Interrupt Masks 1 Register, offset: 0x28 */
3403   __IO  uint32_t IFLAG2;                                 /**< Interrupt Flags 2 Register, offset: 0x2C */
3404   __IO  uint32_t IFLAG1;                                 /**< Interrupt Flags 1 Register, offset: 0x30 */
3405   __IO  uint32_t CTRL2;                                  /**< Control 2 Register, offset: 0x34 */
3406   __I   uint32_t ESR2;                                   /**< Error and Status 2 Register, offset: 0x38 */
3407   uint8_t RESERVED_1[8];
3408   __I   uint32_t CRCR;                                   /**< CRC Register, offset: 0x44 */
3409   __IO  uint32_t RXFGMASK;                               /**< Rx FIFO Global Mask Register, offset: 0x48 */
3410   __I   uint32_t RXFIR;                                  /**< Rx FIFO Information Register, offset: 0x4C */
3411   uint8_t RESERVED_2[48];
3412   struct {                                         /* offset: 0x80, array step: 0x10 */
3413   __IO    uint32_t CS;                                     /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3414   __IO    uint32_t ID;                                     /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3415   __IO    uint32_t WORD0;                                  /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
3416   __IO    uint32_t WORD1;                                  /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
3417  } MB[64];
3418   uint8_t RESERVED_3[1024];
3419   __IO  uint32_t RXIMR[64];                              /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
3420   uint8_t RESERVED_4[96];
3421   __IO  uint32_t GFWR;                                   /**< Glitch Filter Width Registers, offset: 0x9E0 */
3422 } CAN_Type, *CAN_MemMapPtr;
3423 
3424 /* ----------------------------------------------------------------------------
3425    -- CAN - Register accessor macros
3426    ---------------------------------------------------------------------------- */
3427 
3428 /*!
3429  * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
3430  * @{
3431  */
3432 
3433 /* CAN - Register accessors */
3434 #define CAN_MCR_REG(base)                        ((base)->MCR)
3435 #define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
3436 #define CAN_TIMER_REG(base)                      ((base)->TIMER)
3437 #define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
3438 #define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
3439 #define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
3440 #define CAN_ECR_REG(base)                        ((base)->ECR)
3441 #define CAN_ESR1_REG(base)                       ((base)->ESR1)
3442 #define CAN_IMASK2_REG(base)                     ((base)->IMASK2)
3443 #define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
3444 #define CAN_IFLAG2_REG(base)                     ((base)->IFLAG2)
3445 #define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
3446 #define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
3447 #define CAN_ESR2_REG(base)                       ((base)->ESR2)
3448 #define CAN_CRCR_REG(base)                       ((base)->CRCR)
3449 #define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
3450 #define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
3451 #define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
3452 #define CAN_CS_COUNT                             64
3453 #define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
3454 #define CAN_ID_COUNT                             64
3455 #define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
3456 #define CAN_WORD0_COUNT                          64
3457 #define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
3458 #define CAN_WORD1_COUNT                          64
3459 #define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
3460 #define CAN_RXIMR_COUNT                          64
3461 #define CAN_GFWR_REG(base)                       ((base)->GFWR)
3462 
3463 /*!
3464  * @}
3465  */ /* end of group CAN_Register_Accessor_Macros */
3466 
3467 /* ----------------------------------------------------------------------------
3468    -- CAN Register Masks
3469    ---------------------------------------------------------------------------- */
3470 
3471 /*!
3472  * @addtogroup CAN_Register_Masks CAN Register Masks
3473  * @{
3474  */
3475 
3476 /* MCR Bit Fields */
3477 #define CAN_MCR_MAXMB_MASK                       0x7Fu
3478 #define CAN_MCR_MAXMB_SHIFT                      0
3479 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
3480 #define CAN_MCR_IDAM_MASK                        0x300u
3481 #define CAN_MCR_IDAM_SHIFT                       8
3482 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
3483 #define CAN_MCR_AEN_MASK                         0x1000u
3484 #define CAN_MCR_AEN_SHIFT                        12
3485 #define CAN_MCR_LPRIO_EN_MASK                    0x2000u
3486 #define CAN_MCR_LPRIO_EN_SHIFT                   13
3487 #define CAN_MCR_IRMQ_MASK                        0x10000u
3488 #define CAN_MCR_IRMQ_SHIFT                       16
3489 #define CAN_MCR_SRX_DIS_MASK                     0x20000u
3490 #define CAN_MCR_SRX_DIS_SHIFT                    17
3491 #define CAN_MCR_WAK_SRC_MASK                     0x80000u
3492 #define CAN_MCR_WAK_SRC_SHIFT                    19
3493 #define CAN_MCR_LPM_ACK_MASK                     0x100000u
3494 #define CAN_MCR_LPM_ACK_SHIFT                    20
3495 #define CAN_MCR_WRN_EN_MASK                      0x200000u
3496 #define CAN_MCR_WRN_EN_SHIFT                     21
3497 #define CAN_MCR_SLF_WAK_MASK                     0x400000u
3498 #define CAN_MCR_SLF_WAK_SHIFT                    22
3499 #define CAN_MCR_SUPV_MASK                        0x800000u
3500 #define CAN_MCR_SUPV_SHIFT                       23
3501 #define CAN_MCR_FRZ_ACK_MASK                     0x1000000u
3502 #define CAN_MCR_FRZ_ACK_SHIFT                    24
3503 #define CAN_MCR_SOFT_RST_MASK                    0x2000000u
3504 #define CAN_MCR_SOFT_RST_SHIFT                   25
3505 #define CAN_MCR_WAK_MSK_MASK                     0x4000000u
3506 #define CAN_MCR_WAK_MSK_SHIFT                    26
3507 #define CAN_MCR_NOT_RDY_MASK                     0x8000000u
3508 #define CAN_MCR_NOT_RDY_SHIFT                    27
3509 #define CAN_MCR_HALT_MASK                        0x10000000u
3510 #define CAN_MCR_HALT_SHIFT                       28
3511 #define CAN_MCR_RFEN_MASK                        0x20000000u
3512 #define CAN_MCR_RFEN_SHIFT                       29
3513 #define CAN_MCR_FRZ_MASK                         0x40000000u
3514 #define CAN_MCR_FRZ_SHIFT                        30
3515 #define CAN_MCR_MDIS_MASK                        0x80000000u
3516 #define CAN_MCR_MDIS_SHIFT                       31
3517 /* CTRL1 Bit Fields */
3518 #define CAN_CTRL1_PROP_SEG_MASK                  0x7u
3519 #define CAN_CTRL1_PROP_SEG_SHIFT                 0
3520 #define CAN_CTRL1_PROP_SEG(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROP_SEG_SHIFT))&CAN_CTRL1_PROP_SEG_MASK)
3521 #define CAN_CTRL1_LOM_MASK                       0x8u
3522 #define CAN_CTRL1_LOM_SHIFT                      3
3523 #define CAN_CTRL1_LBUF_MASK                      0x10u
3524 #define CAN_CTRL1_LBUF_SHIFT                     4
3525 #define CAN_CTRL1_TSYN_MASK                      0x20u
3526 #define CAN_CTRL1_TSYN_SHIFT                     5
3527 #define CAN_CTRL1_BOFF_REC_MASK                  0x40u
3528 #define CAN_CTRL1_BOFF_REC_SHIFT                 6
3529 #define CAN_CTRL1_SMP_MASK                       0x80u
3530 #define CAN_CTRL1_SMP_SHIFT                      7
3531 #define CAN_CTRL1_RWRN_MSK_MASK                  0x400u
3532 #define CAN_CTRL1_RWRN_MSK_SHIFT                 10
3533 #define CAN_CTRL1_TWRN_MSK_MASK                  0x800u
3534 #define CAN_CTRL1_TWRN_MSK_SHIFT                 11
3535 #define CAN_CTRL1_LPB_MASK                       0x1000u
3536 #define CAN_CTRL1_LPB_SHIFT                      12
3537 #define CAN_CTRL1_ERR_MSK_MASK                   0x4000u
3538 #define CAN_CTRL1_ERR_MSK_SHIFT                  14
3539 #define CAN_CTRL1_BOFF_MSK_MASK                  0x8000u
3540 #define CAN_CTRL1_BOFF_MSK_SHIFT                 15
3541 #define CAN_CTRL1_PSEG2_MASK                     0x70000u
3542 #define CAN_CTRL1_PSEG2_SHIFT                    16
3543 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
3544 #define CAN_CTRL1_PSEG1_MASK                     0x380000u
3545 #define CAN_CTRL1_PSEG1_SHIFT                    19
3546 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
3547 #define CAN_CTRL1_RJW_MASK                       0xC00000u
3548 #define CAN_CTRL1_RJW_SHIFT                      22
3549 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
3550 #define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
3551 #define CAN_CTRL1_PRESDIV_SHIFT                  24
3552 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
3553 /* TIMER Bit Fields */
3554 #define CAN_TIMER_TIMER_MASK                     0xFFFFu
3555 #define CAN_TIMER_TIMER_SHIFT                    0
3556 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
3557 /* RXMGMASK Bit Fields */
3558 #define CAN_RXMGMASK_MG31_MG0_MASK               0xFFFFFFFFu
3559 #define CAN_RXMGMASK_MG31_MG0_SHIFT              0
3560 #define CAN_RXMGMASK_MG31_MG0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG31_MG0_SHIFT))&CAN_RXMGMASK_MG31_MG0_MASK)
3561 /* RX14MASK Bit Fields */
3562 #define CAN_RX14MASK_RX14M31_RX14M0_MASK         0xFFFFFFFFu
3563 #define CAN_RX14MASK_RX14M31_RX14M0_SHIFT        0
3564 #define CAN_RX14MASK_RX14M31_RX14M0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M31_RX14M0_SHIFT))&CAN_RX14MASK_RX14M31_RX14M0_MASK)
3565 /* RX15MASK Bit Fields */
3566 #define CAN_RX15MASK_RX15M31_RX15M0_MASK         0xFFFFFFFFu
3567 #define CAN_RX15MASK_RX15M31_RX15M0_SHIFT        0
3568 #define CAN_RX15MASK_RX15M31_RX15M0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M31_RX15M0_SHIFT))&CAN_RX15MASK_RX15M31_RX15M0_MASK)
3569 /* ECR Bit Fields */
3570 #define CAN_ECR_Tx_Err_Counter_MASK              0xFFu
3571 #define CAN_ECR_Tx_Err_Counter_SHIFT             0
3572 #define CAN_ECR_Tx_Err_Counter(x)                (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Tx_Err_Counter_SHIFT))&CAN_ECR_Tx_Err_Counter_MASK)
3573 #define CAN_ECR_Rx_Err_Counter_MASK              0xFF00u
3574 #define CAN_ECR_Rx_Err_Counter_SHIFT             8
3575 #define CAN_ECR_Rx_Err_Counter(x)                (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Rx_Err_Counter_SHIFT))&CAN_ECR_Rx_Err_Counter_MASK)
3576 /* ESR1 Bit Fields */
3577 #define CAN_ESR1_WAK_INT_MASK                    0x1u
3578 #define CAN_ESR1_WAK_INT_SHIFT                   0
3579 #define CAN_ESR1_ERR_INT_MASK                    0x2u
3580 #define CAN_ESR1_ERR_INT_SHIFT                   1
3581 #define CAN_ESR1_BOFF_INT_MASK                   0x4u
3582 #define CAN_ESR1_BOFF_INT_SHIFT                  2
3583 #define CAN_ESR1_RX_MASK                         0x8u
3584 #define CAN_ESR1_RX_SHIFT                        3
3585 #define CAN_ESR1_FLT_CONF_MASK                   0x30u
3586 #define CAN_ESR1_FLT_CONF_SHIFT                  4
3587 #define CAN_ESR1_FLT_CONF(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLT_CONF_SHIFT))&CAN_ESR1_FLT_CONF_MASK)
3588 #define CAN_ESR1_TX_MASK                         0x40u
3589 #define CAN_ESR1_TX_SHIFT                        6
3590 #define CAN_ESR1_IDLE_MASK                       0x80u
3591 #define CAN_ESR1_IDLE_SHIFT                      7
3592 #define CAN_ESR1_RX_WRN_MASK                     0x100u
3593 #define CAN_ESR1_RX_WRN_SHIFT                    8
3594 #define CAN_ESR1_TX_WRN_MASK                     0x200u
3595 #define CAN_ESR1_TX_WRN_SHIFT                    9
3596 #define CAN_ESR1_STF_ERR_MASK                    0x400u
3597 #define CAN_ESR1_STF_ERR_SHIFT                   10
3598 #define CAN_ESR1_FRM_ERR_MASK                    0x800u
3599 #define CAN_ESR1_FRM_ERR_SHIFT                   11
3600 #define CAN_ESR1_CRC_ERR_MASK                    0x1000u
3601 #define CAN_ESR1_CRC_ERR_SHIFT                   12
3602 #define CAN_ESR1_ACK_ERR_MASK                    0x2000u
3603 #define CAN_ESR1_ACK_ERR_SHIFT                   13
3604 #define CAN_ESR1_BIT0_ERR_MASK                   0x4000u
3605 #define CAN_ESR1_BIT0_ERR_SHIFT                  14
3606 #define CAN_ESR1_BIT1_ERR_MASK                   0x8000u
3607 #define CAN_ESR1_BIT1_ERR_SHIFT                  15
3608 #define CAN_ESR1_RWRN_INT_MASK                   0x10000u
3609 #define CAN_ESR1_RWRN_INT_SHIFT                  16
3610 #define CAN_ESR1_TWRN_INT_MASK                   0x20000u
3611 #define CAN_ESR1_TWRN_INT_SHIFT                  17
3612 #define CAN_ESR1_SYNCH_MASK                      0x40000u
3613 #define CAN_ESR1_SYNCH_SHIFT                     18
3614 /* IMASK2 Bit Fields */
3615 #define CAN_IMASK2_BUF63M_BUF32M_MASK            0xFFFFFFFFu
3616 #define CAN_IMASK2_BUF63M_BUF32M_SHIFT           0
3617 #define CAN_IMASK2_BUF63M_BUF32M(x)              (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUF63M_BUF32M_SHIFT))&CAN_IMASK2_BUF63M_BUF32M_MASK)
3618 /* IMASK1 Bit Fields */
3619 #define CAN_IMASK1_BUF31M_BUF0M_MASK             0xFFFFFFFFu
3620 #define CAN_IMASK1_BUF31M_BUF0M_SHIFT            0
3621 #define CAN_IMASK1_BUF31M_BUF0M(x)               (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31M_BUF0M_SHIFT))&CAN_IMASK1_BUF31M_BUF0M_MASK)
3622 /* IFLAG2 Bit Fields */
3623 #define CAN_IFLAG2_BUF63I_BUF32I_MASK            0xFFFFFFFFu
3624 #define CAN_IFLAG2_BUF63I_BUF32I_SHIFT           0
3625 #define CAN_IFLAG2_BUF63I_BUF32I(x)              (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUF63I_BUF32I_SHIFT))&CAN_IFLAG2_BUF63I_BUF32I_MASK)
3626 /* IFLAG1 Bit Fields */
3627 #define CAN_IFLAG1_BUF4I_BUF0I_MASK              0x1Fu
3628 #define CAN_IFLAG1_BUF4I_BUF0I_SHIFT             0
3629 #define CAN_IFLAG1_BUF4I_BUF0I(x)                (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4I_BUF0I_SHIFT))&CAN_IFLAG1_BUF4I_BUF0I_MASK)
3630 #define CAN_IFLAG1_BUF5I_MASK                    0x20u
3631 #define CAN_IFLAG1_BUF5I_SHIFT                   5
3632 #define CAN_IFLAG1_BUF6I_MASK                    0x40u
3633 #define CAN_IFLAG1_BUF6I_SHIFT                   6
3634 #define CAN_IFLAG1_BUF7I_MASK                    0x80u
3635 #define CAN_IFLAG1_BUF7I_SHIFT                   7
3636 #define CAN_IFLAG1_BUF31I_BUF8I_MASK             0xFFFFFF00u
3637 #define CAN_IFLAG1_BUF31I_BUF8I_SHIFT            8
3638 #define CAN_IFLAG1_BUF31I_BUF8I(x)               (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31I_BUF8I_SHIFT))&CAN_IFLAG1_BUF31I_BUF8I_MASK)
3639 /* CTRL2 Bit Fields */
3640 #define CAN_CTRL2_EACEN_MASK                     0x10000u
3641 #define CAN_CTRL2_EACEN_SHIFT                    16
3642 #define CAN_CTRL2_RRS_MASK                       0x20000u
3643 #define CAN_CTRL2_RRS_SHIFT                      17
3644 #define CAN_CTRL2_MRP_MASK                       0x40000u
3645 #define CAN_CTRL2_MRP_SHIFT                      18
3646 #define CAN_CTRL2_TASD_MASK                      0xF80000u
3647 #define CAN_CTRL2_TASD_SHIFT                     19
3648 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
3649 #define CAN_CTRL2_RFFN_MASK                      0xF000000u
3650 #define CAN_CTRL2_RFFN_SHIFT                     24
3651 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
3652 #define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
3653 #define CAN_CTRL2_WRMFRZ_SHIFT                   28
3654 /* ESR2 Bit Fields */
3655 #define CAN_ESR2_IMB_MASK                        0x2000u
3656 #define CAN_ESR2_IMB_SHIFT                       13
3657 #define CAN_ESR2_VPS_MASK                        0x4000u
3658 #define CAN_ESR2_VPS_SHIFT                       14
3659 #define CAN_ESR2_LPTM_MASK                       0x7F0000u
3660 #define CAN_ESR2_LPTM_SHIFT                      16
3661 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
3662 /* CRCR Bit Fields */
3663 #define CAN_CRCR_TXCRC_MASK                      0x7FFFu
3664 #define CAN_CRCR_TXCRC_SHIFT                     0
3665 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
3666 #define CAN_CRCR_MBCRC_MASK                      0x7F0000u
3667 #define CAN_CRCR_MBCRC_SHIFT                     16
3668 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
3669 /* RXFGMASK Bit Fields */
3670 #define CAN_RXFGMASK_FGM31_FGM0_MASK             0xFFFFFFFFu
3671 #define CAN_RXFGMASK_FGM31_FGM0_SHIFT            0
3672 #define CAN_RXFGMASK_FGM31_FGM0(x)               (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM31_FGM0_SHIFT))&CAN_RXFGMASK_FGM31_FGM0_MASK)
3673 /* RXFIR Bit Fields */
3674 #define CAN_RXFIR_IDHIT_MASK                     0x1FFu
3675 #define CAN_RXFIR_IDHIT_SHIFT                    0
3676 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
3677 /* CS Bit Fields */
3678 #define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
3679 #define CAN_CS_TIME_STAMP_SHIFT                  0
3680 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
3681 #define CAN_CS_DLC_MASK                          0xF0000u
3682 #define CAN_CS_DLC_SHIFT                         16
3683 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
3684 #define CAN_CS_RTR_MASK                          0x100000u
3685 #define CAN_CS_RTR_SHIFT                         20
3686 #define CAN_CS_IDE_MASK                          0x200000u
3687 #define CAN_CS_IDE_SHIFT                         21
3688 #define CAN_CS_SRR_MASK                          0x400000u
3689 #define CAN_CS_SRR_SHIFT                         22
3690 #define CAN_CS_CODE_MASK                         0xF000000u
3691 #define CAN_CS_CODE_SHIFT                        24
3692 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
3693 /* ID Bit Fields */
3694 #define CAN_ID_EXT_MASK                          0x3FFFFu
3695 #define CAN_ID_EXT_SHIFT                         0
3696 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
3697 #define CAN_ID_STD_MASK                          0x1FFC0000u
3698 #define CAN_ID_STD_SHIFT                         18
3699 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
3700 #define CAN_ID_PRIO_MASK                         0xE0000000u
3701 #define CAN_ID_PRIO_SHIFT                        29
3702 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
3703 /* WORD0 Bit Fields */
3704 #define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
3705 #define CAN_WORD0_DATA_BYTE_3_SHIFT              0
3706 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
3707 #define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
3708 #define CAN_WORD0_DATA_BYTE_2_SHIFT              8
3709 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
3710 #define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
3711 #define CAN_WORD0_DATA_BYTE_1_SHIFT              16
3712 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
3713 #define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
3714 #define CAN_WORD0_DATA_BYTE_0_SHIFT              24
3715 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
3716 /* WORD1 Bit Fields */
3717 #define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
3718 #define CAN_WORD1_DATA_BYTE_7_SHIFT              0
3719 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
3720 #define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
3721 #define CAN_WORD1_DATA_BYTE_6_SHIFT              8
3722 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
3723 #define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
3724 #define CAN_WORD1_DATA_BYTE_5_SHIFT              16
3725 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
3726 #define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
3727 #define CAN_WORD1_DATA_BYTE_4_SHIFT              24
3728 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
3729 /* RXIMR Bit Fields */
3730 #define CAN_RXIMR0_RXIMR63_MI31_MI0_MASK         0xFFFFFFFFu
3731 #define CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT        0
3732 #define CAN_RXIMR0_RXIMR63_MI31_MI0(x)           (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT))&CAN_RXIMR0_RXIMR63_MI31_MI0_MASK)
3733 /* GFWR Bit Fields */
3734 #define CAN_GFWR_GFWR_MASK                       0xFFu
3735 #define CAN_GFWR_GFWR_SHIFT                      0
3736 #define CAN_GFWR_GFWR(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_GFWR_GFWR_SHIFT))&CAN_GFWR_GFWR_MASK)
3737 
3738 /*!
3739  * @}
3740  */ /* end of group CAN_Register_Masks */
3741 
3742 /* CAN - Peripheral instance base addresses */
3743 /** Peripheral CAN1 base address */
3744 #define CAN1_BASE                                (0x42090000u)
3745 /** Peripheral CAN1 base pointer */
3746 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
3747 #define CAN1_BASE_PTR                            (CAN1)
3748 /** Peripheral CAN2 base address */
3749 #define CAN2_BASE                                (0x42094000u)
3750 /** Peripheral CAN2 base pointer */
3751 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
3752 #define CAN2_BASE_PTR                            (CAN2)
3753 /** Array initializer of CAN peripheral base addresses */
3754 #define CAN_BASE_ADDRS                           { CAN1_BASE, CAN2_BASE }
3755 /** Array initializer of CAN peripheral base pointers */
3756 #define CAN_BASE_PTRS                            { CAN1, CAN2 }
3757 /** Interrupt vectors for the CAN peripheral type */
3758 #define CAN_IRQS                                 { FLEXCAN1_IRQn, FLEXCAN2_IRQn }
3759 
3760 /* ----------------------------------------------------------------------------
3761    -- CAN - Register accessor macros
3762    ---------------------------------------------------------------------------- */
3763 
3764 /*!
3765  * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
3766  * @{
3767  */
3768 
3769 /* CAN - Register instance definitions */
3770 /* CAN1 */
3771 #define CAN1_MCR                                 CAN_MCR_REG(CAN1_BASE_PTR)
3772 #define CAN1_CTRL1                               CAN_CTRL1_REG(CAN1_BASE_PTR)
3773 #define CAN1_TIMER                               CAN_TIMER_REG(CAN1_BASE_PTR)
3774 #define CAN1_RXMGMASK                            CAN_RXMGMASK_REG(CAN1_BASE_PTR)
3775 #define CAN1_RX14MASK                            CAN_RX14MASK_REG(CAN1_BASE_PTR)
3776 #define CAN1_RX15MASK                            CAN_RX15MASK_REG(CAN1_BASE_PTR)
3777 #define CAN1_ECR                                 CAN_ECR_REG(CAN1_BASE_PTR)
3778 #define CAN1_ESR1                                CAN_ESR1_REG(CAN1_BASE_PTR)
3779 #define CAN1_IMASK2                              CAN_IMASK2_REG(CAN1_BASE_PTR)
3780 #define CAN1_IMASK1                              CAN_IMASK1_REG(CAN1_BASE_PTR)
3781 #define CAN1_IFLAG2                              CAN_IFLAG2_REG(CAN1_BASE_PTR)
3782 #define CAN1_IFLAG1                              CAN_IFLAG1_REG(CAN1_BASE_PTR)
3783 #define CAN1_CTRL2                               CAN_CTRL2_REG(CAN1_BASE_PTR)
3784 #define CAN1_ESR2                                CAN_ESR2_REG(CAN1_BASE_PTR)
3785 #define CAN1_CRCR                                CAN_CRCR_REG(CAN1_BASE_PTR)
3786 #define CAN1_RXFGMASK                            CAN_RXFGMASK_REG(CAN1_BASE_PTR)
3787 #define CAN1_RXFIR                               CAN_RXFIR_REG(CAN1_BASE_PTR)
3788 #define CAN1_CS0                                 CAN_CS_REG(CAN1_BASE_PTR,0)
3789 #define CAN1_ID0                                 CAN_ID_REG(CAN1_BASE_PTR,0)
3790 #define CAN1_WORD00                              CAN_WORD0_REG(CAN1_BASE_PTR,0)
3791 #define CAN1_WORD10                              CAN_WORD1_REG(CAN1_BASE_PTR,0)
3792 #define CAN1_CS1                                 CAN_CS_REG(CAN1_BASE_PTR,1)
3793 #define CAN1_ID1                                 CAN_ID_REG(CAN1_BASE_PTR,1)
3794 #define CAN1_WORD01                              CAN_WORD0_REG(CAN1_BASE_PTR,1)
3795 #define CAN1_WORD11                              CAN_WORD1_REG(CAN1_BASE_PTR,1)
3796 #define CAN1_CS2                                 CAN_CS_REG(CAN1_BASE_PTR,2)
3797 #define CAN1_ID2                                 CAN_ID_REG(CAN1_BASE_PTR,2)
3798 #define CAN1_WORD02                              CAN_WORD0_REG(CAN1_BASE_PTR,2)
3799 #define CAN1_WORD12                              CAN_WORD1_REG(CAN1_BASE_PTR,2)
3800 #define CAN1_CS3                                 CAN_CS_REG(CAN1_BASE_PTR,3)
3801 #define CAN1_ID3                                 CAN_ID_REG(CAN1_BASE_PTR,3)
3802 #define CAN1_WORD03                              CAN_WORD0_REG(CAN1_BASE_PTR,3)
3803 #define CAN1_WORD13                              CAN_WORD1_REG(CAN1_BASE_PTR,3)
3804 #define CAN1_CS4                                 CAN_CS_REG(CAN1_BASE_PTR,4)
3805 #define CAN1_ID4                                 CAN_ID_REG(CAN1_BASE_PTR,4)
3806 #define CAN1_WORD04                              CAN_WORD0_REG(CAN1_BASE_PTR,4)
3807 #define CAN1_WORD14                              CAN_WORD1_REG(CAN1_BASE_PTR,4)
3808 #define CAN1_CS5                                 CAN_CS_REG(CAN1_BASE_PTR,5)
3809 #define CAN1_ID5                                 CAN_ID_REG(CAN1_BASE_PTR,5)
3810 #define CAN1_WORD05                              CAN_WORD0_REG(CAN1_BASE_PTR,5)
3811 #define CAN1_WORD15                              CAN_WORD1_REG(CAN1_BASE_PTR,5)
3812 #define CAN1_CS6                                 CAN_CS_REG(CAN1_BASE_PTR,6)
3813 #define CAN1_ID6                                 CAN_ID_REG(CAN1_BASE_PTR,6)
3814 #define CAN1_WORD06                              CAN_WORD0_REG(CAN1_BASE_PTR,6)
3815 #define CAN1_WORD16                              CAN_WORD1_REG(CAN1_BASE_PTR,6)
3816 #define CAN1_CS7                                 CAN_CS_REG(CAN1_BASE_PTR,7)
3817 #define CAN1_ID7                                 CAN_ID_REG(CAN1_BASE_PTR,7)
3818 #define CAN1_WORD07                              CAN_WORD0_REG(CAN1_BASE_PTR,7)
3819 #define CAN1_WORD17                              CAN_WORD1_REG(CAN1_BASE_PTR,7)
3820 #define CAN1_CS8                                 CAN_CS_REG(CAN1_BASE_PTR,8)
3821 #define CAN1_ID8                                 CAN_ID_REG(CAN1_BASE_PTR,8)
3822 #define CAN1_WORD08                              CAN_WORD0_REG(CAN1_BASE_PTR,8)
3823 #define CAN1_WORD18                              CAN_WORD1_REG(CAN1_BASE_PTR,8)
3824 #define CAN1_CS9                                 CAN_CS_REG(CAN1_BASE_PTR,9)
3825 #define CAN1_ID9                                 CAN_ID_REG(CAN1_BASE_PTR,9)
3826 #define CAN1_WORD09                              CAN_WORD0_REG(CAN1_BASE_PTR,9)
3827 #define CAN1_WORD19                              CAN_WORD1_REG(CAN1_BASE_PTR,9)
3828 #define CAN1_CS10                                CAN_CS_REG(CAN1_BASE_PTR,10)
3829 #define CAN1_ID10                                CAN_ID_REG(CAN1_BASE_PTR,10)
3830 #define CAN1_WORD010                             CAN_WORD0_REG(CAN1_BASE_PTR,10)
3831 #define CAN1_WORD110                             CAN_WORD1_REG(CAN1_BASE_PTR,10)
3832 #define CAN1_CS11                                CAN_CS_REG(CAN1_BASE_PTR,11)
3833 #define CAN1_ID11                                CAN_ID_REG(CAN1_BASE_PTR,11)
3834 #define CAN1_WORD011                             CAN_WORD0_REG(CAN1_BASE_PTR,11)
3835 #define CAN1_WORD111                             CAN_WORD1_REG(CAN1_BASE_PTR,11)
3836 #define CAN1_CS12                                CAN_CS_REG(CAN1_BASE_PTR,12)
3837 #define CAN1_ID12                                CAN_ID_REG(CAN1_BASE_PTR,12)
3838 #define CAN1_WORD012                             CAN_WORD0_REG(CAN1_BASE_PTR,12)
3839 #define CAN1_WORD112                             CAN_WORD1_REG(CAN1_BASE_PTR,12)
3840 #define CAN1_CS13                                CAN_CS_REG(CAN1_BASE_PTR,13)
3841 #define CAN1_ID13                                CAN_ID_REG(CAN1_BASE_PTR,13)
3842 #define CAN1_WORD013                             CAN_WORD0_REG(CAN1_BASE_PTR,13)
3843 #define CAN1_WORD113                             CAN_WORD1_REG(CAN1_BASE_PTR,13)
3844 #define CAN1_CS14                                CAN_CS_REG(CAN1_BASE_PTR,14)
3845 #define CAN1_ID14                                CAN_ID_REG(CAN1_BASE_PTR,14)
3846 #define CAN1_WORD014                             CAN_WORD0_REG(CAN1_BASE_PTR,14)
3847 #define CAN1_WORD114                             CAN_WORD1_REG(CAN1_BASE_PTR,14)
3848 #define CAN1_CS15                                CAN_CS_REG(CAN1_BASE_PTR,15)
3849 #define CAN1_ID15                                CAN_ID_REG(CAN1_BASE_PTR,15)
3850 #define CAN1_WORD015                             CAN_WORD0_REG(CAN1_BASE_PTR,15)
3851 #define CAN1_WORD115                             CAN_WORD1_REG(CAN1_BASE_PTR,15)
3852 #define CAN1_CS16                                CAN_CS_REG(CAN1_BASE_PTR,16)
3853 #define CAN1_ID16                                CAN_ID_REG(CAN1_BASE_PTR,16)
3854 #define CAN1_WORD016                             CAN_WORD0_REG(CAN1_BASE_PTR,16)
3855 #define CAN1_WORD116                             CAN_WORD1_REG(CAN1_BASE_PTR,16)
3856 #define CAN1_CS17                                CAN_CS_REG(CAN1_BASE_PTR,17)
3857 #define CAN1_ID17                                CAN_ID_REG(CAN1_BASE_PTR,17)
3858 #define CAN1_WORD017                             CAN_WORD0_REG(CAN1_BASE_PTR,17)
3859 #define CAN1_WORD117                             CAN_WORD1_REG(CAN1_BASE_PTR,17)
3860 #define CAN1_CS18                                CAN_CS_REG(CAN1_BASE_PTR,18)
3861 #define CAN1_ID18                                CAN_ID_REG(CAN1_BASE_PTR,18)
3862 #define CAN1_WORD018                             CAN_WORD0_REG(CAN1_BASE_PTR,18)
3863 #define CAN1_WORD118                             CAN_WORD1_REG(CAN1_BASE_PTR,18)
3864 #define CAN1_CS19                                CAN_CS_REG(CAN1_BASE_PTR,19)
3865 #define CAN1_ID19                                CAN_ID_REG(CAN1_BASE_PTR,19)
3866 #define CAN1_WORD019                             CAN_WORD0_REG(CAN1_BASE_PTR,19)
3867 #define CAN1_WORD119                             CAN_WORD1_REG(CAN1_BASE_PTR,19)
3868 #define CAN1_CS20                                CAN_CS_REG(CAN1_BASE_PTR,20)
3869 #define CAN1_ID20                                CAN_ID_REG(CAN1_BASE_PTR,20)
3870 #define CAN1_WORD020                             CAN_WORD0_REG(CAN1_BASE_PTR,20)
3871 #define CAN1_WORD120                             CAN_WORD1_REG(CAN1_BASE_PTR,20)
3872 #define CAN1_CS21                                CAN_CS_REG(CAN1_BASE_PTR,21)
3873 #define CAN1_ID21                                CAN_ID_REG(CAN1_BASE_PTR,21)
3874 #define CAN1_WORD021                             CAN_WORD0_REG(CAN1_BASE_PTR,21)
3875 #define CAN1_WORD121                             CAN_WORD1_REG(CAN1_BASE_PTR,21)
3876 #define CAN1_CS22                                CAN_CS_REG(CAN1_BASE_PTR,22)
3877 #define CAN1_ID22                                CAN_ID_REG(CAN1_BASE_PTR,22)
3878 #define CAN1_WORD022                             CAN_WORD0_REG(CAN1_BASE_PTR,22)
3879 #define CAN1_WORD122                             CAN_WORD1_REG(CAN1_BASE_PTR,22)
3880 #define CAN1_CS23                                CAN_CS_REG(CAN1_BASE_PTR,23)
3881 #define CAN1_ID23                                CAN_ID_REG(CAN1_BASE_PTR,23)
3882 #define CAN1_WORD023                             CAN_WORD0_REG(CAN1_BASE_PTR,23)
3883 #define CAN1_WORD123                             CAN_WORD1_REG(CAN1_BASE_PTR,23)
3884 #define CAN1_CS24                                CAN_CS_REG(CAN1_BASE_PTR,24)
3885 #define CAN1_ID24                                CAN_ID_REG(CAN1_BASE_PTR,24)
3886 #define CAN1_WORD024                             CAN_WORD0_REG(CAN1_BASE_PTR,24)
3887 #define CAN1_WORD124                             CAN_WORD1_REG(CAN1_BASE_PTR,24)
3888 #define CAN1_CS25                                CAN_CS_REG(CAN1_BASE_PTR,25)
3889 #define CAN1_ID25                                CAN_ID_REG(CAN1_BASE_PTR,25)
3890 #define CAN1_WORD025                             CAN_WORD0_REG(CAN1_BASE_PTR,25)
3891 #define CAN1_WORD125                             CAN_WORD1_REG(CAN1_BASE_PTR,25)
3892 #define CAN1_CS26                                CAN_CS_REG(CAN1_BASE_PTR,26)
3893 #define CAN1_ID26                                CAN_ID_REG(CAN1_BASE_PTR,26)
3894 #define CAN1_WORD026                             CAN_WORD0_REG(CAN1_BASE_PTR,26)
3895 #define CAN1_WORD126                             CAN_WORD1_REG(CAN1_BASE_PTR,26)
3896 #define CAN1_CS27                                CAN_CS_REG(CAN1_BASE_PTR,27)
3897 #define CAN1_ID27                                CAN_ID_REG(CAN1_BASE_PTR,27)
3898 #define CAN1_WORD027                             CAN_WORD0_REG(CAN1_BASE_PTR,27)
3899 #define CAN1_WORD127                             CAN_WORD1_REG(CAN1_BASE_PTR,27)
3900 #define CAN1_CS28                                CAN_CS_REG(CAN1_BASE_PTR,28)
3901 #define CAN1_ID28                                CAN_ID_REG(CAN1_BASE_PTR,28)
3902 #define CAN1_WORD028                             CAN_WORD0_REG(CAN1_BASE_PTR,28)
3903 #define CAN1_WORD128                             CAN_WORD1_REG(CAN1_BASE_PTR,28)
3904 #define CAN1_CS29                                CAN_CS_REG(CAN1_BASE_PTR,29)
3905 #define CAN1_ID29                                CAN_ID_REG(CAN1_BASE_PTR,29)
3906 #define CAN1_WORD029                             CAN_WORD0_REG(CAN1_BASE_PTR,29)
3907 #define CAN1_WORD129                             CAN_WORD1_REG(CAN1_BASE_PTR,29)
3908 #define CAN1_CS30                                CAN_CS_REG(CAN1_BASE_PTR,30)
3909 #define CAN1_ID30                                CAN_ID_REG(CAN1_BASE_PTR,30)
3910 #define CAN1_WORD030                             CAN_WORD0_REG(CAN1_BASE_PTR,30)
3911 #define CAN1_WORD130                             CAN_WORD1_REG(CAN1_BASE_PTR,30)
3912 #define CAN1_CS31                                CAN_CS_REG(CAN1_BASE_PTR,31)
3913 #define CAN1_ID31                                CAN_ID_REG(CAN1_BASE_PTR,31)
3914 #define CAN1_WORD031                             CAN_WORD0_REG(CAN1_BASE_PTR,31)
3915 #define CAN1_WORD131                             CAN_WORD1_REG(CAN1_BASE_PTR,31)
3916 #define CAN1_CS32                                CAN_CS_REG(CAN1_BASE_PTR,32)
3917 #define CAN1_ID32                                CAN_ID_REG(CAN1_BASE_PTR,32)
3918 #define CAN1_WORD032                             CAN_WORD0_REG(CAN1_BASE_PTR,32)
3919 #define CAN1_WORD132                             CAN_WORD1_REG(CAN1_BASE_PTR,32)
3920 #define CAN1_CS33                                CAN_CS_REG(CAN1_BASE_PTR,33)
3921 #define CAN1_ID33                                CAN_ID_REG(CAN1_BASE_PTR,33)
3922 #define CAN1_WORD033                             CAN_WORD0_REG(CAN1_BASE_PTR,33)
3923 #define CAN1_WORD133                             CAN_WORD1_REG(CAN1_BASE_PTR,33)
3924 #define CAN1_CS34                                CAN_CS_REG(CAN1_BASE_PTR,34)
3925 #define CAN1_ID34                                CAN_ID_REG(CAN1_BASE_PTR,34)
3926 #define CAN1_WORD034                             CAN_WORD0_REG(CAN1_BASE_PTR,34)
3927 #define CAN1_WORD134                             CAN_WORD1_REG(CAN1_BASE_PTR,34)
3928 #define CAN1_CS35                                CAN_CS_REG(CAN1_BASE_PTR,35)
3929 #define CAN1_ID35                                CAN_ID_REG(CAN1_BASE_PTR,35)
3930 #define CAN1_WORD035                             CAN_WORD0_REG(CAN1_BASE_PTR,35)
3931 #define CAN1_WORD135                             CAN_WORD1_REG(CAN1_BASE_PTR,35)
3932 #define CAN1_CS36                                CAN_CS_REG(CAN1_BASE_PTR,36)
3933 #define CAN1_ID36                                CAN_ID_REG(CAN1_BASE_PTR,36)
3934 #define CAN1_WORD036                             CAN_WORD0_REG(CAN1_BASE_PTR,36)
3935 #define CAN1_WORD136                             CAN_WORD1_REG(CAN1_BASE_PTR,36)
3936 #define CAN1_CS37                                CAN_CS_REG(CAN1_BASE_PTR,37)
3937 #define CAN1_ID37                                CAN_ID_REG(CAN1_BASE_PTR,37)
3938 #define CAN1_WORD037                             CAN_WORD0_REG(CAN1_BASE_PTR,37)
3939 #define CAN1_WORD137                             CAN_WORD1_REG(CAN1_BASE_PTR,37)
3940 #define CAN1_CS38                                CAN_CS_REG(CAN1_BASE_PTR,38)
3941 #define CAN1_ID38                                CAN_ID_REG(CAN1_BASE_PTR,38)
3942 #define CAN1_WORD038                             CAN_WORD0_REG(CAN1_BASE_PTR,38)
3943 #define CAN1_WORD138                             CAN_WORD1_REG(CAN1_BASE_PTR,38)
3944 #define CAN1_CS39                                CAN_CS_REG(CAN1_BASE_PTR,39)
3945 #define CAN1_ID39                                CAN_ID_REG(CAN1_BASE_PTR,39)
3946 #define CAN1_WORD039                             CAN_WORD0_REG(CAN1_BASE_PTR,39)
3947 #define CAN1_WORD139                             CAN_WORD1_REG(CAN1_BASE_PTR,39)
3948 #define CAN1_CS40                                CAN_CS_REG(CAN1_BASE_PTR,40)
3949 #define CAN1_ID40                                CAN_ID_REG(CAN1_BASE_PTR,40)
3950 #define CAN1_WORD040                             CAN_WORD0_REG(CAN1_BASE_PTR,40)
3951 #define CAN1_WORD140                             CAN_WORD1_REG(CAN1_BASE_PTR,40)
3952 #define CAN1_CS41                                CAN_CS_REG(CAN1_BASE_PTR,41)
3953 #define CAN1_ID41                                CAN_ID_REG(CAN1_BASE_PTR,41)
3954 #define CAN1_WORD041                             CAN_WORD0_REG(CAN1_BASE_PTR,41)
3955 #define CAN1_WORD141                             CAN_WORD1_REG(CAN1_BASE_PTR,41)
3956 #define CAN1_CS42                                CAN_CS_REG(CAN1_BASE_PTR,42)
3957 #define CAN1_ID42                                CAN_ID_REG(CAN1_BASE_PTR,42)
3958 #define CAN1_WORD042                             CAN_WORD0_REG(CAN1_BASE_PTR,42)
3959 #define CAN1_WORD142                             CAN_WORD1_REG(CAN1_BASE_PTR,42)
3960 #define CAN1_CS43                                CAN_CS_REG(CAN1_BASE_PTR,43)
3961 #define CAN1_ID43                                CAN_ID_REG(CAN1_BASE_PTR,43)
3962 #define CAN1_WORD043                             CAN_WORD0_REG(CAN1_BASE_PTR,43)
3963 #define CAN1_WORD143                             CAN_WORD1_REG(CAN1_BASE_PTR,43)
3964 #define CAN1_CS44                                CAN_CS_REG(CAN1_BASE_PTR,44)
3965 #define CAN1_ID44                                CAN_ID_REG(CAN1_BASE_PTR,44)
3966 #define CAN1_WORD044                             CAN_WORD0_REG(CAN1_BASE_PTR,44)
3967 #define CAN1_WORD144                             CAN_WORD1_REG(CAN1_BASE_PTR,44)
3968 #define CAN1_CS45                                CAN_CS_REG(CAN1_BASE_PTR,45)
3969 #define CAN1_ID45                                CAN_ID_REG(CAN1_BASE_PTR,45)
3970 #define CAN1_WORD045                             CAN_WORD0_REG(CAN1_BASE_PTR,45)
3971 #define CAN1_WORD145                             CAN_WORD1_REG(CAN1_BASE_PTR,45)
3972 #define CAN1_CS46                                CAN_CS_REG(CAN1_BASE_PTR,46)
3973 #define CAN1_ID46                                CAN_ID_REG(CAN1_BASE_PTR,46)
3974 #define CAN1_WORD046                             CAN_WORD0_REG(CAN1_BASE_PTR,46)
3975 #define CAN1_WORD146                             CAN_WORD1_REG(CAN1_BASE_PTR,46)
3976 #define CAN1_CS47                                CAN_CS_REG(CAN1_BASE_PTR,47)
3977 #define CAN1_ID47                                CAN_ID_REG(CAN1_BASE_PTR,47)
3978 #define CAN1_WORD047                             CAN_WORD0_REG(CAN1_BASE_PTR,47)
3979 #define CAN1_WORD147                             CAN_WORD1_REG(CAN1_BASE_PTR,47)
3980 #define CAN1_CS48                                CAN_CS_REG(CAN1_BASE_PTR,48)
3981 #define CAN1_ID48                                CAN_ID_REG(CAN1_BASE_PTR,48)
3982 #define CAN1_WORD048                             CAN_WORD0_REG(CAN1_BASE_PTR,48)
3983 #define CAN1_WORD148                             CAN_WORD1_REG(CAN1_BASE_PTR,48)
3984 #define CAN1_CS49                                CAN_CS_REG(CAN1_BASE_PTR,49)
3985 #define CAN1_ID49                                CAN_ID_REG(CAN1_BASE_PTR,49)
3986 #define CAN1_WORD049                             CAN_WORD0_REG(CAN1_BASE_PTR,49)
3987 #define CAN1_WORD149                             CAN_WORD1_REG(CAN1_BASE_PTR,49)
3988 #define CAN1_CS50                                CAN_CS_REG(CAN1_BASE_PTR,50)
3989 #define CAN1_ID50                                CAN_ID_REG(CAN1_BASE_PTR,50)
3990 #define CAN1_WORD050                             CAN_WORD0_REG(CAN1_BASE_PTR,50)
3991 #define CAN1_WORD150                             CAN_WORD1_REG(CAN1_BASE_PTR,50)
3992 #define CAN1_CS51                                CAN_CS_REG(CAN1_BASE_PTR,51)
3993 #define CAN1_ID51                                CAN_ID_REG(CAN1_BASE_PTR,51)
3994 #define CAN1_WORD051                             CAN_WORD0_REG(CAN1_BASE_PTR,51)
3995 #define CAN1_WORD151                             CAN_WORD1_REG(CAN1_BASE_PTR,51)
3996 #define CAN1_CS52                                CAN_CS_REG(CAN1_BASE_PTR,52)
3997 #define CAN1_ID52                                CAN_ID_REG(CAN1_BASE_PTR,52)
3998 #define CAN1_WORD052                             CAN_WORD0_REG(CAN1_BASE_PTR,52)
3999 #define CAN1_WORD152                             CAN_WORD1_REG(CAN1_BASE_PTR,52)
4000 #define CAN1_CS53                                CAN_CS_REG(CAN1_BASE_PTR,53)
4001 #define CAN1_ID53                                CAN_ID_REG(CAN1_BASE_PTR,53)
4002 #define CAN1_WORD053                             CAN_WORD0_REG(CAN1_BASE_PTR,53)
4003 #define CAN1_WORD153                             CAN_WORD1_REG(CAN1_BASE_PTR,53)
4004 #define CAN1_CS54                                CAN_CS_REG(CAN1_BASE_PTR,54)
4005 #define CAN1_ID54                                CAN_ID_REG(CAN1_BASE_PTR,54)
4006 #define CAN1_WORD054                             CAN_WORD0_REG(CAN1_BASE_PTR,54)
4007 #define CAN1_WORD154                             CAN_WORD1_REG(CAN1_BASE_PTR,54)
4008 #define CAN1_CS55                                CAN_CS_REG(CAN1_BASE_PTR,55)
4009 #define CAN1_ID55                                CAN_ID_REG(CAN1_BASE_PTR,55)
4010 #define CAN1_WORD055                             CAN_WORD0_REG(CAN1_BASE_PTR,55)
4011 #define CAN1_WORD155                             CAN_WORD1_REG(CAN1_BASE_PTR,55)
4012 #define CAN1_CS56                                CAN_CS_REG(CAN1_BASE_PTR,56)
4013 #define CAN1_ID56                                CAN_ID_REG(CAN1_BASE_PTR,56)
4014 #define CAN1_WORD056                             CAN_WORD0_REG(CAN1_BASE_PTR,56)
4015 #define CAN1_WORD156                             CAN_WORD1_REG(CAN1_BASE_PTR,56)
4016 #define CAN1_CS57                                CAN_CS_REG(CAN1_BASE_PTR,57)
4017 #define CAN1_ID57                                CAN_ID_REG(CAN1_BASE_PTR,57)
4018 #define CAN1_WORD057                             CAN_WORD0_REG(CAN1_BASE_PTR,57)
4019 #define CAN1_WORD157                             CAN_WORD1_REG(CAN1_BASE_PTR,57)
4020 #define CAN1_CS58                                CAN_CS_REG(CAN1_BASE_PTR,58)
4021 #define CAN1_ID58                                CAN_ID_REG(CAN1_BASE_PTR,58)
4022 #define CAN1_WORD058                             CAN_WORD0_REG(CAN1_BASE_PTR,58)
4023 #define CAN1_WORD158                             CAN_WORD1_REG(CAN1_BASE_PTR,58)
4024 #define CAN1_CS59                                CAN_CS_REG(CAN1_BASE_PTR,59)
4025 #define CAN1_ID59                                CAN_ID_REG(CAN1_BASE_PTR,59)
4026 #define CAN1_WORD059                             CAN_WORD0_REG(CAN1_BASE_PTR,59)
4027 #define CAN1_WORD159                             CAN_WORD1_REG(CAN1_BASE_PTR,59)
4028 #define CAN1_CS60                                CAN_CS_REG(CAN1_BASE_PTR,60)
4029 #define CAN1_ID60                                CAN_ID_REG(CAN1_BASE_PTR,60)
4030 #define CAN1_WORD060                             CAN_WORD0_REG(CAN1_BASE_PTR,60)
4031 #define CAN1_WORD160                             CAN_WORD1_REG(CAN1_BASE_PTR,60)
4032 #define CAN1_CS61                                CAN_CS_REG(CAN1_BASE_PTR,61)
4033 #define CAN1_ID61                                CAN_ID_REG(CAN1_BASE_PTR,61)
4034 #define CAN1_WORD061                             CAN_WORD0_REG(CAN1_BASE_PTR,61)
4035 #define CAN1_WORD161                             CAN_WORD1_REG(CAN1_BASE_PTR,61)
4036 #define CAN1_CS62                                CAN_CS_REG(CAN1_BASE_PTR,62)
4037 #define CAN1_ID62                                CAN_ID_REG(CAN1_BASE_PTR,62)
4038 #define CAN1_WORD062                             CAN_WORD0_REG(CAN1_BASE_PTR,62)
4039 #define CAN1_WORD162                             CAN_WORD1_REG(CAN1_BASE_PTR,62)
4040 #define CAN1_CS63                                CAN_CS_REG(CAN1_BASE_PTR,63)
4041 #define CAN1_ID63                                CAN_ID_REG(CAN1_BASE_PTR,63)
4042 #define CAN1_WORD063                             CAN_WORD0_REG(CAN1_BASE_PTR,63)
4043 #define CAN1_WORD163                             CAN_WORD1_REG(CAN1_BASE_PTR,63)
4044 #define CAN1_RXIMR0                              CAN_RXIMR_REG(CAN1_BASE_PTR,0)
4045 #define CAN1_RXIMR1                              CAN_RXIMR_REG(CAN1_BASE_PTR,1)
4046 #define CAN1_RXIMR2                              CAN_RXIMR_REG(CAN1_BASE_PTR,2)
4047 #define CAN1_RXIMR3                              CAN_RXIMR_REG(CAN1_BASE_PTR,3)
4048 #define CAN1_RXIMR4                              CAN_RXIMR_REG(CAN1_BASE_PTR,4)
4049 #define CAN1_RXIMR5                              CAN_RXIMR_REG(CAN1_BASE_PTR,5)
4050 #define CAN1_RXIMR6                              CAN_RXIMR_REG(CAN1_BASE_PTR,6)
4051 #define CAN1_RXIMR7                              CAN_RXIMR_REG(CAN1_BASE_PTR,7)
4052 #define CAN1_RXIMR8                              CAN_RXIMR_REG(CAN1_BASE_PTR,8)
4053 #define CAN1_RXIMR9                              CAN_RXIMR_REG(CAN1_BASE_PTR,9)
4054 #define CAN1_RXIMR10                             CAN_RXIMR_REG(CAN1_BASE_PTR,10)
4055 #define CAN1_RXIMR11                             CAN_RXIMR_REG(CAN1_BASE_PTR,11)
4056 #define CAN1_RXIMR12                             CAN_RXIMR_REG(CAN1_BASE_PTR,12)
4057 #define CAN1_RXIMR13                             CAN_RXIMR_REG(CAN1_BASE_PTR,13)
4058 #define CAN1_RXIMR14                             CAN_RXIMR_REG(CAN1_BASE_PTR,14)
4059 #define CAN1_RXIMR15                             CAN_RXIMR_REG(CAN1_BASE_PTR,15)
4060 #define CAN1_RXIMR16                             CAN_RXIMR_REG(CAN1_BASE_PTR,16)
4061 #define CAN1_RXIMR17                             CAN_RXIMR_REG(CAN1_BASE_PTR,17)
4062 #define CAN1_RXIMR18                             CAN_RXIMR_REG(CAN1_BASE_PTR,18)
4063 #define CAN1_RXIMR19                             CAN_RXIMR_REG(CAN1_BASE_PTR,19)
4064 #define CAN1_RXIMR20                             CAN_RXIMR_REG(CAN1_BASE_PTR,20)
4065 #define CAN1_RXIMR21                             CAN_RXIMR_REG(CAN1_BASE_PTR,21)
4066 #define CAN1_RXIMR22                             CAN_RXIMR_REG(CAN1_BASE_PTR,22)
4067 #define CAN1_RXIMR23                             CAN_RXIMR_REG(CAN1_BASE_PTR,23)
4068 #define CAN1_RXIMR24                             CAN_RXIMR_REG(CAN1_BASE_PTR,24)
4069 #define CAN1_RXIMR25                             CAN_RXIMR_REG(CAN1_BASE_PTR,25)
4070 #define CAN1_RXIMR26                             CAN_RXIMR_REG(CAN1_BASE_PTR,26)
4071 #define CAN1_RXIMR27                             CAN_RXIMR_REG(CAN1_BASE_PTR,27)
4072 #define CAN1_RXIMR28                             CAN_RXIMR_REG(CAN1_BASE_PTR,28)
4073 #define CAN1_RXIMR29                             CAN_RXIMR_REG(CAN1_BASE_PTR,29)
4074 #define CAN1_RXIMR30                             CAN_RXIMR_REG(CAN1_BASE_PTR,30)
4075 #define CAN1_RXIMR31                             CAN_RXIMR_REG(CAN1_BASE_PTR,31)
4076 #define CAN1_RXIMR32                             CAN_RXIMR_REG(CAN1_BASE_PTR,32)
4077 #define CAN1_RXIMR33                             CAN_RXIMR_REG(CAN1_BASE_PTR,33)
4078 #define CAN1_RXIMR34                             CAN_RXIMR_REG(CAN1_BASE_PTR,34)
4079 #define CAN1_RXIMR35                             CAN_RXIMR_REG(CAN1_BASE_PTR,35)
4080 #define CAN1_RXIMR36                             CAN_RXIMR_REG(CAN1_BASE_PTR,36)
4081 #define CAN1_RXIMR37                             CAN_RXIMR_REG(CAN1_BASE_PTR,37)
4082 #define CAN1_RXIMR38                             CAN_RXIMR_REG(CAN1_BASE_PTR,38)
4083 #define CAN1_RXIMR39                             CAN_RXIMR_REG(CAN1_BASE_PTR,39)
4084 #define CAN1_RXIMR40                             CAN_RXIMR_REG(CAN1_BASE_PTR,40)
4085 #define CAN1_RXIMR41                             CAN_RXIMR_REG(CAN1_BASE_PTR,41)
4086 #define CAN1_RXIMR42                             CAN_RXIMR_REG(CAN1_BASE_PTR,42)
4087 #define CAN1_RXIMR43                             CAN_RXIMR_REG(CAN1_BASE_PTR,43)
4088 #define CAN1_RXIMR44                             CAN_RXIMR_REG(CAN1_BASE_PTR,44)
4089 #define CAN1_RXIMR45                             CAN_RXIMR_REG(CAN1_BASE_PTR,45)
4090 #define CAN1_RXIMR46                             CAN_RXIMR_REG(CAN1_BASE_PTR,46)
4091 #define CAN1_RXIMR47                             CAN_RXIMR_REG(CAN1_BASE_PTR,47)
4092 #define CAN1_RXIMR48                             CAN_RXIMR_REG(CAN1_BASE_PTR,48)
4093 #define CAN1_RXIMR49                             CAN_RXIMR_REG(CAN1_BASE_PTR,49)
4094 #define CAN1_RXIMR50                             CAN_RXIMR_REG(CAN1_BASE_PTR,50)
4095 #define CAN1_RXIMR51                             CAN_RXIMR_REG(CAN1_BASE_PTR,51)
4096 #define CAN1_RXIMR52                             CAN_RXIMR_REG(CAN1_BASE_PTR,52)
4097 #define CAN1_RXIMR53                             CAN_RXIMR_REG(CAN1_BASE_PTR,53)
4098 #define CAN1_RXIMR54                             CAN_RXIMR_REG(CAN1_BASE_PTR,54)
4099 #define CAN1_RXIMR55                             CAN_RXIMR_REG(CAN1_BASE_PTR,55)
4100 #define CAN1_RXIMR56                             CAN_RXIMR_REG(CAN1_BASE_PTR,56)
4101 #define CAN1_RXIMR57                             CAN_RXIMR_REG(CAN1_BASE_PTR,57)
4102 #define CAN1_RXIMR58                             CAN_RXIMR_REG(CAN1_BASE_PTR,58)
4103 #define CAN1_RXIMR59                             CAN_RXIMR_REG(CAN1_BASE_PTR,59)
4104 #define CAN1_RXIMR60                             CAN_RXIMR_REG(CAN1_BASE_PTR,60)
4105 #define CAN1_RXIMR61                             CAN_RXIMR_REG(CAN1_BASE_PTR,61)
4106 #define CAN1_RXIMR62                             CAN_RXIMR_REG(CAN1_BASE_PTR,62)
4107 #define CAN1_RXIMR63                             CAN_RXIMR_REG(CAN1_BASE_PTR,63)
4108 #define CAN1_GFWR                                CAN_GFWR_REG(CAN1_BASE_PTR)
4109 /* CAN2 */
4110 #define CAN2_MCR                                 CAN_MCR_REG(CAN2_BASE_PTR)
4111 #define CAN2_CTRL1                               CAN_CTRL1_REG(CAN2_BASE_PTR)
4112 #define CAN2_TIMER                               CAN_TIMER_REG(CAN2_BASE_PTR)
4113 #define CAN2_RXMGMASK                            CAN_RXMGMASK_REG(CAN2_BASE_PTR)
4114 #define CAN2_RX14MASK                            CAN_RX14MASK_REG(CAN2_BASE_PTR)
4115 #define CAN2_RX15MASK                            CAN_RX15MASK_REG(CAN2_BASE_PTR)
4116 #define CAN2_ECR                                 CAN_ECR_REG(CAN2_BASE_PTR)
4117 #define CAN2_ESR1                                CAN_ESR1_REG(CAN2_BASE_PTR)
4118 #define CAN2_IMASK2                              CAN_IMASK2_REG(CAN2_BASE_PTR)
4119 #define CAN2_IMASK1                              CAN_IMASK1_REG(CAN2_BASE_PTR)
4120 #define CAN2_IFLAG2                              CAN_IFLAG2_REG(CAN2_BASE_PTR)
4121 #define CAN2_IFLAG1                              CAN_IFLAG1_REG(CAN2_BASE_PTR)
4122 #define CAN2_CTRL2                               CAN_CTRL2_REG(CAN2_BASE_PTR)
4123 #define CAN2_ESR2                                CAN_ESR2_REG(CAN2_BASE_PTR)
4124 #define CAN2_CRCR                                CAN_CRCR_REG(CAN2_BASE_PTR)
4125 #define CAN2_RXFGMASK                            CAN_RXFGMASK_REG(CAN2_BASE_PTR)
4126 #define CAN2_RXFIR                               CAN_RXFIR_REG(CAN2_BASE_PTR)
4127 #define CAN2_CS0                                 CAN_CS_REG(CAN2_BASE_PTR,0)
4128 #define CAN2_ID0                                 CAN_ID_REG(CAN2_BASE_PTR,0)
4129 #define CAN2_WORD00                              CAN_WORD0_REG(CAN2_BASE_PTR,0)
4130 #define CAN2_WORD10                              CAN_WORD1_REG(CAN2_BASE_PTR,0)
4131 #define CAN2_CS1                                 CAN_CS_REG(CAN2_BASE_PTR,1)
4132 #define CAN2_ID1                                 CAN_ID_REG(CAN2_BASE_PTR,1)
4133 #define CAN2_WORD01                              CAN_WORD0_REG(CAN2_BASE_PTR,1)
4134 #define CAN2_WORD11                              CAN_WORD1_REG(CAN2_BASE_PTR,1)
4135 #define CAN2_CS2                                 CAN_CS_REG(CAN2_BASE_PTR,2)
4136 #define CAN2_ID2                                 CAN_ID_REG(CAN2_BASE_PTR,2)
4137 #define CAN2_WORD02                              CAN_WORD0_REG(CAN2_BASE_PTR,2)
4138 #define CAN2_WORD12                              CAN_WORD1_REG(CAN2_BASE_PTR,2)
4139 #define CAN2_CS3                                 CAN_CS_REG(CAN2_BASE_PTR,3)
4140 #define CAN2_ID3                                 CAN_ID_REG(CAN2_BASE_PTR,3)
4141 #define CAN2_WORD03                              CAN_WORD0_REG(CAN2_BASE_PTR,3)
4142 #define CAN2_WORD13                              CAN_WORD1_REG(CAN2_BASE_PTR,3)
4143 #define CAN2_CS4                                 CAN_CS_REG(CAN2_BASE_PTR,4)
4144 #define CAN2_ID4                                 CAN_ID_REG(CAN2_BASE_PTR,4)
4145 #define CAN2_WORD04                              CAN_WORD0_REG(CAN2_BASE_PTR,4)
4146 #define CAN2_WORD14                              CAN_WORD1_REG(CAN2_BASE_PTR,4)
4147 #define CAN2_CS5                                 CAN_CS_REG(CAN2_BASE_PTR,5)
4148 #define CAN2_ID5                                 CAN_ID_REG(CAN2_BASE_PTR,5)
4149 #define CAN2_WORD05                              CAN_WORD0_REG(CAN2_BASE_PTR,5)
4150 #define CAN2_WORD15                              CAN_WORD1_REG(CAN2_BASE_PTR,5)
4151 #define CAN2_CS6                                 CAN_CS_REG(CAN2_BASE_PTR,6)
4152 #define CAN2_ID6                                 CAN_ID_REG(CAN2_BASE_PTR,6)
4153 #define CAN2_WORD06                              CAN_WORD0_REG(CAN2_BASE_PTR,6)
4154 #define CAN2_WORD16                              CAN_WORD1_REG(CAN2_BASE_PTR,6)
4155 #define CAN2_CS7                                 CAN_CS_REG(CAN2_BASE_PTR,7)
4156 #define CAN2_ID7                                 CAN_ID_REG(CAN2_BASE_PTR,7)
4157 #define CAN2_WORD07                              CAN_WORD0_REG(CAN2_BASE_PTR,7)
4158 #define CAN2_WORD17                              CAN_WORD1_REG(CAN2_BASE_PTR,7)
4159 #define CAN2_CS8                                 CAN_CS_REG(CAN2_BASE_PTR,8)
4160 #define CAN2_ID8                                 CAN_ID_REG(CAN2_BASE_PTR,8)
4161 #define CAN2_WORD08                              CAN_WORD0_REG(CAN2_BASE_PTR,8)
4162 #define CAN2_WORD18                              CAN_WORD1_REG(CAN2_BASE_PTR,8)
4163 #define CAN2_CS9                                 CAN_CS_REG(CAN2_BASE_PTR,9)
4164 #define CAN2_ID9                                 CAN_ID_REG(CAN2_BASE_PTR,9)
4165 #define CAN2_WORD09                              CAN_WORD0_REG(CAN2_BASE_PTR,9)
4166 #define CAN2_WORD19                              CAN_WORD1_REG(CAN2_BASE_PTR,9)
4167 #define CAN2_CS10                                CAN_CS_REG(CAN2_BASE_PTR,10)
4168 #define CAN2_ID10                                CAN_ID_REG(CAN2_BASE_PTR,10)
4169 #define CAN2_WORD010                             CAN_WORD0_REG(CAN2_BASE_PTR,10)
4170 #define CAN2_WORD110                             CAN_WORD1_REG(CAN2_BASE_PTR,10)
4171 #define CAN2_CS11                                CAN_CS_REG(CAN2_BASE_PTR,11)
4172 #define CAN2_ID11                                CAN_ID_REG(CAN2_BASE_PTR,11)
4173 #define CAN2_WORD011                             CAN_WORD0_REG(CAN2_BASE_PTR,11)
4174 #define CAN2_WORD111                             CAN_WORD1_REG(CAN2_BASE_PTR,11)
4175 #define CAN2_CS12                                CAN_CS_REG(CAN2_BASE_PTR,12)
4176 #define CAN2_ID12                                CAN_ID_REG(CAN2_BASE_PTR,12)
4177 #define CAN2_WORD012                             CAN_WORD0_REG(CAN2_BASE_PTR,12)
4178 #define CAN2_WORD112                             CAN_WORD1_REG(CAN2_BASE_PTR,12)
4179 #define CAN2_CS13                                CAN_CS_REG(CAN2_BASE_PTR,13)
4180 #define CAN2_ID13                                CAN_ID_REG(CAN2_BASE_PTR,13)
4181 #define CAN2_WORD013                             CAN_WORD0_REG(CAN2_BASE_PTR,13)
4182 #define CAN2_WORD113                             CAN_WORD1_REG(CAN2_BASE_PTR,13)
4183 #define CAN2_CS14                                CAN_CS_REG(CAN2_BASE_PTR,14)
4184 #define CAN2_ID14                                CAN_ID_REG(CAN2_BASE_PTR,14)
4185 #define CAN2_WORD014                             CAN_WORD0_REG(CAN2_BASE_PTR,14)
4186 #define CAN2_WORD114                             CAN_WORD1_REG(CAN2_BASE_PTR,14)
4187 #define CAN2_CS15                                CAN_CS_REG(CAN2_BASE_PTR,15)
4188 #define CAN2_ID15                                CAN_ID_REG(CAN2_BASE_PTR,15)
4189 #define CAN2_WORD015                             CAN_WORD0_REG(CAN2_BASE_PTR,15)
4190 #define CAN2_WORD115                             CAN_WORD1_REG(CAN2_BASE_PTR,15)
4191 #define CAN2_CS16                                CAN_CS_REG(CAN2_BASE_PTR,16)
4192 #define CAN2_ID16                                CAN_ID_REG(CAN2_BASE_PTR,16)
4193 #define CAN2_WORD016                             CAN_WORD0_REG(CAN2_BASE_PTR,16)
4194 #define CAN2_WORD116                             CAN_WORD1_REG(CAN2_BASE_PTR,16)
4195 #define CAN2_CS17                                CAN_CS_REG(CAN2_BASE_PTR,17)
4196 #define CAN2_ID17                                CAN_ID_REG(CAN2_BASE_PTR,17)
4197 #define CAN2_WORD017                             CAN_WORD0_REG(CAN2_BASE_PTR,17)
4198 #define CAN2_WORD117                             CAN_WORD1_REG(CAN2_BASE_PTR,17)
4199 #define CAN2_CS18                                CAN_CS_REG(CAN2_BASE_PTR,18)
4200 #define CAN2_ID18                                CAN_ID_REG(CAN2_BASE_PTR,18)
4201 #define CAN2_WORD018                             CAN_WORD0_REG(CAN2_BASE_PTR,18)
4202 #define CAN2_WORD118                             CAN_WORD1_REG(CAN2_BASE_PTR,18)
4203 #define CAN2_CS19                                CAN_CS_REG(CAN2_BASE_PTR,19)
4204 #define CAN2_ID19                                CAN_ID_REG(CAN2_BASE_PTR,19)
4205 #define CAN2_WORD019                             CAN_WORD0_REG(CAN2_BASE_PTR,19)
4206 #define CAN2_WORD119                             CAN_WORD1_REG(CAN2_BASE_PTR,19)
4207 #define CAN2_CS20                                CAN_CS_REG(CAN2_BASE_PTR,20)
4208 #define CAN2_ID20                                CAN_ID_REG(CAN2_BASE_PTR,20)
4209 #define CAN2_WORD020                             CAN_WORD0_REG(CAN2_BASE_PTR,20)
4210 #define CAN2_WORD120                             CAN_WORD1_REG(CAN2_BASE_PTR,20)
4211 #define CAN2_CS21                                CAN_CS_REG(CAN2_BASE_PTR,21)
4212 #define CAN2_ID21                                CAN_ID_REG(CAN2_BASE_PTR,21)
4213 #define CAN2_WORD021                             CAN_WORD0_REG(CAN2_BASE_PTR,21)
4214 #define CAN2_WORD121                             CAN_WORD1_REG(CAN2_BASE_PTR,21)
4215 #define CAN2_CS22                                CAN_CS_REG(CAN2_BASE_PTR,22)
4216 #define CAN2_ID22                                CAN_ID_REG(CAN2_BASE_PTR,22)
4217 #define CAN2_WORD022                             CAN_WORD0_REG(CAN2_BASE_PTR,22)
4218 #define CAN2_WORD122                             CAN_WORD1_REG(CAN2_BASE_PTR,22)
4219 #define CAN2_CS23                                CAN_CS_REG(CAN2_BASE_PTR,23)
4220 #define CAN2_ID23                                CAN_ID_REG(CAN2_BASE_PTR,23)
4221 #define CAN2_WORD023                             CAN_WORD0_REG(CAN2_BASE_PTR,23)
4222 #define CAN2_WORD123                             CAN_WORD1_REG(CAN2_BASE_PTR,23)
4223 #define CAN2_CS24                                CAN_CS_REG(CAN2_BASE_PTR,24)
4224 #define CAN2_ID24                                CAN_ID_REG(CAN2_BASE_PTR,24)
4225 #define CAN2_WORD024                             CAN_WORD0_REG(CAN2_BASE_PTR,24)
4226 #define CAN2_WORD124                             CAN_WORD1_REG(CAN2_BASE_PTR,24)
4227 #define CAN2_CS25                                CAN_CS_REG(CAN2_BASE_PTR,25)
4228 #define CAN2_ID25                                CAN_ID_REG(CAN2_BASE_PTR,25)
4229 #define CAN2_WORD025                             CAN_WORD0_REG(CAN2_BASE_PTR,25)
4230 #define CAN2_WORD125                             CAN_WORD1_REG(CAN2_BASE_PTR,25)
4231 #define CAN2_CS26                                CAN_CS_REG(CAN2_BASE_PTR,26)
4232 #define CAN2_ID26                                CAN_ID_REG(CAN2_BASE_PTR,26)
4233 #define CAN2_WORD026                             CAN_WORD0_REG(CAN2_BASE_PTR,26)
4234 #define CAN2_WORD126                             CAN_WORD1_REG(CAN2_BASE_PTR,26)
4235 #define CAN2_CS27                                CAN_CS_REG(CAN2_BASE_PTR,27)
4236 #define CAN2_ID27                                CAN_ID_REG(CAN2_BASE_PTR,27)
4237 #define CAN2_WORD027                             CAN_WORD0_REG(CAN2_BASE_PTR,27)
4238 #define CAN2_WORD127                             CAN_WORD1_REG(CAN2_BASE_PTR,27)
4239 #define CAN2_CS28                                CAN_CS_REG(CAN2_BASE_PTR,28)
4240 #define CAN2_ID28                                CAN_ID_REG(CAN2_BASE_PTR,28)
4241 #define CAN2_WORD028                             CAN_WORD0_REG(CAN2_BASE_PTR,28)
4242 #define CAN2_WORD128                             CAN_WORD1_REG(CAN2_BASE_PTR,28)
4243 #define CAN2_CS29                                CAN_CS_REG(CAN2_BASE_PTR,29)
4244 #define CAN2_ID29                                CAN_ID_REG(CAN2_BASE_PTR,29)
4245 #define CAN2_WORD029                             CAN_WORD0_REG(CAN2_BASE_PTR,29)
4246 #define CAN2_WORD129                             CAN_WORD1_REG(CAN2_BASE_PTR,29)
4247 #define CAN2_CS30                                CAN_CS_REG(CAN2_BASE_PTR,30)
4248 #define CAN2_ID30                                CAN_ID_REG(CAN2_BASE_PTR,30)
4249 #define CAN2_WORD030                             CAN_WORD0_REG(CAN2_BASE_PTR,30)
4250 #define CAN2_WORD130                             CAN_WORD1_REG(CAN2_BASE_PTR,30)
4251 #define CAN2_CS31                                CAN_CS_REG(CAN2_BASE_PTR,31)
4252 #define CAN2_ID31                                CAN_ID_REG(CAN2_BASE_PTR,31)
4253 #define CAN2_WORD031                             CAN_WORD0_REG(CAN2_BASE_PTR,31)
4254 #define CAN2_WORD131                             CAN_WORD1_REG(CAN2_BASE_PTR,31)
4255 #define CAN2_CS32                                CAN_CS_REG(CAN2_BASE_PTR,32)
4256 #define CAN2_ID32                                CAN_ID_REG(CAN2_BASE_PTR,32)
4257 #define CAN2_WORD032                             CAN_WORD0_REG(CAN2_BASE_PTR,32)
4258 #define CAN2_WORD132                             CAN_WORD1_REG(CAN2_BASE_PTR,32)
4259 #define CAN2_CS33                                CAN_CS_REG(CAN2_BASE_PTR,33)
4260 #define CAN2_ID33                                CAN_ID_REG(CAN2_BASE_PTR,33)
4261 #define CAN2_WORD033                             CAN_WORD0_REG(CAN2_BASE_PTR,33)
4262 #define CAN2_WORD133                             CAN_WORD1_REG(CAN2_BASE_PTR,33)
4263 #define CAN2_CS34                                CAN_CS_REG(CAN2_BASE_PTR,34)
4264 #define CAN2_ID34                                CAN_ID_REG(CAN2_BASE_PTR,34)
4265 #define CAN2_WORD034                             CAN_WORD0_REG(CAN2_BASE_PTR,34)
4266 #define CAN2_WORD134                             CAN_WORD1_REG(CAN2_BASE_PTR,34)
4267 #define CAN2_CS35                                CAN_CS_REG(CAN2_BASE_PTR,35)
4268 #define CAN2_ID35                                CAN_ID_REG(CAN2_BASE_PTR,35)
4269 #define CAN2_WORD035                             CAN_WORD0_REG(CAN2_BASE_PTR,35)
4270 #define CAN2_WORD135                             CAN_WORD1_REG(CAN2_BASE_PTR,35)
4271 #define CAN2_CS36                                CAN_CS_REG(CAN2_BASE_PTR,36)
4272 #define CAN2_ID36                                CAN_ID_REG(CAN2_BASE_PTR,36)
4273 #define CAN2_WORD036                             CAN_WORD0_REG(CAN2_BASE_PTR,36)
4274 #define CAN2_WORD136                             CAN_WORD1_REG(CAN2_BASE_PTR,36)
4275 #define CAN2_CS37                                CAN_CS_REG(CAN2_BASE_PTR,37)
4276 #define CAN2_ID37                                CAN_ID_REG(CAN2_BASE_PTR,37)
4277 #define CAN2_WORD037                             CAN_WORD0_REG(CAN2_BASE_PTR,37)
4278 #define CAN2_WORD137                             CAN_WORD1_REG(CAN2_BASE_PTR,37)
4279 #define CAN2_CS38                                CAN_CS_REG(CAN2_BASE_PTR,38)
4280 #define CAN2_ID38                                CAN_ID_REG(CAN2_BASE_PTR,38)
4281 #define CAN2_WORD038                             CAN_WORD0_REG(CAN2_BASE_PTR,38)
4282 #define CAN2_WORD138                             CAN_WORD1_REG(CAN2_BASE_PTR,38)
4283 #define CAN2_CS39                                CAN_CS_REG(CAN2_BASE_PTR,39)
4284 #define CAN2_ID39                                CAN_ID_REG(CAN2_BASE_PTR,39)
4285 #define CAN2_WORD039                             CAN_WORD0_REG(CAN2_BASE_PTR,39)
4286 #define CAN2_WORD139                             CAN_WORD1_REG(CAN2_BASE_PTR,39)
4287 #define CAN2_CS40                                CAN_CS_REG(CAN2_BASE_PTR,40)
4288 #define CAN2_ID40                                CAN_ID_REG(CAN2_BASE_PTR,40)
4289 #define CAN2_WORD040                             CAN_WORD0_REG(CAN2_BASE_PTR,40)
4290 #define CAN2_WORD140                             CAN_WORD1_REG(CAN2_BASE_PTR,40)
4291 #define CAN2_CS41                                CAN_CS_REG(CAN2_BASE_PTR,41)
4292 #define CAN2_ID41                                CAN_ID_REG(CAN2_BASE_PTR,41)
4293 #define CAN2_WORD041                             CAN_WORD0_REG(CAN2_BASE_PTR,41)
4294 #define CAN2_WORD141                             CAN_WORD1_REG(CAN2_BASE_PTR,41)
4295 #define CAN2_CS42                                CAN_CS_REG(CAN2_BASE_PTR,42)
4296 #define CAN2_ID42                                CAN_ID_REG(CAN2_BASE_PTR,42)
4297 #define CAN2_WORD042                             CAN_WORD0_REG(CAN2_BASE_PTR,42)
4298 #define CAN2_WORD142                             CAN_WORD1_REG(CAN2_BASE_PTR,42)
4299 #define CAN2_CS43                                CAN_CS_REG(CAN2_BASE_PTR,43)
4300 #define CAN2_ID43                                CAN_ID_REG(CAN2_BASE_PTR,43)
4301 #define CAN2_WORD043                             CAN_WORD0_REG(CAN2_BASE_PTR,43)
4302 #define CAN2_WORD143                             CAN_WORD1_REG(CAN2_BASE_PTR,43)
4303 #define CAN2_CS44                                CAN_CS_REG(CAN2_BASE_PTR,44)
4304 #define CAN2_ID44                                CAN_ID_REG(CAN2_BASE_PTR,44)
4305 #define CAN2_WORD044                             CAN_WORD0_REG(CAN2_BASE_PTR,44)
4306 #define CAN2_WORD144                             CAN_WORD1_REG(CAN2_BASE_PTR,44)
4307 #define CAN2_CS45                                CAN_CS_REG(CAN2_BASE_PTR,45)
4308 #define CAN2_ID45                                CAN_ID_REG(CAN2_BASE_PTR,45)
4309 #define CAN2_WORD045                             CAN_WORD0_REG(CAN2_BASE_PTR,45)
4310 #define CAN2_WORD145                             CAN_WORD1_REG(CAN2_BASE_PTR,45)
4311 #define CAN2_CS46                                CAN_CS_REG(CAN2_BASE_PTR,46)
4312 #define CAN2_ID46                                CAN_ID_REG(CAN2_BASE_PTR,46)
4313 #define CAN2_WORD046                             CAN_WORD0_REG(CAN2_BASE_PTR,46)
4314 #define CAN2_WORD146                             CAN_WORD1_REG(CAN2_BASE_PTR,46)
4315 #define CAN2_CS47                                CAN_CS_REG(CAN2_BASE_PTR,47)
4316 #define CAN2_ID47                                CAN_ID_REG(CAN2_BASE_PTR,47)
4317 #define CAN2_WORD047                             CAN_WORD0_REG(CAN2_BASE_PTR,47)
4318 #define CAN2_WORD147                             CAN_WORD1_REG(CAN2_BASE_PTR,47)
4319 #define CAN2_CS48                                CAN_CS_REG(CAN2_BASE_PTR,48)
4320 #define CAN2_ID48                                CAN_ID_REG(CAN2_BASE_PTR,48)
4321 #define CAN2_WORD048                             CAN_WORD0_REG(CAN2_BASE_PTR,48)
4322 #define CAN2_WORD148                             CAN_WORD1_REG(CAN2_BASE_PTR,48)
4323 #define CAN2_CS49                                CAN_CS_REG(CAN2_BASE_PTR,49)
4324 #define CAN2_ID49                                CAN_ID_REG(CAN2_BASE_PTR,49)
4325 #define CAN2_WORD049                             CAN_WORD0_REG(CAN2_BASE_PTR,49)
4326 #define CAN2_WORD149                             CAN_WORD1_REG(CAN2_BASE_PTR,49)
4327 #define CAN2_CS50                                CAN_CS_REG(CAN2_BASE_PTR,50)
4328 #define CAN2_ID50                                CAN_ID_REG(CAN2_BASE_PTR,50)
4329 #define CAN2_WORD050                             CAN_WORD0_REG(CAN2_BASE_PTR,50)
4330 #define CAN2_WORD150                             CAN_WORD1_REG(CAN2_BASE_PTR,50)
4331 #define CAN2_CS51                                CAN_CS_REG(CAN2_BASE_PTR,51)
4332 #define CAN2_ID51                                CAN_ID_REG(CAN2_BASE_PTR,51)
4333 #define CAN2_WORD051                             CAN_WORD0_REG(CAN2_BASE_PTR,51)
4334 #define CAN2_WORD151                             CAN_WORD1_REG(CAN2_BASE_PTR,51)
4335 #define CAN2_CS52                                CAN_CS_REG(CAN2_BASE_PTR,52)
4336 #define CAN2_ID52                                CAN_ID_REG(CAN2_BASE_PTR,52)
4337 #define CAN2_WORD052                             CAN_WORD0_REG(CAN2_BASE_PTR,52)
4338 #define CAN2_WORD152                             CAN_WORD1_REG(CAN2_BASE_PTR,52)
4339 #define CAN2_CS53                                CAN_CS_REG(CAN2_BASE_PTR,53)
4340 #define CAN2_ID53                                CAN_ID_REG(CAN2_BASE_PTR,53)
4341 #define CAN2_WORD053                             CAN_WORD0_REG(CAN2_BASE_PTR,53)
4342 #define CAN2_WORD153                             CAN_WORD1_REG(CAN2_BASE_PTR,53)
4343 #define CAN2_CS54                                CAN_CS_REG(CAN2_BASE_PTR,54)
4344 #define CAN2_ID54                                CAN_ID_REG(CAN2_BASE_PTR,54)
4345 #define CAN2_WORD054                             CAN_WORD0_REG(CAN2_BASE_PTR,54)
4346 #define CAN2_WORD154                             CAN_WORD1_REG(CAN2_BASE_PTR,54)
4347 #define CAN2_CS55                                CAN_CS_REG(CAN2_BASE_PTR,55)
4348 #define CAN2_ID55                                CAN_ID_REG(CAN2_BASE_PTR,55)
4349 #define CAN2_WORD055                             CAN_WORD0_REG(CAN2_BASE_PTR,55)
4350 #define CAN2_WORD155                             CAN_WORD1_REG(CAN2_BASE_PTR,55)
4351 #define CAN2_CS56                                CAN_CS_REG(CAN2_BASE_PTR,56)
4352 #define CAN2_ID56                                CAN_ID_REG(CAN2_BASE_PTR,56)
4353 #define CAN2_WORD056                             CAN_WORD0_REG(CAN2_BASE_PTR,56)
4354 #define CAN2_WORD156                             CAN_WORD1_REG(CAN2_BASE_PTR,56)
4355 #define CAN2_CS57                                CAN_CS_REG(CAN2_BASE_PTR,57)
4356 #define CAN2_ID57                                CAN_ID_REG(CAN2_BASE_PTR,57)
4357 #define CAN2_WORD057                             CAN_WORD0_REG(CAN2_BASE_PTR,57)
4358 #define CAN2_WORD157                             CAN_WORD1_REG(CAN2_BASE_PTR,57)
4359 #define CAN2_CS58                                CAN_CS_REG(CAN2_BASE_PTR,58)
4360 #define CAN2_ID58                                CAN_ID_REG(CAN2_BASE_PTR,58)
4361 #define CAN2_WORD058                             CAN_WORD0_REG(CAN2_BASE_PTR,58)
4362 #define CAN2_WORD158                             CAN_WORD1_REG(CAN2_BASE_PTR,58)
4363 #define CAN2_CS59                                CAN_CS_REG(CAN2_BASE_PTR,59)
4364 #define CAN2_ID59                                CAN_ID_REG(CAN2_BASE_PTR,59)
4365 #define CAN2_WORD059                             CAN_WORD0_REG(CAN2_BASE_PTR,59)
4366 #define CAN2_WORD159                             CAN_WORD1_REG(CAN2_BASE_PTR,59)
4367 #define CAN2_CS60                                CAN_CS_REG(CAN2_BASE_PTR,60)
4368 #define CAN2_ID60                                CAN_ID_REG(CAN2_BASE_PTR,60)
4369 #define CAN2_WORD060                             CAN_WORD0_REG(CAN2_BASE_PTR,60)
4370 #define CAN2_WORD160                             CAN_WORD1_REG(CAN2_BASE_PTR,60)
4371 #define CAN2_CS61                                CAN_CS_REG(CAN2_BASE_PTR,61)
4372 #define CAN2_ID61                                CAN_ID_REG(CAN2_BASE_PTR,61)
4373 #define CAN2_WORD061                             CAN_WORD0_REG(CAN2_BASE_PTR,61)
4374 #define CAN2_WORD161                             CAN_WORD1_REG(CAN2_BASE_PTR,61)
4375 #define CAN2_CS62                                CAN_CS_REG(CAN2_BASE_PTR,62)
4376 #define CAN2_ID62                                CAN_ID_REG(CAN2_BASE_PTR,62)
4377 #define CAN2_WORD062                             CAN_WORD0_REG(CAN2_BASE_PTR,62)
4378 #define CAN2_WORD162                             CAN_WORD1_REG(CAN2_BASE_PTR,62)
4379 #define CAN2_CS63                                CAN_CS_REG(CAN2_BASE_PTR,63)
4380 #define CAN2_ID63                                CAN_ID_REG(CAN2_BASE_PTR,63)
4381 #define CAN2_WORD063                             CAN_WORD0_REG(CAN2_BASE_PTR,63)
4382 #define CAN2_WORD163                             CAN_WORD1_REG(CAN2_BASE_PTR,63)
4383 #define CAN2_RXIMR0                              CAN_RXIMR_REG(CAN2_BASE_PTR,0)
4384 #define CAN2_RXIMR1                              CAN_RXIMR_REG(CAN2_BASE_PTR,1)
4385 #define CAN2_RXIMR2                              CAN_RXIMR_REG(CAN2_BASE_PTR,2)
4386 #define CAN2_RXIMR3                              CAN_RXIMR_REG(CAN2_BASE_PTR,3)
4387 #define CAN2_RXIMR4                              CAN_RXIMR_REG(CAN2_BASE_PTR,4)
4388 #define CAN2_RXIMR5                              CAN_RXIMR_REG(CAN2_BASE_PTR,5)
4389 #define CAN2_RXIMR6                              CAN_RXIMR_REG(CAN2_BASE_PTR,6)
4390 #define CAN2_RXIMR7                              CAN_RXIMR_REG(CAN2_BASE_PTR,7)
4391 #define CAN2_RXIMR8                              CAN_RXIMR_REG(CAN2_BASE_PTR,8)
4392 #define CAN2_RXIMR9                              CAN_RXIMR_REG(CAN2_BASE_PTR,9)
4393 #define CAN2_RXIMR10                             CAN_RXIMR_REG(CAN2_BASE_PTR,10)
4394 #define CAN2_RXIMR11                             CAN_RXIMR_REG(CAN2_BASE_PTR,11)
4395 #define CAN2_RXIMR12                             CAN_RXIMR_REG(CAN2_BASE_PTR,12)
4396 #define CAN2_RXIMR13                             CAN_RXIMR_REG(CAN2_BASE_PTR,13)
4397 #define CAN2_RXIMR14                             CAN_RXIMR_REG(CAN2_BASE_PTR,14)
4398 #define CAN2_RXIMR15                             CAN_RXIMR_REG(CAN2_BASE_PTR,15)
4399 #define CAN2_RXIMR16                             CAN_RXIMR_REG(CAN2_BASE_PTR,16)
4400 #define CAN2_RXIMR17                             CAN_RXIMR_REG(CAN2_BASE_PTR,17)
4401 #define CAN2_RXIMR18                             CAN_RXIMR_REG(CAN2_BASE_PTR,18)
4402 #define CAN2_RXIMR19                             CAN_RXIMR_REG(CAN2_BASE_PTR,19)
4403 #define CAN2_RXIMR20                             CAN_RXIMR_REG(CAN2_BASE_PTR,20)
4404 #define CAN2_RXIMR21                             CAN_RXIMR_REG(CAN2_BASE_PTR,21)
4405 #define CAN2_RXIMR22                             CAN_RXIMR_REG(CAN2_BASE_PTR,22)
4406 #define CAN2_RXIMR23                             CAN_RXIMR_REG(CAN2_BASE_PTR,23)
4407 #define CAN2_RXIMR24                             CAN_RXIMR_REG(CAN2_BASE_PTR,24)
4408 #define CAN2_RXIMR25                             CAN_RXIMR_REG(CAN2_BASE_PTR,25)
4409 #define CAN2_RXIMR26                             CAN_RXIMR_REG(CAN2_BASE_PTR,26)
4410 #define CAN2_RXIMR27                             CAN_RXIMR_REG(CAN2_BASE_PTR,27)
4411 #define CAN2_RXIMR28                             CAN_RXIMR_REG(CAN2_BASE_PTR,28)
4412 #define CAN2_RXIMR29                             CAN_RXIMR_REG(CAN2_BASE_PTR,29)
4413 #define CAN2_RXIMR30                             CAN_RXIMR_REG(CAN2_BASE_PTR,30)
4414 #define CAN2_RXIMR31                             CAN_RXIMR_REG(CAN2_BASE_PTR,31)
4415 #define CAN2_RXIMR32                             CAN_RXIMR_REG(CAN2_BASE_PTR,32)
4416 #define CAN2_RXIMR33                             CAN_RXIMR_REG(CAN2_BASE_PTR,33)
4417 #define CAN2_RXIMR34                             CAN_RXIMR_REG(CAN2_BASE_PTR,34)
4418 #define CAN2_RXIMR35                             CAN_RXIMR_REG(CAN2_BASE_PTR,35)
4419 #define CAN2_RXIMR36                             CAN_RXIMR_REG(CAN2_BASE_PTR,36)
4420 #define CAN2_RXIMR37                             CAN_RXIMR_REG(CAN2_BASE_PTR,37)
4421 #define CAN2_RXIMR38                             CAN_RXIMR_REG(CAN2_BASE_PTR,38)
4422 #define CAN2_RXIMR39                             CAN_RXIMR_REG(CAN2_BASE_PTR,39)
4423 #define CAN2_RXIMR40                             CAN_RXIMR_REG(CAN2_BASE_PTR,40)
4424 #define CAN2_RXIMR41                             CAN_RXIMR_REG(CAN2_BASE_PTR,41)
4425 #define CAN2_RXIMR42                             CAN_RXIMR_REG(CAN2_BASE_PTR,42)
4426 #define CAN2_RXIMR43                             CAN_RXIMR_REG(CAN2_BASE_PTR,43)
4427 #define CAN2_RXIMR44                             CAN_RXIMR_REG(CAN2_BASE_PTR,44)
4428 #define CAN2_RXIMR45                             CAN_RXIMR_REG(CAN2_BASE_PTR,45)
4429 #define CAN2_RXIMR46                             CAN_RXIMR_REG(CAN2_BASE_PTR,46)
4430 #define CAN2_RXIMR47                             CAN_RXIMR_REG(CAN2_BASE_PTR,47)
4431 #define CAN2_RXIMR48                             CAN_RXIMR_REG(CAN2_BASE_PTR,48)
4432 #define CAN2_RXIMR49                             CAN_RXIMR_REG(CAN2_BASE_PTR,49)
4433 #define CAN2_RXIMR50                             CAN_RXIMR_REG(CAN2_BASE_PTR,50)
4434 #define CAN2_RXIMR51                             CAN_RXIMR_REG(CAN2_BASE_PTR,51)
4435 #define CAN2_RXIMR52                             CAN_RXIMR_REG(CAN2_BASE_PTR,52)
4436 #define CAN2_RXIMR53                             CAN_RXIMR_REG(CAN2_BASE_PTR,53)
4437 #define CAN2_RXIMR54                             CAN_RXIMR_REG(CAN2_BASE_PTR,54)
4438 #define CAN2_RXIMR55                             CAN_RXIMR_REG(CAN2_BASE_PTR,55)
4439 #define CAN2_RXIMR56                             CAN_RXIMR_REG(CAN2_BASE_PTR,56)
4440 #define CAN2_RXIMR57                             CAN_RXIMR_REG(CAN2_BASE_PTR,57)
4441 #define CAN2_RXIMR58                             CAN_RXIMR_REG(CAN2_BASE_PTR,58)
4442 #define CAN2_RXIMR59                             CAN_RXIMR_REG(CAN2_BASE_PTR,59)
4443 #define CAN2_RXIMR60                             CAN_RXIMR_REG(CAN2_BASE_PTR,60)
4444 #define CAN2_RXIMR61                             CAN_RXIMR_REG(CAN2_BASE_PTR,61)
4445 #define CAN2_RXIMR62                             CAN_RXIMR_REG(CAN2_BASE_PTR,62)
4446 #define CAN2_RXIMR63                             CAN_RXIMR_REG(CAN2_BASE_PTR,63)
4447 #define CAN2_GFWR                                CAN_GFWR_REG(CAN2_BASE_PTR)
4448 /* CAN - Register array accessors */
4449 #define CAN1_CS(index)                           CAN_CS_REG(CAN1_BASE_PTR,index)
4450 #define CAN2_CS(index)                           CAN_CS_REG(CAN2_BASE_PTR,index)
4451 #define CAN1_ID(index)                           CAN_ID_REG(CAN1_BASE_PTR,index)
4452 #define CAN2_ID(index)                           CAN_ID_REG(CAN2_BASE_PTR,index)
4453 #define CAN1_WORD0(index)                        CAN_WORD0_REG(CAN1_BASE_PTR,index)
4454 #define CAN2_WORD0(index)                        CAN_WORD0_REG(CAN2_BASE_PTR,index)
4455 #define CAN1_WORD1(index)                        CAN_WORD1_REG(CAN1_BASE_PTR,index)
4456 #define CAN2_WORD1(index)                        CAN_WORD1_REG(CAN2_BASE_PTR,index)
4457 #define CAN1_RXIMR(index)                        CAN_RXIMR_REG(CAN1_BASE_PTR,index)
4458 #define CAN2_RXIMR(index)                        CAN_RXIMR_REG(CAN2_BASE_PTR,index)
4459 
4460 /*!
4461  * @}
4462  */ /* end of group CAN_Register_Accessor_Macros */
4463 
4464 /*!
4465  * @}
4466  */ /* end of group CAN_Peripheral */
4467 
4468 /* ----------------------------------------------------------------------------
4469    -- CCM Peripheral Access Layer
4470    ---------------------------------------------------------------------------- */
4471 
4472 /*!
4473  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
4474  * @{
4475  */
4476 
4477 /** CCM - Register Layout Typedef */
4478 typedef struct {
4479   __IO  uint32_t CCR;                                    /**< CCM Control Register, offset: 0x0 */
4480   __IO  uint32_t CCDR;                                   /**< CCM Control Divider Register, offset: 0x4 */
4481   __I   uint32_t CSR;                                    /**< CCM Status Register, offset: 0x8 */
4482   __IO  uint32_t CCSR;                                   /**< CCM Clock Switcher Register, offset: 0xC */
4483   __IO  uint32_t CACRR;                                  /**< CCM Arm Clock Root Register, offset: 0x10 */
4484   __IO  uint32_t CBCDR;                                  /**< CCM Bus Clock Divider Register, offset: 0x14 */
4485   __IO  uint32_t CBCMR;                                  /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
4486   __IO  uint32_t CSCMR1;                                 /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
4487   __IO  uint32_t CSCMR2;                                 /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
4488   __IO  uint32_t CSCDR1;                                 /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
4489   __IO  uint32_t CS1CDR;                                 /**< CCM SSI1 Clock Divider Register, offset: 0x28 */
4490   __IO  uint32_t CS2CDR;                                 /**< CCM SSI2 Clock Divider Register, offset: 0x2C */
4491   __IO  uint32_t CDCDR;                                  /**< CCM D1 Clock Divider Register, offset: 0x30 */
4492   __IO  uint32_t CHSCCDR;                                /**< CCM HSC Clock Divider Register, offset: 0x34 */
4493   __IO  uint32_t CSCDR2;                                 /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
4494   __IO  uint32_t CSCDR3;                                 /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
4495   uint8_t RESERVED_0[4];
4496   __IO  uint32_t CWDR;                                   /**< CCM Wakeup Detector Register, offset: 0x44 */
4497   __I   uint32_t CDHIPR;                                 /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
4498   uint8_t RESERVED_1[8];
4499   __IO  uint32_t CLPCR;                                  /**< CCM Low Power Control Register, offset: 0x54 */
4500   __IO  uint32_t CISR;                                   /**< CCM Interrupt Status Register, offset: 0x58 */
4501   __IO  uint32_t CIMR;                                   /**< CCM Interrupt Mask Register, offset: 0x5C */
4502   __IO  uint32_t CCOSR;                                  /**< CCM Clock Output Source Register, offset: 0x60 */
4503   __IO  uint32_t CGPR;                                   /**< CCM General Purpose Register, offset: 0x64 */
4504   __IO  uint32_t CCGR0;                                  /**< CCM Clock Gating Register 0, offset: 0x68 */
4505   __IO  uint32_t CCGR1;                                  /**< CCM Clock Gating Register 1, offset: 0x6C */
4506   __IO  uint32_t CCGR2;                                  /**< CCM Clock Gating Register 2, offset: 0x70 */
4507   __IO  uint32_t CCGR3;                                  /**< CCM Clock Gating Register 3, offset: 0x74 */
4508   __IO  uint32_t CCGR4;                                  /**< CCM Clock Gating Register 4, offset: 0x78 */
4509   __IO  uint32_t CCGR5;                                  /**< CCM Clock Gating Register 5, offset: 0x7C */
4510   __IO  uint32_t CCGR6;                                  /**< CCM Clock Gating Register 6, offset: 0x80 */
4511   uint8_t RESERVED_2[4];
4512   __IO  uint32_t CMEOR;                                  /**< CCM Module Enable Overide Register, offset: 0x88 */
4513 } CCM_Type, *CCM_MemMapPtr;
4514 
4515 /* ----------------------------------------------------------------------------
4516    -- CCM - Register accessor macros
4517    ---------------------------------------------------------------------------- */
4518 
4519 /*!
4520  * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros
4521  * @{
4522  */
4523 
4524 /* CCM - Register accessors */
4525 #define CCM_CCR_REG(base)                        ((base)->CCR)
4526 #define CCM_CCDR_REG(base)                       ((base)->CCDR)
4527 #define CCM_CSR_REG(base)                        ((base)->CSR)
4528 #define CCM_CCSR_REG(base)                       ((base)->CCSR)
4529 #define CCM_CACRR_REG(base)                      ((base)->CACRR)
4530 #define CCM_CBCDR_REG(base)                      ((base)->CBCDR)
4531 #define CCM_CBCMR_REG(base)                      ((base)->CBCMR)
4532 #define CCM_CSCMR1_REG(base)                     ((base)->CSCMR1)
4533 #define CCM_CSCMR2_REG(base)                     ((base)->CSCMR2)
4534 #define CCM_CSCDR1_REG(base)                     ((base)->CSCDR1)
4535 #define CCM_CS1CDR_REG(base)                     ((base)->CS1CDR)
4536 #define CCM_CS2CDR_REG(base)                     ((base)->CS2CDR)
4537 #define CCM_CDCDR_REG(base)                      ((base)->CDCDR)
4538 #define CCM_CHSCCDR_REG(base)                    ((base)->CHSCCDR)
4539 #define CCM_CSCDR2_REG(base)                     ((base)->CSCDR2)
4540 #define CCM_CSCDR3_REG(base)                     ((base)->CSCDR3)
4541 #define CCM_CWDR_REG(base)                       ((base)->CWDR)
4542 #define CCM_CDHIPR_REG(base)                     ((base)->CDHIPR)
4543 #define CCM_CLPCR_REG(base)                      ((base)->CLPCR)
4544 #define CCM_CISR_REG(base)                       ((base)->CISR)
4545 #define CCM_CIMR_REG(base)                       ((base)->CIMR)
4546 #define CCM_CCOSR_REG(base)                      ((base)->CCOSR)
4547 #define CCM_CGPR_REG(base)                       ((base)->CGPR)
4548 #define CCM_CCGR0_REG(base)                      ((base)->CCGR0)
4549 #define CCM_CCGR1_REG(base)                      ((base)->CCGR1)
4550 #define CCM_CCGR2_REG(base)                      ((base)->CCGR2)
4551 #define CCM_CCGR3_REG(base)                      ((base)->CCGR3)
4552 #define CCM_CCGR4_REG(base)                      ((base)->CCGR4)
4553 #define CCM_CCGR5_REG(base)                      ((base)->CCGR5)
4554 #define CCM_CCGR6_REG(base)                      ((base)->CCGR6)
4555 #define CCM_CMEOR_REG(base)                      ((base)->CMEOR)
4556 
4557 /*!
4558  * @}
4559  */ /* end of group CCM_Register_Accessor_Macros */
4560 
4561 /* ----------------------------------------------------------------------------
4562    -- CCM Register Masks
4563    ---------------------------------------------------------------------------- */
4564 
4565 /*!
4566  * @addtogroup CCM_Register_Masks CCM Register Masks
4567  * @{
4568  */
4569 
4570 /* CCR Bit Fields */
4571 #define CCM_CCR_OSCNT_MASK                       0x7Fu
4572 #define CCM_CCR_OSCNT_SHIFT                      0
4573 #define CCM_CCR_OSCNT(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCR_OSCNT_SHIFT))&CCM_CCR_OSCNT_MASK)
4574 #define CCM_CCR_COSC_EN_MASK                     0x1000u
4575 #define CCM_CCR_COSC_EN_SHIFT                    12
4576 #define CCM_CCR_REG_BYPASS_COUNT_MASK            0x7E00000u
4577 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT           21
4578 #define CCM_CCR_REG_BYPASS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CCR_REG_BYPASS_COUNT_SHIFT))&CCM_CCR_REG_BYPASS_COUNT_MASK)
4579 #define CCM_CCR_RBC_EN_MASK                      0x8000000u
4580 #define CCM_CCR_RBC_EN_SHIFT                     27
4581 /* CCDR Bit Fields */
4582 #define CCM_CCDR_mmdc_mask_MASK                  0x10000u
4583 #define CCM_CCDR_mmdc_mask_SHIFT                 16
4584 /* CSR Bit Fields */
4585 #define CCM_CSR_REF_EN_B_MASK                    0x1u
4586 #define CCM_CSR_REF_EN_B_SHIFT                   0
4587 #define CCM_CSR_cosc_ready_MASK                  0x20u
4588 #define CCM_CSR_cosc_ready_SHIFT                 5
4589 /* CCSR Bit Fields */
4590 #define CCM_CCSR_pll3_sw_clk_sel_MASK            0x1u
4591 #define CCM_CCSR_pll3_sw_clk_sel_SHIFT           0
4592 #define CCM_CCSR_pll1_sw_clk_sel_MASK            0x4u
4593 #define CCM_CCSR_pll1_sw_clk_sel_SHIFT           2
4594 #define CCM_CCSR_step_sel_MASK                   0x100u
4595 #define CCM_CCSR_step_sel_SHIFT                  8
4596 /* CACRR Bit Fields */
4597 #define CCM_CACRR_arm_podf_MASK                  0x7u
4598 #define CCM_CACRR_arm_podf_SHIFT                 0
4599 #define CCM_CACRR_arm_podf(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_arm_podf_SHIFT))&CCM_CACRR_arm_podf_MASK)
4600 /* CBCDR Bit Fields */
4601 #define CCM_CBCDR_periph2_clk2_podf_MASK         0x7u
4602 #define CCM_CBCDR_periph2_clk2_podf_SHIFT        0
4603 #define CCM_CBCDR_periph2_clk2_podf(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_periph2_clk2_podf_SHIFT))&CCM_CBCDR_periph2_clk2_podf_MASK)
4604 #define CCM_CBCDR_fabric_mmdc_podf_MASK          0x38u
4605 #define CCM_CBCDR_fabric_mmdc_podf_SHIFT         3
4606 #define CCM_CBCDR_fabric_mmdc_podf(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_fabric_mmdc_podf_SHIFT))&CCM_CBCDR_fabric_mmdc_podf_MASK)
4607 #define CCM_CBCDR_ocram_clk_sel_MASK             0x40u
4608 #define CCM_CBCDR_ocram_clk_sel_SHIFT            6
4609 #define CCM_CBCDR_ocram_alt_clk_sel_MASK         0x80u
4610 #define CCM_CBCDR_ocram_alt_clk_sel_SHIFT        7
4611 #define CCM_CBCDR_ipg_podf_MASK                  0x300u
4612 #define CCM_CBCDR_ipg_podf_SHIFT                 8
4613 #define CCM_CBCDR_ipg_podf(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ipg_podf_SHIFT))&CCM_CBCDR_ipg_podf_MASK)
4614 #define CCM_CBCDR_ahb_podf_MASK                  0x1C00u
4615 #define CCM_CBCDR_ahb_podf_SHIFT                 10
4616 #define CCM_CBCDR_ahb_podf(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ahb_podf_SHIFT))&CCM_CBCDR_ahb_podf_MASK)
4617 #define CCM_CBCDR_ocram_podf_MASK                0x70000u
4618 #define CCM_CBCDR_ocram_podf_SHIFT               16
4619 #define CCM_CBCDR_ocram_podf(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ocram_podf_SHIFT))&CCM_CBCDR_ocram_podf_MASK)
4620 #define CCM_CBCDR_periph_clk_sel_MASK            0x2000000u
4621 #define CCM_CBCDR_periph_clk_sel_SHIFT           25
4622 #define CCM_CBCDR_periph2_clk_sel_MASK           0x4000000u
4623 #define CCM_CBCDR_periph2_clk_sel_SHIFT          26
4624 #define CCM_CBCDR_periph_clk2_podf_MASK          0x38000000u
4625 #define CCM_CBCDR_periph_clk2_podf_SHIFT         27
4626 #define CCM_CBCDR_periph_clk2_podf(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_periph_clk2_podf_SHIFT))&CCM_CBCDR_periph_clk2_podf_MASK)
4627 /* CBCMR Bit Fields */
4628 #define CCM_CBCMR_gpu_core_sel_MASK              0x30u
4629 #define CCM_CBCMR_gpu_core_sel_SHIFT             4
4630 #define CCM_CBCMR_gpu_core_sel(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_core_sel_SHIFT))&CCM_CBCMR_gpu_core_sel_MASK)
4631 #define CCM_CBCMR_gpu_axi_sel_MASK               0x300u
4632 #define CCM_CBCMR_gpu_axi_sel_SHIFT              8
4633 #define CCM_CBCMR_gpu_axi_sel(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_axi_sel_SHIFT))&CCM_CBCMR_gpu_axi_sel_MASK)
4634 #define CCM_CBCMR_pcie_axi_clk_sel_MASK          0x400u
4635 #define CCM_CBCMR_pcie_axi_clk_sel_SHIFT         10
4636 #define CCM_CBCMR_periph_clk2_sel_MASK           0x3000u
4637 #define CCM_CBCMR_periph_clk2_sel_SHIFT          12
4638 #define CCM_CBCMR_periph_clk2_sel(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_periph_clk2_sel_SHIFT))&CCM_CBCMR_periph_clk2_sel_MASK)
4639 #define CCM_CBCMR_pre_periph_clk_sel_MASK        0xC0000u
4640 #define CCM_CBCMR_pre_periph_clk_sel_SHIFT       18
4641 #define CCM_CBCMR_pre_periph_clk_sel(x)          (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_pre_periph_clk_sel_SHIFT))&CCM_CBCMR_pre_periph_clk_sel_MASK)
4642 #define CCM_CBCMR_periph2_clk2_sel_MASK          0x100000u
4643 #define CCM_CBCMR_periph2_clk2_sel_SHIFT         20
4644 #define CCM_CBCMR_pre_periph2_clk_sel_MASK       0x600000u
4645 #define CCM_CBCMR_pre_periph2_clk_sel_SHIFT      21
4646 #define CCM_CBCMR_pre_periph2_clk_sel(x)         (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_pre_periph2_clk_sel_SHIFT))&CCM_CBCMR_pre_periph2_clk_sel_MASK)
4647 #define CCM_CBCMR_lcdif1_podf_MASK               0x3800000u
4648 #define CCM_CBCMR_lcdif1_podf_SHIFT              23
4649 #define CCM_CBCMR_lcdif1_podf(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_lcdif1_podf_SHIFT))&CCM_CBCMR_lcdif1_podf_MASK)
4650 #define CCM_CBCMR_gpu_axi_podf_MASK              0x1C000000u
4651 #define CCM_CBCMR_gpu_axi_podf_SHIFT             26
4652 #define CCM_CBCMR_gpu_axi_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_axi_podf_SHIFT))&CCM_CBCMR_gpu_axi_podf_MASK)
4653 #define CCM_CBCMR_gpu_core_podf_MASK             0xE0000000u
4654 #define CCM_CBCMR_gpu_core_podf_SHIFT            29
4655 #define CCM_CBCMR_gpu_core_podf(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_core_podf_SHIFT))&CCM_CBCMR_gpu_core_podf_MASK)
4656 /* CSCMR1 Bit Fields */
4657 #define CCM_CSCMR1_perclk_podf_MASK              0x3Fu
4658 #define CCM_CSCMR1_perclk_podf_SHIFT             0
4659 #define CCM_CSCMR1_perclk_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_perclk_podf_SHIFT))&CCM_CSCMR1_perclk_podf_MASK)
4660 #define CCM_CSCMR1_perclk_clk_sel_MASK           0x40u
4661 #define CCM_CSCMR1_perclk_clk_sel_SHIFT          6
4662 #define CCM_CSCMR1_qspi1_sel_MASK                0x380u
4663 #define CCM_CSCMR1_qspi1_sel_SHIFT               7
4664 #define CCM_CSCMR1_qspi1_sel(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_qspi1_sel_SHIFT))&CCM_CSCMR1_qspi1_sel_MASK)
4665 #define CCM_CSCMR1_ssi1_clk_sel_MASK             0xC00u
4666 #define CCM_CSCMR1_ssi1_clk_sel_SHIFT            10
4667 #define CCM_CSCMR1_ssi1_clk_sel(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi1_clk_sel_SHIFT))&CCM_CSCMR1_ssi1_clk_sel_MASK)
4668 #define CCM_CSCMR1_ssi2_clk_sel_MASK             0x3000u
4669 #define CCM_CSCMR1_ssi2_clk_sel_SHIFT            12
4670 #define CCM_CSCMR1_ssi2_clk_sel(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi2_clk_sel_SHIFT))&CCM_CSCMR1_ssi2_clk_sel_MASK)
4671 #define CCM_CSCMR1_ssi3_clk_sel_MASK             0xC000u
4672 #define CCM_CSCMR1_ssi3_clk_sel_SHIFT            14
4673 #define CCM_CSCMR1_ssi3_clk_sel(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi3_clk_sel_SHIFT))&CCM_CSCMR1_ssi3_clk_sel_MASK)
4674 #define CCM_CSCMR1_usdhc1_clk_sel_MASK           0x10000u
4675 #define CCM_CSCMR1_usdhc1_clk_sel_SHIFT          16
4676 #define CCM_CSCMR1_usdhc2_clk_sel_MASK           0x20000u
4677 #define CCM_CSCMR1_usdhc2_clk_sel_SHIFT          17
4678 #define CCM_CSCMR1_usdhc3_clk_sel_MASK           0x40000u
4679 #define CCM_CSCMR1_usdhc3_clk_sel_SHIFT          18
4680 #define CCM_CSCMR1_usdhc4_clk_sel_MASK           0x80000u
4681 #define CCM_CSCMR1_usdhc4_clk_sel_SHIFT          19
4682 #define CCM_CSCMR1_lcdif2_podf_MASK              0x700000u
4683 #define CCM_CSCMR1_lcdif2_podf_SHIFT             20
4684 #define CCM_CSCMR1_lcdif2_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_lcdif2_podf_SHIFT))&CCM_CSCMR1_lcdif2_podf_MASK)
4685 #define CCM_CSCMR1_aclk_eim_slow_podf_MASK       0x3800000u
4686 #define CCM_CSCMR1_aclk_eim_slow_podf_SHIFT      23
4687 #define CCM_CSCMR1_aclk_eim_slow_podf(x)         (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_aclk_eim_slow_podf_SHIFT))&CCM_CSCMR1_aclk_eim_slow_podf_MASK)
4688 #define CCM_CSCMR1_qspi1_podf_MASK               0x1C000000u
4689 #define CCM_CSCMR1_qspi1_podf_SHIFT              26
4690 #define CCM_CSCMR1_qspi1_podf(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_qspi1_podf_SHIFT))&CCM_CSCMR1_qspi1_podf_MASK)
4691 #define CCM_CSCMR1_aclk_eim_slow_sel_MASK        0x60000000u
4692 #define CCM_CSCMR1_aclk_eim_slow_sel_SHIFT       29
4693 #define CCM_CSCMR1_aclk_eim_slow_sel(x)          (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_aclk_eim_slow_sel_SHIFT))&CCM_CSCMR1_aclk_eim_slow_sel_MASK)
4694 /* CSCMR2 Bit Fields */
4695 #define CCM_CSCMR2_can_clk_podf_MASK             0xFCu
4696 #define CCM_CSCMR2_can_clk_podf_SHIFT            2
4697 #define CCM_CSCMR2_can_clk_podf(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_can_clk_podf_SHIFT))&CCM_CSCMR2_can_clk_podf_MASK)
4698 #define CCM_CSCMR2_can_clk_sel_MASK              0x300u
4699 #define CCM_CSCMR2_can_clk_sel_SHIFT             8
4700 #define CCM_CSCMR2_can_clk_sel(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_can_clk_sel_SHIFT))&CCM_CSCMR2_can_clk_sel_MASK)
4701 #define CCM_CSCMR2_ldb_di0_div_MASK              0x400u
4702 #define CCM_CSCMR2_ldb_di0_div_SHIFT             10
4703 #define CCM_CSCMR2_ldb_di1_div_MASK              0x800u
4704 #define CCM_CSCMR2_ldb_di1_div_SHIFT             11
4705 #define CCM_CSCMR2_esai_clk_sel_MASK             0x180000u
4706 #define CCM_CSCMR2_esai_clk_sel_SHIFT            19
4707 #define CCM_CSCMR2_esai_clk_sel(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_esai_clk_sel_SHIFT))&CCM_CSCMR2_esai_clk_sel_MASK)
4708 #define CCM_CSCMR2_vid_clk_sel_MASK              0xE00000u
4709 #define CCM_CSCMR2_vid_clk_sel_SHIFT             21
4710 #define CCM_CSCMR2_vid_clk_sel(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_sel_SHIFT))&CCM_CSCMR2_vid_clk_sel_MASK)
4711 #define CCM_CSCMR2_vid_clk_pre_podf_MASK         0x3000000u
4712 #define CCM_CSCMR2_vid_clk_pre_podf_SHIFT        24
4713 #define CCM_CSCMR2_vid_clk_pre_podf(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_pre_podf_SHIFT))&CCM_CSCMR2_vid_clk_pre_podf_MASK)
4714 #define CCM_CSCMR2_vid_clk_podf_MASK             0x1C000000u
4715 #define CCM_CSCMR2_vid_clk_podf_SHIFT            26
4716 #define CCM_CSCMR2_vid_clk_podf(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_podf_SHIFT))&CCM_CSCMR2_vid_clk_podf_MASK)
4717 /* CSCDR1 Bit Fields */
4718 #define CCM_CSCDR1_uart_clk_podf_MASK            0x3Fu
4719 #define CCM_CSCDR1_uart_clk_podf_SHIFT           0
4720 #define CCM_CSCDR1_uart_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_uart_clk_podf_SHIFT))&CCM_CSCDR1_uart_clk_podf_MASK)
4721 #define CCM_CSCDR1_uart_clk_sel_MASK             0x40u
4722 #define CCM_CSCDR1_uart_clk_sel_SHIFT            6
4723 #define CCM_CSCDR1_usdhc1_podf_MASK              0x3800u
4724 #define CCM_CSCDR1_usdhc1_podf_SHIFT             11
4725 #define CCM_CSCDR1_usdhc1_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc1_podf_SHIFT))&CCM_CSCDR1_usdhc1_podf_MASK)
4726 #define CCM_CSCDR1_usdhc2_podf_MASK              0x70000u
4727 #define CCM_CSCDR1_usdhc2_podf_SHIFT             16
4728 #define CCM_CSCDR1_usdhc2_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc2_podf_SHIFT))&CCM_CSCDR1_usdhc2_podf_MASK)
4729 #define CCM_CSCDR1_usdhc3_podf_MASK              0x380000u
4730 #define CCM_CSCDR1_usdhc3_podf_SHIFT             19
4731 #define CCM_CSCDR1_usdhc3_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc3_podf_SHIFT))&CCM_CSCDR1_usdhc3_podf_MASK)
4732 #define CCM_CSCDR1_usdhc4_podf_MASK              0x1C00000u
4733 #define CCM_CSCDR1_usdhc4_podf_SHIFT             22
4734 #define CCM_CSCDR1_usdhc4_podf(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc4_podf_SHIFT))&CCM_CSCDR1_usdhc4_podf_MASK)
4735 /* CS1CDR Bit Fields */
4736 #define CCM_CS1CDR_ssi1_clk_podf_MASK            0x3Fu
4737 #define CCM_CS1CDR_ssi1_clk_podf_SHIFT           0
4738 #define CCM_CS1CDR_ssi1_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi1_clk_podf_SHIFT))&CCM_CS1CDR_ssi1_clk_podf_MASK)
4739 #define CCM_CS1CDR_ssi1_clk_pred_MASK            0x1C0u
4740 #define CCM_CS1CDR_ssi1_clk_pred_SHIFT           6
4741 #define CCM_CS1CDR_ssi1_clk_pred(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi1_clk_pred_SHIFT))&CCM_CS1CDR_ssi1_clk_pred_MASK)
4742 #define CCM_CS1CDR_esai_clk_pred_MASK            0xE00u
4743 #define CCM_CS1CDR_esai_clk_pred_SHIFT           9
4744 #define CCM_CS1CDR_esai_clk_pred(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_esai_clk_pred_SHIFT))&CCM_CS1CDR_esai_clk_pred_MASK)
4745 #define CCM_CS1CDR_ssi3_clk_podf_MASK            0x3F0000u
4746 #define CCM_CS1CDR_ssi3_clk_podf_SHIFT           16
4747 #define CCM_CS1CDR_ssi3_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi3_clk_podf_SHIFT))&CCM_CS1CDR_ssi3_clk_podf_MASK)
4748 #define CCM_CS1CDR_ssi3_clk_pred_MASK            0x1C00000u
4749 #define CCM_CS1CDR_ssi3_clk_pred_SHIFT           22
4750 #define CCM_CS1CDR_ssi3_clk_pred(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi3_clk_pred_SHIFT))&CCM_CS1CDR_ssi3_clk_pred_MASK)
4751 #define CCM_CS1CDR_esai_clk_podf_MASK            0xE000000u
4752 #define CCM_CS1CDR_esai_clk_podf_SHIFT           25
4753 #define CCM_CS1CDR_esai_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_esai_clk_podf_SHIFT))&CCM_CS1CDR_esai_clk_podf_MASK)
4754 /* CS2CDR Bit Fields */
4755 #define CCM_CS2CDR_ssi2_clk_podf_MASK            0x3Fu
4756 #define CCM_CS2CDR_ssi2_clk_podf_SHIFT           0
4757 #define CCM_CS2CDR_ssi2_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ssi2_clk_podf_SHIFT))&CCM_CS2CDR_ssi2_clk_podf_MASK)
4758 #define CCM_CS2CDR_ssi2_clk_pred_MASK            0x1C0u
4759 #define CCM_CS2CDR_ssi2_clk_pred_SHIFT           6
4760 #define CCM_CS2CDR_ssi2_clk_pred(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ssi2_clk_pred_SHIFT))&CCM_CS2CDR_ssi2_clk_pred_MASK)
4761 #define CCM_CS2CDR_ldb_di0_clk_sel_MASK          0xE00u
4762 #define CCM_CS2CDR_ldb_di0_clk_sel_SHIFT         9
4763 #define CCM_CS2CDR_ldb_di0_clk_sel(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ldb_di0_clk_sel_SHIFT))&CCM_CS2CDR_ldb_di0_clk_sel_MASK)
4764 #define CCM_CS2CDR_ldb_di1_clk_sel_MASK          0x7000u
4765 #define CCM_CS2CDR_ldb_di1_clk_sel_SHIFT         12
4766 #define CCM_CS2CDR_ldb_di1_clk_sel(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ldb_di1_clk_sel_SHIFT))&CCM_CS2CDR_ldb_di1_clk_sel_MASK)
4767 #define CCM_CS2CDR_qspi2_clk_sel_MASK            0x38000u
4768 #define CCM_CS2CDR_qspi2_clk_sel_SHIFT           15
4769 #define CCM_CS2CDR_qspi2_clk_sel(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_sel_SHIFT))&CCM_CS2CDR_qspi2_clk_sel_MASK)
4770 #define CCM_CS2CDR_qspi2_clk_pred_MASK           0x1C0000u
4771 #define CCM_CS2CDR_qspi2_clk_pred_SHIFT          18
4772 #define CCM_CS2CDR_qspi2_clk_pred(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_pred_SHIFT))&CCM_CS2CDR_qspi2_clk_pred_MASK)
4773 #define CCM_CS2CDR_qspi2_clk_podf_MASK           0x7E00000u
4774 #define CCM_CS2CDR_qspi2_clk_podf_SHIFT          21
4775 #define CCM_CS2CDR_qspi2_clk_podf(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_podf_SHIFT))&CCM_CS2CDR_qspi2_clk_podf_MASK)
4776 /* CDCDR Bit Fields */
4777 #define CCM_CDCDR_audio_clk_sel_MASK             0x180u
4778 #define CCM_CDCDR_audio_clk_sel_SHIFT            7
4779 #define CCM_CDCDR_audio_clk_sel(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_sel_SHIFT))&CCM_CDCDR_audio_clk_sel_MASK)
4780 #define CCM_CDCDR_audio_clk_podf_MASK            0xE00u
4781 #define CCM_CDCDR_audio_clk_podf_SHIFT           9
4782 #define CCM_CDCDR_audio_clk_podf(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_podf_SHIFT))&CCM_CDCDR_audio_clk_podf_MASK)
4783 #define CCM_CDCDR_audio_clk_pred_MASK            0x7000u
4784 #define CCM_CDCDR_audio_clk_pred_SHIFT           12
4785 #define CCM_CDCDR_audio_clk_pred(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_pred_SHIFT))&CCM_CDCDR_audio_clk_pred_MASK)
4786 #define CCM_CDCDR_spdif0_clk_sel_MASK            0x300000u
4787 #define CCM_CDCDR_spdif0_clk_sel_SHIFT           20
4788 #define CCM_CDCDR_spdif0_clk_sel(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_sel_SHIFT))&CCM_CDCDR_spdif0_clk_sel_MASK)
4789 #define CCM_CDCDR_spdif0_clk_podf_MASK           0x1C00000u
4790 #define CCM_CDCDR_spdif0_clk_podf_SHIFT          22
4791 #define CCM_CDCDR_spdif0_clk_podf(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_podf_SHIFT))&CCM_CDCDR_spdif0_clk_podf_MASK)
4792 #define CCM_CDCDR_spdif0_clk_pred_MASK           0xE000000u
4793 #define CCM_CDCDR_spdif0_clk_pred_SHIFT          25
4794 #define CCM_CDCDR_spdif0_clk_pred(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_pred_SHIFT))&CCM_CDCDR_spdif0_clk_pred_MASK)
4795 /* CHSCCDR Bit Fields */
4796 #define CCM_CHSCCDR_m4_clk_sel_MASK              0x7u
4797 #define CCM_CHSCCDR_m4_clk_sel_SHIFT             0
4798 #define CCM_CHSCCDR_m4_clk_sel(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_clk_sel_SHIFT))&CCM_CHSCCDR_m4_clk_sel_MASK)
4799 #define CCM_CHSCCDR_m4_podf_MASK                 0x38u
4800 #define CCM_CHSCCDR_m4_podf_SHIFT                3
4801 #define CCM_CHSCCDR_m4_podf(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_podf_SHIFT))&CCM_CHSCCDR_m4_podf_MASK)
4802 #define CCM_CHSCCDR_m4_pre_clk_sel_MASK          0x1C0u
4803 #define CCM_CHSCCDR_m4_pre_clk_sel_SHIFT         6
4804 #define CCM_CHSCCDR_m4_pre_clk_sel(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_pre_clk_sel_SHIFT))&CCM_CHSCCDR_m4_pre_clk_sel_MASK)
4805 #define CCM_CHSCCDR_enet_clk_sel_MASK            0xE00u
4806 #define CCM_CHSCCDR_enet_clk_sel_SHIFT           9
4807 #define CCM_CHSCCDR_enet_clk_sel(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_clk_sel_SHIFT))&CCM_CHSCCDR_enet_clk_sel_MASK)
4808 #define CCM_CHSCCDR_enet_podf_MASK               0x7000u
4809 #define CCM_CHSCCDR_enet_podf_SHIFT              12
4810 #define CCM_CHSCCDR_enet_podf(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_podf_SHIFT))&CCM_CHSCCDR_enet_podf_MASK)
4811 #define CCM_CHSCCDR_enet_pre_clk_sel_MASK        0x38000u
4812 #define CCM_CHSCCDR_enet_pre_clk_sel_SHIFT       15
4813 #define CCM_CHSCCDR_enet_pre_clk_sel(x)          (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_pre_clk_sel_SHIFT))&CCM_CHSCCDR_enet_pre_clk_sel_MASK)
4814 /* CSCDR2 Bit Fields */
4815 #define CCM_CSCDR2_lcdif2_clk_sel_MASK           0x7u
4816 #define CCM_CSCDR2_lcdif2_clk_sel_SHIFT          0
4817 #define CCM_CSCDR2_lcdif2_clk_sel(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_clk_sel_SHIFT))&CCM_CSCDR2_lcdif2_clk_sel_MASK)
4818 #define CCM_CSCDR2_lcdif2_pred_MASK              0x38u
4819 #define CCM_CSCDR2_lcdif2_pred_SHIFT             3
4820 #define CCM_CSCDR2_lcdif2_pred(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_pred_SHIFT))&CCM_CSCDR2_lcdif2_pred_MASK)
4821 #define CCM_CSCDR2_lcdif2_pre_clk_sel_MASK       0x1C0u
4822 #define CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT      6
4823 #define CCM_CSCDR2_lcdif2_pre_clk_sel(x)         (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT))&CCM_CSCDR2_lcdif2_pre_clk_sel_MASK)
4824 #define CCM_CSCDR2_lcdif1_clk_sel_MASK           0xE00u
4825 #define CCM_CSCDR2_lcdif1_clk_sel_SHIFT          9
4826 #define CCM_CSCDR2_lcdif1_clk_sel(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_clk_sel_SHIFT))&CCM_CSCDR2_lcdif1_clk_sel_MASK)
4827 #define CCM_CSCDR2_lcdif1_pred_MASK              0x7000u
4828 #define CCM_CSCDR2_lcdif1_pred_SHIFT             12
4829 #define CCM_CSCDR2_lcdif1_pred(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_pred_SHIFT))&CCM_CSCDR2_lcdif1_pred_MASK)
4830 #define CCM_CSCDR2_lcdif1_pre_clk_sel_MASK       0x38000u
4831 #define CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT      15
4832 #define CCM_CSCDR2_lcdif1_pre_clk_sel(x)         (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT))&CCM_CSCDR2_lcdif1_pre_clk_sel_MASK)
4833 #define CCM_CSCDR2_ecspi_clk_sel_MASK            0x40000u
4834 #define CCM_CSCDR2_ecspi_clk_sel_SHIFT           18
4835 #define CCM_CSCDR2_ecspi_clk_podf_MASK           0x1F80000u
4836 #define CCM_CSCDR2_ecspi_clk_podf_SHIFT          19
4837 #define CCM_CSCDR2_ecspi_clk_podf(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_ecspi_clk_podf_SHIFT))&CCM_CSCDR2_ecspi_clk_podf_MASK)
4838 /* CSCDR3 Bit Fields */
4839 #define CCM_CSCDR3_csi_clk_sel_MASK              0x600u
4840 #define CCM_CSCDR3_csi_clk_sel_SHIFT             9
4841 #define CCM_CSCDR3_csi_clk_sel(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_csi_clk_sel_SHIFT))&CCM_CSCDR3_csi_clk_sel_MASK)
4842 #define CCM_CSCDR3_csi_podf_MASK                 0x3800u
4843 #define CCM_CSCDR3_csi_podf_SHIFT                11
4844 #define CCM_CSCDR3_csi_podf(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_csi_podf_SHIFT))&CCM_CSCDR3_csi_podf_MASK)
4845 #define CCM_CSCDR3_display_clk_sel_MASK          0xC000u
4846 #define CCM_CSCDR3_display_clk_sel_SHIFT         14
4847 #define CCM_CSCDR3_display_clk_sel(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_display_clk_sel_SHIFT))&CCM_CSCDR3_display_clk_sel_MASK)
4848 #define CCM_CSCDR3_display_podf_MASK             0x70000u
4849 #define CCM_CSCDR3_display_podf_SHIFT            16
4850 #define CCM_CSCDR3_display_podf(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_display_podf_SHIFT))&CCM_CSCDR3_display_podf_MASK)
4851 /* CWDR Bit Fields */
4852 /* CDHIPR Bit Fields */
4853 #define CCM_CDHIPR_ocram_podf_busy_MASK          0x1u
4854 #define CCM_CDHIPR_ocram_podf_busy_SHIFT         0
4855 #define CCM_CDHIPR_ahb_podf_busy_MASK            0x2u
4856 #define CCM_CDHIPR_ahb_podf_busy_SHIFT           1
4857 #define CCM_CDHIPR_mmdc_podf_busy_MASK           0x4u
4858 #define CCM_CDHIPR_mmdc_podf_busy_SHIFT          2
4859 #define CCM_CDHIPR_periph2_clk_sel_busy_MASK     0x8u
4860 #define CCM_CDHIPR_periph2_clk_sel_busy_SHIFT    3
4861 #define CCM_CDHIPR_periph_clk_sel_busy_MASK      0x20u
4862 #define CCM_CDHIPR_periph_clk_sel_busy_SHIFT     5
4863 #define CCM_CDHIPR_arm_podf_busy_MASK            0x10000u
4864 #define CCM_CDHIPR_arm_podf_busy_SHIFT           16
4865 /* CLPCR Bit Fields */
4866 #define CCM_CLPCR_LPM_MASK                       0x3u
4867 #define CCM_CLPCR_LPM_SHIFT                      0
4868 #define CCM_CLPCR_LPM(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CLPCR_LPM_SHIFT))&CCM_CLPCR_LPM_MASK)
4869 #define CCM_CLPCR_ARM_clk_dis_on_lpm_MASK        0x20u
4870 #define CCM_CLPCR_ARM_clk_dis_on_lpm_SHIFT       5
4871 #define CCM_CLPCR_SBYOS_MASK                     0x40u
4872 #define CCM_CLPCR_SBYOS_SHIFT                    6
4873 #define CCM_CLPCR_dis_ref_osc_MASK               0x80u
4874 #define CCM_CLPCR_dis_ref_osc_SHIFT              7
4875 #define CCM_CLPCR_VSTBY_MASK                     0x100u
4876 #define CCM_CLPCR_VSTBY_SHIFT                    8
4877 #define CCM_CLPCR_stby_count_MASK                0x600u
4878 #define CCM_CLPCR_stby_count_SHIFT               9
4879 #define CCM_CLPCR_stby_count(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CLPCR_stby_count_SHIFT))&CCM_CLPCR_stby_count_MASK)
4880 #define CCM_CLPCR_cosc_pwrdown_MASK              0x800u
4881 #define CCM_CLPCR_cosc_pwrdown_SHIFT             11
4882 #define CCM_CLPCR_bypass_mmdc_lpm_hs_MASK        0x200000u
4883 #define CCM_CLPCR_bypass_mmdc_lpm_hs_SHIFT       21
4884 #define CCM_CLPCR_mask_core0_wfi_MASK            0x400000u
4885 #define CCM_CLPCR_mask_core0_wfi_SHIFT           22
4886 #define CCM_CLPCR_mask_scu_idle_MASK             0x4000000u
4887 #define CCM_CLPCR_mask_scu_idle_SHIFT            26
4888 #define CCM_CLPCR_mask_l2cc_idle_MASK            0x8000000u
4889 #define CCM_CLPCR_mask_l2cc_idle_SHIFT           27
4890 /* CISR Bit Fields */
4891 #define CCM_CISR_lrf_pll_MASK                    0x1u
4892 #define CCM_CISR_lrf_pll_SHIFT                   0
4893 #define CCM_CISR_cosc_ready_MASK                 0x40u
4894 #define CCM_CISR_cosc_ready_SHIFT                6
4895 #define CCM_CISR_ocram_podf_loaded_MASK          0x20000u
4896 #define CCM_CISR_ocram_podf_loaded_SHIFT         17
4897 #define CCM_CISR_periph2_clk_sel_loaded_MASK     0x80000u
4898 #define CCM_CISR_periph2_clk_sel_loaded_SHIFT    19
4899 #define CCM_CISR_ahb_podf_loaded_MASK            0x100000u
4900 #define CCM_CISR_ahb_podf_loaded_SHIFT           20
4901 #define CCM_CISR_mmdc_podf_loaded_MASK           0x200000u
4902 #define CCM_CISR_mmdc_podf_loaded_SHIFT          21
4903 #define CCM_CISR_periph_clk_sel_loaded_MASK      0x400000u
4904 #define CCM_CISR_periph_clk_sel_loaded_SHIFT     22
4905 #define CCM_CISR_arm_podf_loaded_MASK            0x4000000u
4906 #define CCM_CISR_arm_podf_loaded_SHIFT           26
4907 /* CIMR Bit Fields */
4908 #define CCM_CIMR_mask_lrf_pll_MASK               0x1u
4909 #define CCM_CIMR_mask_lrf_pll_SHIFT              0
4910 #define CCM_CIMR_mask_cosc_ready_MASK            0x40u
4911 #define CCM_CIMR_mask_cosc_ready_SHIFT           6
4912 #define CCM_CIMR_mask_ocram_podf_loaded_MASK     0x20000u
4913 #define CCM_CIMR_mask_ocram_podf_loaded_SHIFT    17
4914 #define CCM_CIMR_mask_periph2_clk_sel_loaded_MASK 0x80000u
4915 #define CCM_CIMR_mask_periph2_clk_sel_loaded_SHIFT 19
4916 #define CCM_CIMR_mask_ahb_podf_loaded_MASK       0x100000u
4917 #define CCM_CIMR_mask_ahb_podf_loaded_SHIFT      20
4918 #define CCM_CIMR_mask_mmdc_podf_loaded_MASK      0x200000u
4919 #define CCM_CIMR_mask_mmdc_podf_loaded_SHIFT     21
4920 #define CCM_CIMR_mask_periph_clk_sel_loaded_MASK 0x400000u
4921 #define CCM_CIMR_mask_periph_clk_sel_loaded_SHIFT 22
4922 #define CCM_CIMR_arm_podf_loaded_MASK            0x4000000u
4923 #define CCM_CIMR_arm_podf_loaded_SHIFT           26
4924 /* CCOSR Bit Fields */
4925 #define CCM_CCOSR_CLKO_SEL_MASK                  0xFu
4926 #define CCM_CCOSR_CLKO_SEL_SHIFT                 0
4927 #define CCM_CCOSR_CLKO_SEL(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO_SEL_SHIFT))&CCM_CCOSR_CLKO_SEL_MASK)
4928 #define CCM_CCOSR_CLKO1_DIV_MASK                 0x70u
4929 #define CCM_CCOSR_CLKO1_DIV_SHIFT                4
4930 #define CCM_CCOSR_CLKO1_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO1_DIV_SHIFT))&CCM_CCOSR_CLKO1_DIV_MASK)
4931 #define CCM_CCOSR_CLKO1_EN_MASK                  0x80u
4932 #define CCM_CCOSR_CLKO1_EN_SHIFT                 7
4933 #define CCM_CCOSR_CLK_OUT_SEL_MASK               0x100u
4934 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT              8
4935 #define CCM_CCOSR_CLKO2_SEL_MASK                 0x1F0000u
4936 #define CCM_CCOSR_CLKO2_SEL_SHIFT                16
4937 #define CCM_CCOSR_CLKO2_SEL(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO2_SEL_SHIFT))&CCM_CCOSR_CLKO2_SEL_MASK)
4938 #define CCM_CCOSR_CLKO2_DIV_MASK                 0xE00000u
4939 #define CCM_CCOSR_CLKO2_DIV_SHIFT                21
4940 #define CCM_CCOSR_CLKO2_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO2_DIV_SHIFT))&CCM_CCOSR_CLKO2_DIV_MASK)
4941 #define CCM_CCOSR_CLKO2_EN_MASK                  0x1000000u
4942 #define CCM_CCOSR_CLKO2_EN_SHIFT                 24
4943 /* CGPR Bit Fields */
4944 #define CCM_CGPR_pmic_delay_scaler_MASK          0x1u
4945 #define CCM_CGPR_pmic_delay_scaler_SHIFT         0
4946 #define CCM_CGPR_mmdc_ext_clk_dis_MASK           0x4u
4947 #define CCM_CGPR_mmdc_ext_clk_dis_SHIFT          2
4948 #define CCM_CGPR_efuse_prog_supply_gate_MASK     0x10u
4949 #define CCM_CGPR_efuse_prog_supply_gate_SHIFT    4
4950 #define CCM_CGPR_FPL_MASK                        0x10000u
4951 #define CCM_CGPR_FPL_SHIFT                       16
4952 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK            0x20000u
4953 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT           17
4954 /* CCGR0 Bit Fields */
4955 #define CCM_CCGR0_CG0_MASK                       0x3u
4956 #define CCM_CCGR0_CG0_SHIFT                      0
4957 #define CCM_CCGR0_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG0_SHIFT))&CCM_CCGR0_CG0_MASK)
4958 #define CCM_CCGR0_CG1_MASK                       0xCu
4959 #define CCM_CCGR0_CG1_SHIFT                      2
4960 #define CCM_CCGR0_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG1_SHIFT))&CCM_CCGR0_CG1_MASK)
4961 #define CCM_CCGR0_CG2_MASK                       0x30u
4962 #define CCM_CCGR0_CG2_SHIFT                      4
4963 #define CCM_CCGR0_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG2_SHIFT))&CCM_CCGR0_CG2_MASK)
4964 #define CCM_CCGR0_CG3_MASK                       0xC0u
4965 #define CCM_CCGR0_CG3_SHIFT                      6
4966 #define CCM_CCGR0_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG3_SHIFT))&CCM_CCGR0_CG3_MASK)
4967 #define CCM_CCGR0_CG4_MASK                       0x300u
4968 #define CCM_CCGR0_CG4_SHIFT                      8
4969 #define CCM_CCGR0_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG4_SHIFT))&CCM_CCGR0_CG4_MASK)
4970 #define CCM_CCGR0_CG5_MASK                       0xC00u
4971 #define CCM_CCGR0_CG5_SHIFT                      10
4972 #define CCM_CCGR0_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG5_SHIFT))&CCM_CCGR0_CG5_MASK)
4973 #define CCM_CCGR0_CG6_MASK                       0x3000u
4974 #define CCM_CCGR0_CG6_SHIFT                      12
4975 #define CCM_CCGR0_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG6_SHIFT))&CCM_CCGR0_CG6_MASK)
4976 #define CCM_CCGR0_CG7_MASK                       0xC000u
4977 #define CCM_CCGR0_CG7_SHIFT                      14
4978 #define CCM_CCGR0_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG7_SHIFT))&CCM_CCGR0_CG7_MASK)
4979 #define CCM_CCGR0_CG8_MASK                       0x30000u
4980 #define CCM_CCGR0_CG8_SHIFT                      16
4981 #define CCM_CCGR0_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG8_SHIFT))&CCM_CCGR0_CG8_MASK)
4982 #define CCM_CCGR0_CG9_MASK                       0xC0000u
4983 #define CCM_CCGR0_CG9_SHIFT                      18
4984 #define CCM_CCGR0_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG9_SHIFT))&CCM_CCGR0_CG9_MASK)
4985 #define CCM_CCGR0_CG10_MASK                      0x300000u
4986 #define CCM_CCGR0_CG10_SHIFT                     20
4987 #define CCM_CCGR0_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG10_SHIFT))&CCM_CCGR0_CG10_MASK)
4988 #define CCM_CCGR0_CG11_MASK                      0xC00000u
4989 #define CCM_CCGR0_CG11_SHIFT                     22
4990 #define CCM_CCGR0_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG11_SHIFT))&CCM_CCGR0_CG11_MASK)
4991 #define CCM_CCGR0_CG12_MASK                      0x3000000u
4992 #define CCM_CCGR0_CG12_SHIFT                     24
4993 #define CCM_CCGR0_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG12_SHIFT))&CCM_CCGR0_CG12_MASK)
4994 #define CCM_CCGR0_CG13_MASK                      0xC000000u
4995 #define CCM_CCGR0_CG13_SHIFT                     26
4996 #define CCM_CCGR0_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG13_SHIFT))&CCM_CCGR0_CG13_MASK)
4997 #define CCM_CCGR0_CG14_MASK                      0x30000000u
4998 #define CCM_CCGR0_CG14_SHIFT                     28
4999 #define CCM_CCGR0_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG14_SHIFT))&CCM_CCGR0_CG14_MASK)
5000 #define CCM_CCGR0_CG15_MASK                      0xC0000000u
5001 #define CCM_CCGR0_CG15_SHIFT                     30
5002 #define CCM_CCGR0_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG15_SHIFT))&CCM_CCGR0_CG15_MASK)
5003 /* CCGR1 Bit Fields */
5004 #define CCM_CCGR1_CG0_MASK                       0x3u
5005 #define CCM_CCGR1_CG0_SHIFT                      0
5006 #define CCM_CCGR1_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG0_SHIFT))&CCM_CCGR1_CG0_MASK)
5007 #define CCM_CCGR1_CG1_MASK                       0xCu
5008 #define CCM_CCGR1_CG1_SHIFT                      2
5009 #define CCM_CCGR1_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG1_SHIFT))&CCM_CCGR1_CG1_MASK)
5010 #define CCM_CCGR1_CG2_MASK                       0x30u
5011 #define CCM_CCGR1_CG2_SHIFT                      4
5012 #define CCM_CCGR1_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG2_SHIFT))&CCM_CCGR1_CG2_MASK)
5013 #define CCM_CCGR1_CG3_MASK                       0xC0u
5014 #define CCM_CCGR1_CG3_SHIFT                      6
5015 #define CCM_CCGR1_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG3_SHIFT))&CCM_CCGR1_CG3_MASK)
5016 #define CCM_CCGR1_CG4_MASK                       0x300u
5017 #define CCM_CCGR1_CG4_SHIFT                      8
5018 #define CCM_CCGR1_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG4_SHIFT))&CCM_CCGR1_CG4_MASK)
5019 #define CCM_CCGR1_CG5_MASK                       0xC00u
5020 #define CCM_CCGR1_CG5_SHIFT                      10
5021 #define CCM_CCGR1_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG5_SHIFT))&CCM_CCGR1_CG5_MASK)
5022 #define CCM_CCGR1_CG6_MASK                       0x3000u
5023 #define CCM_CCGR1_CG6_SHIFT                      12
5024 #define CCM_CCGR1_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG6_SHIFT))&CCM_CCGR1_CG6_MASK)
5025 #define CCM_CCGR1_CG7_MASK                       0xC000u
5026 #define CCM_CCGR1_CG7_SHIFT                      14
5027 #define CCM_CCGR1_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG7_SHIFT))&CCM_CCGR1_CG7_MASK)
5028 #define CCM_CCGR1_CG8_MASK                       0x30000u
5029 #define CCM_CCGR1_CG8_SHIFT                      16
5030 #define CCM_CCGR1_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG8_SHIFT))&CCM_CCGR1_CG8_MASK)
5031 #define CCM_CCGR1_CG9_MASK                       0xC0000u
5032 #define CCM_CCGR1_CG9_SHIFT                      18
5033 #define CCM_CCGR1_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG9_SHIFT))&CCM_CCGR1_CG9_MASK)
5034 #define CCM_CCGR1_CG10_MASK                      0x300000u
5035 #define CCM_CCGR1_CG10_SHIFT                     20
5036 #define CCM_CCGR1_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG10_SHIFT))&CCM_CCGR1_CG10_MASK)
5037 #define CCM_CCGR1_CG11_MASK                      0xC00000u
5038 #define CCM_CCGR1_CG11_SHIFT                     22
5039 #define CCM_CCGR1_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG11_SHIFT))&CCM_CCGR1_CG11_MASK)
5040 #define CCM_CCGR1_CG12_MASK                      0x3000000u
5041 #define CCM_CCGR1_CG12_SHIFT                     24
5042 #define CCM_CCGR1_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG12_SHIFT))&CCM_CCGR1_CG12_MASK)
5043 #define CCM_CCGR1_CG13_MASK                      0xC000000u
5044 #define CCM_CCGR1_CG13_SHIFT                     26
5045 #define CCM_CCGR1_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG13_SHIFT))&CCM_CCGR1_CG13_MASK)
5046 #define CCM_CCGR1_CG14_MASK                      0x30000000u
5047 #define CCM_CCGR1_CG14_SHIFT                     28
5048 #define CCM_CCGR1_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG14_SHIFT))&CCM_CCGR1_CG14_MASK)
5049 #define CCM_CCGR1_CG15_MASK                      0xC0000000u
5050 #define CCM_CCGR1_CG15_SHIFT                     30
5051 #define CCM_CCGR1_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG15_SHIFT))&CCM_CCGR1_CG15_MASK)
5052 /* CCGR2 Bit Fields */
5053 #define CCM_CCGR2_CG0_MASK                       0x3u
5054 #define CCM_CCGR2_CG0_SHIFT                      0
5055 #define CCM_CCGR2_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG0_SHIFT))&CCM_CCGR2_CG0_MASK)
5056 #define CCM_CCGR2_CG1_MASK                       0xCu
5057 #define CCM_CCGR2_CG1_SHIFT                      2
5058 #define CCM_CCGR2_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG1_SHIFT))&CCM_CCGR2_CG1_MASK)
5059 #define CCM_CCGR2_CG2_MASK                       0x30u
5060 #define CCM_CCGR2_CG2_SHIFT                      4
5061 #define CCM_CCGR2_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG2_SHIFT))&CCM_CCGR2_CG2_MASK)
5062 #define CCM_CCGR2_CG3_MASK                       0xC0u
5063 #define CCM_CCGR2_CG3_SHIFT                      6
5064 #define CCM_CCGR2_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG3_SHIFT))&CCM_CCGR2_CG3_MASK)
5065 #define CCM_CCGR2_CG4_MASK                       0x300u
5066 #define CCM_CCGR2_CG4_SHIFT                      8
5067 #define CCM_CCGR2_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG4_SHIFT))&CCM_CCGR2_CG4_MASK)
5068 #define CCM_CCGR2_CG5_MASK                       0xC00u
5069 #define CCM_CCGR2_CG5_SHIFT                      10
5070 #define CCM_CCGR2_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG5_SHIFT))&CCM_CCGR2_CG5_MASK)
5071 #define CCM_CCGR2_CG6_MASK                       0x3000u
5072 #define CCM_CCGR2_CG6_SHIFT                      12
5073 #define CCM_CCGR2_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG6_SHIFT))&CCM_CCGR2_CG6_MASK)
5074 #define CCM_CCGR2_CG7_MASK                       0xC000u
5075 #define CCM_CCGR2_CG7_SHIFT                      14
5076 #define CCM_CCGR2_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG7_SHIFT))&CCM_CCGR2_CG7_MASK)
5077 #define CCM_CCGR2_CG8_MASK                       0x30000u
5078 #define CCM_CCGR2_CG8_SHIFT                      16
5079 #define CCM_CCGR2_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG8_SHIFT))&CCM_CCGR2_CG8_MASK)
5080 #define CCM_CCGR2_CG9_MASK                       0xC0000u
5081 #define CCM_CCGR2_CG9_SHIFT                      18
5082 #define CCM_CCGR2_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG9_SHIFT))&CCM_CCGR2_CG9_MASK)
5083 #define CCM_CCGR2_CG10_MASK                      0x300000u
5084 #define CCM_CCGR2_CG10_SHIFT                     20
5085 #define CCM_CCGR2_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG10_SHIFT))&CCM_CCGR2_CG10_MASK)
5086 #define CCM_CCGR2_CG11_MASK                      0xC00000u
5087 #define CCM_CCGR2_CG11_SHIFT                     22
5088 #define CCM_CCGR2_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG11_SHIFT))&CCM_CCGR2_CG11_MASK)
5089 #define CCM_CCGR2_CG12_MASK                      0x3000000u
5090 #define CCM_CCGR2_CG12_SHIFT                     24
5091 #define CCM_CCGR2_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG12_SHIFT))&CCM_CCGR2_CG12_MASK)
5092 #define CCM_CCGR2_CG13_MASK                      0xC000000u
5093 #define CCM_CCGR2_CG13_SHIFT                     26
5094 #define CCM_CCGR2_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG13_SHIFT))&CCM_CCGR2_CG13_MASK)
5095 #define CCM_CCGR2_CG14_MASK                      0x30000000u
5096 #define CCM_CCGR2_CG14_SHIFT                     28
5097 #define CCM_CCGR2_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG14_SHIFT))&CCM_CCGR2_CG14_MASK)
5098 #define CCM_CCGR2_CG15_MASK                      0xC0000000u
5099 #define CCM_CCGR2_CG15_SHIFT                     30
5100 #define CCM_CCGR2_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG15_SHIFT))&CCM_CCGR2_CG15_MASK)
5101 /* CCGR3 Bit Fields */
5102 #define CCM_CCGR3_CG0_MASK                       0x3u
5103 #define CCM_CCGR3_CG0_SHIFT                      0
5104 #define CCM_CCGR3_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG0_SHIFT))&CCM_CCGR3_CG0_MASK)
5105 #define CCM_CCGR3_CG1_MASK                       0xCu
5106 #define CCM_CCGR3_CG1_SHIFT                      2
5107 #define CCM_CCGR3_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG1_SHIFT))&CCM_CCGR3_CG1_MASK)
5108 #define CCM_CCGR3_CG2_MASK                       0x30u
5109 #define CCM_CCGR3_CG2_SHIFT                      4
5110 #define CCM_CCGR3_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG2_SHIFT))&CCM_CCGR3_CG2_MASK)
5111 #define CCM_CCGR3_CG3_MASK                       0xC0u
5112 #define CCM_CCGR3_CG3_SHIFT                      6
5113 #define CCM_CCGR3_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG3_SHIFT))&CCM_CCGR3_CG3_MASK)
5114 #define CCM_CCGR3_CG4_MASK                       0x300u
5115 #define CCM_CCGR3_CG4_SHIFT                      8
5116 #define CCM_CCGR3_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG4_SHIFT))&CCM_CCGR3_CG4_MASK)
5117 #define CCM_CCGR3_CG5_MASK                       0xC00u
5118 #define CCM_CCGR3_CG5_SHIFT                      10
5119 #define CCM_CCGR3_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG5_SHIFT))&CCM_CCGR3_CG5_MASK)
5120 #define CCM_CCGR3_CG6_MASK                       0x3000u
5121 #define CCM_CCGR3_CG6_SHIFT                      12
5122 #define CCM_CCGR3_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG6_SHIFT))&CCM_CCGR3_CG6_MASK)
5123 #define CCM_CCGR3_CG7_MASK                       0xC000u
5124 #define CCM_CCGR3_CG7_SHIFT                      14
5125 #define CCM_CCGR3_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG7_SHIFT))&CCM_CCGR3_CG7_MASK)
5126 #define CCM_CCGR3_CG8_MASK                       0x30000u
5127 #define CCM_CCGR3_CG8_SHIFT                      16
5128 #define CCM_CCGR3_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG8_SHIFT))&CCM_CCGR3_CG8_MASK)
5129 #define CCM_CCGR3_CG9_MASK                       0xC0000u
5130 #define CCM_CCGR3_CG9_SHIFT                      18
5131 #define CCM_CCGR3_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG9_SHIFT))&CCM_CCGR3_CG9_MASK)
5132 #define CCM_CCGR3_CG10_MASK                      0x300000u
5133 #define CCM_CCGR3_CG10_SHIFT                     20
5134 #define CCM_CCGR3_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG10_SHIFT))&CCM_CCGR3_CG10_MASK)
5135 #define CCM_CCGR3_CG11_MASK                      0xC00000u
5136 #define CCM_CCGR3_CG11_SHIFT                     22
5137 #define CCM_CCGR3_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG11_SHIFT))&CCM_CCGR3_CG11_MASK)
5138 #define CCM_CCGR3_CG12_MASK                      0x3000000u
5139 #define CCM_CCGR3_CG12_SHIFT                     24
5140 #define CCM_CCGR3_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG12_SHIFT))&CCM_CCGR3_CG12_MASK)
5141 #define CCM_CCGR3_CG13_MASK                      0xC000000u
5142 #define CCM_CCGR3_CG13_SHIFT                     26
5143 #define CCM_CCGR3_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG13_SHIFT))&CCM_CCGR3_CG13_MASK)
5144 #define CCM_CCGR3_CG14_MASK                      0x30000000u
5145 #define CCM_CCGR3_CG14_SHIFT                     28
5146 #define CCM_CCGR3_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG14_SHIFT))&CCM_CCGR3_CG14_MASK)
5147 #define CCM_CCGR3_CG15_MASK                      0xC0000000u
5148 #define CCM_CCGR3_CG15_SHIFT                     30
5149 #define CCM_CCGR3_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG15_SHIFT))&CCM_CCGR3_CG15_MASK)
5150 /* CCGR4 Bit Fields */
5151 #define CCM_CCGR4_CG0_MASK                       0x3u
5152 #define CCM_CCGR4_CG0_SHIFT                      0
5153 #define CCM_CCGR4_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG0_SHIFT))&CCM_CCGR4_CG0_MASK)
5154 #define CCM_CCGR4_CG1_MASK                       0xCu
5155 #define CCM_CCGR4_CG1_SHIFT                      2
5156 #define CCM_CCGR4_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG1_SHIFT))&CCM_CCGR4_CG1_MASK)
5157 #define CCM_CCGR4_CG2_MASK                       0x30u
5158 #define CCM_CCGR4_CG2_SHIFT                      4
5159 #define CCM_CCGR4_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG2_SHIFT))&CCM_CCGR4_CG2_MASK)
5160 #define CCM_CCGR4_CG3_MASK                       0xC0u
5161 #define CCM_CCGR4_CG3_SHIFT                      6
5162 #define CCM_CCGR4_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG3_SHIFT))&CCM_CCGR4_CG3_MASK)
5163 #define CCM_CCGR4_CG4_MASK                       0x300u
5164 #define CCM_CCGR4_CG4_SHIFT                      8
5165 #define CCM_CCGR4_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG4_SHIFT))&CCM_CCGR4_CG4_MASK)
5166 #define CCM_CCGR4_CG5_MASK                       0xC00u
5167 #define CCM_CCGR4_CG5_SHIFT                      10
5168 #define CCM_CCGR4_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG5_SHIFT))&CCM_CCGR4_CG5_MASK)
5169 #define CCM_CCGR4_CG6_MASK                       0x3000u
5170 #define CCM_CCGR4_CG6_SHIFT                      12
5171 #define CCM_CCGR4_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG6_SHIFT))&CCM_CCGR4_CG6_MASK)
5172 #define CCM_CCGR4_CG7_MASK                       0xC000u
5173 #define CCM_CCGR4_CG7_SHIFT                      14
5174 #define CCM_CCGR4_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG7_SHIFT))&CCM_CCGR4_CG7_MASK)
5175 #define CCM_CCGR4_CG8_MASK                       0x30000u
5176 #define CCM_CCGR4_CG8_SHIFT                      16
5177 #define CCM_CCGR4_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG8_SHIFT))&CCM_CCGR4_CG8_MASK)
5178 #define CCM_CCGR4_CG9_MASK                       0xC0000u
5179 #define CCM_CCGR4_CG9_SHIFT                      18
5180 #define CCM_CCGR4_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG9_SHIFT))&CCM_CCGR4_CG9_MASK)
5181 #define CCM_CCGR4_CG10_MASK                      0x300000u
5182 #define CCM_CCGR4_CG10_SHIFT                     20
5183 #define CCM_CCGR4_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG10_SHIFT))&CCM_CCGR4_CG10_MASK)
5184 #define CCM_CCGR4_CG11_MASK                      0xC00000u
5185 #define CCM_CCGR4_CG11_SHIFT                     22
5186 #define CCM_CCGR4_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG11_SHIFT))&CCM_CCGR4_CG11_MASK)
5187 #define CCM_CCGR4_CG12_MASK                      0x3000000u
5188 #define CCM_CCGR4_CG12_SHIFT                     24
5189 #define CCM_CCGR4_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG12_SHIFT))&CCM_CCGR4_CG12_MASK)
5190 #define CCM_CCGR4_CG13_MASK                      0xC000000u
5191 #define CCM_CCGR4_CG13_SHIFT                     26
5192 #define CCM_CCGR4_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG13_SHIFT))&CCM_CCGR4_CG13_MASK)
5193 #define CCM_CCGR4_CG14_MASK                      0x30000000u
5194 #define CCM_CCGR4_CG14_SHIFT                     28
5195 #define CCM_CCGR4_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG14_SHIFT))&CCM_CCGR4_CG14_MASK)
5196 #define CCM_CCGR4_CG15_MASK                      0xC0000000u
5197 #define CCM_CCGR4_CG15_SHIFT                     30
5198 #define CCM_CCGR4_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG15_SHIFT))&CCM_CCGR4_CG15_MASK)
5199 /* CCGR5 Bit Fields */
5200 #define CCM_CCGR5_CG0_MASK                       0x3u
5201 #define CCM_CCGR5_CG0_SHIFT                      0
5202 #define CCM_CCGR5_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG0_SHIFT))&CCM_CCGR5_CG0_MASK)
5203 #define CCM_CCGR5_CG1_MASK                       0xCu
5204 #define CCM_CCGR5_CG1_SHIFT                      2
5205 #define CCM_CCGR5_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG1_SHIFT))&CCM_CCGR5_CG1_MASK)
5206 #define CCM_CCGR5_CG2_MASK                       0x30u
5207 #define CCM_CCGR5_CG2_SHIFT                      4
5208 #define CCM_CCGR5_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG2_SHIFT))&CCM_CCGR5_CG2_MASK)
5209 #define CCM_CCGR5_CG3_MASK                       0xC0u
5210 #define CCM_CCGR5_CG3_SHIFT                      6
5211 #define CCM_CCGR5_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG3_SHIFT))&CCM_CCGR5_CG3_MASK)
5212 #define CCM_CCGR5_CG4_MASK                       0x300u
5213 #define CCM_CCGR5_CG4_SHIFT                      8
5214 #define CCM_CCGR5_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG4_SHIFT))&CCM_CCGR5_CG4_MASK)
5215 #define CCM_CCGR5_CG5_MASK                       0xC00u
5216 #define CCM_CCGR5_CG5_SHIFT                      10
5217 #define CCM_CCGR5_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG5_SHIFT))&CCM_CCGR5_CG5_MASK)
5218 #define CCM_CCGR5_CG6_MASK                       0x3000u
5219 #define CCM_CCGR5_CG6_SHIFT                      12
5220 #define CCM_CCGR5_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG6_SHIFT))&CCM_CCGR5_CG6_MASK)
5221 #define CCM_CCGR5_CG7_MASK                       0xC000u
5222 #define CCM_CCGR5_CG7_SHIFT                      14
5223 #define CCM_CCGR5_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG7_SHIFT))&CCM_CCGR5_CG7_MASK)
5224 #define CCM_CCGR5_CG8_MASK                       0x30000u
5225 #define CCM_CCGR5_CG8_SHIFT                      16
5226 #define CCM_CCGR5_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG8_SHIFT))&CCM_CCGR5_CG8_MASK)
5227 #define CCM_CCGR5_CG9_MASK                       0xC0000u
5228 #define CCM_CCGR5_CG9_SHIFT                      18
5229 #define CCM_CCGR5_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG9_SHIFT))&CCM_CCGR5_CG9_MASK)
5230 #define CCM_CCGR5_CG10_MASK                      0x300000u
5231 #define CCM_CCGR5_CG10_SHIFT                     20
5232 #define CCM_CCGR5_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG10_SHIFT))&CCM_CCGR5_CG10_MASK)
5233 #define CCM_CCGR5_CG11_MASK                      0xC00000u
5234 #define CCM_CCGR5_CG11_SHIFT                     22
5235 #define CCM_CCGR5_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG11_SHIFT))&CCM_CCGR5_CG11_MASK)
5236 #define CCM_CCGR5_CG12_MASK                      0x3000000u
5237 #define CCM_CCGR5_CG12_SHIFT                     24
5238 #define CCM_CCGR5_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG12_SHIFT))&CCM_CCGR5_CG12_MASK)
5239 #define CCM_CCGR5_CG13_MASK                      0xC000000u
5240 #define CCM_CCGR5_CG13_SHIFT                     26
5241 #define CCM_CCGR5_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG13_SHIFT))&CCM_CCGR5_CG13_MASK)
5242 #define CCM_CCGR5_CG14_MASK                      0x30000000u
5243 #define CCM_CCGR5_CG14_SHIFT                     28
5244 #define CCM_CCGR5_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG14_SHIFT))&CCM_CCGR5_CG14_MASK)
5245 #define CCM_CCGR5_CG15_MASK                      0xC0000000u
5246 #define CCM_CCGR5_CG15_SHIFT                     30
5247 #define CCM_CCGR5_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG15_SHIFT))&CCM_CCGR5_CG15_MASK)
5248 /* CCGR6 Bit Fields */
5249 #define CCM_CCGR6_CG0_MASK                       0x3u
5250 #define CCM_CCGR6_CG0_SHIFT                      0
5251 #define CCM_CCGR6_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG0_SHIFT))&CCM_CCGR6_CG0_MASK)
5252 #define CCM_CCGR6_CG1_MASK                       0xCu
5253 #define CCM_CCGR6_CG1_SHIFT                      2
5254 #define CCM_CCGR6_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG1_SHIFT))&CCM_CCGR6_CG1_MASK)
5255 #define CCM_CCGR6_CG2_MASK                       0x30u
5256 #define CCM_CCGR6_CG2_SHIFT                      4
5257 #define CCM_CCGR6_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG2_SHIFT))&CCM_CCGR6_CG2_MASK)
5258 #define CCM_CCGR6_CG3_MASK                       0xC0u
5259 #define CCM_CCGR6_CG3_SHIFT                      6
5260 #define CCM_CCGR6_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG3_SHIFT))&CCM_CCGR6_CG3_MASK)
5261 #define CCM_CCGR6_CG4_MASK                       0x300u
5262 #define CCM_CCGR6_CG4_SHIFT                      8
5263 #define CCM_CCGR6_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG4_SHIFT))&CCM_CCGR6_CG4_MASK)
5264 #define CCM_CCGR6_CG5_MASK                       0xC00u
5265 #define CCM_CCGR6_CG5_SHIFT                      10
5266 #define CCM_CCGR6_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG5_SHIFT))&CCM_CCGR6_CG5_MASK)
5267 #define CCM_CCGR6_CG6_MASK                       0x3000u
5268 #define CCM_CCGR6_CG6_SHIFT                      12
5269 #define CCM_CCGR6_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG6_SHIFT))&CCM_CCGR6_CG6_MASK)
5270 #define CCM_CCGR6_CG7_MASK                       0xC000u
5271 #define CCM_CCGR6_CG7_SHIFT                      14
5272 #define CCM_CCGR6_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG7_SHIFT))&CCM_CCGR6_CG7_MASK)
5273 #define CCM_CCGR6_CG8_MASK                       0x30000u
5274 #define CCM_CCGR6_CG8_SHIFT                      16
5275 #define CCM_CCGR6_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG8_SHIFT))&CCM_CCGR6_CG8_MASK)
5276 #define CCM_CCGR6_CG9_MASK                       0xC0000u
5277 #define CCM_CCGR6_CG9_SHIFT                      18
5278 #define CCM_CCGR6_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG9_SHIFT))&CCM_CCGR6_CG9_MASK)
5279 #define CCM_CCGR6_CG10_MASK                      0x300000u
5280 #define CCM_CCGR6_CG10_SHIFT                     20
5281 #define CCM_CCGR6_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG10_SHIFT))&CCM_CCGR6_CG10_MASK)
5282 #define CCM_CCGR6_CG11_MASK                      0xC00000u
5283 #define CCM_CCGR6_CG11_SHIFT                     22
5284 #define CCM_CCGR6_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG11_SHIFT))&CCM_CCGR6_CG11_MASK)
5285 #define CCM_CCGR6_CG12_MASK                      0x3000000u
5286 #define CCM_CCGR6_CG12_SHIFT                     24
5287 #define CCM_CCGR6_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG12_SHIFT))&CCM_CCGR6_CG12_MASK)
5288 #define CCM_CCGR6_CG13_MASK                      0xC000000u
5289 #define CCM_CCGR6_CG13_SHIFT                     26
5290 #define CCM_CCGR6_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG13_SHIFT))&CCM_CCGR6_CG13_MASK)
5291 #define CCM_CCGR6_CG14_MASK                      0x30000000u
5292 #define CCM_CCGR6_CG14_SHIFT                     28
5293 #define CCM_CCGR6_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG14_SHIFT))&CCM_CCGR6_CG14_MASK)
5294 #define CCM_CCGR6_CG15_MASK                      0xC0000000u
5295 #define CCM_CCGR6_CG15_SHIFT                     30
5296 #define CCM_CCGR6_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG15_SHIFT))&CCM_CCGR6_CG15_MASK)
5297 /* CMEOR Bit Fields */
5298 #define CCM_CMEOR_mod_en_ov_gpt_MASK             0x20u
5299 #define CCM_CMEOR_mod_en_ov_gpt_SHIFT            5
5300 #define CCM_CMEOR_mod_en_ov_epit_MASK            0x40u
5301 #define CCM_CMEOR_mod_en_ov_epit_SHIFT           6
5302 #define CCM_CMEOR_mod_en_usdhc_MASK              0x80u
5303 #define CCM_CMEOR_mod_en_usdhc_SHIFT             7
5304 #define CCM_CMEOR_mod_en_ov_gpu_MASK             0x400u
5305 #define CCM_CMEOR_mod_en_ov_gpu_SHIFT            10
5306 #define CCM_CMEOR_mod_en_ov_can2_cpi_MASK        0x10000000u
5307 #define CCM_CMEOR_mod_en_ov_can2_cpi_SHIFT       28
5308 #define CCM_CMEOR_mod_en_ov_can1_cpi_MASK        0x40000000u
5309 #define CCM_CMEOR_mod_en_ov_can1_cpi_SHIFT       30
5310 
5311 /*!
5312  * @}
5313  */ /* end of group CCM_Register_Masks */
5314 
5315 /* CCM - Peripheral instance base addresses */
5316 /** Peripheral CCM base address */
5317 #define CCM_BASE                                 (0x420C4000u)
5318 /** Peripheral CCM base pointer */
5319 #define CCM                                      ((CCM_Type *)CCM_BASE)
5320 #define CCM_BASE_PTR                             (CCM)
5321 /** Array initializer of CCM peripheral base addresses */
5322 #define CCM_BASE_ADDRS                           { CCM_BASE }
5323 /** Array initializer of CCM peripheral base pointers */
5324 #define CCM_BASE_PTRS                            { CCM }
5325 
5326 /* ----------------------------------------------------------------------------
5327    -- CCM - Register accessor macros
5328    ---------------------------------------------------------------------------- */
5329 
5330 /*!
5331  * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros
5332  * @{
5333  */
5334 
5335 /* CCM - Register instance definitions */
5336 /* CCM */
5337 #define CCM_CCR                                  CCM_CCR_REG(CCM_BASE_PTR)
5338 #define CCM_CCDR                                 CCM_CCDR_REG(CCM_BASE_PTR)
5339 #define CCM_CSR                                  CCM_CSR_REG(CCM_BASE_PTR)
5340 #define CCM_CCSR                                 CCM_CCSR_REG(CCM_BASE_PTR)
5341 #define CCM_CACRR                                CCM_CACRR_REG(CCM_BASE_PTR)
5342 #define CCM_CBCDR                                CCM_CBCDR_REG(CCM_BASE_PTR)
5343 #define CCM_CBCMR                                CCM_CBCMR_REG(CCM_BASE_PTR)
5344 #define CCM_CSCMR1                               CCM_CSCMR1_REG(CCM_BASE_PTR)
5345 #define CCM_CSCMR2                               CCM_CSCMR2_REG(CCM_BASE_PTR)
5346 #define CCM_CSCDR1                               CCM_CSCDR1_REG(CCM_BASE_PTR)
5347 #define CCM_CS1CDR                               CCM_CS1CDR_REG(CCM_BASE_PTR)
5348 #define CCM_CS2CDR                               CCM_CS2CDR_REG(CCM_BASE_PTR)
5349 #define CCM_CDCDR                                CCM_CDCDR_REG(CCM_BASE_PTR)
5350 #define CCM_CHSCCDR                              CCM_CHSCCDR_REG(CCM_BASE_PTR)
5351 #define CCM_CSCDR2                               CCM_CSCDR2_REG(CCM_BASE_PTR)
5352 #define CCM_CSCDR3                               CCM_CSCDR3_REG(CCM_BASE_PTR)
5353 #define CCM_CWDR                                 CCM_CWDR_REG(CCM_BASE_PTR)
5354 #define CCM_CDHIPR                               CCM_CDHIPR_REG(CCM_BASE_PTR)
5355 #define CCM_CLPCR                                CCM_CLPCR_REG(CCM_BASE_PTR)
5356 #define CCM_CISR                                 CCM_CISR_REG(CCM_BASE_PTR)
5357 #define CCM_CIMR                                 CCM_CIMR_REG(CCM_BASE_PTR)
5358 #define CCM_CCOSR                                CCM_CCOSR_REG(CCM_BASE_PTR)
5359 #define CCM_CGPR                                 CCM_CGPR_REG(CCM_BASE_PTR)
5360 #define CCM_CCGR0                                CCM_CCGR0_REG(CCM_BASE_PTR)
5361 #define CCM_CCGR1                                CCM_CCGR1_REG(CCM_BASE_PTR)
5362 #define CCM_CCGR2                                CCM_CCGR2_REG(CCM_BASE_PTR)
5363 #define CCM_CCGR3                                CCM_CCGR3_REG(CCM_BASE_PTR)
5364 #define CCM_CCGR4                                CCM_CCGR4_REG(CCM_BASE_PTR)
5365 #define CCM_CCGR5                                CCM_CCGR5_REG(CCM_BASE_PTR)
5366 #define CCM_CCGR6                                CCM_CCGR6_REG(CCM_BASE_PTR)
5367 #define CCM_CMEOR                                CCM_CMEOR_REG(CCM_BASE_PTR)
5368 
5369 /*!
5370  * @}
5371  */ /* end of group CCM_Register_Accessor_Macros */
5372 
5373 /*!
5374  * @}
5375  */ /* end of group CCM_Peripheral */
5376 
5377 /* ----------------------------------------------------------------------------
5378    -- CCM_ANALOG Peripheral Access Layer
5379    ---------------------------------------------------------------------------- */
5380 
5381 /*!
5382  * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
5383  * @{
5384  */
5385 
5386 /** CCM_ANALOG - Register Layout Typedef */
5387 typedef struct {
5388   __IO  uint32_t PLL_ARM;                                /**< Analog ARM PLL control Register, offset: 0x0 */
5389   __IO  uint32_t PLL_ARM_SET;                            /**< Analog ARM PLL control Register, offset: 0x4 */
5390   __IO  uint32_t PLL_ARM_CLR;                            /**< Analog ARM PLL control Register, offset: 0x8 */
5391   __IO  uint32_t PLL_ARM_TOG;                            /**< Analog ARM PLL control Register, offset: 0xC */
5392   __IO  uint32_t PLL_USB1;                               /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
5393   __IO  uint32_t PLL_USB1_SET;                           /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
5394   __IO  uint32_t PLL_USB1_CLR;                           /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
5395   __IO  uint32_t PLL_USB1_TOG;                           /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
5396   __IO  uint32_t PLL_USB2;                               /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
5397   __IO  uint32_t PLL_USB2_SET;                           /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
5398   __IO  uint32_t PLL_USB2_CLR;                           /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
5399   __IO  uint32_t PLL_USB2_TOG;                           /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
5400   __IO  uint32_t PLL_SYS;                                /**< Analog System PLL Control Register, offset: 0x30 */
5401   __IO  uint32_t PLL_SYS_SET;                            /**< Analog System PLL Control Register, offset: 0x34 */
5402   __IO  uint32_t PLL_SYS_CLR;                            /**< Analog System PLL Control Register, offset: 0x38 */
5403   __IO  uint32_t PLL_SYS_TOG;                            /**< Analog System PLL Control Register, offset: 0x3C */
5404   __IO  uint32_t PLL_SYS_SS;                             /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
5405   uint8_t RESERVED_0[44];
5406   __IO  uint32_t PLL_AUDIO;                              /**< Analog Audio PLL control Register, offset: 0x70 */
5407   __IO  uint32_t PLL_AUDIO_SET;                          /**< Analog Audio PLL control Register, offset: 0x74 */
5408   __IO  uint32_t PLL_AUDIO_CLR;                          /**< Analog Audio PLL control Register, offset: 0x78 */
5409   __IO  uint32_t PLL_AUDIO_TOG;                          /**< Analog Audio PLL control Register, offset: 0x7C */
5410   __IO  uint32_t PLL_AUDIO_NUM;                          /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
5411   uint8_t RESERVED_1[12];
5412   __IO  uint32_t PLL_AUDIO_DENOM;                        /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
5413   uint8_t RESERVED_2[12];
5414   __IO  uint32_t PLL_VIDEO;                              /**< Analog Video PLL control Register, offset: 0xA0 */
5415   __IO  uint32_t PLL_VIDEO_SET;                          /**< Analog Video PLL control Register, offset: 0xA4 */
5416   __IO  uint32_t PLL_VIDEO_CLR;                          /**< Analog Video PLL control Register, offset: 0xA8 */
5417   __IO  uint32_t PLL_VIDEO_TOG;                          /**< Analog Video PLL control Register, offset: 0xAC */
5418   __IO  uint32_t PLL_VIDEO_NUM;                          /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
5419   uint8_t RESERVED_3[12];
5420   __IO  uint32_t PLL_VIDEO_DENOM;                        /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
5421   uint8_t RESERVED_4[28];
5422   __IO  uint32_t PLL_ENET;                               /**< Analog ENET PLL Control Register, offset: 0xE0 */
5423   __IO  uint32_t PLL_ENET_SET;                           /**< Analog ENET PLL Control Register, offset: 0xE4 */
5424   __IO  uint32_t PLL_ENET_CLR;                           /**< Analog ENET PLL Control Register, offset: 0xE8 */
5425   __IO  uint32_t PLL_ENET_TOG;                           /**< Analog ENET PLL Control Register, offset: 0xEC */
5426   __IO  uint32_t PFD_480;                                /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
5427   __IO  uint32_t PFD_480_SET;                            /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
5428   __IO  uint32_t PFD_480_CLR;                            /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
5429   __IO  uint32_t PFD_480_TOG;                            /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
5430   __IO  uint32_t PFD_528;                                /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
5431   __IO  uint32_t PFD_528_SET;                            /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
5432   __IO  uint32_t PFD_528_CLR;                            /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
5433   __IO  uint32_t PFD_528_TOG;                            /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
5434   uint8_t RESERVED_5[64];
5435   __IO  uint32_t MISC0;                                  /**< Miscellaneous Register 0, offset: 0x150 */
5436   __IO  uint32_t MISC0_SET;                              /**< Miscellaneous Register 0, offset: 0x154 */
5437   __IO  uint32_t MISC0_CLR;                              /**< Miscellaneous Register 0, offset: 0x158 */
5438   __IO  uint32_t MISC0_TOG;                              /**< Miscellaneous Register 0, offset: 0x15C */
5439   __IO  uint32_t MISC1;                                  /**< Miscellaneous Register 1, offset: 0x160 */
5440   __IO  uint32_t MISC1_SET;                              /**< Miscellaneous Register 1, offset: 0x164 */
5441   __IO  uint32_t MISC1_CLR;                              /**< Miscellaneous Register 1, offset: 0x168 */
5442   __IO  uint32_t MISC1_TOG;                              /**< Miscellaneous Register 1, offset: 0x16C */
5443   __IO  uint32_t MISC2;                                  /**< Miscellaneous Register 2, offset: 0x170 */
5444   __IO  uint32_t MISC2_SET;                              /**< Miscellaneous Register 2, offset: 0x174 */
5445   __IO  uint32_t MISC2_CLR;                              /**< Miscellaneous Register 2, offset: 0x178 */
5446   __IO  uint32_t MISC2_TOG;                              /**< Miscellaneous Register 2, offset: 0x17C */
5447 } CCM_ANALOG_Type, *CCM_ANALOG_MemMapPtr;
5448 
5449 /* ----------------------------------------------------------------------------
5450    -- CCM_ANALOG - Register accessor macros
5451    ---------------------------------------------------------------------------- */
5452 
5453 /*!
5454  * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros
5455  * @{
5456  */
5457 
5458 /* CCM_ANALOG - Register accessors */
5459 #define CCM_ANALOG_PLL_ARM_REG(base)             ((base)->PLL_ARM)
5460 #define CCM_ANALOG_PLL_ARM_SET_REG(base)         ((base)->PLL_ARM_SET)
5461 #define CCM_ANALOG_PLL_ARM_CLR_REG(base)         ((base)->PLL_ARM_CLR)
5462 #define CCM_ANALOG_PLL_ARM_TOG_REG(base)         ((base)->PLL_ARM_TOG)
5463 #define CCM_ANALOG_PLL_USB1_REG(base)            ((base)->PLL_USB1)
5464 #define CCM_ANALOG_PLL_USB1_SET_REG(base)        ((base)->PLL_USB1_SET)
5465 #define CCM_ANALOG_PLL_USB1_CLR_REG(base)        ((base)->PLL_USB1_CLR)
5466 #define CCM_ANALOG_PLL_USB1_TOG_REG(base)        ((base)->PLL_USB1_TOG)
5467 #define CCM_ANALOG_PLL_USB2_REG(base)            ((base)->PLL_USB2)
5468 #define CCM_ANALOG_PLL_USB2_SET_REG(base)        ((base)->PLL_USB2_SET)
5469 #define CCM_ANALOG_PLL_USB2_CLR_REG(base)        ((base)->PLL_USB2_CLR)
5470 #define CCM_ANALOG_PLL_USB2_TOG_REG(base)        ((base)->PLL_USB2_TOG)
5471 #define CCM_ANALOG_PLL_SYS_REG(base)             ((base)->PLL_SYS)
5472 #define CCM_ANALOG_PLL_SYS_SET_REG(base)         ((base)->PLL_SYS_SET)
5473 #define CCM_ANALOG_PLL_SYS_CLR_REG(base)         ((base)->PLL_SYS_CLR)
5474 #define CCM_ANALOG_PLL_SYS_TOG_REG(base)         ((base)->PLL_SYS_TOG)
5475 #define CCM_ANALOG_PLL_SYS_SS_REG(base)          ((base)->PLL_SYS_SS)
5476 #define CCM_ANALOG_PLL_AUDIO_REG(base)           ((base)->PLL_AUDIO)
5477 #define CCM_ANALOG_PLL_AUDIO_SET_REG(base)       ((base)->PLL_AUDIO_SET)
5478 #define CCM_ANALOG_PLL_AUDIO_CLR_REG(base)       ((base)->PLL_AUDIO_CLR)
5479 #define CCM_ANALOG_PLL_AUDIO_TOG_REG(base)       ((base)->PLL_AUDIO_TOG)
5480 #define CCM_ANALOG_PLL_AUDIO_NUM_REG(base)       ((base)->PLL_AUDIO_NUM)
5481 #define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base)     ((base)->PLL_AUDIO_DENOM)
5482 #define CCM_ANALOG_PLL_VIDEO_REG(base)           ((base)->PLL_VIDEO)
5483 #define CCM_ANALOG_PLL_VIDEO_SET_REG(base)       ((base)->PLL_VIDEO_SET)
5484 #define CCM_ANALOG_PLL_VIDEO_CLR_REG(base)       ((base)->PLL_VIDEO_CLR)
5485 #define CCM_ANALOG_PLL_VIDEO_TOG_REG(base)       ((base)->PLL_VIDEO_TOG)
5486 #define CCM_ANALOG_PLL_VIDEO_NUM_REG(base)       ((base)->PLL_VIDEO_NUM)
5487 #define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base)     ((base)->PLL_VIDEO_DENOM)
5488 #define CCM_ANALOG_PLL_ENET_REG(base)            ((base)->PLL_ENET)
5489 #define CCM_ANALOG_PLL_ENET_SET_REG(base)        ((base)->PLL_ENET_SET)
5490 #define CCM_ANALOG_PLL_ENET_CLR_REG(base)        ((base)->PLL_ENET_CLR)
5491 #define CCM_ANALOG_PLL_ENET_TOG_REG(base)        ((base)->PLL_ENET_TOG)
5492 #define CCM_ANALOG_PFD_480_REG(base)             ((base)->PFD_480)
5493 #define CCM_ANALOG_PFD_480_SET_REG(base)         ((base)->PFD_480_SET)
5494 #define CCM_ANALOG_PFD_480_CLR_REG(base)         ((base)->PFD_480_CLR)
5495 #define CCM_ANALOG_PFD_480_TOG_REG(base)         ((base)->PFD_480_TOG)
5496 #define CCM_ANALOG_PFD_528_REG(base)             ((base)->PFD_528)
5497 #define CCM_ANALOG_PFD_528_SET_REG(base)         ((base)->PFD_528_SET)
5498 #define CCM_ANALOG_PFD_528_CLR_REG(base)         ((base)->PFD_528_CLR)
5499 #define CCM_ANALOG_PFD_528_TOG_REG(base)         ((base)->PFD_528_TOG)
5500 #define CCM_ANALOG_MISC0_REG(base)               ((base)->MISC0)
5501 #define CCM_ANALOG_MISC0_SET_REG(base)           ((base)->MISC0_SET)
5502 #define CCM_ANALOG_MISC0_CLR_REG(base)           ((base)->MISC0_CLR)
5503 #define CCM_ANALOG_MISC0_TOG_REG(base)           ((base)->MISC0_TOG)
5504 #define CCM_ANALOG_MISC1_REG(base)               ((base)->MISC1)
5505 #define CCM_ANALOG_MISC1_SET_REG(base)           ((base)->MISC1_SET)
5506 #define CCM_ANALOG_MISC1_CLR_REG(base)           ((base)->MISC1_CLR)
5507 #define CCM_ANALOG_MISC1_TOG_REG(base)           ((base)->MISC1_TOG)
5508 #define CCM_ANALOG_MISC2_REG(base)               ((base)->MISC2)
5509 #define CCM_ANALOG_MISC2_SET_REG(base)           ((base)->MISC2_SET)
5510 #define CCM_ANALOG_MISC2_CLR_REG(base)           ((base)->MISC2_CLR)
5511 #define CCM_ANALOG_MISC2_TOG_REG(base)           ((base)->MISC2_TOG)
5512 
5513 /*!
5514  * @}
5515  */ /* end of group CCM_ANALOG_Register_Accessor_Macros */
5516 
5517 /* ----------------------------------------------------------------------------
5518    -- CCM_ANALOG Register Masks
5519    ---------------------------------------------------------------------------- */
5520 
5521 /*!
5522  * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
5523  * @{
5524  */
5525 
5526 /* PLL_ARM Bit Fields */
5527 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK       0x7Fu
5528 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT      0
5529 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
5530 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK        0x1000u
5531 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT       12
5532 #define CCM_ANALOG_PLL_ARM_ENABLE_MASK           0x2000u
5533 #define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT          13
5534 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK   0xC000u
5535 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT  14
5536 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
5537 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK           0x10000u
5538 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT          16
5539 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK         0x20000u
5540 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT        17
5541 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK   0x40000u
5542 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT  18
5543 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK          0x80000u
5544 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT         19
5545 #define CCM_ANALOG_PLL_ARM_LOCK_MASK             0x80000000u
5546 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT            31
5547 /* PLL_ARM_SET Bit Fields */
5548 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK   0x7Fu
5549 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT  0
5550 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
5551 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK    0x1000u
5552 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT   12
5553 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK       0x2000u
5554 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT      13
5555 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK 0xC000u
5556 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT 14
5557 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
5558 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK       0x10000u
5559 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT      16
5560 #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_MASK     0x20000u
5561 #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_SHIFT    17
5562 #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_MASK 0x40000u
5563 #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_SHIFT 18
5564 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK      0x80000u
5565 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT     19
5566 #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK         0x80000000u
5567 #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT        31
5568 /* PLL_ARM_CLR Bit Fields */
5569 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK   0x7Fu
5570 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT  0
5571 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
5572 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK    0x1000u
5573 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT   12
5574 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK       0x2000u
5575 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT      13
5576 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5577 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT 14
5578 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
5579 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK       0x10000u
5580 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT      16
5581 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_MASK     0x20000u
5582 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_SHIFT    17
5583 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_MASK 0x40000u
5584 #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_SHIFT 18
5585 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK      0x80000u
5586 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT     19
5587 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK         0x80000000u
5588 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT        31
5589 /* PLL_ARM_TOG Bit Fields */
5590 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK   0x7Fu
5591 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT  0
5592 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
5593 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK    0x1000u
5594 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT   12
5595 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK       0x2000u
5596 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT      13
5597 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5598 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT 14
5599 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
5600 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK       0x10000u
5601 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT      16
5602 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_MASK     0x20000u
5603 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_SHIFT    17
5604 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_MASK 0x40000u
5605 #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_SHIFT 18
5606 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK      0x80000u
5607 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT     19
5608 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK         0x80000000u
5609 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT        31
5610 /* PLL_USB1 Bit Fields */
5611 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK      0x3u
5612 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT     0
5613 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
5614 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK     0x40u
5615 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT    6
5616 #define CCM_ANALOG_PLL_USB1_POWER_MASK           0x1000u
5617 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT          12
5618 #define CCM_ANALOG_PLL_USB1_ENABLE_MASK          0x2000u
5619 #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT         13
5620 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK  0xC000u
5621 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT 14
5622 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
5623 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK          0x10000u
5624 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT         16
5625 #define CCM_ANALOG_PLL_USB1_LOCK_MASK            0x80000000u
5626 #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT           31
5627 /* PLL_USB1_SET Bit Fields */
5628 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK  0x3u
5629 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT 0
5630 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
5631 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK 0x40u
5632 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT 6
5633 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK       0x1000u
5634 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT      12
5635 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK      0x2000u
5636 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT     13
5637 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK 0xC000u
5638 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT 14
5639 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
5640 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK      0x10000u
5641 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT     16
5642 #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK        0x80000000u
5643 #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT       31
5644 /* PLL_USB1_CLR Bit Fields */
5645 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK  0x3u
5646 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT 0
5647 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
5648 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK 0x40u
5649 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT 6
5650 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK       0x1000u
5651 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT      12
5652 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK      0x2000u
5653 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT     13
5654 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5655 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT 14
5656 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
5657 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK      0x10000u
5658 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT     16
5659 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK        0x80000000u
5660 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT       31
5661 /* PLL_USB1_TOG Bit Fields */
5662 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK  0x3u
5663 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT 0
5664 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
5665 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK 0x40u
5666 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT 6
5667 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK       0x1000u
5668 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT      12
5669 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK      0x2000u
5670 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT     13
5671 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5672 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT 14
5673 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
5674 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK      0x10000u
5675 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT     16
5676 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK        0x80000000u
5677 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT       31
5678 /* PLL_USB2 Bit Fields */
5679 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK      0x3u
5680 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT     0
5681 #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
5682 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK     0x40u
5683 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT    6
5684 #define CCM_ANALOG_PLL_USB2_POWER_MASK           0x1000u
5685 #define CCM_ANALOG_PLL_USB2_POWER_SHIFT          12
5686 #define CCM_ANALOG_PLL_USB2_ENABLE_MASK          0x2000u
5687 #define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT         13
5688 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK  0xC000u
5689 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT 14
5690 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
5691 #define CCM_ANALOG_PLL_USB2_BYPASS_MASK          0x10000u
5692 #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT         16
5693 #define CCM_ANALOG_PLL_USB2_LOCK_MASK            0x80000000u
5694 #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT           31
5695 /* PLL_USB2_SET Bit Fields */
5696 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK  0x3u
5697 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT 0
5698 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
5699 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK 0x40u
5700 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT 6
5701 #define CCM_ANALOG_PLL_USB2_SET_POWER_MASK       0x1000u
5702 #define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT      12
5703 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK      0x2000u
5704 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT     13
5705 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK 0xC000u
5706 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT 14
5707 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
5708 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK      0x10000u
5709 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT     16
5710 #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK        0x80000000u
5711 #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT       31
5712 /* PLL_USB2_CLR Bit Fields */
5713 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK  0x3u
5714 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT 0
5715 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
5716 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK 0x40u
5717 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT 6
5718 #define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK       0x1000u
5719 #define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT      12
5720 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK      0x2000u
5721 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT     13
5722 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5723 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT 14
5724 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
5725 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK      0x10000u
5726 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT     16
5727 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK        0x80000000u
5728 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT       31
5729 /* PLL_USB2_TOG Bit Fields */
5730 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK  0x3u
5731 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT 0
5732 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
5733 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK 0x40u
5734 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT 6
5735 #define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK       0x1000u
5736 #define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT      12
5737 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK      0x2000u
5738 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT     13
5739 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5740 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT 14
5741 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
5742 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK      0x10000u
5743 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT     16
5744 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK        0x80000000u
5745 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT       31
5746 /* PLL_SYS Bit Fields */
5747 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK       0x1u
5748 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT      0
5749 #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK        0x1000u
5750 #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT       12
5751 #define CCM_ANALOG_PLL_SYS_ENABLE_MASK           0x2000u
5752 #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT          13
5753 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK   0xC000u
5754 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT  14
5755 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
5756 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK           0x10000u
5757 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT          16
5758 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK    0x40000u
5759 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT   18
5760 #define CCM_ANALOG_PLL_SYS_LOCK_MASK             0x80000000u
5761 #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT            31
5762 /* PLL_SYS_SET Bit Fields */
5763 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK   0x1u
5764 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT  0
5765 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK    0x1000u
5766 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT   12
5767 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK       0x2000u
5768 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT      13
5769 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK 0xC000u
5770 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT 14
5771 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
5772 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK       0x10000u
5773 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT      16
5774 #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK 0x40000u
5775 #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT 18
5776 #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK         0x80000000u
5777 #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT        31
5778 /* PLL_SYS_CLR Bit Fields */
5779 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK   0x1u
5780 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT  0
5781 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK    0x1000u
5782 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT   12
5783 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK       0x2000u
5784 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT      13
5785 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5786 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT 14
5787 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
5788 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK       0x10000u
5789 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT      16
5790 #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK 0x40000u
5791 #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT 18
5792 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK         0x80000000u
5793 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT        31
5794 /* PLL_SYS_TOG Bit Fields */
5795 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK   0x1u
5796 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT  0
5797 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK    0x1000u
5798 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT   12
5799 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK       0x2000u
5800 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT      13
5801 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5802 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT 14
5803 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
5804 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK       0x10000u
5805 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT      16
5806 #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK 0x40000u
5807 #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT 18
5808 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK         0x80000000u
5809 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT        31
5810 /* PLL_SYS_SS Bit Fields */
5811 #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK          0x7FFFu
5812 #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT         0
5813 #define CCM_ANALOG_PLL_SYS_SS_STEP(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT))&CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
5814 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK        0x8000u
5815 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT       15
5816 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK          0xFFFF0000u
5817 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT         16
5818 #define CCM_ANALOG_PLL_SYS_SS_STOP(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT))&CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
5819 /* PLL_AUDIO Bit Fields */
5820 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK     0x7Fu
5821 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT    0
5822 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
5823 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK      0x1000u
5824 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT     12
5825 #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK         0x2000u
5826 #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT        13
5827 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
5828 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
5829 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
5830 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         0x10000u
5831 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT        16
5832 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK  0x40000u
5833 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
5834 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK 0x180000u
5835 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT 19
5836 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
5837 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           0x80000000u
5838 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT          31
5839 /* PLL_AUDIO_SET Bit Fields */
5840 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
5841 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
5842 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
5843 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK  0x1000u
5844 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
5845 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK     0x2000u
5846 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT    13
5847 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
5848 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
5849 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
5850 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     0x10000u
5851 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT    16
5852 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
5853 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
5854 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK 0x180000u
5855 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT 19
5856 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
5857 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       0x80000000u
5858 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT      31
5859 /* PLL_AUDIO_CLR Bit Fields */
5860 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
5861 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
5862 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
5863 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK  0x1000u
5864 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
5865 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK     0x2000u
5866 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT    13
5867 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5868 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
5869 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
5870 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     0x10000u
5871 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT    16
5872 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
5873 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
5874 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK 0x180000u
5875 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT 19
5876 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
5877 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       0x80000000u
5878 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT      31
5879 /* PLL_AUDIO_TOG Bit Fields */
5880 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
5881 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
5882 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
5883 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK  0x1000u
5884 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
5885 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK     0x2000u
5886 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT    13
5887 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5888 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
5889 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
5890 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     0x10000u
5891 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT    16
5892 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
5893 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
5894 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK 0x180000u
5895 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT 19
5896 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
5897 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       0x80000000u
5898 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT      31
5899 /* PLL_AUDIO_NUM Bit Fields */
5900 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK          0x3FFFFFFFu
5901 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT         0
5902 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
5903 /* PLL_AUDIO_DENOM Bit Fields */
5904 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK        0x3FFFFFFFu
5905 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT       0
5906 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
5907 /* PLL_VIDEO Bit Fields */
5908 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK     0x7Fu
5909 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT    0
5910 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
5911 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK      0x1000u
5912 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT     12
5913 #define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK         0x2000u
5914 #define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT        13
5915 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
5916 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
5917 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
5918 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         0x10000u
5919 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT        16
5920 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK  0x40000u
5921 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
5922 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK 0x180000u
5923 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT 19
5924 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
5925 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           0x80000000u
5926 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT          31
5927 /* PLL_VIDEO_SET Bit Fields */
5928 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
5929 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
5930 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
5931 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK  0x1000u
5932 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
5933 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK     0x2000u
5934 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT    13
5935 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
5936 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
5937 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
5938 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     0x10000u
5939 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT    16
5940 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
5941 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
5942 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK 0x180000u
5943 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT 19
5944 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
5945 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       0x80000000u
5946 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT      31
5947 /* PLL_VIDEO_CLR Bit Fields */
5948 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
5949 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
5950 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
5951 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK  0x1000u
5952 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
5953 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK     0x2000u
5954 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT    13
5955 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
5956 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
5957 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
5958 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     0x10000u
5959 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT    16
5960 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
5961 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
5962 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK 0x180000u
5963 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT 19
5964 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
5965 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       0x80000000u
5966 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT      31
5967 /* PLL_VIDEO_TOG Bit Fields */
5968 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
5969 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
5970 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
5971 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK  0x1000u
5972 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
5973 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK     0x2000u
5974 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT    13
5975 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
5976 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
5977 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
5978 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     0x10000u
5979 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT    16
5980 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
5981 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
5982 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK 0x180000u
5983 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT 19
5984 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
5985 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       0x80000000u
5986 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT      31
5987 /* PLL_VIDEO_NUM Bit Fields */
5988 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK          0x3FFFFFFFu
5989 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT         0
5990 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
5991 /* PLL_VIDEO_DENOM Bit Fields */
5992 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK        0x3FFFFFFFu
5993 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT       0
5994 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
5995 /* PLL_ENET Bit Fields */
5996 #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK 0x3u
5997 #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT 0
5998 #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)
5999 #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK 0xCu
6000 #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT 2
6001 #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)
6002 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK       0x1000u
6003 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT      12
6004 #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK   0x2000u
6005 #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT  13
6006 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK  0xC000u
6007 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14
6008 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
6009 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK          0x10000u
6010 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT         16
6011 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK   0x40000u
6012 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT  18
6013 #define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK     0x80000u
6014 #define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT    19
6015 #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK   0x100000u
6016 #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT  20
6017 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK 0x200000u
6018 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT 21
6019 #define CCM_ANALOG_PLL_ENET_LOCK_MASK            0x80000000u
6020 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT           31
6021 /* PLL_ENET_SET Bit Fields */
6022 #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK 0x3u
6023 #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT 0
6024 #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK)
6025 #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK 0xCu
6026 #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT 2
6027 #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK)
6028 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK   0x1000u
6029 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT  12
6030 #define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK 0x2000u
6031 #define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT 13
6032 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK 0xC000u
6033 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT 14
6034 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
6035 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK      0x10000u
6036 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT     16
6037 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK 0x40000u
6038 #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT 18
6039 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK 0x80000u
6040 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT 19
6041 #define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK 0x100000u
6042 #define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT 20
6043 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK 0x200000u
6044 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT 21
6045 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK        0x80000000u
6046 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT       31
6047 /* PLL_ENET_CLR Bit Fields */
6048 #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK 0x3u
6049 #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT 0
6050 #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK)
6051 #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK 0xCu
6052 #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT 2
6053 #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK)
6054 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK   0x1000u
6055 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT  12
6056 #define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK 0x2000u
6057 #define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT 13
6058 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK 0xC000u
6059 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT 14
6060 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
6061 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK      0x10000u
6062 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT     16
6063 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK 0x40000u
6064 #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT 18
6065 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK 0x80000u
6066 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT 19
6067 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK 0x100000u
6068 #define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT 20
6069 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK 0x200000u
6070 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT 21
6071 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK        0x80000000u
6072 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT       31
6073 /* PLL_ENET_TOG Bit Fields */
6074 #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK 0x3u
6075 #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT 0
6076 #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK)
6077 #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK 0xCu
6078 #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT 2
6079 #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK)
6080 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK   0x1000u
6081 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT  12
6082 #define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK 0x2000u
6083 #define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT 13
6084 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK 0xC000u
6085 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT 14
6086 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
6087 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK      0x10000u
6088 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT     16
6089 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK 0x40000u
6090 #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT 18
6091 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK 0x80000u
6092 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT 19
6093 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK 0x100000u
6094 #define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT 20
6095 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK 0x200000u
6096 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT 21
6097 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK        0x80000000u
6098 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT       31
6099 /* PFD_480 Bit Fields */
6100 #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK        0x3Fu
6101 #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT       0
6102 #define CCM_ANALOG_PFD_480_PFD0_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
6103 #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK      0x40u
6104 #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT     6
6105 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK     0x80u
6106 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT    7
6107 #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK        0x3F00u
6108 #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT       8
6109 #define CCM_ANALOG_PFD_480_PFD1_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
6110 #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK      0x4000u
6111 #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT     14
6112 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK     0x8000u
6113 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT    15
6114 #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK        0x3F0000u
6115 #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT       16
6116 #define CCM_ANALOG_PFD_480_PFD2_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
6117 #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK      0x400000u
6118 #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT     22
6119 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK     0x800000u
6120 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT    23
6121 #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK        0x3F000000u
6122 #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT       24
6123 #define CCM_ANALOG_PFD_480_PFD3_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
6124 #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK      0x40000000u
6125 #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT     30
6126 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK     0x80000000u
6127 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT    31
6128 /* PFD_480_SET Bit Fields */
6129 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK    0x3Fu
6130 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT   0
6131 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
6132 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK  0x40u
6133 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT 6
6134 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK 0x80u
6135 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT 7
6136 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK    0x3F00u
6137 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT   8
6138 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
6139 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK  0x4000u
6140 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT 14
6141 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK 0x8000u
6142 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT 15
6143 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK    0x3F0000u
6144 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT   16
6145 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
6146 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK  0x400000u
6147 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT 22
6148 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK 0x800000u
6149 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT 23
6150 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK    0x3F000000u
6151 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT   24
6152 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
6153 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK  0x40000000u
6154 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT 30
6155 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK 0x80000000u
6156 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT 31
6157 /* PFD_480_CLR Bit Fields */
6158 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK    0x3Fu
6159 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT   0
6160 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
6161 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK  0x40u
6162 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT 6
6163 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK 0x80u
6164 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT 7
6165 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK    0x3F00u
6166 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT   8
6167 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
6168 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK  0x4000u
6169 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT 14
6170 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK 0x8000u
6171 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT 15
6172 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK    0x3F0000u
6173 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT   16
6174 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
6175 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK  0x400000u
6176 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT 22
6177 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK 0x800000u
6178 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT 23
6179 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK    0x3F000000u
6180 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT   24
6181 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
6182 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK  0x40000000u
6183 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT 30
6184 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK 0x80000000u
6185 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT 31
6186 /* PFD_480_TOG Bit Fields */
6187 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK    0x3Fu
6188 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT   0
6189 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
6190 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK  0x40u
6191 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT 6
6192 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK 0x80u
6193 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT 7
6194 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK    0x3F00u
6195 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT   8
6196 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
6197 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK  0x4000u
6198 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT 14
6199 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK 0x8000u
6200 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT 15
6201 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK    0x3F0000u
6202 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT   16
6203 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
6204 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK  0x400000u
6205 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT 22
6206 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK 0x800000u
6207 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT 23
6208 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK    0x3F000000u
6209 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT   24
6210 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
6211 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK  0x40000000u
6212 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT 30
6213 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK 0x80000000u
6214 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT 31
6215 /* PFD_528 Bit Fields */
6216 #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK        0x3Fu
6217 #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT       0
6218 #define CCM_ANALOG_PFD_528_PFD0_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
6219 #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK      0x40u
6220 #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT     6
6221 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK     0x80u
6222 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT    7
6223 #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK        0x3F00u
6224 #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT       8
6225 #define CCM_ANALOG_PFD_528_PFD1_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
6226 #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK      0x4000u
6227 #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT     14
6228 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK     0x8000u
6229 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT    15
6230 #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK        0x3F0000u
6231 #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT       16
6232 #define CCM_ANALOG_PFD_528_PFD2_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
6233 #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK      0x400000u
6234 #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT     22
6235 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK     0x800000u
6236 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT    23
6237 #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK        0x3F000000u
6238 #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT       24
6239 #define CCM_ANALOG_PFD_528_PFD3_FRAC(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
6240 #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK      0x40000000u
6241 #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT     30
6242 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK     0x80000000u
6243 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT    31
6244 /* PFD_528_SET Bit Fields */
6245 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK    0x3Fu
6246 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT   0
6247 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
6248 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK  0x40u
6249 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT 6
6250 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK 0x80u
6251 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT 7
6252 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK    0x3F00u
6253 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT   8
6254 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
6255 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK  0x4000u
6256 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT 14
6257 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK 0x8000u
6258 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT 15
6259 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK    0x3F0000u
6260 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT   16
6261 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
6262 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK  0x400000u
6263 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT 22
6264 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK 0x800000u
6265 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT 23
6266 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK    0x3F000000u
6267 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT   24
6268 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
6269 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK  0x40000000u
6270 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT 30
6271 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK 0x80000000u
6272 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT 31
6273 /* PFD_528_CLR Bit Fields */
6274 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK    0x3Fu
6275 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT   0
6276 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
6277 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK  0x40u
6278 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT 6
6279 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK 0x80u
6280 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT 7
6281 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK    0x3F00u
6282 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT   8
6283 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
6284 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK  0x4000u
6285 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT 14
6286 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK 0x8000u
6287 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT 15
6288 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK    0x3F0000u
6289 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT   16
6290 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
6291 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK  0x400000u
6292 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT 22
6293 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK 0x800000u
6294 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT 23
6295 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK    0x3F000000u
6296 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT   24
6297 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
6298 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK  0x40000000u
6299 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT 30
6300 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK 0x80000000u
6301 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT 31
6302 /* PFD_528_TOG Bit Fields */
6303 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK    0x3Fu
6304 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT   0
6305 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
6306 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK  0x40u
6307 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT 6
6308 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK 0x80u
6309 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT 7
6310 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK    0x3F00u
6311 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT   8
6312 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
6313 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK  0x4000u
6314 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT 14
6315 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK 0x8000u
6316 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT 15
6317 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK    0x3F0000u
6318 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT   16
6319 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
6320 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK  0x400000u
6321 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT 22
6322 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK 0x800000u
6323 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT 23
6324 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK    0x3F000000u
6325 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT   24
6326 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
6327 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK  0x40000000u
6328 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT 30
6329 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK 0x80000000u
6330 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT 31
6331 /* MISC0 Bit Fields */
6332 #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK         0x1u
6333 #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT        0
6334 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u
6335 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT 3
6336 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK      0x70u
6337 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT     4
6338 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
6339 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK       0x80u
6340 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT      7
6341 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK   0xC00u
6342 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT  10
6343 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
6344 #define CCM_ANALOG_MISC0_RTC_RINGOSC_EN_MASK     0x1000u
6345 #define CCM_ANALOG_MISC0_RTC_RINGOSC_EN_SHIFT    12
6346 #define CCM_ANALOG_MISC0_OSC_I_MASK              0x6000u
6347 #define CCM_ANALOG_MISC0_OSC_I_SHIFT             13
6348 #define CCM_ANALOG_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_OSC_I_SHIFT))&CCM_ANALOG_MISC0_OSC_I_MASK)
6349 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK         0x8000u
6350 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT        15
6351 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK      0x10000u
6352 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT     16
6353 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK       0x2000000u
6354 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT      25
6355 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK      0x1C000000u
6356 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT     26
6357 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
6358 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK    0x20000000u
6359 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT   29
6360 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK       0x40000000u
6361 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT      30
6362 #define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK     0x80000000u
6363 #define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT    31
6364 /* MISC0_SET Bit Fields */
6365 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK     0x1u
6366 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT    0
6367 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK 0x8u
6368 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT 3
6369 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK  0x70u
6370 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT 4
6371 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
6372 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK   0x80u
6373 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT  7
6374 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK 0xC00u
6375 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT 10
6376 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
6377 #define CCM_ANALOG_MISC0_SET_RTC_RINGOSC_EN_MASK 0x1000u
6378 #define CCM_ANALOG_MISC0_SET_RTC_RINGOSC_EN_SHIFT 12
6379 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK          0x6000u
6380 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT         13
6381 #define CCM_ANALOG_MISC0_SET_OSC_I(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_OSC_I_SHIFT))&CCM_ANALOG_MISC0_SET_OSC_I_MASK)
6382 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK     0x8000u
6383 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT    15
6384 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK  0x10000u
6385 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT 16
6386 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK   0x2000000u
6387 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT  25
6388 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK  0x1C000000u
6389 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT 26
6390 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
6391 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK 0x20000000u
6392 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT 29
6393 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK   0x40000000u
6394 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT  30
6395 #define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK 0x80000000u
6396 #define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT 31
6397 /* MISC0_CLR Bit Fields */
6398 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK     0x1u
6399 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT    0
6400 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK 0x8u
6401 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT 3
6402 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK  0x70u
6403 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT 4
6404 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
6405 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK   0x80u
6406 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT  7
6407 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK 0xC00u
6408 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT 10
6409 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
6410 #define CCM_ANALOG_MISC0_CLR_RTC_RINGOSC_EN_MASK 0x1000u
6411 #define CCM_ANALOG_MISC0_CLR_RTC_RINGOSC_EN_SHIFT 12
6412 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK          0x6000u
6413 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT         13
6414 #define CCM_ANALOG_MISC0_CLR_OSC_I(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT))&CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
6415 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK     0x8000u
6416 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT    15
6417 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK  0x10000u
6418 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT 16
6419 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK   0x2000000u
6420 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT  25
6421 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK  0x1C000000u
6422 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT 26
6423 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
6424 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK 0x20000000u
6425 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT 29
6426 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK   0x40000000u
6427 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT  30
6428 #define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK 0x80000000u
6429 #define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT 31
6430 /* MISC0_TOG Bit Fields */
6431 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK     0x1u
6432 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT    0
6433 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK 0x8u
6434 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT 3
6435 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK  0x70u
6436 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT 4
6437 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
6438 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK   0x80u
6439 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT  7
6440 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK 0xC00u
6441 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT 10
6442 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
6443 #define CCM_ANALOG_MISC0_TOG_RTC_RINGOSC_EN_MASK 0x1000u
6444 #define CCM_ANALOG_MISC0_TOG_RTC_RINGOSC_EN_SHIFT 12
6445 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK          0x6000u
6446 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT         13
6447 #define CCM_ANALOG_MISC0_TOG_OSC_I(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT))&CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
6448 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK     0x8000u
6449 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT    15
6450 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK  0x10000u
6451 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT 16
6452 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK   0x2000000u
6453 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT  25
6454 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK  0x1C000000u
6455 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT 26
6456 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
6457 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK 0x20000000u
6458 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT 29
6459 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK   0x40000000u
6460 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT  30
6461 #define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK 0x80000000u
6462 #define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT 31
6463 /* MISC1 Bit Fields */
6464 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK      0x1Fu
6465 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT     0
6466 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
6467 #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL_MASK      0x3E0u
6468 #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL_SHIFT     5
6469 #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_LVDS2_CLK_SEL_MASK)
6470 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK      0x400u
6471 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT     10
6472 #define CCM_ANALOG_MISC1_LVDSCLK2_OBEN_MASK      0x800u
6473 #define CCM_ANALOG_MISC1_LVDSCLK2_OBEN_SHIFT     11
6474 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK      0x1000u
6475 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT     12
6476 #define CCM_ANALOG_MISC1_LVDSCLK2_IBEN_MASK      0x2000u
6477 #define CCM_ANALOG_MISC1_LVDSCLK2_IBEN_SHIFT     13
6478 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK 0x10000u
6479 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT 16
6480 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK 0x20000u
6481 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT 17
6482 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK      0x8000000u
6483 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT     27
6484 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK        0x10000000u
6485 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT       28
6486 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK       0x20000000u
6487 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT      29
6488 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK         0x40000000u
6489 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT        30
6490 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK         0x80000000u
6491 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT        31
6492 /* MISC1_SET Bit Fields */
6493 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK  0x1Fu
6494 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT 0
6495 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
6496 #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_MASK  0x3E0u
6497 #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_SHIFT 5
6498 #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_MASK)
6499 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK  0x400u
6500 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT 10
6501 #define CCM_ANALOG_MISC1_SET_LVDSCLK2_OBEN_MASK  0x800u
6502 #define CCM_ANALOG_MISC1_SET_LVDSCLK2_OBEN_SHIFT 11
6503 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK  0x1000u
6504 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT 12
6505 #define CCM_ANALOG_MISC1_SET_LVDSCLK2_IBEN_MASK  0x2000u
6506 #define CCM_ANALOG_MISC1_SET_LVDSCLK2_IBEN_SHIFT 13
6507 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK 0x10000u
6508 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT 16
6509 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK 0x20000u
6510 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT 17
6511 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK  0x8000000u
6512 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT 27
6513 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK    0x10000000u
6514 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT   28
6515 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK   0x20000000u
6516 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT  29
6517 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK     0x40000000u
6518 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT    30
6519 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK     0x80000000u
6520 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT    31
6521 /* MISC1_CLR Bit Fields */
6522 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK  0x1Fu
6523 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT 0
6524 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
6525 #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_MASK  0x3E0u
6526 #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_SHIFT 5
6527 #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_MASK)
6528 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK  0x400u
6529 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT 10
6530 #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_OBEN_MASK  0x800u
6531 #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_OBEN_SHIFT 11
6532 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK  0x1000u
6533 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT 12
6534 #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_IBEN_MASK  0x2000u
6535 #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_IBEN_SHIFT 13
6536 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK 0x10000u
6537 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT 16
6538 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK 0x20000u
6539 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT 17
6540 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK  0x8000000u
6541 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT 27
6542 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK    0x10000000u
6543 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT   28
6544 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK   0x20000000u
6545 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT  29
6546 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK     0x40000000u
6547 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT    30
6548 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK     0x80000000u
6549 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT    31
6550 /* MISC1_TOG Bit Fields */
6551 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK  0x1Fu
6552 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT 0
6553 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
6554 #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_MASK  0x3E0u
6555 #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_SHIFT 5
6556 #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_MASK)
6557 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK  0x400u
6558 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT 10
6559 #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_OBEN_MASK  0x800u
6560 #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_OBEN_SHIFT 11
6561 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK  0x1000u
6562 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT 12
6563 #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_IBEN_MASK  0x2000u
6564 #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_IBEN_SHIFT 13
6565 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK 0x10000u
6566 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT 16
6567 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK 0x20000u
6568 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT 17
6569 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK  0x8000000u
6570 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT 27
6571 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK    0x10000000u
6572 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT   28
6573 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK   0x20000000u
6574 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT  29
6575 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK     0x40000000u
6576 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT    30
6577 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK     0x80000000u
6578 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT    31
6579 /* MISC2 Bit Fields */
6580 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK     0x7u
6581 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT    0
6582 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
6583 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK     0x8u
6584 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT    3
6585 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK     0x20u
6586 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT    5
6587 #define CCM_ANALOG_MISC2_PLL3_disable_MASK       0x80u
6588 #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT      7
6589 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK     0x700u
6590 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT    8
6591 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
6592 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK     0x800u
6593 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT    11
6594 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK     0x2000u
6595 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT    13
6596 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK      0x8000u
6597 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT     15
6598 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK     0x70000u
6599 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT    16
6600 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
6601 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK     0x80000u
6602 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT    19
6603 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK     0x200000u
6604 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT    21
6605 #define CCM_ANALOG_MISC2_REG2_OK_MASK            0x400000u
6606 #define CCM_ANALOG_MISC2_REG2_OK_SHIFT           22
6607 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK      0x800000u
6608 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT     23
6609 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK     0x3000000u
6610 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT    24
6611 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
6612 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK     0xC000000u
6613 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT    26
6614 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
6615 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK     0x30000000u
6616 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT    28
6617 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
6618 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK          0xC0000000u
6619 #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT         30
6620 #define CCM_ANALOG_MISC2_VIDEO_DIV(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
6621 /* MISC2_SET Bit Fields */
6622 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK 0x7u
6623 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT 0
6624 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
6625 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK 0x8u
6626 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT 3
6627 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK 0x20u
6628 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT 5
6629 #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK   0x80u
6630 #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT  7
6631 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK 0x700u
6632 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT 8
6633 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
6634 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK 0x800u
6635 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT 11
6636 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK 0x2000u
6637 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT 13
6638 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK  0x8000u
6639 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT 15
6640 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK 0x70000u
6641 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT 16
6642 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
6643 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK 0x80000u
6644 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT 19
6645 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK 0x200000u
6646 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT 21
6647 #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK        0x400000u
6648 #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT       22
6649 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK  0x800000u
6650 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT 23
6651 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK 0x3000000u
6652 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT 24
6653 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
6654 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK 0xC000000u
6655 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT 26
6656 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
6657 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK 0x30000000u
6658 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT 28
6659 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
6660 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK      0xC0000000u
6661 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT     30
6662 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
6663 /* MISC2_CLR Bit Fields */
6664 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK 0x7u
6665 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT 0
6666 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
6667 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK 0x8u
6668 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT 3
6669 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK 0x20u
6670 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT 5
6671 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK   0x80u
6672 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT  7
6673 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK 0x700u
6674 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT 8
6675 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
6676 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK 0x800u
6677 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT 11
6678 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK 0x2000u
6679 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT 13
6680 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK  0x8000u
6681 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT 15
6682 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK 0x70000u
6683 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT 16
6684 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
6685 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK 0x80000u
6686 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT 19
6687 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK 0x200000u
6688 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT 21
6689 #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK        0x400000u
6690 #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT       22
6691 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK  0x800000u
6692 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT 23
6693 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK 0x3000000u
6694 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT 24
6695 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
6696 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK 0xC000000u
6697 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT 26
6698 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
6699 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK 0x30000000u
6700 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT 28
6701 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
6702 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK      0xC0000000u
6703 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT     30
6704 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
6705 /* MISC2_TOG Bit Fields */
6706 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK 0x7u
6707 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT 0
6708 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
6709 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK 0x8u
6710 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT 3
6711 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK 0x20u
6712 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT 5
6713 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK   0x80u
6714 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT  7
6715 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK 0x700u
6716 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT 8
6717 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
6718 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK 0x800u
6719 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT 11
6720 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK 0x2000u
6721 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT 13
6722 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK  0x8000u
6723 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT 15
6724 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK 0x70000u
6725 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT 16
6726 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
6727 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK 0x80000u
6728 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT 19
6729 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK 0x200000u
6730 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT 21
6731 #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK        0x400000u
6732 #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT       22
6733 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK  0x800000u
6734 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT 23
6735 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK 0x3000000u
6736 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT 24
6737 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
6738 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK 0xC000000u
6739 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT 26
6740 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
6741 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK 0x30000000u
6742 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT 28
6743 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
6744 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK      0xC0000000u
6745 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT     30
6746 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
6747 
6748 /*!
6749  * @}
6750  */ /* end of group CCM_ANALOG_Register_Masks */
6751 
6752 /* CCM_ANALOG - Peripheral instance base addresses */
6753 /** Peripheral CCM_ANALOG base address */
6754 #define CCM_ANALOG_BASE                          (0x420C8000u)
6755 /** Peripheral CCM_ANALOG base pointer */
6756 #define CCM_ANALOG                               ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
6757 #define CCM_ANALOG_BASE_PTR                      (CCM_ANALOG)
6758 /** Array initializer of CCM_ANALOG peripheral base addresses */
6759 #define CCM_ANALOG_BASE_ADDRS                    { CCM_ANALOG_BASE }
6760 /** Array initializer of CCM_ANALOG peripheral base pointers */
6761 #define CCM_ANALOG_BASE_PTRS                     { CCM_ANALOG }
6762 
6763 /* ----------------------------------------------------------------------------
6764    -- CCM_ANALOG - Register accessor macros
6765    ---------------------------------------------------------------------------- */
6766 
6767 /*!
6768  * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros
6769  * @{
6770  */
6771 
6772 /* CCM_ANALOG - Register instance definitions */
6773 /* CCM_ANALOG */
6774 #define CCM_ANALOG_PLL_ARM                       CCM_ANALOG_PLL_ARM_REG(CCM_ANALOG_BASE_PTR)
6775 #define CCM_ANALOG_PLL_ARM_SET                   CCM_ANALOG_PLL_ARM_SET_REG(CCM_ANALOG_BASE_PTR)
6776 #define CCM_ANALOG_PLL_ARM_CLR                   CCM_ANALOG_PLL_ARM_CLR_REG(CCM_ANALOG_BASE_PTR)
6777 #define CCM_ANALOG_PLL_ARM_TOG                   CCM_ANALOG_PLL_ARM_TOG_REG(CCM_ANALOG_BASE_PTR)
6778 #define CCM_ANALOG_PLL_USB1                      CCM_ANALOG_PLL_USB1_REG(CCM_ANALOG_BASE_PTR)
6779 #define CCM_ANALOG_PLL_USB1_SET                  CCM_ANALOG_PLL_USB1_SET_REG(CCM_ANALOG_BASE_PTR)
6780 #define CCM_ANALOG_PLL_USB1_CLR                  CCM_ANALOG_PLL_USB1_CLR_REG(CCM_ANALOG_BASE_PTR)
6781 #define CCM_ANALOG_PLL_USB1_TOG                  CCM_ANALOG_PLL_USB1_TOG_REG(CCM_ANALOG_BASE_PTR)
6782 #define CCM_ANALOG_PLL_USB2                      CCM_ANALOG_PLL_USB2_REG(CCM_ANALOG_BASE_PTR)
6783 #define CCM_ANALOG_PLL_USB2_SET                  CCM_ANALOG_PLL_USB2_SET_REG(CCM_ANALOG_BASE_PTR)
6784 #define CCM_ANALOG_PLL_USB2_CLR                  CCM_ANALOG_PLL_USB2_CLR_REG(CCM_ANALOG_BASE_PTR)
6785 #define CCM_ANALOG_PLL_USB2_TOG                  CCM_ANALOG_PLL_USB2_TOG_REG(CCM_ANALOG_BASE_PTR)
6786 #define CCM_ANALOG_PLL_SYS                       CCM_ANALOG_PLL_SYS_REG(CCM_ANALOG_BASE_PTR)
6787 #define CCM_ANALOG_PLL_SYS_SET                   CCM_ANALOG_PLL_SYS_SET_REG(CCM_ANALOG_BASE_PTR)
6788 #define CCM_ANALOG_PLL_SYS_CLR                   CCM_ANALOG_PLL_SYS_CLR_REG(CCM_ANALOG_BASE_PTR)
6789 #define CCM_ANALOG_PLL_SYS_TOG                   CCM_ANALOG_PLL_SYS_TOG_REG(CCM_ANALOG_BASE_PTR)
6790 #define CCM_ANALOG_PLL_SYS_SS                    CCM_ANALOG_PLL_SYS_SS_REG(CCM_ANALOG_BASE_PTR)
6791 #define CCM_ANALOG_PLL_AUDIO                     CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG_BASE_PTR)
6792 #define CCM_ANALOG_PLL_AUDIO_SET                 CCM_ANALOG_PLL_AUDIO_SET_REG(CCM_ANALOG_BASE_PTR)
6793 #define CCM_ANALOG_PLL_AUDIO_CLR                 CCM_ANALOG_PLL_AUDIO_CLR_REG(CCM_ANALOG_BASE_PTR)
6794 #define CCM_ANALOG_PLL_AUDIO_TOG                 CCM_ANALOG_PLL_AUDIO_TOG_REG(CCM_ANALOG_BASE_PTR)
6795 #define CCM_ANALOG_PLL_AUDIO_NUM                 CCM_ANALOG_PLL_AUDIO_NUM_REG(CCM_ANALOG_BASE_PTR)
6796 #define CCM_ANALOG_PLL_AUDIO_DENOM               CCM_ANALOG_PLL_AUDIO_DENOM_REG(CCM_ANALOG_BASE_PTR)
6797 #define CCM_ANALOG_PLL_VIDEO                     CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG_BASE_PTR)
6798 #define CCM_ANALOG_PLL_VIDEO_SET                 CCM_ANALOG_PLL_VIDEO_SET_REG(CCM_ANALOG_BASE_PTR)
6799 #define CCM_ANALOG_PLL_VIDEO_CLR                 CCM_ANALOG_PLL_VIDEO_CLR_REG(CCM_ANALOG_BASE_PTR)
6800 #define CCM_ANALOG_PLL_VIDEO_TOG                 CCM_ANALOG_PLL_VIDEO_TOG_REG(CCM_ANALOG_BASE_PTR)
6801 #define CCM_ANALOG_PLL_VIDEO_NUM                 CCM_ANALOG_PLL_VIDEO_NUM_REG(CCM_ANALOG_BASE_PTR)
6802 #define CCM_ANALOG_PLL_VIDEO_DENOM               CCM_ANALOG_PLL_VIDEO_DENOM_REG(CCM_ANALOG_BASE_PTR)
6803 #define CCM_ANALOG_PLL_ENET                      CCM_ANALOG_PLL_ENET_REG(CCM_ANALOG_BASE_PTR)
6804 #define CCM_ANALOG_PLL_ENET_SET                  CCM_ANALOG_PLL_ENET_SET_REG(CCM_ANALOG_BASE_PTR)
6805 #define CCM_ANALOG_PLL_ENET_CLR                  CCM_ANALOG_PLL_ENET_CLR_REG(CCM_ANALOG_BASE_PTR)
6806 #define CCM_ANALOG_PLL_ENET_TOG                  CCM_ANALOG_PLL_ENET_TOG_REG(CCM_ANALOG_BASE_PTR)
6807 #define CCM_ANALOG_PFD_480                       CCM_ANALOG_PFD_480_REG(CCM_ANALOG_BASE_PTR)
6808 #define CCM_ANALOG_PFD_480_SET                   CCM_ANALOG_PFD_480_SET_REG(CCM_ANALOG_BASE_PTR)
6809 #define CCM_ANALOG_PFD_480_CLR                   CCM_ANALOG_PFD_480_CLR_REG(CCM_ANALOG_BASE_PTR)
6810 #define CCM_ANALOG_PFD_480_TOG                   CCM_ANALOG_PFD_480_TOG_REG(CCM_ANALOG_BASE_PTR)
6811 #define CCM_ANALOG_PFD_528                       CCM_ANALOG_PFD_528_REG(CCM_ANALOG_BASE_PTR)
6812 #define CCM_ANALOG_PFD_528_SET                   CCM_ANALOG_PFD_528_SET_REG(CCM_ANALOG_BASE_PTR)
6813 #define CCM_ANALOG_PFD_528_CLR                   CCM_ANALOG_PFD_528_CLR_REG(CCM_ANALOG_BASE_PTR)
6814 #define CCM_ANALOG_PFD_528_TOG                   CCM_ANALOG_PFD_528_TOG_REG(CCM_ANALOG_BASE_PTR)
6815 #define CCM_ANALOG_MISC0                         CCM_ANALOG_MISC0_REG(CCM_ANALOG_BASE_PTR)
6816 #define CCM_ANALOG_MISC0_SET                     CCM_ANALOG_MISC0_SET_REG(CCM_ANALOG_BASE_PTR)
6817 #define CCM_ANALOG_MISC0_CLR                     CCM_ANALOG_MISC0_CLR_REG(CCM_ANALOG_BASE_PTR)
6818 #define CCM_ANALOG_MISC0_TOG                     CCM_ANALOG_MISC0_TOG_REG(CCM_ANALOG_BASE_PTR)
6819 #define CCM_ANALOG_MISC1                         CCM_ANALOG_MISC1_REG(CCM_ANALOG_BASE_PTR)
6820 #define CCM_ANALOG_MISC1_SET                     CCM_ANALOG_MISC1_SET_REG(CCM_ANALOG_BASE_PTR)
6821 #define CCM_ANALOG_MISC1_CLR                     CCM_ANALOG_MISC1_CLR_REG(CCM_ANALOG_BASE_PTR)
6822 #define CCM_ANALOG_MISC1_TOG                     CCM_ANALOG_MISC1_TOG_REG(CCM_ANALOG_BASE_PTR)
6823 #define CCM_ANALOG_MISC2                         CCM_ANALOG_MISC2_REG(CCM_ANALOG_BASE_PTR)
6824 #define CCM_ANALOG_MISC2_SET                     CCM_ANALOG_MISC2_SET_REG(CCM_ANALOG_BASE_PTR)
6825 #define CCM_ANALOG_MISC2_CLR                     CCM_ANALOG_MISC2_CLR_REG(CCM_ANALOG_BASE_PTR)
6826 #define CCM_ANALOG_MISC2_TOG                     CCM_ANALOG_MISC2_TOG_REG(CCM_ANALOG_BASE_PTR)
6827 
6828 /*!
6829  * @}
6830  */ /* end of group CCM_ANALOG_Register_Accessor_Macros */
6831 
6832 /*!
6833  * @}
6834  */ /* end of group CCM_ANALOG_Peripheral */
6835 
6836 /* ----------------------------------------------------------------------------
6837    -- CSI Peripheral Access Layer
6838    ---------------------------------------------------------------------------- */
6839 
6840 /*!
6841  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
6842  * @{
6843  */
6844 
6845 /** CSI - Register Layout Typedef */
6846 typedef struct {
6847   __IO  uint32_t CSICR1;                                 /**< CSI Control Register 1, offset: 0x0 */
6848   __IO  uint32_t CSICR2;                                 /**< CSI Control Register 2, offset: 0x4 */
6849   __IO  uint32_t CSICR3;                                 /**< CSI Control Register 3, offset: 0x8 */
6850   __I   uint32_t CSISTATFIFO;                            /**< CSI Statistic FIFO Register, offset: 0xC */
6851   __I   uint32_t CSIRFIFO;                               /**< CSI RX FIFO Register, offset: 0x10 */
6852   __IO  uint32_t CSIRXCNT;                               /**< CSI RX Count Register, offset: 0x14 */
6853   __IO  uint32_t CSISR;                                  /**< CSI Status Register, offset: 0x18 */
6854   uint8_t RESERVED_0[4];
6855   __IO  uint32_t CSIDMASA_STATFIFO;                      /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
6856   __IO  uint32_t CSIDMATS_STATFIFO;                      /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
6857   __IO  uint32_t CSIDMASA_FB1;                           /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
6858   __IO  uint32_t CSIDMASA_FB2;                           /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
6859   __IO  uint32_t CSIFBUF_PARA;                           /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
6860   __IO  uint32_t CSIIMAG_PARA;                           /**< CSI Image Parameter Register, offset: 0x34 */
6861   uint8_t RESERVED_1[16];
6862   __IO  uint32_t CSICR18;                                /**< CSI Control Register 18, offset: 0x48 */
6863   __IO  uint32_t CSICR19;                                /**< CSI Control Register 19, offset: 0x4C */
6864 } CSI_Type, *CSI_MemMapPtr;
6865 
6866 /* ----------------------------------------------------------------------------
6867    -- CSI - Register accessor macros
6868    ---------------------------------------------------------------------------- */
6869 
6870 /*!
6871  * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros
6872  * @{
6873  */
6874 
6875 /* CSI - Register accessors */
6876 #define CSI_CSICR1_REG(base)                     ((base)->CSICR1)
6877 #define CSI_CSICR2_REG(base)                     ((base)->CSICR2)
6878 #define CSI_CSICR3_REG(base)                     ((base)->CSICR3)
6879 #define CSI_CSISTATFIFO_REG(base)                ((base)->CSISTATFIFO)
6880 #define CSI_CSIRFIFO_REG(base)                   ((base)->CSIRFIFO)
6881 #define CSI_CSIRXCNT_REG(base)                   ((base)->CSIRXCNT)
6882 #define CSI_CSISR_REG(base)                      ((base)->CSISR)
6883 #define CSI_CSIDMASA_STATFIFO_REG(base)          ((base)->CSIDMASA_STATFIFO)
6884 #define CSI_CSIDMATS_STATFIFO_REG(base)          ((base)->CSIDMATS_STATFIFO)
6885 #define CSI_CSIDMASA_FB1_REG(base)               ((base)->CSIDMASA_FB1)
6886 #define CSI_CSIDMASA_FB2_REG(base)               ((base)->CSIDMASA_FB2)
6887 #define CSI_CSIFBUF_PARA_REG(base)               ((base)->CSIFBUF_PARA)
6888 #define CSI_CSIIMAG_PARA_REG(base)               ((base)->CSIIMAG_PARA)
6889 #define CSI_CSICR18_REG(base)                    ((base)->CSICR18)
6890 #define CSI_CSICR19_REG(base)                    ((base)->CSICR19)
6891 
6892 /*!
6893  * @}
6894  */ /* end of group CSI_Register_Accessor_Macros */
6895 
6896 /* ----------------------------------------------------------------------------
6897    -- CSI Register Masks
6898    ---------------------------------------------------------------------------- */
6899 
6900 /*!
6901  * @addtogroup CSI_Register_Masks CSI Register Masks
6902  * @{
6903  */
6904 
6905 /* CSICR1 Bit Fields */
6906 #define CSI_CSICR1_PIXEL_BIT_MASK                0x1u
6907 #define CSI_CSICR1_PIXEL_BIT_SHIFT               0
6908 #define CSI_CSICR1_REDGE_MASK                    0x2u
6909 #define CSI_CSICR1_REDGE_SHIFT                   1
6910 #define CSI_CSICR1_INV_PCLK_MASK                 0x4u
6911 #define CSI_CSICR1_INV_PCLK_SHIFT                2
6912 #define CSI_CSICR1_INV_DATA_MASK                 0x8u
6913 #define CSI_CSICR1_INV_DATA_SHIFT                3
6914 #define CSI_CSICR1_GCLK_MODE_MASK                0x10u
6915 #define CSI_CSICR1_GCLK_MODE_SHIFT               4
6916 #define CSI_CSICR1_CLR_RXFIFO_MASK               0x20u
6917 #define CSI_CSICR1_CLR_RXFIFO_SHIFT              5
6918 #define CSI_CSICR1_CLR_STATFIFO_MASK             0x40u
6919 #define CSI_CSICR1_CLR_STATFIFO_SHIFT            6
6920 #define CSI_CSICR1_PACK_DIR_MASK                 0x80u
6921 #define CSI_CSICR1_PACK_DIR_SHIFT                7
6922 #define CSI_CSICR1_FCC_MASK                      0x100u
6923 #define CSI_CSICR1_FCC_SHIFT                     8
6924 #define CSI_CSICR1_CCIR_EN_MASK                  0x400u
6925 #define CSI_CSICR1_CCIR_EN_SHIFT                 10
6926 #define CSI_CSICR1_HSYNC_POL_MASK                0x800u
6927 #define CSI_CSICR1_HSYNC_POL_SHIFT               11
6928 #define CSI_CSICR1_SOF_INTEN_MASK                0x10000u
6929 #define CSI_CSICR1_SOF_INTEN_SHIFT               16
6930 #define CSI_CSICR1_SOF_POL_MASK                  0x20000u
6931 #define CSI_CSICR1_SOF_POL_SHIFT                 17
6932 #define CSI_CSICR1_RXFF_INTEN_MASK               0x40000u
6933 #define CSI_CSICR1_RXFF_INTEN_SHIFT              18
6934 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK       0x80000u
6935 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT      19
6936 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK       0x100000u
6937 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT      20
6938 #define CSI_CSICR1_STATFF_INTEN_MASK             0x200000u
6939 #define CSI_CSICR1_STATFF_INTEN_SHIFT            21
6940 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK       0x400000u
6941 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT      22
6942 #define CSI_CSICR1_RF_OR_INTEN_MASK              0x1000000u
6943 #define CSI_CSICR1_RF_OR_INTEN_SHIFT             24
6944 #define CSI_CSICR1_SF_OR_INTEN_MASK              0x2000000u
6945 #define CSI_CSICR1_SF_OR_INTEN_SHIFT             25
6946 #define CSI_CSICR1_COF_INT_EN_MASK               0x4000000u
6947 #define CSI_CSICR1_COF_INT_EN_SHIFT              26
6948 #define CSI_CSICR1_VIDEO_MODE_MASK               0x8000000u
6949 #define CSI_CSICR1_VIDEO_MODE_SHIFT              27
6950 #define CSI_CSICR1_PrP_IF_EN_MASK                0x10000000u
6951 #define CSI_CSICR1_PrP_IF_EN_SHIFT               28
6952 #define CSI_CSICR1_EOF_INT_EN_MASK               0x20000000u
6953 #define CSI_CSICR1_EOF_INT_EN_SHIFT              29
6954 #define CSI_CSICR1_EXT_VSYNC_MASK                0x40000000u
6955 #define CSI_CSICR1_EXT_VSYNC_SHIFT               30
6956 #define CSI_CSICR1_SWAP16_EN_MASK                0x80000000u
6957 #define CSI_CSICR1_SWAP16_EN_SHIFT               31
6958 /* CSICR2 Bit Fields */
6959 #define CSI_CSICR2_HSC_MASK                      0xFFu
6960 #define CSI_CSICR2_HSC_SHIFT                     0
6961 #define CSI_CSICR2_HSC(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_HSC_SHIFT))&CSI_CSICR2_HSC_MASK)
6962 #define CSI_CSICR2_VSC_MASK                      0xFF00u
6963 #define CSI_CSICR2_VSC_SHIFT                     8
6964 #define CSI_CSICR2_VSC(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_VSC_SHIFT))&CSI_CSICR2_VSC_MASK)
6965 #define CSI_CSICR2_LVRM_MASK                     0x70000u
6966 #define CSI_CSICR2_LVRM_SHIFT                    16
6967 #define CSI_CSICR2_LVRM(x)                       (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_LVRM_SHIFT))&CSI_CSICR2_LVRM_MASK)
6968 #define CSI_CSICR2_BTS_MASK                      0x180000u
6969 #define CSI_CSICR2_BTS_SHIFT                     19
6970 #define CSI_CSICR2_BTS(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_BTS_SHIFT))&CSI_CSICR2_BTS_MASK)
6971 #define CSI_CSICR2_SCE_MASK                      0x800000u
6972 #define CSI_CSICR2_SCE_SHIFT                     23
6973 #define CSI_CSICR2_AFS_MASK                      0x3000000u
6974 #define CSI_CSICR2_AFS_SHIFT                     24
6975 #define CSI_CSICR2_AFS(x)                        (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_AFS_SHIFT))&CSI_CSICR2_AFS_MASK)
6976 #define CSI_CSICR2_DRM_MASK                      0x4000000u
6977 #define CSI_CSICR2_DRM_SHIFT                     26
6978 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK       0x30000000u
6979 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT      28
6980 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
6981 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK       0xC0000000u
6982 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT      30
6983 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
6984 /* CSICR3 Bit Fields */
6985 #define CSI_CSICR3_ECC_AUTO_EN_MASK              0x1u
6986 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT             0
6987 #define CSI_CSICR3_ECC_INT_EN_MASK               0x2u
6988 #define CSI_CSICR3_ECC_INT_EN_SHIFT              1
6989 #define CSI_CSICR3_ZERO_PACK_EN_MASK             0x4u
6990 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT            2
6991 #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK          0x8u
6992 #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT         3
6993 #define CSI_CSICR3_RxFF_LEVEL_MASK               0x70u
6994 #define CSI_CSICR3_RxFF_LEVEL_SHIFT              4
6995 #define CSI_CSICR3_RxFF_LEVEL(x)                 (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_RxFF_LEVEL_SHIFT))&CSI_CSICR3_RxFF_LEVEL_MASK)
6996 #define CSI_CSICR3_HRESP_ERR_EN_MASK             0x80u
6997 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT            7
6998 #define CSI_CSICR3_STATFF_LEVEL_MASK             0x700u
6999 #define CSI_CSICR3_STATFF_LEVEL_SHIFT            8
7000 #define CSI_CSICR3_STATFF_LEVEL(x)               (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_STATFF_LEVEL_SHIFT))&CSI_CSICR3_STATFF_LEVEL_MASK)
7001 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK           0x800u
7002 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT          11
7003 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK           0x1000u
7004 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT          12
7005 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK          0x2000u
7006 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT         13
7007 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK          0x4000u
7008 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT         14
7009 #define CSI_CSICR3_FRMCNT_RST_MASK               0x8000u
7010 #define CSI_CSICR3_FRMCNT_RST_SHIFT              15
7011 #define CSI_CSICR3_FRMCNT_MASK                   0xFFFF0000u
7012 #define CSI_CSICR3_FRMCNT_SHIFT                  16
7013 #define CSI_CSICR3_FRMCNT(x)                     (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_FRMCNT_SHIFT))&CSI_CSICR3_FRMCNT_MASK)
7014 /* CSISTATFIFO Bit Fields */
7015 #define CSI_CSISTATFIFO_STAT_MASK                0xFFFFFFFFu
7016 #define CSI_CSISTATFIFO_STAT_SHIFT               0
7017 #define CSI_CSISTATFIFO_STAT(x)                  (((uint32_t)(((uint32_t)(x))<<CSI_CSISTATFIFO_STAT_SHIFT))&CSI_CSISTATFIFO_STAT_MASK)
7018 /* CSIRFIFO Bit Fields */
7019 #define CSI_CSIRFIFO_IMAGE_MASK                  0xFFFFFFFFu
7020 #define CSI_CSIRFIFO_IMAGE_SHIFT                 0
7021 #define CSI_CSIRFIFO_IMAGE(x)                    (((uint32_t)(((uint32_t)(x))<<CSI_CSIRFIFO_IMAGE_SHIFT))&CSI_CSIRFIFO_IMAGE_MASK)
7022 /* CSIRXCNT Bit Fields */
7023 #define CSI_CSIRXCNT_RXCNT_MASK                  0x3FFFFFu
7024 #define CSI_CSIRXCNT_RXCNT_SHIFT                 0
7025 #define CSI_CSIRXCNT_RXCNT(x)                    (((uint32_t)(((uint32_t)(x))<<CSI_CSIRXCNT_RXCNT_SHIFT))&CSI_CSIRXCNT_RXCNT_MASK)
7026 /* CSISR Bit Fields */
7027 #define CSI_CSISR_DRDY_MASK                      0x1u
7028 #define CSI_CSISR_DRDY_SHIFT                     0
7029 #define CSI_CSISR_ECC_INT_MASK                   0x2u
7030 #define CSI_CSISR_ECC_INT_SHIFT                  1
7031 #define CSI_CSISR_HRESP_ERR_INT_MASK             0x80u
7032 #define CSI_CSISR_HRESP_ERR_INT_SHIFT            7
7033 #define CSI_CSISR_COF_INT_MASK                   0x2000u
7034 #define CSI_CSISR_COF_INT_SHIFT                  13
7035 #define CSI_CSISR_F1_INT_MASK                    0x4000u
7036 #define CSI_CSISR_F1_INT_SHIFT                   14
7037 #define CSI_CSISR_F2_INT_MASK                    0x8000u
7038 #define CSI_CSISR_F2_INT_SHIFT                   15
7039 #define CSI_CSISR_SOF_INT_MASK                   0x10000u
7040 #define CSI_CSISR_SOF_INT_SHIFT                  16
7041 #define CSI_CSISR_EOF_INT_MASK                   0x20000u
7042 #define CSI_CSISR_EOF_INT_SHIFT                  17
7043 #define CSI_CSISR_RxFF_INT_MASK                  0x40000u
7044 #define CSI_CSISR_RxFF_INT_SHIFT                 18
7045 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK          0x80000u
7046 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT         19
7047 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK          0x100000u
7048 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT         20
7049 #define CSI_CSISR_STATFF_INT_MASK                0x200000u
7050 #define CSI_CSISR_STATFF_INT_SHIFT               21
7051 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK          0x400000u
7052 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT         22
7053 #define CSI_CSISR_RF_OR_INT_MASK                 0x1000000u
7054 #define CSI_CSISR_RF_OR_INT_SHIFT                24
7055 #define CSI_CSISR_SF_OR_INT_MASK                 0x2000000u
7056 #define CSI_CSISR_SF_OR_INT_SHIFT                25
7057 #define CSI_CSISR_DMA_FIELD1_DONE_MASK           0x4000000u
7058 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT          26
7059 #define CSI_CSISR_DMA_FIELD0_DONE_MASK           0x8000000u
7060 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT          27
7061 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK    0x10000000u
7062 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT   28
7063 /* CSIDMASA_STATFIFO Bit Fields */
7064 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK 0xFFFFFFFCu
7065 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT 2
7066 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT))&CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
7067 /* CSIDMATS_STATFIFO Bit Fields */
7068 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK 0xFFFFFFFFu
7069 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT 0
7070 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT))&CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
7071 /* CSIDMASA_FB1 Bit Fields */
7072 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK 0xFFFFFFFCu
7073 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT 2
7074 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)   (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT))&CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
7075 /* CSIDMASA_FB2 Bit Fields */
7076 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK 0xFFFFFFFCu
7077 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT 2
7078 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)   (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT))&CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
7079 /* CSIFBUF_PARA Bit Fields */
7080 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK        0xFFFFu
7081 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT       0
7082 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)          (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
7083 /* CSIIMAG_PARA Bit Fields */
7084 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK       0xFFFFu
7085 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT      0
7086 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)         (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
7087 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK        0xFFFF0000u
7088 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT       16
7089 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)          (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
7090 /* CSICR18 Bit Fields */
7091 #define CSI_CSICR18_NTSC_EN_MASK                 0x1u
7092 #define CSI_CSICR18_NTSC_EN_SHIFT                0
7093 #define CSI_CSICR18_TVDECODER_IN_EN_MASK         0x2u
7094 #define CSI_CSICR18_TVDECODER_IN_EN_SHIFT        1
7095 #define CSI_CSICR18_DEINTERLACE_EN_MASK          0x4u
7096 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT         2
7097 #define CSI_CSICR18_PARALLEL24_EN_MASK           0x8u
7098 #define CSI_CSICR18_PARALLEL24_EN_SHIFT          3
7099 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK      0x10u
7100 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     4
7101 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     0x20u
7102 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT    5
7103 #define CSI_CSICR18_FIELD0_DONE_IE_MASK          0x40u
7104 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT         6
7105 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK      0x80u
7106 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     7
7107 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK        0x100u
7108 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT       8
7109 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK 0x200u
7110 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT 9
7111 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK      0x400u
7112 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     10
7113 #define CSI_CSICR18_AHB_HPROT_MASK               0xF000u
7114 #define CSI_CSICR18_AHB_HPROT_SHIFT              12
7115 #define CSI_CSICR18_AHB_HPROT(x)                 (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_AHB_HPROT_SHIFT))&CSI_CSICR18_AHB_HPROT_MASK)
7116 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK  0x30000u
7117 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT 16
7118 #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x)    (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT))&CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)
7119 #define CSI_CSICR18_MASK_OPTION_MASK             0xC0000u
7120 #define CSI_CSICR18_MASK_OPTION_SHIFT            18
7121 #define CSI_CSICR18_MASK_OPTION(x)               (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MASK_OPTION_SHIFT))&CSI_CSICR18_MASK_OPTION_MASK)
7122 #define CSI_CSICR18_CSI_ENABLE_MASK              0x80000000u
7123 #define CSI_CSICR18_CSI_ENABLE_SHIFT             31
7124 /* CSICR19 Bit Fields */
7125 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK 0xFFu
7126 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT 0
7127 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT))&CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
7128 
7129 /*!
7130  * @}
7131  */ /* end of group CSI_Register_Masks */
7132 
7133 /* CSI - Peripheral instance base addresses */
7134 /** Peripheral CSI1 base address */
7135 #define CSI1_BASE                                (0x42214000u)
7136 /** Peripheral CSI1 base pointer */
7137 #define CSI1                                     ((CSI_Type *)CSI1_BASE)
7138 #define CSI1_BASE_PTR                            (CSI1)
7139 /** Peripheral CSI2 base address */
7140 #define CSI2_BASE                                (0x4221C000u)
7141 /** Peripheral CSI2 base pointer */
7142 #define CSI2                                     ((CSI_Type *)CSI2_BASE)
7143 #define CSI2_BASE_PTR                            (CSI2)
7144 /** Array initializer of CSI peripheral base addresses */
7145 #define CSI_BASE_ADDRS                           { CSI1_BASE, CSI2_BASE }
7146 /** Array initializer of CSI peripheral base pointers */
7147 #define CSI_BASE_PTRS                            { CSI1, CSI2 }
7148 /** Interrupt vectors for the CSI peripheral type */
7149 #define CSI_IRQS                                 { CSI1_IRQn, CSI2_IRQn }
7150 
7151 /* ----------------------------------------------------------------------------
7152    -- CSI - Register accessor macros
7153    ---------------------------------------------------------------------------- */
7154 
7155 /*!
7156  * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros
7157  * @{
7158  */
7159 
7160 /* CSI - Register instance definitions */
7161 /* CSI1 */
7162 #define CSI1_CSICR1                              CSI_CSICR1_REG(CSI1_BASE_PTR)
7163 #define CSI1_CSICR2                              CSI_CSICR2_REG(CSI1_BASE_PTR)
7164 #define CSI1_CSICR3                              CSI_CSICR3_REG(CSI1_BASE_PTR)
7165 #define CSI1_CSISTATFIFO                         CSI_CSISTATFIFO_REG(CSI1_BASE_PTR)
7166 #define CSI1_CSIRFIFO                            CSI_CSIRFIFO_REG(CSI1_BASE_PTR)
7167 #define CSI1_CSIRXCNT                            CSI_CSIRXCNT_REG(CSI1_BASE_PTR)
7168 #define CSI1_CSISR                               CSI_CSISR_REG(CSI1_BASE_PTR)
7169 #define CSI1_CSIDMASA_STATFIFO                   CSI_CSIDMASA_STATFIFO_REG(CSI1_BASE_PTR)
7170 #define CSI1_CSIDMATS_STATFIFO                   CSI_CSIDMATS_STATFIFO_REG(CSI1_BASE_PTR)
7171 #define CSI1_CSIDMASA_FB1                        CSI_CSIDMASA_FB1_REG(CSI1_BASE_PTR)
7172 #define CSI1_CSIDMASA_FB2                        CSI_CSIDMASA_FB2_REG(CSI1_BASE_PTR)
7173 #define CSI1_CSIFBUF_PARA                        CSI_CSIFBUF_PARA_REG(CSI1_BASE_PTR)
7174 #define CSI1_CSIIMAG_PARA                        CSI_CSIIMAG_PARA_REG(CSI1_BASE_PTR)
7175 #define CSI1_CSICR18                             CSI_CSICR18_REG(CSI1_BASE_PTR)
7176 #define CSI1_CSICR19                             CSI_CSICR19_REG(CSI1_BASE_PTR)
7177 /* CSI2 */
7178 #define CSI2_CSICR1                              CSI_CSICR1_REG(CSI2_BASE_PTR)
7179 #define CSI2_CSICR2                              CSI_CSICR2_REG(CSI2_BASE_PTR)
7180 #define CSI2_CSICR3                              CSI_CSICR3_REG(CSI2_BASE_PTR)
7181 #define CSI2_CSISTATFIFO                         CSI_CSISTATFIFO_REG(CSI2_BASE_PTR)
7182 #define CSI2_CSIRFIFO                            CSI_CSIRFIFO_REG(CSI2_BASE_PTR)
7183 #define CSI2_CSIRXCNT                            CSI_CSIRXCNT_REG(CSI2_BASE_PTR)
7184 #define CSI2_CSISR                               CSI_CSISR_REG(CSI2_BASE_PTR)
7185 #define CSI2_CSIDMASA_STATFIFO                   CSI_CSIDMASA_STATFIFO_REG(CSI2_BASE_PTR)
7186 #define CSI2_CSIDMATS_STATFIFO                   CSI_CSIDMATS_STATFIFO_REG(CSI2_BASE_PTR)
7187 #define CSI2_CSIDMASA_FB1                        CSI_CSIDMASA_FB1_REG(CSI2_BASE_PTR)
7188 #define CSI2_CSIDMASA_FB2                        CSI_CSIDMASA_FB2_REG(CSI2_BASE_PTR)
7189 #define CSI2_CSIFBUF_PARA                        CSI_CSIFBUF_PARA_REG(CSI2_BASE_PTR)
7190 #define CSI2_CSIIMAG_PARA                        CSI_CSIIMAG_PARA_REG(CSI2_BASE_PTR)
7191 #define CSI2_CSICR18                             CSI_CSICR18_REG(CSI2_BASE_PTR)
7192 #define CSI2_CSICR19                             CSI_CSICR19_REG(CSI2_BASE_PTR)
7193 
7194 /*!
7195  * @}
7196  */ /* end of group CSI_Register_Accessor_Macros */
7197 
7198 /*!
7199  * @}
7200  */ /* end of group CSI_Peripheral */
7201 
7202 /* ----------------------------------------------------------------------------
7203    -- DCIC Peripheral Access Layer
7204    ---------------------------------------------------------------------------- */
7205 
7206 /*!
7207  * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer
7208  * @{
7209  */
7210 
7211 /** DCIC - Register Layout Typedef */
7212 typedef struct {
7213   __IO  uint32_t DCICC;                                  /**< DCIC Control Register, offset: 0x0 */
7214   __IO  uint32_t DCICIC;                                 /**< DCIC Interrupt Control Register, offset: 0x4 */
7215   __IO  uint32_t DCICS;                                  /**< DCIC Status Register, offset: 0x8 */
7216   uint8_t RESERVED_0[4];
7217   __IO  uint32_t DCICRC;                                 /**< DCIC ROI Config Register m, offset: 0x10 */
7218   __IO  uint32_t DCICRS;                                 /**< DCIC ROI Size Register m, offset: 0x14 */
7219   __IO  uint32_t DCICRRS;                                /**< DCIC ROI Reference Signature Register m, offset: 0x18 */
7220   __I   uint32_t DCICRCS;                                /**< DCIC ROI Calculated Signature m, offset: 0x1C */
7221 } DCIC_Type, *DCIC_MemMapPtr;
7222 
7223 /* ----------------------------------------------------------------------------
7224    -- DCIC - Register accessor macros
7225    ---------------------------------------------------------------------------- */
7226 
7227 /*!
7228  * @addtogroup DCIC_Register_Accessor_Macros DCIC - Register accessor macros
7229  * @{
7230  */
7231 
7232 /* DCIC - Register accessors */
7233 #define DCIC_DCICC_REG(base)                     ((base)->DCICC)
7234 #define DCIC_DCICIC_REG(base)                    ((base)->DCICIC)
7235 #define DCIC_DCICS_REG(base)                     ((base)->DCICS)
7236 #define DCIC_DCICRC_REG(base)                    ((base)->DCICRC)
7237 #define DCIC_DCICRS_REG(base)                    ((base)->DCICRS)
7238 #define DCIC_DCICRRS_REG(base)                   ((base)->DCICRRS)
7239 #define DCIC_DCICRCS_REG(base)                   ((base)->DCICRCS)
7240 
7241 /*!
7242  * @}
7243  */ /* end of group DCIC_Register_Accessor_Macros */
7244 
7245 /* ----------------------------------------------------------------------------
7246    -- DCIC Register Masks
7247    ---------------------------------------------------------------------------- */
7248 
7249 /*!
7250  * @addtogroup DCIC_Register_Masks DCIC Register Masks
7251  * @{
7252  */
7253 
7254 /* DCICC Bit Fields */
7255 #define DCIC_DCICC_IC_EN_MASK                    0x1u
7256 #define DCIC_DCICC_IC_EN_SHIFT                   0
7257 #define DCIC_DCICC_DE_POL_MASK                   0x10u
7258 #define DCIC_DCICC_DE_POL_SHIFT                  4
7259 #define DCIC_DCICC_HSYNC_POL_MASK                0x20u
7260 #define DCIC_DCICC_HSYNC_POL_SHIFT               5
7261 #define DCIC_DCICC_VSYNC_POL_MASK                0x40u
7262 #define DCIC_DCICC_VSYNC_POL_SHIFT               6
7263 #define DCIC_DCICC_CLK_POL_MASK                  0x80u
7264 #define DCIC_DCICC_CLK_POL_SHIFT                 7
7265 /* DCICIC Bit Fields */
7266 #define DCIC_DCICIC_EI_MASK_MASK                 0x1u
7267 #define DCIC_DCICIC_EI_MASK_SHIFT                0
7268 #define DCIC_DCICIC_FI_MASK_MASK                 0x2u
7269 #define DCIC_DCICIC_FI_MASK_SHIFT                1
7270 #define DCIC_DCICIC_FREEZE_MASK_MASK             0x8u
7271 #define DCIC_DCICIC_FREEZE_MASK_SHIFT            3
7272 #define DCIC_DCICIC_EXT_SIG_EN_MASK              0x10000u
7273 #define DCIC_DCICIC_EXT_SIG_EN_SHIFT             16
7274 /* DCICS Bit Fields */
7275 #define DCIC_DCICS_ROI_MATCH_STAT_MASK           0xFFFFu
7276 #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT          0
7277 #define DCIC_DCICS_ROI_MATCH_STAT(x)             (((uint32_t)(((uint32_t)(x))<<DCIC_DCICS_ROI_MATCH_STAT_SHIFT))&DCIC_DCICS_ROI_MATCH_STAT_MASK)
7278 #define DCIC_DCICS_EI_STAT_MASK                  0x10000u
7279 #define DCIC_DCICS_EI_STAT_SHIFT                 16
7280 #define DCIC_DCICS_FI_STAT_MASK                  0x20000u
7281 #define DCIC_DCICS_FI_STAT_SHIFT                 17
7282 /* DCICRC Bit Fields */
7283 #define DCIC_DCICRC_START_OFFSET_X_MASK          0x1FFFu
7284 #define DCIC_DCICRC_START_OFFSET_X_SHIFT         0
7285 #define DCIC_DCICRC_START_OFFSET_X(x)            (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRC_START_OFFSET_X_SHIFT))&DCIC_DCICRC_START_OFFSET_X_MASK)
7286 #define DCIC_DCICRC_START_OFFSET_Y_MASK          0xFFF0000u
7287 #define DCIC_DCICRC_START_OFFSET_Y_SHIFT         16
7288 #define DCIC_DCICRC_START_OFFSET_Y(x)            (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRC_START_OFFSET_Y_SHIFT))&DCIC_DCICRC_START_OFFSET_Y_MASK)
7289 #define DCIC_DCICRC_ROI_FREEZE_MASK              0x40000000u
7290 #define DCIC_DCICRC_ROI_FREEZE_SHIFT             30
7291 #define DCIC_DCICRC_ROI_EN_MASK                  0x80000000u
7292 #define DCIC_DCICRC_ROI_EN_SHIFT                 31
7293 /* DCICRS Bit Fields */
7294 #define DCIC_DCICRS_END_OFFSET_X_MASK            0x1FFFu
7295 #define DCIC_DCICRS_END_OFFSET_X_SHIFT           0
7296 #define DCIC_DCICRS_END_OFFSET_X(x)              (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRS_END_OFFSET_X_SHIFT))&DCIC_DCICRS_END_OFFSET_X_MASK)
7297 #define DCIC_DCICRS_END_OFFSET_Y_MASK            0xFFF0000u
7298 #define DCIC_DCICRS_END_OFFSET_Y_SHIFT           16
7299 #define DCIC_DCICRS_END_OFFSET_Y(x)              (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRS_END_OFFSET_Y_SHIFT))&DCIC_DCICRS_END_OFFSET_Y_MASK)
7300 /* DCICRRS Bit Fields */
7301 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK    0xFFFFFFFFu
7302 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT   0
7303 #define DCIC_DCICRRS_REFERENCE_SIGNATURE(x)      (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT))&DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
7304 /* DCICRCS Bit Fields */
7305 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK   0xFFFFFFFFu
7306 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT  0
7307 #define DCIC_DCICRCS_CALCULATED_SIGNATURE(x)     (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT))&DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
7308 
7309 /*!
7310  * @}
7311  */ /* end of group DCIC_Register_Masks */
7312 
7313 /* DCIC - Peripheral instance base addresses */
7314 /** Peripheral DCIC1 base address */
7315 #define DCIC1_BASE                               (0x4220C000u)
7316 /** Peripheral DCIC1 base pointer */
7317 #define DCIC1                                    ((DCIC_Type *)DCIC1_BASE)
7318 #define DCIC1_BASE_PTR                           (DCIC1)
7319 /** Peripheral DCIC2 base address */
7320 #define DCIC2_BASE                               (0x42210000u)
7321 /** Peripheral DCIC2 base pointer */
7322 #define DCIC2                                    ((DCIC_Type *)DCIC2_BASE)
7323 #define DCIC2_BASE_PTR                           (DCIC2)
7324 /** Array initializer of DCIC peripheral base addresses */
7325 #define DCIC_BASE_ADDRS                          { DCIC1_BASE, DCIC2_BASE }
7326 /** Array initializer of DCIC peripheral base pointers */
7327 #define DCIC_BASE_PTRS                           { DCIC1, DCIC2 }
7328 /** Interrupt vectors for the DCIC peripheral type */
7329 #define DCIC_IRQS                                { DCIC1_IRQn, DCIC2_IRQn }
7330 /* ----------------------------------------------------------------------------
7331    -- DCIC - Register accessor macros
7332    ---------------------------------------------------------------------------- */
7333 
7334 /*!
7335  * @addtogroup DCIC_Register_Accessor_Macros DCIC - Register accessor macros
7336  * @{
7337  */
7338 
7339 /* DCIC - Register instance definitions */
7340 /* DCIC1 */
7341 #define DCIC1_DCICC                              DCIC_DCICC_REG(DCIC1_BASE_PTR)
7342 #define DCIC1_DCICIC                             DCIC_DCICIC_REG(DCIC1_BASE_PTR)
7343 #define DCIC1_DCICS                              DCIC_DCICS_REG(DCIC1_BASE_PTR)
7344 #define DCIC1_DCICRC                             DCIC_DCICRC_REG(DCIC1_BASE_PTR)
7345 #define DCIC1_DCICRS                             DCIC_DCICRS_REG(DCIC1_BASE_PTR)
7346 #define DCIC1_DCICRRS                            DCIC_DCICRRS_REG(DCIC1_BASE_PTR)
7347 #define DCIC1_DCICRCS                            DCIC_DCICRCS_REG(DCIC1_BASE_PTR)
7348 /* DCIC2 */
7349 #define DCIC2_DCICC                              DCIC_DCICC_REG(DCIC2_BASE_PTR)
7350 #define DCIC2_DCICIC                             DCIC_DCICIC_REG(DCIC2_BASE_PTR)
7351 #define DCIC2_DCICS                              DCIC_DCICS_REG(DCIC2_BASE_PTR)
7352 #define DCIC2_DCICRC                             DCIC_DCICRC_REG(DCIC2_BASE_PTR)
7353 #define DCIC2_DCICRS                             DCIC_DCICRS_REG(DCIC2_BASE_PTR)
7354 #define DCIC2_DCICRRS                            DCIC_DCICRRS_REG(DCIC2_BASE_PTR)
7355 #define DCIC2_DCICRCS                            DCIC_DCICRCS_REG(DCIC2_BASE_PTR)
7356 
7357 /*!
7358  * @}
7359  */ /* end of group DCIC_Register_Accessor_Macros */
7360 
7361 /*!
7362  * @}
7363  */ /* end of group DCIC_Peripheral */
7364 
7365 /* ----------------------------------------------------------------------------
7366    -- DVFSC Peripheral Access Layer
7367    ---------------------------------------------------------------------------- */
7368 
7369 /*!
7370  * @addtogroup DVFSC_Peripheral_Access_Layer DVFSC Peripheral Access Layer
7371  * @{
7372  */
7373 
7374 /** DVFSC - Register Layout Typedef */
7375 typedef struct {
7376   __IO  uint32_t THRS;                                   /**< DVFS Thresholds, offset: 0x0 */
7377   __IO  uint32_t COUN;                                   /**< DVFS Counters thresholds, offset: 0x4 */
7378   __IO  uint32_t SIG1;                                   /**< DVFS general purpose bits weight, offset: 0x8 */
7379   __IO  uint32_t DVFSSIG0;                               /**< DVFS general purpose bits weight, offset: 0xC */
7380   __IO  uint32_t DVFSGPC0;                               /**< DVFS general purpose bit 0 weight counter, offset: 0x10 */
7381   __IO  uint32_t DVFSGPC1;                               /**< DVFS general purpose bit 1 weight counter, offset: 0x14 */
7382   __IO  uint32_t DVFSGPBT;                               /**< DVFS general purpose bits enables, offset: 0x18 */
7383   __IO  uint32_t DVFSEMAC;                               /**< DVFS EMAC settings, offset: 0x1C */
7384   __IO  uint32_t CNTR;                                   /**< DVFS Control, offset: 0x20 */
7385   __I   uint32_t DVFSLTR0_0;                             /**< DVFS Load Tracking Register 0, portion 0, offset: 0x24 */
7386   __I   uint32_t DVFSLTR0_1;                             /**< DVFS Load Tracking Register 0, portion 1, offset: 0x28 */
7387   __I   uint32_t DVFSLTR1_0;                             /**< DVFS Load Tracking Register 1, portion 0, offset: 0x2C */
7388   __I   uint32_t DVFSLTR1_1;                             /**< DVFS Load Tracking Register 3, portion 1, offset: 0x30 */
7389   __IO  uint32_t DVFSPT0;                                /**< DVFS pattern 0 length, offset: 0x34 */
7390   __IO  uint32_t DVFSPT1;                                /**< DVFS pattern 1 length, offset: 0x38 */
7391   __IO  uint32_t DVFSPT2;                                /**< DVFS pattern 2 length, offset: 0x3C */
7392   __IO  uint32_t DVFSPT3;                                /**< DVFS pattern 3 length, offset: 0x40 */
7393 } DVFSC_Type, *DVFSC_MemMapPtr;
7394 
7395 /* ----------------------------------------------------------------------------
7396    -- DVFSC - Register accessor macros
7397    ---------------------------------------------------------------------------- */
7398 
7399 /*!
7400  * @addtogroup DVFSC_Register_Accessor_Macros DVFSC - Register accessor macros
7401  * @{
7402  */
7403 
7404 /* DVFSC - Register accessors */
7405 #define DVFSC_THRS_REG(base)                     ((base)->THRS)
7406 #define DVFSC_COUN_REG(base)                     ((base)->COUN)
7407 #define DVFSC_SIG1_REG(base)                     ((base)->SIG1)
7408 #define DVFSC_DVFSSIG0_REG(base)                 ((base)->DVFSSIG0)
7409 #define DVFSC_DVFSGPC0_REG(base)                 ((base)->DVFSGPC0)
7410 #define DVFSC_DVFSGPC1_REG(base)                 ((base)->DVFSGPC1)
7411 #define DVFSC_DVFSGPBT_REG(base)                 ((base)->DVFSGPBT)
7412 #define DVFSC_DVFSEMAC_REG(base)                 ((base)->DVFSEMAC)
7413 #define DVFSC_CNTR_REG(base)                     ((base)->CNTR)
7414 #define DVFSC_DVFSLTR0_0_REG(base)               ((base)->DVFSLTR0_0)
7415 #define DVFSC_DVFSLTR0_1_REG(base)               ((base)->DVFSLTR0_1)
7416 #define DVFSC_DVFSLTR1_0_REG(base)               ((base)->DVFSLTR1_0)
7417 #define DVFSC_DVFSLTR1_1_REG(base)               ((base)->DVFSLTR1_1)
7418 #define DVFSC_DVFSPT0_REG(base)                  ((base)->DVFSPT0)
7419 #define DVFSC_DVFSPT1_REG(base)                  ((base)->DVFSPT1)
7420 #define DVFSC_DVFSPT2_REG(base)                  ((base)->DVFSPT2)
7421 #define DVFSC_DVFSPT3_REG(base)                  ((base)->DVFSPT3)
7422 
7423 /*!
7424  * @}
7425  */ /* end of group DVFSC_Register_Accessor_Macros */
7426 /* ----------------------------------------------------------------------------
7427    -- DVFSC Register Masks
7428    ---------------------------------------------------------------------------- */
7429 
7430 /*!
7431  * @addtogroup DVFSC_Register_Masks DVFSC Register Masks
7432  * @{
7433  */
7434 
7435 /* THRS Bit Fields */
7436 #define DVFSC_THRS_PNCTHR_MASK                   0x3Fu
7437 #define DVFSC_THRS_PNCTHR_SHIFT                  0
7438 #define DVFSC_THRS_PNCTHR(x)                     (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_PNCTHR_SHIFT))&DVFSC_THRS_PNCTHR_MASK)
7439 #define DVFSC_THRS_DWTHR_MASK                    0x3F0000u
7440 #define DVFSC_THRS_DWTHR_SHIFT                   16
7441 #define DVFSC_THRS_DWTHR(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_DWTHR_SHIFT))&DVFSC_THRS_DWTHR_MASK)
7442 #define DVFSC_THRS_UPTHR_MASK                    0xFC00000u
7443 #define DVFSC_THRS_UPTHR_SHIFT                   22
7444 #define DVFSC_THRS_UPTHR(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_UPTHR_SHIFT))&DVFSC_THRS_UPTHR_MASK)
7445 /* COUN Bit Fields */
7446 #define DVFSC_COUN_UPCNT_MASK                    0xFFu
7447 #define DVFSC_COUN_UPCNT_SHIFT                   0
7448 #define DVFSC_COUN_UPCNT(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_COUN_UPCNT_SHIFT))&DVFSC_COUN_UPCNT_MASK)
7449 #define DVFSC_COUN_DN_CNT_MASK                   0xFF0000u
7450 #define DVFSC_COUN_DN_CNT_SHIFT                  16
7451 #define DVFSC_COUN_DN_CNT(x)                     (((uint32_t)(((uint32_t)(x))<<DVFSC_COUN_DN_CNT_SHIFT))&DVFSC_COUN_DN_CNT_MASK)
7452 /* SIG1 Bit Fields */
7453 #define DVFSC_SIG1_WSW6_MASK                     0x1Cu
7454 #define DVFSC_SIG1_WSW6_SHIFT                    2
7455 #define DVFSC_SIG1_WSW6(x)                       (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW6_SHIFT))&DVFSC_SIG1_WSW6_MASK)
7456 #define DVFSC_SIG1_WSW7_MASK                     0xE0u
7457 #define DVFSC_SIG1_WSW7_SHIFT                    5
7458 #define DVFSC_SIG1_WSW7(x)                       (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW7_SHIFT))&DVFSC_SIG1_WSW7_MASK)
7459 #define DVFSC_SIG1_WSW8_MASK                     0x700u
7460 #define DVFSC_SIG1_WSW8_SHIFT                    8
7461 #define DVFSC_SIG1_WSW8(x)                       (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW8_SHIFT))&DVFSC_SIG1_WSW8_MASK)
7462 #define DVFSC_SIG1_WSW9_MASK                     0x3800u
7463 #define DVFSC_SIG1_WSW9_SHIFT                    11
7464 #define DVFSC_SIG1_WSW9(x)                       (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW9_SHIFT))&DVFSC_SIG1_WSW9_MASK)
7465 #define DVFSC_SIG1_WSW10_MASK                    0x1C000u
7466 #define DVFSC_SIG1_WSW10_SHIFT                   14
7467 #define DVFSC_SIG1_WSW10(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW10_SHIFT))&DVFSC_SIG1_WSW10_MASK)
7468 #define DVFSC_SIG1_WSW11_MASK                    0xE0000u
7469 #define DVFSC_SIG1_WSW11_SHIFT                   17
7470 #define DVFSC_SIG1_WSW11(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW11_SHIFT))&DVFSC_SIG1_WSW11_MASK)
7471 #define DVFSC_SIG1_WSW12_MASK                    0x700000u
7472 #define DVFSC_SIG1_WSW12_SHIFT                   20
7473 #define DVFSC_SIG1_WSW12(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW12_SHIFT))&DVFSC_SIG1_WSW12_MASK)
7474 #define DVFSC_SIG1_WSW13_MASK                    0x3800000u
7475 #define DVFSC_SIG1_WSW13_SHIFT                   23
7476 #define DVFSC_SIG1_WSW13(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW13_SHIFT))&DVFSC_SIG1_WSW13_MASK)
7477 #define DVFSC_SIG1_WSW14_MASK                    0x1C000000u
7478 #define DVFSC_SIG1_WSW14_SHIFT                   26
7479 #define DVFSC_SIG1_WSW14(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW14_SHIFT))&DVFSC_SIG1_WSW14_MASK)
7480 #define DVFSC_SIG1_WSW15_MASK                    0xE0000000u
7481 #define DVFSC_SIG1_WSW15_SHIFT                   29
7482 #define DVFSC_SIG1_WSW15(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW15_SHIFT))&DVFSC_SIG1_WSW15_MASK)
7483 /* DVFSSIG0 Bit Fields */
7484 #define DVFSC_DVFSSIG0_WSW0_MASK                 0x3Fu
7485 #define DVFSC_DVFSSIG0_WSW0_SHIFT                0
7486 #define DVFSC_DVFSSIG0_WSW0(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW0_SHIFT))&DVFSC_DVFSSIG0_WSW0_MASK)
7487 #define DVFSC_DVFSSIG0_WSW1_MASK                 0xFC0u
7488 #define DVFSC_DVFSSIG0_WSW1_SHIFT                6
7489 #define DVFSC_DVFSSIG0_WSW1(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW1_SHIFT))&DVFSC_DVFSSIG0_WSW1_MASK)
7490 #define DVFSC_DVFSSIG0_WSW2_MASK                 0x700000u
7491 #define DVFSC_DVFSSIG0_WSW2_SHIFT                20
7492 #define DVFSC_DVFSSIG0_WSW2(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW2_SHIFT))&DVFSC_DVFSSIG0_WSW2_MASK)
7493 #define DVFSC_DVFSSIG0_WSW3_MASK                 0x3800000u
7494 #define DVFSC_DVFSSIG0_WSW3_SHIFT                23
7495 #define DVFSC_DVFSSIG0_WSW3(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW3_SHIFT))&DVFSC_DVFSSIG0_WSW3_MASK)
7496 #define DVFSC_DVFSSIG0_WSW4_MASK                 0x1C000000u
7497 #define DVFSC_DVFSSIG0_WSW4_SHIFT                26
7498 #define DVFSC_DVFSSIG0_WSW4(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW4_SHIFT))&DVFSC_DVFSSIG0_WSW4_MASK)
7499 #define DVFSC_DVFSSIG0_WSW5_MASK                 0xE0000000u
7500 #define DVFSC_DVFSSIG0_WSW5_SHIFT                29
7501 #define DVFSC_DVFSSIG0_WSW5(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW5_SHIFT))&DVFSC_DVFSSIG0_WSW5_MASK)
7502 /* DVFSGPC0 Bit Fields */
7503 #define DVFSC_DVFSGPC0_GPBC0_MASK                0x1FFFFu
7504 #define DVFSC_DVFSGPC0_GPBC0_SHIFT               0
7505 #define DVFSC_DVFSGPC0_GPBC0(x)                  (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSGPC0_GPBC0_SHIFT))&DVFSC_DVFSGPC0_GPBC0_MASK)
7506 #define DVFSC_DVFSGPC0_C0ACT_MASK                0x40000000u
7507 #define DVFSC_DVFSGPC0_C0ACT_SHIFT               30
7508 #define DVFSC_DVFSGPC0_C0STRT_MASK               0x80000000u
7509 #define DVFSC_DVFSGPC0_C0STRT_SHIFT              31
7510 /* DVFSGPC1 Bit Fields */
7511 #define DVFSC_DVFSGPC1_GPBC1_MASK                0x1FFFFu
7512 #define DVFSC_DVFSGPC1_GPBC1_SHIFT               0
7513 #define DVFSC_DVFSGPC1_GPBC1(x)                  (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSGPC1_GPBC1_SHIFT))&DVFSC_DVFSGPC1_GPBC1_MASK)
7514 #define DVFSC_DVFSGPC1_C1ACT_MASK                0x40000000u
7515 #define DVFSC_DVFSGPC1_C1ACT_SHIFT               30
7516 #define DVFSC_DVFSGPC1_C1STRT_MASK               0x80000000u
7517 #define DVFSC_DVFSGPC1_C1STRT_SHIFT              31
7518 /* DVFSGPBT Bit Fields */
7519 #define DVFSC_DVFSGPBT_GPB0_MASK                 0x1u
7520 #define DVFSC_DVFSGPBT_GPB0_SHIFT                0
7521 #define DVFSC_DVFSGPBT_GPB1_MASK                 0x2u
7522 #define DVFSC_DVFSGPBT_GPB1_SHIFT                1
7523 #define DVFSC_DVFSGPBT_GPB2_MASK                 0x4u
7524 #define DVFSC_DVFSGPBT_GPB2_SHIFT                2
7525 #define DVFSC_DVFSGPBT_GPB3_MASK                 0x8u
7526 #define DVFSC_DVFSGPBT_GPB3_SHIFT                3
7527 #define DVFSC_DVFSGPBT_GPB4_MASK                 0x10u
7528 #define DVFSC_DVFSGPBT_GPB4_SHIFT                4
7529 #define DVFSC_DVFSGPBT_GPB5_MASK                 0x20u
7530 #define DVFSC_DVFSGPBT_GPB5_SHIFT                5
7531 #define DVFSC_DVFSGPBT_GPB6_MASK                 0x40u
7532 #define DVFSC_DVFSGPBT_GPB6_SHIFT                6
7533 #define DVFSC_DVFSGPBT_GPB7_MASK                 0x80u
7534 #define DVFSC_DVFSGPBT_GPB7_SHIFT                7
7535 #define DVFSC_DVFSGPBT_GPB8_MASK                 0x100u
7536 #define DVFSC_DVFSGPBT_GPB8_SHIFT                8
7537 #define DVFSC_DVFSGPBT_GPB9_MASK                 0x200u
7538 #define DVFSC_DVFSGPBT_GPB9_SHIFT                9
7539 #define DVFSC_DVFSGPBT_GPB10_MASK                0x400u
7540 #define DVFSC_DVFSGPBT_GPB10_SHIFT               10
7541 #define DVFSC_DVFSGPBT_GPB11_MASK                0x800u
7542 #define DVFSC_DVFSGPBT_GPB11_SHIFT               11
7543 #define DVFSC_DVFSGPBT_GPB12_MASK                0x1000u
7544 #define DVFSC_DVFSGPBT_GPB12_SHIFT               12
7545 #define DVFSC_DVFSGPBT_GPB13_MASK                0x2000u
7546 #define DVFSC_DVFSGPBT_GPB13_SHIFT               13
7547 #define DVFSC_DVFSGPBT_GPB14_MASK                0x4000u
7548 #define DVFSC_DVFSGPBT_GPB14_SHIFT               14
7549 #define DVFSC_DVFSGPBT_GPB15_MASK                0x8000u
7550 #define DVFSC_DVFSGPBT_GPB15_SHIFT               15
7551 /* DVFSEMAC Bit Fields */
7552 #define DVFSC_DVFSEMAC_EMAC_MASK                 0x1FFu
7553 #define DVFSC_DVFSEMAC_EMAC_SHIFT                0
7554 #define DVFSC_DVFSEMAC_EMAC(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSEMAC_EMAC_SHIFT))&DVFSC_DVFSEMAC_EMAC_MASK)
7555 #define DVFSC_DVFSEMAC_DVFEN0_MASK               0x200u
7556 #define DVFSC_DVFSEMAC_DVFEN0_SHIFT              9
7557 #define DVFSC_DVFSEMAC_FSVAI0_MASK               0x30000u
7558 #define DVFSC_DVFSEMAC_FSVAI0_SHIFT              16
7559 #define DVFSC_DVFSEMAC_FSVAI0(x)                 (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSEMAC_FSVAI0_SHIFT))&DVFSC_DVFSEMAC_FSVAI0_MASK)
7560 #define DVFSC_DVFSEMAC_WFIM0_MASK                0x1000000u
7561 #define DVFSC_DVFSEMAC_WFIM0_SHIFT               24
7562 /* CNTR Bit Fields */
7563 #define DVFSC_CNTR_LTBRSR_MASK                   0x18u
7564 #define DVFSC_CNTR_LTBRSR_SHIFT                  3
7565 #define DVFSC_CNTR_LTBRSR(x)                     (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_LTBRSR_SHIFT))&DVFSC_CNTR_LTBRSR_MASK)
7566 #define DVFSC_CNTR_LTBRSH_MASK                   0x20u
7567 #define DVFSC_CNTR_LTBRSH_SHIFT                  5
7568 #define DVFSC_CNTR_PFUS_MASK                     0x1C0u
7569 #define DVFSC_CNTR_PFUS_SHIFT                    6
7570 #define DVFSC_CNTR_PFUS(x)                       (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_PFUS_SHIFT))&DVFSC_CNTR_PFUS_MASK)
7571 #define DVFSC_CNTR_PFUE_MASK                     0x200u
7572 #define DVFSC_CNTR_PFUE_SHIFT                    9
7573 #define DVFSC_CNTR_DIV_RATIO_MASK                0x1F800u
7574 #define DVFSC_CNTR_DIV_RATIO_SHIFT               11
7575 #define DVFSC_CNTR_DIV_RATIO(x)                  (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_DIV_RATIO_SHIFT))&DVFSC_CNTR_DIV_RATIO_MASK)
7576 #define DVFSC_CNTR_MINF_MASK                     0x20000u
7577 #define DVFSC_CNTR_MINF_SHIFT                    17
7578 #define DVFSC_CNTR_MAXF_MASK                     0x40000u
7579 #define DVFSC_CNTR_MAXF_SHIFT                    18
7580 #define DVFSC_CNTR_FSVAI_MASK                    0x300000u
7581 #define DVFSC_CNTR_FSVAI_SHIFT                   20
7582 #define DVFSC_CNTR_FSVAI(x)                      (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_FSVAI_SHIFT))&DVFSC_CNTR_FSVAI_MASK)
7583 #define DVFSC_CNTR_FSVAIM_MASK                   0x400000u
7584 #define DVFSC_CNTR_FSVAIM_SHIFT                  22
7585 #define DVFSC_CNTR_PIRQS_MASK                    0x800000u
7586 #define DVFSC_CNTR_PIRQS_SHIFT                   23
7587 #define DVFSC_CNTR_DVFIS_MASK                    0x1000000u
7588 #define DVFSC_CNTR_DVFIS_SHIFT                   24
7589 #define DVFSC_CNTR_LBFL0_MASK                    0x2000000u
7590 #define DVFSC_CNTR_LBFL0_SHIFT                   25
7591 #define DVFSC_CNTR_LBFL1_MASK                    0x4000000u
7592 #define DVFSC_CNTR_LBFL1_SHIFT                   26
7593 #define DVFSC_CNTR_LBMI_MASK                     0x8000000u
7594 #define DVFSC_CNTR_LBMI_SHIFT                    27
7595 #define DVFSC_CNTR_DVFEV_MASK                    0x10000000u
7596 #define DVFSC_CNTR_DVFEV_SHIFT                   28
7597 #define DVFSC_CNTR_DIV3CK_MASK                   0xE0000000u
7598 #define DVFSC_CNTR_DIV3CK_SHIFT                  29
7599 #define DVFSC_CNTR_DIV3CK(x)                     (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_DIV3CK_SHIFT))&DVFSC_CNTR_DIV3CK_MASK)
7600 /* DVFSLTR0_0 Bit Fields */
7601 #define DVFSC_DVFSLTR0_0_LTS0_0_MASK             0xFu
7602 #define DVFSC_DVFSLTR0_0_LTS0_0_SHIFT            0
7603 #define DVFSC_DVFSLTR0_0_LTS0_0(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_0_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_0_MASK)
7604 #define DVFSC_DVFSLTR0_0_LTS0_1_MASK             0xF0u
7605 #define DVFSC_DVFSLTR0_0_LTS0_1_SHIFT            4
7606 #define DVFSC_DVFSLTR0_0_LTS0_1(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_1_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_1_MASK)
7607 #define DVFSC_DVFSLTR0_0_LTS0_2_MASK             0xF00u
7608 #define DVFSC_DVFSLTR0_0_LTS0_2_SHIFT            8
7609 #define DVFSC_DVFSLTR0_0_LTS0_2(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_2_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_2_MASK)
7610 #define DVFSC_DVFSLTR0_0_LTS0_3_MASK             0xF000u
7611 #define DVFSC_DVFSLTR0_0_LTS0_3_SHIFT            12
7612 #define DVFSC_DVFSLTR0_0_LTS0_3(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_3_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_3_MASK)
7613 #define DVFSC_DVFSLTR0_0_LTS0_4_MASK             0xF0000u
7614 #define DVFSC_DVFSLTR0_0_LTS0_4_SHIFT            16
7615 #define DVFSC_DVFSLTR0_0_LTS0_4(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_4_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_4_MASK)
7616 #define DVFSC_DVFSLTR0_0_LTS0_5_MASK             0xF00000u
7617 #define DVFSC_DVFSLTR0_0_LTS0_5_SHIFT            20
7618 #define DVFSC_DVFSLTR0_0_LTS0_5(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_5_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_5_MASK)
7619 #define DVFSC_DVFSLTR0_0_LTS0_6_MASK             0xF000000u
7620 #define DVFSC_DVFSLTR0_0_LTS0_6_SHIFT            24
7621 #define DVFSC_DVFSLTR0_0_LTS0_6(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_6_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_6_MASK)
7622 #define DVFSC_DVFSLTR0_0_LTS0_7_MASK             0xF0000000u
7623 #define DVFSC_DVFSLTR0_0_LTS0_7_SHIFT            28
7624 #define DVFSC_DVFSLTR0_0_LTS0_7(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_7_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_7_MASK)
7625 /* DVFSLTR0_1 Bit Fields */
7626 #define DVFSC_DVFSLTR0_1_LTS0_8_MASK             0xFu
7627 #define DVFSC_DVFSLTR0_1_LTS0_8_SHIFT            0
7628 #define DVFSC_DVFSLTR0_1_LTS0_8(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_8_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_8_MASK)
7629 #define DVFSC_DVFSLTR0_1_LTS0_9_MASK             0xF0u
7630 #define DVFSC_DVFSLTR0_1_LTS0_9_SHIFT            4
7631 #define DVFSC_DVFSLTR0_1_LTS0_9(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_9_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_9_MASK)
7632 #define DVFSC_DVFSLTR0_1_LTS0_10_MASK            0xF00u
7633 #define DVFSC_DVFSLTR0_1_LTS0_10_SHIFT           8
7634 #define DVFSC_DVFSLTR0_1_LTS0_10(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_10_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_10_MASK)
7635 #define DVFSC_DVFSLTR0_1_LTS0_11_MASK            0xF000u
7636 #define DVFSC_DVFSLTR0_1_LTS0_11_SHIFT           12
7637 #define DVFSC_DVFSLTR0_1_LTS0_11(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_11_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_11_MASK)
7638 #define DVFSC_DVFSLTR0_1_LTS0_12_MASK            0xF0000u
7639 #define DVFSC_DVFSLTR0_1_LTS0_12_SHIFT           16
7640 #define DVFSC_DVFSLTR0_1_LTS0_12(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_12_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_12_MASK)
7641 #define DVFSC_DVFSLTR0_1_LTS0_13_MASK            0xF00000u
7642 #define DVFSC_DVFSLTR0_1_LTS0_13_SHIFT           20
7643 #define DVFSC_DVFSLTR0_1_LTS0_13(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_13_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_13_MASK)
7644 #define DVFSC_DVFSLTR0_1_LTS0_14_MASK            0xF000000u
7645 #define DVFSC_DVFSLTR0_1_LTS0_14_SHIFT           24
7646 #define DVFSC_DVFSLTR0_1_LTS0_14(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_14_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_14_MASK)
7647 #define DVFSC_DVFSLTR0_1_LTS0_15_MASK            0xF0000000u
7648 #define DVFSC_DVFSLTR0_1_LTS0_15_SHIFT           28
7649 #define DVFSC_DVFSLTR0_1_LTS0_15(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_15_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_15_MASK)
7650 /* DVFSLTR1_0 Bit Fields */
7651 #define DVFSC_DVFSLTR1_0_LTS1_0_MASK             0xFu
7652 #define DVFSC_DVFSLTR1_0_LTS1_0_SHIFT            0
7653 #define DVFSC_DVFSLTR1_0_LTS1_0(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_0_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_0_MASK)
7654 #define DVFSC_DVFSLTR1_0_LTS1_1_MASK             0xF0u
7655 #define DVFSC_DVFSLTR1_0_LTS1_1_SHIFT            4
7656 #define DVFSC_DVFSLTR1_0_LTS1_1(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_1_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_1_MASK)
7657 #define DVFSC_DVFSLTR1_0_LTS1_2_MASK             0xF00u
7658 #define DVFSC_DVFSLTR1_0_LTS1_2_SHIFT            8
7659 #define DVFSC_DVFSLTR1_0_LTS1_2(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_2_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_2_MASK)
7660 #define DVFSC_DVFSLTR1_0_LTS1_3_MASK             0xF000u
7661 #define DVFSC_DVFSLTR1_0_LTS1_3_SHIFT            12
7662 #define DVFSC_DVFSLTR1_0_LTS1_3(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_3_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_3_MASK)
7663 #define DVFSC_DVFSLTR1_0_LTS1_4_MASK             0xF0000u
7664 #define DVFSC_DVFSLTR1_0_LTS1_4_SHIFT            16
7665 #define DVFSC_DVFSLTR1_0_LTS1_4(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_4_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_4_MASK)
7666 #define DVFSC_DVFSLTR1_0_LTS1_5_MASK             0xF00000u
7667 #define DVFSC_DVFSLTR1_0_LTS1_5_SHIFT            20
7668 #define DVFSC_DVFSLTR1_0_LTS1_5(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_5_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_5_MASK)
7669 #define DVFSC_DVFSLTR1_0_LTS1_6_MASK             0xF000000u
7670 #define DVFSC_DVFSLTR1_0_LTS1_6_SHIFT            24
7671 #define DVFSC_DVFSLTR1_0_LTS1_6(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_6_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_6_MASK)
7672 #define DVFSC_DVFSLTR1_0_LTS1_7_MASK             0xF0000000u
7673 #define DVFSC_DVFSLTR1_0_LTS1_7_SHIFT            28
7674 #define DVFSC_DVFSLTR1_0_LTS1_7(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_7_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_7_MASK)
7675 /* DVFSLTR1_1 Bit Fields */
7676 #define DVFSC_DVFSLTR1_1_LTS1_8_MASK             0xFu
7677 #define DVFSC_DVFSLTR1_1_LTS1_8_SHIFT            0
7678 #define DVFSC_DVFSLTR1_1_LTS1_8(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_8_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_8_MASK)
7679 #define DVFSC_DVFSLTR1_1_LTS1_9_MASK             0xF0u
7680 #define DVFSC_DVFSLTR1_1_LTS1_9_SHIFT            4
7681 #define DVFSC_DVFSLTR1_1_LTS1_9(x)               (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_9_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_9_MASK)
7682 #define DVFSC_DVFSLTR1_1_LTS1_10_MASK            0xF00u
7683 #define DVFSC_DVFSLTR1_1_LTS1_10_SHIFT           8
7684 #define DVFSC_DVFSLTR1_1_LTS1_10(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_10_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_10_MASK)
7685 #define DVFSC_DVFSLTR1_1_LTS1_11_MASK            0xF000u
7686 #define DVFSC_DVFSLTR1_1_LTS1_11_SHIFT           12
7687 #define DVFSC_DVFSLTR1_1_LTS1_11(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_11_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_11_MASK)
7688 #define DVFSC_DVFSLTR1_1_LTS1_12_MASK            0xF0000u
7689 #define DVFSC_DVFSLTR1_1_LTS1_12_SHIFT           16
7690 #define DVFSC_DVFSLTR1_1_LTS1_12(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_12_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_12_MASK)
7691 #define DVFSC_DVFSLTR1_1_LTS1_13_MASK            0xF00000u
7692 #define DVFSC_DVFSLTR1_1_LTS1_13_SHIFT           20
7693 #define DVFSC_DVFSLTR1_1_LTS1_13(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_13_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_13_MASK)
7694 #define DVFSC_DVFSLTR1_1_LTS1_14_MASK            0xF000000u
7695 #define DVFSC_DVFSLTR1_1_LTS1_14_SHIFT           24
7696 #define DVFSC_DVFSLTR1_1_LTS1_14(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_14_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_14_MASK)
7697 #define DVFSC_DVFSLTR1_1_LTS1_15_MASK            0xF0000000u
7698 #define DVFSC_DVFSLTR1_1_LTS1_15_SHIFT           28
7699 #define DVFSC_DVFSLTR1_1_LTS1_15(x)              (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_15_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_15_MASK)
7700 /* DVFSPT0 Bit Fields */
7701 #define DVFSC_DVFSPT0_FPTN0_MASK                 0x1FFFFu
7702 #define DVFSC_DVFSPT0_FPTN0_SHIFT                0
7703 #define DVFSC_DVFSPT0_FPTN0(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT0_FPTN0_SHIFT))&DVFSC_DVFSPT0_FPTN0_MASK)
7704 #define DVFSC_DVFSPT0_PT0A_MASK                  0x20000u
7705 #define DVFSC_DVFSPT0_PT0A_SHIFT                 17
7706 /* DVFSPT1 Bit Fields */
7707 #define DVFSC_DVFSPT1_FPTN1_MASK                 0x1FFFFu
7708 #define DVFSC_DVFSPT1_FPTN1_SHIFT                0
7709 #define DVFSC_DVFSPT1_FPTN1(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT1_FPTN1_SHIFT))&DVFSC_DVFSPT1_FPTN1_MASK)
7710 #define DVFSC_DVFSPT1_PT1A_MASK                  0x20000u
7711 #define DVFSC_DVFSPT1_PT1A_SHIFT                 17
7712 /* DVFSPT2 Bit Fields */
7713 #define DVFSC_DVFSPT2_FPTN2_MASK                 0x1FFFFu
7714 #define DVFSC_DVFSPT2_FPTN2_SHIFT                0
7715 #define DVFSC_DVFSPT2_FPTN2(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT2_FPTN2_SHIFT))&DVFSC_DVFSPT2_FPTN2_MASK)
7716 #define DVFSC_DVFSPT2_PT2A_MASK                  0x20000u
7717 #define DVFSC_DVFSPT2_PT2A_SHIFT                 17
7718 #define DVFSC_DVFSPT2_P2THR_MASK                 0xFC000000u
7719 #define DVFSC_DVFSPT2_P2THR_SHIFT                26
7720 #define DVFSC_DVFSPT2_P2THR(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT2_P2THR_SHIFT))&DVFSC_DVFSPT2_P2THR_MASK)
7721 /* DVFSPT3 Bit Fields */
7722 #define DVFSC_DVFSPT3_FPTN3_MASK                 0x1FFFFu
7723 #define DVFSC_DVFSPT3_FPTN3_SHIFT                0
7724 #define DVFSC_DVFSPT3_FPTN3(x)                   (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT3_FPTN3_SHIFT))&DVFSC_DVFSPT3_FPTN3_MASK)
7725 #define DVFSC_DVFSPT3_PT3A_MASK                  0x20000u
7726 #define DVFSC_DVFSPT3_PT3A_SHIFT                 17
7727 
7728 /*!
7729  * @}
7730  */ /* end of group DVFSC_Register_Masks */
7731 
7732 /* DVFSC - Peripheral instance base addresses */
7733 /** Peripheral DVFSC base address */
7734 #define DVFSC_BASE                               (0x420DC180u)
7735 /** Peripheral DVFSC base pointer */
7736 #define DVFSC                                    ((DVFSC_Type *)DVFSC_BASE)
7737 #define DVFSC_BASE_PTR                           (DVFSC)
7738 /** Array initializer of DVFSC peripheral base addresses */
7739 #define DVFSC_BASE_ADDRS                         { DVFSC_BASE }
7740 /** Array initializer of DVFSC peripheral base pointers */
7741 #define DVFSC_BASE_PTRS                          { DVFSC }
7742 
7743 /* ----------------------------------------------------------------------------
7744    -- DVFSC - Register accessor macros
7745    ---------------------------------------------------------------------------- */
7746 
7747 /*!
7748  * @addtogroup DVFSC_Register_Accessor_Macros DVFSC - Register accessor macros
7749  * @{
7750  */
7751 
7752 /* DVFSC - Register instance definitions */
7753 /* DVFSC */
7754 #define DVFSC_THRS                               DVFSC_THRS_REG(DVFSC_BASE_PTR)
7755 #define DVFSC_COUN                               DVFSC_COUN_REG(DVFSC_BASE_PTR)
7756 #define DVFSC_SIG1                               DVFSC_SIG1_REG(DVFSC_BASE_PTR)
7757 #define DVFSC_DVFSSIG0                           DVFSC_DVFSSIG0_REG(DVFSC_BASE_PTR)
7758 #define DVFSC_DVFSGPC0                           DVFSC_DVFSGPC0_REG(DVFSC_BASE_PTR)
7759 #define DVFSC_DVFSGPC1                           DVFSC_DVFSGPC1_REG(DVFSC_BASE_PTR)
7760 #define DVFSC_DVFSGPBT                           DVFSC_DVFSGPBT_REG(DVFSC_BASE_PTR)
7761 #define DVFSC_DVFSEMAC                           DVFSC_DVFSEMAC_REG(DVFSC_BASE_PTR)
7762 #define DVFSC_CNTR                               DVFSC_CNTR_REG(DVFSC_BASE_PTR)
7763 #define DVFSC_DVFSLTR0_0                         DVFSC_DVFSLTR0_0_REG(DVFSC_BASE_PTR)
7764 #define DVFSC_DVFSLTR0_1                         DVFSC_DVFSLTR0_1_REG(DVFSC_BASE_PTR)
7765 #define DVFSC_DVFSLTR1_0                         DVFSC_DVFSLTR1_0_REG(DVFSC_BASE_PTR)
7766 #define DVFSC_DVFSLTR1_1                         DVFSC_DVFSLTR1_1_REG(DVFSC_BASE_PTR)
7767 #define DVFSC_DVFSPT0                            DVFSC_DVFSPT0_REG(DVFSC_BASE_PTR)
7768 #define DVFSC_DVFSPT1                            DVFSC_DVFSPT1_REG(DVFSC_BASE_PTR)
7769 #define DVFSC_DVFSPT2                            DVFSC_DVFSPT2_REG(DVFSC_BASE_PTR)
7770 #define DVFSC_DVFSPT3                            DVFSC_DVFSPT3_REG(DVFSC_BASE_PTR)
7771 
7772 /*!
7773  * @}
7774  */ /* end of group DVFSC_Register_Accessor_Macros */
7775 
7776 /*!
7777  * @}
7778  */ /* end of group DVFSC_Peripheral */
7779 
7780 /* ----------------------------------------------------------------------------
7781    -- ECSPI Peripheral Access Layer
7782    ---------------------------------------------------------------------------- */
7783 
7784 /*!
7785  * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
7786  * @{
7787  */
7788 
7789 /** ECSPI - Register Layout Typedef */
7790 typedef struct {
7791   __I   uint32_t RXDATA;                                 /**< Receive Data Register, offset: 0x0 */
7792   __O   uint32_t TXDATA;                                 /**< Transmit Data Register, offset: 0x4 */
7793   __IO  uint32_t CONREG;                                 /**< Control Register, offset: 0x8 */
7794   __IO  uint32_t CONFIGREG;                              /**< Config Register, offset: 0xC */
7795   __IO  uint32_t INTREG;                                 /**< Interrupt Control Register, offset: 0x10 */
7796   __IO  uint32_t DMAREG;                                 /**< DMA Control Register, offset: 0x14 */
7797   __IO  uint32_t STATREG;                                /**< Status Register, offset: 0x18 */
7798   __IO  uint32_t PERIODREG;                              /**< Sample Period Control Register, offset: 0x1C */
7799   __IO  uint32_t TESTREG;                                /**< Test Control Register, offset: 0x20 */
7800   uint8_t RESERVED_0[28];
7801   __O   uint32_t MSGDATA;                                /**< Message Data Register, offset: 0x40 */
7802 } ECSPI_Type, *ECSPI_MemMapPtr;
7803 
7804 /* ----------------------------------------------------------------------------
7805    -- ECSPI - Register accessor macros
7806    ---------------------------------------------------------------------------- */
7807 
7808 /*!
7809  * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros
7810  * @{
7811  */
7812 
7813 /* ECSPI - Register accessors */
7814 #define ECSPI_RXDATA_REG(base)                   ((base)->RXDATA)
7815 #define ECSPI_TXDATA_REG(base)                   ((base)->TXDATA)
7816 #define ECSPI_CONREG_REG(base)                   ((base)->CONREG)
7817 #define ECSPI_CONFIGREG_REG(base)                ((base)->CONFIGREG)
7818 #define ECSPI_INTREG_REG(base)                   ((base)->INTREG)
7819 #define ECSPI_DMAREG_REG(base)                   ((base)->DMAREG)
7820 #define ECSPI_STATREG_REG(base)                  ((base)->STATREG)
7821 #define ECSPI_PERIODREG_REG(base)                ((base)->PERIODREG)
7822 #define ECSPI_TESTREG_REG(base)                  ((base)->TESTREG)
7823 #define ECSPI_MSGDATA_REG(base)                  ((base)->MSGDATA)
7824 
7825 /*!
7826  * @}
7827  */ /* end of group ECSPI_Register_Accessor_Macros */
7828 
7829 /* ----------------------------------------------------------------------------
7830    -- ECSPI Register Masks
7831    ---------------------------------------------------------------------------- */
7832 
7833 /*!
7834  * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
7835  * @{
7836  */
7837 
7838 /* RXDATA Bit Fields */
7839 #define ECSPI_RXDATA_ECSPI_RXDATA_MASK           0xFFFFFFFFu
7840 #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT          0
7841 #define ECSPI_RXDATA_ECSPI_RXDATA(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_RXDATA_ECSPI_RXDATA_SHIFT))&ECSPI_RXDATA_ECSPI_RXDATA_MASK)
7842 /* TXDATA Bit Fields */
7843 #define ECSPI_TXDATA_ECSPI_TXDATA_MASK           0xFFFFFFFFu
7844 #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT          0
7845 #define ECSPI_TXDATA_ECSPI_TXDATA(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_TXDATA_ECSPI_TXDATA_SHIFT))&ECSPI_TXDATA_ECSPI_TXDATA_MASK)
7846 /* CONREG Bit Fields */
7847 #define ECSPI_CONREG_EN_MASK                     0x1u
7848 #define ECSPI_CONREG_EN_SHIFT                    0
7849 #define ECSPI_CONREG_HT_MASK                     0x2u
7850 #define ECSPI_CONREG_HT_SHIFT                    1
7851 #define ECSPI_CONREG_XCH_MASK                    0x4u
7852 #define ECSPI_CONREG_XCH_SHIFT                   2
7853 #define ECSPI_CONREG_SMC_MASK                    0x8u
7854 #define ECSPI_CONREG_SMC_SHIFT                   3
7855 #define ECSPI_CONREG_CHANNEL_MODE_MASK           0xF0u
7856 #define ECSPI_CONREG_CHANNEL_MODE_SHIFT          4
7857 #define ECSPI_CONREG_CHANNEL_MODE(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_MODE_SHIFT))&ECSPI_CONREG_CHANNEL_MODE_MASK)
7858 #define ECSPI_CONREG_POST_DIVIDER_MASK           0xF00u
7859 #define ECSPI_CONREG_POST_DIVIDER_SHIFT          8
7860 #define ECSPI_CONREG_POST_DIVIDER(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_POST_DIVIDER_SHIFT))&ECSPI_CONREG_POST_DIVIDER_MASK)
7861 #define ECSPI_CONREG_PRE_DIVIDER_MASK            0xF000u
7862 #define ECSPI_CONREG_PRE_DIVIDER_SHIFT           12
7863 #define ECSPI_CONREG_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_PRE_DIVIDER_SHIFT))&ECSPI_CONREG_PRE_DIVIDER_MASK)
7864 #define ECSPI_CONREG_DRCTL_MASK                  0x30000u
7865 #define ECSPI_CONREG_DRCTL_SHIFT                 16
7866 #define ECSPI_CONREG_DRCTL(x)                    (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_DRCTL_SHIFT))&ECSPI_CONREG_DRCTL_MASK)
7867 #define ECSPI_CONREG_CHANNEL_SELECT_MASK         0xC0000u
7868 #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT        18
7869 #define ECSPI_CONREG_CHANNEL_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_SELECT_SHIFT))&ECSPI_CONREG_CHANNEL_SELECT_MASK)
7870 #define ECSPI_CONREG_BURST_LENGTH_MASK           0xFFF00000u
7871 #define ECSPI_CONREG_BURST_LENGTH_SHIFT          20
7872 #define ECSPI_CONREG_BURST_LENGTH(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_BURST_LENGTH_SHIFT))&ECSPI_CONREG_BURST_LENGTH_MASK)
7873 /* CONFIGREG Bit Fields */
7874 #define ECSPI_CONFIGREG_SCLK_PHA_MASK            0xFu
7875 #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT           0
7876 #define ECSPI_CONFIGREG_SCLK_PHA(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_PHA_SHIFT))&ECSPI_CONFIGREG_SCLK_PHA_MASK)
7877 #define ECSPI_CONFIGREG_SCLK_POL_MASK            0xF0u
7878 #define ECSPI_CONFIGREG_SCLK_POL_SHIFT           4
7879 #define ECSPI_CONFIGREG_SCLK_POL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_POL_SHIFT))&ECSPI_CONFIGREG_SCLK_POL_MASK)
7880 #define ECSPI_CONFIGREG_SS_CTL_MASK              0xF00u
7881 #define ECSPI_CONFIGREG_SS_CTL_SHIFT             8
7882 #define ECSPI_CONFIGREG_SS_CTL(x)                (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_CTL_SHIFT))&ECSPI_CONFIGREG_SS_CTL_MASK)
7883 #define ECSPI_CONFIGREG_SS_POL_MASK              0xF000u
7884 #define ECSPI_CONFIGREG_SS_POL_SHIFT             12
7885 #define ECSPI_CONFIGREG_SS_POL(x)                (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_POL_SHIFT))&ECSPI_CONFIGREG_SS_POL_MASK)
7886 #define ECSPI_CONFIGREG_DATA_CTL_MASK            0xF0000u
7887 #define ECSPI_CONFIGREG_DATA_CTL_SHIFT           16
7888 #define ECSPI_CONFIGREG_DATA_CTL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_DATA_CTL_SHIFT))&ECSPI_CONFIGREG_DATA_CTL_MASK)
7889 #define ECSPI_CONFIGREG_SCLK_CTL_MASK            0xF00000u
7890 #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT           20
7891 #define ECSPI_CONFIGREG_SCLK_CTL(x)              (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_CTL_SHIFT))&ECSPI_CONFIGREG_SCLK_CTL_MASK)
7892 #define ECSPI_CONFIGREG_HT_LENGTH_MASK           0x1F000000u
7893 #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT          24
7894 #define ECSPI_CONFIGREG_HT_LENGTH(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_HT_LENGTH_SHIFT))&ECSPI_CONFIGREG_HT_LENGTH_MASK)
7895 /* INTREG Bit Fields */
7896 #define ECSPI_INTREG_TEEN_MASK                   0x1u
7897 #define ECSPI_INTREG_TEEN_SHIFT                  0
7898 #define ECSPI_INTREG_TDREN_MASK                  0x2u
7899 #define ECSPI_INTREG_TDREN_SHIFT                 1
7900 #define ECSPI_INTREG_TFEN_MASK                   0x4u
7901 #define ECSPI_INTREG_TFEN_SHIFT                  2
7902 #define ECSPI_INTREG_RREN_MASK                   0x8u
7903 #define ECSPI_INTREG_RREN_SHIFT                  3
7904 #define ECSPI_INTREG_RDREN_MASK                  0x10u
7905 #define ECSPI_INTREG_RDREN_SHIFT                 4
7906 #define ECSPI_INTREG_RFEN_MASK                   0x20u
7907 #define ECSPI_INTREG_RFEN_SHIFT                  5
7908 #define ECSPI_INTREG_ROEN_MASK                   0x40u
7909 #define ECSPI_INTREG_ROEN_SHIFT                  6
7910 #define ECSPI_INTREG_TCEN_MASK                   0x80u
7911 #define ECSPI_INTREG_TCEN_SHIFT                  7
7912 /* DMAREG Bit Fields */
7913 #define ECSPI_DMAREG_TX_THRESHOLD_MASK           0x3Fu
7914 #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT          0
7915 #define ECSPI_DMAREG_TX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_TX_THRESHOLD_SHIFT))&ECSPI_DMAREG_TX_THRESHOLD_MASK)
7916 #define ECSPI_DMAREG_TEDEN_MASK                  0x80u
7917 #define ECSPI_DMAREG_TEDEN_SHIFT                 7
7918 #define ECSPI_DMAREG_RX_THRESHOLD_MASK           0x3F0000u
7919 #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT          16
7920 #define ECSPI_DMAREG_RX_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_THRESHOLD_SHIFT))&ECSPI_DMAREG_RX_THRESHOLD_MASK)
7921 #define ECSPI_DMAREG_RXDEN_MASK                  0x800000u
7922 #define ECSPI_DMAREG_RXDEN_SHIFT                 23
7923 #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK          0x3F000000u
7924 #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT         24
7925 #define ECSPI_DMAREG_RX_DMA_LENGTH(x)            (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT))&ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
7926 #define ECSPI_DMAREG_RXTDEN_MASK                 0x80000000u
7927 #define ECSPI_DMAREG_RXTDEN_SHIFT                31
7928 /* STATREG Bit Fields */
7929 #define ECSPI_STATREG_TE_MASK                    0x1u
7930 #define ECSPI_STATREG_TE_SHIFT                   0
7931 #define ECSPI_STATREG_TDR_MASK                   0x2u
7932 #define ECSPI_STATREG_TDR_SHIFT                  1
7933 #define ECSPI_STATREG_TF_MASK                    0x4u
7934 #define ECSPI_STATREG_TF_SHIFT                   2
7935 #define ECSPI_STATREG_RR_MASK                    0x8u
7936 #define ECSPI_STATREG_RR_SHIFT                   3
7937 #define ECSPI_STATREG_RDR_MASK                   0x10u
7938 #define ECSPI_STATREG_RDR_SHIFT                  4
7939 #define ECSPI_STATREG_RF_MASK                    0x20u
7940 #define ECSPI_STATREG_RF_SHIFT                   5
7941 #define ECSPI_STATREG_RO_MASK                    0x40u
7942 #define ECSPI_STATREG_RO_SHIFT                   6
7943 #define ECSPI_STATREG_TC_MASK                    0x80u
7944 #define ECSPI_STATREG_TC_SHIFT                   7
7945 /* PERIODREG Bit Fields */
7946 #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK       0x7FFFu
7947 #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT      0
7948 #define ECSPI_PERIODREG_SAMPLE_PERIOD(x)         (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT))&ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
7949 #define ECSPI_PERIODREG_CSRC_MASK                0x8000u
7950 #define ECSPI_PERIODREG_CSRC_SHIFT               15
7951 #define ECSPI_PERIODREG_CSD_CTL_MASK             0x3F0000u
7952 #define ECSPI_PERIODREG_CSD_CTL_SHIFT            16
7953 #define ECSPI_PERIODREG_CSD_CTL(x)               (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_CSD_CTL_SHIFT))&ECSPI_PERIODREG_CSD_CTL_MASK)
7954 /* TESTREG Bit Fields */
7955 #define ECSPI_TESTREG_TXCNT_MASK                 0x7Fu
7956 #define ECSPI_TESTREG_TXCNT_SHIFT                0
7957 #define ECSPI_TESTREG_TXCNT(x)                   (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_TXCNT_SHIFT))&ECSPI_TESTREG_TXCNT_MASK)
7958 #define ECSPI_TESTREG_RXCNT_MASK                 0x7F00u
7959 #define ECSPI_TESTREG_RXCNT_SHIFT                8
7960 #define ECSPI_TESTREG_RXCNT(x)                   (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_RXCNT_SHIFT))&ECSPI_TESTREG_RXCNT_MASK)
7961 #define ECSPI_TESTREG_LBC_MASK                   0x80000000u
7962 #define ECSPI_TESTREG_LBC_SHIFT                  31
7963 /* MSGDATA Bit Fields */
7964 #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK         0xFFFFFFFFu
7965 #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT        0
7966 #define ECSPI_MSGDATA_ECSPI_MSGDATA(x)           (((uint32_t)(((uint32_t)(x))<<ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT))&ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
7967 
7968 /*!
7969  * @}
7970  */ /* end of group ECSPI_Register_Masks */
7971 
7972 /* ECSPI - Peripheral instance base addresses */
7973 /** Peripheral ECSPI1 base address */
7974 #define ECSPI1_BASE                              (0x42008000u)
7975 /** Peripheral ECSPI1 base pointer */
7976 #define ECSPI1                                   ((ECSPI_Type *)ECSPI1_BASE)
7977 #define ECSPI1_BASE_PTR                          (ECSPI1)
7978 /** Peripheral ECSPI2 base address */
7979 #define ECSPI2_BASE                              (0x4200C000u)
7980 /** Peripheral ECSPI2 base pointer */
7981 #define ECSPI2                                   ((ECSPI_Type *)ECSPI2_BASE)
7982 #define ECSPI2_BASE_PTR                          (ECSPI2)
7983 /** Peripheral ECSPI3 base address */
7984 #define ECSPI3_BASE                              (0x42010000u)
7985 /** Peripheral ECSPI3 base pointer */
7986 #define ECSPI3                                   ((ECSPI_Type *)ECSPI3_BASE)
7987 #define ECSPI3_BASE_PTR                          (ECSPI3)
7988 /** Peripheral ECSPI4 base address */
7989 #define ECSPI4_BASE                              (0x42014000u)
7990 /** Peripheral ECSPI4 base pointer */
7991 #define ECSPI4                                   ((ECSPI_Type *)ECSPI4_BASE)
7992 #define ECSPI4_BASE_PTR                          (ECSPI4)
7993 /** Peripheral ECSPI5 base address */
7994 #define ECSPI5_BASE                              (0x4228C000u)
7995 /** Peripheral ECSPI5 base pointer */
7996 #define ECSPI5                                   ((ECSPI_Type *)ECSPI5_BASE)
7997 #define ECSPI5_BASE_PTR                          (ECSPI5)
7998 /** Array initializer of ECSPI peripheral base addresses */
7999 #define ECSPI_BASE_ADDRS                         { ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE, ECSPI5_BASE }
8000 /** Array initializer of ECSPI peripheral base pointers */
8001 #define ECSPI_BASE_PTRS                          { ECSPI1, ECSPI2, ECSPI3, ECSPI4, ECSPI5 }
8002 /** Interrupt vectors for the ECSPI peripheral type */
8003 #define ECSPI_IRQS                               { eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn, eCSPI5_IRQn }
8004 
8005 /* ----------------------------------------------------------------------------
8006    -- ECSPI - Register accessor macros
8007    ---------------------------------------------------------------------------- */
8008 
8009 /*!
8010  * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros
8011  * @{
8012  */
8013 
8014 /* ECSPI - Register instance definitions */
8015 /* ECSPI1 */
8016 #define ECSPI1_RXDATA                            ECSPI_RXDATA_REG(ECSPI1_BASE_PTR)
8017 #define ECSPI1_TXDATA                            ECSPI_TXDATA_REG(ECSPI1_BASE_PTR)
8018 #define ECSPI1_CONREG                            ECSPI_CONREG_REG(ECSPI1_BASE_PTR)
8019 #define ECSPI1_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI1_BASE_PTR)
8020 #define ECSPI1_INTREG                            ECSPI_INTREG_REG(ECSPI1_BASE_PTR)
8021 #define ECSPI1_DMAREG                            ECSPI_DMAREG_REG(ECSPI1_BASE_PTR)
8022 #define ECSPI1_STATREG                           ECSPI_STATREG_REG(ECSPI1_BASE_PTR)
8023 #define ECSPI1_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI1_BASE_PTR)
8024 #define ECSPI1_TESTREG                           ECSPI_TESTREG_REG(ECSPI1_BASE_PTR)
8025 #define ECSPI1_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI1_BASE_PTR)
8026 /* ECSPI2 */
8027 #define ECSPI2_RXDATA                            ECSPI_RXDATA_REG(ECSPI2_BASE_PTR)
8028 #define ECSPI2_TXDATA                            ECSPI_TXDATA_REG(ECSPI2_BASE_PTR)
8029 #define ECSPI2_CONREG                            ECSPI_CONREG_REG(ECSPI2_BASE_PTR)
8030 #define ECSPI2_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI2_BASE_PTR)
8031 #define ECSPI2_INTREG                            ECSPI_INTREG_REG(ECSPI2_BASE_PTR)
8032 #define ECSPI2_DMAREG                            ECSPI_DMAREG_REG(ECSPI2_BASE_PTR)
8033 #define ECSPI2_STATREG                           ECSPI_STATREG_REG(ECSPI2_BASE_PTR)
8034 #define ECSPI2_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI2_BASE_PTR)
8035 #define ECSPI2_TESTREG                           ECSPI_TESTREG_REG(ECSPI2_BASE_PTR)
8036 #define ECSPI2_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI2_BASE_PTR)
8037 /* ECSPI3 */
8038 #define ECSPI3_RXDATA                            ECSPI_RXDATA_REG(ECSPI3_BASE_PTR)
8039 #define ECSPI3_TXDATA                            ECSPI_TXDATA_REG(ECSPI3_BASE_PTR)
8040 #define ECSPI3_CONREG                            ECSPI_CONREG_REG(ECSPI3_BASE_PTR)
8041 #define ECSPI3_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI3_BASE_PTR)
8042 #define ECSPI3_INTREG                            ECSPI_INTREG_REG(ECSPI3_BASE_PTR)
8043 #define ECSPI3_DMAREG                            ECSPI_DMAREG_REG(ECSPI3_BASE_PTR)
8044 #define ECSPI3_STATREG                           ECSPI_STATREG_REG(ECSPI3_BASE_PTR)
8045 #define ECSPI3_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI3_BASE_PTR)
8046 #define ECSPI3_TESTREG                           ECSPI_TESTREG_REG(ECSPI3_BASE_PTR)
8047 #define ECSPI3_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI3_BASE_PTR)
8048 /* ECSPI4 */
8049 #define ECSPI4_RXDATA                            ECSPI_RXDATA_REG(ECSPI4_BASE_PTR)
8050 #define ECSPI4_TXDATA                            ECSPI_TXDATA_REG(ECSPI4_BASE_PTR)
8051 #define ECSPI4_CONREG                            ECSPI_CONREG_REG(ECSPI4_BASE_PTR)
8052 #define ECSPI4_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI4_BASE_PTR)
8053 #define ECSPI4_INTREG                            ECSPI_INTREG_REG(ECSPI4_BASE_PTR)
8054 #define ECSPI4_DMAREG                            ECSPI_DMAREG_REG(ECSPI4_BASE_PTR)
8055 #define ECSPI4_STATREG                           ECSPI_STATREG_REG(ECSPI4_BASE_PTR)
8056 #define ECSPI4_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI4_BASE_PTR)
8057 #define ECSPI4_TESTREG                           ECSPI_TESTREG_REG(ECSPI4_BASE_PTR)
8058 #define ECSPI4_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI4_BASE_PTR)
8059 /* ECSPI5 */
8060 #define ECSPI5_RXDATA                            ECSPI_RXDATA_REG(ECSPI5_BASE_PTR)
8061 #define ECSPI5_TXDATA                            ECSPI_TXDATA_REG(ECSPI5_BASE_PTR)
8062 #define ECSPI5_CONREG                            ECSPI_CONREG_REG(ECSPI5_BASE_PTR)
8063 #define ECSPI5_CONFIGREG                         ECSPI_CONFIGREG_REG(ECSPI5_BASE_PTR)
8064 #define ECSPI5_INTREG                            ECSPI_INTREG_REG(ECSPI5_BASE_PTR)
8065 #define ECSPI5_DMAREG                            ECSPI_DMAREG_REG(ECSPI5_BASE_PTR)
8066 #define ECSPI5_STATREG                           ECSPI_STATREG_REG(ECSPI5_BASE_PTR)
8067 #define ECSPI5_PERIODREG                         ECSPI_PERIODREG_REG(ECSPI5_BASE_PTR)
8068 #define ECSPI5_TESTREG                           ECSPI_TESTREG_REG(ECSPI5_BASE_PTR)
8069 #define ECSPI5_MSGDATA                           ECSPI_MSGDATA_REG(ECSPI5_BASE_PTR)
8070 
8071 /*!
8072  * @}
8073  */ /* end of group ECSPI_Register_Accessor_Macros */
8074 
8075 /*!
8076  * @}
8077  */ /* end of group ECSPI_Peripheral */
8078 
8079 /* ----------------------------------------------------------------------------
8080    -- EIM Peripheral Access Layer
8081    ---------------------------------------------------------------------------- */
8082 
8083 /*!
8084  * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
8085  * @{
8086  */
8087 
8088 /** EIM - Register Layout Typedef */
8089 typedef struct {
8090   struct {                                         /* offset: 0x0, array step: 0x18 */
8091   __IO    uint32_t CSGCR1;                                 /**< Chip Select n General Configuration Register 1, array offset: 0x0, array step: 0x18 */
8092   __IO    uint32_t CSGCR2;                                 /**< Chip Select n General Configuration Register 2, array offset: 0x4, array step: 0x18 */
8093   __IO    uint32_t CSRCR1;                                 /**< Chip Select n Read Configuration Register 1, array offset: 0x8, array step: 0x18 */
8094   __IO    uint32_t CSRCR2;                                 /**< Chip Select n Read Configuration Register 2, array offset: 0xC, array step: 0x18 */
8095   __IO    uint32_t CSWCR1;                                 /**< Chip Select n Write Configuration Register 1, array offset: 0x10, array step: 0x18 */
8096   __IO    uint32_t CSWCR2;                                 /**< Chip Select n Write Configuration Register 2, array offset: 0x14, array step: 0x18 */
8097  } CS[6];
8098   __IO  uint32_t WCR;                                    /**< EIM Configuration Register, offset: 0x90 */
8099   __IO  uint32_t DCR;                                    /**< DLL Control Register, offset: 0x94 */
8100   __I   uint32_t DSR;                                    /**< DLL Status Register, offset: 0x98 */
8101   __IO  uint32_t WIAR;                                   /**< EIM IP Access Register, offset: 0x9C */
8102   __IO  uint32_t EAR;                                    /**< Error Address Register, offset: 0xA0 */
8103 } EIM_Type, *EIM_MemMapPtr;
8104 
8105 /* ----------------------------------------------------------------------------
8106    -- EIM - Register accessor macros
8107    ---------------------------------------------------------------------------- */
8108 
8109 /*!
8110  * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros
8111  * @{
8112  */
8113 
8114 /* EIM - Register accessors */
8115 #define EIM_CSGCR1_REG(base,index)               ((base)->CS[index].CSGCR1)
8116 #define EIM_CSGCR2_REG(base,index)               ((base)->CS[index].CSGCR2)
8117 #define EIM_CSRCR1_REG(base,index)               ((base)->CS[index].CSRCR1)
8118 #define EIM_CSRCR2_REG(base,index)               ((base)->CS[index].CSRCR2)
8119 #define EIM_CSWCR1_REG(base,index)               ((base)->CS[index].CSWCR1)
8120 #define EIM_CSWCR2_REG(base,index)               ((base)->CS[index].CSWCR2)
8121 #define EIM_WCR_REG(base)                        ((base)->WCR)
8122 #define EIM_DCR_REG(base)                        ((base)->DCR)
8123 #define EIM_DSR_REG(base)                        ((base)->DSR)
8124 #define EIM_WIAR_REG(base)                       ((base)->WIAR)
8125 #define EIM_EAR_REG(base)                        ((base)->EAR)
8126 
8127 /*!
8128  * @}
8129  */ /* end of group EIM_Register_Accessor_Macros */
8130 
8131 /* ----------------------------------------------------------------------------
8132    -- EIM Register Masks
8133    ---------------------------------------------------------------------------- */
8134 
8135 /*!
8136  * @addtogroup EIM_Register_Masks EIM Register Masks
8137  * @{
8138  */
8139 
8140 /* CSGCR1 Bit Fields */
8141 #define EIM_CSGCR1_CSEN_MASK                     0x1u
8142 #define EIM_CSGCR1_CSEN_SHIFT                    0
8143 #define EIM_CSGCR1_SWR_MASK                      0x2u
8144 #define EIM_CSGCR1_SWR_SHIFT                     1
8145 #define EIM_CSGCR1_SRD_MASK                      0x4u
8146 #define EIM_CSGCR1_SRD_SHIFT                     2
8147 #define EIM_CSGCR1_MUM_MASK                      0x8u
8148 #define EIM_CSGCR1_MUM_SHIFT                     3
8149 #define EIM_CSGCR1_WFL_MASK                      0x10u
8150 #define EIM_CSGCR1_WFL_SHIFT                     4
8151 #define EIM_CSGCR1_RFL_MASK                      0x20u
8152 #define EIM_CSGCR1_RFL_SHIFT                     5
8153 #define EIM_CSGCR1_CRE_MASK                      0x40u
8154 #define EIM_CSGCR1_CRE_SHIFT                     6
8155 #define EIM_CSGCR1_CREP_MASK                     0x80u
8156 #define EIM_CSGCR1_CREP_SHIFT                    7
8157 #define EIM_CSGCR1_BL_MASK                       0x700u
8158 #define EIM_CSGCR1_BL_SHIFT                      8
8159 #define EIM_CSGCR1_BL(x)                         (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BL_SHIFT))&EIM_CSGCR1_BL_MASK)
8160 #define EIM_CSGCR1_WC_MASK                       0x800u
8161 #define EIM_CSGCR1_WC_SHIFT                      11
8162 #define EIM_CSGCR1_BCD_MASK                      0x3000u
8163 #define EIM_CSGCR1_BCD_SHIFT                     12
8164 #define EIM_CSGCR1_BCD(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCD_SHIFT))&EIM_CSGCR1_BCD_MASK)
8165 #define EIM_CSGCR1_BCS_MASK                      0xC000u
8166 #define EIM_CSGCR1_BCS_SHIFT                     14
8167 #define EIM_CSGCR1_BCS(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCS_SHIFT))&EIM_CSGCR1_BCS_MASK)
8168 #define EIM_CSGCR1_DSZ_MASK                      0x70000u
8169 #define EIM_CSGCR1_DSZ_SHIFT                     16
8170 #define EIM_CSGCR1_DSZ(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_DSZ_SHIFT))&EIM_CSGCR1_DSZ_MASK)
8171 #define EIM_CSGCR1_SP_MASK                       0x80000u
8172 #define EIM_CSGCR1_SP_SHIFT                      19
8173 #define EIM_CSGCR1_CSREC_MASK                    0x700000u
8174 #define EIM_CSGCR1_CSREC_SHIFT                   20
8175 #define EIM_CSGCR1_CSREC(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_CSREC_SHIFT))&EIM_CSGCR1_CSREC_MASK)
8176 #define EIM_CSGCR1_AUS_MASK                      0x800000u
8177 #define EIM_CSGCR1_AUS_SHIFT                     23
8178 #define EIM_CSGCR1_GBC_MASK                      0x7000000u
8179 #define EIM_CSGCR1_GBC_SHIFT                     24
8180 #define EIM_CSGCR1_GBC(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_GBC_SHIFT))&EIM_CSGCR1_GBC_MASK)
8181 #define EIM_CSGCR1_WP_MASK                       0x8000000u
8182 #define EIM_CSGCR1_WP_SHIFT                      27
8183 #define EIM_CSGCR1_PSZ_MASK                      0xF0000000u
8184 #define EIM_CSGCR1_PSZ_SHIFT                     28
8185 #define EIM_CSGCR1_PSZ(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_PSZ_SHIFT))&EIM_CSGCR1_PSZ_MASK)
8186 /* CSGCR2 Bit Fields */
8187 #define EIM_CSGCR2_ADH_MASK                      0x3u
8188 #define EIM_CSGCR2_ADH_SHIFT                     0
8189 #define EIM_CSGCR2_ADH(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_ADH_SHIFT))&EIM_CSGCR2_ADH_MASK)
8190 #define EIM_CSGCR2_DAPS_MASK                     0xF0u
8191 #define EIM_CSGCR2_DAPS_SHIFT                    4
8192 #define EIM_CSGCR2_DAPS(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_DAPS_SHIFT))&EIM_CSGCR2_DAPS_MASK)
8193 #define EIM_CSGCR2_DAE_MASK                      0x100u
8194 #define EIM_CSGCR2_DAE_SHIFT                     8
8195 #define EIM_CSGCR2_DAP_MASK                      0x200u
8196 #define EIM_CSGCR2_DAP_SHIFT                     9
8197 #define EIM_CSGCR2_MUX16_BYP_GRANT_MASK          0x1000u
8198 #define EIM_CSGCR2_MUX16_BYP_GRANT_SHIFT         12
8199 /* CSRCR1 Bit Fields */
8200 #define EIM_CSRCR1_RCSN_MASK                     0x7u
8201 #define EIM_CSRCR1_RCSN_SHIFT                    0
8202 #define EIM_CSRCR1_RCSN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSN_SHIFT))&EIM_CSRCR1_RCSN_MASK)
8203 #define EIM_CSRCR1_RCSA_MASK                     0x70u
8204 #define EIM_CSRCR1_RCSA_SHIFT                    4
8205 #define EIM_CSRCR1_RCSA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSA_SHIFT))&EIM_CSRCR1_RCSA_MASK)
8206 #define EIM_CSRCR1_OEN_MASK                      0x700u
8207 #define EIM_CSRCR1_OEN_SHIFT                     8
8208 #define EIM_CSRCR1_OEN(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEN_SHIFT))&EIM_CSRCR1_OEN_MASK)
8209 #define EIM_CSRCR1_OEA_MASK                      0x7000u
8210 #define EIM_CSRCR1_OEA_SHIFT                     12
8211 #define EIM_CSRCR1_OEA(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEA_SHIFT))&EIM_CSRCR1_OEA_MASK)
8212 #define EIM_CSRCR1_RADVN_MASK                    0x70000u
8213 #define EIM_CSRCR1_RADVN_SHIFT                   16
8214 #define EIM_CSRCR1_RADVN(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVN_SHIFT))&EIM_CSRCR1_RADVN_MASK)
8215 #define EIM_CSRCR1_RAL_MASK                      0x80000u
8216 #define EIM_CSRCR1_RAL_SHIFT                     19
8217 #define EIM_CSRCR1_RADVA_MASK                    0x700000u
8218 #define EIM_CSRCR1_RADVA_SHIFT                   20
8219 #define EIM_CSRCR1_RADVA(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVA_SHIFT))&EIM_CSRCR1_RADVA_MASK)
8220 #define EIM_CSRCR1_RWSC_MASK                     0x3F000000u
8221 #define EIM_CSRCR1_RWSC_SHIFT                    24
8222 #define EIM_CSRCR1_RWSC(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RWSC_SHIFT))&EIM_CSRCR1_RWSC_MASK)
8223 /* CSRCR2 Bit Fields */
8224 #define EIM_CSRCR2_RBEN_MASK                     0x7u
8225 #define EIM_CSRCR2_RBEN_SHIFT                    0
8226 #define EIM_CSRCR2_RBEN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEN_SHIFT))&EIM_CSRCR2_RBEN_MASK)
8227 #define EIM_CSRCR2_RBE_MASK                      0x8u
8228 #define EIM_CSRCR2_RBE_SHIFT                     3
8229 #define EIM_CSRCR2_RBEA_MASK                     0x70u
8230 #define EIM_CSRCR2_RBEA_SHIFT                    4
8231 #define EIM_CSRCR2_RBEA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEA_SHIFT))&EIM_CSRCR2_RBEA_MASK)
8232 #define EIM_CSRCR2_RL_MASK                       0x300u
8233 #define EIM_CSRCR2_RL_SHIFT                      8
8234 #define EIM_CSRCR2_RL(x)                         (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RL_SHIFT))&EIM_CSRCR2_RL_MASK)
8235 #define EIM_CSRCR2_PAT_MASK                      0x7000u
8236 #define EIM_CSRCR2_PAT_SHIFT                     12
8237 #define EIM_CSRCR2_PAT(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_PAT_SHIFT))&EIM_CSRCR2_PAT_MASK)
8238 #define EIM_CSRCR2_APR_MASK                      0x8000u
8239 #define EIM_CSRCR2_APR_SHIFT                     15
8240 /* CSWCR1 Bit Fields */
8241 #define EIM_CSWCR1_WCSN_MASK                     0x7u
8242 #define EIM_CSWCR1_WCSN_SHIFT                    0
8243 #define EIM_CSWCR1_WCSN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSN_SHIFT))&EIM_CSWCR1_WCSN_MASK)
8244 #define EIM_CSWCR1_WCSA_MASK                     0x38u
8245 #define EIM_CSWCR1_WCSA_SHIFT                    3
8246 #define EIM_CSWCR1_WCSA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSA_SHIFT))&EIM_CSWCR1_WCSA_MASK)
8247 #define EIM_CSWCR1_WEN_MASK                      0x1C0u
8248 #define EIM_CSWCR1_WEN_SHIFT                     6
8249 #define EIM_CSWCR1_WEN(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEN_SHIFT))&EIM_CSWCR1_WEN_MASK)
8250 #define EIM_CSWCR1_WEA_MASK                      0xE00u
8251 #define EIM_CSWCR1_WEA_SHIFT                     9
8252 #define EIM_CSWCR1_WEA(x)                        (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEA_SHIFT))&EIM_CSWCR1_WEA_MASK)
8253 #define EIM_CSWCR1_WBEN_MASK                     0x7000u
8254 #define EIM_CSWCR1_WBEN_SHIFT                    12
8255 #define EIM_CSWCR1_WBEN(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEN_SHIFT))&EIM_CSWCR1_WBEN_MASK)
8256 #define EIM_CSWCR1_WBEA_MASK                     0x38000u
8257 #define EIM_CSWCR1_WBEA_SHIFT                    15
8258 #define EIM_CSWCR1_WBEA(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEA_SHIFT))&EIM_CSWCR1_WBEA_MASK)
8259 #define EIM_CSWCR1_WADVN_MASK                    0x1C0000u
8260 #define EIM_CSWCR1_WADVN_SHIFT                   18
8261 #define EIM_CSWCR1_WADVN(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVN_SHIFT))&EIM_CSWCR1_WADVN_MASK)
8262 #define EIM_CSWCR1_WADVA_MASK                    0xE00000u
8263 #define EIM_CSWCR1_WADVA_SHIFT                   21
8264 #define EIM_CSWCR1_WADVA(x)                      (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVA_SHIFT))&EIM_CSWCR1_WADVA_MASK)
8265 #define EIM_CSWCR1_WWSC_MASK                     0x3F000000u
8266 #define EIM_CSWCR1_WWSC_SHIFT                    24
8267 #define EIM_CSWCR1_WWSC(x)                       (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WWSC_SHIFT))&EIM_CSWCR1_WWSC_MASK)
8268 #define EIM_CSWCR1_WBED_MASK                     0x40000000u
8269 #define EIM_CSWCR1_WBED_SHIFT                    30
8270 #define EIM_CSWCR1_WAL_MASK                      0x80000000u
8271 #define EIM_CSWCR1_WAL_SHIFT                     31
8272 /* CSWCR2 Bit Fields */
8273 #define EIM_CSWCR2_WBCDD_MASK                    0x1u
8274 #define EIM_CSWCR2_WBCDD_SHIFT                   0
8275 /* WCR Bit Fields */
8276 #define EIM_WCR_BCM_MASK                         0x1u
8277 #define EIM_WCR_BCM_SHIFT                        0
8278 #define EIM_WCR_GBCD_MASK                        0x6u
8279 #define EIM_WCR_GBCD_SHIFT                       1
8280 #define EIM_WCR_GBCD(x)                          (((uint32_t)(((uint32_t)(x))<<EIM_WCR_GBCD_SHIFT))&EIM_WCR_GBCD_MASK)
8281 #define EIM_WCR_CONT_BCLK_SEL_MASK               0x8u
8282 #define EIM_WCR_CONT_BCLK_SEL_SHIFT              3
8283 #define EIM_WCR_INTEN_MASK                       0x10u
8284 #define EIM_WCR_INTEN_SHIFT                      4
8285 #define EIM_WCR_INTPOL_MASK                      0x20u
8286 #define EIM_WCR_INTPOL_SHIFT                     5
8287 #define EIM_WCR_WDOG_EN_MASK                     0x100u
8288 #define EIM_WCR_WDOG_EN_SHIFT                    8
8289 #define EIM_WCR_WDOG_LIMIT_MASK                  0x600u
8290 #define EIM_WCR_WDOG_LIMIT_SHIFT                 9
8291 #define EIM_WCR_WDOG_LIMIT(x)                    (((uint32_t)(((uint32_t)(x))<<EIM_WCR_WDOG_LIMIT_SHIFT))&EIM_WCR_WDOG_LIMIT_MASK)
8292 #define EIM_WCR_FRUN_ACLK_EN_MASK                0x800u
8293 #define EIM_WCR_FRUN_ACLK_EN_SHIFT               11
8294 /* DCR Bit Fields */
8295 #define EIM_DCR_DLL_CTRL_ENABLE_MASK             0x1u
8296 #define EIM_DCR_DLL_CTRL_ENABLE_SHIFT            0
8297 #define EIM_DCR_DLL_CTRL_RESET_MASK              0x2u
8298 #define EIM_DCR_DLL_CTRL_RESET_SHIFT             1
8299 #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_MASK      0x4u
8300 #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_SHIFT     2
8301 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_MASK     0x8u
8302 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_SHIFT    3
8303 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK         0x70u
8304 #define EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT        4
8305 #define EIM_DCR_DLL_CTRL_SLV_OFFSET(x)           (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK)
8306 #define EIM_DCR_DLL_CTRL_GATE_UPDATE_MASK        0x80u
8307 #define EIM_DCR_DLL_CTRL_GATE_UPDATE_SHIFT       7
8308 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_MASK       0x100u
8309 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_SHIFT      8
8310 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK   0xFE00u
8311 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT  9
8312 #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL(x)     (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
8313 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK    0x7F0000u
8314 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT   16
8315 #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL(x)      (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT))&EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK)
8316 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK     0xF800000u
8317 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT    23
8318 #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT(x)       (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK)
8319 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK     0xF0000000u
8320 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT    28
8321 #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT(x)       (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK)
8322 /* DSR Bit Fields */
8323 #define EIM_DSR_DLL_STS_SLV_LOCK_MASK            0x1u
8324 #define EIM_DSR_DLL_STS_SLV_LOCK_SHIFT           0
8325 #define EIM_DSR_DLL_STS_REF_LOCK_MASK            0x2u
8326 #define EIM_DSR_DLL_STS_REF_LOCK_SHIFT           1
8327 #define EIM_DSR_DLL_STS_SLV_SEL_MASK             0x1FCu
8328 #define EIM_DSR_DLL_STS_SLV_SEL_SHIFT            2
8329 #define EIM_DSR_DLL_STS_SLV_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_SLV_SEL_SHIFT))&EIM_DSR_DLL_STS_SLV_SEL_MASK)
8330 #define EIM_DSR_DLL_STS_REF_SEL_MASK             0xFE00u
8331 #define EIM_DSR_DLL_STS_REF_SEL_SHIFT            9
8332 #define EIM_DSR_DLL_STS_REF_SEL(x)               (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_REF_SEL_SHIFT))&EIM_DSR_DLL_STS_REF_SEL_MASK)
8333 /* WIAR Bit Fields */
8334 #define EIM_WIAR_IPS_REQ_MASK                    0x1u
8335 #define EIM_WIAR_IPS_REQ_SHIFT                   0
8336 #define EIM_WIAR_IPS_ACK_MASK                    0x2u
8337 #define EIM_WIAR_IPS_ACK_SHIFT                   1
8338 #define EIM_WIAR_INT_MASK                        0x4u
8339 #define EIM_WIAR_INT_SHIFT                       2
8340 #define EIM_WIAR_ERRST_MASK                      0x8u
8341 #define EIM_WIAR_ERRST_SHIFT                     3
8342 #define EIM_WIAR_ACLK_EN_MASK                    0x10u
8343 #define EIM_WIAR_ACLK_EN_SHIFT                   4
8344 /* EAR Bit Fields */
8345 #define EIM_EAR_Error_ADDR_MASK                  0xFFFFFFFFu
8346 #define EIM_EAR_Error_ADDR_SHIFT                 0
8347 #define EIM_EAR_Error_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<EIM_EAR_Error_ADDR_SHIFT))&EIM_EAR_Error_ADDR_MASK)
8348 
8349 /*!
8350  * @}
8351  */ /* end of group EIM_Register_Masks */
8352 
8353 /* EIM - Peripheral instance base addresses */
8354 /** Peripheral EIM base address */
8355 #define EIM_BASE                                 (0x421B8000u)
8356 /** Peripheral EIM base pointer */
8357 #define EIM                                      ((EIM_Type *)EIM_BASE)
8358 #define EIM_BASE_PTR                             (EIM)
8359 /** Array initializer of EIM peripheral base addresses */
8360 #define EIM_BASE_ADDRS                           { EIM_BASE }
8361 /** Array initializer of EIM peripheral base pointers */
8362 #define EIM_BASE_PTRS                            { EIM }
8363 /** Interrupt vectors for the EIM peripheral type */
8364 #define EIM_IRQS                                 { EIM_IRQn }
8365 
8366 /* ----------------------------------------------------------------------------
8367    -- EIM - Register accessor macros
8368    ---------------------------------------------------------------------------- */
8369 
8370 /*!
8371  * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros
8372  * @{
8373  */
8374 
8375 /* EIM - Register instance definitions */
8376 /* EIM */
8377 #define EIM_CS0GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,0)
8378 #define EIM_CS0GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,0)
8379 #define EIM_CS0RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,0)
8380 #define EIM_CS0RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,0)
8381 #define EIM_CS0WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,0)
8382 #define EIM_CS0WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,0)
8383 #define EIM_CS1GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,1)
8384 #define EIM_CS1GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,1)
8385 #define EIM_CS1RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,1)
8386 #define EIM_CS1RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,1)
8387 #define EIM_CS1WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,1)
8388 #define EIM_CS1WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,1)
8389 #define EIM_CS2GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,2)
8390 #define EIM_CS2GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,2)
8391 #define EIM_CS2RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,2)
8392 #define EIM_CS2RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,2)
8393 #define EIM_CS2WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,2)
8394 #define EIM_CS2WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,2)
8395 #define EIM_CS3GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,3)
8396 #define EIM_CS3GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,3)
8397 #define EIM_CS3RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,3)
8398 #define EIM_CS3RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,3)
8399 #define EIM_CS3WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,3)
8400 #define EIM_CS3WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,3)
8401 #define EIM_CS4GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,4)
8402 #define EIM_CS4GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,4)
8403 #define EIM_CS4RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,4)
8404 #define EIM_CS4RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,4)
8405 #define EIM_CS4WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,4)
8406 #define EIM_CS4WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,4)
8407 #define EIM_CS5GCR1                              EIM_CSGCR1_REG(EIM_BASE_PTR,5)
8408 #define EIM_CS5GCR2                              EIM_CSGCR2_REG(EIM_BASE_PTR,5)
8409 #define EIM_CS5RCR1                              EIM_CSRCR1_REG(EIM_BASE_PTR,5)
8410 #define EIM_CS5RCR2                              EIM_CSRCR2_REG(EIM_BASE_PTR,5)
8411 #define EIM_CS5WCR1                              EIM_CSWCR1_REG(EIM_BASE_PTR,5)
8412 #define EIM_CS5WCR2                              EIM_CSWCR2_REG(EIM_BASE_PTR,5)
8413 #define EIM_WCR                                  EIM_WCR_REG(EIM_BASE_PTR)
8414 #define EIM_DCR                                  EIM_DCR_REG(EIM_BASE_PTR)
8415 #define EIM_DSR                                  EIM_DSR_REG(EIM_BASE_PTR)
8416 #define EIM_WIAR                                 EIM_WIAR_REG(EIM_BASE_PTR)
8417 #define EIM_EAR                                  EIM_EAR_REG(EIM_BASE_PTR)
8418 /* EIM - Register array accessors */
8419 #define EIM_CSGCR1(index)                        EIM_CSGCR1_REG(EIM_BASE_PTR,index)
8420 #define EIM_CSGCR2(index)                        EIM_CSGCR2_REG(EIM_BASE_PTR,index)
8421 #define EIM_CSRCR1(index)                        EIM_CSRCR1_REG(EIM_BASE_PTR,index)
8422 #define EIM_CSRCR2(index)                        EIM_CSRCR2_REG(EIM_BASE_PTR,index)
8423 #define EIM_CSWCR1(index)                        EIM_CSWCR1_REG(EIM_BASE_PTR,index)
8424 #define EIM_CSWCR2(index)                        EIM_CSWCR2_REG(EIM_BASE_PTR,index)
8425 
8426 /*!
8427  * @}
8428  */ /* end of group EIM_Register_Accessor_Macros */
8429 
8430 /*!
8431  * @}
8432  */ /* end of group EIM_Peripheral */
8433 
8434 /* ----------------------------------------------------------------------------
8435    -- ENET Peripheral Access Layer
8436    ---------------------------------------------------------------------------- */
8437 
8438 /*!
8439  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
8440  * @{
8441  */
8442 
8443 /** ENET - Register Layout Typedef */
8444 typedef struct {
8445   uint8_t RESERVED_0[4];
8446   __IO  uint32_t EIR;                                    /**< Interrupt Event Register, offset: 0x4 */
8447   __IO  uint32_t EIMR;                                   /**< Interrupt Mask Register, offset: 0x8 */
8448   uint8_t RESERVED_1[4];
8449   __IO  uint32_t RDAR;                                   /**< Receive Descriptor Active Register, offset: 0x10 */
8450   __IO  uint32_t TDAR;                                   /**< Transmit Descriptor Active Register, offset: 0x14 */
8451   uint8_t RESERVED_2[12];
8452   __IO  uint32_t ECR;                                    /**< Ethernet Control Register, offset: 0x24 */
8453   uint8_t RESERVED_3[24];
8454   __IO  uint32_t MMFR;                                   /**< MII Management Frame Register, offset: 0x40 */
8455   __IO  uint32_t MSCR;                                   /**< MII Speed Control Register, offset: 0x44 */
8456   uint8_t RESERVED_4[28];
8457   __IO  uint32_t MIBC;                                   /**< MIB Control Register, offset: 0x64 */
8458   uint8_t RESERVED_5[28];
8459   __IO  uint32_t RCR;                                    /**< Receive Control Register, offset: 0x84 */
8460   uint8_t RESERVED_6[60];
8461   __IO  uint32_t TCR;                                    /**< Transmit Control Register, offset: 0xC4 */
8462   uint8_t RESERVED_7[28];
8463   __IO  uint32_t PALR;                                   /**< Physical Address Lower Register, offset: 0xE4 */
8464   __IO  uint32_t PAUR;                                   /**< Physical Address Upper Register, offset: 0xE8 */
8465   __IO  uint32_t OPD;                                    /**< Opcode/Pause Duration Register, offset: 0xEC */
8466   __IO  uint32_t TXIC[3];                                /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
8467   uint8_t RESERVED_8[4];
8468   __IO  uint32_t RXIC[3];                                /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
8469   uint8_t RESERVED_9[12];
8470   __IO  uint32_t IAUR;                                   /**< Descriptor Individual Upper Address Register, offset: 0x118 */
8471   __IO  uint32_t IALR;                                   /**< Descriptor Individual Lower Address Register, offset: 0x11C */
8472   __IO  uint32_t GAUR;                                   /**< Descriptor Group Upper Address Register, offset: 0x120 */
8473   __IO  uint32_t GALR;                                   /**< Descriptor Group Lower Address Register, offset: 0x124 */
8474   uint8_t RESERVED_10[28];
8475   __IO  uint32_t TFWR;                                   /**< Transmit FIFO Watermark Register, offset: 0x144 */
8476   uint8_t RESERVED_11[24];
8477   __IO  uint32_t RDSR1;                                  /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
8478   __IO  uint32_t TDSR1;                                  /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
8479   __IO  uint32_t MRBR1;                                  /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
8480   __IO  uint32_t RDSR2;                                  /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
8481   __IO  uint32_t TDSR2;                                  /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
8482   __IO  uint32_t MRBR2;                                  /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
8483   uint8_t RESERVED_12[8];
8484   __IO  uint32_t RDSR;                                   /**< Receive Descriptor Ring , offset: 0x180 */
8485   __IO  uint32_t TDSR;                                   /**< Transmit Buffer Descriptor Ring , offset: 0x184 */
8486   __IO  uint32_t MRBR;                                   /**< Maximum Receive Buffer Size Register, offset: 0x188 */
8487   uint8_t RESERVED_13[4];
8488   __IO  uint32_t RSFL;                                   /**< Receive FIFO Section Full Threshold, offset: 0x190 */
8489   __IO  uint32_t RSEM;                                   /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
8490   __IO  uint32_t RAEM;                                   /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
8491   __IO  uint32_t RAFL;                                   /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
8492   __IO  uint32_t TSEM;                                   /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
8493   __IO  uint32_t TAEM;                                   /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
8494   __IO  uint32_t TAFL;                                   /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
8495   __IO  uint32_t TIPG;                                   /**< Transmit Inter-Packet Gap, offset: 0x1AC */
8496   __IO  uint32_t FTRL;                                   /**< Frame Truncation Length, offset: 0x1B0 */
8497   uint8_t RESERVED_14[12];
8498   __IO  uint32_t TACC;                                   /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
8499   __IO  uint32_t RACC;                                   /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
8500   __IO  uint32_t RCMR[2];                                /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
8501   uint8_t RESERVED_15[8];
8502   __IO  uint32_t DMACFG[2];                              /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
8503   __IO  uint32_t RDAR1;                                  /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
8504   __IO  uint32_t TDAR1;                                  /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
8505   __IO  uint32_t RDAR2;                                  /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
8506   __IO  uint32_t TDAR2;                                  /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
8507   __IO  uint32_t QOS;                                    /**< QOS Scheme, offset: 0x1F0 */
8508   uint8_t RESERVED_16[12];
8509   __I   uint32_t RMON_T_DROP;                            /**< Incorrectly Counted Frames Statistic Register, offset: 0x200 */
8510   __I   uint32_t RMON_T_PACKETS;                         /**< Tx Packet Count Statistic Register, offset: 0x204 */
8511   __I   uint32_t RMON_T_BC_PKT;                          /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
8512   __I   uint32_t RMON_T_MC_PKT;                          /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
8513   __I   uint32_t RMON_T_CRC_ALIGN;                       /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
8514   __I   uint32_t RMON_T_UNDERSIZE;                       /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
8515   __I   uint32_t RMON_T_OVERSIZE;                        /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
8516   __I   uint32_t RMON_T_FRAG;                            /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
8517   __I   uint32_t RMON_T_JAB;                             /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
8518   __I   uint32_t RMON_T_COL;                             /**< Tx Collision Count Statistic Register, offset: 0x224 */
8519   __I   uint32_t RMON_T_P64;                             /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
8520   __I   uint32_t RMON_T_P65TO127;                        /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
8521   __I   uint32_t RMON_T_P128TO255;                       /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
8522   __I   uint32_t RMON_T_P256TO511;                       /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
8523   __I   uint32_t RMON_T_P512TO1023;                      /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
8524   __I   uint32_t RMON_T_P1024TO2047;                     /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
8525   __I   uint32_t RMON_T_P_GTE2048;                       /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
8526   __I   uint32_t RMON_T_OCTETS;                          /**< Tx Octets Statistic Register, offset: 0x244 */
8527   __I   uint32_t IEEE_T_DROP;                            /**< IEEE_T_DROP Statistic Register, offset: 0x248 */
8528   __I   uint32_t IEEE_T_FRAME_OK;                        /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
8529   __I   uint32_t IEEE_T_1COL;                            /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
8530   __I   uint32_t IEEE_T_MCOL;                            /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
8531   __I   uint32_t IEEE_T_DEF;                             /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
8532   __I   uint32_t IEEE_T_LCOL;                            /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
8533   __I   uint32_t IEEE_T_EXCOL;                           /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
8534   __I   uint32_t IEEE_T_MACERR;                          /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
8535   __I   uint32_t IEEE_T_CSERR;                           /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
8536   __I   uint32_t IEEE_T_SQE;                             /**< , offset: 0x26C */
8537   __I   uint32_t IEEE_T_FDXFC;                           /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
8538   __I   uint32_t IEEE_T_OCTETS_OK;                       /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
8539   uint8_t RESERVED_17[12];
8540   __I   uint32_t RMON_R_PACKETS;                         /**< Rx Packet Count Statistic Register, offset: 0x284 */
8541   __I   uint32_t RMON_R_BC_PKT;                          /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
8542   __I   uint32_t RMON_R_MC_PKT;                          /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
8543   __I   uint32_t RMON_R_CRC_ALIGN;                       /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
8544   __I   uint32_t RMON_R_UNDERSIZE;                       /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
8545   __I   uint32_t RMON_R_OVERSIZE;                        /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
8546   __I   uint32_t RMON_R_FRAG;                            /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
8547   __I   uint32_t RMON_R_JAB;                             /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
8548   __I   uint32_t RMON_R_RESVD_0;                         /**< RMON Reserved Register, offset: 0x2A4 */
8549   __I   uint32_t RMON_R_P64;                             /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
8550   __I   uint32_t RMON_R_P65TO127;                        /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
8551   __I   uint32_t RMON_R_P128TO255;                       /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
8552   __I   uint32_t RMON_R_P256TO511;                       /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
8553   __I   uint32_t RMON_R_P512TO1023;                      /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
8554   __I   uint32_t RMON_R_P1024TO2047;                     /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
8555   __I   uint32_t RMON_R_P_GTE2048;                       /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
8556   __I   uint32_t RMON_R_OCTETS;                          /**< Rx Octets Statistic Register, offset: 0x2C4 */
8557   __I   uint32_t IEEE_R_DROP;                            /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
8558   __I   uint32_t IEEE_R_FRAME_OK;                        /**< Frames Received OK Statistic Register, offset: 0x2CC */
8559   __I   uint32_t IEEE_R_CRC;                             /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
8560   __I   uint32_t IEEE_R_ALIGN;                           /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
8561   __I   uint32_t IEEE_R_MACERR;                          /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
8562   __I   uint32_t IEEE_R_FDXFC;                           /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
8563   __I   uint32_t IEEE_R_OCTETS_OK;                       /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
8564   uint8_t RESERVED_18[284];
8565   __IO  uint32_t ATCR;                                   /**< Adjustable Timer Control Register, offset: 0x400 */
8566   __IO  uint32_t ATVR;                                   /**< Timer Value Register, offset: 0x404 */
8567   __IO  uint32_t ATOFF;                                  /**< Timer Offset Register, offset: 0x408 */
8568   __IO  uint32_t ATPER;                                  /**< Timer Period Register, offset: 0x40C */
8569   __IO  uint32_t ATCOR;                                  /**< Timer Correction Register, offset: 0x410 */
8570   __IO  uint32_t ATINC;                                  /**< Time-Stamping Clock Period Register, offset: 0x414 */
8571   __I   uint32_t ATSTMP;                                 /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
8572   uint8_t RESERVED_19[488];
8573   __IO  uint32_t TGSR;                                   /**< Timer Global Status Register, offset: 0x604 */
8574   struct {                                         /* offset: 0x608, array step: 0x8 */
8575   __IO    uint32_t TCSR;                                   /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
8576   __IO    uint32_t TCCR;                                   /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
8577  } TC[4];
8578 } ENET_Type, *ENET_MemMapPtr;
8579 
8580 /* ----------------------------------------------------------------------------
8581    -- ENET - Register accessor macros
8582    ---------------------------------------------------------------------------- */
8583 
8584 /*!
8585  * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
8586  * @{
8587  */
8588 
8589 /* ENET - Register accessors */
8590 #define ENET_EIR_REG(base)                       ((base)->EIR)
8591 #define ENET_EIMR_REG(base)                      ((base)->EIMR)
8592 #define ENET_RDAR_REG(base)                      ((base)->RDAR)
8593 #define ENET_TDAR_REG(base)                      ((base)->TDAR)
8594 #define ENET_ECR_REG(base)                       ((base)->ECR)
8595 #define ENET_MMFR_REG(base)                      ((base)->MMFR)
8596 #define ENET_MSCR_REG(base)                      ((base)->MSCR)
8597 #define ENET_MIBC_REG(base)                      ((base)->MIBC)
8598 #define ENET_RCR_REG(base)                       ((base)->RCR)
8599 #define ENET_TCR_REG(base)                       ((base)->TCR)
8600 #define ENET_PALR_REG(base)                      ((base)->PALR)
8601 #define ENET_PAUR_REG(base)                      ((base)->PAUR)
8602 #define ENET_OPD_REG(base)                       ((base)->OPD)
8603 #define ENET_TXIC_REG(base,index)                ((base)->TXIC[index])
8604 #define ENET_RXIC_REG(base,index)                ((base)->RXIC[index])
8605 #define ENET_IAUR_REG(base)                      ((base)->IAUR)
8606 #define ENET_IALR_REG(base)                      ((base)->IALR)
8607 #define ENET_GAUR_REG(base)                      ((base)->GAUR)
8608 #define ENET_GALR_REG(base)                      ((base)->GALR)
8609 #define ENET_TFWR_REG(base)                      ((base)->TFWR)
8610 #define ENET_RDSR1_REG(base)                     ((base)->RDSR1)
8611 #define ENET_TDSR1_REG(base)                     ((base)->TDSR1)
8612 #define ENET_MRBR1_REG(base)                     ((base)->MRBR1)
8613 #define ENET_RDSR2_REG(base)                     ((base)->RDSR2)
8614 #define ENET_TDSR2_REG(base)                     ((base)->TDSR2)
8615 #define ENET_MRBR2_REG(base)                     ((base)->MRBR2)
8616 #define ENET_RDSR_REG(base)                      ((base)->RDSR)
8617 #define ENET_TDSR_REG(base)                      ((base)->TDSR)
8618 #define ENET_MRBR_REG(base)                      ((base)->MRBR)
8619 #define ENET_RSFL_REG(base)                      ((base)->RSFL)
8620 #define ENET_RSEM_REG(base)                      ((base)->RSEM)
8621 #define ENET_RAEM_REG(base)                      ((base)->RAEM)
8622 #define ENET_RAFL_REG(base)                      ((base)->RAFL)
8623 #define ENET_TSEM_REG(base)                      ((base)->TSEM)
8624 #define ENET_TAEM_REG(base)                      ((base)->TAEM)
8625 #define ENET_TAFL_REG(base)                      ((base)->TAFL)
8626 #define ENET_TIPG_REG(base)                      ((base)->TIPG)
8627 #define ENET_FTRL_REG(base)                      ((base)->FTRL)
8628 #define ENET_TACC_REG(base)                      ((base)->TACC)
8629 #define ENET_RACC_REG(base)                      ((base)->RACC)
8630 #define ENET_RCMR_REG(base,index)                ((base)->RCMR[index])
8631 #define ENET_DMACFG_REG(base,index)              ((base)->DMACFG[index])
8632 #define ENET_RDAR1_REG(base)                     ((base)->RDAR1)
8633 #define ENET_TDAR1_REG(base)                     ((base)->TDAR1)
8634 #define ENET_RDAR2_REG(base)                     ((base)->RDAR2)
8635 #define ENET_TDAR2_REG(base)                     ((base)->TDAR2)
8636 #define ENET_QOS_REG(base)                       ((base)->QOS)
8637 #define ENET_RMON_T_DROP_REG(base)               ((base)->RMON_T_DROP)
8638 #define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
8639 #define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
8640 #define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
8641 #define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
8642 #define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
8643 #define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
8644 #define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
8645 #define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
8646 #define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
8647 #define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
8648 #define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
8649 #define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
8650 #define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
8651 #define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
8652 #define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
8653 #define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
8654 #define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
8655 #define ENET_IEEE_T_DROP_REG(base)               ((base)->IEEE_T_DROP)
8656 #define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
8657 #define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
8658 #define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
8659 #define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
8660 #define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
8661 #define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
8662 #define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
8663 #define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
8664 #define ENET_IEEE_T_SQE_REG(base)                ((base)->IEEE_T_SQE)
8665 #define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
8666 #define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
8667 #define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
8668 #define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
8669 #define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
8670 #define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
8671 #define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
8672 #define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
8673 #define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
8674 #define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
8675 #define ENET_RMON_R_RESVD_0_REG(base)            ((base)->RMON_R_RESVD_0)
8676 #define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
8677 #define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
8678 #define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
8679 #define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
8680 #define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
8681 #define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
8682 #define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
8683 #define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
8684 #define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
8685 #define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
8686 #define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
8687 #define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
8688 #define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
8689 #define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
8690 #define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
8691 #define ENET_ATCR_REG(base)                      ((base)->ATCR)
8692 #define ENET_ATVR_REG(base)                      ((base)->ATVR)
8693 #define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
8694 #define ENET_ATPER_REG(base)                     ((base)->ATPER)
8695 #define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
8696 #define ENET_ATINC_REG(base)                     ((base)->ATINC)
8697 #define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
8698 #define ENET_TGSR_REG(base)                      ((base)->TGSR)
8699 #define ENET_TCSR_REG(base,index)                ((base)->TC[index].TCSR)
8700 #define ENET_TCCR_REG(base,index)                ((base)->TC[index].TCCR)
8701 
8702 /*!
8703  * @}
8704  */ /* end of group ENET_Register_Accessor_Macros */
8705 
8706 /* ----------------------------------------------------------------------------
8707    -- ENET Register Masks
8708    ---------------------------------------------------------------------------- */
8709 
8710 /*!
8711  * @addtogroup ENET_Register_Masks ENET Register Masks
8712  * @{
8713  */
8714 
8715 /* EIR Bit Fields */
8716 #define ENET_EIR_RXB1_MASK                       0x1u
8717 #define ENET_EIR_RXB1_SHIFT                      0
8718 #define ENET_EIR_RXF1_MASK                       0x2u
8719 #define ENET_EIR_RXF1_SHIFT                      1
8720 #define ENET_EIR_TXB1_MASK                       0x4u
8721 #define ENET_EIR_TXB1_SHIFT                      2
8722 #define ENET_EIR_TXF1_MASK                       0x8u
8723 #define ENET_EIR_TXF1_SHIFT                      3
8724 #define ENET_EIR_RXB2_MASK                       0x10u
8725 #define ENET_EIR_RXB2_SHIFT                      4
8726 #define ENET_EIR_RXF2_MASK                       0x20u
8727 #define ENET_EIR_RXF2_SHIFT                      5
8728 #define ENET_EIR_TXB2_MASK                       0x40u
8729 #define ENET_EIR_TXB2_SHIFT                      6
8730 #define ENET_EIR_TXF2_MASK                       0x80u
8731 #define ENET_EIR_TXF2_SHIFT                      7
8732 #define ENET_EIR_RXFLUSH_0_MASK                  0x1000u
8733 #define ENET_EIR_RXFLUSH_0_SHIFT                 12
8734 #define ENET_EIR_RXFLUSH_1_MASK                  0x2000u
8735 #define ENET_EIR_RXFLUSH_1_SHIFT                 13
8736 #define ENET_EIR_RXFLUSH_2_MASK                  0x4000u
8737 #define ENET_EIR_RXFLUSH_2_SHIFT                 14
8738 #define ENET_EIR_TS_TIMER_MASK                   0x8000u
8739 #define ENET_EIR_TS_TIMER_SHIFT                  15
8740 #define ENET_EIR_TS_AVAIL_MASK                   0x10000u
8741 #define ENET_EIR_TS_AVAIL_SHIFT                  16
8742 #define ENET_EIR_WAKEUP_MASK                     0x20000u
8743 #define ENET_EIR_WAKEUP_SHIFT                    17
8744 #define ENET_EIR_PLR_MASK                        0x40000u
8745 #define ENET_EIR_PLR_SHIFT                       18
8746 #define ENET_EIR_UN_MASK                         0x80000u
8747 #define ENET_EIR_UN_SHIFT                        19
8748 #define ENET_EIR_RL_MASK                         0x100000u
8749 #define ENET_EIR_RL_SHIFT                        20
8750 #define ENET_EIR_LC_MASK                         0x200000u
8751 #define ENET_EIR_LC_SHIFT                        21
8752 #define ENET_EIR_EBERR_MASK                      0x400000u
8753 #define ENET_EIR_EBERR_SHIFT                     22
8754 #define ENET_EIR_MII_MASK                        0x800000u
8755 #define ENET_EIR_MII_SHIFT                       23
8756 #define ENET_EIR_RXB_MASK                        0x1000000u
8757 #define ENET_EIR_RXB_SHIFT                       24
8758 #define ENET_EIR_RXF_MASK                        0x2000000u
8759 #define ENET_EIR_RXF_SHIFT                       25
8760 #define ENET_EIR_TXB_MASK                        0x4000000u
8761 #define ENET_EIR_TXB_SHIFT                       26
8762 #define ENET_EIR_TXF_MASK                        0x8000000u
8763 #define ENET_EIR_TXF_SHIFT                       27
8764 #define ENET_EIR_GRA_MASK                        0x10000000u
8765 #define ENET_EIR_GRA_SHIFT                       28
8766 #define ENET_EIR_BABT_MASK                       0x20000000u
8767 #define ENET_EIR_BABT_SHIFT                      29
8768 #define ENET_EIR_BABR_MASK                       0x40000000u
8769 #define ENET_EIR_BABR_SHIFT                      30
8770 /* EIMR Bit Fields */
8771 #define ENET_EIMR_RXB1_MASK                      0x1u
8772 #define ENET_EIMR_RXB1_SHIFT                     0
8773 #define ENET_EIMR_RXF1_MASK                      0x2u
8774 #define ENET_EIMR_RXF1_SHIFT                     1
8775 #define ENET_EIMR_TXB1_MASK                      0x4u
8776 #define ENET_EIMR_TXB1_SHIFT                     2
8777 #define ENET_EIMR_TXF1_MASK                      0x8u
8778 #define ENET_EIMR_TXF1_SHIFT                     3
8779 #define ENET_EIMR_RXB2_MASK                      0x10u
8780 #define ENET_EIMR_RXB2_SHIFT                     4
8781 #define ENET_EIMR_RXF2_MASK                      0x20u
8782 #define ENET_EIMR_RXF2_SHIFT                     5
8783 #define ENET_EIMR_TXB2_MASK                      0x40u
8784 #define ENET_EIMR_TXB2_SHIFT                     6
8785 #define ENET_EIMR_TXF2_MASK                      0x80u
8786 #define ENET_EIMR_TXF2_SHIFT                     7
8787 #define ENET_EIMR_RXFLUSH_0_MASK                 0x1000u
8788 #define ENET_EIMR_RXFLUSH_0_SHIFT                12
8789 #define ENET_EIMR_RXFLUSH_1_MASK                 0x2000u
8790 #define ENET_EIMR_RXFLUSH_1_SHIFT                13
8791 #define ENET_EIMR_RXFLUSH_2_MASK                 0x4000u
8792 #define ENET_EIMR_RXFLUSH_2_SHIFT                14
8793 #define ENET_EIMR_TS_TIMER_MASK                  0x8000u
8794 #define ENET_EIMR_TS_TIMER_SHIFT                 15
8795 #define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
8796 #define ENET_EIMR_TS_AVAIL_SHIFT                 16
8797 #define ENET_EIMR_WAKEUP_MASK                    0x20000u
8798 #define ENET_EIMR_WAKEUP_SHIFT                   17
8799 #define ENET_EIMR_PLR_MASK                       0x40000u
8800 #define ENET_EIMR_PLR_SHIFT                      18
8801 #define ENET_EIMR_UN_MASK                        0x80000u
8802 #define ENET_EIMR_UN_SHIFT                       19
8803 #define ENET_EIMR_RL_MASK                        0x100000u
8804 #define ENET_EIMR_RL_SHIFT                       20
8805 #define ENET_EIMR_LC_MASK                        0x200000u
8806 #define ENET_EIMR_LC_SHIFT                       21
8807 #define ENET_EIMR_EBERR_MASK                     0x400000u
8808 #define ENET_EIMR_EBERR_SHIFT                    22
8809 #define ENET_EIMR_MII_MASK                       0x800000u
8810 #define ENET_EIMR_MII_SHIFT                      23
8811 #define ENET_EIMR_RXB_MASK                       0x1000000u
8812 #define ENET_EIMR_RXB_SHIFT                      24
8813 #define ENET_EIMR_RXF_MASK                       0x2000000u
8814 #define ENET_EIMR_RXF_SHIFT                      25
8815 #define ENET_EIMR_TXB_MASK                       0x4000000u
8816 #define ENET_EIMR_TXB_SHIFT                      26
8817 #define ENET_EIMR_TXF_MASK                       0x8000000u
8818 #define ENET_EIMR_TXF_SHIFT                      27
8819 #define ENET_EIMR_GRA_MASK                       0x10000000u
8820 #define ENET_EIMR_GRA_SHIFT                      28
8821 #define ENET_EIMR_BABT_MASK                      0x20000000u
8822 #define ENET_EIMR_BABT_SHIFT                     29
8823 #define ENET_EIMR_BABR_MASK                      0x40000000u
8824 #define ENET_EIMR_BABR_SHIFT                     30
8825 /* RDAR Bit Fields */
8826 #define ENET_RDAR_RDAR_MASK                      0x1000000u
8827 #define ENET_RDAR_RDAR_SHIFT                     24
8828 /* TDAR Bit Fields */
8829 #define ENET_TDAR_TDAR_MASK                      0x1000000u
8830 #define ENET_TDAR_TDAR_SHIFT                     24
8831 /* ECR Bit Fields */
8832 #define ENET_ECR_RESET_MASK                      0x1u
8833 #define ENET_ECR_RESET_SHIFT                     0
8834 #define ENET_ECR_ETHEREN_MASK                    0x2u
8835 #define ENET_ECR_ETHEREN_SHIFT                   1
8836 #define ENET_ECR_MAGICEN_MASK                    0x4u
8837 #define ENET_ECR_MAGICEN_SHIFT                   2
8838 #define ENET_ECR_SLEEP_MASK                      0x8u
8839 #define ENET_ECR_SLEEP_SHIFT                     3
8840 #define ENET_ECR_EN1588_MASK                     0x10u
8841 #define ENET_ECR_EN1588_SHIFT                    4
8842 #define ENET_ECR_SPEED_MASK                      0x20u
8843 #define ENET_ECR_SPEED_SHIFT                     5
8844 #define ENET_ECR_DBGEN_MASK                      0x40u
8845 #define ENET_ECR_DBGEN_SHIFT                     6
8846 #define ENET_ECR_DBSWP_MASK                      0x100u
8847 #define ENET_ECR_DBSWP_SHIFT                     8
8848 #define ENET_ECR_SVLANEN_MASK                    0x200u
8849 #define ENET_ECR_SVLANEN_SHIFT                   9
8850 #define ENET_ECR_VLANUSE2ND_MASK                 0x400u
8851 #define ENET_ECR_VLANUSE2ND_SHIFT                10
8852 #define ENET_ECR_SVLANDBL_MASK                   0x800u
8853 #define ENET_ECR_SVLANDBL_SHIFT                  11
8854 /* MMFR Bit Fields */
8855 #define ENET_MMFR_DATA_MASK                      0xFFFFu
8856 #define ENET_MMFR_DATA_SHIFT                     0
8857 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
8858 #define ENET_MMFR_TA_MASK                        0x30000u
8859 #define ENET_MMFR_TA_SHIFT                       16
8860 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
8861 #define ENET_MMFR_RA_MASK                        0x7C0000u
8862 #define ENET_MMFR_RA_SHIFT                       18
8863 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
8864 #define ENET_MMFR_PA_MASK                        0xF800000u
8865 #define ENET_MMFR_PA_SHIFT                       23
8866 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
8867 #define ENET_MMFR_OP_MASK                        0x30000000u
8868 #define ENET_MMFR_OP_SHIFT                       28
8869 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
8870 #define ENET_MMFR_ST_MASK                        0xC0000000u
8871 #define ENET_MMFR_ST_SHIFT                       30
8872 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
8873 /* MSCR Bit Fields */
8874 #define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
8875 #define ENET_MSCR_MII_SPEED_SHIFT                1
8876 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
8877 #define ENET_MSCR_DIS_PRE_MASK                   0x80u
8878 #define ENET_MSCR_DIS_PRE_SHIFT                  7
8879 #define ENET_MSCR_HOLDTIME_MASK                  0x700u
8880 #define ENET_MSCR_HOLDTIME_SHIFT                 8
8881 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
8882 /* MIBC Bit Fields */
8883 #define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
8884 #define ENET_MIBC_MIB_CLEAR_SHIFT                29
8885 #define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
8886 #define ENET_MIBC_MIB_IDLE_SHIFT                 30
8887 #define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
8888 #define ENET_MIBC_MIB_DIS_SHIFT                  31
8889 /* RCR Bit Fields */
8890 #define ENET_RCR_LOOP_MASK                       0x1u
8891 #define ENET_RCR_LOOP_SHIFT                      0
8892 #define ENET_RCR_DRT_MASK                        0x2u
8893 #define ENET_RCR_DRT_SHIFT                       1
8894 #define ENET_RCR_MII_MODE_MASK                   0x4u
8895 #define ENET_RCR_MII_MODE_SHIFT                  2
8896 #define ENET_RCR_PROM_MASK                       0x8u
8897 #define ENET_RCR_PROM_SHIFT                      3
8898 #define ENET_RCR_BC_REJ_MASK                     0x10u
8899 #define ENET_RCR_BC_REJ_SHIFT                    4
8900 #define ENET_RCR_FCE_MASK                        0x20u
8901 #define ENET_RCR_FCE_SHIFT                       5
8902 #define ENET_RCR_RGMII_EN_MASK                   0x40u
8903 #define ENET_RCR_RGMII_EN_SHIFT                  6
8904 #define ENET_RCR_RMII_MODE_MASK                  0x100u
8905 #define ENET_RCR_RMII_MODE_SHIFT                 8
8906 #define ENET_RCR_RMII_10T_MASK                   0x200u
8907 #define ENET_RCR_RMII_10T_SHIFT                  9
8908 #define ENET_RCR_PADEN_MASK                      0x1000u
8909 #define ENET_RCR_PADEN_SHIFT                     12
8910 #define ENET_RCR_PAUFWD_MASK                     0x2000u
8911 #define ENET_RCR_PAUFWD_SHIFT                    13
8912 #define ENET_RCR_CRCFWD_MASK                     0x4000u
8913 #define ENET_RCR_CRCFWD_SHIFT                    14
8914 #define ENET_RCR_CFEN_MASK                       0x8000u
8915 #define ENET_RCR_CFEN_SHIFT                      15
8916 #define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
8917 #define ENET_RCR_MAX_FL_SHIFT                    16
8918 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
8919 #define ENET_RCR_NLC_MASK                        0x40000000u
8920 #define ENET_RCR_NLC_SHIFT                       30
8921 #define ENET_RCR_GRS_MASK                        0x80000000u
8922 #define ENET_RCR_GRS_SHIFT                       31
8923 /* TCR Bit Fields */
8924 #define ENET_TCR_GTS_MASK                        0x1u
8925 #define ENET_TCR_GTS_SHIFT                       0
8926 #define ENET_TCR_FDEN_MASK                       0x4u
8927 #define ENET_TCR_FDEN_SHIFT                      2
8928 #define ENET_TCR_TFC_PAUSE_MASK                  0x8u
8929 #define ENET_TCR_TFC_PAUSE_SHIFT                 3
8930 #define ENET_TCR_RFC_PAUSE_MASK                  0x10u
8931 #define ENET_TCR_RFC_PAUSE_SHIFT                 4
8932 #define ENET_TCR_ADDSEL_MASK                     0xE0u
8933 #define ENET_TCR_ADDSEL_SHIFT                    5
8934 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
8935 #define ENET_TCR_ADDINS_MASK                     0x100u
8936 #define ENET_TCR_ADDINS_SHIFT                    8
8937 #define ENET_TCR_CRCFWD_MASK                     0x200u
8938 #define ENET_TCR_CRCFWD_SHIFT                    9
8939 /* PALR Bit Fields */
8940 #define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
8941 #define ENET_PALR_PADDR1_SHIFT                   0
8942 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
8943 /* PAUR Bit Fields */
8944 #define ENET_PAUR_TYPE_MASK                      0xFFFFu
8945 #define ENET_PAUR_TYPE_SHIFT                     0
8946 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
8947 #define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
8948 #define ENET_PAUR_PADDR2_SHIFT                   16
8949 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
8950 /* OPD Bit Fields */
8951 #define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
8952 #define ENET_OPD_PAUSE_DUR_SHIFT                 0
8953 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
8954 #define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
8955 #define ENET_OPD_OPCODE_SHIFT                    16
8956 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
8957 /* TXIC Bit Fields */
8958 #define ENET_TXIC_ICTT_MASK                      0xFFFFu
8959 #define ENET_TXIC_ICTT_SHIFT                     0
8960 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICTT_SHIFT))&ENET_TXIC_ICTT_MASK)
8961 #define ENET_TXIC_ICFT_MASK                      0xFF00000u
8962 #define ENET_TXIC_ICFT_SHIFT                     20
8963 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICFT_SHIFT))&ENET_TXIC_ICFT_MASK)
8964 #define ENET_TXIC_ICCS_MASK                      0x40000000u
8965 #define ENET_TXIC_ICCS_SHIFT                     30
8966 #define ENET_TXIC_ICEN_MASK                      0x80000000u
8967 #define ENET_TXIC_ICEN_SHIFT                     31
8968 /* RXIC Bit Fields */
8969 #define ENET_RXIC_ICTT_MASK                      0xFFFFu
8970 #define ENET_RXIC_ICTT_SHIFT                     0
8971 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICTT_SHIFT))&ENET_RXIC_ICTT_MASK)
8972 #define ENET_RXIC_ICFT_MASK                      0xFF00000u
8973 #define ENET_RXIC_ICFT_SHIFT                     20
8974 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICFT_SHIFT))&ENET_RXIC_ICFT_MASK)
8975 #define ENET_RXIC_ICCS_MASK                      0x40000000u
8976 #define ENET_RXIC_ICCS_SHIFT                     30
8977 #define ENET_RXIC_ICEN_MASK                      0x80000000u
8978 #define ENET_RXIC_ICEN_SHIFT                     31
8979 /* IAUR Bit Fields */
8980 #define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
8981 #define ENET_IAUR_IADDR1_SHIFT                   0
8982 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
8983 /* IALR Bit Fields */
8984 #define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
8985 #define ENET_IALR_IADDR2_SHIFT                   0
8986 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
8987 /* GAUR Bit Fields */
8988 #define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
8989 #define ENET_GAUR_GADDR1_SHIFT                   0
8990 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
8991 /* GALR Bit Fields */
8992 #define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
8993 #define ENET_GALR_GADDR2_SHIFT                   0
8994 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
8995 /* TFWR Bit Fields */
8996 #define ENET_TFWR_TFWR_MASK                      0x3Fu
8997 #define ENET_TFWR_TFWR_SHIFT                     0
8998 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
8999 #define ENET_TFWR_STRFWD_MASK                    0x100u
9000 #define ENET_TFWR_STRFWD_SHIFT                   8
9001 /* RDSR1 Bit Fields */
9002 #define ENET_RDSR1_R_DES_START_MASK              0xFFFFFFF8u
9003 #define ENET_RDSR1_R_DES_START_SHIFT             3
9004 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR1_R_DES_START_SHIFT))&ENET_RDSR1_R_DES_START_MASK)
9005 /* TDSR1 Bit Fields */
9006 #define ENET_TDSR1_X_DES_START_MASK              0xFFFFFFF8u
9007 #define ENET_TDSR1_X_DES_START_SHIFT             3
9008 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK)
9009 /* MRBR1 Bit Fields */
9010 #define ENET_MRBR1_R_BUF_SIZE_MASK               0x7F0u
9011 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              4
9012 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK)
9013 /* RDSR2 Bit Fields */
9014 #define ENET_RDSR2_R_DES_START_MASK              0xFFFFFFF8u
9015 #define ENET_RDSR2_R_DES_START_SHIFT             3
9016 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR2_R_DES_START_SHIFT))&ENET_RDSR2_R_DES_START_MASK)
9017 /* TDSR2 Bit Fields */
9018 #define ENET_TDSR2_X_DES_START_MASK              0xFFFFFFF8u
9019 #define ENET_TDSR2_X_DES_START_SHIFT             3
9020 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK)
9021 /* MRBR2 Bit Fields */
9022 #define ENET_MRBR2_R_BUF_SIZE_MASK               0x7F0u
9023 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              4
9024 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK)
9025 /* RDSR Bit Fields */
9026 #define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
9027 #define ENET_RDSR_R_DES_START_SHIFT              3
9028 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
9029 /* TDSR Bit Fields */
9030 #define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
9031 #define ENET_TDSR_X_DES_START_SHIFT              3
9032 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
9033 /* MRBR Bit Fields */
9034 #define ENET_MRBR_R_BUF_SIZE_MASK                0x7F0u
9035 #define ENET_MRBR_R_BUF_SIZE_SHIFT               4
9036 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
9037 /* RSFL Bit Fields */
9038 #define ENET_RSFL_RX_SECTION_FULL_MASK           0x3FFu
9039 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
9040 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
9041 /* RSEM Bit Fields */
9042 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          0x3FFu
9043 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
9044 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
9045 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
9046 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
9047 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
9048 /* RAEM Bit Fields */
9049 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0x3FFu
9050 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
9051 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
9052 /* RAFL Bit Fields */
9053 #define ENET_RAFL_RX_ALMOST_FULL_MASK            0x3FFu
9054 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
9055 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
9056 /* TSEM Bit Fields */
9057 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          0x3FFu
9058 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
9059 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
9060 /* TAEM Bit Fields */
9061 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0x3FFu
9062 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
9063 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
9064 /* TAFL Bit Fields */
9065 #define ENET_TAFL_TX_ALMOST_FULL_MASK            0x3FFu
9066 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
9067 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
9068 /* TIPG Bit Fields */
9069 #define ENET_TIPG_IPG_MASK                       0x1Fu
9070 #define ENET_TIPG_IPG_SHIFT                      0
9071 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
9072 /* FTRL Bit Fields */
9073 #define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
9074 #define ENET_FTRL_TRUNC_FL_SHIFT                 0
9075 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
9076 /* TACC Bit Fields */
9077 #define ENET_TACC_SHIFT16_MASK                   0x1u
9078 #define ENET_TACC_SHIFT16_SHIFT                  0
9079 #define ENET_TACC_IPCHK_MASK                     0x8u
9080 #define ENET_TACC_IPCHK_SHIFT                    3
9081 #define ENET_TACC_PROCHK_MASK                    0x10u
9082 #define ENET_TACC_PROCHK_SHIFT                   4
9083 /* RACC Bit Fields */
9084 #define ENET_RACC_PADREM_MASK                    0x1u
9085 #define ENET_RACC_PADREM_SHIFT                   0
9086 #define ENET_RACC_IPDIS_MASK                     0x2u
9087 #define ENET_RACC_IPDIS_SHIFT                    1
9088 #define ENET_RACC_PRODIS_MASK                    0x4u
9089 #define ENET_RACC_PRODIS_SHIFT                   2
9090 #define ENET_RACC_LINEDIS_MASK                   0x40u
9091 #define ENET_RACC_LINEDIS_SHIFT                  6
9092 #define ENET_RACC_SHIFT16_MASK                   0x80u
9093 #define ENET_RACC_SHIFT16_SHIFT                  7
9094 /* RCMR Bit Fields */
9095 #define ENET_RCMR_CMP0_MASK                      0x7u
9096 #define ENET_RCMR_CMP0_SHIFT                     0
9097 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP0_SHIFT))&ENET_RCMR_CMP0_MASK)
9098 #define ENET_RCMR_CMP1_MASK                      0x70u
9099 #define ENET_RCMR_CMP1_SHIFT                     4
9100 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP1_SHIFT))&ENET_RCMR_CMP1_MASK)
9101 #define ENET_RCMR_CMP2_MASK                      0x700u
9102 #define ENET_RCMR_CMP2_SHIFT                     8
9103 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP2_SHIFT))&ENET_RCMR_CMP2_MASK)
9104 #define ENET_RCMR_CMP3_MASK                      0x7000u
9105 #define ENET_RCMR_CMP3_SHIFT                     12
9106 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP3_SHIFT))&ENET_RCMR_CMP3_MASK)
9107 #define ENET_RCMR_MATCHEN_MASK                   0x10000u
9108 #define ENET_RCMR_MATCHEN_SHIFT                  16
9109 /* DMACFG Bit Fields */
9110 #define ENET_DMACFG_IDLE_SLOPE_MASK              0xFFFFu
9111 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             0
9112 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x))<<ENET_DMACFG_IDLE_SLOPE_SHIFT))&ENET_DMACFG_IDLE_SLOPE_MASK)
9113 #define ENET_DMACFG_DMA_CLASS_EN_MASK            0x10000u
9114 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           16
9115 #define ENET_DMACFG_CALC_NOIPG_MASK              0x20000u
9116 #define ENET_DMACFG_CALC_NOIPG_SHIFT             17
9117 /* RDAR1 Bit Fields */
9118 #define ENET_RDAR1_RDAR_MASK                     0x1000000u
9119 #define ENET_RDAR1_RDAR_SHIFT                    24
9120 /* TDAR1 Bit Fields */
9121 #define ENET_TDAR1_TDAR_MASK                     0x1000000u
9122 #define ENET_TDAR1_TDAR_SHIFT                    24
9123 /* RDAR2 Bit Fields */
9124 #define ENET_RDAR2_RDAR_MASK                     0x1000000u
9125 #define ENET_RDAR2_RDAR_SHIFT                    24
9126 /* TDAR2 Bit Fields */
9127 #define ENET_TDAR2_TDAR_MASK                     0x1000000u
9128 #define ENET_TDAR2_TDAR_SHIFT                    24
9129 /* QOS Bit Fields */
9130 #define ENET_QOS_TX_SCHEME_MASK                  0x7u
9131 #define ENET_QOS_TX_SCHEME_SHIFT                 0
9132 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_QOS_TX_SCHEME_SHIFT))&ENET_QOS_TX_SCHEME_MASK)
9133 #define ENET_QOS_RX_FLUSH0_MASK                  0x8u
9134 #define ENET_QOS_RX_FLUSH0_SHIFT                 3
9135 #define ENET_QOS_RX_FLUSH1_MASK                  0x10u
9136 #define ENET_QOS_RX_FLUSH1_SHIFT                 4
9137 #define ENET_QOS_RX_FLUSH2_MASK                  0x20u
9138 #define ENET_QOS_RX_FLUSH2_SHIFT                 5
9139 /* RMON_T_DROP Bit Fields */
9140 #define ENET_RMON_T_DROP_INCCNTF_MASK            0xFFFFu
9141 #define ENET_RMON_T_DROP_INCCNTF_SHIFT           0
9142 #define ENET_RMON_T_DROP_INCCNTF(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_DROP_INCCNTF_SHIFT))&ENET_RMON_T_DROP_INCCNTF_MASK)
9143 /* RMON_T_PACKETS Bit Fields */
9144 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
9145 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
9146 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
9147 /* RMON_T_BC_PKT Bit Fields */
9148 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
9149 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
9150 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
9151 /* RMON_T_MC_PKT Bit Fields */
9152 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
9153 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
9154 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
9155 /* RMON_T_CRC_ALIGN Bit Fields */
9156 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
9157 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
9158 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
9159 /* RMON_T_UNDERSIZE Bit Fields */
9160 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
9161 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
9162 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
9163 /* RMON_T_OVERSIZE Bit Fields */
9164 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
9165 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
9166 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
9167 /* RMON_T_FRAG Bit Fields */
9168 #define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
9169 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
9170 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
9171 /* RMON_T_JAB Bit Fields */
9172 #define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
9173 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
9174 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
9175 /* RMON_T_COL Bit Fields */
9176 #define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
9177 #define ENET_RMON_T_COL_TXPKTS_SHIFT             0
9178 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
9179 /* RMON_T_P64 Bit Fields */
9180 #define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
9181 #define ENET_RMON_T_P64_TXPKTS_SHIFT             0
9182 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
9183 /* RMON_T_P65TO127 Bit Fields */
9184 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
9185 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
9186 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
9187 /* RMON_T_P128TO255 Bit Fields */
9188 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
9189 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
9190 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
9191 /* RMON_T_P256TO511 Bit Fields */
9192 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
9193 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
9194 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
9195 /* RMON_T_P512TO1023 Bit Fields */
9196 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
9197 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
9198 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
9199 /* RMON_T_P1024TO2047 Bit Fields */
9200 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
9201 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
9202 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
9203 /* RMON_T_P_GTE2048 Bit Fields */
9204 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
9205 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
9206 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
9207 /* RMON_T_OCTETS Bit Fields */
9208 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
9209 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
9210 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
9211 /* IEEE_T_DROP Bit Fields */
9212 #define ENET_IEEE_T_DROP_COUNT_MASK              0xFFFFu
9213 #define ENET_IEEE_T_DROP_COUNT_SHIFT             0
9214 #define ENET_IEEE_T_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DROP_COUNT_SHIFT))&ENET_IEEE_T_DROP_COUNT_MASK)
9215 /* IEEE_T_FRAME_OK Bit Fields */
9216 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
9217 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
9218 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
9219 /* IEEE_T_1COL Bit Fields */
9220 #define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
9221 #define ENET_IEEE_T_1COL_COUNT_SHIFT             0
9222 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
9223 /* IEEE_T_MCOL Bit Fields */
9224 #define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
9225 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
9226 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
9227 /* IEEE_T_DEF Bit Fields */
9228 #define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
9229 #define ENET_IEEE_T_DEF_COUNT_SHIFT              0
9230 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
9231 /* IEEE_T_LCOL Bit Fields */
9232 #define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
9233 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
9234 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
9235 /* IEEE_T_EXCOL Bit Fields */
9236 #define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
9237 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
9238 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
9239 /* IEEE_T_MACERR Bit Fields */
9240 #define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
9241 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
9242 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
9243 /* IEEE_T_CSERR Bit Fields */
9244 #define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
9245 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
9246 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
9247 /* IEEE_T_SQE Bit Fields */
9248 #define ENET_IEEE_T_SQE_COUNT_MASK               0xFFFFu
9249 #define ENET_IEEE_T_SQE_COUNT_SHIFT              0
9250 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK)
9251 /* IEEE_T_FDXFC Bit Fields */
9252 #define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
9253 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
9254 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
9255 /* IEEE_T_OCTETS_OK Bit Fields */
9256 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
9257 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
9258 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
9259 /* RMON_R_PACKETS Bit Fields */
9260 #define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
9261 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
9262 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
9263 /* RMON_R_BC_PKT Bit Fields */
9264 #define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
9265 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
9266 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
9267 /* RMON_R_MC_PKT Bit Fields */
9268 #define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
9269 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
9270 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
9271 /* RMON_R_CRC_ALIGN Bit Fields */
9272 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
9273 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
9274 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
9275 /* RMON_R_UNDERSIZE Bit Fields */
9276 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
9277 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
9278 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
9279 /* RMON_R_OVERSIZE Bit Fields */
9280 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
9281 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
9282 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
9283 /* RMON_R_FRAG Bit Fields */
9284 #define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
9285 #define ENET_RMON_R_FRAG_COUNT_SHIFT             0
9286 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
9287 /* RMON_R_JAB Bit Fields */
9288 #define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
9289 #define ENET_RMON_R_JAB_COUNT_SHIFT              0
9290 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
9291 /* RMON_R_RESVD_0 Bit Fields */
9292 /* RMON_R_P64 Bit Fields */
9293 #define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
9294 #define ENET_RMON_R_P64_COUNT_SHIFT              0
9295 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
9296 /* RMON_R_P65TO127 Bit Fields */
9297 #define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
9298 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
9299 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
9300 /* RMON_R_P128TO255 Bit Fields */
9301 #define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
9302 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
9303 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
9304 /* RMON_R_P256TO511 Bit Fields */
9305 #define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
9306 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
9307 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
9308 /* RMON_R_P512TO1023 Bit Fields */
9309 #define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
9310 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
9311 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
9312 /* RMON_R_P1024TO2047 Bit Fields */
9313 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
9314 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
9315 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
9316 /* RMON_R_P_GTE2048 Bit Fields */
9317 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
9318 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
9319 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
9320 /* RMON_R_OCTETS Bit Fields */
9321 #define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
9322 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
9323 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
9324 /* IEEE_R_DROP Bit Fields */
9325 #define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
9326 #define ENET_IEEE_R_DROP_COUNT_SHIFT             0
9327 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
9328 /* IEEE_R_FRAME_OK Bit Fields */
9329 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
9330 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
9331 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
9332 /* IEEE_R_CRC Bit Fields */
9333 #define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
9334 #define ENET_IEEE_R_CRC_COUNT_SHIFT              0
9335 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
9336 /* IEEE_R_ALIGN Bit Fields */
9337 #define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
9338 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
9339 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
9340 /* IEEE_R_MACERR Bit Fields */
9341 #define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
9342 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
9343 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
9344 /* IEEE_R_FDXFC Bit Fields */
9345 #define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
9346 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
9347 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
9348 /* IEEE_R_OCTETS_OK Bit Fields */
9349 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
9350 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
9351 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
9352 /* ATCR Bit Fields */
9353 #define ENET_ATCR_EN_MASK                        0x1u
9354 #define ENET_ATCR_EN_SHIFT                       0
9355 #define ENET_ATCR_OFFEN_MASK                     0x4u
9356 #define ENET_ATCR_OFFEN_SHIFT                    2
9357 #define ENET_ATCR_OFFRST_MASK                    0x8u
9358 #define ENET_ATCR_OFFRST_SHIFT                   3
9359 #define ENET_ATCR_PEREN_MASK                     0x10u
9360 #define ENET_ATCR_PEREN_SHIFT                    4
9361 #define ENET_ATCR_PINPER_MASK                    0x80u
9362 #define ENET_ATCR_PINPER_SHIFT                   7
9363 #define ENET_ATCR_RESTART_MASK                   0x200u
9364 #define ENET_ATCR_RESTART_SHIFT                  9
9365 #define ENET_ATCR_CAPTURE_MASK                   0x800u
9366 #define ENET_ATCR_CAPTURE_SHIFT                  11
9367 #define ENET_ATCR_SLAVE_MASK                     0x2000u
9368 #define ENET_ATCR_SLAVE_SHIFT                    13
9369 /* ATVR Bit Fields */
9370 #define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
9371 #define ENET_ATVR_ATIME_SHIFT                    0
9372 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
9373 /* ATOFF Bit Fields */
9374 #define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
9375 #define ENET_ATOFF_OFFSET_SHIFT                  0
9376 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
9377 /* ATPER Bit Fields */
9378 #define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
9379 #define ENET_ATPER_PERIOD_SHIFT                  0
9380 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
9381 /* ATCOR Bit Fields */
9382 #define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
9383 #define ENET_ATCOR_COR_SHIFT                     0
9384 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
9385 /* ATINC Bit Fields */
9386 #define ENET_ATINC_INC_MASK                      0x7Fu
9387 #define ENET_ATINC_INC_SHIFT                     0
9388 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
9389 #define ENET_ATINC_INC_CORR_MASK                 0x7F00u
9390 #define ENET_ATINC_INC_CORR_SHIFT                8
9391 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
9392 /* ATSTMP Bit Fields */
9393 #define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
9394 #define ENET_ATSTMP_TIMESTAMP_SHIFT              0
9395 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
9396 /* TGSR Bit Fields */
9397 #define ENET_TGSR_TF0_MASK                       0x1u
9398 #define ENET_TGSR_TF0_SHIFT                      0
9399 #define ENET_TGSR_TF1_MASK                       0x2u
9400 #define ENET_TGSR_TF1_SHIFT                      1
9401 #define ENET_TGSR_TF2_MASK                       0x4u
9402 #define ENET_TGSR_TF2_SHIFT                      2
9403 #define ENET_TGSR_TF3_MASK                       0x8u
9404 #define ENET_TGSR_TF3_SHIFT                      3
9405 /* TCSR Bit Fields */
9406 #define ENET_TCSR_TDRE_MASK                      0x1u
9407 #define ENET_TCSR_TDRE_SHIFT                     0
9408 #define ENET_TCSR_TMODE_MASK                     0x3Cu
9409 #define ENET_TCSR_TMODE_SHIFT                    2
9410 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
9411 #define ENET_TCSR_TIE_MASK                       0x40u
9412 #define ENET_TCSR_TIE_SHIFT                      6
9413 #define ENET_TCSR_TF_MASK                        0x80u
9414 #define ENET_TCSR_TF_SHIFT                       7
9415 /* TCCR Bit Fields */
9416 #define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
9417 #define ENET_TCCR_TCC_SHIFT                      0
9418 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
9419 
9420 /*!
9421  * @}
9422  */ /* end of group ENET_Register_Masks */
9423 
9424 /* ENET - Peripheral instance base addresses */
9425 /** Peripheral ENET1 base address */
9426 #define ENET1_BASE                               (0x42188000u)
9427 /** Peripheral ENET1 base pointer */
9428 #define ENET1                                    ((ENET_Type *)ENET1_BASE)
9429 #define ENET1_BASE_PTR                           (ENET1)
9430 /** Peripheral ENET2 base address */
9431 #define ENET2_BASE                               (0x421B4000u)
9432 /** Peripheral ENET2 base pointer */
9433 #define ENET2                                    ((ENET_Type *)ENET2_BASE)
9434 #define ENET2_BASE_PTR                           (ENET2)
9435 /** Array initializer of ENET peripheral base addresses */
9436 #define ENET_BASE_ADDRS                          { ENET1_BASE, ENET2_BASE }
9437 /** Array initializer of ENET peripheral base pointers */
9438 #define ENET_BASE_PTRS                           { ENET1, ENET2 }
9439 
9440 /* ----------------------------------------------------------------------------
9441    -- ENET - Register accessor macros
9442    ---------------------------------------------------------------------------- */
9443 
9444 /*!
9445  * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
9446  * @{
9447  */
9448 
9449 
9450 /* ENET - Register instance definitions */
9451 /* ENET1 */
9452 #define ENET1_EIR                                ENET_EIR_REG(ENET1_BASE_PTR)
9453 #define ENET1_EIMR                               ENET_EIMR_REG(ENET1_BASE_PTR)
9454 #define ENET1_RDAR                               ENET_RDAR_REG(ENET1_BASE_PTR)
9455 #define ENET1_TDAR                               ENET_TDAR_REG(ENET1_BASE_PTR)
9456 #define ENET1_ECR                                ENET_ECR_REG(ENET1_BASE_PTR)
9457 #define ENET1_MMFR                               ENET_MMFR_REG(ENET1_BASE_PTR)
9458 #define ENET1_MSCR                               ENET_MSCR_REG(ENET1_BASE_PTR)
9459 #define ENET1_MIBC                               ENET_MIBC_REG(ENET1_BASE_PTR)
9460 #define ENET1_RCR                                ENET_RCR_REG(ENET1_BASE_PTR)
9461 #define ENET1_TCR                                ENET_TCR_REG(ENET1_BASE_PTR)
9462 #define ENET1_PALR                               ENET_PALR_REG(ENET1_BASE_PTR)
9463 #define ENET1_PAUR                               ENET_PAUR_REG(ENET1_BASE_PTR)
9464 #define ENET1_OPD                                ENET_OPD_REG(ENET1_BASE_PTR)
9465 #define ENET1_TXIC0                              ENET_TXIC_REG(ENET1_BASE_PTR,0)
9466 #define ENET1_TXIC1                              ENET_TXIC_REG(ENET1_BASE_PTR,1)
9467 #define ENET1_TXIC2                              ENET_TXIC_REG(ENET1_BASE_PTR,2)
9468 #define ENET1_RXIC0                              ENET_RXIC_REG(ENET1_BASE_PTR,0)
9469 #define ENET1_RXIC1                              ENET_RXIC_REG(ENET1_BASE_PTR,1)
9470 #define ENET1_RXIC2                              ENET_RXIC_REG(ENET1_BASE_PTR,2)
9471 #define ENET1_IAUR                               ENET_IAUR_REG(ENET1_BASE_PTR)
9472 #define ENET1_IALR                               ENET_IALR_REG(ENET1_BASE_PTR)
9473 #define ENET1_GAUR                               ENET_GAUR_REG(ENET1_BASE_PTR)
9474 #define ENET1_GALR                               ENET_GALR_REG(ENET1_BASE_PTR)
9475 #define ENET1_TFWR                               ENET_TFWR_REG(ENET1_BASE_PTR)
9476 #define ENET1_RDSR1                              ENET_RDSR1_REG(ENET1_BASE_PTR)
9477 #define ENET1_TDSR1                              ENET_TDSR1_REG(ENET1_BASE_PTR)
9478 #define ENET1_MRBR1                              ENET_MRBR1_REG(ENET1_BASE_PTR)
9479 #define ENET1_RDSR2                              ENET_RDSR2_REG(ENET1_BASE_PTR)
9480 #define ENET1_TDSR2                              ENET_TDSR2_REG(ENET1_BASE_PTR)
9481 #define ENET1_MRBR2                              ENET_MRBR2_REG(ENET1_BASE_PTR)
9482 #define ENET1_RDSR                               ENET_RDSR_REG(ENET1_BASE_PTR)
9483 #define ENET1_TDSR                               ENET_TDSR_REG(ENET1_BASE_PTR)
9484 #define ENET1_MRBR                               ENET_MRBR_REG(ENET1_BASE_PTR)
9485 #define ENET1_RSFL                               ENET_RSFL_REG(ENET1_BASE_PTR)
9486 #define ENET1_RSEM                               ENET_RSEM_REG(ENET1_BASE_PTR)
9487 #define ENET1_RAEM                               ENET_RAEM_REG(ENET1_BASE_PTR)
9488 #define ENET1_RAFL                               ENET_RAFL_REG(ENET1_BASE_PTR)
9489 #define ENET1_TSEM                               ENET_TSEM_REG(ENET1_BASE_PTR)
9490 #define ENET1_TAEM                               ENET_TAEM_REG(ENET1_BASE_PTR)
9491 #define ENET1_TAFL                               ENET_TAFL_REG(ENET1_BASE_PTR)
9492 #define ENET1_TIPG                               ENET_TIPG_REG(ENET1_BASE_PTR)
9493 #define ENET1_FTRL                               ENET_FTRL_REG(ENET1_BASE_PTR)
9494 #define ENET1_TACC                               ENET_TACC_REG(ENET1_BASE_PTR)
9495 #define ENET1_RACC                               ENET_RACC_REG(ENET1_BASE_PTR)
9496 #define ENET1_RCMR1                              ENET_RCMR_REG(ENET1_BASE_PTR,0)
9497 #define ENET1_RCMR2                              ENET_RCMR_REG(ENET1_BASE_PTR,1)
9498 #define ENET1_DMA1CFG                            ENET_DMACFG_REG(ENET1_BASE_PTR,0)
9499 #define ENET1_DMA2CFG                            ENET_DMACFG_REG(ENET1_BASE_PTR,1)
9500 #define ENET1_RDAR1                              ENET_RDAR1_REG(ENET1_BASE_PTR)
9501 #define ENET1_TDAR1                              ENET_TDAR1_REG(ENET1_BASE_PTR)
9502 #define ENET1_RDAR2                              ENET_RDAR2_REG(ENET1_BASE_PTR)
9503 #define ENET1_TDAR2                              ENET_TDAR2_REG(ENET1_BASE_PTR)
9504 #define ENET1_QOS                                ENET_QOS_REG(ENET1_BASE_PTR)
9505 #define ENET1_RMON_T_DROP                        ENET_RMON_T_DROP_REG(ENET1_BASE_PTR)
9506 #define ENET1_RMON_T_PACKETS                     ENET_RMON_T_PACKETS_REG(ENET1_BASE_PTR)
9507 #define ENET1_RMON_T_BC_PKT                      ENET_RMON_T_BC_PKT_REG(ENET1_BASE_PTR)
9508 #define ENET1_RMON_T_MC_PKT                      ENET_RMON_T_MC_PKT_REG(ENET1_BASE_PTR)
9509 #define ENET1_RMON_T_CRC_ALIGN                   ENET_RMON_T_CRC_ALIGN_REG(ENET1_BASE_PTR)
9510 #define ENET1_RMON_T_UNDERSIZE                   ENET_RMON_T_UNDERSIZE_REG(ENET1_BASE_PTR)
9511 #define ENET1_RMON_T_OVERSIZE                    ENET_RMON_T_OVERSIZE_REG(ENET1_BASE_PTR)
9512 #define ENET1_RMON_T_FRAG                        ENET_RMON_T_FRAG_REG(ENET1_BASE_PTR)
9513 #define ENET1_RMON_T_JAB                         ENET_RMON_T_JAB_REG(ENET1_BASE_PTR)
9514 #define ENET1_RMON_T_COL                         ENET_RMON_T_COL_REG(ENET1_BASE_PTR)
9515 #define ENET1_RMON_T_P64                         ENET_RMON_T_P64_REG(ENET1_BASE_PTR)
9516 #define ENET1_RMON_T_P65TO127                    ENET_RMON_T_P65TO127_REG(ENET1_BASE_PTR)
9517 #define ENET1_RMON_T_P128TO255                   ENET_RMON_T_P128TO255_REG(ENET1_BASE_PTR)
9518 #define ENET1_RMON_T_P256TO511                   ENET_RMON_T_P256TO511_REG(ENET1_BASE_PTR)
9519 #define ENET1_RMON_T_P512TO1023                  ENET_RMON_T_P512TO1023_REG(ENET1_BASE_PTR)
9520 #define ENET1_RMON_T_P1024TO2047                 ENET_RMON_T_P1024TO2047_REG(ENET1_BASE_PTR)
9521 #define ENET1_RMON_T_P_GTE2048                   ENET_RMON_T_P_GTE2048_REG(ENET1_BASE_PTR)
9522 #define ENET1_RMON_T_OCTETS                      ENET_RMON_T_OCTETS_REG(ENET1_BASE_PTR)
9523 #define ENET1_IEEE_T_DROP                        ENET_IEEE_T_DROP_REG(ENET1_BASE_PTR)
9524 #define ENET1_IEEE_T_FRAME_OK                    ENET_IEEE_T_FRAME_OK_REG(ENET1_BASE_PTR)
9525 #define ENET1_IEEE_T_1COL                        ENET_IEEE_T_1COL_REG(ENET1_BASE_PTR)
9526 #define ENET1_IEEE_T_MCOL                        ENET_IEEE_T_MCOL_REG(ENET1_BASE_PTR)
9527 #define ENET1_IEEE_T_DEF                         ENET_IEEE_T_DEF_REG(ENET1_BASE_PTR)
9528 #define ENET1_IEEE_T_LCOL                        ENET_IEEE_T_LCOL_REG(ENET1_BASE_PTR)
9529 #define ENET1_IEEE_T_EXCOL                       ENET_IEEE_T_EXCOL_REG(ENET1_BASE_PTR)
9530 #define ENET1_IEEE_T_MACERR                      ENET_IEEE_T_MACERR_REG(ENET1_BASE_PTR)
9531 #define ENET1_IEEE_T_CSERR                       ENET_IEEE_T_CSERR_REG(ENET1_BASE_PTR)
9532 #define ENET1_IEEE_T_SQE                         ENET_IEEE_T_SQE_REG(ENET1_BASE_PTR)
9533 #define ENET1_IEEE_T_FDXFC                       ENET_IEEE_T_FDXFC_REG(ENET1_BASE_PTR)
9534 #define ENET1_IEEE_T_OCTETS_OK                   ENET_IEEE_T_OCTETS_OK_REG(ENET1_BASE_PTR)
9535 #define ENET1_RMON_R_PACKETS                     ENET_RMON_R_PACKETS_REG(ENET1_BASE_PTR)
9536 #define ENET1_RMON_R_BC_PKT                      ENET_RMON_R_BC_PKT_REG(ENET1_BASE_PTR)
9537 #define ENET1_RMON_R_MC_PKT                      ENET_RMON_R_MC_PKT_REG(ENET1_BASE_PTR)
9538 #define ENET1_RMON_R_CRC_ALIGN                   ENET_RMON_R_CRC_ALIGN_REG(ENET1_BASE_PTR)
9539 #define ENET1_RMON_R_UNDERSIZE                   ENET_RMON_R_UNDERSIZE_REG(ENET1_BASE_PTR)
9540 #define ENET1_RMON_R_OVERSIZE                    ENET_RMON_R_OVERSIZE_REG(ENET1_BASE_PTR)
9541 #define ENET1_RMON_R_FRAG                        ENET_RMON_R_FRAG_REG(ENET1_BASE_PTR)
9542 #define ENET1_RMON_R_JAB                         ENET_RMON_R_JAB_REG(ENET1_BASE_PTR)
9543 #define ENET1_RMON_R_RESVD_0                     ENET_RMON_R_RESVD_0_REG(ENET1_BASE_PTR)
9544 #define ENET1_RMON_R_P64                         ENET_RMON_R_P64_REG(ENET1_BASE_PTR)
9545 #define ENET1_RMON_R_P65TO127                    ENET_RMON_R_P65TO127_REG(ENET1_BASE_PTR)
9546 #define ENET1_RMON_R_P128TO255                   ENET_RMON_R_P128TO255_REG(ENET1_BASE_PTR)
9547 #define ENET1_RMON_R_P256TO511                   ENET_RMON_R_P256TO511_REG(ENET1_BASE_PTR)
9548 #define ENET1_RMON_R_P512TO1023                  ENET_RMON_R_P512TO1023_REG(ENET1_BASE_PTR)
9549 #define ENET1_RMON_R_P1024TO2047                 ENET_RMON_R_P1024TO2047_REG(ENET1_BASE_PTR)
9550 #define ENET1_RMON_R_P_GTE2048                   ENET_RMON_R_P_GTE2048_REG(ENET1_BASE_PTR)
9551 #define ENET1_RMON_R_OCTETS                      ENET_RMON_R_OCTETS_REG(ENET1_BASE_PTR)
9552 #define ENET1_IEEE_R_DROP                        ENET_IEEE_R_DROP_REG(ENET1_BASE_PTR)
9553 #define ENET1_IEEE_R_FRAME_OK                    ENET_IEEE_R_FRAME_OK_REG(ENET1_BASE_PTR)
9554 #define ENET1_IEEE_R_CRC                         ENET_IEEE_R_CRC_REG(ENET1_BASE_PTR)
9555 #define ENET1_IEEE_R_ALIGN                       ENET_IEEE_R_ALIGN_REG(ENET1_BASE_PTR)
9556 #define ENET1_IEEE_R_MACERR                      ENET_IEEE_R_MACERR_REG(ENET1_BASE_PTR)
9557 #define ENET1_IEEE_R_FDXFC                       ENET_IEEE_R_FDXFC_REG(ENET1_BASE_PTR)
9558 #define ENET1_IEEE_R_OCTETS_OK                   ENET_IEEE_R_OCTETS_OK_REG(ENET1_BASE_PTR)
9559 #define ENET1_ATCR                               ENET_ATCR_REG(ENET1_BASE_PTR)
9560 #define ENET1_ATVR                               ENET_ATVR_REG(ENET1_BASE_PTR)
9561 #define ENET1_ATOFF                              ENET_ATOFF_REG(ENET1_BASE_PTR)
9562 #define ENET1_ATPER                              ENET_ATPER_REG(ENET1_BASE_PTR)
9563 #define ENET1_ATCOR                              ENET_ATCOR_REG(ENET1_BASE_PTR)
9564 #define ENET1_ATINC                              ENET_ATINC_REG(ENET1_BASE_PTR)
9565 #define ENET1_ATSTMP                             ENET_ATSTMP_REG(ENET1_BASE_PTR)
9566 #define ENET1_TGSR                               ENET_TGSR_REG(ENET1_BASE_PTR)
9567 #define ENET1_TCSR0                              ENET_TCSR_REG(ENET1_BASE_PTR,0)
9568 #define ENET1_TCCR0                              ENET_TCCR_REG(ENET1_BASE_PTR,0)
9569 #define ENET1_TCSR1                              ENET_TCSR_REG(ENET1_BASE_PTR,1)
9570 #define ENET1_TCCR1                              ENET_TCCR_REG(ENET1_BASE_PTR,1)
9571 #define ENET1_TCSR2                              ENET_TCSR_REG(ENET1_BASE_PTR,2)
9572 #define ENET1_TCCR2                              ENET_TCCR_REG(ENET1_BASE_PTR,2)
9573 #define ENET1_TCSR3                              ENET_TCSR_REG(ENET1_BASE_PTR,3)
9574 #define ENET1_TCCR3                              ENET_TCCR_REG(ENET1_BASE_PTR,3)
9575 /* ENET2 */
9576 #define ENET2_EIR                                ENET_EIR_REG(ENET2_BASE_PTR)
9577 #define ENET2_EIMR                               ENET_EIMR_REG(ENET2_BASE_PTR)
9578 #define ENET2_RDAR                               ENET_RDAR_REG(ENET2_BASE_PTR)
9579 #define ENET2_TDAR                               ENET_TDAR_REG(ENET2_BASE_PTR)
9580 #define ENET2_ECR                                ENET_ECR_REG(ENET2_BASE_PTR)
9581 #define ENET2_MMFR                               ENET_MMFR_REG(ENET2_BASE_PTR)
9582 #define ENET2_MSCR                               ENET_MSCR_REG(ENET2_BASE_PTR)
9583 #define ENET2_MIBC                               ENET_MIBC_REG(ENET2_BASE_PTR)
9584 #define ENET2_RCR                                ENET_RCR_REG(ENET2_BASE_PTR)
9585 #define ENET2_TCR                                ENET_TCR_REG(ENET2_BASE_PTR)
9586 #define ENET2_PALR                               ENET_PALR_REG(ENET2_BASE_PTR)
9587 #define ENET2_PAUR                               ENET_PAUR_REG(ENET2_BASE_PTR)
9588 #define ENET2_OPD                                ENET_OPD_REG(ENET2_BASE_PTR)
9589 #define ENET2_TXIC0                              ENET_TXIC_REG(ENET2_BASE_PTR,0)
9590 #define ENET2_TXIC1                              ENET_TXIC_REG(ENET2_BASE_PTR,1)
9591 #define ENET2_TXIC2                              ENET_TXIC_REG(ENET2_BASE_PTR,2)
9592 #define ENET2_RXIC0                              ENET_RXIC_REG(ENET2_BASE_PTR,0)
9593 #define ENET2_RXIC1                              ENET_RXIC_REG(ENET2_BASE_PTR,1)
9594 #define ENET2_RXIC2                              ENET_RXIC_REG(ENET2_BASE_PTR,2)
9595 #define ENET2_IAUR                               ENET_IAUR_REG(ENET2_BASE_PTR)
9596 #define ENET2_IALR                               ENET_IALR_REG(ENET2_BASE_PTR)
9597 #define ENET2_GAUR                               ENET_GAUR_REG(ENET2_BASE_PTR)
9598 #define ENET2_GALR                               ENET_GALR_REG(ENET2_BASE_PTR)
9599 #define ENET2_TFWR                               ENET_TFWR_REG(ENET2_BASE_PTR)
9600 #define ENET2_RDSR1                              ENET_RDSR1_REG(ENET2_BASE_PTR)
9601 #define ENET2_TDSR1                              ENET_TDSR1_REG(ENET2_BASE_PTR)
9602 #define ENET2_MRBR1                              ENET_MRBR1_REG(ENET2_BASE_PTR)
9603 #define ENET2_RDSR2                              ENET_RDSR2_REG(ENET2_BASE_PTR)
9604 #define ENET2_TDSR2                              ENET_TDSR2_REG(ENET2_BASE_PTR)
9605 #define ENET2_MRBR2                              ENET_MRBR2_REG(ENET2_BASE_PTR)
9606 #define ENET2_RDSR                               ENET_RDSR_REG(ENET2_BASE_PTR)
9607 #define ENET2_TDSR                               ENET_TDSR_REG(ENET2_BASE_PTR)
9608 #define ENET2_MRBR                               ENET_MRBR_REG(ENET2_BASE_PTR)
9609 #define ENET2_RSFL                               ENET_RSFL_REG(ENET2_BASE_PTR)
9610 #define ENET2_RSEM                               ENET_RSEM_REG(ENET2_BASE_PTR)
9611 #define ENET2_RAEM                               ENET_RAEM_REG(ENET2_BASE_PTR)
9612 #define ENET2_RAFL                               ENET_RAFL_REG(ENET2_BASE_PTR)
9613 #define ENET2_TSEM                               ENET_TSEM_REG(ENET2_BASE_PTR)
9614 #define ENET2_TAEM                               ENET_TAEM_REG(ENET2_BASE_PTR)
9615 #define ENET2_TAFL                               ENET_TAFL_REG(ENET2_BASE_PTR)
9616 #define ENET2_TIPG                               ENET_TIPG_REG(ENET2_BASE_PTR)
9617 #define ENET2_FTRL                               ENET_FTRL_REG(ENET2_BASE_PTR)
9618 #define ENET2_TACC                               ENET_TACC_REG(ENET2_BASE_PTR)
9619 #define ENET2_RACC                               ENET_RACC_REG(ENET2_BASE_PTR)
9620 #define ENET2_RCMR1                              ENET_RCMR_REG(ENET2_BASE_PTR,0)
9621 #define ENET2_RCMR2                              ENET_RCMR_REG(ENET2_BASE_PTR,1)
9622 #define ENET2_DMA1CFG                            ENET_DMACFG_REG(ENET2_BASE_PTR,0)
9623 #define ENET2_DMA2CFG                            ENET_DMACFG_REG(ENET2_BASE_PTR,1)
9624 #define ENET2_RDAR1                              ENET_RDAR1_REG(ENET2_BASE_PTR)
9625 #define ENET2_TDAR1                              ENET_TDAR1_REG(ENET2_BASE_PTR)
9626 #define ENET2_RDAR2                              ENET_RDAR2_REG(ENET2_BASE_PTR)
9627 #define ENET2_TDAR2                              ENET_TDAR2_REG(ENET2_BASE_PTR)
9628 #define ENET2_QOS                                ENET_QOS_REG(ENET2_BASE_PTR)
9629 #define ENET2_RMON_T_DROP                        ENET_RMON_T_DROP_REG(ENET2_BASE_PTR)
9630 #define ENET2_RMON_T_PACKETS                     ENET_RMON_T_PACKETS_REG(ENET2_BASE_PTR)
9631 #define ENET2_RMON_T_BC_PKT                      ENET_RMON_T_BC_PKT_REG(ENET2_BASE_PTR)
9632 #define ENET2_RMON_T_MC_PKT                      ENET_RMON_T_MC_PKT_REG(ENET2_BASE_PTR)
9633 #define ENET2_RMON_T_CRC_ALIGN                   ENET_RMON_T_CRC_ALIGN_REG(ENET2_BASE_PTR)
9634 #define ENET2_RMON_T_UNDERSIZE                   ENET_RMON_T_UNDERSIZE_REG(ENET2_BASE_PTR)
9635 #define ENET2_RMON_T_OVERSIZE                    ENET_RMON_T_OVERSIZE_REG(ENET2_BASE_PTR)
9636 #define ENET2_RMON_T_FRAG                        ENET_RMON_T_FRAG_REG(ENET2_BASE_PTR)
9637 #define ENET2_RMON_T_JAB                         ENET_RMON_T_JAB_REG(ENET2_BASE_PTR)
9638 #define ENET2_RMON_T_COL                         ENET_RMON_T_COL_REG(ENET2_BASE_PTR)
9639 #define ENET2_RMON_T_P64                         ENET_RMON_T_P64_REG(ENET2_BASE_PTR)
9640 #define ENET2_RMON_T_P65TO127                    ENET_RMON_T_P65TO127_REG(ENET2_BASE_PTR)
9641 #define ENET2_RMON_T_P128TO255                   ENET_RMON_T_P128TO255_REG(ENET2_BASE_PTR)
9642 #define ENET2_RMON_T_P256TO511                   ENET_RMON_T_P256TO511_REG(ENET2_BASE_PTR)
9643 #define ENET2_RMON_T_P512TO1023                  ENET_RMON_T_P512TO1023_REG(ENET2_BASE_PTR)
9644 #define ENET2_RMON_T_P1024TO2047                 ENET_RMON_T_P1024TO2047_REG(ENET2_BASE_PTR)
9645 #define ENET2_RMON_T_P_GTE2048                   ENET_RMON_T_P_GTE2048_REG(ENET2_BASE_PTR)
9646 #define ENET2_RMON_T_OCTETS                      ENET_RMON_T_OCTETS_REG(ENET2_BASE_PTR)
9647 #define ENET2_IEEE_T_DROP                        ENET_IEEE_T_DROP_REG(ENET2_BASE_PTR)
9648 #define ENET2_IEEE_T_FRAME_OK                    ENET_IEEE_T_FRAME_OK_REG(ENET2_BASE_PTR)
9649 #define ENET2_IEEE_T_1COL                        ENET_IEEE_T_1COL_REG(ENET2_BASE_PTR)
9650 #define ENET2_IEEE_T_MCOL                        ENET_IEEE_T_MCOL_REG(ENET2_BASE_PTR)
9651 #define ENET2_IEEE_T_DEF                         ENET_IEEE_T_DEF_REG(ENET2_BASE_PTR)
9652 #define ENET2_IEEE_T_LCOL                        ENET_IEEE_T_LCOL_REG(ENET2_BASE_PTR)
9653 #define ENET2_IEEE_T_EXCOL                       ENET_IEEE_T_EXCOL_REG(ENET2_BASE_PTR)
9654 #define ENET2_IEEE_T_MACERR                      ENET_IEEE_T_MACERR_REG(ENET2_BASE_PTR)
9655 #define ENET2_IEEE_T_CSERR                       ENET_IEEE_T_CSERR_REG(ENET2_BASE_PTR)
9656 #define ENET2_IEEE_T_SQE                         ENET_IEEE_T_SQE_REG(ENET2_BASE_PTR)
9657 #define ENET2_IEEE_T_FDXFC                       ENET_IEEE_T_FDXFC_REG(ENET2_BASE_PTR)
9658 #define ENET2_IEEE_T_OCTETS_OK                   ENET_IEEE_T_OCTETS_OK_REG(ENET2_BASE_PTR)
9659 #define ENET2_RMON_R_PACKETS                     ENET_RMON_R_PACKETS_REG(ENET2_BASE_PTR)
9660 #define ENET2_RMON_R_BC_PKT                      ENET_RMON_R_BC_PKT_REG(ENET2_BASE_PTR)
9661 #define ENET2_RMON_R_MC_PKT                      ENET_RMON_R_MC_PKT_REG(ENET2_BASE_PTR)
9662 #define ENET2_RMON_R_CRC_ALIGN                   ENET_RMON_R_CRC_ALIGN_REG(ENET2_BASE_PTR)
9663 #define ENET2_RMON_R_UNDERSIZE                   ENET_RMON_R_UNDERSIZE_REG(ENET2_BASE_PTR)
9664 #define ENET2_RMON_R_OVERSIZE                    ENET_RMON_R_OVERSIZE_REG(ENET2_BASE_PTR)
9665 #define ENET2_RMON_R_FRAG                        ENET_RMON_R_FRAG_REG(ENET2_BASE_PTR)
9666 #define ENET2_RMON_R_JAB                         ENET_RMON_R_JAB_REG(ENET2_BASE_PTR)
9667 #define ENET2_RMON_R_RESVD_0                     ENET_RMON_R_RESVD_0_REG(ENET2_BASE_PTR)
9668 #define ENET2_RMON_R_P64                         ENET_RMON_R_P64_REG(ENET2_BASE_PTR)
9669 #define ENET2_RMON_R_P65TO127                    ENET_RMON_R_P65TO127_REG(ENET2_BASE_PTR)
9670 #define ENET2_RMON_R_P128TO255                   ENET_RMON_R_P128TO255_REG(ENET2_BASE_PTR)
9671 #define ENET2_RMON_R_P256TO511                   ENET_RMON_R_P256TO511_REG(ENET2_BASE_PTR)
9672 #define ENET2_RMON_R_P512TO1023                  ENET_RMON_R_P512TO1023_REG(ENET2_BASE_PTR)
9673 #define ENET2_RMON_R_P1024TO2047                 ENET_RMON_R_P1024TO2047_REG(ENET2_BASE_PTR)
9674 #define ENET2_RMON_R_P_GTE2048                   ENET_RMON_R_P_GTE2048_REG(ENET2_BASE_PTR)
9675 #define ENET2_RMON_R_OCTETS                      ENET_RMON_R_OCTETS_REG(ENET2_BASE_PTR)
9676 #define ENET2_IEEE_R_DROP                        ENET_IEEE_R_DROP_REG(ENET2_BASE_PTR)
9677 #define ENET2_IEEE_R_FRAME_OK                    ENET_IEEE_R_FRAME_OK_REG(ENET2_BASE_PTR)
9678 #define ENET2_IEEE_R_CRC                         ENET_IEEE_R_CRC_REG(ENET2_BASE_PTR)
9679 #define ENET2_IEEE_R_ALIGN                       ENET_IEEE_R_ALIGN_REG(ENET2_BASE_PTR)
9680 #define ENET2_IEEE_R_MACERR                      ENET_IEEE_R_MACERR_REG(ENET2_BASE_PTR)
9681 #define ENET2_IEEE_R_FDXFC                       ENET_IEEE_R_FDXFC_REG(ENET2_BASE_PTR)
9682 #define ENET2_IEEE_R_OCTETS_OK                   ENET_IEEE_R_OCTETS_OK_REG(ENET2_BASE_PTR)
9683 #define ENET2_ATCR                               ENET_ATCR_REG(ENET2_BASE_PTR)
9684 #define ENET2_ATVR                               ENET_ATVR_REG(ENET2_BASE_PTR)
9685 #define ENET2_ATOFF                              ENET_ATOFF_REG(ENET2_BASE_PTR)
9686 #define ENET2_ATPER                              ENET_ATPER_REG(ENET2_BASE_PTR)
9687 #define ENET2_ATCOR                              ENET_ATCOR_REG(ENET2_BASE_PTR)
9688 #define ENET2_ATINC                              ENET_ATINC_REG(ENET2_BASE_PTR)
9689 #define ENET2_ATSTMP                             ENET_ATSTMP_REG(ENET2_BASE_PTR)
9690 #define ENET2_TGSR                               ENET_TGSR_REG(ENET2_BASE_PTR)
9691 #define ENET2_TCSR0                              ENET_TCSR_REG(ENET2_BASE_PTR,0)
9692 #define ENET2_TCCR0                              ENET_TCCR_REG(ENET2_BASE_PTR,0)
9693 #define ENET2_TCSR1                              ENET_TCSR_REG(ENET2_BASE_PTR,1)
9694 #define ENET2_TCCR1                              ENET_TCCR_REG(ENET2_BASE_PTR,1)
9695 #define ENET2_TCSR2                              ENET_TCSR_REG(ENET2_BASE_PTR,2)
9696 #define ENET2_TCCR2                              ENET_TCCR_REG(ENET2_BASE_PTR,2)
9697 #define ENET2_TCSR3                              ENET_TCSR_REG(ENET2_BASE_PTR,3)
9698 #define ENET2_TCCR3                              ENET_TCCR_REG(ENET2_BASE_PTR,3)
9699 /* ENET - Register array accessors */
9700 #define ENET1_TXIC(index)                        ENET_TXIC_REG(ENET1_BASE_PTR,index)
9701 #define ENET2_TXIC(index)                        ENET_TXIC_REG(ENET2_BASE_PTR,index)
9702 #define ENET1_RXIC(index)                        ENET_RXIC_REG(ENET1_BASE_PTR,index)
9703 #define ENET2_RXIC(index)                        ENET_RXIC_REG(ENET2_BASE_PTR,index)
9704 #define ENET1_RCMR(index)                        ENET_RCMR_REG(ENET1_BASE_PTR,index)
9705 #define ENET2_RCMR(index)                        ENET_RCMR_REG(ENET2_BASE_PTR,index)
9706 #define ENET1_DMACFG(index)                      ENET_DMACFG_REG(ENET1_BASE_PTR,index)
9707 #define ENET2_DMACFG(index)                      ENET_DMACFG_REG(ENET2_BASE_PTR,index)
9708 #define ENET1_TCSR(index)                        ENET_TCSR_REG(ENET1_BASE_PTR,index)
9709 #define ENET2_TCSR(index)                        ENET_TCSR_REG(ENET2_BASE_PTR,index)
9710 #define ENET1_TCCR(index)                        ENET_TCCR_REG(ENET1_BASE_PTR,index)
9711 #define ENET2_TCCR(index)                        ENET_TCCR_REG(ENET2_BASE_PTR,index)
9712 
9713 /*!
9714  * @}
9715  */ /* end of group ENET_Register_Accessor_Macros */
9716 
9717 /*!
9718  * @}
9719  */ /* end of group ENET_Peripheral */
9720 
9721 /* ----------------------------------------------------------------------------
9722    -- EPIT Peripheral Access Layer
9723    ---------------------------------------------------------------------------- */
9724 
9725 /*!
9726  * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer
9727  * @{
9728  */
9729 
9730 /** EPIT - Register Layout Typedef */
9731 typedef struct {
9732   __IO  uint32_t CR;                                     /**< Control register, offset: 0x0 */
9733   __IO  uint32_t SR;                                     /**< Status register, offset: 0x4 */
9734   __IO  uint32_t LR;                                     /**< Load register, offset: 0x8 */
9735   __IO  uint32_t CMPR;                                   /**< Compare register, offset: 0xC */
9736   __I   uint32_t CNR;                                    /**< Counter register, offset: 0x10 */
9737 } EPIT_Type, *EPIT_MemMapPtr;
9738 
9739 /* ----------------------------------------------------------------------------
9740    -- EPIT - Register accessor macros
9741    ---------------------------------------------------------------------------- */
9742 
9743 /*!
9744  * @addtogroup EPIT_Register_Accessor_Macros EPIT - Register accessor macros
9745  * @{
9746  */
9747 
9748 /* EPIT - Register accessors */
9749 #define EPIT_CR_REG(base)                        ((base)->CR)
9750 #define EPIT_SR_REG(base)                        ((base)->SR)
9751 #define EPIT_LR_REG(base)                        ((base)->LR)
9752 #define EPIT_CMPR_REG(base)                      ((base)->CMPR)
9753 #define EPIT_CNR_REG(base)                       ((base)->CNR)
9754 
9755 /*!
9756  * @}
9757  */ /* end of group EPIT_Register_Accessor_Macros */
9758 /* ----------------------------------------------------------------------------
9759    -- EPIT Register Masks
9760    ---------------------------------------------------------------------------- */
9761 
9762 /*!
9763  * @addtogroup EPIT_Register_Masks EPIT Register Masks
9764  * @{
9765  */
9766 
9767 /* CR Bit Fields */
9768 #define EPIT_CR_EN_MASK                          0x1u
9769 #define EPIT_CR_EN_SHIFT                         0
9770 #define EPIT_CR_ENMOD_MASK                       0x2u
9771 #define EPIT_CR_ENMOD_SHIFT                      1
9772 #define EPIT_CR_OCIEN_MASK                       0x4u
9773 #define EPIT_CR_OCIEN_SHIFT                      2
9774 #define EPIT_CR_RLD_MASK                         0x8u
9775 #define EPIT_CR_RLD_SHIFT                        3
9776 #define EPIT_CR_PRESCALAR_MASK                   0xFFF0u
9777 #define EPIT_CR_PRESCALAR_SHIFT                  4
9778 #define EPIT_CR_PRESCALAR(x)                     (((uint32_t)(((uint32_t)(x))<<EPIT_CR_PRESCALAR_SHIFT))&EPIT_CR_PRESCALAR_MASK)
9779 #define EPIT_CR_SWR_MASK                         0x10000u
9780 #define EPIT_CR_SWR_SHIFT                        16
9781 #define EPIT_CR_IOVW_MASK                        0x20000u
9782 #define EPIT_CR_IOVW_SHIFT                       17
9783 #define EPIT_CR_DBGEN_MASK                       0x40000u
9784 #define EPIT_CR_DBGEN_SHIFT                      18
9785 #define EPIT_CR_WAITEN_MASK                      0x80000u
9786 #define EPIT_CR_WAITEN_SHIFT                     19
9787 #define EPIT_CR_STOPEN_MASK                      0x200000u
9788 #define EPIT_CR_STOPEN_SHIFT                     21
9789 #define EPIT_CR_OM_MASK                          0xC00000u
9790 #define EPIT_CR_OM_SHIFT                         22
9791 #define EPIT_CR_OM(x)                            (((uint32_t)(((uint32_t)(x))<<EPIT_CR_OM_SHIFT))&EPIT_CR_OM_MASK)
9792 #define EPIT_CR_CLKSRC_MASK                      0x3000000u
9793 #define EPIT_CR_CLKSRC_SHIFT                     24
9794 #define EPIT_CR_CLKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<EPIT_CR_CLKSRC_SHIFT))&EPIT_CR_CLKSRC_MASK)
9795 /* SR Bit Fields */
9796 #define EPIT_SR_OCIF_MASK                        0x1u
9797 #define EPIT_SR_OCIF_SHIFT                       0
9798 /* LR Bit Fields */
9799 #define EPIT_LR_LOAD_MASK                        0xFFFFFFFFu
9800 #define EPIT_LR_LOAD_SHIFT                       0
9801 #define EPIT_LR_LOAD(x)                          (((uint32_t)(((uint32_t)(x))<<EPIT_LR_LOAD_SHIFT))&EPIT_LR_LOAD_MASK)
9802 /* CMPR Bit Fields */
9803 #define EPIT_CMPR_COMPARE_MASK                   0xFFFFFFFFu
9804 #define EPIT_CMPR_COMPARE_SHIFT                  0
9805 #define EPIT_CMPR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<EPIT_CMPR_COMPARE_SHIFT))&EPIT_CMPR_COMPARE_MASK)
9806 /* CNR Bit Fields */
9807 #define EPIT_CNR_COUNT_MASK                      0xFFFFFFFFu
9808 #define EPIT_CNR_COUNT_SHIFT                     0
9809 #define EPIT_CNR_COUNT(x)                        (((uint32_t)(((uint32_t)(x))<<EPIT_CNR_COUNT_SHIFT))&EPIT_CNR_COUNT_MASK)
9810 
9811 /*!
9812  * @}
9813  */ /* end of group EPIT_Register_Masks */
9814 
9815 /* EPIT - Peripheral instance base addresses */
9816 /** Peripheral EPIT1 base address */
9817 #define EPIT1_BASE                               (0x420D0000u)
9818 /** Peripheral EPIT1 base pointer */
9819 #define EPIT1                                    ((EPIT_Type *)EPIT1_BASE)
9820 #define EPIT1_BASE_PTR                           (EPIT1)
9821 /** Peripheral EPIT2 base address */
9822 #define EPIT2_BASE                               (0x420D4000u)
9823 /** Peripheral EPIT2 base pointer */
9824 #define EPIT2                                    ((EPIT_Type *)EPIT2_BASE)
9825 #define EPIT2_BASE_PTR                           (EPIT2)
9826 /** Array initializer of EPIT peripheral base addresses */
9827 #define EPIT_BASE_ADDRS                          { EPIT1_BASE, EPIT2_BASE }
9828 /** Array initializer of EPIT peripheral base pointers */
9829 #define EPIT_BASE_PTRS                           { EPIT1, EPIT2 }
9830 /** Interrupt vectors for the EPIT peripheral type */
9831 #define EPIT_IRQS                                { EPIT1_IRQn, EPIT2_IRQn }
9832 
9833 /* ----------------------------------------------------------------------------
9834    -- EPIT - Register accessor macros
9835    ---------------------------------------------------------------------------- */
9836 
9837 /*!
9838  * @addtogroup EPIT_Register_Accessor_Macros EPIT - Register accessor macros
9839  * @{
9840  */
9841 
9842 /* EPIT - Register instance definitions */
9843 /* EPIT1 */
9844 #define EPIT1_CR                                 EPIT_CR_REG(EPIT1_BASE_PTR)
9845 #define EPIT1_SR                                 EPIT_SR_REG(EPIT1_BASE_PTR)
9846 #define EPIT1_LR                                 EPIT_LR_REG(EPIT1_BASE_PTR)
9847 #define EPIT1_CMPR                               EPIT_CMPR_REG(EPIT1_BASE_PTR)
9848 #define EPIT1_CNR                                EPIT_CNR_REG(EPIT1_BASE_PTR)
9849 /* EPIT2 */
9850 #define EPIT2_CR                                 EPIT_CR_REG(EPIT2_BASE_PTR)
9851 #define EPIT2_SR                                 EPIT_SR_REG(EPIT2_BASE_PTR)
9852 #define EPIT2_LR                                 EPIT_LR_REG(EPIT2_BASE_PTR)
9853 #define EPIT2_CMPR                               EPIT_CMPR_REG(EPIT2_BASE_PTR)
9854 #define EPIT2_CNR                                EPIT_CNR_REG(EPIT2_BASE_PTR)
9855 
9856 /*!
9857  * @}
9858  */ /* end of group EPIT_Register_Accessor_Macros */
9859 
9860 /*!
9861  * @}
9862  */ /* end of group EPIT_Peripheral */
9863 
9864 /* ----------------------------------------------------------------------------
9865    -- ESAI Peripheral Access Layer
9866    ---------------------------------------------------------------------------- */
9867 
9868 /*!
9869  * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer
9870  * @{
9871  */
9872 
9873 /** ESAI - Register Layout Typedef */
9874 typedef struct {
9875   __O   uint32_t ETDR;                                   /**< ESAI Transmit Data Register, offset: 0x0 */
9876   __I   uint32_t ERDR;                                   /**< ESAI Receive Data Register, offset: 0x4 */
9877   __IO  uint32_t ECR;                                    /**< ESAI Control Register, offset: 0x8 */
9878   __I   uint32_t ESR;                                    /**< ESAI Status Register, offset: 0xC */
9879   __IO  uint32_t TFCR;                                   /**< Transmit FIFO Configuration Register, offset: 0x10 */
9880   __I   uint32_t TFSR;                                   /**< Transmit FIFO Status Register, offset: 0x14 */
9881   __IO  uint32_t RFCR;                                   /**< Receive FIFO Configuration Register, offset: 0x18 */
9882   __I   uint32_t RFSR;                                   /**< Receive FIFO Status Register, offset: 0x1C */
9883   uint8_t RESERVED_0[96];
9884   __O   uint32_t TX[6];                                  /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */
9885   __O   uint32_t TSR;                                    /**< ESAI Transmit Slot Register, offset: 0x98 */
9886   uint8_t RESERVED_1[4];
9887   __I   uint32_t RX[4];                                  /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */
9888   uint8_t RESERVED_2[28];
9889   __I   uint32_t SAISR;                                  /**< Serial Audio Interface Status Register, offset: 0xCC */
9890   __IO  uint32_t SAICR;                                  /**< Serial Audio Interface Control Register, offset: 0xD0 */
9891   __IO  uint32_t TCR;                                    /**< Transmit Control Register, offset: 0xD4 */
9892   __IO  uint32_t TCCR;                                   /**< Transmit Clock Control Register, offset: 0xD8 */
9893   __IO  uint32_t RCR;                                    /**< Receive Control Register, offset: 0xDC */
9894   __IO  uint32_t RCCR;                                   /**< Receive Clock Control Register, offset: 0xE0 */
9895   __IO  uint32_t TSMA;                                   /**< Transmit Slot Mask Register A, offset: 0xE4 */
9896   __IO  uint32_t TSMB;                                   /**< Transmit Slot Mask Register B, offset: 0xE8 */
9897   __IO  uint32_t RSMA;                                   /**< Receive Slot Mask Register A, offset: 0xEC */
9898   __IO  uint32_t RSMB;                                   /**< Receive Slot Mask Register B, offset: 0xF0 */
9899   uint8_t RESERVED_3[4];
9900   __IO  uint32_t PRRC;                                   /**< Port C Direction Register, offset: 0xF8 */
9901   __IO  uint32_t PCRC;                                   /**< Port C Control Register, offset: 0xFC */
9902 } ESAI_Type, *ESAI_MemMapPtr;
9903 
9904 /* ----------------------------------------------------------------------------
9905    -- ESAI - Register accessor macros
9906    ---------------------------------------------------------------------------- */
9907 
9908 /*!
9909  * @addtogroup ESAI_Register_Accessor_Macros ESAI - Register accessor macros
9910  * @{
9911  */
9912 
9913 /* ESAI - Register accessors */
9914 #define ESAI_ETDR_REG(base)                      ((base)->ETDR)
9915 #define ESAI_ERDR_REG(base)                      ((base)->ERDR)
9916 #define ESAI_ECR_REG(base)                       ((base)->ECR)
9917 #define ESAI_ESR_REG(base)                       ((base)->ESR)
9918 #define ESAI_TFCR_REG(base)                      ((base)->TFCR)
9919 #define ESAI_TFSR_REG(base)                      ((base)->TFSR)
9920 #define ESAI_RFCR_REG(base)                      ((base)->RFCR)
9921 #define ESAI_RFSR_REG(base)                      ((base)->RFSR)
9922 #define ESAI_TX_REG(base,index)                  ((base)->TX[index])
9923 #define ESAI_TSR_REG(base)                       ((base)->TSR)
9924 #define ESAI_RX_REG(base,index)                  ((base)->RX[index])
9925 #define ESAI_SAISR_REG(base)                     ((base)->SAISR)
9926 #define ESAI_SAICR_REG(base)                     ((base)->SAICR)
9927 #define ESAI_TCR_REG(base)                       ((base)->TCR)
9928 #define ESAI_TCCR_REG(base)                      ((base)->TCCR)
9929 #define ESAI_RCR_REG(base)                       ((base)->RCR)
9930 #define ESAI_RCCR_REG(base)                      ((base)->RCCR)
9931 #define ESAI_TSMA_REG(base)                      ((base)->TSMA)
9932 #define ESAI_TSMB_REG(base)                      ((base)->TSMB)
9933 #define ESAI_RSMA_REG(base)                      ((base)->RSMA)
9934 #define ESAI_RSMB_REG(base)                      ((base)->RSMB)
9935 #define ESAI_PRRC_REG(base)                      ((base)->PRRC)
9936 #define ESAI_PCRC_REG(base)                      ((base)->PCRC)
9937 
9938 /*!
9939  * @}
9940  */ /* end of group ESAI_Register_Accessor_Macros */
9941 
9942 /* ----------------------------------------------------------------------------
9943    -- ESAI Register Masks
9944    ---------------------------------------------------------------------------- */
9945 
9946 /*!
9947  * @addtogroup ESAI_Register_Masks ESAI Register Masks
9948  * @{
9949  */
9950 
9951 /* ETDR Bit Fields */
9952 #define ESAI_ETDR_ETDR_MASK                      0xFFFFFFFFu
9953 #define ESAI_ETDR_ETDR_SHIFT                     0
9954 #define ESAI_ETDR_ETDR(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_ETDR_ETDR_SHIFT))&ESAI_ETDR_ETDR_MASK)
9955 /* ERDR Bit Fields */
9956 #define ESAI_ERDR_ERDR_MASK                      0xFFFFFFFFu
9957 #define ESAI_ERDR_ERDR_SHIFT                     0
9958 #define ESAI_ERDR_ERDR(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_ERDR_ERDR_SHIFT))&ESAI_ERDR_ERDR_MASK)
9959 /* ECR Bit Fields */
9960 #define ESAI_ECR_ESAIEN_MASK                     0x1u
9961 #define ESAI_ECR_ESAIEN_SHIFT                    0
9962 #define ESAI_ECR_ERST_MASK                       0x2u
9963 #define ESAI_ECR_ERST_SHIFT                      1
9964 #define ESAI_ECR_ERO_MASK                        0x10000u
9965 #define ESAI_ECR_ERO_SHIFT                       16
9966 #define ESAI_ECR_ERI_MASK                        0x20000u
9967 #define ESAI_ECR_ERI_SHIFT                       17
9968 #define ESAI_ECR_ETO_MASK                        0x40000u
9969 #define ESAI_ECR_ETO_SHIFT                       18
9970 #define ESAI_ECR_ETI_MASK                        0x80000u
9971 #define ESAI_ECR_ETI_SHIFT                       19
9972 /* ESR Bit Fields */
9973 #define ESAI_ESR_RD_MASK                         0x1u
9974 #define ESAI_ESR_RD_SHIFT                        0
9975 #define ESAI_ESR_RED_MASK                        0x2u
9976 #define ESAI_ESR_RED_SHIFT                       1
9977 #define ESAI_ESR_RDE_MASK                        0x4u
9978 #define ESAI_ESR_RDE_SHIFT                       2
9979 #define ESAI_ESR_RLS_MASK                        0x8u
9980 #define ESAI_ESR_RLS_SHIFT                       3
9981 #define ESAI_ESR_TD_MASK                         0x10u
9982 #define ESAI_ESR_TD_SHIFT                        4
9983 #define ESAI_ESR_TED_MASK                        0x20u
9984 #define ESAI_ESR_TED_SHIFT                       5
9985 #define ESAI_ESR_TDE_MASK                        0x40u
9986 #define ESAI_ESR_TDE_SHIFT                       6
9987 #define ESAI_ESR_TLS_MASK                        0x80u
9988 #define ESAI_ESR_TLS_SHIFT                       7
9989 #define ESAI_ESR_TFE_MASK                        0x100u
9990 #define ESAI_ESR_TFE_SHIFT                       8
9991 #define ESAI_ESR_RFF_MASK                        0x200u
9992 #define ESAI_ESR_RFF_SHIFT                       9
9993 #define ESAI_ESR_TINIT_MASK                      0x400u
9994 #define ESAI_ESR_TINIT_SHIFT                     10
9995 /* TFCR Bit Fields */
9996 #define ESAI_TFCR_TFE_MASK                       0x1u
9997 #define ESAI_TFCR_TFE_SHIFT                      0
9998 #define ESAI_TFCR_TFR_MASK                       0x2u
9999 #define ESAI_TFCR_TFR_SHIFT                      1
10000 #define ESAI_TFCR_TE0_MASK                       0x4u
10001 #define ESAI_TFCR_TE0_SHIFT                      2
10002 #define ESAI_TFCR_TE1_MASK                       0x8u
10003 #define ESAI_TFCR_TE1_SHIFT                      3
10004 #define ESAI_TFCR_TE2_MASK                       0x10u
10005 #define ESAI_TFCR_TE2_SHIFT                      4
10006 #define ESAI_TFCR_TE3_MASK                       0x20u
10007 #define ESAI_TFCR_TE3_SHIFT                      5
10008 #define ESAI_TFCR_TE4_MASK                       0x40u
10009 #define ESAI_TFCR_TE4_SHIFT                      6
10010 #define ESAI_TFCR_TE5_MASK                       0x80u
10011 #define ESAI_TFCR_TE5_SHIFT                      7
10012 #define ESAI_TFCR_TFWM_MASK                      0xFF00u
10013 #define ESAI_TFCR_TFWM_SHIFT                     8
10014 #define ESAI_TFCR_TFWM(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TFWM_SHIFT))&ESAI_TFCR_TFWM_MASK)
10015 #define ESAI_TFCR_TWA_MASK                       0x70000u
10016 #define ESAI_TFCR_TWA_SHIFT                      16
10017 #define ESAI_TFCR_TWA(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TWA_SHIFT))&ESAI_TFCR_TWA_MASK)
10018 #define ESAI_TFCR_TIEN_MASK                      0x80000u
10019 #define ESAI_TFCR_TIEN_SHIFT                     19
10020 /* TFSR Bit Fields */
10021 #define ESAI_TFSR_TFCNT_MASK                     0xFFu
10022 #define ESAI_TFSR_TFCNT_SHIFT                    0
10023 #define ESAI_TFSR_TFCNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_TFCNT_SHIFT))&ESAI_TFSR_TFCNT_MASK)
10024 #define ESAI_TFSR_NTFI_MASK                      0x700u
10025 #define ESAI_TFSR_NTFI_SHIFT                     8
10026 #define ESAI_TFSR_NTFI(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFI_SHIFT))&ESAI_TFSR_NTFI_MASK)
10027 #define ESAI_TFSR_NTFO_MASK                      0x7000u
10028 #define ESAI_TFSR_NTFO_SHIFT                     12
10029 #define ESAI_TFSR_NTFO(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFO_SHIFT))&ESAI_TFSR_NTFO_MASK)
10030 /* RFCR Bit Fields */
10031 #define ESAI_RFCR_RFE_MASK                       0x1u
10032 #define ESAI_RFCR_RFE_SHIFT                      0
10033 #define ESAI_RFCR_RFR_MASK                       0x2u
10034 #define ESAI_RFCR_RFR_SHIFT                      1
10035 #define ESAI_RFCR_RE0_MASK                       0x4u
10036 #define ESAI_RFCR_RE0_SHIFT                      2
10037 #define ESAI_RFCR_RE1_MASK                       0x8u
10038 #define ESAI_RFCR_RE1_SHIFT                      3
10039 #define ESAI_RFCR_RE2_MASK                       0x10u
10040 #define ESAI_RFCR_RE2_SHIFT                      4
10041 #define ESAI_RFCR_RE3_MASK                       0x20u
10042 #define ESAI_RFCR_RE3_SHIFT                      5
10043 #define ESAI_RFCR_RFWM_MASK                      0xFF00u
10044 #define ESAI_RFCR_RFWM_SHIFT                     8
10045 #define ESAI_RFCR_RFWM(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RFWM_SHIFT))&ESAI_RFCR_RFWM_MASK)
10046 #define ESAI_RFCR_RWA_MASK                       0x70000u
10047 #define ESAI_RFCR_RWA_SHIFT                      16
10048 #define ESAI_RFCR_RWA(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RWA_SHIFT))&ESAI_RFCR_RWA_MASK)
10049 #define ESAI_RFCR_REXT_MASK                      0x80000u
10050 #define ESAI_RFCR_REXT_SHIFT                     19
10051 /* RFSR Bit Fields */
10052 #define ESAI_RFSR_RFCNT_MASK                     0xFFu
10053 #define ESAI_RFSR_RFCNT_SHIFT                    0
10054 #define ESAI_RFSR_RFCNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_RFCNT_SHIFT))&ESAI_RFSR_RFCNT_MASK)
10055 #define ESAI_RFSR_NRFO_MASK                      0x300u
10056 #define ESAI_RFSR_NRFO_SHIFT                     8
10057 #define ESAI_RFSR_NRFO(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFO_SHIFT))&ESAI_RFSR_NRFO_MASK)
10058 #define ESAI_RFSR_NRFI_MASK                      0x3000u
10059 #define ESAI_RFSR_NRFI_SHIFT                     12
10060 #define ESAI_RFSR_NRFI(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFI_SHIFT))&ESAI_RFSR_NRFI_MASK)
10061 /* TX Bit Fields */
10062 #define ESAI_TX_TXn_MASK                         0xFFFFFFu
10063 #define ESAI_TX_TXn_SHIFT                        0
10064 #define ESAI_TX_TXn(x)                           (((uint32_t)(((uint32_t)(x))<<ESAI_TX_TXn_SHIFT))&ESAI_TX_TXn_MASK)
10065 /* TSR Bit Fields */
10066 #define ESAI_TSR_TSR_MASK                        0xFFFFFFu
10067 #define ESAI_TSR_TSR_SHIFT                       0
10068 #define ESAI_TSR_TSR(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSR_TSR_SHIFT))&ESAI_TSR_TSR_MASK)
10069 /* RX Bit Fields */
10070 #define ESAI_RX_RXn_MASK                         0xFFFFFFu
10071 #define ESAI_RX_RXn_SHIFT                        0
10072 #define ESAI_RX_RXn(x)                           (((uint32_t)(((uint32_t)(x))<<ESAI_RX_RXn_SHIFT))&ESAI_RX_RXn_MASK)
10073 /* SAISR Bit Fields */
10074 #define ESAI_SAISR_IF0_MASK                      0x1u
10075 #define ESAI_SAISR_IF0_SHIFT                     0
10076 #define ESAI_SAISR_IF1_MASK                      0x2u
10077 #define ESAI_SAISR_IF1_SHIFT                     1
10078 #define ESAI_SAISR_IF2_MASK                      0x4u
10079 #define ESAI_SAISR_IF2_SHIFT                     2
10080 #define ESAI_SAISR_RFS_MASK                      0x40u
10081 #define ESAI_SAISR_RFS_SHIFT                     6
10082 #define ESAI_SAISR_ROE_MASK                      0x80u
10083 #define ESAI_SAISR_ROE_SHIFT                     7
10084 #define ESAI_SAISR_RDF_MASK                      0x100u
10085 #define ESAI_SAISR_RDF_SHIFT                     8
10086 #define ESAI_SAISR_REDF_MASK                     0x200u
10087 #define ESAI_SAISR_REDF_SHIFT                    9
10088 #define ESAI_SAISR_RODF_MASK                     0x400u
10089 #define ESAI_SAISR_RODF_SHIFT                    10
10090 #define ESAI_SAISR_TFS_MASK                      0x2000u
10091 #define ESAI_SAISR_TFS_SHIFT                     13
10092 #define ESAI_SAISR_TUE_MASK                      0x4000u
10093 #define ESAI_SAISR_TUE_SHIFT                     14
10094 #define ESAI_SAISR_TDE_MASK                      0x8000u
10095 #define ESAI_SAISR_TDE_SHIFT                     15
10096 #define ESAI_SAISR_TEDE_MASK                     0x10000u
10097 #define ESAI_SAISR_TEDE_SHIFT                    16
10098 #define ESAI_SAISR_TODFE_MASK                    0x20000u
10099 #define ESAI_SAISR_TODFE_SHIFT                   17
10100 /* SAICR Bit Fields */
10101 #define ESAI_SAICR_OF0_MASK                      0x1u
10102 #define ESAI_SAICR_OF0_SHIFT                     0
10103 #define ESAI_SAICR_OF1_MASK                      0x2u
10104 #define ESAI_SAICR_OF1_SHIFT                     1
10105 #define ESAI_SAICR_OF2_MASK                      0x4u
10106 #define ESAI_SAICR_OF2_SHIFT                     2
10107 #define ESAI_SAICR_SYN_MASK                      0x40u
10108 #define ESAI_SAICR_SYN_SHIFT                     6
10109 #define ESAI_SAICR_TEBE_MASK                     0x80u
10110 #define ESAI_SAICR_TEBE_SHIFT                    7
10111 #define ESAI_SAICR_ALC_MASK                      0x100u
10112 #define ESAI_SAICR_ALC_SHIFT                     8
10113 /* TCR Bit Fields */
10114 #define ESAI_TCR_TE0_MASK                        0x1u
10115 #define ESAI_TCR_TE0_SHIFT                       0
10116 #define ESAI_TCR_TE1_MASK                        0x2u
10117 #define ESAI_TCR_TE1_SHIFT                       1
10118 #define ESAI_TCR_TE2_MASK                        0x4u
10119 #define ESAI_TCR_TE2_SHIFT                       2
10120 #define ESAI_TCR_TE3_MASK                        0x8u
10121 #define ESAI_TCR_TE3_SHIFT                       3
10122 #define ESAI_TCR_TE4_MASK                        0x10u
10123 #define ESAI_TCR_TE4_SHIFT                       4
10124 #define ESAI_TCR_TE5_MASK                        0x20u
10125 #define ESAI_TCR_TE5_SHIFT                       5
10126 #define ESAI_TCR_TSHFD_MASK                      0x40u
10127 #define ESAI_TCR_TSHFD_SHIFT                     6
10128 #define ESAI_TCR_TWA_MASK                        0x80u
10129 #define ESAI_TCR_TWA_SHIFT                       7
10130 #define ESAI_TCR_TMOD_MASK                       0x300u
10131 #define ESAI_TCR_TMOD_SHIFT                      8
10132 #define ESAI_TCR_TMOD(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TMOD_SHIFT))&ESAI_TCR_TMOD_MASK)
10133 #define ESAI_TCR_TSWS_MASK                       0x7C00u
10134 #define ESAI_TCR_TSWS_SHIFT                      10
10135 #define ESAI_TCR_TSWS(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TSWS_SHIFT))&ESAI_TCR_TSWS_MASK)
10136 #define ESAI_TCR_TFSL_MASK                       0x8000u
10137 #define ESAI_TCR_TFSL_SHIFT                      15
10138 #define ESAI_TCR_TFSR_MASK                       0x10000u
10139 #define ESAI_TCR_TFSR_SHIFT                      16
10140 #define ESAI_TCR_PADC_MASK                       0x20000u
10141 #define ESAI_TCR_PADC_SHIFT                      17
10142 #define ESAI_TCR_TPR_MASK                        0x80000u
10143 #define ESAI_TCR_TPR_SHIFT                       19
10144 #define ESAI_TCR_TEIE_MASK                       0x100000u
10145 #define ESAI_TCR_TEIE_SHIFT                      20
10146 #define ESAI_TCR_TEDIE_MASK                      0x200000u
10147 #define ESAI_TCR_TEDIE_SHIFT                     21
10148 #define ESAI_TCR_TIE_MASK                        0x400000u
10149 #define ESAI_TCR_TIE_SHIFT                       22
10150 #define ESAI_TCR_TLIE_MASK                       0x800000u
10151 #define ESAI_TCR_TLIE_SHIFT                      23
10152 /* TCCR Bit Fields */
10153 #define ESAI_TCCR_TPM_MASK                       0xFFu
10154 #define ESAI_TCCR_TPM_SHIFT                      0
10155 #define ESAI_TCCR_TPM(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TPM_SHIFT))&ESAI_TCCR_TPM_MASK)
10156 #define ESAI_TCCR_TPSR_MASK                      0x100u
10157 #define ESAI_TCCR_TPSR_SHIFT                     8
10158 #define ESAI_TCCR_TDC_MASK                       0x3E00u
10159 #define ESAI_TCCR_TDC_SHIFT                      9
10160 #define ESAI_TCCR_TDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TDC_SHIFT))&ESAI_TCCR_TDC_MASK)
10161 #define ESAI_TCCR_TFP_MASK                       0x3C000u
10162 #define ESAI_TCCR_TFP_SHIFT                      14
10163 #define ESAI_TCCR_TFP(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TFP_SHIFT))&ESAI_TCCR_TFP_MASK)
10164 #define ESAI_TCCR_TCKP_MASK                      0x40000u
10165 #define ESAI_TCCR_TCKP_SHIFT                     18
10166 #define ESAI_TCCR_TFSP_MASK                      0x80000u
10167 #define ESAI_TCCR_TFSP_SHIFT                     19
10168 #define ESAI_TCCR_THCKP_MASK                     0x100000u
10169 #define ESAI_TCCR_THCKP_SHIFT                    20
10170 #define ESAI_TCCR_TCKD_MASK                      0x200000u
10171 #define ESAI_TCCR_TCKD_SHIFT                     21
10172 #define ESAI_TCCR_TFSD_MASK                      0x400000u
10173 #define ESAI_TCCR_TFSD_SHIFT                     22
10174 #define ESAI_TCCR_THCKD_MASK                     0x800000u
10175 #define ESAI_TCCR_THCKD_SHIFT                    23
10176 /* RCR Bit Fields */
10177 #define ESAI_RCR_RE0_MASK                        0x1u
10178 #define ESAI_RCR_RE0_SHIFT                       0
10179 #define ESAI_RCR_RE1_MASK                        0x2u
10180 #define ESAI_RCR_RE1_SHIFT                       1
10181 #define ESAI_RCR_RE2_MASK                        0x4u
10182 #define ESAI_RCR_RE2_SHIFT                       2
10183 #define ESAI_RCR_RE3_MASK                        0x8u
10184 #define ESAI_RCR_RE3_SHIFT                       3
10185 #define ESAI_RCR_RSHFD_MASK                      0x40u
10186 #define ESAI_RCR_RSHFD_SHIFT                     6
10187 #define ESAI_RCR_RWA_MASK                        0x80u
10188 #define ESAI_RCR_RWA_SHIFT                       7
10189 #define ESAI_RCR_RMOD_MASK                       0x300u
10190 #define ESAI_RCR_RMOD_SHIFT                      8
10191 #define ESAI_RCR_RMOD(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RMOD_SHIFT))&ESAI_RCR_RMOD_MASK)
10192 #define ESAI_RCR_RSWS_MASK                       0x7C00u
10193 #define ESAI_RCR_RSWS_SHIFT                      10
10194 #define ESAI_RCR_RSWS(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RSWS_SHIFT))&ESAI_RCR_RSWS_MASK)
10195 #define ESAI_RCR_RFSL_MASK                       0x8000u
10196 #define ESAI_RCR_RFSL_SHIFT                      15
10197 #define ESAI_RCR_RFSR_MASK                       0x10000u
10198 #define ESAI_RCR_RFSR_SHIFT                      16
10199 #define ESAI_RCR_RPR_MASK                        0x80000u
10200 #define ESAI_RCR_RPR_SHIFT                       19
10201 #define ESAI_RCR_REIE_MASK                       0x100000u
10202 #define ESAI_RCR_REIE_SHIFT                      20
10203 #define ESAI_RCR_REDIE_MASK                      0x200000u
10204 #define ESAI_RCR_REDIE_SHIFT                     21
10205 #define ESAI_RCR_RIE_MASK                        0x400000u
10206 #define ESAI_RCR_RIE_SHIFT                       22
10207 #define ESAI_RCR_RLIE_MASK                       0x800000u
10208 #define ESAI_RCR_RLIE_SHIFT                      23
10209 /* RCCR Bit Fields */
10210 #define ESAI_RCCR_RPM_MASK                       0xFFu
10211 #define ESAI_RCCR_RPM_SHIFT                      0
10212 #define ESAI_RCCR_RPM(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RPM_SHIFT))&ESAI_RCCR_RPM_MASK)
10213 #define ESAI_RCCR_RPSR_MASK                      0x100u
10214 #define ESAI_RCCR_RPSR_SHIFT                     8
10215 #define ESAI_RCCR_RDC_MASK                       0x3E00u
10216 #define ESAI_RCCR_RDC_SHIFT                      9
10217 #define ESAI_RCCR_RDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RDC_SHIFT))&ESAI_RCCR_RDC_MASK)
10218 #define ESAI_RCCR_RFP_MASK                       0x3C000u
10219 #define ESAI_RCCR_RFP_SHIFT                      14
10220 #define ESAI_RCCR_RFP(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RFP_SHIFT))&ESAI_RCCR_RFP_MASK)
10221 #define ESAI_RCCR_RCKP_MASK                      0x40000u
10222 #define ESAI_RCCR_RCKP_SHIFT                     18
10223 #define ESAI_RCCR_RFSP_MASK                      0x80000u
10224 #define ESAI_RCCR_RFSP_SHIFT                     19
10225 #define ESAI_RCCR_RHCKP_MASK                     0x100000u
10226 #define ESAI_RCCR_RHCKP_SHIFT                    20
10227 #define ESAI_RCCR_RCKD_MASK                      0x200000u
10228 #define ESAI_RCCR_RCKD_SHIFT                     21
10229 #define ESAI_RCCR_RFSD_MASK                      0x400000u
10230 #define ESAI_RCCR_RFSD_SHIFT                     22
10231 #define ESAI_RCCR_RHCKD_MASK                     0x800000u
10232 #define ESAI_RCCR_RHCKD_SHIFT                    23
10233 /* TSMA Bit Fields */
10234 #define ESAI_TSMA_TS_MASK                        0xFFFFu
10235 #define ESAI_TSMA_TS_SHIFT                       0
10236 #define ESAI_TSMA_TS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSMA_TS_SHIFT))&ESAI_TSMA_TS_MASK)
10237 /* TSMB Bit Fields */
10238 #define ESAI_TSMB_TS_MASK                        0xFFFFu
10239 #define ESAI_TSMB_TS_SHIFT                       0
10240 #define ESAI_TSMB_TS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSMB_TS_SHIFT))&ESAI_TSMB_TS_MASK)
10241 /* RSMA Bit Fields */
10242 #define ESAI_RSMA_RS_MASK                        0xFFFFu
10243 #define ESAI_RSMA_RS_SHIFT                       0
10244 #define ESAI_RSMA_RS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_RSMA_RS_SHIFT))&ESAI_RSMA_RS_MASK)
10245 /* RSMB Bit Fields */
10246 #define ESAI_RSMB_RS_MASK                        0xFFFFu
10247 #define ESAI_RSMB_RS_SHIFT                       0
10248 #define ESAI_RSMB_RS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_RSMB_RS_SHIFT))&ESAI_RSMB_RS_MASK)
10249 /* PRRC Bit Fields */
10250 #define ESAI_PRRC_PDC_MASK                       0xFFFu
10251 #define ESAI_PRRC_PDC_SHIFT                      0
10252 #define ESAI_PRRC_PDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_PRRC_PDC_SHIFT))&ESAI_PRRC_PDC_MASK)
10253 /* PCRC Bit Fields */
10254 #define ESAI_PCRC_PC_MASK                        0xFFFu
10255 #define ESAI_PCRC_PC_SHIFT                       0
10256 #define ESAI_PCRC_PC(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_PCRC_PC_SHIFT))&ESAI_PCRC_PC_MASK)
10257 
10258 /*!
10259  * @}
10260  */ /* end of group ESAI_Register_Masks */
10261 
10262 /* ESAI - Peripheral instance base addresses */
10263 /** Peripheral ESAI base address */
10264 #define ESAI_BASE                                (0x42024000u)
10265 /** Peripheral ESAI base pointer */
10266 #define ESAI                                     ((ESAI_Type *)ESAI_BASE)
10267 #define ESAI_BASE_PTR                            (ESAI)
10268 /** Array initializer of ESAI peripheral base addresses */
10269 #define ESAI_BASE_ADDRS                          { ESAI_BASE }
10270 /** Array initializer of ESAI peripheral base pointers */
10271 #define ESAI_BASE_PTRS                           { ESAI }
10272 /** Interrupt vectors for the ESAI peripheral type */
10273 #define ESAI_IRQS                                { ESAI_IRQn }
10274 
10275 /* ----------------------------------------------------------------------------
10276    -- ESAI - Register accessor macros
10277    ---------------------------------------------------------------------------- */
10278 
10279 /*!
10280  * @addtogroup ESAI_Register_Accessor_Macros ESAI - Register accessor macros
10281  * @{
10282  */
10283 
10284 /* ESAI - Register instance definitions */
10285 /* ESAI */
10286 #define ESAI_ETDR                                ESAI_ETDR_REG(ESAI_BASE_PTR)
10287 #define ESAI_ERDR                                ESAI_ERDR_REG(ESAI_BASE_PTR)
10288 #define ESAI_ECR                                 ESAI_ECR_REG(ESAI_BASE_PTR)
10289 #define ESAI_ESR                                 ESAI_ESR_REG(ESAI_BASE_PTR)
10290 #define ESAI_TFCR                                ESAI_TFCR_REG(ESAI_BASE_PTR)
10291 #define ESAI_TFSR                                ESAI_TFSR_REG(ESAI_BASE_PTR)
10292 #define ESAI_RFCR                                ESAI_RFCR_REG(ESAI_BASE_PTR)
10293 #define ESAI_RFSR                                ESAI_RFSR_REG(ESAI_BASE_PTR)
10294 #define ESAI_TX0                                 ESAI_TX_REG(ESAI_BASE_PTR,0)
10295 #define ESAI_TX1                                 ESAI_TX_REG(ESAI_BASE_PTR,1)
10296 #define ESAI_TX2                                 ESAI_TX_REG(ESAI_BASE_PTR,2)
10297 #define ESAI_TX3                                 ESAI_TX_REG(ESAI_BASE_PTR,3)
10298 #define ESAI_TX4                                 ESAI_TX_REG(ESAI_BASE_PTR,4)
10299 #define ESAI_TX5                                 ESAI_TX_REG(ESAI_BASE_PTR,5)
10300 #define ESAI_TSR                                 ESAI_TSR_REG(ESAI_BASE_PTR)
10301 #define ESAI_RX0                                 ESAI_RX_REG(ESAI_BASE_PTR,0)
10302 #define ESAI_RX1                                 ESAI_RX_REG(ESAI_BASE_PTR,1)
10303 #define ESAI_RX2                                 ESAI_RX_REG(ESAI_BASE_PTR,2)
10304 #define ESAI_RX3                                 ESAI_RX_REG(ESAI_BASE_PTR,3)
10305 #define ESAI_SAISR                               ESAI_SAISR_REG(ESAI_BASE_PTR)
10306 #define ESAI_SAICR                               ESAI_SAICR_REG(ESAI_BASE_PTR)
10307 #define ESAI_TCR                                 ESAI_TCR_REG(ESAI_BASE_PTR)
10308 #define ESAI_TCCR                                ESAI_TCCR_REG(ESAI_BASE_PTR)
10309 #define ESAI_RCR                                 ESAI_RCR_REG(ESAI_BASE_PTR)
10310 #define ESAI_RCCR                                ESAI_RCCR_REG(ESAI_BASE_PTR)
10311 #define ESAI_TSMA                                ESAI_TSMA_REG(ESAI_BASE_PTR)
10312 #define ESAI_TSMB                                ESAI_TSMB_REG(ESAI_BASE_PTR)
10313 #define ESAI_RSMA                                ESAI_RSMA_REG(ESAI_BASE_PTR)
10314 #define ESAI_RSMB                                ESAI_RSMB_REG(ESAI_BASE_PTR)
10315 #define ESAI_PRRC                                ESAI_PRRC_REG(ESAI_BASE_PTR)
10316 #define ESAI_PCRC                                ESAI_PCRC_REG(ESAI_BASE_PTR)
10317 /* ESAI - Register array accessors */
10318 #define ESAI_TX(index)                           ESAI_TX_REG(ESAI_BASE_PTR,index)
10319 #define ESAI_RX(index)                           ESAI_RX_REG(ESAI_BASE_PTR,index)
10320 
10321 /*!
10322  * @}
10323  */ /* end of group ESAI_Register_Accessor_Macros */
10324 
10325 /*!
10326  * @}
10327  */ /* end of group ESAI_Peripheral */
10328 
10329 /* ----------------------------------------------------------------------------
10330    -- GIS Peripheral Access Layer
10331    ---------------------------------------------------------------------------- */
10332 
10333 /*!
10334  * @addtogroup GIS_Peripheral_Access_Layer GIS Peripheral Access Layer
10335  * @{
10336  */
10337 
10338 /** GIS - Register Layout Typedef */
10339 typedef struct {
10340   __IO  uint32_t CTRL;                                   /**< GIS Control Register, offset: 0x0 */
10341   __IO  uint32_t CTRL_SET;                               /**< GIS Control Register, offset: 0x4 */
10342   __IO  uint32_t CTRL_CLR;                               /**< GIS Control Register, offset: 0x8 */
10343   __IO  uint32_t CTRL_TOG;                               /**< GIS Control Register, offset: 0xC */
10344   __IO  uint32_t CONFIG0;                                /**< GIS Configuration 0 Register, offset: 0x10 */
10345   __IO  uint32_t CONFIG0_SET;                            /**< GIS Configuration 0 Register, offset: 0x14 */
10346   __IO  uint32_t CONFIG0_CLR;                            /**< GIS Configuration 0 Register, offset: 0x18 */
10347   __IO  uint32_t CONFIG0_TOG;                            /**< GIS Configuration 0 Register, offset: 0x1C */
10348   __IO  uint32_t CONFIG1;                                /**< GIS Configuration 1 Register, offset: 0x20 */
10349   __IO  uint32_t CONFIG1_SET;                            /**< GIS Configuration 1 Register, offset: 0x24 */
10350   __IO  uint32_t CONFIG1_CLR;                            /**< GIS Configuration 1 Register, offset: 0x28 */
10351   __IO  uint32_t CONFIG1_TOG;                            /**< GIS Configuration 1 Register, offset: 0x2C */
10352   __IO  uint32_t FB0;                                    /**< Camera Frame Buffer Address 0 Register, offset: 0x30 */
10353   uint8_t RESERVED_0[12];
10354   __IO  uint32_t FB1;                                    /**< Camera Frame Buffer Address 1 Register, offset: 0x40 */
10355   uint8_t RESERVED_1[12];
10356   __IO  uint32_t PXP_FB0;                                /**< PXP Frame Buffer Address 0 Register., offset: 0x50 */
10357   uint8_t RESERVED_2[12];
10358   __IO  uint32_t PXP_FB1;                                /**< PXP Frame Buffer Address 1 Register, offset: 0x60 */
10359   uint8_t RESERVED_3[12];
10360   __IO  uint32_t CH0_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x70 */
10361   __IO  uint32_t CH0_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x74 */
10362   __IO  uint32_t CH0_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x78 */
10363   __IO  uint32_t CH0_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x7C */
10364   __IO  uint32_t CH0_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x80 */
10365   __IO  uint32_t CH0_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x84 */
10366   __IO  uint32_t CH0_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x88 */
10367   __IO  uint32_t CH0_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x8C */
10368   __IO  uint32_t CH0_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x90 */
10369   uint8_t RESERVED_4[12];
10370   __IO  uint32_t CH0_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0xA0 */
10371   __IO  uint32_t CH0_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0xA4 */
10372   __IO  uint32_t CH0_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0xA8 */
10373   __IO  uint32_t CH0_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0xAC */
10374   __IO  uint32_t CH0_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0xB0 */
10375   uint8_t RESERVED_5[12];
10376   __IO  uint32_t CH0_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0xC0 */
10377   __IO  uint32_t CH0_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0xC4 */
10378   __IO  uint32_t CH0_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0xC8 */
10379   __IO  uint32_t CH0_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0xCC */
10380   __IO  uint32_t CH0_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0xD0 */
10381   uint8_t RESERVED_6[12];
10382   __IO  uint32_t CH0_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0xE0 */
10383   __IO  uint32_t CH0_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0xE4 */
10384   __IO  uint32_t CH0_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0xE8 */
10385   __IO  uint32_t CH0_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0xEC */
10386   __IO  uint32_t CH0_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0xF0 */
10387   uint8_t RESERVED_7[12];
10388   __IO  uint32_t CH1_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x100 */
10389   __IO  uint32_t CH1_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x104 */
10390   __IO  uint32_t CH1_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x108 */
10391   __IO  uint32_t CH1_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x10C */
10392   __IO  uint32_t CH1_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x110 */
10393   __IO  uint32_t CH1_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x114 */
10394   __IO  uint32_t CH1_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x118 */
10395   __IO  uint32_t CH1_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x11C */
10396   __IO  uint32_t CH1_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x120 */
10397   uint8_t RESERVED_8[12];
10398   __IO  uint32_t CH1_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0x130 */
10399   __IO  uint32_t CH1_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0x134 */
10400   __IO  uint32_t CH1_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0x138 */
10401   __IO  uint32_t CH1_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0x13C */
10402   __IO  uint32_t CH1_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0x140 */
10403   uint8_t RESERVED_9[12];
10404   __IO  uint32_t CH1_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0x150 */
10405   __IO  uint32_t CH1_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0x154 */
10406   __IO  uint32_t CH1_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0x158 */
10407   __IO  uint32_t CH1_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0x15C */
10408   __IO  uint32_t CH1_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0x160 */
10409   uint8_t RESERVED_10[12];
10410   __IO  uint32_t CH1_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0x170 */
10411   __IO  uint32_t CH1_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0x174 */
10412   __IO  uint32_t CH1_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0x178 */
10413   __IO  uint32_t CH1_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0x17C */
10414   __IO  uint32_t CH1_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0x180 */
10415   uint8_t RESERVED_11[12];
10416   __IO  uint32_t CH2_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x190 */
10417   __IO  uint32_t CH2_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x194 */
10418   __IO  uint32_t CH2_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x198 */
10419   __IO  uint32_t CH2_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x19C */
10420   __IO  uint32_t CH2_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x1A0 */
10421   __IO  uint32_t CH2_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x1A4 */
10422   __IO  uint32_t CH2_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x1A8 */
10423   __IO  uint32_t CH2_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x1AC */
10424   __IO  uint32_t CH2_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x1B0 */
10425   uint8_t RESERVED_12[12];
10426   __IO  uint32_t CH2_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0x1C0 */
10427   __IO  uint32_t CH2_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0x1C4 */
10428   __IO  uint32_t CH2_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0x1C8 */
10429   __IO  uint32_t CH2_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0x1CC */
10430   __IO  uint32_t CH2_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0x1D0 */
10431   uint8_t RESERVED_13[12];
10432   __IO  uint32_t CH2_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0x1E0 */
10433   __IO  uint32_t CH2_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0x1E4 */
10434   __IO  uint32_t CH2_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0x1E8 */
10435   __IO  uint32_t CH2_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0x1EC */
10436   __IO  uint32_t CH2_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0x1F0 */
10437   uint8_t RESERVED_14[12];
10438   __IO  uint32_t CH2_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0x200 */
10439   __IO  uint32_t CH2_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0x204 */
10440   __IO  uint32_t CH2_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0x208 */
10441   __IO  uint32_t CH2_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0x20C */
10442   __IO  uint32_t CH2_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0x210 */
10443   uint8_t RESERVED_15[12];
10444   __IO  uint32_t CH3_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x220 */
10445   __IO  uint32_t CH3_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x224 */
10446   __IO  uint32_t CH3_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x228 */
10447   __IO  uint32_t CH3_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x22C */
10448   __IO  uint32_t CH3_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x230 */
10449   __IO  uint32_t CH3_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x234 */
10450   __IO  uint32_t CH3_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x238 */
10451   __IO  uint32_t CH3_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x23C */
10452   __IO  uint32_t CH3_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x240 */
10453   uint8_t RESERVED_16[12];
10454   __IO  uint32_t CH3_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0x250 */
10455   __IO  uint32_t CH3_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0x254 */
10456   __IO  uint32_t CH3_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0x258 */
10457   __IO  uint32_t CH3_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0x25C */
10458   __IO  uint32_t CH3_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0x260 */
10459   uint8_t RESERVED_17[12];
10460   __IO  uint32_t CH3_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0x270 */
10461   __IO  uint32_t CH3_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0x274 */
10462   __IO  uint32_t CH3_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0x278 */
10463   __IO  uint32_t CH3_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0x27C */
10464   __IO  uint32_t CH3_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0x280 */
10465   uint8_t RESERVED_18[12];
10466   __IO  uint32_t CH3_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0x290 */
10467   __IO  uint32_t CH3_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0x294 */
10468   __IO  uint32_t CH3_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0x298 */
10469   __IO  uint32_t CH3_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0x29C */
10470   __IO  uint32_t CH3_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0x2A0 */
10471   uint8_t RESERVED_19[12];
10472   __IO  uint32_t CH4_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x2B0 */
10473   __IO  uint32_t CH4_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x2B4 */
10474   __IO  uint32_t CH4_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x2B8 */
10475   __IO  uint32_t CH4_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x2BC */
10476   __IO  uint32_t CH4_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x2C0 */
10477   __IO  uint32_t CH4_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x2C4 */
10478   __IO  uint32_t CH4_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x2C8 */
10479   __IO  uint32_t CH4_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x2CC */
10480   __IO  uint32_t CH4_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x2D0 */
10481   uint8_t RESERVED_20[12];
10482   __IO  uint32_t CH4_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0x2E0 */
10483   __IO  uint32_t CH4_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0x2E4 */
10484   __IO  uint32_t CH4_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0x2E8 */
10485   __IO  uint32_t CH4_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0x2EC */
10486   __IO  uint32_t CH4_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0x2F0 */
10487   uint8_t RESERVED_21[12];
10488   __IO  uint32_t CH4_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0x300 */
10489   __IO  uint32_t CH4_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0x304 */
10490   __IO  uint32_t CH4_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0x308 */
10491   __IO  uint32_t CH4_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0x30C */
10492   __IO  uint32_t CH4_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0x310 */
10493   uint8_t RESERVED_22[12];
10494   __IO  uint32_t CH4_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0x320 */
10495   __IO  uint32_t CH4_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0x324 */
10496   __IO  uint32_t CH4_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0x328 */
10497   __IO  uint32_t CH4_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0x32C */
10498   __IO  uint32_t CH4_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0x330 */
10499   uint8_t RESERVED_23[12];
10500   __IO  uint32_t CH5_CTRL;                               /**< Control Command Channel 0 Register, offset: 0x340 */
10501   __IO  uint32_t CH5_CTRL_SET;                           /**< Control Command Channel 0 Register, offset: 0x344 */
10502   __IO  uint32_t CH5_CTRL_CLR;                           /**< Control Command Channel 0 Register, offset: 0x348 */
10503   __IO  uint32_t CH5_CTRL_TOG;                           /**< Control Command Channel 0 Register, offset: 0x34C */
10504   __IO  uint32_t CH5_ADDR0;                              /**< Channel 0 Command 0 Address Register., offset: 0x350 */
10505   __IO  uint32_t CH5_ADDR0_SET;                          /**< Channel 0 Command 0 Address Register., offset: 0x354 */
10506   __IO  uint32_t CH5_ADDR0_CLR;                          /**< Channel 0 Command 0 Address Register., offset: 0x358 */
10507   __IO  uint32_t CH5_ADDR0_TOG;                          /**< Channel 0 Command 0 Address Register., offset: 0x35C */
10508   __IO  uint32_t CH5_DATA0;                              /**< Channel 0 Command 0 Data Register, offset: 0x360 */
10509   uint8_t RESERVED_24[12];
10510   __IO  uint32_t CH5_ADDR1;                              /**< Channel 0 Command 1 Address Register., offset: 0x370 */
10511   __IO  uint32_t CH5_ADDR1_SET;                          /**< Channel 0 Command 1 Address Register., offset: 0x374 */
10512   __IO  uint32_t CH5_ADDR1_CLR;                          /**< Channel 0 Command 1 Address Register., offset: 0x378 */
10513   __IO  uint32_t CH5_ADDR1_TOG;                          /**< Channel 0 Command 1 Address Register., offset: 0x37C */
10514   __IO  uint32_t CH5_DATA1;                              /**< Channel 0 Command 1 Data Register, offset: 0x380 */
10515   uint8_t RESERVED_25[12];
10516   __IO  uint32_t CH5_ADDR2;                              /**< Channel 0 Command 2 Address Register., offset: 0x390 */
10517   __IO  uint32_t CH5_ADDR2_SET;                          /**< Channel 0 Command 2 Address Register., offset: 0x394 */
10518   __IO  uint32_t CH5_ADDR2_CLR;                          /**< Channel 0 Command 2 Address Register., offset: 0x398 */
10519   __IO  uint32_t CH5_ADDR2_TOG;                          /**< Channel 0 Command 2 Address Register., offset: 0x39C */
10520   __IO  uint32_t CH5_DATA2;                              /**< Channel 0 Command 2 Data Register, offset: 0x3A0 */
10521   uint8_t RESERVED_26[12];
10522   __IO  uint32_t CH5_ADDR3;                              /**< Channel 0 Command 3 Address Register., offset: 0x3B0 */
10523   __IO  uint32_t CH5_ADDR3_SET;                          /**< Channel 0 Command 3 Address Register., offset: 0x3B4 */
10524   __IO  uint32_t CH5_ADDR3_CLR;                          /**< Channel 0 Command 3 Address Register., offset: 0x3B8 */
10525   __IO  uint32_t CH5_ADDR3_TOG;                          /**< Channel 0 Command 3 Address Register., offset: 0x3BC */
10526   __IO  uint32_t CH5_DATA3;                              /**< Channel 0 Command 3 Data Register, offset: 0x3C0 */
10527   uint8_t RESERVED_27[12];
10528   __I   uint32_t DEBUG0;                                 /**< Debug 0 Register, offset: 0x3D0 */
10529   uint8_t RESERVED_28[12];
10530   __I   uint32_t DEBUG1;                                 /**< Debug 1 Register, offset: 0x3E0 */
10531   uint8_t RESERVED_29[12];
10532   __I   uint32_t VERSION;                                /**< Version Register, offset: 0x3F0 */
10533 } GIS_Type, *GIS_MemMapPtr;
10534 
10535 /* ----------------------------------------------------------------------------
10536    -- GIS - Register accessor macros
10537    ---------------------------------------------------------------------------- */
10538 
10539 /*!
10540  * @addtogroup GIS_Register_Accessor_Macros GIS - Register accessor macros
10541  * @{
10542  */
10543 
10544 /* GIS - Register accessors */
10545 #define GIS_CTRL_REG(base)                       ((base)->CTRL)
10546 #define GIS_CTRL_SET_REG(base)                   ((base)->CTRL_SET)
10547 #define GIS_CTRL_CLR_REG(base)                   ((base)->CTRL_CLR)
10548 #define GIS_CTRL_TOG_REG(base)                   ((base)->CTRL_TOG)
10549 #define GIS_CONFIG0_REG(base)                    ((base)->CONFIG0)
10550 #define GIS_CONFIG0_SET_REG(base)                ((base)->CONFIG0_SET)
10551 #define GIS_CONFIG0_CLR_REG(base)                ((base)->CONFIG0_CLR)
10552 #define GIS_CONFIG0_TOG_REG(base)                ((base)->CONFIG0_TOG)
10553 #define GIS_CONFIG1_REG(base)                    ((base)->CONFIG1)
10554 #define GIS_CONFIG1_SET_REG(base)                ((base)->CONFIG1_SET)
10555 #define GIS_CONFIG1_CLR_REG(base)                ((base)->CONFIG1_CLR)
10556 #define GIS_CONFIG1_TOG_REG(base)                ((base)->CONFIG1_TOG)
10557 #define GIS_FB0_REG(base)                        ((base)->FB0)
10558 #define GIS_FB1_REG(base)                        ((base)->FB1)
10559 #define GIS_PXP_FB0_REG(base)                    ((base)->PXP_FB0)
10560 #define GIS_PXP_FB1_REG(base)                    ((base)->PXP_FB1)
10561 #define GIS_CH0_CTRL_REG(base)                   ((base)->CH0_CTRL)
10562 #define GIS_CH0_CTRL_SET_REG(base)               ((base)->CH0_CTRL_SET)
10563 #define GIS_CH0_CTRL_CLR_REG(base)               ((base)->CH0_CTRL_CLR)
10564 #define GIS_CH0_CTRL_TOG_REG(base)               ((base)->CH0_CTRL_TOG)
10565 #define GIS_CH0_ADDR0_REG(base)                  ((base)->CH0_ADDR0)
10566 #define GIS_CH0_ADDR0_SET_REG(base)              ((base)->CH0_ADDR0_SET)
10567 #define GIS_CH0_ADDR0_CLR_REG(base)              ((base)->CH0_ADDR0_CLR)
10568 #define GIS_CH0_ADDR0_TOG_REG(base)              ((base)->CH0_ADDR0_TOG)
10569 #define GIS_CH0_DATA0_REG(base)                  ((base)->CH0_DATA0)
10570 #define GIS_CH0_ADDR1_REG(base)                  ((base)->CH0_ADDR1)
10571 #define GIS_CH0_ADDR1_SET_REG(base)              ((base)->CH0_ADDR1_SET)
10572 #define GIS_CH0_ADDR1_CLR_REG(base)              ((base)->CH0_ADDR1_CLR)
10573 #define GIS_CH0_ADDR1_TOG_REG(base)              ((base)->CH0_ADDR1_TOG)
10574 #define GIS_CH0_DATA1_REG(base)                  ((base)->CH0_DATA1)
10575 #define GIS_CH0_ADDR2_REG(base)                  ((base)->CH0_ADDR2)
10576 #define GIS_CH0_ADDR2_SET_REG(base)              ((base)->CH0_ADDR2_SET)
10577 #define GIS_CH0_ADDR2_CLR_REG(base)              ((base)->CH0_ADDR2_CLR)
10578 #define GIS_CH0_ADDR2_TOG_REG(base)              ((base)->CH0_ADDR2_TOG)
10579 #define GIS_CH0_DATA2_REG(base)                  ((base)->CH0_DATA2)
10580 #define GIS_CH0_ADDR3_REG(base)                  ((base)->CH0_ADDR3)
10581 #define GIS_CH0_ADDR3_SET_REG(base)              ((base)->CH0_ADDR3_SET)
10582 #define GIS_CH0_ADDR3_CLR_REG(base)              ((base)->CH0_ADDR3_CLR)
10583 #define GIS_CH0_ADDR3_TOG_REG(base)              ((base)->CH0_ADDR3_TOG)
10584 #define GIS_CH0_DATA3_REG(base)                  ((base)->CH0_DATA3)
10585 #define GIS_CH1_CTRL_REG(base)                   ((base)->CH1_CTRL)
10586 #define GIS_CH1_CTRL_SET_REG(base)               ((base)->CH1_CTRL_SET)
10587 #define GIS_CH1_CTRL_CLR_REG(base)               ((base)->CH1_CTRL_CLR)
10588 #define GIS_CH1_CTRL_TOG_REG(base)               ((base)->CH1_CTRL_TOG)
10589 #define GIS_CH1_ADDR0_REG(base)                  ((base)->CH1_ADDR0)
10590 #define GIS_CH1_ADDR0_SET_REG(base)              ((base)->CH1_ADDR0_SET)
10591 #define GIS_CH1_ADDR0_CLR_REG(base)              ((base)->CH1_ADDR0_CLR)
10592 #define GIS_CH1_ADDR0_TOG_REG(base)              ((base)->CH1_ADDR0_TOG)
10593 #define GIS_CH1_DATA0_REG(base)                  ((base)->CH1_DATA0)
10594 #define GIS_CH1_ADDR1_REG(base)                  ((base)->CH1_ADDR1)
10595 #define GIS_CH1_ADDR1_SET_REG(base)              ((base)->CH1_ADDR1_SET)
10596 #define GIS_CH1_ADDR1_CLR_REG(base)              ((base)->CH1_ADDR1_CLR)
10597 #define GIS_CH1_ADDR1_TOG_REG(base)              ((base)->CH1_ADDR1_TOG)
10598 #define GIS_CH1_DATA1_REG(base)                  ((base)->CH1_DATA1)
10599 #define GIS_CH1_ADDR2_REG(base)                  ((base)->CH1_ADDR2)
10600 #define GIS_CH1_ADDR2_SET_REG(base)              ((base)->CH1_ADDR2_SET)
10601 #define GIS_CH1_ADDR2_CLR_REG(base)              ((base)->CH1_ADDR2_CLR)
10602 #define GIS_CH1_ADDR2_TOG_REG(base)              ((base)->CH1_ADDR2_TOG)
10603 #define GIS_CH1_DATA2_REG(base)                  ((base)->CH1_DATA2)
10604 #define GIS_CH1_ADDR3_REG(base)                  ((base)->CH1_ADDR3)
10605 #define GIS_CH1_ADDR3_SET_REG(base)              ((base)->CH1_ADDR3_SET)
10606 #define GIS_CH1_ADDR3_CLR_REG(base)              ((base)->CH1_ADDR3_CLR)
10607 #define GIS_CH1_ADDR3_TOG_REG(base)              ((base)->CH1_ADDR3_TOG)
10608 #define GIS_CH1_DATA3_REG(base)                  ((base)->CH1_DATA3)
10609 #define GIS_CH2_CTRL_REG(base)                   ((base)->CH2_CTRL)
10610 #define GIS_CH2_CTRL_SET_REG(base)               ((base)->CH2_CTRL_SET)
10611 #define GIS_CH2_CTRL_CLR_REG(base)               ((base)->CH2_CTRL_CLR)
10612 #define GIS_CH2_CTRL_TOG_REG(base)               ((base)->CH2_CTRL_TOG)
10613 #define GIS_CH2_ADDR0_REG(base)                  ((base)->CH2_ADDR0)
10614 #define GIS_CH2_ADDR0_SET_REG(base)              ((base)->CH2_ADDR0_SET)
10615 #define GIS_CH2_ADDR0_CLR_REG(base)              ((base)->CH2_ADDR0_CLR)
10616 #define GIS_CH2_ADDR0_TOG_REG(base)              ((base)->CH2_ADDR0_TOG)
10617 #define GIS_CH2_DATA0_REG(base)                  ((base)->CH2_DATA0)
10618 #define GIS_CH2_ADDR1_REG(base)                  ((base)->CH2_ADDR1)
10619 #define GIS_CH2_ADDR1_SET_REG(base)              ((base)->CH2_ADDR1_SET)
10620 #define GIS_CH2_ADDR1_CLR_REG(base)              ((base)->CH2_ADDR1_CLR)
10621 #define GIS_CH2_ADDR1_TOG_REG(base)              ((base)->CH2_ADDR1_TOG)
10622 #define GIS_CH2_DATA1_REG(base)                  ((base)->CH2_DATA1)
10623 #define GIS_CH2_ADDR2_REG(base)                  ((base)->CH2_ADDR2)
10624 #define GIS_CH2_ADDR2_SET_REG(base)              ((base)->CH2_ADDR2_SET)
10625 #define GIS_CH2_ADDR2_CLR_REG(base)              ((base)->CH2_ADDR2_CLR)
10626 #define GIS_CH2_ADDR2_TOG_REG(base)              ((base)->CH2_ADDR2_TOG)
10627 #define GIS_CH2_DATA2_REG(base)                  ((base)->CH2_DATA2)
10628 #define GIS_CH2_ADDR3_REG(base)                  ((base)->CH2_ADDR3)
10629 #define GIS_CH2_ADDR3_SET_REG(base)              ((base)->CH2_ADDR3_SET)
10630 #define GIS_CH2_ADDR3_CLR_REG(base)              ((base)->CH2_ADDR3_CLR)
10631 #define GIS_CH2_ADDR3_TOG_REG(base)              ((base)->CH2_ADDR3_TOG)
10632 #define GIS_CH2_DATA3_REG(base)                  ((base)->CH2_DATA3)
10633 #define GIS_CH3_CTRL_REG(base)                   ((base)->CH3_CTRL)
10634 #define GIS_CH3_CTRL_SET_REG(base)               ((base)->CH3_CTRL_SET)
10635 #define GIS_CH3_CTRL_CLR_REG(base)               ((base)->CH3_CTRL_CLR)
10636 #define GIS_CH3_CTRL_TOG_REG(base)               ((base)->CH3_CTRL_TOG)
10637 #define GIS_CH3_ADDR0_REG(base)                  ((base)->CH3_ADDR0)
10638 #define GIS_CH3_ADDR0_SET_REG(base)              ((base)->CH3_ADDR0_SET)
10639 #define GIS_CH3_ADDR0_CLR_REG(base)              ((base)->CH3_ADDR0_CLR)
10640 #define GIS_CH3_ADDR0_TOG_REG(base)              ((base)->CH3_ADDR0_TOG)
10641 #define GIS_CH3_DATA0_REG(base)                  ((base)->CH3_DATA0)
10642 #define GIS_CH3_ADDR1_REG(base)                  ((base)->CH3_ADDR1)
10643 #define GIS_CH3_ADDR1_SET_REG(base)              ((base)->CH3_ADDR1_SET)
10644 #define GIS_CH3_ADDR1_CLR_REG(base)              ((base)->CH3_ADDR1_CLR)
10645 #define GIS_CH3_ADDR1_TOG_REG(base)              ((base)->CH3_ADDR1_TOG)
10646 #define GIS_CH3_DATA1_REG(base)                  ((base)->CH3_DATA1)
10647 #define GIS_CH3_ADDR2_REG(base)                  ((base)->CH3_ADDR2)
10648 #define GIS_CH3_ADDR2_SET_REG(base)              ((base)->CH3_ADDR2_SET)
10649 #define GIS_CH3_ADDR2_CLR_REG(base)              ((base)->CH3_ADDR2_CLR)
10650 #define GIS_CH3_ADDR2_TOG_REG(base)              ((base)->CH3_ADDR2_TOG)
10651 #define GIS_CH3_DATA2_REG(base)                  ((base)->CH3_DATA2)
10652 #define GIS_CH3_ADDR3_REG(base)                  ((base)->CH3_ADDR3)
10653 #define GIS_CH3_ADDR3_SET_REG(base)              ((base)->CH3_ADDR3_SET)
10654 #define GIS_CH3_ADDR3_CLR_REG(base)              ((base)->CH3_ADDR3_CLR)
10655 #define GIS_CH3_ADDR3_TOG_REG(base)              ((base)->CH3_ADDR3_TOG)
10656 #define GIS_CH3_DATA3_REG(base)                  ((base)->CH3_DATA3)
10657 #define GIS_CH4_CTRL_REG(base)                   ((base)->CH4_CTRL)
10658 #define GIS_CH4_CTRL_SET_REG(base)               ((base)->CH4_CTRL_SET)
10659 #define GIS_CH4_CTRL_CLR_REG(base)               ((base)->CH4_CTRL_CLR)
10660 #define GIS_CH4_CTRL_TOG_REG(base)               ((base)->CH4_CTRL_TOG)
10661 #define GIS_CH4_ADDR0_REG(base)                  ((base)->CH4_ADDR0)
10662 #define GIS_CH4_ADDR0_SET_REG(base)              ((base)->CH4_ADDR0_SET)
10663 #define GIS_CH4_ADDR0_CLR_REG(base)              ((base)->CH4_ADDR0_CLR)
10664 #define GIS_CH4_ADDR0_TOG_REG(base)              ((base)->CH4_ADDR0_TOG)
10665 #define GIS_CH4_DATA0_REG(base)                  ((base)->CH4_DATA0)
10666 #define GIS_CH4_ADDR1_REG(base)                  ((base)->CH4_ADDR1)
10667 #define GIS_CH4_ADDR1_SET_REG(base)              ((base)->CH4_ADDR1_SET)
10668 #define GIS_CH4_ADDR1_CLR_REG(base)              ((base)->CH4_ADDR1_CLR)
10669 #define GIS_CH4_ADDR1_TOG_REG(base)              ((base)->CH4_ADDR1_TOG)
10670 #define GIS_CH4_DATA1_REG(base)                  ((base)->CH4_DATA1)
10671 #define GIS_CH4_ADDR2_REG(base)                  ((base)->CH4_ADDR2)
10672 #define GIS_CH4_ADDR2_SET_REG(base)              ((base)->CH4_ADDR2_SET)
10673 #define GIS_CH4_ADDR2_CLR_REG(base)              ((base)->CH4_ADDR2_CLR)
10674 #define GIS_CH4_ADDR2_TOG_REG(base)              ((base)->CH4_ADDR2_TOG)
10675 #define GIS_CH4_DATA2_REG(base)                  ((base)->CH4_DATA2)
10676 #define GIS_CH4_ADDR3_REG(base)                  ((base)->CH4_ADDR3)
10677 #define GIS_CH4_ADDR3_SET_REG(base)              ((base)->CH4_ADDR3_SET)
10678 #define GIS_CH4_ADDR3_CLR_REG(base)              ((base)->CH4_ADDR3_CLR)
10679 #define GIS_CH4_ADDR3_TOG_REG(base)              ((base)->CH4_ADDR3_TOG)
10680 #define GIS_CH4_DATA3_REG(base)                  ((base)->CH4_DATA3)
10681 #define GIS_CH5_CTRL_REG(base)                   ((base)->CH5_CTRL)
10682 #define GIS_CH5_CTRL_SET_REG(base)               ((base)->CH5_CTRL_SET)
10683 #define GIS_CH5_CTRL_CLR_REG(base)               ((base)->CH5_CTRL_CLR)
10684 #define GIS_CH5_CTRL_TOG_REG(base)               ((base)->CH5_CTRL_TOG)
10685 #define GIS_CH5_ADDR0_REG(base)                  ((base)->CH5_ADDR0)
10686 #define GIS_CH5_ADDR0_SET_REG(base)              ((base)->CH5_ADDR0_SET)
10687 #define GIS_CH5_ADDR0_CLR_REG(base)              ((base)->CH5_ADDR0_CLR)
10688 #define GIS_CH5_ADDR0_TOG_REG(base)              ((base)->CH5_ADDR0_TOG)
10689 #define GIS_CH5_DATA0_REG(base)                  ((base)->CH5_DATA0)
10690 #define GIS_CH5_ADDR1_REG(base)                  ((base)->CH5_ADDR1)
10691 #define GIS_CH5_ADDR1_SET_REG(base)              ((base)->CH5_ADDR1_SET)
10692 #define GIS_CH5_ADDR1_CLR_REG(base)              ((base)->CH5_ADDR1_CLR)
10693 #define GIS_CH5_ADDR1_TOG_REG(base)              ((base)->CH5_ADDR1_TOG)
10694 #define GIS_CH5_DATA1_REG(base)                  ((base)->CH5_DATA1)
10695 #define GIS_CH5_ADDR2_REG(base)                  ((base)->CH5_ADDR2)
10696 #define GIS_CH5_ADDR2_SET_REG(base)              ((base)->CH5_ADDR2_SET)
10697 #define GIS_CH5_ADDR2_CLR_REG(base)              ((base)->CH5_ADDR2_CLR)
10698 #define GIS_CH5_ADDR2_TOG_REG(base)              ((base)->CH5_ADDR2_TOG)
10699 #define GIS_CH5_DATA2_REG(base)                  ((base)->CH5_DATA2)
10700 #define GIS_CH5_ADDR3_REG(base)                  ((base)->CH5_ADDR3)
10701 #define GIS_CH5_ADDR3_SET_REG(base)              ((base)->CH5_ADDR3_SET)
10702 #define GIS_CH5_ADDR3_CLR_REG(base)              ((base)->CH5_ADDR3_CLR)
10703 #define GIS_CH5_ADDR3_TOG_REG(base)              ((base)->CH5_ADDR3_TOG)
10704 #define GIS_CH5_DATA3_REG(base)                  ((base)->CH5_DATA3)
10705 #define GIS_DEBUG0_REG(base)                     ((base)->DEBUG0)
10706 #define GIS_DEBUG1_REG(base)                     ((base)->DEBUG1)
10707 #define GIS_VERSION_REG(base)                    ((base)->VERSION)
10708 
10709 /*!
10710  * @}
10711  */ /* end of group GIS_Register_Accessor_Macros */
10712 
10713 /* ----------------------------------------------------------------------------
10714    -- GIS Register Masks
10715    ---------------------------------------------------------------------------- */
10716 
10717 /*!
10718  * @addtogroup GIS_Register_Masks GIS Register Masks
10719  * @{
10720  */
10721 
10722 /* CTRL Bit Fields */
10723 #define GIS_CTRL_ENABLE_MASK                     0x1u
10724 #define GIS_CTRL_ENABLE_SHIFT                    0
10725 #define GIS_CTRL_FB_START_MASK                   0x2u
10726 #define GIS_CTRL_FB_START_SHIFT                  1
10727 #define GIS_CTRL_LCDIF_SEL_MASK                  0x4u
10728 #define GIS_CTRL_LCDIF_SEL_SHIFT                 2
10729 #define GIS_CTRL_CSI_SEL_MASK                    0x8u
10730 #define GIS_CTRL_CSI_SEL_SHIFT                   3
10731 #define GIS_CTRL_CSI0_IRQ_POLARITY_MASK          0x10u
10732 #define GIS_CTRL_CSI0_IRQ_POLARITY_SHIFT         4
10733 #define GIS_CTRL_CSI1_IRQ_POLARITY_MASK          0x20u
10734 #define GIS_CTRL_CSI1_IRQ_POLARITY_SHIFT         5
10735 #define GIS_CTRL_PXP_IRQ_POLARITY_MASK           0x40u
10736 #define GIS_CTRL_PXP_IRQ_POLARITY_SHIFT          6
10737 #define GIS_CTRL_LCDIF0_IRQ_POLARITY_MASK        0x80u
10738 #define GIS_CTRL_LCDIF0_IRQ_POLARITY_SHIFT       7
10739 #define GIS_CTRL_LCDIF1_IRQ_POLARITY_MASK        0x100u
10740 #define GIS_CTRL_LCDIF1_IRQ_POLARITY_SHIFT       8
10741 #define GIS_CTRL_CLKGATE_MASK                    0x40000000u
10742 #define GIS_CTRL_CLKGATE_SHIFT                   30
10743 #define GIS_CTRL_SFTRST_MASK                     0x80000000u
10744 #define GIS_CTRL_SFTRST_SHIFT                    31
10745 /* CTRL_SET Bit Fields */
10746 #define GIS_CTRL_SET_ENABLE_MASK                 0x1u
10747 #define GIS_CTRL_SET_ENABLE_SHIFT                0
10748 #define GIS_CTRL_SET_FB_START_MASK               0x2u
10749 #define GIS_CTRL_SET_FB_START_SHIFT              1
10750 #define GIS_CTRL_SET_LCDIF_SEL_MASK              0x4u
10751 #define GIS_CTRL_SET_LCDIF_SEL_SHIFT             2
10752 #define GIS_CTRL_SET_CSI_SEL_MASK                0x8u
10753 #define GIS_CTRL_SET_CSI_SEL_SHIFT               3
10754 #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_MASK      0x10u
10755 #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_SHIFT     4
10756 #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_MASK      0x20u
10757 #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_SHIFT     5
10758 #define GIS_CTRL_SET_PXP_IRQ_POLARITY_MASK       0x40u
10759 #define GIS_CTRL_SET_PXP_IRQ_POLARITY_SHIFT      6
10760 #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_MASK    0x80u
10761 #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_SHIFT   7
10762 #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_MASK    0x100u
10763 #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_SHIFT   8
10764 #define GIS_CTRL_SET_CLKGATE_MASK                0x40000000u
10765 #define GIS_CTRL_SET_CLKGATE_SHIFT               30
10766 #define GIS_CTRL_SET_SFTRST_MASK                 0x80000000u
10767 #define GIS_CTRL_SET_SFTRST_SHIFT                31
10768 /* CTRL_CLR Bit Fields */
10769 #define GIS_CTRL_CLR_ENABLE_MASK                 0x1u
10770 #define GIS_CTRL_CLR_ENABLE_SHIFT                0
10771 #define GIS_CTRL_CLR_FB_START_MASK               0x2u
10772 #define GIS_CTRL_CLR_FB_START_SHIFT              1
10773 #define GIS_CTRL_CLR_LCDIF_SEL_MASK              0x4u
10774 #define GIS_CTRL_CLR_LCDIF_SEL_SHIFT             2
10775 #define GIS_CTRL_CLR_CSI_SEL_MASK                0x8u
10776 #define GIS_CTRL_CLR_CSI_SEL_SHIFT               3
10777 #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_MASK      0x10u
10778 #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_SHIFT     4
10779 #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_MASK      0x20u
10780 #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_SHIFT     5
10781 #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_MASK       0x40u
10782 #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_SHIFT      6
10783 #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_MASK    0x80u
10784 #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_SHIFT   7
10785 #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_MASK    0x100u
10786 #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_SHIFT   8
10787 #define GIS_CTRL_CLR_CLKGATE_MASK                0x40000000u
10788 #define GIS_CTRL_CLR_CLKGATE_SHIFT               30
10789 #define GIS_CTRL_CLR_SFTRST_MASK                 0x80000000u
10790 #define GIS_CTRL_CLR_SFTRST_SHIFT                31
10791 /* CTRL_TOG Bit Fields */
10792 #define GIS_CTRL_TOG_ENABLE_MASK                 0x1u
10793 #define GIS_CTRL_TOG_ENABLE_SHIFT                0
10794 #define GIS_CTRL_TOG_FB_START_MASK               0x2u
10795 #define GIS_CTRL_TOG_FB_START_SHIFT              1
10796 #define GIS_CTRL_TOG_LCDIF_SEL_MASK              0x4u
10797 #define GIS_CTRL_TOG_LCDIF_SEL_SHIFT             2
10798 #define GIS_CTRL_TOG_CSI_SEL_MASK                0x8u
10799 #define GIS_CTRL_TOG_CSI_SEL_SHIFT               3
10800 #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_MASK      0x10u
10801 #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_SHIFT     4
10802 #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_MASK      0x20u
10803 #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_SHIFT     5
10804 #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_MASK       0x40u
10805 #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_SHIFT      6
10806 #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_MASK    0x80u
10807 #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_SHIFT   7
10808 #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_MASK    0x100u
10809 #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_SHIFT   8
10810 #define GIS_CTRL_TOG_CLKGATE_MASK                0x40000000u
10811 #define GIS_CTRL_TOG_CLKGATE_SHIFT               30
10812 #define GIS_CTRL_TOG_SFTRST_MASK                 0x80000000u
10813 #define GIS_CTRL_TOG_SFTRST_SHIFT                31
10814 /* CONFIG0 Bit Fields */
10815 #define GIS_CONFIG0_CH0_MAPPING_MASK             0x7u
10816 #define GIS_CONFIG0_CH0_MAPPING_SHIFT            0
10817 #define GIS_CONFIG0_CH0_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH0_MAPPING_SHIFT))&GIS_CONFIG0_CH0_MAPPING_MASK)
10818 #define GIS_CONFIG0_CH0_NUM_MASK                 0x38u
10819 #define GIS_CONFIG0_CH0_NUM_SHIFT                3
10820 #define GIS_CONFIG0_CH0_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH0_NUM_SHIFT))&GIS_CONFIG0_CH0_NUM_MASK)
10821 #define GIS_CONFIG0_CH1_MAPPING_MASK             0x700u
10822 #define GIS_CONFIG0_CH1_MAPPING_SHIFT            8
10823 #define GIS_CONFIG0_CH1_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH1_MAPPING_SHIFT))&GIS_CONFIG0_CH1_MAPPING_MASK)
10824 #define GIS_CONFIG0_CH1_NUM_MASK                 0x3800u
10825 #define GIS_CONFIG0_CH1_NUM_SHIFT                11
10826 #define GIS_CONFIG0_CH1_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH1_NUM_SHIFT))&GIS_CONFIG0_CH1_NUM_MASK)
10827 #define GIS_CONFIG0_CH2_MAPPING_MASK             0x70000u
10828 #define GIS_CONFIG0_CH2_MAPPING_SHIFT            16
10829 #define GIS_CONFIG0_CH2_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH2_MAPPING_SHIFT))&GIS_CONFIG0_CH2_MAPPING_MASK)
10830 #define GIS_CONFIG0_CH2_NUM_MASK                 0x380000u
10831 #define GIS_CONFIG0_CH2_NUM_SHIFT                19
10832 #define GIS_CONFIG0_CH2_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH2_NUM_SHIFT))&GIS_CONFIG0_CH2_NUM_MASK)
10833 #define GIS_CONFIG0_CH3_MAPPING_MASK             0x7000000u
10834 #define GIS_CONFIG0_CH3_MAPPING_SHIFT            24
10835 #define GIS_CONFIG0_CH3_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH3_MAPPING_SHIFT))&GIS_CONFIG0_CH3_MAPPING_MASK)
10836 #define GIS_CONFIG0_CH3_NUM_MASK                 0x38000000u
10837 #define GIS_CONFIG0_CH3_NUM_SHIFT                27
10838 #define GIS_CONFIG0_CH3_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH3_NUM_SHIFT))&GIS_CONFIG0_CH3_NUM_MASK)
10839 /* CONFIG0_SET Bit Fields */
10840 #define GIS_CONFIG0_SET_CH0_MAPPING_MASK         0x7u
10841 #define GIS_CONFIG0_SET_CH0_MAPPING_SHIFT        0
10842 #define GIS_CONFIG0_SET_CH0_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH0_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH0_MAPPING_MASK)
10843 #define GIS_CONFIG0_SET_CH0_NUM_MASK             0x38u
10844 #define GIS_CONFIG0_SET_CH0_NUM_SHIFT            3
10845 #define GIS_CONFIG0_SET_CH0_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH0_NUM_SHIFT))&GIS_CONFIG0_SET_CH0_NUM_MASK)
10846 #define GIS_CONFIG0_SET_CH1_MAPPING_MASK         0x700u
10847 #define GIS_CONFIG0_SET_CH1_MAPPING_SHIFT        8
10848 #define GIS_CONFIG0_SET_CH1_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH1_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH1_MAPPING_MASK)
10849 #define GIS_CONFIG0_SET_CH1_NUM_MASK             0x3800u
10850 #define GIS_CONFIG0_SET_CH1_NUM_SHIFT            11
10851 #define GIS_CONFIG0_SET_CH1_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH1_NUM_SHIFT))&GIS_CONFIG0_SET_CH1_NUM_MASK)
10852 #define GIS_CONFIG0_SET_CH2_MAPPING_MASK         0x70000u
10853 #define GIS_CONFIG0_SET_CH2_MAPPING_SHIFT        16
10854 #define GIS_CONFIG0_SET_CH2_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH2_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH2_MAPPING_MASK)
10855 #define GIS_CONFIG0_SET_CH2_NUM_MASK             0x380000u
10856 #define GIS_CONFIG0_SET_CH2_NUM_SHIFT            19
10857 #define GIS_CONFIG0_SET_CH2_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH2_NUM_SHIFT))&GIS_CONFIG0_SET_CH2_NUM_MASK)
10858 #define GIS_CONFIG0_SET_CH3_MAPPING_MASK         0x7000000u
10859 #define GIS_CONFIG0_SET_CH3_MAPPING_SHIFT        24
10860 #define GIS_CONFIG0_SET_CH3_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH3_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH3_MAPPING_MASK)
10861 #define GIS_CONFIG0_SET_CH3_NUM_MASK             0x38000000u
10862 #define GIS_CONFIG0_SET_CH3_NUM_SHIFT            27
10863 #define GIS_CONFIG0_SET_CH3_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH3_NUM_SHIFT))&GIS_CONFIG0_SET_CH3_NUM_MASK)
10864 /* CONFIG0_CLR Bit Fields */
10865 #define GIS_CONFIG0_CLR_CH0_MAPPING_MASK         0x7u
10866 #define GIS_CONFIG0_CLR_CH0_MAPPING_SHIFT        0
10867 #define GIS_CONFIG0_CLR_CH0_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH0_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH0_MAPPING_MASK)
10868 #define GIS_CONFIG0_CLR_CH0_NUM_MASK             0x38u
10869 #define GIS_CONFIG0_CLR_CH0_NUM_SHIFT            3
10870 #define GIS_CONFIG0_CLR_CH0_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH0_NUM_SHIFT))&GIS_CONFIG0_CLR_CH0_NUM_MASK)
10871 #define GIS_CONFIG0_CLR_CH1_MAPPING_MASK         0x700u
10872 #define GIS_CONFIG0_CLR_CH1_MAPPING_SHIFT        8
10873 #define GIS_CONFIG0_CLR_CH1_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH1_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH1_MAPPING_MASK)
10874 #define GIS_CONFIG0_CLR_CH1_NUM_MASK             0x3800u
10875 #define GIS_CONFIG0_CLR_CH1_NUM_SHIFT            11
10876 #define GIS_CONFIG0_CLR_CH1_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH1_NUM_SHIFT))&GIS_CONFIG0_CLR_CH1_NUM_MASK)
10877 #define GIS_CONFIG0_CLR_CH2_MAPPING_MASK         0x70000u
10878 #define GIS_CONFIG0_CLR_CH2_MAPPING_SHIFT        16
10879 #define GIS_CONFIG0_CLR_CH2_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH2_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH2_MAPPING_MASK)
10880 #define GIS_CONFIG0_CLR_CH2_NUM_MASK             0x380000u
10881 #define GIS_CONFIG0_CLR_CH2_NUM_SHIFT            19
10882 #define GIS_CONFIG0_CLR_CH2_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH2_NUM_SHIFT))&GIS_CONFIG0_CLR_CH2_NUM_MASK)
10883 #define GIS_CONFIG0_CLR_CH3_MAPPING_MASK         0x7000000u
10884 #define GIS_CONFIG0_CLR_CH3_MAPPING_SHIFT        24
10885 #define GIS_CONFIG0_CLR_CH3_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH3_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH3_MAPPING_MASK)
10886 #define GIS_CONFIG0_CLR_CH3_NUM_MASK             0x38000000u
10887 #define GIS_CONFIG0_CLR_CH3_NUM_SHIFT            27
10888 #define GIS_CONFIG0_CLR_CH3_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH3_NUM_SHIFT))&GIS_CONFIG0_CLR_CH3_NUM_MASK)
10889 /* CONFIG0_TOG Bit Fields */
10890 #define GIS_CONFIG0_TOG_CH0_MAPPING_MASK         0x7u
10891 #define GIS_CONFIG0_TOG_CH0_MAPPING_SHIFT        0
10892 #define GIS_CONFIG0_TOG_CH0_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH0_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH0_MAPPING_MASK)
10893 #define GIS_CONFIG0_TOG_CH0_NUM_MASK             0x38u
10894 #define GIS_CONFIG0_TOG_CH0_NUM_SHIFT            3
10895 #define GIS_CONFIG0_TOG_CH0_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH0_NUM_SHIFT))&GIS_CONFIG0_TOG_CH0_NUM_MASK)
10896 #define GIS_CONFIG0_TOG_CH1_MAPPING_MASK         0x700u
10897 #define GIS_CONFIG0_TOG_CH1_MAPPING_SHIFT        8
10898 #define GIS_CONFIG0_TOG_CH1_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH1_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH1_MAPPING_MASK)
10899 #define GIS_CONFIG0_TOG_CH1_NUM_MASK             0x3800u
10900 #define GIS_CONFIG0_TOG_CH1_NUM_SHIFT            11
10901 #define GIS_CONFIG0_TOG_CH1_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH1_NUM_SHIFT))&GIS_CONFIG0_TOG_CH1_NUM_MASK)
10902 #define GIS_CONFIG0_TOG_CH2_MAPPING_MASK         0x70000u
10903 #define GIS_CONFIG0_TOG_CH2_MAPPING_SHIFT        16
10904 #define GIS_CONFIG0_TOG_CH2_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH2_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH2_MAPPING_MASK)
10905 #define GIS_CONFIG0_TOG_CH2_NUM_MASK             0x380000u
10906 #define GIS_CONFIG0_TOG_CH2_NUM_SHIFT            19
10907 #define GIS_CONFIG0_TOG_CH2_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH2_NUM_SHIFT))&GIS_CONFIG0_TOG_CH2_NUM_MASK)
10908 #define GIS_CONFIG0_TOG_CH3_MAPPING_MASK         0x7000000u
10909 #define GIS_CONFIG0_TOG_CH3_MAPPING_SHIFT        24
10910 #define GIS_CONFIG0_TOG_CH3_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH3_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH3_MAPPING_MASK)
10911 #define GIS_CONFIG0_TOG_CH3_NUM_MASK             0x38000000u
10912 #define GIS_CONFIG0_TOG_CH3_NUM_SHIFT            27
10913 #define GIS_CONFIG0_TOG_CH3_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH3_NUM_SHIFT))&GIS_CONFIG0_TOG_CH3_NUM_MASK)
10914 /* CONFIG1 Bit Fields */
10915 #define GIS_CONFIG1_CH4_MAPPING_MASK             0x7u
10916 #define GIS_CONFIG1_CH4_MAPPING_SHIFT            0
10917 #define GIS_CONFIG1_CH4_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH4_MAPPING_SHIFT))&GIS_CONFIG1_CH4_MAPPING_MASK)
10918 #define GIS_CONFIG1_CH4_NUM_MASK                 0x38u
10919 #define GIS_CONFIG1_CH4_NUM_SHIFT                3
10920 #define GIS_CONFIG1_CH4_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH4_NUM_SHIFT))&GIS_CONFIG1_CH4_NUM_MASK)
10921 #define GIS_CONFIG1_CH5_MAPPING_MASK             0x700u
10922 #define GIS_CONFIG1_CH5_MAPPING_SHIFT            8
10923 #define GIS_CONFIG1_CH5_MAPPING(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH5_MAPPING_SHIFT))&GIS_CONFIG1_CH5_MAPPING_MASK)
10924 #define GIS_CONFIG1_CH5_NUM_MASK                 0x3800u
10925 #define GIS_CONFIG1_CH5_NUM_SHIFT                11
10926 #define GIS_CONFIG1_CH5_NUM(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH5_NUM_SHIFT))&GIS_CONFIG1_CH5_NUM_MASK)
10927 /* CONFIG1_SET Bit Fields */
10928 #define GIS_CONFIG1_SET_CH4_MAPPING_MASK         0x7u
10929 #define GIS_CONFIG1_SET_CH4_MAPPING_SHIFT        0
10930 #define GIS_CONFIG1_SET_CH4_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH4_MAPPING_SHIFT))&GIS_CONFIG1_SET_CH4_MAPPING_MASK)
10931 #define GIS_CONFIG1_SET_CH4_NUM_MASK             0x38u
10932 #define GIS_CONFIG1_SET_CH4_NUM_SHIFT            3
10933 #define GIS_CONFIG1_SET_CH4_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH4_NUM_SHIFT))&GIS_CONFIG1_SET_CH4_NUM_MASK)
10934 #define GIS_CONFIG1_SET_CH5_MAPPING_MASK         0x700u
10935 #define GIS_CONFIG1_SET_CH5_MAPPING_SHIFT        8
10936 #define GIS_CONFIG1_SET_CH5_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH5_MAPPING_SHIFT))&GIS_CONFIG1_SET_CH5_MAPPING_MASK)
10937 #define GIS_CONFIG1_SET_CH5_NUM_MASK             0x3800u
10938 #define GIS_CONFIG1_SET_CH5_NUM_SHIFT            11
10939 #define GIS_CONFIG1_SET_CH5_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH5_NUM_SHIFT))&GIS_CONFIG1_SET_CH5_NUM_MASK)
10940 /* CONFIG1_CLR Bit Fields */
10941 #define GIS_CONFIG1_CLR_CH4_MAPPING_MASK         0x7u
10942 #define GIS_CONFIG1_CLR_CH4_MAPPING_SHIFT        0
10943 #define GIS_CONFIG1_CLR_CH4_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH4_MAPPING_SHIFT))&GIS_CONFIG1_CLR_CH4_MAPPING_MASK)
10944 #define GIS_CONFIG1_CLR_CH4_NUM_MASK             0x38u
10945 #define GIS_CONFIG1_CLR_CH4_NUM_SHIFT            3
10946 #define GIS_CONFIG1_CLR_CH4_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH4_NUM_SHIFT))&GIS_CONFIG1_CLR_CH4_NUM_MASK)
10947 #define GIS_CONFIG1_CLR_CH5_MAPPING_MASK         0x700u
10948 #define GIS_CONFIG1_CLR_CH5_MAPPING_SHIFT        8
10949 #define GIS_CONFIG1_CLR_CH5_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH5_MAPPING_SHIFT))&GIS_CONFIG1_CLR_CH5_MAPPING_MASK)
10950 #define GIS_CONFIG1_CLR_CH5_NUM_MASK             0x3800u
10951 #define GIS_CONFIG1_CLR_CH5_NUM_SHIFT            11
10952 #define GIS_CONFIG1_CLR_CH5_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH5_NUM_SHIFT))&GIS_CONFIG1_CLR_CH5_NUM_MASK)
10953 /* CONFIG1_TOG Bit Fields */
10954 #define GIS_CONFIG1_TOG_CH4_MAPPING_MASK         0x7u
10955 #define GIS_CONFIG1_TOG_CH4_MAPPING_SHIFT        0
10956 #define GIS_CONFIG1_TOG_CH4_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH4_MAPPING_SHIFT))&GIS_CONFIG1_TOG_CH4_MAPPING_MASK)
10957 #define GIS_CONFIG1_TOG_CH4_NUM_MASK             0x38u
10958 #define GIS_CONFIG1_TOG_CH4_NUM_SHIFT            3
10959 #define GIS_CONFIG1_TOG_CH4_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH4_NUM_SHIFT))&GIS_CONFIG1_TOG_CH4_NUM_MASK)
10960 #define GIS_CONFIG1_TOG_CH5_MAPPING_MASK         0x700u
10961 #define GIS_CONFIG1_TOG_CH5_MAPPING_SHIFT        8
10962 #define GIS_CONFIG1_TOG_CH5_MAPPING(x)           (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH5_MAPPING_SHIFT))&GIS_CONFIG1_TOG_CH5_MAPPING_MASK)
10963 #define GIS_CONFIG1_TOG_CH5_NUM_MASK             0x3800u
10964 #define GIS_CONFIG1_TOG_CH5_NUM_SHIFT            11
10965 #define GIS_CONFIG1_TOG_CH5_NUM(x)               (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH5_NUM_SHIFT))&GIS_CONFIG1_TOG_CH5_NUM_MASK)
10966 /* FB0 Bit Fields */
10967 #define GIS_FB0_ADDR_MASK                        0xFFFFFFFFu
10968 #define GIS_FB0_ADDR_SHIFT                       0
10969 #define GIS_FB0_ADDR(x)                          (((uint32_t)(((uint32_t)(x))<<GIS_FB0_ADDR_SHIFT))&GIS_FB0_ADDR_MASK)
10970 /* FB1 Bit Fields */
10971 #define GIS_FB1_ADDR_MASK                        0xFFFFFFFFu
10972 #define GIS_FB1_ADDR_SHIFT                       0
10973 #define GIS_FB1_ADDR(x)                          (((uint32_t)(((uint32_t)(x))<<GIS_FB1_ADDR_SHIFT))&GIS_FB1_ADDR_MASK)
10974 /* PXP_FB0 Bit Fields */
10975 #define GIS_PXP_FB0_ADDR_MASK                    0xFFFFFFFFu
10976 #define GIS_PXP_FB0_ADDR_SHIFT                   0
10977 #define GIS_PXP_FB0_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<GIS_PXP_FB0_ADDR_SHIFT))&GIS_PXP_FB0_ADDR_MASK)
10978 /* PXP_FB1 Bit Fields */
10979 #define GIS_PXP_FB1_ADDR_MASK                    0xFFFFFFFFu
10980 #define GIS_PXP_FB1_ADDR_SHIFT                   0
10981 #define GIS_PXP_FB1_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<GIS_PXP_FB1_ADDR_SHIFT))&GIS_PXP_FB1_ADDR_MASK)
10982 /* CH0_CTRL Bit Fields */
10983 #define GIS_CH0_CTRL_CMD0_OPCODE_MASK            0xFu
10984 #define GIS_CH0_CTRL_CMD0_OPCODE_SHIFT           0
10985 #define GIS_CH0_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD0_OPCODE_MASK)
10986 #define GIS_CH0_CTRL_CMD0_ALU_MASK               0x70u
10987 #define GIS_CH0_CTRL_CMD0_ALU_SHIFT              4
10988 #define GIS_CH0_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_CMD0_ALU_MASK)
10989 #define GIS_CH0_CTRL_CMD0_ACC_NEG_MASK           0x80u
10990 #define GIS_CH0_CTRL_CMD0_ACC_NEG_SHIFT          7
10991 #define GIS_CH0_CTRL_CMD1_OPCODE_MASK            0xF00u
10992 #define GIS_CH0_CTRL_CMD1_OPCODE_SHIFT           8
10993 #define GIS_CH0_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD1_OPCODE_MASK)
10994 #define GIS_CH0_CTRL_CMD1_ALU_MASK               0x7000u
10995 #define GIS_CH0_CTRL_CMD1_ALU_SHIFT              12
10996 #define GIS_CH0_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_CMD1_ALU_MASK)
10997 #define GIS_CH0_CTRL_CMD1_ACC_NEG_MASK           0x8000u
10998 #define GIS_CH0_CTRL_CMD1_ACC_NEG_SHIFT          15
10999 #define GIS_CH0_CTRL_CMD2_OPCODE_MASK            0xF0000u
11000 #define GIS_CH0_CTRL_CMD2_OPCODE_SHIFT           16
11001 #define GIS_CH0_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD2_OPCODE_MASK)
11002 #define GIS_CH0_CTRL_CMD2_ALU_MASK               0x700000u
11003 #define GIS_CH0_CTRL_CMD2_ALU_SHIFT              20
11004 #define GIS_CH0_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_CMD2_ALU_MASK)
11005 #define GIS_CH0_CTRL_CMD2_ACC_NEG_MASK           0x800000u
11006 #define GIS_CH0_CTRL_CMD2_ACC_NEG_SHIFT          23
11007 #define GIS_CH0_CTRL_CMD3_OPCODE_MASK            0xF000000u
11008 #define GIS_CH0_CTRL_CMD3_OPCODE_SHIFT           24
11009 #define GIS_CH0_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD3_OPCODE_MASK)
11010 #define GIS_CH0_CTRL_CMD3_ALU_MASK               0x70000000u
11011 #define GIS_CH0_CTRL_CMD3_ALU_SHIFT              28
11012 #define GIS_CH0_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_CMD3_ALU_MASK)
11013 #define GIS_CH0_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
11014 #define GIS_CH0_CTRL_CMD3_ACC_NEG_SHIFT          31
11015 /* CH0_CTRL_SET Bit Fields */
11016 #define GIS_CH0_CTRL_SET_CMD0_OPCODE_MASK        0xFu
11017 #define GIS_CH0_CTRL_SET_CMD0_OPCODE_SHIFT       0
11018 #define GIS_CH0_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD0_OPCODE_MASK)
11019 #define GIS_CH0_CTRL_SET_CMD0_ALU_MASK           0x70u
11020 #define GIS_CH0_CTRL_SET_CMD0_ALU_SHIFT          4
11021 #define GIS_CH0_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD0_ALU_MASK)
11022 #define GIS_CH0_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
11023 #define GIS_CH0_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
11024 #define GIS_CH0_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
11025 #define GIS_CH0_CTRL_SET_CMD1_OPCODE_SHIFT       8
11026 #define GIS_CH0_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD1_OPCODE_MASK)
11027 #define GIS_CH0_CTRL_SET_CMD1_ALU_MASK           0x7000u
11028 #define GIS_CH0_CTRL_SET_CMD1_ALU_SHIFT          12
11029 #define GIS_CH0_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD1_ALU_MASK)
11030 #define GIS_CH0_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
11031 #define GIS_CH0_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
11032 #define GIS_CH0_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
11033 #define GIS_CH0_CTRL_SET_CMD2_OPCODE_SHIFT       16
11034 #define GIS_CH0_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD2_OPCODE_MASK)
11035 #define GIS_CH0_CTRL_SET_CMD2_ALU_MASK           0x700000u
11036 #define GIS_CH0_CTRL_SET_CMD2_ALU_SHIFT          20
11037 #define GIS_CH0_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD2_ALU_MASK)
11038 #define GIS_CH0_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
11039 #define GIS_CH0_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
11040 #define GIS_CH0_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
11041 #define GIS_CH0_CTRL_SET_CMD3_OPCODE_SHIFT       24
11042 #define GIS_CH0_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD3_OPCODE_MASK)
11043 #define GIS_CH0_CTRL_SET_CMD3_ALU_MASK           0x70000000u
11044 #define GIS_CH0_CTRL_SET_CMD3_ALU_SHIFT          28
11045 #define GIS_CH0_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD3_ALU_MASK)
11046 #define GIS_CH0_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
11047 #define GIS_CH0_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
11048 /* CH0_CTRL_CLR Bit Fields */
11049 #define GIS_CH0_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
11050 #define GIS_CH0_CTRL_CLR_CMD0_OPCODE_SHIFT       0
11051 #define GIS_CH0_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD0_OPCODE_MASK)
11052 #define GIS_CH0_CTRL_CLR_CMD0_ALU_MASK           0x70u
11053 #define GIS_CH0_CTRL_CLR_CMD0_ALU_SHIFT          4
11054 #define GIS_CH0_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD0_ALU_MASK)
11055 #define GIS_CH0_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
11056 #define GIS_CH0_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
11057 #define GIS_CH0_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
11058 #define GIS_CH0_CTRL_CLR_CMD1_OPCODE_SHIFT       8
11059 #define GIS_CH0_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD1_OPCODE_MASK)
11060 #define GIS_CH0_CTRL_CLR_CMD1_ALU_MASK           0x7000u
11061 #define GIS_CH0_CTRL_CLR_CMD1_ALU_SHIFT          12
11062 #define GIS_CH0_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD1_ALU_MASK)
11063 #define GIS_CH0_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
11064 #define GIS_CH0_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
11065 #define GIS_CH0_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
11066 #define GIS_CH0_CTRL_CLR_CMD2_OPCODE_SHIFT       16
11067 #define GIS_CH0_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD2_OPCODE_MASK)
11068 #define GIS_CH0_CTRL_CLR_CMD2_ALU_MASK           0x700000u
11069 #define GIS_CH0_CTRL_CLR_CMD2_ALU_SHIFT          20
11070 #define GIS_CH0_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD2_ALU_MASK)
11071 #define GIS_CH0_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
11072 #define GIS_CH0_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
11073 #define GIS_CH0_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
11074 #define GIS_CH0_CTRL_CLR_CMD3_OPCODE_SHIFT       24
11075 #define GIS_CH0_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD3_OPCODE_MASK)
11076 #define GIS_CH0_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
11077 #define GIS_CH0_CTRL_CLR_CMD3_ALU_SHIFT          28
11078 #define GIS_CH0_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD3_ALU_MASK)
11079 #define GIS_CH0_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
11080 #define GIS_CH0_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
11081 /* CH0_CTRL_TOG Bit Fields */
11082 #define GIS_CH0_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
11083 #define GIS_CH0_CTRL_TOG_CMD0_OPCODE_SHIFT       0
11084 #define GIS_CH0_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD0_OPCODE_MASK)
11085 #define GIS_CH0_CTRL_TOG_CMD0_ALU_MASK           0x70u
11086 #define GIS_CH0_CTRL_TOG_CMD0_ALU_SHIFT          4
11087 #define GIS_CH0_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD0_ALU_MASK)
11088 #define GIS_CH0_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
11089 #define GIS_CH0_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
11090 #define GIS_CH0_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
11091 #define GIS_CH0_CTRL_TOG_CMD1_OPCODE_SHIFT       8
11092 #define GIS_CH0_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD1_OPCODE_MASK)
11093 #define GIS_CH0_CTRL_TOG_CMD1_ALU_MASK           0x7000u
11094 #define GIS_CH0_CTRL_TOG_CMD1_ALU_SHIFT          12
11095 #define GIS_CH0_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD1_ALU_MASK)
11096 #define GIS_CH0_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
11097 #define GIS_CH0_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
11098 #define GIS_CH0_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
11099 #define GIS_CH0_CTRL_TOG_CMD2_OPCODE_SHIFT       16
11100 #define GIS_CH0_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD2_OPCODE_MASK)
11101 #define GIS_CH0_CTRL_TOG_CMD2_ALU_MASK           0x700000u
11102 #define GIS_CH0_CTRL_TOG_CMD2_ALU_SHIFT          20
11103 #define GIS_CH0_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD2_ALU_MASK)
11104 #define GIS_CH0_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
11105 #define GIS_CH0_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
11106 #define GIS_CH0_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
11107 #define GIS_CH0_CTRL_TOG_CMD3_OPCODE_SHIFT       24
11108 #define GIS_CH0_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD3_OPCODE_MASK)
11109 #define GIS_CH0_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
11110 #define GIS_CH0_CTRL_TOG_CMD3_ALU_SHIFT          28
11111 #define GIS_CH0_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD3_ALU_MASK)
11112 #define GIS_CH0_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
11113 #define GIS_CH0_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
11114 /* CH0_ADDR0 Bit Fields */
11115 #define GIS_CH0_ADDR0_ADDR_MASK                  0x7FFFFFFu
11116 #define GIS_CH0_ADDR0_ADDR_SHIFT                 0
11117 #define GIS_CH0_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_ADDR_SHIFT))&GIS_CH0_ADDR0_ADDR_MASK)
11118 #define GIS_CH0_ADDR0_CSI0_SEL_MASK              0x8000000u
11119 #define GIS_CH0_ADDR0_CSI0_SEL_SHIFT             27
11120 #define GIS_CH0_ADDR0_CSI1_SEL_MASK              0x10000000u
11121 #define GIS_CH0_ADDR0_CSI1_SEL_SHIFT             28
11122 #define GIS_CH0_ADDR0_PXP_SEL_MASK               0x20000000u
11123 #define GIS_CH0_ADDR0_PXP_SEL_SHIFT              29
11124 #define GIS_CH0_ADDR0_LCDIF0_SEL_MASK            0x40000000u
11125 #define GIS_CH0_ADDR0_LCDIF0_SEL_SHIFT           30
11126 #define GIS_CH0_ADDR0_LCDIF1_SEL_MASK            0x80000000u
11127 #define GIS_CH0_ADDR0_LCDIF1_SEL_SHIFT           31
11128 /* CH0_ADDR0_SET Bit Fields */
11129 #define GIS_CH0_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
11130 #define GIS_CH0_ADDR0_SET_ADDR_SHIFT             0
11131 #define GIS_CH0_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_SET_ADDR_SHIFT))&GIS_CH0_ADDR0_SET_ADDR_MASK)
11132 #define GIS_CH0_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
11133 #define GIS_CH0_ADDR0_SET_CSI0_SEL_SHIFT         27
11134 #define GIS_CH0_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
11135 #define GIS_CH0_ADDR0_SET_CSI1_SEL_SHIFT         28
11136 #define GIS_CH0_ADDR0_SET_PXP_SEL_MASK           0x20000000u
11137 #define GIS_CH0_ADDR0_SET_PXP_SEL_SHIFT          29
11138 #define GIS_CH0_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
11139 #define GIS_CH0_ADDR0_SET_LCDIF0_SEL_SHIFT       30
11140 #define GIS_CH0_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
11141 #define GIS_CH0_ADDR0_SET_LCDIF1_SEL_SHIFT       31
11142 /* CH0_ADDR0_CLR Bit Fields */
11143 #define GIS_CH0_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
11144 #define GIS_CH0_ADDR0_CLR_ADDR_SHIFT             0
11145 #define GIS_CH0_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_CLR_ADDR_SHIFT))&GIS_CH0_ADDR0_CLR_ADDR_MASK)
11146 #define GIS_CH0_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
11147 #define GIS_CH0_ADDR0_CLR_CSI0_SEL_SHIFT         27
11148 #define GIS_CH0_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
11149 #define GIS_CH0_ADDR0_CLR_CSI1_SEL_SHIFT         28
11150 #define GIS_CH0_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
11151 #define GIS_CH0_ADDR0_CLR_PXP_SEL_SHIFT          29
11152 #define GIS_CH0_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
11153 #define GIS_CH0_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
11154 #define GIS_CH0_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
11155 #define GIS_CH0_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
11156 /* CH0_ADDR0_TOG Bit Fields */
11157 #define GIS_CH0_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
11158 #define GIS_CH0_ADDR0_TOG_ADDR_SHIFT             0
11159 #define GIS_CH0_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_TOG_ADDR_SHIFT))&GIS_CH0_ADDR0_TOG_ADDR_MASK)
11160 #define GIS_CH0_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
11161 #define GIS_CH0_ADDR0_TOG_CSI0_SEL_SHIFT         27
11162 #define GIS_CH0_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
11163 #define GIS_CH0_ADDR0_TOG_CSI1_SEL_SHIFT         28
11164 #define GIS_CH0_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
11165 #define GIS_CH0_ADDR0_TOG_PXP_SEL_SHIFT          29
11166 #define GIS_CH0_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
11167 #define GIS_CH0_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
11168 #define GIS_CH0_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
11169 #define GIS_CH0_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
11170 /* CH0_DATA0 Bit Fields */
11171 #define GIS_CH0_DATA0_DATA_MASK                  0xFFFFFFFFu
11172 #define GIS_CH0_DATA0_DATA_SHIFT                 0
11173 #define GIS_CH0_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA0_DATA_SHIFT))&GIS_CH0_DATA0_DATA_MASK)
11174 /* CH0_ADDR1 Bit Fields */
11175 #define GIS_CH0_ADDR1_ADDR_MASK                  0x7FFFFFFu
11176 #define GIS_CH0_ADDR1_ADDR_SHIFT                 0
11177 #define GIS_CH0_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_ADDR_SHIFT))&GIS_CH0_ADDR1_ADDR_MASK)
11178 #define GIS_CH0_ADDR1_CSI0_SEL_MASK              0x8000000u
11179 #define GIS_CH0_ADDR1_CSI0_SEL_SHIFT             27
11180 #define GIS_CH0_ADDR1_CSI1_SEL_MASK              0x10000000u
11181 #define GIS_CH0_ADDR1_CSI1_SEL_SHIFT             28
11182 #define GIS_CH0_ADDR1_PXP_SEL_MASK               0x20000000u
11183 #define GIS_CH0_ADDR1_PXP_SEL_SHIFT              29
11184 #define GIS_CH0_ADDR1_LCDIF0_SEL_MASK            0x40000000u
11185 #define GIS_CH0_ADDR1_LCDIF0_SEL_SHIFT           30
11186 #define GIS_CH0_ADDR1_LCDIF1_SEL_MASK            0x80000000u
11187 #define GIS_CH0_ADDR1_LCDIF1_SEL_SHIFT           31
11188 /* CH0_ADDR1_SET Bit Fields */
11189 #define GIS_CH0_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
11190 #define GIS_CH0_ADDR1_SET_ADDR_SHIFT             0
11191 #define GIS_CH0_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_SET_ADDR_SHIFT))&GIS_CH0_ADDR1_SET_ADDR_MASK)
11192 #define GIS_CH0_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
11193 #define GIS_CH0_ADDR1_SET_CSI0_SEL_SHIFT         27
11194 #define GIS_CH0_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
11195 #define GIS_CH0_ADDR1_SET_CSI1_SEL_SHIFT         28
11196 #define GIS_CH0_ADDR1_SET_PXP_SEL_MASK           0x20000000u
11197 #define GIS_CH0_ADDR1_SET_PXP_SEL_SHIFT          29
11198 #define GIS_CH0_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
11199 #define GIS_CH0_ADDR1_SET_LCDIF0_SEL_SHIFT       30
11200 #define GIS_CH0_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
11201 #define GIS_CH0_ADDR1_SET_LCDIF1_SEL_SHIFT       31
11202 /* CH0_ADDR1_CLR Bit Fields */
11203 #define GIS_CH0_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
11204 #define GIS_CH0_ADDR1_CLR_ADDR_SHIFT             0
11205 #define GIS_CH0_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_CLR_ADDR_SHIFT))&GIS_CH0_ADDR1_CLR_ADDR_MASK)
11206 #define GIS_CH0_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
11207 #define GIS_CH0_ADDR1_CLR_CSI0_SEL_SHIFT         27
11208 #define GIS_CH0_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
11209 #define GIS_CH0_ADDR1_CLR_CSI1_SEL_SHIFT         28
11210 #define GIS_CH0_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
11211 #define GIS_CH0_ADDR1_CLR_PXP_SEL_SHIFT          29
11212 #define GIS_CH0_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
11213 #define GIS_CH0_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
11214 #define GIS_CH0_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
11215 #define GIS_CH0_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
11216 /* CH0_ADDR1_TOG Bit Fields */
11217 #define GIS_CH0_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
11218 #define GIS_CH0_ADDR1_TOG_ADDR_SHIFT             0
11219 #define GIS_CH0_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_TOG_ADDR_SHIFT))&GIS_CH0_ADDR1_TOG_ADDR_MASK)
11220 #define GIS_CH0_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
11221 #define GIS_CH0_ADDR1_TOG_CSI0_SEL_SHIFT         27
11222 #define GIS_CH0_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
11223 #define GIS_CH0_ADDR1_TOG_CSI1_SEL_SHIFT         28
11224 #define GIS_CH0_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
11225 #define GIS_CH0_ADDR1_TOG_PXP_SEL_SHIFT          29
11226 #define GIS_CH0_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
11227 #define GIS_CH0_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
11228 #define GIS_CH0_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
11229 #define GIS_CH0_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
11230 /* CH0_DATA1 Bit Fields */
11231 #define GIS_CH0_DATA1_DATA_MASK                  0xFFFFFFFFu
11232 #define GIS_CH0_DATA1_DATA_SHIFT                 0
11233 #define GIS_CH0_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA1_DATA_SHIFT))&GIS_CH0_DATA1_DATA_MASK)
11234 /* CH0_ADDR2 Bit Fields */
11235 #define GIS_CH0_ADDR2_ADDR_MASK                  0x7FFFFFFu
11236 #define GIS_CH0_ADDR2_ADDR_SHIFT                 0
11237 #define GIS_CH0_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_ADDR_SHIFT))&GIS_CH0_ADDR2_ADDR_MASK)
11238 #define GIS_CH0_ADDR2_CSI0_SEL_MASK              0x8000000u
11239 #define GIS_CH0_ADDR2_CSI0_SEL_SHIFT             27
11240 #define GIS_CH0_ADDR2_CSI1_SEL_MASK              0x10000000u
11241 #define GIS_CH0_ADDR2_CSI1_SEL_SHIFT             28
11242 #define GIS_CH0_ADDR2_PXP_SEL_MASK               0x20000000u
11243 #define GIS_CH0_ADDR2_PXP_SEL_SHIFT              29
11244 #define GIS_CH0_ADDR2_LCDIF0_SEL_MASK            0x40000000u
11245 #define GIS_CH0_ADDR2_LCDIF0_SEL_SHIFT           30
11246 #define GIS_CH0_ADDR2_LCDIF1_SEL_MASK            0x80000000u
11247 #define GIS_CH0_ADDR2_LCDIF1_SEL_SHIFT           31
11248 /* CH0_ADDR2_SET Bit Fields */
11249 #define GIS_CH0_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
11250 #define GIS_CH0_ADDR2_SET_ADDR_SHIFT             0
11251 #define GIS_CH0_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_SET_ADDR_SHIFT))&GIS_CH0_ADDR2_SET_ADDR_MASK)
11252 #define GIS_CH0_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
11253 #define GIS_CH0_ADDR2_SET_CSI0_SEL_SHIFT         27
11254 #define GIS_CH0_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
11255 #define GIS_CH0_ADDR2_SET_CSI1_SEL_SHIFT         28
11256 #define GIS_CH0_ADDR2_SET_PXP_SEL_MASK           0x20000000u
11257 #define GIS_CH0_ADDR2_SET_PXP_SEL_SHIFT          29
11258 #define GIS_CH0_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
11259 #define GIS_CH0_ADDR2_SET_LCDIF0_SEL_SHIFT       30
11260 #define GIS_CH0_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
11261 #define GIS_CH0_ADDR2_SET_LCDIF1_SEL_SHIFT       31
11262 /* CH0_ADDR2_CLR Bit Fields */
11263 #define GIS_CH0_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
11264 #define GIS_CH0_ADDR2_CLR_ADDR_SHIFT             0
11265 #define GIS_CH0_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_CLR_ADDR_SHIFT))&GIS_CH0_ADDR2_CLR_ADDR_MASK)
11266 #define GIS_CH0_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
11267 #define GIS_CH0_ADDR2_CLR_CSI0_SEL_SHIFT         27
11268 #define GIS_CH0_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
11269 #define GIS_CH0_ADDR2_CLR_CSI1_SEL_SHIFT         28
11270 #define GIS_CH0_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
11271 #define GIS_CH0_ADDR2_CLR_PXP_SEL_SHIFT          29
11272 #define GIS_CH0_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
11273 #define GIS_CH0_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
11274 #define GIS_CH0_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
11275 #define GIS_CH0_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
11276 /* CH0_ADDR2_TOG Bit Fields */
11277 #define GIS_CH0_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
11278 #define GIS_CH0_ADDR2_TOG_ADDR_SHIFT             0
11279 #define GIS_CH0_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_TOG_ADDR_SHIFT))&GIS_CH0_ADDR2_TOG_ADDR_MASK)
11280 #define GIS_CH0_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
11281 #define GIS_CH0_ADDR2_TOG_CSI0_SEL_SHIFT         27
11282 #define GIS_CH0_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
11283 #define GIS_CH0_ADDR2_TOG_CSI1_SEL_SHIFT         28
11284 #define GIS_CH0_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
11285 #define GIS_CH0_ADDR2_TOG_PXP_SEL_SHIFT          29
11286 #define GIS_CH0_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
11287 #define GIS_CH0_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
11288 #define GIS_CH0_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
11289 #define GIS_CH0_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
11290 /* CH0_DATA2 Bit Fields */
11291 #define GIS_CH0_DATA2_DATA_MASK                  0xFFFFFFFFu
11292 #define GIS_CH0_DATA2_DATA_SHIFT                 0
11293 #define GIS_CH0_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA2_DATA_SHIFT))&GIS_CH0_DATA2_DATA_MASK)
11294 /* CH0_ADDR3 Bit Fields */
11295 #define GIS_CH0_ADDR3_ADDR_MASK                  0x7FFFFFFu
11296 #define GIS_CH0_ADDR3_ADDR_SHIFT                 0
11297 #define GIS_CH0_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_ADDR_SHIFT))&GIS_CH0_ADDR3_ADDR_MASK)
11298 #define GIS_CH0_ADDR3_CSI0_SEL_MASK              0x8000000u
11299 #define GIS_CH0_ADDR3_CSI0_SEL_SHIFT             27
11300 #define GIS_CH0_ADDR3_CSI1_SEL_MASK              0x10000000u
11301 #define GIS_CH0_ADDR3_CSI1_SEL_SHIFT             28
11302 #define GIS_CH0_ADDR3_PXP_SEL_MASK               0x20000000u
11303 #define GIS_CH0_ADDR3_PXP_SEL_SHIFT              29
11304 #define GIS_CH0_ADDR3_LCDIF0_SEL_MASK            0x40000000u
11305 #define GIS_CH0_ADDR3_LCDIF0_SEL_SHIFT           30
11306 #define GIS_CH0_ADDR3_LCDIF1_SEL_MASK            0x80000000u
11307 #define GIS_CH0_ADDR3_LCDIF1_SEL_SHIFT           31
11308 /* CH0_ADDR3_SET Bit Fields */
11309 #define GIS_CH0_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
11310 #define GIS_CH0_ADDR3_SET_ADDR_SHIFT             0
11311 #define GIS_CH0_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_SET_ADDR_SHIFT))&GIS_CH0_ADDR3_SET_ADDR_MASK)
11312 #define GIS_CH0_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
11313 #define GIS_CH0_ADDR3_SET_CSI0_SEL_SHIFT         27
11314 #define GIS_CH0_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
11315 #define GIS_CH0_ADDR3_SET_CSI1_SEL_SHIFT         28
11316 #define GIS_CH0_ADDR3_SET_PXP_SEL_MASK           0x20000000u
11317 #define GIS_CH0_ADDR3_SET_PXP_SEL_SHIFT          29
11318 #define GIS_CH0_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
11319 #define GIS_CH0_ADDR3_SET_LCDIF0_SEL_SHIFT       30
11320 #define GIS_CH0_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
11321 #define GIS_CH0_ADDR3_SET_LCDIF1_SEL_SHIFT       31
11322 /* CH0_ADDR3_CLR Bit Fields */
11323 #define GIS_CH0_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
11324 #define GIS_CH0_ADDR3_CLR_ADDR_SHIFT             0
11325 #define GIS_CH0_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_CLR_ADDR_SHIFT))&GIS_CH0_ADDR3_CLR_ADDR_MASK)
11326 #define GIS_CH0_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
11327 #define GIS_CH0_ADDR3_CLR_CSI0_SEL_SHIFT         27
11328 #define GIS_CH0_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
11329 #define GIS_CH0_ADDR3_CLR_CSI1_SEL_SHIFT         28
11330 #define GIS_CH0_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
11331 #define GIS_CH0_ADDR3_CLR_PXP_SEL_SHIFT          29
11332 #define GIS_CH0_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
11333 #define GIS_CH0_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
11334 #define GIS_CH0_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
11335 #define GIS_CH0_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
11336 /* CH0_ADDR3_TOG Bit Fields */
11337 #define GIS_CH0_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
11338 #define GIS_CH0_ADDR3_TOG_ADDR_SHIFT             0
11339 #define GIS_CH0_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_TOG_ADDR_SHIFT))&GIS_CH0_ADDR3_TOG_ADDR_MASK)
11340 #define GIS_CH0_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
11341 #define GIS_CH0_ADDR3_TOG_CSI0_SEL_SHIFT         27
11342 #define GIS_CH0_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
11343 #define GIS_CH0_ADDR3_TOG_CSI1_SEL_SHIFT         28
11344 #define GIS_CH0_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
11345 #define GIS_CH0_ADDR3_TOG_PXP_SEL_SHIFT          29
11346 #define GIS_CH0_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
11347 #define GIS_CH0_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
11348 #define GIS_CH0_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
11349 #define GIS_CH0_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
11350 /* CH0_DATA3 Bit Fields */
11351 #define GIS_CH0_DATA3_DATA_MASK                  0xFFFFFFFFu
11352 #define GIS_CH0_DATA3_DATA_SHIFT                 0
11353 #define GIS_CH0_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA3_DATA_SHIFT))&GIS_CH0_DATA3_DATA_MASK)
11354 /* CH1_CTRL Bit Fields */
11355 #define GIS_CH1_CTRL_CMD0_OPCODE_MASK            0xFu
11356 #define GIS_CH1_CTRL_CMD0_OPCODE_SHIFT           0
11357 #define GIS_CH1_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD0_OPCODE_MASK)
11358 #define GIS_CH1_CTRL_CMD0_ALU_MASK               0x70u
11359 #define GIS_CH1_CTRL_CMD0_ALU_SHIFT              4
11360 #define GIS_CH1_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_CMD0_ALU_MASK)
11361 #define GIS_CH1_CTRL_CMD0_ACC_NEG_MASK           0x80u
11362 #define GIS_CH1_CTRL_CMD0_ACC_NEG_SHIFT          7
11363 #define GIS_CH1_CTRL_CMD1_OPCODE_MASK            0xF00u
11364 #define GIS_CH1_CTRL_CMD1_OPCODE_SHIFT           8
11365 #define GIS_CH1_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD1_OPCODE_MASK)
11366 #define GIS_CH1_CTRL_CMD1_ALU_MASK               0x7000u
11367 #define GIS_CH1_CTRL_CMD1_ALU_SHIFT              12
11368 #define GIS_CH1_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_CMD1_ALU_MASK)
11369 #define GIS_CH1_CTRL_CMD1_ACC_NEG_MASK           0x8000u
11370 #define GIS_CH1_CTRL_CMD1_ACC_NEG_SHIFT          15
11371 #define GIS_CH1_CTRL_CMD2_OPCODE_MASK            0xF0000u
11372 #define GIS_CH1_CTRL_CMD2_OPCODE_SHIFT           16
11373 #define GIS_CH1_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD2_OPCODE_MASK)
11374 #define GIS_CH1_CTRL_CMD2_ALU_MASK               0x700000u
11375 #define GIS_CH1_CTRL_CMD2_ALU_SHIFT              20
11376 #define GIS_CH1_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_CMD2_ALU_MASK)
11377 #define GIS_CH1_CTRL_CMD2_ACC_NEG_MASK           0x800000u
11378 #define GIS_CH1_CTRL_CMD2_ACC_NEG_SHIFT          23
11379 #define GIS_CH1_CTRL_CMD3_OPCODE_MASK            0xF000000u
11380 #define GIS_CH1_CTRL_CMD3_OPCODE_SHIFT           24
11381 #define GIS_CH1_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD3_OPCODE_MASK)
11382 #define GIS_CH1_CTRL_CMD3_ALU_MASK               0x70000000u
11383 #define GIS_CH1_CTRL_CMD3_ALU_SHIFT              28
11384 #define GIS_CH1_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_CMD3_ALU_MASK)
11385 #define GIS_CH1_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
11386 #define GIS_CH1_CTRL_CMD3_ACC_NEG_SHIFT          31
11387 /* CH1_CTRL_SET Bit Fields */
11388 #define GIS_CH1_CTRL_SET_CMD0_OPCODE_MASK        0xFu
11389 #define GIS_CH1_CTRL_SET_CMD0_OPCODE_SHIFT       0
11390 #define GIS_CH1_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD0_OPCODE_MASK)
11391 #define GIS_CH1_CTRL_SET_CMD0_ALU_MASK           0x70u
11392 #define GIS_CH1_CTRL_SET_CMD0_ALU_SHIFT          4
11393 #define GIS_CH1_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD0_ALU_MASK)
11394 #define GIS_CH1_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
11395 #define GIS_CH1_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
11396 #define GIS_CH1_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
11397 #define GIS_CH1_CTRL_SET_CMD1_OPCODE_SHIFT       8
11398 #define GIS_CH1_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD1_OPCODE_MASK)
11399 #define GIS_CH1_CTRL_SET_CMD1_ALU_MASK           0x7000u
11400 #define GIS_CH1_CTRL_SET_CMD1_ALU_SHIFT          12
11401 #define GIS_CH1_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD1_ALU_MASK)
11402 #define GIS_CH1_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
11403 #define GIS_CH1_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
11404 #define GIS_CH1_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
11405 #define GIS_CH1_CTRL_SET_CMD2_OPCODE_SHIFT       16
11406 #define GIS_CH1_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD2_OPCODE_MASK)
11407 #define GIS_CH1_CTRL_SET_CMD2_ALU_MASK           0x700000u
11408 #define GIS_CH1_CTRL_SET_CMD2_ALU_SHIFT          20
11409 #define GIS_CH1_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD2_ALU_MASK)
11410 #define GIS_CH1_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
11411 #define GIS_CH1_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
11412 #define GIS_CH1_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
11413 #define GIS_CH1_CTRL_SET_CMD3_OPCODE_SHIFT       24
11414 #define GIS_CH1_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD3_OPCODE_MASK)
11415 #define GIS_CH1_CTRL_SET_CMD3_ALU_MASK           0x70000000u
11416 #define GIS_CH1_CTRL_SET_CMD3_ALU_SHIFT          28
11417 #define GIS_CH1_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD3_ALU_MASK)
11418 #define GIS_CH1_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
11419 #define GIS_CH1_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
11420 /* CH1_CTRL_CLR Bit Fields */
11421 #define GIS_CH1_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
11422 #define GIS_CH1_CTRL_CLR_CMD0_OPCODE_SHIFT       0
11423 #define GIS_CH1_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD0_OPCODE_MASK)
11424 #define GIS_CH1_CTRL_CLR_CMD0_ALU_MASK           0x70u
11425 #define GIS_CH1_CTRL_CLR_CMD0_ALU_SHIFT          4
11426 #define GIS_CH1_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD0_ALU_MASK)
11427 #define GIS_CH1_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
11428 #define GIS_CH1_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
11429 #define GIS_CH1_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
11430 #define GIS_CH1_CTRL_CLR_CMD1_OPCODE_SHIFT       8
11431 #define GIS_CH1_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD1_OPCODE_MASK)
11432 #define GIS_CH1_CTRL_CLR_CMD1_ALU_MASK           0x7000u
11433 #define GIS_CH1_CTRL_CLR_CMD1_ALU_SHIFT          12
11434 #define GIS_CH1_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD1_ALU_MASK)
11435 #define GIS_CH1_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
11436 #define GIS_CH1_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
11437 #define GIS_CH1_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
11438 #define GIS_CH1_CTRL_CLR_CMD2_OPCODE_SHIFT       16
11439 #define GIS_CH1_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD2_OPCODE_MASK)
11440 #define GIS_CH1_CTRL_CLR_CMD2_ALU_MASK           0x700000u
11441 #define GIS_CH1_CTRL_CLR_CMD2_ALU_SHIFT          20
11442 #define GIS_CH1_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD2_ALU_MASK)
11443 #define GIS_CH1_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
11444 #define GIS_CH1_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
11445 #define GIS_CH1_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
11446 #define GIS_CH1_CTRL_CLR_CMD3_OPCODE_SHIFT       24
11447 #define GIS_CH1_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD3_OPCODE_MASK)
11448 #define GIS_CH1_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
11449 #define GIS_CH1_CTRL_CLR_CMD3_ALU_SHIFT          28
11450 #define GIS_CH1_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD3_ALU_MASK)
11451 #define GIS_CH1_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
11452 #define GIS_CH1_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
11453 /* CH1_CTRL_TOG Bit Fields */
11454 #define GIS_CH1_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
11455 #define GIS_CH1_CTRL_TOG_CMD0_OPCODE_SHIFT       0
11456 #define GIS_CH1_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD0_OPCODE_MASK)
11457 #define GIS_CH1_CTRL_TOG_CMD0_ALU_MASK           0x70u
11458 #define GIS_CH1_CTRL_TOG_CMD0_ALU_SHIFT          4
11459 #define GIS_CH1_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD0_ALU_MASK)
11460 #define GIS_CH1_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
11461 #define GIS_CH1_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
11462 #define GIS_CH1_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
11463 #define GIS_CH1_CTRL_TOG_CMD1_OPCODE_SHIFT       8
11464 #define GIS_CH1_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD1_OPCODE_MASK)
11465 #define GIS_CH1_CTRL_TOG_CMD1_ALU_MASK           0x7000u
11466 #define GIS_CH1_CTRL_TOG_CMD1_ALU_SHIFT          12
11467 #define GIS_CH1_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD1_ALU_MASK)
11468 #define GIS_CH1_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
11469 #define GIS_CH1_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
11470 #define GIS_CH1_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
11471 #define GIS_CH1_CTRL_TOG_CMD2_OPCODE_SHIFT       16
11472 #define GIS_CH1_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD2_OPCODE_MASK)
11473 #define GIS_CH1_CTRL_TOG_CMD2_ALU_MASK           0x700000u
11474 #define GIS_CH1_CTRL_TOG_CMD2_ALU_SHIFT          20
11475 #define GIS_CH1_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD2_ALU_MASK)
11476 #define GIS_CH1_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
11477 #define GIS_CH1_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
11478 #define GIS_CH1_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
11479 #define GIS_CH1_CTRL_TOG_CMD3_OPCODE_SHIFT       24
11480 #define GIS_CH1_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD3_OPCODE_MASK)
11481 #define GIS_CH1_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
11482 #define GIS_CH1_CTRL_TOG_CMD3_ALU_SHIFT          28
11483 #define GIS_CH1_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD3_ALU_MASK)
11484 #define GIS_CH1_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
11485 #define GIS_CH1_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
11486 /* CH1_ADDR0 Bit Fields */
11487 #define GIS_CH1_ADDR0_ADDR_MASK                  0x7FFFFFFu
11488 #define GIS_CH1_ADDR0_ADDR_SHIFT                 0
11489 #define GIS_CH1_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_ADDR_SHIFT))&GIS_CH1_ADDR0_ADDR_MASK)
11490 #define GIS_CH1_ADDR0_CSI0_SEL_MASK              0x8000000u
11491 #define GIS_CH1_ADDR0_CSI0_SEL_SHIFT             27
11492 #define GIS_CH1_ADDR0_CSI1_SEL_MASK              0x10000000u
11493 #define GIS_CH1_ADDR0_CSI1_SEL_SHIFT             28
11494 #define GIS_CH1_ADDR0_PXP_SEL_MASK               0x20000000u
11495 #define GIS_CH1_ADDR0_PXP_SEL_SHIFT              29
11496 #define GIS_CH1_ADDR0_LCDIF0_SEL_MASK            0x40000000u
11497 #define GIS_CH1_ADDR0_LCDIF0_SEL_SHIFT           30
11498 #define GIS_CH1_ADDR0_LCDIF1_SEL_MASK            0x80000000u
11499 #define GIS_CH1_ADDR0_LCDIF1_SEL_SHIFT           31
11500 /* CH1_ADDR0_SET Bit Fields */
11501 #define GIS_CH1_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
11502 #define GIS_CH1_ADDR0_SET_ADDR_SHIFT             0
11503 #define GIS_CH1_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_SET_ADDR_SHIFT))&GIS_CH1_ADDR0_SET_ADDR_MASK)
11504 #define GIS_CH1_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
11505 #define GIS_CH1_ADDR0_SET_CSI0_SEL_SHIFT         27
11506 #define GIS_CH1_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
11507 #define GIS_CH1_ADDR0_SET_CSI1_SEL_SHIFT         28
11508 #define GIS_CH1_ADDR0_SET_PXP_SEL_MASK           0x20000000u
11509 #define GIS_CH1_ADDR0_SET_PXP_SEL_SHIFT          29
11510 #define GIS_CH1_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
11511 #define GIS_CH1_ADDR0_SET_LCDIF0_SEL_SHIFT       30
11512 #define GIS_CH1_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
11513 #define GIS_CH1_ADDR0_SET_LCDIF1_SEL_SHIFT       31
11514 /* CH1_ADDR0_CLR Bit Fields */
11515 #define GIS_CH1_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
11516 #define GIS_CH1_ADDR0_CLR_ADDR_SHIFT             0
11517 #define GIS_CH1_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_CLR_ADDR_SHIFT))&GIS_CH1_ADDR0_CLR_ADDR_MASK)
11518 #define GIS_CH1_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
11519 #define GIS_CH1_ADDR0_CLR_CSI0_SEL_SHIFT         27
11520 #define GIS_CH1_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
11521 #define GIS_CH1_ADDR0_CLR_CSI1_SEL_SHIFT         28
11522 #define GIS_CH1_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
11523 #define GIS_CH1_ADDR0_CLR_PXP_SEL_SHIFT          29
11524 #define GIS_CH1_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
11525 #define GIS_CH1_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
11526 #define GIS_CH1_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
11527 #define GIS_CH1_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
11528 /* CH1_ADDR0_TOG Bit Fields */
11529 #define GIS_CH1_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
11530 #define GIS_CH1_ADDR0_TOG_ADDR_SHIFT             0
11531 #define GIS_CH1_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_TOG_ADDR_SHIFT))&GIS_CH1_ADDR0_TOG_ADDR_MASK)
11532 #define GIS_CH1_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
11533 #define GIS_CH1_ADDR0_TOG_CSI0_SEL_SHIFT         27
11534 #define GIS_CH1_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
11535 #define GIS_CH1_ADDR0_TOG_CSI1_SEL_SHIFT         28
11536 #define GIS_CH1_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
11537 #define GIS_CH1_ADDR0_TOG_PXP_SEL_SHIFT          29
11538 #define GIS_CH1_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
11539 #define GIS_CH1_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
11540 #define GIS_CH1_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
11541 #define GIS_CH1_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
11542 /* CH1_DATA0 Bit Fields */
11543 #define GIS_CH1_DATA0_DATA_MASK                  0xFFFFFFFFu
11544 #define GIS_CH1_DATA0_DATA_SHIFT                 0
11545 #define GIS_CH1_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA0_DATA_SHIFT))&GIS_CH1_DATA0_DATA_MASK)
11546 /* CH1_ADDR1 Bit Fields */
11547 #define GIS_CH1_ADDR1_ADDR_MASK                  0x7FFFFFFu
11548 #define GIS_CH1_ADDR1_ADDR_SHIFT                 0
11549 #define GIS_CH1_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_ADDR_SHIFT))&GIS_CH1_ADDR1_ADDR_MASK)
11550 #define GIS_CH1_ADDR1_CSI0_SEL_MASK              0x8000000u
11551 #define GIS_CH1_ADDR1_CSI0_SEL_SHIFT             27
11552 #define GIS_CH1_ADDR1_CSI1_SEL_MASK              0x10000000u
11553 #define GIS_CH1_ADDR1_CSI1_SEL_SHIFT             28
11554 #define GIS_CH1_ADDR1_PXP_SEL_MASK               0x20000000u
11555 #define GIS_CH1_ADDR1_PXP_SEL_SHIFT              29
11556 #define GIS_CH1_ADDR1_LCDIF0_SEL_MASK            0x40000000u
11557 #define GIS_CH1_ADDR1_LCDIF0_SEL_SHIFT           30
11558 #define GIS_CH1_ADDR1_LCDIF1_SEL_MASK            0x80000000u
11559 #define GIS_CH1_ADDR1_LCDIF1_SEL_SHIFT           31
11560 /* CH1_ADDR1_SET Bit Fields */
11561 #define GIS_CH1_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
11562 #define GIS_CH1_ADDR1_SET_ADDR_SHIFT             0
11563 #define GIS_CH1_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_SET_ADDR_SHIFT))&GIS_CH1_ADDR1_SET_ADDR_MASK)
11564 #define GIS_CH1_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
11565 #define GIS_CH1_ADDR1_SET_CSI0_SEL_SHIFT         27
11566 #define GIS_CH1_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
11567 #define GIS_CH1_ADDR1_SET_CSI1_SEL_SHIFT         28
11568 #define GIS_CH1_ADDR1_SET_PXP_SEL_MASK           0x20000000u
11569 #define GIS_CH1_ADDR1_SET_PXP_SEL_SHIFT          29
11570 #define GIS_CH1_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
11571 #define GIS_CH1_ADDR1_SET_LCDIF0_SEL_SHIFT       30
11572 #define GIS_CH1_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
11573 #define GIS_CH1_ADDR1_SET_LCDIF1_SEL_SHIFT       31
11574 /* CH1_ADDR1_CLR Bit Fields */
11575 #define GIS_CH1_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
11576 #define GIS_CH1_ADDR1_CLR_ADDR_SHIFT             0
11577 #define GIS_CH1_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_CLR_ADDR_SHIFT))&GIS_CH1_ADDR1_CLR_ADDR_MASK)
11578 #define GIS_CH1_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
11579 #define GIS_CH1_ADDR1_CLR_CSI0_SEL_SHIFT         27
11580 #define GIS_CH1_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
11581 #define GIS_CH1_ADDR1_CLR_CSI1_SEL_SHIFT         28
11582 #define GIS_CH1_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
11583 #define GIS_CH1_ADDR1_CLR_PXP_SEL_SHIFT          29
11584 #define GIS_CH1_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
11585 #define GIS_CH1_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
11586 #define GIS_CH1_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
11587 #define GIS_CH1_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
11588 /* CH1_ADDR1_TOG Bit Fields */
11589 #define GIS_CH1_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
11590 #define GIS_CH1_ADDR1_TOG_ADDR_SHIFT             0
11591 #define GIS_CH1_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_TOG_ADDR_SHIFT))&GIS_CH1_ADDR1_TOG_ADDR_MASK)
11592 #define GIS_CH1_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
11593 #define GIS_CH1_ADDR1_TOG_CSI0_SEL_SHIFT         27
11594 #define GIS_CH1_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
11595 #define GIS_CH1_ADDR1_TOG_CSI1_SEL_SHIFT         28
11596 #define GIS_CH1_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
11597 #define GIS_CH1_ADDR1_TOG_PXP_SEL_SHIFT          29
11598 #define GIS_CH1_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
11599 #define GIS_CH1_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
11600 #define GIS_CH1_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
11601 #define GIS_CH1_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
11602 /* CH1_DATA1 Bit Fields */
11603 #define GIS_CH1_DATA1_DATA_MASK                  0xFFFFFFFFu
11604 #define GIS_CH1_DATA1_DATA_SHIFT                 0
11605 #define GIS_CH1_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA1_DATA_SHIFT))&GIS_CH1_DATA1_DATA_MASK)
11606 /* CH1_ADDR2 Bit Fields */
11607 #define GIS_CH1_ADDR2_ADDR_MASK                  0x7FFFFFFu
11608 #define GIS_CH1_ADDR2_ADDR_SHIFT                 0
11609 #define GIS_CH1_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_ADDR_SHIFT))&GIS_CH1_ADDR2_ADDR_MASK)
11610 #define GIS_CH1_ADDR2_CSI0_SEL_MASK              0x8000000u
11611 #define GIS_CH1_ADDR2_CSI0_SEL_SHIFT             27
11612 #define GIS_CH1_ADDR2_CSI1_SEL_MASK              0x10000000u
11613 #define GIS_CH1_ADDR2_CSI1_SEL_SHIFT             28
11614 #define GIS_CH1_ADDR2_PXP_SEL_MASK               0x20000000u
11615 #define GIS_CH1_ADDR2_PXP_SEL_SHIFT              29
11616 #define GIS_CH1_ADDR2_LCDIF0_SEL_MASK            0x40000000u
11617 #define GIS_CH1_ADDR2_LCDIF0_SEL_SHIFT           30
11618 #define GIS_CH1_ADDR2_LCDIF1_SEL_MASK            0x80000000u
11619 #define GIS_CH1_ADDR2_LCDIF1_SEL_SHIFT           31
11620 /* CH1_ADDR2_SET Bit Fields */
11621 #define GIS_CH1_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
11622 #define GIS_CH1_ADDR2_SET_ADDR_SHIFT             0
11623 #define GIS_CH1_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_SET_ADDR_SHIFT))&GIS_CH1_ADDR2_SET_ADDR_MASK)
11624 #define GIS_CH1_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
11625 #define GIS_CH1_ADDR2_SET_CSI0_SEL_SHIFT         27
11626 #define GIS_CH1_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
11627 #define GIS_CH1_ADDR2_SET_CSI1_SEL_SHIFT         28
11628 #define GIS_CH1_ADDR2_SET_PXP_SEL_MASK           0x20000000u
11629 #define GIS_CH1_ADDR2_SET_PXP_SEL_SHIFT          29
11630 #define GIS_CH1_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
11631 #define GIS_CH1_ADDR2_SET_LCDIF0_SEL_SHIFT       30
11632 #define GIS_CH1_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
11633 #define GIS_CH1_ADDR2_SET_LCDIF1_SEL_SHIFT       31
11634 /* CH1_ADDR2_CLR Bit Fields */
11635 #define GIS_CH1_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
11636 #define GIS_CH1_ADDR2_CLR_ADDR_SHIFT             0
11637 #define GIS_CH1_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_CLR_ADDR_SHIFT))&GIS_CH1_ADDR2_CLR_ADDR_MASK)
11638 #define GIS_CH1_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
11639 #define GIS_CH1_ADDR2_CLR_CSI0_SEL_SHIFT         27
11640 #define GIS_CH1_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
11641 #define GIS_CH1_ADDR2_CLR_CSI1_SEL_SHIFT         28
11642 #define GIS_CH1_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
11643 #define GIS_CH1_ADDR2_CLR_PXP_SEL_SHIFT          29
11644 #define GIS_CH1_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
11645 #define GIS_CH1_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
11646 #define GIS_CH1_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
11647 #define GIS_CH1_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
11648 /* CH1_ADDR2_TOG Bit Fields */
11649 #define GIS_CH1_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
11650 #define GIS_CH1_ADDR2_TOG_ADDR_SHIFT             0
11651 #define GIS_CH1_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_TOG_ADDR_SHIFT))&GIS_CH1_ADDR2_TOG_ADDR_MASK)
11652 #define GIS_CH1_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
11653 #define GIS_CH1_ADDR2_TOG_CSI0_SEL_SHIFT         27
11654 #define GIS_CH1_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
11655 #define GIS_CH1_ADDR2_TOG_CSI1_SEL_SHIFT         28
11656 #define GIS_CH1_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
11657 #define GIS_CH1_ADDR2_TOG_PXP_SEL_SHIFT          29
11658 #define GIS_CH1_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
11659 #define GIS_CH1_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
11660 #define GIS_CH1_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
11661 #define GIS_CH1_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
11662 /* CH1_DATA2 Bit Fields */
11663 #define GIS_CH1_DATA2_DATA_MASK                  0xFFFFFFFFu
11664 #define GIS_CH1_DATA2_DATA_SHIFT                 0
11665 #define GIS_CH1_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA2_DATA_SHIFT))&GIS_CH1_DATA2_DATA_MASK)
11666 /* CH1_ADDR3 Bit Fields */
11667 #define GIS_CH1_ADDR3_ADDR_MASK                  0x7FFFFFFu
11668 #define GIS_CH1_ADDR3_ADDR_SHIFT                 0
11669 #define GIS_CH1_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_ADDR_SHIFT))&GIS_CH1_ADDR3_ADDR_MASK)
11670 #define GIS_CH1_ADDR3_CSI0_SEL_MASK              0x8000000u
11671 #define GIS_CH1_ADDR3_CSI0_SEL_SHIFT             27
11672 #define GIS_CH1_ADDR3_CSI1_SEL_MASK              0x10000000u
11673 #define GIS_CH1_ADDR3_CSI1_SEL_SHIFT             28
11674 #define GIS_CH1_ADDR3_PXP_SEL_MASK               0x20000000u
11675 #define GIS_CH1_ADDR3_PXP_SEL_SHIFT              29
11676 #define GIS_CH1_ADDR3_LCDIF0_SEL_MASK            0x40000000u
11677 #define GIS_CH1_ADDR3_LCDIF0_SEL_SHIFT           30
11678 #define GIS_CH1_ADDR3_LCDIF1_SEL_MASK            0x80000000u
11679 #define GIS_CH1_ADDR3_LCDIF1_SEL_SHIFT           31
11680 /* CH1_ADDR3_SET Bit Fields */
11681 #define GIS_CH1_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
11682 #define GIS_CH1_ADDR3_SET_ADDR_SHIFT             0
11683 #define GIS_CH1_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_SET_ADDR_SHIFT))&GIS_CH1_ADDR3_SET_ADDR_MASK)
11684 #define GIS_CH1_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
11685 #define GIS_CH1_ADDR3_SET_CSI0_SEL_SHIFT         27
11686 #define GIS_CH1_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
11687 #define GIS_CH1_ADDR3_SET_CSI1_SEL_SHIFT         28
11688 #define GIS_CH1_ADDR3_SET_PXP_SEL_MASK           0x20000000u
11689 #define GIS_CH1_ADDR3_SET_PXP_SEL_SHIFT          29
11690 #define GIS_CH1_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
11691 #define GIS_CH1_ADDR3_SET_LCDIF0_SEL_SHIFT       30
11692 #define GIS_CH1_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
11693 #define GIS_CH1_ADDR3_SET_LCDIF1_SEL_SHIFT       31
11694 /* CH1_ADDR3_CLR Bit Fields */
11695 #define GIS_CH1_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
11696 #define GIS_CH1_ADDR3_CLR_ADDR_SHIFT             0
11697 #define GIS_CH1_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_CLR_ADDR_SHIFT))&GIS_CH1_ADDR3_CLR_ADDR_MASK)
11698 #define GIS_CH1_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
11699 #define GIS_CH1_ADDR3_CLR_CSI0_SEL_SHIFT         27
11700 #define GIS_CH1_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
11701 #define GIS_CH1_ADDR3_CLR_CSI1_SEL_SHIFT         28
11702 #define GIS_CH1_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
11703 #define GIS_CH1_ADDR3_CLR_PXP_SEL_SHIFT          29
11704 #define GIS_CH1_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
11705 #define GIS_CH1_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
11706 #define GIS_CH1_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
11707 #define GIS_CH1_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
11708 /* CH1_ADDR3_TOG Bit Fields */
11709 #define GIS_CH1_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
11710 #define GIS_CH1_ADDR3_TOG_ADDR_SHIFT             0
11711 #define GIS_CH1_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_TOG_ADDR_SHIFT))&GIS_CH1_ADDR3_TOG_ADDR_MASK)
11712 #define GIS_CH1_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
11713 #define GIS_CH1_ADDR3_TOG_CSI0_SEL_SHIFT         27
11714 #define GIS_CH1_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
11715 #define GIS_CH1_ADDR3_TOG_CSI1_SEL_SHIFT         28
11716 #define GIS_CH1_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
11717 #define GIS_CH1_ADDR3_TOG_PXP_SEL_SHIFT          29
11718 #define GIS_CH1_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
11719 #define GIS_CH1_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
11720 #define GIS_CH1_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
11721 #define GIS_CH1_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
11722 /* CH1_DATA3 Bit Fields */
11723 #define GIS_CH1_DATA3_DATA_MASK                  0xFFFFFFFFu
11724 #define GIS_CH1_DATA3_DATA_SHIFT                 0
11725 #define GIS_CH1_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA3_DATA_SHIFT))&GIS_CH1_DATA3_DATA_MASK)
11726 /* CH2_CTRL Bit Fields */
11727 #define GIS_CH2_CTRL_CMD0_OPCODE_MASK            0xFu
11728 #define GIS_CH2_CTRL_CMD0_OPCODE_SHIFT           0
11729 #define GIS_CH2_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD0_OPCODE_MASK)
11730 #define GIS_CH2_CTRL_CMD0_ALU_MASK               0x70u
11731 #define GIS_CH2_CTRL_CMD0_ALU_SHIFT              4
11732 #define GIS_CH2_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_CMD0_ALU_MASK)
11733 #define GIS_CH2_CTRL_CMD0_ACC_NEG_MASK           0x80u
11734 #define GIS_CH2_CTRL_CMD0_ACC_NEG_SHIFT          7
11735 #define GIS_CH2_CTRL_CMD1_OPCODE_MASK            0xF00u
11736 #define GIS_CH2_CTRL_CMD1_OPCODE_SHIFT           8
11737 #define GIS_CH2_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD1_OPCODE_MASK)
11738 #define GIS_CH2_CTRL_CMD1_ALU_MASK               0x7000u
11739 #define GIS_CH2_CTRL_CMD1_ALU_SHIFT              12
11740 #define GIS_CH2_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_CMD1_ALU_MASK)
11741 #define GIS_CH2_CTRL_CMD1_ACC_NEG_MASK           0x8000u
11742 #define GIS_CH2_CTRL_CMD1_ACC_NEG_SHIFT          15
11743 #define GIS_CH2_CTRL_CMD2_OPCODE_MASK            0xF0000u
11744 #define GIS_CH2_CTRL_CMD2_OPCODE_SHIFT           16
11745 #define GIS_CH2_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD2_OPCODE_MASK)
11746 #define GIS_CH2_CTRL_CMD2_ALU_MASK               0x700000u
11747 #define GIS_CH2_CTRL_CMD2_ALU_SHIFT              20
11748 #define GIS_CH2_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_CMD2_ALU_MASK)
11749 #define GIS_CH2_CTRL_CMD2_ACC_NEG_MASK           0x800000u
11750 #define GIS_CH2_CTRL_CMD2_ACC_NEG_SHIFT          23
11751 #define GIS_CH2_CTRL_CMD3_OPCODE_MASK            0xF000000u
11752 #define GIS_CH2_CTRL_CMD3_OPCODE_SHIFT           24
11753 #define GIS_CH2_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD3_OPCODE_MASK)
11754 #define GIS_CH2_CTRL_CMD3_ALU_MASK               0x70000000u
11755 #define GIS_CH2_CTRL_CMD3_ALU_SHIFT              28
11756 #define GIS_CH2_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_CMD3_ALU_MASK)
11757 #define GIS_CH2_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
11758 #define GIS_CH2_CTRL_CMD3_ACC_NEG_SHIFT          31
11759 /* CH2_CTRL_SET Bit Fields */
11760 #define GIS_CH2_CTRL_SET_CMD0_OPCODE_MASK        0xFu
11761 #define GIS_CH2_CTRL_SET_CMD0_OPCODE_SHIFT       0
11762 #define GIS_CH2_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD0_OPCODE_MASK)
11763 #define GIS_CH2_CTRL_SET_CMD0_ALU_MASK           0x70u
11764 #define GIS_CH2_CTRL_SET_CMD0_ALU_SHIFT          4
11765 #define GIS_CH2_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD0_ALU_MASK)
11766 #define GIS_CH2_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
11767 #define GIS_CH2_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
11768 #define GIS_CH2_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
11769 #define GIS_CH2_CTRL_SET_CMD1_OPCODE_SHIFT       8
11770 #define GIS_CH2_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD1_OPCODE_MASK)
11771 #define GIS_CH2_CTRL_SET_CMD1_ALU_MASK           0x7000u
11772 #define GIS_CH2_CTRL_SET_CMD1_ALU_SHIFT          12
11773 #define GIS_CH2_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD1_ALU_MASK)
11774 #define GIS_CH2_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
11775 #define GIS_CH2_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
11776 #define GIS_CH2_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
11777 #define GIS_CH2_CTRL_SET_CMD2_OPCODE_SHIFT       16
11778 #define GIS_CH2_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD2_OPCODE_MASK)
11779 #define GIS_CH2_CTRL_SET_CMD2_ALU_MASK           0x700000u
11780 #define GIS_CH2_CTRL_SET_CMD2_ALU_SHIFT          20
11781 #define GIS_CH2_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD2_ALU_MASK)
11782 #define GIS_CH2_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
11783 #define GIS_CH2_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
11784 #define GIS_CH2_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
11785 #define GIS_CH2_CTRL_SET_CMD3_OPCODE_SHIFT       24
11786 #define GIS_CH2_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD3_OPCODE_MASK)
11787 #define GIS_CH2_CTRL_SET_CMD3_ALU_MASK           0x70000000u
11788 #define GIS_CH2_CTRL_SET_CMD3_ALU_SHIFT          28
11789 #define GIS_CH2_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD3_ALU_MASK)
11790 #define GIS_CH2_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
11791 #define GIS_CH2_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
11792 /* CH2_CTRL_CLR Bit Fields */
11793 #define GIS_CH2_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
11794 #define GIS_CH2_CTRL_CLR_CMD0_OPCODE_SHIFT       0
11795 #define GIS_CH2_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD0_OPCODE_MASK)
11796 #define GIS_CH2_CTRL_CLR_CMD0_ALU_MASK           0x70u
11797 #define GIS_CH2_CTRL_CLR_CMD0_ALU_SHIFT          4
11798 #define GIS_CH2_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD0_ALU_MASK)
11799 #define GIS_CH2_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
11800 #define GIS_CH2_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
11801 #define GIS_CH2_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
11802 #define GIS_CH2_CTRL_CLR_CMD1_OPCODE_SHIFT       8
11803 #define GIS_CH2_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD1_OPCODE_MASK)
11804 #define GIS_CH2_CTRL_CLR_CMD1_ALU_MASK           0x7000u
11805 #define GIS_CH2_CTRL_CLR_CMD1_ALU_SHIFT          12
11806 #define GIS_CH2_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD1_ALU_MASK)
11807 #define GIS_CH2_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
11808 #define GIS_CH2_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
11809 #define GIS_CH2_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
11810 #define GIS_CH2_CTRL_CLR_CMD2_OPCODE_SHIFT       16
11811 #define GIS_CH2_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD2_OPCODE_MASK)
11812 #define GIS_CH2_CTRL_CLR_CMD2_ALU_MASK           0x700000u
11813 #define GIS_CH2_CTRL_CLR_CMD2_ALU_SHIFT          20
11814 #define GIS_CH2_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD2_ALU_MASK)
11815 #define GIS_CH2_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
11816 #define GIS_CH2_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
11817 #define GIS_CH2_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
11818 #define GIS_CH2_CTRL_CLR_CMD3_OPCODE_SHIFT       24
11819 #define GIS_CH2_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD3_OPCODE_MASK)
11820 #define GIS_CH2_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
11821 #define GIS_CH2_CTRL_CLR_CMD3_ALU_SHIFT          28
11822 #define GIS_CH2_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD3_ALU_MASK)
11823 #define GIS_CH2_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
11824 #define GIS_CH2_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
11825 /* CH2_CTRL_TOG Bit Fields */
11826 #define GIS_CH2_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
11827 #define GIS_CH2_CTRL_TOG_CMD0_OPCODE_SHIFT       0
11828 #define GIS_CH2_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD0_OPCODE_MASK)
11829 #define GIS_CH2_CTRL_TOG_CMD0_ALU_MASK           0x70u
11830 #define GIS_CH2_CTRL_TOG_CMD0_ALU_SHIFT          4
11831 #define GIS_CH2_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD0_ALU_MASK)
11832 #define GIS_CH2_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
11833 #define GIS_CH2_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
11834 #define GIS_CH2_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
11835 #define GIS_CH2_CTRL_TOG_CMD1_OPCODE_SHIFT       8
11836 #define GIS_CH2_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD1_OPCODE_MASK)
11837 #define GIS_CH2_CTRL_TOG_CMD1_ALU_MASK           0x7000u
11838 #define GIS_CH2_CTRL_TOG_CMD1_ALU_SHIFT          12
11839 #define GIS_CH2_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD1_ALU_MASK)
11840 #define GIS_CH2_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
11841 #define GIS_CH2_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
11842 #define GIS_CH2_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
11843 #define GIS_CH2_CTRL_TOG_CMD2_OPCODE_SHIFT       16
11844 #define GIS_CH2_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD2_OPCODE_MASK)
11845 #define GIS_CH2_CTRL_TOG_CMD2_ALU_MASK           0x700000u
11846 #define GIS_CH2_CTRL_TOG_CMD2_ALU_SHIFT          20
11847 #define GIS_CH2_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD2_ALU_MASK)
11848 #define GIS_CH2_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
11849 #define GIS_CH2_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
11850 #define GIS_CH2_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
11851 #define GIS_CH2_CTRL_TOG_CMD3_OPCODE_SHIFT       24
11852 #define GIS_CH2_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD3_OPCODE_MASK)
11853 #define GIS_CH2_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
11854 #define GIS_CH2_CTRL_TOG_CMD3_ALU_SHIFT          28
11855 #define GIS_CH2_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD3_ALU_MASK)
11856 #define GIS_CH2_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
11857 #define GIS_CH2_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
11858 /* CH2_ADDR0 Bit Fields */
11859 #define GIS_CH2_ADDR0_ADDR_MASK                  0x7FFFFFFu
11860 #define GIS_CH2_ADDR0_ADDR_SHIFT                 0
11861 #define GIS_CH2_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_ADDR_SHIFT))&GIS_CH2_ADDR0_ADDR_MASK)
11862 #define GIS_CH2_ADDR0_CSI0_SEL_MASK              0x8000000u
11863 #define GIS_CH2_ADDR0_CSI0_SEL_SHIFT             27
11864 #define GIS_CH2_ADDR0_CSI1_SEL_MASK              0x10000000u
11865 #define GIS_CH2_ADDR0_CSI1_SEL_SHIFT             28
11866 #define GIS_CH2_ADDR0_PXP_SEL_MASK               0x20000000u
11867 #define GIS_CH2_ADDR0_PXP_SEL_SHIFT              29
11868 #define GIS_CH2_ADDR0_LCDIF0_SEL_MASK            0x40000000u
11869 #define GIS_CH2_ADDR0_LCDIF0_SEL_SHIFT           30
11870 #define GIS_CH2_ADDR0_LCDIF1_SEL_MASK            0x80000000u
11871 #define GIS_CH2_ADDR0_LCDIF1_SEL_SHIFT           31
11872 /* CH2_ADDR0_SET Bit Fields */
11873 #define GIS_CH2_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
11874 #define GIS_CH2_ADDR0_SET_ADDR_SHIFT             0
11875 #define GIS_CH2_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_SET_ADDR_SHIFT))&GIS_CH2_ADDR0_SET_ADDR_MASK)
11876 #define GIS_CH2_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
11877 #define GIS_CH2_ADDR0_SET_CSI0_SEL_SHIFT         27
11878 #define GIS_CH2_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
11879 #define GIS_CH2_ADDR0_SET_CSI1_SEL_SHIFT         28
11880 #define GIS_CH2_ADDR0_SET_PXP_SEL_MASK           0x20000000u
11881 #define GIS_CH2_ADDR0_SET_PXP_SEL_SHIFT          29
11882 #define GIS_CH2_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
11883 #define GIS_CH2_ADDR0_SET_LCDIF0_SEL_SHIFT       30
11884 #define GIS_CH2_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
11885 #define GIS_CH2_ADDR0_SET_LCDIF1_SEL_SHIFT       31
11886 /* CH2_ADDR0_CLR Bit Fields */
11887 #define GIS_CH2_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
11888 #define GIS_CH2_ADDR0_CLR_ADDR_SHIFT             0
11889 #define GIS_CH2_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_CLR_ADDR_SHIFT))&GIS_CH2_ADDR0_CLR_ADDR_MASK)
11890 #define GIS_CH2_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
11891 #define GIS_CH2_ADDR0_CLR_CSI0_SEL_SHIFT         27
11892 #define GIS_CH2_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
11893 #define GIS_CH2_ADDR0_CLR_CSI1_SEL_SHIFT         28
11894 #define GIS_CH2_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
11895 #define GIS_CH2_ADDR0_CLR_PXP_SEL_SHIFT          29
11896 #define GIS_CH2_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
11897 #define GIS_CH2_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
11898 #define GIS_CH2_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
11899 #define GIS_CH2_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
11900 /* CH2_ADDR0_TOG Bit Fields */
11901 #define GIS_CH2_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
11902 #define GIS_CH2_ADDR0_TOG_ADDR_SHIFT             0
11903 #define GIS_CH2_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_TOG_ADDR_SHIFT))&GIS_CH2_ADDR0_TOG_ADDR_MASK)
11904 #define GIS_CH2_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
11905 #define GIS_CH2_ADDR0_TOG_CSI0_SEL_SHIFT         27
11906 #define GIS_CH2_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
11907 #define GIS_CH2_ADDR0_TOG_CSI1_SEL_SHIFT         28
11908 #define GIS_CH2_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
11909 #define GIS_CH2_ADDR0_TOG_PXP_SEL_SHIFT          29
11910 #define GIS_CH2_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
11911 #define GIS_CH2_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
11912 #define GIS_CH2_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
11913 #define GIS_CH2_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
11914 /* CH2_DATA0 Bit Fields */
11915 #define GIS_CH2_DATA0_DATA_MASK                  0xFFFFFFFFu
11916 #define GIS_CH2_DATA0_DATA_SHIFT                 0
11917 #define GIS_CH2_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA0_DATA_SHIFT))&GIS_CH2_DATA0_DATA_MASK)
11918 /* CH2_ADDR1 Bit Fields */
11919 #define GIS_CH2_ADDR1_ADDR_MASK                  0x7FFFFFFu
11920 #define GIS_CH2_ADDR1_ADDR_SHIFT                 0
11921 #define GIS_CH2_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_ADDR_SHIFT))&GIS_CH2_ADDR1_ADDR_MASK)
11922 #define GIS_CH2_ADDR1_CSI0_SEL_MASK              0x8000000u
11923 #define GIS_CH2_ADDR1_CSI0_SEL_SHIFT             27
11924 #define GIS_CH2_ADDR1_CSI1_SEL_MASK              0x10000000u
11925 #define GIS_CH2_ADDR1_CSI1_SEL_SHIFT             28
11926 #define GIS_CH2_ADDR1_PXP_SEL_MASK               0x20000000u
11927 #define GIS_CH2_ADDR1_PXP_SEL_SHIFT              29
11928 #define GIS_CH2_ADDR1_LCDIF0_SEL_MASK            0x40000000u
11929 #define GIS_CH2_ADDR1_LCDIF0_SEL_SHIFT           30
11930 #define GIS_CH2_ADDR1_LCDIF1_SEL_MASK            0x80000000u
11931 #define GIS_CH2_ADDR1_LCDIF1_SEL_SHIFT           31
11932 /* CH2_ADDR1_SET Bit Fields */
11933 #define GIS_CH2_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
11934 #define GIS_CH2_ADDR1_SET_ADDR_SHIFT             0
11935 #define GIS_CH2_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_SET_ADDR_SHIFT))&GIS_CH2_ADDR1_SET_ADDR_MASK)
11936 #define GIS_CH2_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
11937 #define GIS_CH2_ADDR1_SET_CSI0_SEL_SHIFT         27
11938 #define GIS_CH2_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
11939 #define GIS_CH2_ADDR1_SET_CSI1_SEL_SHIFT         28
11940 #define GIS_CH2_ADDR1_SET_PXP_SEL_MASK           0x20000000u
11941 #define GIS_CH2_ADDR1_SET_PXP_SEL_SHIFT          29
11942 #define GIS_CH2_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
11943 #define GIS_CH2_ADDR1_SET_LCDIF0_SEL_SHIFT       30
11944 #define GIS_CH2_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
11945 #define GIS_CH2_ADDR1_SET_LCDIF1_SEL_SHIFT       31
11946 /* CH2_ADDR1_CLR Bit Fields */
11947 #define GIS_CH2_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
11948 #define GIS_CH2_ADDR1_CLR_ADDR_SHIFT             0
11949 #define GIS_CH2_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_CLR_ADDR_SHIFT))&GIS_CH2_ADDR1_CLR_ADDR_MASK)
11950 #define GIS_CH2_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
11951 #define GIS_CH2_ADDR1_CLR_CSI0_SEL_SHIFT         27
11952 #define GIS_CH2_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
11953 #define GIS_CH2_ADDR1_CLR_CSI1_SEL_SHIFT         28
11954 #define GIS_CH2_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
11955 #define GIS_CH2_ADDR1_CLR_PXP_SEL_SHIFT          29
11956 #define GIS_CH2_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
11957 #define GIS_CH2_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
11958 #define GIS_CH2_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
11959 #define GIS_CH2_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
11960 /* CH2_ADDR1_TOG Bit Fields */
11961 #define GIS_CH2_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
11962 #define GIS_CH2_ADDR1_TOG_ADDR_SHIFT             0
11963 #define GIS_CH2_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_TOG_ADDR_SHIFT))&GIS_CH2_ADDR1_TOG_ADDR_MASK)
11964 #define GIS_CH2_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
11965 #define GIS_CH2_ADDR1_TOG_CSI0_SEL_SHIFT         27
11966 #define GIS_CH2_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
11967 #define GIS_CH2_ADDR1_TOG_CSI1_SEL_SHIFT         28
11968 #define GIS_CH2_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
11969 #define GIS_CH2_ADDR1_TOG_PXP_SEL_SHIFT          29
11970 #define GIS_CH2_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
11971 #define GIS_CH2_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
11972 #define GIS_CH2_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
11973 #define GIS_CH2_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
11974 /* CH2_DATA1 Bit Fields */
11975 #define GIS_CH2_DATA1_DATA_MASK                  0xFFFFFFFFu
11976 #define GIS_CH2_DATA1_DATA_SHIFT                 0
11977 #define GIS_CH2_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA1_DATA_SHIFT))&GIS_CH2_DATA1_DATA_MASK)
11978 /* CH2_ADDR2 Bit Fields */
11979 #define GIS_CH2_ADDR2_ADDR_MASK                  0x7FFFFFFu
11980 #define GIS_CH2_ADDR2_ADDR_SHIFT                 0
11981 #define GIS_CH2_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_ADDR_SHIFT))&GIS_CH2_ADDR2_ADDR_MASK)
11982 #define GIS_CH2_ADDR2_CSI0_SEL_MASK              0x8000000u
11983 #define GIS_CH2_ADDR2_CSI0_SEL_SHIFT             27
11984 #define GIS_CH2_ADDR2_CSI1_SEL_MASK              0x10000000u
11985 #define GIS_CH2_ADDR2_CSI1_SEL_SHIFT             28
11986 #define GIS_CH2_ADDR2_PXP_SEL_MASK               0x20000000u
11987 #define GIS_CH2_ADDR2_PXP_SEL_SHIFT              29
11988 #define GIS_CH2_ADDR2_LCDIF0_SEL_MASK            0x40000000u
11989 #define GIS_CH2_ADDR2_LCDIF0_SEL_SHIFT           30
11990 #define GIS_CH2_ADDR2_LCDIF1_SEL_MASK            0x80000000u
11991 #define GIS_CH2_ADDR2_LCDIF1_SEL_SHIFT           31
11992 /* CH2_ADDR2_SET Bit Fields */
11993 #define GIS_CH2_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
11994 #define GIS_CH2_ADDR2_SET_ADDR_SHIFT             0
11995 #define GIS_CH2_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_SET_ADDR_SHIFT))&GIS_CH2_ADDR2_SET_ADDR_MASK)
11996 #define GIS_CH2_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
11997 #define GIS_CH2_ADDR2_SET_CSI0_SEL_SHIFT         27
11998 #define GIS_CH2_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
11999 #define GIS_CH2_ADDR2_SET_CSI1_SEL_SHIFT         28
12000 #define GIS_CH2_ADDR2_SET_PXP_SEL_MASK           0x20000000u
12001 #define GIS_CH2_ADDR2_SET_PXP_SEL_SHIFT          29
12002 #define GIS_CH2_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
12003 #define GIS_CH2_ADDR2_SET_LCDIF0_SEL_SHIFT       30
12004 #define GIS_CH2_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
12005 #define GIS_CH2_ADDR2_SET_LCDIF1_SEL_SHIFT       31
12006 /* CH2_ADDR2_CLR Bit Fields */
12007 #define GIS_CH2_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
12008 #define GIS_CH2_ADDR2_CLR_ADDR_SHIFT             0
12009 #define GIS_CH2_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_CLR_ADDR_SHIFT))&GIS_CH2_ADDR2_CLR_ADDR_MASK)
12010 #define GIS_CH2_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
12011 #define GIS_CH2_ADDR2_CLR_CSI0_SEL_SHIFT         27
12012 #define GIS_CH2_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
12013 #define GIS_CH2_ADDR2_CLR_CSI1_SEL_SHIFT         28
12014 #define GIS_CH2_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
12015 #define GIS_CH2_ADDR2_CLR_PXP_SEL_SHIFT          29
12016 #define GIS_CH2_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
12017 #define GIS_CH2_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
12018 #define GIS_CH2_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
12019 #define GIS_CH2_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
12020 /* CH2_ADDR2_TOG Bit Fields */
12021 #define GIS_CH2_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
12022 #define GIS_CH2_ADDR2_TOG_ADDR_SHIFT             0
12023 #define GIS_CH2_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_TOG_ADDR_SHIFT))&GIS_CH2_ADDR2_TOG_ADDR_MASK)
12024 #define GIS_CH2_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
12025 #define GIS_CH2_ADDR2_TOG_CSI0_SEL_SHIFT         27
12026 #define GIS_CH2_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
12027 #define GIS_CH2_ADDR2_TOG_CSI1_SEL_SHIFT         28
12028 #define GIS_CH2_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
12029 #define GIS_CH2_ADDR2_TOG_PXP_SEL_SHIFT          29
12030 #define GIS_CH2_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
12031 #define GIS_CH2_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
12032 #define GIS_CH2_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
12033 #define GIS_CH2_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
12034 /* CH2_DATA2 Bit Fields */
12035 #define GIS_CH2_DATA2_DATA_MASK                  0xFFFFFFFFu
12036 #define GIS_CH2_DATA2_DATA_SHIFT                 0
12037 #define GIS_CH2_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA2_DATA_SHIFT))&GIS_CH2_DATA2_DATA_MASK)
12038 /* CH2_ADDR3 Bit Fields */
12039 #define GIS_CH2_ADDR3_ADDR_MASK                  0x7FFFFFFu
12040 #define GIS_CH2_ADDR3_ADDR_SHIFT                 0
12041 #define GIS_CH2_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_ADDR_SHIFT))&GIS_CH2_ADDR3_ADDR_MASK)
12042 #define GIS_CH2_ADDR3_CSI0_SEL_MASK              0x8000000u
12043 #define GIS_CH2_ADDR3_CSI0_SEL_SHIFT             27
12044 #define GIS_CH2_ADDR3_CSI1_SEL_MASK              0x10000000u
12045 #define GIS_CH2_ADDR3_CSI1_SEL_SHIFT             28
12046 #define GIS_CH2_ADDR3_PXP_SEL_MASK               0x20000000u
12047 #define GIS_CH2_ADDR3_PXP_SEL_SHIFT              29
12048 #define GIS_CH2_ADDR3_LCDIF0_SEL_MASK            0x40000000u
12049 #define GIS_CH2_ADDR3_LCDIF0_SEL_SHIFT           30
12050 #define GIS_CH2_ADDR3_LCDIF1_SEL_MASK            0x80000000u
12051 #define GIS_CH2_ADDR3_LCDIF1_SEL_SHIFT           31
12052 /* CH2_ADDR3_SET Bit Fields */
12053 #define GIS_CH2_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
12054 #define GIS_CH2_ADDR3_SET_ADDR_SHIFT             0
12055 #define GIS_CH2_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_SET_ADDR_SHIFT))&GIS_CH2_ADDR3_SET_ADDR_MASK)
12056 #define GIS_CH2_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
12057 #define GIS_CH2_ADDR3_SET_CSI0_SEL_SHIFT         27
12058 #define GIS_CH2_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
12059 #define GIS_CH2_ADDR3_SET_CSI1_SEL_SHIFT         28
12060 #define GIS_CH2_ADDR3_SET_PXP_SEL_MASK           0x20000000u
12061 #define GIS_CH2_ADDR3_SET_PXP_SEL_SHIFT          29
12062 #define GIS_CH2_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
12063 #define GIS_CH2_ADDR3_SET_LCDIF0_SEL_SHIFT       30
12064 #define GIS_CH2_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
12065 #define GIS_CH2_ADDR3_SET_LCDIF1_SEL_SHIFT       31
12066 /* CH2_ADDR3_CLR Bit Fields */
12067 #define GIS_CH2_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
12068 #define GIS_CH2_ADDR3_CLR_ADDR_SHIFT             0
12069 #define GIS_CH2_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_CLR_ADDR_SHIFT))&GIS_CH2_ADDR3_CLR_ADDR_MASK)
12070 #define GIS_CH2_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
12071 #define GIS_CH2_ADDR3_CLR_CSI0_SEL_SHIFT         27
12072 #define GIS_CH2_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
12073 #define GIS_CH2_ADDR3_CLR_CSI1_SEL_SHIFT         28
12074 #define GIS_CH2_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
12075 #define GIS_CH2_ADDR3_CLR_PXP_SEL_SHIFT          29
12076 #define GIS_CH2_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
12077 #define GIS_CH2_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
12078 #define GIS_CH2_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
12079 #define GIS_CH2_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
12080 /* CH2_ADDR3_TOG Bit Fields */
12081 #define GIS_CH2_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
12082 #define GIS_CH2_ADDR3_TOG_ADDR_SHIFT             0
12083 #define GIS_CH2_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_TOG_ADDR_SHIFT))&GIS_CH2_ADDR3_TOG_ADDR_MASK)
12084 #define GIS_CH2_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
12085 #define GIS_CH2_ADDR3_TOG_CSI0_SEL_SHIFT         27
12086 #define GIS_CH2_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
12087 #define GIS_CH2_ADDR3_TOG_CSI1_SEL_SHIFT         28
12088 #define GIS_CH2_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
12089 #define GIS_CH2_ADDR3_TOG_PXP_SEL_SHIFT          29
12090 #define GIS_CH2_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
12091 #define GIS_CH2_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
12092 #define GIS_CH2_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
12093 #define GIS_CH2_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
12094 /* CH2_DATA3 Bit Fields */
12095 #define GIS_CH2_DATA3_DATA_MASK                  0xFFFFFFFFu
12096 #define GIS_CH2_DATA3_DATA_SHIFT                 0
12097 #define GIS_CH2_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA3_DATA_SHIFT))&GIS_CH2_DATA3_DATA_MASK)
12098 /* CH3_CTRL Bit Fields */
12099 #define GIS_CH3_CTRL_CMD0_OPCODE_MASK            0xFu
12100 #define GIS_CH3_CTRL_CMD0_OPCODE_SHIFT           0
12101 #define GIS_CH3_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD0_OPCODE_MASK)
12102 #define GIS_CH3_CTRL_CMD0_ALU_MASK               0x70u
12103 #define GIS_CH3_CTRL_CMD0_ALU_SHIFT              4
12104 #define GIS_CH3_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_CMD0_ALU_MASK)
12105 #define GIS_CH3_CTRL_CMD0_ACC_NEG_MASK           0x80u
12106 #define GIS_CH3_CTRL_CMD0_ACC_NEG_SHIFT          7
12107 #define GIS_CH3_CTRL_CMD1_OPCODE_MASK            0xF00u
12108 #define GIS_CH3_CTRL_CMD1_OPCODE_SHIFT           8
12109 #define GIS_CH3_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD1_OPCODE_MASK)
12110 #define GIS_CH3_CTRL_CMD1_ALU_MASK               0x7000u
12111 #define GIS_CH3_CTRL_CMD1_ALU_SHIFT              12
12112 #define GIS_CH3_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_CMD1_ALU_MASK)
12113 #define GIS_CH3_CTRL_CMD1_ACC_NEG_MASK           0x8000u
12114 #define GIS_CH3_CTRL_CMD1_ACC_NEG_SHIFT          15
12115 #define GIS_CH3_CTRL_CMD2_OPCODE_MASK            0xF0000u
12116 #define GIS_CH3_CTRL_CMD2_OPCODE_SHIFT           16
12117 #define GIS_CH3_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD2_OPCODE_MASK)
12118 #define GIS_CH3_CTRL_CMD2_ALU_MASK               0x700000u
12119 #define GIS_CH3_CTRL_CMD2_ALU_SHIFT              20
12120 #define GIS_CH3_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_CMD2_ALU_MASK)
12121 #define GIS_CH3_CTRL_CMD2_ACC_NEG_MASK           0x800000u
12122 #define GIS_CH3_CTRL_CMD2_ACC_NEG_SHIFT          23
12123 #define GIS_CH3_CTRL_CMD3_OPCODE_MASK            0xF000000u
12124 #define GIS_CH3_CTRL_CMD3_OPCODE_SHIFT           24
12125 #define GIS_CH3_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD3_OPCODE_MASK)
12126 #define GIS_CH3_CTRL_CMD3_ALU_MASK               0x70000000u
12127 #define GIS_CH3_CTRL_CMD3_ALU_SHIFT              28
12128 #define GIS_CH3_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_CMD3_ALU_MASK)
12129 #define GIS_CH3_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
12130 #define GIS_CH3_CTRL_CMD3_ACC_NEG_SHIFT          31
12131 /* CH3_CTRL_SET Bit Fields */
12132 #define GIS_CH3_CTRL_SET_CMD0_OPCODE_MASK        0xFu
12133 #define GIS_CH3_CTRL_SET_CMD0_OPCODE_SHIFT       0
12134 #define GIS_CH3_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD0_OPCODE_MASK)
12135 #define GIS_CH3_CTRL_SET_CMD0_ALU_MASK           0x70u
12136 #define GIS_CH3_CTRL_SET_CMD0_ALU_SHIFT          4
12137 #define GIS_CH3_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD0_ALU_MASK)
12138 #define GIS_CH3_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
12139 #define GIS_CH3_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
12140 #define GIS_CH3_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
12141 #define GIS_CH3_CTRL_SET_CMD1_OPCODE_SHIFT       8
12142 #define GIS_CH3_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD1_OPCODE_MASK)
12143 #define GIS_CH3_CTRL_SET_CMD1_ALU_MASK           0x7000u
12144 #define GIS_CH3_CTRL_SET_CMD1_ALU_SHIFT          12
12145 #define GIS_CH3_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD1_ALU_MASK)
12146 #define GIS_CH3_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
12147 #define GIS_CH3_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
12148 #define GIS_CH3_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
12149 #define GIS_CH3_CTRL_SET_CMD2_OPCODE_SHIFT       16
12150 #define GIS_CH3_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD2_OPCODE_MASK)
12151 #define GIS_CH3_CTRL_SET_CMD2_ALU_MASK           0x700000u
12152 #define GIS_CH3_CTRL_SET_CMD2_ALU_SHIFT          20
12153 #define GIS_CH3_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD2_ALU_MASK)
12154 #define GIS_CH3_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
12155 #define GIS_CH3_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
12156 #define GIS_CH3_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
12157 #define GIS_CH3_CTRL_SET_CMD3_OPCODE_SHIFT       24
12158 #define GIS_CH3_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD3_OPCODE_MASK)
12159 #define GIS_CH3_CTRL_SET_CMD3_ALU_MASK           0x70000000u
12160 #define GIS_CH3_CTRL_SET_CMD3_ALU_SHIFT          28
12161 #define GIS_CH3_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD3_ALU_MASK)
12162 #define GIS_CH3_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
12163 #define GIS_CH3_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
12164 /* CH3_CTRL_CLR Bit Fields */
12165 #define GIS_CH3_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
12166 #define GIS_CH3_CTRL_CLR_CMD0_OPCODE_SHIFT       0
12167 #define GIS_CH3_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD0_OPCODE_MASK)
12168 #define GIS_CH3_CTRL_CLR_CMD0_ALU_MASK           0x70u
12169 #define GIS_CH3_CTRL_CLR_CMD0_ALU_SHIFT          4
12170 #define GIS_CH3_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD0_ALU_MASK)
12171 #define GIS_CH3_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
12172 #define GIS_CH3_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
12173 #define GIS_CH3_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
12174 #define GIS_CH3_CTRL_CLR_CMD1_OPCODE_SHIFT       8
12175 #define GIS_CH3_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD1_OPCODE_MASK)
12176 #define GIS_CH3_CTRL_CLR_CMD1_ALU_MASK           0x7000u
12177 #define GIS_CH3_CTRL_CLR_CMD1_ALU_SHIFT          12
12178 #define GIS_CH3_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD1_ALU_MASK)
12179 #define GIS_CH3_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
12180 #define GIS_CH3_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
12181 #define GIS_CH3_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
12182 #define GIS_CH3_CTRL_CLR_CMD2_OPCODE_SHIFT       16
12183 #define GIS_CH3_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD2_OPCODE_MASK)
12184 #define GIS_CH3_CTRL_CLR_CMD2_ALU_MASK           0x700000u
12185 #define GIS_CH3_CTRL_CLR_CMD2_ALU_SHIFT          20
12186 #define GIS_CH3_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD2_ALU_MASK)
12187 #define GIS_CH3_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
12188 #define GIS_CH3_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
12189 #define GIS_CH3_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
12190 #define GIS_CH3_CTRL_CLR_CMD3_OPCODE_SHIFT       24
12191 #define GIS_CH3_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD3_OPCODE_MASK)
12192 #define GIS_CH3_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
12193 #define GIS_CH3_CTRL_CLR_CMD3_ALU_SHIFT          28
12194 #define GIS_CH3_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD3_ALU_MASK)
12195 #define GIS_CH3_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
12196 #define GIS_CH3_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
12197 /* CH3_CTRL_TOG Bit Fields */
12198 #define GIS_CH3_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
12199 #define GIS_CH3_CTRL_TOG_CMD0_OPCODE_SHIFT       0
12200 #define GIS_CH3_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD0_OPCODE_MASK)
12201 #define GIS_CH3_CTRL_TOG_CMD0_ALU_MASK           0x70u
12202 #define GIS_CH3_CTRL_TOG_CMD0_ALU_SHIFT          4
12203 #define GIS_CH3_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD0_ALU_MASK)
12204 #define GIS_CH3_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
12205 #define GIS_CH3_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
12206 #define GIS_CH3_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
12207 #define GIS_CH3_CTRL_TOG_CMD1_OPCODE_SHIFT       8
12208 #define GIS_CH3_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD1_OPCODE_MASK)
12209 #define GIS_CH3_CTRL_TOG_CMD1_ALU_MASK           0x7000u
12210 #define GIS_CH3_CTRL_TOG_CMD1_ALU_SHIFT          12
12211 #define GIS_CH3_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD1_ALU_MASK)
12212 #define GIS_CH3_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
12213 #define GIS_CH3_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
12214 #define GIS_CH3_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
12215 #define GIS_CH3_CTRL_TOG_CMD2_OPCODE_SHIFT       16
12216 #define GIS_CH3_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD2_OPCODE_MASK)
12217 #define GIS_CH3_CTRL_TOG_CMD2_ALU_MASK           0x700000u
12218 #define GIS_CH3_CTRL_TOG_CMD2_ALU_SHIFT          20
12219 #define GIS_CH3_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD2_ALU_MASK)
12220 #define GIS_CH3_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
12221 #define GIS_CH3_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
12222 #define GIS_CH3_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
12223 #define GIS_CH3_CTRL_TOG_CMD3_OPCODE_SHIFT       24
12224 #define GIS_CH3_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD3_OPCODE_MASK)
12225 #define GIS_CH3_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
12226 #define GIS_CH3_CTRL_TOG_CMD3_ALU_SHIFT          28
12227 #define GIS_CH3_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD3_ALU_MASK)
12228 #define GIS_CH3_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
12229 #define GIS_CH3_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
12230 /* CH3_ADDR0 Bit Fields */
12231 #define GIS_CH3_ADDR0_ADDR_MASK                  0x7FFFFFFu
12232 #define GIS_CH3_ADDR0_ADDR_SHIFT                 0
12233 #define GIS_CH3_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_ADDR_SHIFT))&GIS_CH3_ADDR0_ADDR_MASK)
12234 #define GIS_CH3_ADDR0_CSI0_SEL_MASK              0x8000000u
12235 #define GIS_CH3_ADDR0_CSI0_SEL_SHIFT             27
12236 #define GIS_CH3_ADDR0_CSI1_SEL_MASK              0x10000000u
12237 #define GIS_CH3_ADDR0_CSI1_SEL_SHIFT             28
12238 #define GIS_CH3_ADDR0_PXP_SEL_MASK               0x20000000u
12239 #define GIS_CH3_ADDR0_PXP_SEL_SHIFT              29
12240 #define GIS_CH3_ADDR0_LCDIF0_SEL_MASK            0x40000000u
12241 #define GIS_CH3_ADDR0_LCDIF0_SEL_SHIFT           30
12242 #define GIS_CH3_ADDR0_LCDIF1_SEL_MASK            0x80000000u
12243 #define GIS_CH3_ADDR0_LCDIF1_SEL_SHIFT           31
12244 /* CH3_ADDR0_SET Bit Fields */
12245 #define GIS_CH3_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
12246 #define GIS_CH3_ADDR0_SET_ADDR_SHIFT             0
12247 #define GIS_CH3_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_SET_ADDR_SHIFT))&GIS_CH3_ADDR0_SET_ADDR_MASK)
12248 #define GIS_CH3_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
12249 #define GIS_CH3_ADDR0_SET_CSI0_SEL_SHIFT         27
12250 #define GIS_CH3_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
12251 #define GIS_CH3_ADDR0_SET_CSI1_SEL_SHIFT         28
12252 #define GIS_CH3_ADDR0_SET_PXP_SEL_MASK           0x20000000u
12253 #define GIS_CH3_ADDR0_SET_PXP_SEL_SHIFT          29
12254 #define GIS_CH3_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
12255 #define GIS_CH3_ADDR0_SET_LCDIF0_SEL_SHIFT       30
12256 #define GIS_CH3_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
12257 #define GIS_CH3_ADDR0_SET_LCDIF1_SEL_SHIFT       31
12258 /* CH3_ADDR0_CLR Bit Fields */
12259 #define GIS_CH3_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
12260 #define GIS_CH3_ADDR0_CLR_ADDR_SHIFT             0
12261 #define GIS_CH3_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_CLR_ADDR_SHIFT))&GIS_CH3_ADDR0_CLR_ADDR_MASK)
12262 #define GIS_CH3_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
12263 #define GIS_CH3_ADDR0_CLR_CSI0_SEL_SHIFT         27
12264 #define GIS_CH3_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
12265 #define GIS_CH3_ADDR0_CLR_CSI1_SEL_SHIFT         28
12266 #define GIS_CH3_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
12267 #define GIS_CH3_ADDR0_CLR_PXP_SEL_SHIFT          29
12268 #define GIS_CH3_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
12269 #define GIS_CH3_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
12270 #define GIS_CH3_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
12271 #define GIS_CH3_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
12272 /* CH3_ADDR0_TOG Bit Fields */
12273 #define GIS_CH3_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
12274 #define GIS_CH3_ADDR0_TOG_ADDR_SHIFT             0
12275 #define GIS_CH3_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_TOG_ADDR_SHIFT))&GIS_CH3_ADDR0_TOG_ADDR_MASK)
12276 #define GIS_CH3_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
12277 #define GIS_CH3_ADDR0_TOG_CSI0_SEL_SHIFT         27
12278 #define GIS_CH3_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
12279 #define GIS_CH3_ADDR0_TOG_CSI1_SEL_SHIFT         28
12280 #define GIS_CH3_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
12281 #define GIS_CH3_ADDR0_TOG_PXP_SEL_SHIFT          29
12282 #define GIS_CH3_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
12283 #define GIS_CH3_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
12284 #define GIS_CH3_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
12285 #define GIS_CH3_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
12286 /* CH3_DATA0 Bit Fields */
12287 #define GIS_CH3_DATA0_DATA_MASK                  0xFFFFFFFFu
12288 #define GIS_CH3_DATA0_DATA_SHIFT                 0
12289 #define GIS_CH3_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA0_DATA_SHIFT))&GIS_CH3_DATA0_DATA_MASK)
12290 /* CH3_ADDR1 Bit Fields */
12291 #define GIS_CH3_ADDR1_ADDR_MASK                  0x7FFFFFFu
12292 #define GIS_CH3_ADDR1_ADDR_SHIFT                 0
12293 #define GIS_CH3_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_ADDR_SHIFT))&GIS_CH3_ADDR1_ADDR_MASK)
12294 #define GIS_CH3_ADDR1_CSI0_SEL_MASK              0x8000000u
12295 #define GIS_CH3_ADDR1_CSI0_SEL_SHIFT             27
12296 #define GIS_CH3_ADDR1_CSI1_SEL_MASK              0x10000000u
12297 #define GIS_CH3_ADDR1_CSI1_SEL_SHIFT             28
12298 #define GIS_CH3_ADDR1_PXP_SEL_MASK               0x20000000u
12299 #define GIS_CH3_ADDR1_PXP_SEL_SHIFT              29
12300 #define GIS_CH3_ADDR1_LCDIF0_SEL_MASK            0x40000000u
12301 #define GIS_CH3_ADDR1_LCDIF0_SEL_SHIFT           30
12302 #define GIS_CH3_ADDR1_LCDIF1_SEL_MASK            0x80000000u
12303 #define GIS_CH3_ADDR1_LCDIF1_SEL_SHIFT           31
12304 /* CH3_ADDR1_SET Bit Fields */
12305 #define GIS_CH3_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
12306 #define GIS_CH3_ADDR1_SET_ADDR_SHIFT             0
12307 #define GIS_CH3_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_SET_ADDR_SHIFT))&GIS_CH3_ADDR1_SET_ADDR_MASK)
12308 #define GIS_CH3_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
12309 #define GIS_CH3_ADDR1_SET_CSI0_SEL_SHIFT         27
12310 #define GIS_CH3_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
12311 #define GIS_CH3_ADDR1_SET_CSI1_SEL_SHIFT         28
12312 #define GIS_CH3_ADDR1_SET_PXP_SEL_MASK           0x20000000u
12313 #define GIS_CH3_ADDR1_SET_PXP_SEL_SHIFT          29
12314 #define GIS_CH3_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
12315 #define GIS_CH3_ADDR1_SET_LCDIF0_SEL_SHIFT       30
12316 #define GIS_CH3_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
12317 #define GIS_CH3_ADDR1_SET_LCDIF1_SEL_SHIFT       31
12318 /* CH3_ADDR1_CLR Bit Fields */
12319 #define GIS_CH3_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
12320 #define GIS_CH3_ADDR1_CLR_ADDR_SHIFT             0
12321 #define GIS_CH3_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_CLR_ADDR_SHIFT))&GIS_CH3_ADDR1_CLR_ADDR_MASK)
12322 #define GIS_CH3_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
12323 #define GIS_CH3_ADDR1_CLR_CSI0_SEL_SHIFT         27
12324 #define GIS_CH3_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
12325 #define GIS_CH3_ADDR1_CLR_CSI1_SEL_SHIFT         28
12326 #define GIS_CH3_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
12327 #define GIS_CH3_ADDR1_CLR_PXP_SEL_SHIFT          29
12328 #define GIS_CH3_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
12329 #define GIS_CH3_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
12330 #define GIS_CH3_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
12331 #define GIS_CH3_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
12332 /* CH3_ADDR1_TOG Bit Fields */
12333 #define GIS_CH3_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
12334 #define GIS_CH3_ADDR1_TOG_ADDR_SHIFT             0
12335 #define GIS_CH3_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_TOG_ADDR_SHIFT))&GIS_CH3_ADDR1_TOG_ADDR_MASK)
12336 #define GIS_CH3_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
12337 #define GIS_CH3_ADDR1_TOG_CSI0_SEL_SHIFT         27
12338 #define GIS_CH3_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
12339 #define GIS_CH3_ADDR1_TOG_CSI1_SEL_SHIFT         28
12340 #define GIS_CH3_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
12341 #define GIS_CH3_ADDR1_TOG_PXP_SEL_SHIFT          29
12342 #define GIS_CH3_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
12343 #define GIS_CH3_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
12344 #define GIS_CH3_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
12345 #define GIS_CH3_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
12346 /* CH3_DATA1 Bit Fields */
12347 #define GIS_CH3_DATA1_DATA_MASK                  0xFFFFFFFFu
12348 #define GIS_CH3_DATA1_DATA_SHIFT                 0
12349 #define GIS_CH3_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA1_DATA_SHIFT))&GIS_CH3_DATA1_DATA_MASK)
12350 /* CH3_ADDR2 Bit Fields */
12351 #define GIS_CH3_ADDR2_ADDR_MASK                  0x7FFFFFFu
12352 #define GIS_CH3_ADDR2_ADDR_SHIFT                 0
12353 #define GIS_CH3_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_ADDR_SHIFT))&GIS_CH3_ADDR2_ADDR_MASK)
12354 #define GIS_CH3_ADDR2_CSI0_SEL_MASK              0x8000000u
12355 #define GIS_CH3_ADDR2_CSI0_SEL_SHIFT             27
12356 #define GIS_CH3_ADDR2_CSI1_SEL_MASK              0x10000000u
12357 #define GIS_CH3_ADDR2_CSI1_SEL_SHIFT             28
12358 #define GIS_CH3_ADDR2_PXP_SEL_MASK               0x20000000u
12359 #define GIS_CH3_ADDR2_PXP_SEL_SHIFT              29
12360 #define GIS_CH3_ADDR2_LCDIF0_SEL_MASK            0x40000000u
12361 #define GIS_CH3_ADDR2_LCDIF0_SEL_SHIFT           30
12362 #define GIS_CH3_ADDR2_LCDIF1_SEL_MASK            0x80000000u
12363 #define GIS_CH3_ADDR2_LCDIF1_SEL_SHIFT           31
12364 /* CH3_ADDR2_SET Bit Fields */
12365 #define GIS_CH3_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
12366 #define GIS_CH3_ADDR2_SET_ADDR_SHIFT             0
12367 #define GIS_CH3_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_SET_ADDR_SHIFT))&GIS_CH3_ADDR2_SET_ADDR_MASK)
12368 #define GIS_CH3_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
12369 #define GIS_CH3_ADDR2_SET_CSI0_SEL_SHIFT         27
12370 #define GIS_CH3_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
12371 #define GIS_CH3_ADDR2_SET_CSI1_SEL_SHIFT         28
12372 #define GIS_CH3_ADDR2_SET_PXP_SEL_MASK           0x20000000u
12373 #define GIS_CH3_ADDR2_SET_PXP_SEL_SHIFT          29
12374 #define GIS_CH3_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
12375 #define GIS_CH3_ADDR2_SET_LCDIF0_SEL_SHIFT       30
12376 #define GIS_CH3_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
12377 #define GIS_CH3_ADDR2_SET_LCDIF1_SEL_SHIFT       31
12378 /* CH3_ADDR2_CLR Bit Fields */
12379 #define GIS_CH3_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
12380 #define GIS_CH3_ADDR2_CLR_ADDR_SHIFT             0
12381 #define GIS_CH3_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_CLR_ADDR_SHIFT))&GIS_CH3_ADDR2_CLR_ADDR_MASK)
12382 #define GIS_CH3_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
12383 #define GIS_CH3_ADDR2_CLR_CSI0_SEL_SHIFT         27
12384 #define GIS_CH3_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
12385 #define GIS_CH3_ADDR2_CLR_CSI1_SEL_SHIFT         28
12386 #define GIS_CH3_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
12387 #define GIS_CH3_ADDR2_CLR_PXP_SEL_SHIFT          29
12388 #define GIS_CH3_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
12389 #define GIS_CH3_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
12390 #define GIS_CH3_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
12391 #define GIS_CH3_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
12392 /* CH3_ADDR2_TOG Bit Fields */
12393 #define GIS_CH3_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
12394 #define GIS_CH3_ADDR2_TOG_ADDR_SHIFT             0
12395 #define GIS_CH3_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_TOG_ADDR_SHIFT))&GIS_CH3_ADDR2_TOG_ADDR_MASK)
12396 #define GIS_CH3_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
12397 #define GIS_CH3_ADDR2_TOG_CSI0_SEL_SHIFT         27
12398 #define GIS_CH3_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
12399 #define GIS_CH3_ADDR2_TOG_CSI1_SEL_SHIFT         28
12400 #define GIS_CH3_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
12401 #define GIS_CH3_ADDR2_TOG_PXP_SEL_SHIFT          29
12402 #define GIS_CH3_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
12403 #define GIS_CH3_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
12404 #define GIS_CH3_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
12405 #define GIS_CH3_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
12406 /* CH3_DATA2 Bit Fields */
12407 #define GIS_CH3_DATA2_DATA_MASK                  0xFFFFFFFFu
12408 #define GIS_CH3_DATA2_DATA_SHIFT                 0
12409 #define GIS_CH3_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA2_DATA_SHIFT))&GIS_CH3_DATA2_DATA_MASK)
12410 /* CH3_ADDR3 Bit Fields */
12411 #define GIS_CH3_ADDR3_ADDR_MASK                  0x7FFFFFFu
12412 #define GIS_CH3_ADDR3_ADDR_SHIFT                 0
12413 #define GIS_CH3_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_ADDR_SHIFT))&GIS_CH3_ADDR3_ADDR_MASK)
12414 #define GIS_CH3_ADDR3_CSI0_SEL_MASK              0x8000000u
12415 #define GIS_CH3_ADDR3_CSI0_SEL_SHIFT             27
12416 #define GIS_CH3_ADDR3_CSI1_SEL_MASK              0x10000000u
12417 #define GIS_CH3_ADDR3_CSI1_SEL_SHIFT             28
12418 #define GIS_CH3_ADDR3_PXP_SEL_MASK               0x20000000u
12419 #define GIS_CH3_ADDR3_PXP_SEL_SHIFT              29
12420 #define GIS_CH3_ADDR3_LCDIF0_SEL_MASK            0x40000000u
12421 #define GIS_CH3_ADDR3_LCDIF0_SEL_SHIFT           30
12422 #define GIS_CH3_ADDR3_LCDIF1_SEL_MASK            0x80000000u
12423 #define GIS_CH3_ADDR3_LCDIF1_SEL_SHIFT           31
12424 /* CH3_ADDR3_SET Bit Fields */
12425 #define GIS_CH3_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
12426 #define GIS_CH3_ADDR3_SET_ADDR_SHIFT             0
12427 #define GIS_CH3_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_SET_ADDR_SHIFT))&GIS_CH3_ADDR3_SET_ADDR_MASK)
12428 #define GIS_CH3_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
12429 #define GIS_CH3_ADDR3_SET_CSI0_SEL_SHIFT         27
12430 #define GIS_CH3_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
12431 #define GIS_CH3_ADDR3_SET_CSI1_SEL_SHIFT         28
12432 #define GIS_CH3_ADDR3_SET_PXP_SEL_MASK           0x20000000u
12433 #define GIS_CH3_ADDR3_SET_PXP_SEL_SHIFT          29
12434 #define GIS_CH3_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
12435 #define GIS_CH3_ADDR3_SET_LCDIF0_SEL_SHIFT       30
12436 #define GIS_CH3_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
12437 #define GIS_CH3_ADDR3_SET_LCDIF1_SEL_SHIFT       31
12438 /* CH3_ADDR3_CLR Bit Fields */
12439 #define GIS_CH3_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
12440 #define GIS_CH3_ADDR3_CLR_ADDR_SHIFT             0
12441 #define GIS_CH3_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_CLR_ADDR_SHIFT))&GIS_CH3_ADDR3_CLR_ADDR_MASK)
12442 #define GIS_CH3_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
12443 #define GIS_CH3_ADDR3_CLR_CSI0_SEL_SHIFT         27
12444 #define GIS_CH3_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
12445 #define GIS_CH3_ADDR3_CLR_CSI1_SEL_SHIFT         28
12446 #define GIS_CH3_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
12447 #define GIS_CH3_ADDR3_CLR_PXP_SEL_SHIFT          29
12448 #define GIS_CH3_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
12449 #define GIS_CH3_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
12450 #define GIS_CH3_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
12451 #define GIS_CH3_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
12452 /* CH3_ADDR3_TOG Bit Fields */
12453 #define GIS_CH3_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
12454 #define GIS_CH3_ADDR3_TOG_ADDR_SHIFT             0
12455 #define GIS_CH3_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_TOG_ADDR_SHIFT))&GIS_CH3_ADDR3_TOG_ADDR_MASK)
12456 #define GIS_CH3_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
12457 #define GIS_CH3_ADDR3_TOG_CSI0_SEL_SHIFT         27
12458 #define GIS_CH3_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
12459 #define GIS_CH3_ADDR3_TOG_CSI1_SEL_SHIFT         28
12460 #define GIS_CH3_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
12461 #define GIS_CH3_ADDR3_TOG_PXP_SEL_SHIFT          29
12462 #define GIS_CH3_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
12463 #define GIS_CH3_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
12464 #define GIS_CH3_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
12465 #define GIS_CH3_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
12466 /* CH3_DATA3 Bit Fields */
12467 #define GIS_CH3_DATA3_DATA_MASK                  0xFFFFFFFFu
12468 #define GIS_CH3_DATA3_DATA_SHIFT                 0
12469 #define GIS_CH3_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA3_DATA_SHIFT))&GIS_CH3_DATA3_DATA_MASK)
12470 /* CH4_CTRL Bit Fields */
12471 #define GIS_CH4_CTRL_CMD0_OPCODE_MASK            0xFu
12472 #define GIS_CH4_CTRL_CMD0_OPCODE_SHIFT           0
12473 #define GIS_CH4_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD0_OPCODE_MASK)
12474 #define GIS_CH4_CTRL_CMD0_ALU_MASK               0x70u
12475 #define GIS_CH4_CTRL_CMD0_ALU_SHIFT              4
12476 #define GIS_CH4_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_CMD0_ALU_MASK)
12477 #define GIS_CH4_CTRL_CMD0_ACC_NEG_MASK           0x80u
12478 #define GIS_CH4_CTRL_CMD0_ACC_NEG_SHIFT          7
12479 #define GIS_CH4_CTRL_CMD1_OPCODE_MASK            0xF00u
12480 #define GIS_CH4_CTRL_CMD1_OPCODE_SHIFT           8
12481 #define GIS_CH4_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD1_OPCODE_MASK)
12482 #define GIS_CH4_CTRL_CMD1_ALU_MASK               0x7000u
12483 #define GIS_CH4_CTRL_CMD1_ALU_SHIFT              12
12484 #define GIS_CH4_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_CMD1_ALU_MASK)
12485 #define GIS_CH4_CTRL_CMD1_ACC_NEG_MASK           0x8000u
12486 #define GIS_CH4_CTRL_CMD1_ACC_NEG_SHIFT          15
12487 #define GIS_CH4_CTRL_CMD2_OPCODE_MASK            0xF0000u
12488 #define GIS_CH4_CTRL_CMD2_OPCODE_SHIFT           16
12489 #define GIS_CH4_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD2_OPCODE_MASK)
12490 #define GIS_CH4_CTRL_CMD2_ALU_MASK               0x700000u
12491 #define GIS_CH4_CTRL_CMD2_ALU_SHIFT              20
12492 #define GIS_CH4_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_CMD2_ALU_MASK)
12493 #define GIS_CH4_CTRL_CMD2_ACC_NEG_MASK           0x800000u
12494 #define GIS_CH4_CTRL_CMD2_ACC_NEG_SHIFT          23
12495 #define GIS_CH4_CTRL_CMD3_OPCODE_MASK            0xF000000u
12496 #define GIS_CH4_CTRL_CMD3_OPCODE_SHIFT           24
12497 #define GIS_CH4_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD3_OPCODE_MASK)
12498 #define GIS_CH4_CTRL_CMD3_ALU_MASK               0x70000000u
12499 #define GIS_CH4_CTRL_CMD3_ALU_SHIFT              28
12500 #define GIS_CH4_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_CMD3_ALU_MASK)
12501 #define GIS_CH4_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
12502 #define GIS_CH4_CTRL_CMD3_ACC_NEG_SHIFT          31
12503 /* CH4_CTRL_SET Bit Fields */
12504 #define GIS_CH4_CTRL_SET_CMD0_OPCODE_MASK        0xFu
12505 #define GIS_CH4_CTRL_SET_CMD0_OPCODE_SHIFT       0
12506 #define GIS_CH4_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD0_OPCODE_MASK)
12507 #define GIS_CH4_CTRL_SET_CMD0_ALU_MASK           0x70u
12508 #define GIS_CH4_CTRL_SET_CMD0_ALU_SHIFT          4
12509 #define GIS_CH4_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD0_ALU_MASK)
12510 #define GIS_CH4_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
12511 #define GIS_CH4_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
12512 #define GIS_CH4_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
12513 #define GIS_CH4_CTRL_SET_CMD1_OPCODE_SHIFT       8
12514 #define GIS_CH4_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD1_OPCODE_MASK)
12515 #define GIS_CH4_CTRL_SET_CMD1_ALU_MASK           0x7000u
12516 #define GIS_CH4_CTRL_SET_CMD1_ALU_SHIFT          12
12517 #define GIS_CH4_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD1_ALU_MASK)
12518 #define GIS_CH4_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
12519 #define GIS_CH4_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
12520 #define GIS_CH4_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
12521 #define GIS_CH4_CTRL_SET_CMD2_OPCODE_SHIFT       16
12522 #define GIS_CH4_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD2_OPCODE_MASK)
12523 #define GIS_CH4_CTRL_SET_CMD2_ALU_MASK           0x700000u
12524 #define GIS_CH4_CTRL_SET_CMD2_ALU_SHIFT          20
12525 #define GIS_CH4_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD2_ALU_MASK)
12526 #define GIS_CH4_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
12527 #define GIS_CH4_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
12528 #define GIS_CH4_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
12529 #define GIS_CH4_CTRL_SET_CMD3_OPCODE_SHIFT       24
12530 #define GIS_CH4_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD3_OPCODE_MASK)
12531 #define GIS_CH4_CTRL_SET_CMD3_ALU_MASK           0x70000000u
12532 #define GIS_CH4_CTRL_SET_CMD3_ALU_SHIFT          28
12533 #define GIS_CH4_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD3_ALU_MASK)
12534 #define GIS_CH4_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
12535 #define GIS_CH4_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
12536 /* CH4_CTRL_CLR Bit Fields */
12537 #define GIS_CH4_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
12538 #define GIS_CH4_CTRL_CLR_CMD0_OPCODE_SHIFT       0
12539 #define GIS_CH4_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD0_OPCODE_MASK)
12540 #define GIS_CH4_CTRL_CLR_CMD0_ALU_MASK           0x70u
12541 #define GIS_CH4_CTRL_CLR_CMD0_ALU_SHIFT          4
12542 #define GIS_CH4_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD0_ALU_MASK)
12543 #define GIS_CH4_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
12544 #define GIS_CH4_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
12545 #define GIS_CH4_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
12546 #define GIS_CH4_CTRL_CLR_CMD1_OPCODE_SHIFT       8
12547 #define GIS_CH4_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD1_OPCODE_MASK)
12548 #define GIS_CH4_CTRL_CLR_CMD1_ALU_MASK           0x7000u
12549 #define GIS_CH4_CTRL_CLR_CMD1_ALU_SHIFT          12
12550 #define GIS_CH4_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD1_ALU_MASK)
12551 #define GIS_CH4_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
12552 #define GIS_CH4_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
12553 #define GIS_CH4_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
12554 #define GIS_CH4_CTRL_CLR_CMD2_OPCODE_SHIFT       16
12555 #define GIS_CH4_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD2_OPCODE_MASK)
12556 #define GIS_CH4_CTRL_CLR_CMD2_ALU_MASK           0x700000u
12557 #define GIS_CH4_CTRL_CLR_CMD2_ALU_SHIFT          20
12558 #define GIS_CH4_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD2_ALU_MASK)
12559 #define GIS_CH4_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
12560 #define GIS_CH4_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
12561 #define GIS_CH4_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
12562 #define GIS_CH4_CTRL_CLR_CMD3_OPCODE_SHIFT       24
12563 #define GIS_CH4_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD3_OPCODE_MASK)
12564 #define GIS_CH4_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
12565 #define GIS_CH4_CTRL_CLR_CMD3_ALU_SHIFT          28
12566 #define GIS_CH4_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD3_ALU_MASK)
12567 #define GIS_CH4_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
12568 #define GIS_CH4_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
12569 /* CH4_CTRL_TOG Bit Fields */
12570 #define GIS_CH4_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
12571 #define GIS_CH4_CTRL_TOG_CMD0_OPCODE_SHIFT       0
12572 #define GIS_CH4_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD0_OPCODE_MASK)
12573 #define GIS_CH4_CTRL_TOG_CMD0_ALU_MASK           0x70u
12574 #define GIS_CH4_CTRL_TOG_CMD0_ALU_SHIFT          4
12575 #define GIS_CH4_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD0_ALU_MASK)
12576 #define GIS_CH4_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
12577 #define GIS_CH4_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
12578 #define GIS_CH4_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
12579 #define GIS_CH4_CTRL_TOG_CMD1_OPCODE_SHIFT       8
12580 #define GIS_CH4_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD1_OPCODE_MASK)
12581 #define GIS_CH4_CTRL_TOG_CMD1_ALU_MASK           0x7000u
12582 #define GIS_CH4_CTRL_TOG_CMD1_ALU_SHIFT          12
12583 #define GIS_CH4_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD1_ALU_MASK)
12584 #define GIS_CH4_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
12585 #define GIS_CH4_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
12586 #define GIS_CH4_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
12587 #define GIS_CH4_CTRL_TOG_CMD2_OPCODE_SHIFT       16
12588 #define GIS_CH4_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD2_OPCODE_MASK)
12589 #define GIS_CH4_CTRL_TOG_CMD2_ALU_MASK           0x700000u
12590 #define GIS_CH4_CTRL_TOG_CMD2_ALU_SHIFT          20
12591 #define GIS_CH4_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD2_ALU_MASK)
12592 #define GIS_CH4_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
12593 #define GIS_CH4_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
12594 #define GIS_CH4_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
12595 #define GIS_CH4_CTRL_TOG_CMD3_OPCODE_SHIFT       24
12596 #define GIS_CH4_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD3_OPCODE_MASK)
12597 #define GIS_CH4_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
12598 #define GIS_CH4_CTRL_TOG_CMD3_ALU_SHIFT          28
12599 #define GIS_CH4_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD3_ALU_MASK)
12600 #define GIS_CH4_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
12601 #define GIS_CH4_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
12602 /* CH4_ADDR0 Bit Fields */
12603 #define GIS_CH4_ADDR0_ADDR_MASK                  0x7FFFFFFu
12604 #define GIS_CH4_ADDR0_ADDR_SHIFT                 0
12605 #define GIS_CH4_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_ADDR_SHIFT))&GIS_CH4_ADDR0_ADDR_MASK)
12606 #define GIS_CH4_ADDR0_CSI0_SEL_MASK              0x8000000u
12607 #define GIS_CH4_ADDR0_CSI0_SEL_SHIFT             27
12608 #define GIS_CH4_ADDR0_CSI1_SEL_MASK              0x10000000u
12609 #define GIS_CH4_ADDR0_CSI1_SEL_SHIFT             28
12610 #define GIS_CH4_ADDR0_PXP_SEL_MASK               0x20000000u
12611 #define GIS_CH4_ADDR0_PXP_SEL_SHIFT              29
12612 #define GIS_CH4_ADDR0_LCDIF0_SEL_MASK            0x40000000u
12613 #define GIS_CH4_ADDR0_LCDIF0_SEL_SHIFT           30
12614 #define GIS_CH4_ADDR0_LCDIF1_SEL_MASK            0x80000000u
12615 #define GIS_CH4_ADDR0_LCDIF1_SEL_SHIFT           31
12616 /* CH4_ADDR0_SET Bit Fields */
12617 #define GIS_CH4_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
12618 #define GIS_CH4_ADDR0_SET_ADDR_SHIFT             0
12619 #define GIS_CH4_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_SET_ADDR_SHIFT))&GIS_CH4_ADDR0_SET_ADDR_MASK)
12620 #define GIS_CH4_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
12621 #define GIS_CH4_ADDR0_SET_CSI0_SEL_SHIFT         27
12622 #define GIS_CH4_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
12623 #define GIS_CH4_ADDR0_SET_CSI1_SEL_SHIFT         28
12624 #define GIS_CH4_ADDR0_SET_PXP_SEL_MASK           0x20000000u
12625 #define GIS_CH4_ADDR0_SET_PXP_SEL_SHIFT          29
12626 #define GIS_CH4_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
12627 #define GIS_CH4_ADDR0_SET_LCDIF0_SEL_SHIFT       30
12628 #define GIS_CH4_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
12629 #define GIS_CH4_ADDR0_SET_LCDIF1_SEL_SHIFT       31
12630 /* CH4_ADDR0_CLR Bit Fields */
12631 #define GIS_CH4_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
12632 #define GIS_CH4_ADDR0_CLR_ADDR_SHIFT             0
12633 #define GIS_CH4_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_CLR_ADDR_SHIFT))&GIS_CH4_ADDR0_CLR_ADDR_MASK)
12634 #define GIS_CH4_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
12635 #define GIS_CH4_ADDR0_CLR_CSI0_SEL_SHIFT         27
12636 #define GIS_CH4_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
12637 #define GIS_CH4_ADDR0_CLR_CSI1_SEL_SHIFT         28
12638 #define GIS_CH4_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
12639 #define GIS_CH4_ADDR0_CLR_PXP_SEL_SHIFT          29
12640 #define GIS_CH4_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
12641 #define GIS_CH4_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
12642 #define GIS_CH4_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
12643 #define GIS_CH4_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
12644 /* CH4_ADDR0_TOG Bit Fields */
12645 #define GIS_CH4_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
12646 #define GIS_CH4_ADDR0_TOG_ADDR_SHIFT             0
12647 #define GIS_CH4_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_TOG_ADDR_SHIFT))&GIS_CH4_ADDR0_TOG_ADDR_MASK)
12648 #define GIS_CH4_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
12649 #define GIS_CH4_ADDR0_TOG_CSI0_SEL_SHIFT         27
12650 #define GIS_CH4_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
12651 #define GIS_CH4_ADDR0_TOG_CSI1_SEL_SHIFT         28
12652 #define GIS_CH4_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
12653 #define GIS_CH4_ADDR0_TOG_PXP_SEL_SHIFT          29
12654 #define GIS_CH4_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
12655 #define GIS_CH4_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
12656 #define GIS_CH4_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
12657 #define GIS_CH4_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
12658 /* CH4_DATA0 Bit Fields */
12659 #define GIS_CH4_DATA0_DATA_MASK                  0xFFFFFFFFu
12660 #define GIS_CH4_DATA0_DATA_SHIFT                 0
12661 #define GIS_CH4_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA0_DATA_SHIFT))&GIS_CH4_DATA0_DATA_MASK)
12662 /* CH4_ADDR1 Bit Fields */
12663 #define GIS_CH4_ADDR1_ADDR_MASK                  0x7FFFFFFu
12664 #define GIS_CH4_ADDR1_ADDR_SHIFT                 0
12665 #define GIS_CH4_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_ADDR_SHIFT))&GIS_CH4_ADDR1_ADDR_MASK)
12666 #define GIS_CH4_ADDR1_CSI0_SEL_MASK              0x8000000u
12667 #define GIS_CH4_ADDR1_CSI0_SEL_SHIFT             27
12668 #define GIS_CH4_ADDR1_CSI1_SEL_MASK              0x10000000u
12669 #define GIS_CH4_ADDR1_CSI1_SEL_SHIFT             28
12670 #define GIS_CH4_ADDR1_PXP_SEL_MASK               0x20000000u
12671 #define GIS_CH4_ADDR1_PXP_SEL_SHIFT              29
12672 #define GIS_CH4_ADDR1_LCDIF0_SEL_MASK            0x40000000u
12673 #define GIS_CH4_ADDR1_LCDIF0_SEL_SHIFT           30
12674 #define GIS_CH4_ADDR1_LCDIF1_SEL_MASK            0x80000000u
12675 #define GIS_CH4_ADDR1_LCDIF1_SEL_SHIFT           31
12676 /* CH4_ADDR1_SET Bit Fields */
12677 #define GIS_CH4_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
12678 #define GIS_CH4_ADDR1_SET_ADDR_SHIFT             0
12679 #define GIS_CH4_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_SET_ADDR_SHIFT))&GIS_CH4_ADDR1_SET_ADDR_MASK)
12680 #define GIS_CH4_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
12681 #define GIS_CH4_ADDR1_SET_CSI0_SEL_SHIFT         27
12682 #define GIS_CH4_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
12683 #define GIS_CH4_ADDR1_SET_CSI1_SEL_SHIFT         28
12684 #define GIS_CH4_ADDR1_SET_PXP_SEL_MASK           0x20000000u
12685 #define GIS_CH4_ADDR1_SET_PXP_SEL_SHIFT          29
12686 #define GIS_CH4_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
12687 #define GIS_CH4_ADDR1_SET_LCDIF0_SEL_SHIFT       30
12688 #define GIS_CH4_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
12689 #define GIS_CH4_ADDR1_SET_LCDIF1_SEL_SHIFT       31
12690 /* CH4_ADDR1_CLR Bit Fields */
12691 #define GIS_CH4_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
12692 #define GIS_CH4_ADDR1_CLR_ADDR_SHIFT             0
12693 #define GIS_CH4_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_CLR_ADDR_SHIFT))&GIS_CH4_ADDR1_CLR_ADDR_MASK)
12694 #define GIS_CH4_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
12695 #define GIS_CH4_ADDR1_CLR_CSI0_SEL_SHIFT         27
12696 #define GIS_CH4_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
12697 #define GIS_CH4_ADDR1_CLR_CSI1_SEL_SHIFT         28
12698 #define GIS_CH4_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
12699 #define GIS_CH4_ADDR1_CLR_PXP_SEL_SHIFT          29
12700 #define GIS_CH4_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
12701 #define GIS_CH4_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
12702 #define GIS_CH4_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
12703 #define GIS_CH4_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
12704 /* CH4_ADDR1_TOG Bit Fields */
12705 #define GIS_CH4_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
12706 #define GIS_CH4_ADDR1_TOG_ADDR_SHIFT             0
12707 #define GIS_CH4_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_TOG_ADDR_SHIFT))&GIS_CH4_ADDR1_TOG_ADDR_MASK)
12708 #define GIS_CH4_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
12709 #define GIS_CH4_ADDR1_TOG_CSI0_SEL_SHIFT         27
12710 #define GIS_CH4_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
12711 #define GIS_CH4_ADDR1_TOG_CSI1_SEL_SHIFT         28
12712 #define GIS_CH4_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
12713 #define GIS_CH4_ADDR1_TOG_PXP_SEL_SHIFT          29
12714 #define GIS_CH4_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
12715 #define GIS_CH4_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
12716 #define GIS_CH4_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
12717 #define GIS_CH4_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
12718 /* CH4_DATA1 Bit Fields */
12719 #define GIS_CH4_DATA1_DATA_MASK                  0xFFFFFFFFu
12720 #define GIS_CH4_DATA1_DATA_SHIFT                 0
12721 #define GIS_CH4_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA1_DATA_SHIFT))&GIS_CH4_DATA1_DATA_MASK)
12722 /* CH4_ADDR2 Bit Fields */
12723 #define GIS_CH4_ADDR2_ADDR_MASK                  0x7FFFFFFu
12724 #define GIS_CH4_ADDR2_ADDR_SHIFT                 0
12725 #define GIS_CH4_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_ADDR_SHIFT))&GIS_CH4_ADDR2_ADDR_MASK)
12726 #define GIS_CH4_ADDR2_CSI0_SEL_MASK              0x8000000u
12727 #define GIS_CH4_ADDR2_CSI0_SEL_SHIFT             27
12728 #define GIS_CH4_ADDR2_CSI1_SEL_MASK              0x10000000u
12729 #define GIS_CH4_ADDR2_CSI1_SEL_SHIFT             28
12730 #define GIS_CH4_ADDR2_PXP_SEL_MASK               0x20000000u
12731 #define GIS_CH4_ADDR2_PXP_SEL_SHIFT              29
12732 #define GIS_CH4_ADDR2_LCDIF0_SEL_MASK            0x40000000u
12733 #define GIS_CH4_ADDR2_LCDIF0_SEL_SHIFT           30
12734 #define GIS_CH4_ADDR2_LCDIF1_SEL_MASK            0x80000000u
12735 #define GIS_CH4_ADDR2_LCDIF1_SEL_SHIFT           31
12736 /* CH4_ADDR2_SET Bit Fields */
12737 #define GIS_CH4_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
12738 #define GIS_CH4_ADDR2_SET_ADDR_SHIFT             0
12739 #define GIS_CH4_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_SET_ADDR_SHIFT))&GIS_CH4_ADDR2_SET_ADDR_MASK)
12740 #define GIS_CH4_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
12741 #define GIS_CH4_ADDR2_SET_CSI0_SEL_SHIFT         27
12742 #define GIS_CH4_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
12743 #define GIS_CH4_ADDR2_SET_CSI1_SEL_SHIFT         28
12744 #define GIS_CH4_ADDR2_SET_PXP_SEL_MASK           0x20000000u
12745 #define GIS_CH4_ADDR2_SET_PXP_SEL_SHIFT          29
12746 #define GIS_CH4_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
12747 #define GIS_CH4_ADDR2_SET_LCDIF0_SEL_SHIFT       30
12748 #define GIS_CH4_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
12749 #define GIS_CH4_ADDR2_SET_LCDIF1_SEL_SHIFT       31
12750 /* CH4_ADDR2_CLR Bit Fields */
12751 #define GIS_CH4_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
12752 #define GIS_CH4_ADDR2_CLR_ADDR_SHIFT             0
12753 #define GIS_CH4_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_CLR_ADDR_SHIFT))&GIS_CH4_ADDR2_CLR_ADDR_MASK)
12754 #define GIS_CH4_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
12755 #define GIS_CH4_ADDR2_CLR_CSI0_SEL_SHIFT         27
12756 #define GIS_CH4_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
12757 #define GIS_CH4_ADDR2_CLR_CSI1_SEL_SHIFT         28
12758 #define GIS_CH4_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
12759 #define GIS_CH4_ADDR2_CLR_PXP_SEL_SHIFT          29
12760 #define GIS_CH4_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
12761 #define GIS_CH4_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
12762 #define GIS_CH4_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
12763 #define GIS_CH4_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
12764 /* CH4_ADDR2_TOG Bit Fields */
12765 #define GIS_CH4_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
12766 #define GIS_CH4_ADDR2_TOG_ADDR_SHIFT             0
12767 #define GIS_CH4_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_TOG_ADDR_SHIFT))&GIS_CH4_ADDR2_TOG_ADDR_MASK)
12768 #define GIS_CH4_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
12769 #define GIS_CH4_ADDR2_TOG_CSI0_SEL_SHIFT         27
12770 #define GIS_CH4_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
12771 #define GIS_CH4_ADDR2_TOG_CSI1_SEL_SHIFT         28
12772 #define GIS_CH4_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
12773 #define GIS_CH4_ADDR2_TOG_PXP_SEL_SHIFT          29
12774 #define GIS_CH4_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
12775 #define GIS_CH4_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
12776 #define GIS_CH4_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
12777 #define GIS_CH4_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
12778 /* CH4_DATA2 Bit Fields */
12779 #define GIS_CH4_DATA2_DATA_MASK                  0xFFFFFFFFu
12780 #define GIS_CH4_DATA2_DATA_SHIFT                 0
12781 #define GIS_CH4_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA2_DATA_SHIFT))&GIS_CH4_DATA2_DATA_MASK)
12782 /* CH4_ADDR3 Bit Fields */
12783 #define GIS_CH4_ADDR3_ADDR_MASK                  0x7FFFFFFu
12784 #define GIS_CH4_ADDR3_ADDR_SHIFT                 0
12785 #define GIS_CH4_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_ADDR_SHIFT))&GIS_CH4_ADDR3_ADDR_MASK)
12786 #define GIS_CH4_ADDR3_CSI0_SEL_MASK              0x8000000u
12787 #define GIS_CH4_ADDR3_CSI0_SEL_SHIFT             27
12788 #define GIS_CH4_ADDR3_CSI1_SEL_MASK              0x10000000u
12789 #define GIS_CH4_ADDR3_CSI1_SEL_SHIFT             28
12790 #define GIS_CH4_ADDR3_PXP_SEL_MASK               0x20000000u
12791 #define GIS_CH4_ADDR3_PXP_SEL_SHIFT              29
12792 #define GIS_CH4_ADDR3_LCDIF0_SEL_MASK            0x40000000u
12793 #define GIS_CH4_ADDR3_LCDIF0_SEL_SHIFT           30
12794 #define GIS_CH4_ADDR3_LCDIF1_SEL_MASK            0x80000000u
12795 #define GIS_CH4_ADDR3_LCDIF1_SEL_SHIFT           31
12796 /* CH4_ADDR3_SET Bit Fields */
12797 #define GIS_CH4_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
12798 #define GIS_CH4_ADDR3_SET_ADDR_SHIFT             0
12799 #define GIS_CH4_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_SET_ADDR_SHIFT))&GIS_CH4_ADDR3_SET_ADDR_MASK)
12800 #define GIS_CH4_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
12801 #define GIS_CH4_ADDR3_SET_CSI0_SEL_SHIFT         27
12802 #define GIS_CH4_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
12803 #define GIS_CH4_ADDR3_SET_CSI1_SEL_SHIFT         28
12804 #define GIS_CH4_ADDR3_SET_PXP_SEL_MASK           0x20000000u
12805 #define GIS_CH4_ADDR3_SET_PXP_SEL_SHIFT          29
12806 #define GIS_CH4_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
12807 #define GIS_CH4_ADDR3_SET_LCDIF0_SEL_SHIFT       30
12808 #define GIS_CH4_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
12809 #define GIS_CH4_ADDR3_SET_LCDIF1_SEL_SHIFT       31
12810 /* CH4_ADDR3_CLR Bit Fields */
12811 #define GIS_CH4_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
12812 #define GIS_CH4_ADDR3_CLR_ADDR_SHIFT             0
12813 #define GIS_CH4_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_CLR_ADDR_SHIFT))&GIS_CH4_ADDR3_CLR_ADDR_MASK)
12814 #define GIS_CH4_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
12815 #define GIS_CH4_ADDR3_CLR_CSI0_SEL_SHIFT         27
12816 #define GIS_CH4_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
12817 #define GIS_CH4_ADDR3_CLR_CSI1_SEL_SHIFT         28
12818 #define GIS_CH4_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
12819 #define GIS_CH4_ADDR3_CLR_PXP_SEL_SHIFT          29
12820 #define GIS_CH4_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
12821 #define GIS_CH4_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
12822 #define GIS_CH4_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
12823 #define GIS_CH4_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
12824 /* CH4_ADDR3_TOG Bit Fields */
12825 #define GIS_CH4_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
12826 #define GIS_CH4_ADDR3_TOG_ADDR_SHIFT             0
12827 #define GIS_CH4_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_TOG_ADDR_SHIFT))&GIS_CH4_ADDR3_TOG_ADDR_MASK)
12828 #define GIS_CH4_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
12829 #define GIS_CH4_ADDR3_TOG_CSI0_SEL_SHIFT         27
12830 #define GIS_CH4_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
12831 #define GIS_CH4_ADDR3_TOG_CSI1_SEL_SHIFT         28
12832 #define GIS_CH4_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
12833 #define GIS_CH4_ADDR3_TOG_PXP_SEL_SHIFT          29
12834 #define GIS_CH4_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
12835 #define GIS_CH4_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
12836 #define GIS_CH4_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
12837 #define GIS_CH4_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
12838 /* CH4_DATA3 Bit Fields */
12839 #define GIS_CH4_DATA3_DATA_MASK                  0xFFFFFFFFu
12840 #define GIS_CH4_DATA3_DATA_SHIFT                 0
12841 #define GIS_CH4_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA3_DATA_SHIFT))&GIS_CH4_DATA3_DATA_MASK)
12842 /* CH5_CTRL Bit Fields */
12843 #define GIS_CH5_CTRL_CMD0_OPCODE_MASK            0xFu
12844 #define GIS_CH5_CTRL_CMD0_OPCODE_SHIFT           0
12845 #define GIS_CH5_CTRL_CMD0_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD0_OPCODE_MASK)
12846 #define GIS_CH5_CTRL_CMD0_ALU_MASK               0x70u
12847 #define GIS_CH5_CTRL_CMD0_ALU_SHIFT              4
12848 #define GIS_CH5_CTRL_CMD0_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_CMD0_ALU_MASK)
12849 #define GIS_CH5_CTRL_CMD0_ACC_NEG_MASK           0x80u
12850 #define GIS_CH5_CTRL_CMD0_ACC_NEG_SHIFT          7
12851 #define GIS_CH5_CTRL_CMD1_OPCODE_MASK            0xF00u
12852 #define GIS_CH5_CTRL_CMD1_OPCODE_SHIFT           8
12853 #define GIS_CH5_CTRL_CMD1_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD1_OPCODE_MASK)
12854 #define GIS_CH5_CTRL_CMD1_ALU_MASK               0x7000u
12855 #define GIS_CH5_CTRL_CMD1_ALU_SHIFT              12
12856 #define GIS_CH5_CTRL_CMD1_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_CMD1_ALU_MASK)
12857 #define GIS_CH5_CTRL_CMD1_ACC_NEG_MASK           0x8000u
12858 #define GIS_CH5_CTRL_CMD1_ACC_NEG_SHIFT          15
12859 #define GIS_CH5_CTRL_CMD2_OPCODE_MASK            0xF0000u
12860 #define GIS_CH5_CTRL_CMD2_OPCODE_SHIFT           16
12861 #define GIS_CH5_CTRL_CMD2_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD2_OPCODE_MASK)
12862 #define GIS_CH5_CTRL_CMD2_ALU_MASK               0x700000u
12863 #define GIS_CH5_CTRL_CMD2_ALU_SHIFT              20
12864 #define GIS_CH5_CTRL_CMD2_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_CMD2_ALU_MASK)
12865 #define GIS_CH5_CTRL_CMD2_ACC_NEG_MASK           0x800000u
12866 #define GIS_CH5_CTRL_CMD2_ACC_NEG_SHIFT          23
12867 #define GIS_CH5_CTRL_CMD3_OPCODE_MASK            0xF000000u
12868 #define GIS_CH5_CTRL_CMD3_OPCODE_SHIFT           24
12869 #define GIS_CH5_CTRL_CMD3_OPCODE(x)              (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD3_OPCODE_MASK)
12870 #define GIS_CH5_CTRL_CMD3_ALU_MASK               0x70000000u
12871 #define GIS_CH5_CTRL_CMD3_ALU_SHIFT              28
12872 #define GIS_CH5_CTRL_CMD3_ALU(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_CMD3_ALU_MASK)
12873 #define GIS_CH5_CTRL_CMD3_ACC_NEG_MASK           0x80000000u
12874 #define GIS_CH5_CTRL_CMD3_ACC_NEG_SHIFT          31
12875 /* CH5_CTRL_SET Bit Fields */
12876 #define GIS_CH5_CTRL_SET_CMD0_OPCODE_MASK        0xFu
12877 #define GIS_CH5_CTRL_SET_CMD0_OPCODE_SHIFT       0
12878 #define GIS_CH5_CTRL_SET_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD0_OPCODE_MASK)
12879 #define GIS_CH5_CTRL_SET_CMD0_ALU_MASK           0x70u
12880 #define GIS_CH5_CTRL_SET_CMD0_ALU_SHIFT          4
12881 #define GIS_CH5_CTRL_SET_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD0_ALU_MASK)
12882 #define GIS_CH5_CTRL_SET_CMD0_ACC_NEG_MASK       0x80u
12883 #define GIS_CH5_CTRL_SET_CMD0_ACC_NEG_SHIFT      7
12884 #define GIS_CH5_CTRL_SET_CMD1_OPCODE_MASK        0xF00u
12885 #define GIS_CH5_CTRL_SET_CMD1_OPCODE_SHIFT       8
12886 #define GIS_CH5_CTRL_SET_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD1_OPCODE_MASK)
12887 #define GIS_CH5_CTRL_SET_CMD1_ALU_MASK           0x7000u
12888 #define GIS_CH5_CTRL_SET_CMD1_ALU_SHIFT          12
12889 #define GIS_CH5_CTRL_SET_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD1_ALU_MASK)
12890 #define GIS_CH5_CTRL_SET_CMD1_ACC_NEG_MASK       0x8000u
12891 #define GIS_CH5_CTRL_SET_CMD1_ACC_NEG_SHIFT      15
12892 #define GIS_CH5_CTRL_SET_CMD2_OPCODE_MASK        0xF0000u
12893 #define GIS_CH5_CTRL_SET_CMD2_OPCODE_SHIFT       16
12894 #define GIS_CH5_CTRL_SET_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD2_OPCODE_MASK)
12895 #define GIS_CH5_CTRL_SET_CMD2_ALU_MASK           0x700000u
12896 #define GIS_CH5_CTRL_SET_CMD2_ALU_SHIFT          20
12897 #define GIS_CH5_CTRL_SET_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD2_ALU_MASK)
12898 #define GIS_CH5_CTRL_SET_CMD2_ACC_NEG_MASK       0x800000u
12899 #define GIS_CH5_CTRL_SET_CMD2_ACC_NEG_SHIFT      23
12900 #define GIS_CH5_CTRL_SET_CMD3_OPCODE_MASK        0xF000000u
12901 #define GIS_CH5_CTRL_SET_CMD3_OPCODE_SHIFT       24
12902 #define GIS_CH5_CTRL_SET_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD3_OPCODE_MASK)
12903 #define GIS_CH5_CTRL_SET_CMD3_ALU_MASK           0x70000000u
12904 #define GIS_CH5_CTRL_SET_CMD3_ALU_SHIFT          28
12905 #define GIS_CH5_CTRL_SET_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD3_ALU_MASK)
12906 #define GIS_CH5_CTRL_SET_CMD3_ACC_NEG_MASK       0x80000000u
12907 #define GIS_CH5_CTRL_SET_CMD3_ACC_NEG_SHIFT      31
12908 /* CH5_CTRL_CLR Bit Fields */
12909 #define GIS_CH5_CTRL_CLR_CMD0_OPCODE_MASK        0xFu
12910 #define GIS_CH5_CTRL_CLR_CMD0_OPCODE_SHIFT       0
12911 #define GIS_CH5_CTRL_CLR_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD0_OPCODE_MASK)
12912 #define GIS_CH5_CTRL_CLR_CMD0_ALU_MASK           0x70u
12913 #define GIS_CH5_CTRL_CLR_CMD0_ALU_SHIFT          4
12914 #define GIS_CH5_CTRL_CLR_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD0_ALU_MASK)
12915 #define GIS_CH5_CTRL_CLR_CMD0_ACC_NEG_MASK       0x80u
12916 #define GIS_CH5_CTRL_CLR_CMD0_ACC_NEG_SHIFT      7
12917 #define GIS_CH5_CTRL_CLR_CMD1_OPCODE_MASK        0xF00u
12918 #define GIS_CH5_CTRL_CLR_CMD1_OPCODE_SHIFT       8
12919 #define GIS_CH5_CTRL_CLR_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD1_OPCODE_MASK)
12920 #define GIS_CH5_CTRL_CLR_CMD1_ALU_MASK           0x7000u
12921 #define GIS_CH5_CTRL_CLR_CMD1_ALU_SHIFT          12
12922 #define GIS_CH5_CTRL_CLR_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD1_ALU_MASK)
12923 #define GIS_CH5_CTRL_CLR_CMD1_ACC_NEG_MASK       0x8000u
12924 #define GIS_CH5_CTRL_CLR_CMD1_ACC_NEG_SHIFT      15
12925 #define GIS_CH5_CTRL_CLR_CMD2_OPCODE_MASK        0xF0000u
12926 #define GIS_CH5_CTRL_CLR_CMD2_OPCODE_SHIFT       16
12927 #define GIS_CH5_CTRL_CLR_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD2_OPCODE_MASK)
12928 #define GIS_CH5_CTRL_CLR_CMD2_ALU_MASK           0x700000u
12929 #define GIS_CH5_CTRL_CLR_CMD2_ALU_SHIFT          20
12930 #define GIS_CH5_CTRL_CLR_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD2_ALU_MASK)
12931 #define GIS_CH5_CTRL_CLR_CMD2_ACC_NEG_MASK       0x800000u
12932 #define GIS_CH5_CTRL_CLR_CMD2_ACC_NEG_SHIFT      23
12933 #define GIS_CH5_CTRL_CLR_CMD3_OPCODE_MASK        0xF000000u
12934 #define GIS_CH5_CTRL_CLR_CMD3_OPCODE_SHIFT       24
12935 #define GIS_CH5_CTRL_CLR_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD3_OPCODE_MASK)
12936 #define GIS_CH5_CTRL_CLR_CMD3_ALU_MASK           0x70000000u
12937 #define GIS_CH5_CTRL_CLR_CMD3_ALU_SHIFT          28
12938 #define GIS_CH5_CTRL_CLR_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD3_ALU_MASK)
12939 #define GIS_CH5_CTRL_CLR_CMD3_ACC_NEG_MASK       0x80000000u
12940 #define GIS_CH5_CTRL_CLR_CMD3_ACC_NEG_SHIFT      31
12941 /* CH5_CTRL_TOG Bit Fields */
12942 #define GIS_CH5_CTRL_TOG_CMD0_OPCODE_MASK        0xFu
12943 #define GIS_CH5_CTRL_TOG_CMD0_OPCODE_SHIFT       0
12944 #define GIS_CH5_CTRL_TOG_CMD0_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD0_OPCODE_MASK)
12945 #define GIS_CH5_CTRL_TOG_CMD0_ALU_MASK           0x70u
12946 #define GIS_CH5_CTRL_TOG_CMD0_ALU_SHIFT          4
12947 #define GIS_CH5_CTRL_TOG_CMD0_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD0_ALU_MASK)
12948 #define GIS_CH5_CTRL_TOG_CMD0_ACC_NEG_MASK       0x80u
12949 #define GIS_CH5_CTRL_TOG_CMD0_ACC_NEG_SHIFT      7
12950 #define GIS_CH5_CTRL_TOG_CMD1_OPCODE_MASK        0xF00u
12951 #define GIS_CH5_CTRL_TOG_CMD1_OPCODE_SHIFT       8
12952 #define GIS_CH5_CTRL_TOG_CMD1_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD1_OPCODE_MASK)
12953 #define GIS_CH5_CTRL_TOG_CMD1_ALU_MASK           0x7000u
12954 #define GIS_CH5_CTRL_TOG_CMD1_ALU_SHIFT          12
12955 #define GIS_CH5_CTRL_TOG_CMD1_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD1_ALU_MASK)
12956 #define GIS_CH5_CTRL_TOG_CMD1_ACC_NEG_MASK       0x8000u
12957 #define GIS_CH5_CTRL_TOG_CMD1_ACC_NEG_SHIFT      15
12958 #define GIS_CH5_CTRL_TOG_CMD2_OPCODE_MASK        0xF0000u
12959 #define GIS_CH5_CTRL_TOG_CMD2_OPCODE_SHIFT       16
12960 #define GIS_CH5_CTRL_TOG_CMD2_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD2_OPCODE_MASK)
12961 #define GIS_CH5_CTRL_TOG_CMD2_ALU_MASK           0x700000u
12962 #define GIS_CH5_CTRL_TOG_CMD2_ALU_SHIFT          20
12963 #define GIS_CH5_CTRL_TOG_CMD2_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD2_ALU_MASK)
12964 #define GIS_CH5_CTRL_TOG_CMD2_ACC_NEG_MASK       0x800000u
12965 #define GIS_CH5_CTRL_TOG_CMD2_ACC_NEG_SHIFT      23
12966 #define GIS_CH5_CTRL_TOG_CMD3_OPCODE_MASK        0xF000000u
12967 #define GIS_CH5_CTRL_TOG_CMD3_OPCODE_SHIFT       24
12968 #define GIS_CH5_CTRL_TOG_CMD3_OPCODE(x)          (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD3_OPCODE_MASK)
12969 #define GIS_CH5_CTRL_TOG_CMD3_ALU_MASK           0x70000000u
12970 #define GIS_CH5_CTRL_TOG_CMD3_ALU_SHIFT          28
12971 #define GIS_CH5_CTRL_TOG_CMD3_ALU(x)             (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD3_ALU_MASK)
12972 #define GIS_CH5_CTRL_TOG_CMD3_ACC_NEG_MASK       0x80000000u
12973 #define GIS_CH5_CTRL_TOG_CMD3_ACC_NEG_SHIFT      31
12974 /* CH5_ADDR0 Bit Fields */
12975 #define GIS_CH5_ADDR0_ADDR_MASK                  0x7FFFFFFu
12976 #define GIS_CH5_ADDR0_ADDR_SHIFT                 0
12977 #define GIS_CH5_ADDR0_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_ADDR_SHIFT))&GIS_CH5_ADDR0_ADDR_MASK)
12978 #define GIS_CH5_ADDR0_CSI0_SEL_MASK              0x8000000u
12979 #define GIS_CH5_ADDR0_CSI0_SEL_SHIFT             27
12980 #define GIS_CH5_ADDR0_CSI1_SEL_MASK              0x10000000u
12981 #define GIS_CH5_ADDR0_CSI1_SEL_SHIFT             28
12982 #define GIS_CH5_ADDR0_PXP_SEL_MASK               0x20000000u
12983 #define GIS_CH5_ADDR0_PXP_SEL_SHIFT              29
12984 #define GIS_CH5_ADDR0_LCDIF0_SEL_MASK            0x40000000u
12985 #define GIS_CH5_ADDR0_LCDIF0_SEL_SHIFT           30
12986 #define GIS_CH5_ADDR0_LCDIF1_SEL_MASK            0x80000000u
12987 #define GIS_CH5_ADDR0_LCDIF1_SEL_SHIFT           31
12988 /* CH5_ADDR0_SET Bit Fields */
12989 #define GIS_CH5_ADDR0_SET_ADDR_MASK              0x7FFFFFFu
12990 #define GIS_CH5_ADDR0_SET_ADDR_SHIFT             0
12991 #define GIS_CH5_ADDR0_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_SET_ADDR_SHIFT))&GIS_CH5_ADDR0_SET_ADDR_MASK)
12992 #define GIS_CH5_ADDR0_SET_CSI0_SEL_MASK          0x8000000u
12993 #define GIS_CH5_ADDR0_SET_CSI0_SEL_SHIFT         27
12994 #define GIS_CH5_ADDR0_SET_CSI1_SEL_MASK          0x10000000u
12995 #define GIS_CH5_ADDR0_SET_CSI1_SEL_SHIFT         28
12996 #define GIS_CH5_ADDR0_SET_PXP_SEL_MASK           0x20000000u
12997 #define GIS_CH5_ADDR0_SET_PXP_SEL_SHIFT          29
12998 #define GIS_CH5_ADDR0_SET_LCDIF0_SEL_MASK        0x40000000u
12999 #define GIS_CH5_ADDR0_SET_LCDIF0_SEL_SHIFT       30
13000 #define GIS_CH5_ADDR0_SET_LCDIF1_SEL_MASK        0x80000000u
13001 #define GIS_CH5_ADDR0_SET_LCDIF1_SEL_SHIFT       31
13002 /* CH5_ADDR0_CLR Bit Fields */
13003 #define GIS_CH5_ADDR0_CLR_ADDR_MASK              0x7FFFFFFu
13004 #define GIS_CH5_ADDR0_CLR_ADDR_SHIFT             0
13005 #define GIS_CH5_ADDR0_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_CLR_ADDR_SHIFT))&GIS_CH5_ADDR0_CLR_ADDR_MASK)
13006 #define GIS_CH5_ADDR0_CLR_CSI0_SEL_MASK          0x8000000u
13007 #define GIS_CH5_ADDR0_CLR_CSI0_SEL_SHIFT         27
13008 #define GIS_CH5_ADDR0_CLR_CSI1_SEL_MASK          0x10000000u
13009 #define GIS_CH5_ADDR0_CLR_CSI1_SEL_SHIFT         28
13010 #define GIS_CH5_ADDR0_CLR_PXP_SEL_MASK           0x20000000u
13011 #define GIS_CH5_ADDR0_CLR_PXP_SEL_SHIFT          29
13012 #define GIS_CH5_ADDR0_CLR_LCDIF0_SEL_MASK        0x40000000u
13013 #define GIS_CH5_ADDR0_CLR_LCDIF0_SEL_SHIFT       30
13014 #define GIS_CH5_ADDR0_CLR_LCDIF1_SEL_MASK        0x80000000u
13015 #define GIS_CH5_ADDR0_CLR_LCDIF1_SEL_SHIFT       31
13016 /* CH5_ADDR0_TOG Bit Fields */
13017 #define GIS_CH5_ADDR0_TOG_ADDR_MASK              0x7FFFFFFu
13018 #define GIS_CH5_ADDR0_TOG_ADDR_SHIFT             0
13019 #define GIS_CH5_ADDR0_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_TOG_ADDR_SHIFT))&GIS_CH5_ADDR0_TOG_ADDR_MASK)
13020 #define GIS_CH5_ADDR0_TOG_CSI0_SEL_MASK          0x8000000u
13021 #define GIS_CH5_ADDR0_TOG_CSI0_SEL_SHIFT         27
13022 #define GIS_CH5_ADDR0_TOG_CSI1_SEL_MASK          0x10000000u
13023 #define GIS_CH5_ADDR0_TOG_CSI1_SEL_SHIFT         28
13024 #define GIS_CH5_ADDR0_TOG_PXP_SEL_MASK           0x20000000u
13025 #define GIS_CH5_ADDR0_TOG_PXP_SEL_SHIFT          29
13026 #define GIS_CH5_ADDR0_TOG_LCDIF0_SEL_MASK        0x40000000u
13027 #define GIS_CH5_ADDR0_TOG_LCDIF0_SEL_SHIFT       30
13028 #define GIS_CH5_ADDR0_TOG_LCDIF1_SEL_MASK        0x80000000u
13029 #define GIS_CH5_ADDR0_TOG_LCDIF1_SEL_SHIFT       31
13030 /* CH5_DATA0 Bit Fields */
13031 #define GIS_CH5_DATA0_DATA_MASK                  0xFFFFFFFFu
13032 #define GIS_CH5_DATA0_DATA_SHIFT                 0
13033 #define GIS_CH5_DATA0_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA0_DATA_SHIFT))&GIS_CH5_DATA0_DATA_MASK)
13034 /* CH5_ADDR1 Bit Fields */
13035 #define GIS_CH5_ADDR1_ADDR_MASK                  0x7FFFFFFu
13036 #define GIS_CH5_ADDR1_ADDR_SHIFT                 0
13037 #define GIS_CH5_ADDR1_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_ADDR_SHIFT))&GIS_CH5_ADDR1_ADDR_MASK)
13038 #define GIS_CH5_ADDR1_CSI0_SEL_MASK              0x8000000u
13039 #define GIS_CH5_ADDR1_CSI0_SEL_SHIFT             27
13040 #define GIS_CH5_ADDR1_CSI1_SEL_MASK              0x10000000u
13041 #define GIS_CH5_ADDR1_CSI1_SEL_SHIFT             28
13042 #define GIS_CH5_ADDR1_PXP_SEL_MASK               0x20000000u
13043 #define GIS_CH5_ADDR1_PXP_SEL_SHIFT              29
13044 #define GIS_CH5_ADDR1_LCDIF0_SEL_MASK            0x40000000u
13045 #define GIS_CH5_ADDR1_LCDIF0_SEL_SHIFT           30
13046 #define GIS_CH5_ADDR1_LCDIF1_SEL_MASK            0x80000000u
13047 #define GIS_CH5_ADDR1_LCDIF1_SEL_SHIFT           31
13048 /* CH5_ADDR1_SET Bit Fields */
13049 #define GIS_CH5_ADDR1_SET_ADDR_MASK              0x7FFFFFFu
13050 #define GIS_CH5_ADDR1_SET_ADDR_SHIFT             0
13051 #define GIS_CH5_ADDR1_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_SET_ADDR_SHIFT))&GIS_CH5_ADDR1_SET_ADDR_MASK)
13052 #define GIS_CH5_ADDR1_SET_CSI0_SEL_MASK          0x8000000u
13053 #define GIS_CH5_ADDR1_SET_CSI0_SEL_SHIFT         27
13054 #define GIS_CH5_ADDR1_SET_CSI1_SEL_MASK          0x10000000u
13055 #define GIS_CH5_ADDR1_SET_CSI1_SEL_SHIFT         28
13056 #define GIS_CH5_ADDR1_SET_PXP_SEL_MASK           0x20000000u
13057 #define GIS_CH5_ADDR1_SET_PXP_SEL_SHIFT          29
13058 #define GIS_CH5_ADDR1_SET_LCDIF0_SEL_MASK        0x40000000u
13059 #define GIS_CH5_ADDR1_SET_LCDIF0_SEL_SHIFT       30
13060 #define GIS_CH5_ADDR1_SET_LCDIF1_SEL_MASK        0x80000000u
13061 #define GIS_CH5_ADDR1_SET_LCDIF1_SEL_SHIFT       31
13062 /* CH5_ADDR1_CLR Bit Fields */
13063 #define GIS_CH5_ADDR1_CLR_ADDR_MASK              0x7FFFFFFu
13064 #define GIS_CH5_ADDR1_CLR_ADDR_SHIFT             0
13065 #define GIS_CH5_ADDR1_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_CLR_ADDR_SHIFT))&GIS_CH5_ADDR1_CLR_ADDR_MASK)
13066 #define GIS_CH5_ADDR1_CLR_CSI0_SEL_MASK          0x8000000u
13067 #define GIS_CH5_ADDR1_CLR_CSI0_SEL_SHIFT         27
13068 #define GIS_CH5_ADDR1_CLR_CSI1_SEL_MASK          0x10000000u
13069 #define GIS_CH5_ADDR1_CLR_CSI1_SEL_SHIFT         28
13070 #define GIS_CH5_ADDR1_CLR_PXP_SEL_MASK           0x20000000u
13071 #define GIS_CH5_ADDR1_CLR_PXP_SEL_SHIFT          29
13072 #define GIS_CH5_ADDR1_CLR_LCDIF0_SEL_MASK        0x40000000u
13073 #define GIS_CH5_ADDR1_CLR_LCDIF0_SEL_SHIFT       30
13074 #define GIS_CH5_ADDR1_CLR_LCDIF1_SEL_MASK        0x80000000u
13075 #define GIS_CH5_ADDR1_CLR_LCDIF1_SEL_SHIFT       31
13076 /* CH5_ADDR1_TOG Bit Fields */
13077 #define GIS_CH5_ADDR1_TOG_ADDR_MASK              0x7FFFFFFu
13078 #define GIS_CH5_ADDR1_TOG_ADDR_SHIFT             0
13079 #define GIS_CH5_ADDR1_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_TOG_ADDR_SHIFT))&GIS_CH5_ADDR1_TOG_ADDR_MASK)
13080 #define GIS_CH5_ADDR1_TOG_CSI0_SEL_MASK          0x8000000u
13081 #define GIS_CH5_ADDR1_TOG_CSI0_SEL_SHIFT         27
13082 #define GIS_CH5_ADDR1_TOG_CSI1_SEL_MASK          0x10000000u
13083 #define GIS_CH5_ADDR1_TOG_CSI1_SEL_SHIFT         28
13084 #define GIS_CH5_ADDR1_TOG_PXP_SEL_MASK           0x20000000u
13085 #define GIS_CH5_ADDR1_TOG_PXP_SEL_SHIFT          29
13086 #define GIS_CH5_ADDR1_TOG_LCDIF0_SEL_MASK        0x40000000u
13087 #define GIS_CH5_ADDR1_TOG_LCDIF0_SEL_SHIFT       30
13088 #define GIS_CH5_ADDR1_TOG_LCDIF1_SEL_MASK        0x80000000u
13089 #define GIS_CH5_ADDR1_TOG_LCDIF1_SEL_SHIFT       31
13090 /* CH5_DATA1 Bit Fields */
13091 #define GIS_CH5_DATA1_DATA_MASK                  0xFFFFFFFFu
13092 #define GIS_CH5_DATA1_DATA_SHIFT                 0
13093 #define GIS_CH5_DATA1_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA1_DATA_SHIFT))&GIS_CH5_DATA1_DATA_MASK)
13094 /* CH5_ADDR2 Bit Fields */
13095 #define GIS_CH5_ADDR2_ADDR_MASK                  0x7FFFFFFu
13096 #define GIS_CH5_ADDR2_ADDR_SHIFT                 0
13097 #define GIS_CH5_ADDR2_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_ADDR_SHIFT))&GIS_CH5_ADDR2_ADDR_MASK)
13098 #define GIS_CH5_ADDR2_CSI0_SEL_MASK              0x8000000u
13099 #define GIS_CH5_ADDR2_CSI0_SEL_SHIFT             27
13100 #define GIS_CH5_ADDR2_CSI1_SEL_MASK              0x10000000u
13101 #define GIS_CH5_ADDR2_CSI1_SEL_SHIFT             28
13102 #define GIS_CH5_ADDR2_PXP_SEL_MASK               0x20000000u
13103 #define GIS_CH5_ADDR2_PXP_SEL_SHIFT              29
13104 #define GIS_CH5_ADDR2_LCDIF0_SEL_MASK            0x40000000u
13105 #define GIS_CH5_ADDR2_LCDIF0_SEL_SHIFT           30
13106 #define GIS_CH5_ADDR2_LCDIF1_SEL_MASK            0x80000000u
13107 #define GIS_CH5_ADDR2_LCDIF1_SEL_SHIFT           31
13108 /* CH5_ADDR2_SET Bit Fields */
13109 #define GIS_CH5_ADDR2_SET_ADDR_MASK              0x7FFFFFFu
13110 #define GIS_CH5_ADDR2_SET_ADDR_SHIFT             0
13111 #define GIS_CH5_ADDR2_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_SET_ADDR_SHIFT))&GIS_CH5_ADDR2_SET_ADDR_MASK)
13112 #define GIS_CH5_ADDR2_SET_CSI0_SEL_MASK          0x8000000u
13113 #define GIS_CH5_ADDR2_SET_CSI0_SEL_SHIFT         27
13114 #define GIS_CH5_ADDR2_SET_CSI1_SEL_MASK          0x10000000u
13115 #define GIS_CH5_ADDR2_SET_CSI1_SEL_SHIFT         28
13116 #define GIS_CH5_ADDR2_SET_PXP_SEL_MASK           0x20000000u
13117 #define GIS_CH5_ADDR2_SET_PXP_SEL_SHIFT          29
13118 #define GIS_CH5_ADDR2_SET_LCDIF0_SEL_MASK        0x40000000u
13119 #define GIS_CH5_ADDR2_SET_LCDIF0_SEL_SHIFT       30
13120 #define GIS_CH5_ADDR2_SET_LCDIF1_SEL_MASK        0x80000000u
13121 #define GIS_CH5_ADDR2_SET_LCDIF1_SEL_SHIFT       31
13122 /* CH5_ADDR2_CLR Bit Fields */
13123 #define GIS_CH5_ADDR2_CLR_ADDR_MASK              0x7FFFFFFu
13124 #define GIS_CH5_ADDR2_CLR_ADDR_SHIFT             0
13125 #define GIS_CH5_ADDR2_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_CLR_ADDR_SHIFT))&GIS_CH5_ADDR2_CLR_ADDR_MASK)
13126 #define GIS_CH5_ADDR2_CLR_CSI0_SEL_MASK          0x8000000u
13127 #define GIS_CH5_ADDR2_CLR_CSI0_SEL_SHIFT         27
13128 #define GIS_CH5_ADDR2_CLR_CSI1_SEL_MASK          0x10000000u
13129 #define GIS_CH5_ADDR2_CLR_CSI1_SEL_SHIFT         28
13130 #define GIS_CH5_ADDR2_CLR_PXP_SEL_MASK           0x20000000u
13131 #define GIS_CH5_ADDR2_CLR_PXP_SEL_SHIFT          29
13132 #define GIS_CH5_ADDR2_CLR_LCDIF0_SEL_MASK        0x40000000u
13133 #define GIS_CH5_ADDR2_CLR_LCDIF0_SEL_SHIFT       30
13134 #define GIS_CH5_ADDR2_CLR_LCDIF1_SEL_MASK        0x80000000u
13135 #define GIS_CH5_ADDR2_CLR_LCDIF1_SEL_SHIFT       31
13136 /* CH5_ADDR2_TOG Bit Fields */
13137 #define GIS_CH5_ADDR2_TOG_ADDR_MASK              0x7FFFFFFu
13138 #define GIS_CH5_ADDR2_TOG_ADDR_SHIFT             0
13139 #define GIS_CH5_ADDR2_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_TOG_ADDR_SHIFT))&GIS_CH5_ADDR2_TOG_ADDR_MASK)
13140 #define GIS_CH5_ADDR2_TOG_CSI0_SEL_MASK          0x8000000u
13141 #define GIS_CH5_ADDR2_TOG_CSI0_SEL_SHIFT         27
13142 #define GIS_CH5_ADDR2_TOG_CSI1_SEL_MASK          0x10000000u
13143 #define GIS_CH5_ADDR2_TOG_CSI1_SEL_SHIFT         28
13144 #define GIS_CH5_ADDR2_TOG_PXP_SEL_MASK           0x20000000u
13145 #define GIS_CH5_ADDR2_TOG_PXP_SEL_SHIFT          29
13146 #define GIS_CH5_ADDR2_TOG_LCDIF0_SEL_MASK        0x40000000u
13147 #define GIS_CH5_ADDR2_TOG_LCDIF0_SEL_SHIFT       30
13148 #define GIS_CH5_ADDR2_TOG_LCDIF1_SEL_MASK        0x80000000u
13149 #define GIS_CH5_ADDR2_TOG_LCDIF1_SEL_SHIFT       31
13150 /* CH5_DATA2 Bit Fields */
13151 #define GIS_CH5_DATA2_DATA_MASK                  0xFFFFFFFFu
13152 #define GIS_CH5_DATA2_DATA_SHIFT                 0
13153 #define GIS_CH5_DATA2_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA2_DATA_SHIFT))&GIS_CH5_DATA2_DATA_MASK)
13154 /* CH5_ADDR3 Bit Fields */
13155 #define GIS_CH5_ADDR3_ADDR_MASK                  0x7FFFFFFu
13156 #define GIS_CH5_ADDR3_ADDR_SHIFT                 0
13157 #define GIS_CH5_ADDR3_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_ADDR_SHIFT))&GIS_CH5_ADDR3_ADDR_MASK)
13158 #define GIS_CH5_ADDR3_CSI0_SEL_MASK              0x8000000u
13159 #define GIS_CH5_ADDR3_CSI0_SEL_SHIFT             27
13160 #define GIS_CH5_ADDR3_CSI1_SEL_MASK              0x10000000u
13161 #define GIS_CH5_ADDR3_CSI1_SEL_SHIFT             28
13162 #define GIS_CH5_ADDR3_PXP_SEL_MASK               0x20000000u
13163 #define GIS_CH5_ADDR3_PXP_SEL_SHIFT              29
13164 #define GIS_CH5_ADDR3_LCDIF0_SEL_MASK            0x40000000u
13165 #define GIS_CH5_ADDR3_LCDIF0_SEL_SHIFT           30
13166 #define GIS_CH5_ADDR3_LCDIF1_SEL_MASK            0x80000000u
13167 #define GIS_CH5_ADDR3_LCDIF1_SEL_SHIFT           31
13168 /* CH5_ADDR3_SET Bit Fields */
13169 #define GIS_CH5_ADDR3_SET_ADDR_MASK              0x7FFFFFFu
13170 #define GIS_CH5_ADDR3_SET_ADDR_SHIFT             0
13171 #define GIS_CH5_ADDR3_SET_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_SET_ADDR_SHIFT))&GIS_CH5_ADDR3_SET_ADDR_MASK)
13172 #define GIS_CH5_ADDR3_SET_CSI0_SEL_MASK          0x8000000u
13173 #define GIS_CH5_ADDR3_SET_CSI0_SEL_SHIFT         27
13174 #define GIS_CH5_ADDR3_SET_CSI1_SEL_MASK          0x10000000u
13175 #define GIS_CH5_ADDR3_SET_CSI1_SEL_SHIFT         28
13176 #define GIS_CH5_ADDR3_SET_PXP_SEL_MASK           0x20000000u
13177 #define GIS_CH5_ADDR3_SET_PXP_SEL_SHIFT          29
13178 #define GIS_CH5_ADDR3_SET_LCDIF0_SEL_MASK        0x40000000u
13179 #define GIS_CH5_ADDR3_SET_LCDIF0_SEL_SHIFT       30
13180 #define GIS_CH5_ADDR3_SET_LCDIF1_SEL_MASK        0x80000000u
13181 #define GIS_CH5_ADDR3_SET_LCDIF1_SEL_SHIFT       31
13182 /* CH5_ADDR3_CLR Bit Fields */
13183 #define GIS_CH5_ADDR3_CLR_ADDR_MASK              0x7FFFFFFu
13184 #define GIS_CH5_ADDR3_CLR_ADDR_SHIFT             0
13185 #define GIS_CH5_ADDR3_CLR_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_CLR_ADDR_SHIFT))&GIS_CH5_ADDR3_CLR_ADDR_MASK)
13186 #define GIS_CH5_ADDR3_CLR_CSI0_SEL_MASK          0x8000000u
13187 #define GIS_CH5_ADDR3_CLR_CSI0_SEL_SHIFT         27
13188 #define GIS_CH5_ADDR3_CLR_CSI1_SEL_MASK          0x10000000u
13189 #define GIS_CH5_ADDR3_CLR_CSI1_SEL_SHIFT         28
13190 #define GIS_CH5_ADDR3_CLR_PXP_SEL_MASK           0x20000000u
13191 #define GIS_CH5_ADDR3_CLR_PXP_SEL_SHIFT          29
13192 #define GIS_CH5_ADDR3_CLR_LCDIF0_SEL_MASK        0x40000000u
13193 #define GIS_CH5_ADDR3_CLR_LCDIF0_SEL_SHIFT       30
13194 #define GIS_CH5_ADDR3_CLR_LCDIF1_SEL_MASK        0x80000000u
13195 #define GIS_CH5_ADDR3_CLR_LCDIF1_SEL_SHIFT       31
13196 /* CH5_ADDR3_TOG Bit Fields */
13197 #define GIS_CH5_ADDR3_TOG_ADDR_MASK              0x7FFFFFFu
13198 #define GIS_CH5_ADDR3_TOG_ADDR_SHIFT             0
13199 #define GIS_CH5_ADDR3_TOG_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_TOG_ADDR_SHIFT))&GIS_CH5_ADDR3_TOG_ADDR_MASK)
13200 #define GIS_CH5_ADDR3_TOG_CSI0_SEL_MASK          0x8000000u
13201 #define GIS_CH5_ADDR3_TOG_CSI0_SEL_SHIFT         27
13202 #define GIS_CH5_ADDR3_TOG_CSI1_SEL_MASK          0x10000000u
13203 #define GIS_CH5_ADDR3_TOG_CSI1_SEL_SHIFT         28
13204 #define GIS_CH5_ADDR3_TOG_PXP_SEL_MASK           0x20000000u
13205 #define GIS_CH5_ADDR3_TOG_PXP_SEL_SHIFT          29
13206 #define GIS_CH5_ADDR3_TOG_LCDIF0_SEL_MASK        0x40000000u
13207 #define GIS_CH5_ADDR3_TOG_LCDIF0_SEL_SHIFT       30
13208 #define GIS_CH5_ADDR3_TOG_LCDIF1_SEL_MASK        0x80000000u
13209 #define GIS_CH5_ADDR3_TOG_LCDIF1_SEL_SHIFT       31
13210 /* CH5_DATA3 Bit Fields */
13211 #define GIS_CH5_DATA3_DATA_MASK                  0xFFFFFFFFu
13212 #define GIS_CH5_DATA3_DATA_SHIFT                 0
13213 #define GIS_CH5_DATA3_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA3_DATA_SHIFT))&GIS_CH5_DATA3_DATA_MASK)
13214 /* DEBUG0 Bit Fields */
13215 #define GIS_DEBUG0_CMD_STATE_MASK                0xFFu
13216 #define GIS_DEBUG0_CMD_STATE_SHIFT               0
13217 #define GIS_DEBUG0_CMD_STATE(x)                  (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_STATE_SHIFT))&GIS_DEBUG0_CMD_STATE_MASK)
13218 #define GIS_DEBUG0_MAIN_STATE_MASK               0x3F00u
13219 #define GIS_DEBUG0_MAIN_STATE_SHIFT              8
13220 #define GIS_DEBUG0_MAIN_STATE(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_MAIN_STATE_SHIFT))&GIS_DEBUG0_MAIN_STATE_MASK)
13221 #define GIS_DEBUG0_CHANNEL_CUR_MASK              0x3C000u
13222 #define GIS_DEBUG0_CHANNEL_CUR_SHIFT             14
13223 #define GIS_DEBUG0_CHANNEL_CUR(x)                (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CHANNEL_CUR_SHIFT))&GIS_DEBUG0_CHANNEL_CUR_MASK)
13224 #define GIS_DEBUG0_CMD_COUNTER_MASK              0x1C0000u
13225 #define GIS_DEBUG0_CMD_COUNTER_SHIFT             18
13226 #define GIS_DEBUG0_CMD_COUNTER(x)                (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_COUNTER_SHIFT))&GIS_DEBUG0_CMD_COUNTER_MASK)
13227 #define GIS_DEBUG0_CMD_OPCODE_MASK               0x1E00000u
13228 #define GIS_DEBUG0_CMD_OPCODE_SHIFT              21
13229 #define GIS_DEBUG0_CMD_OPCODE(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_OPCODE_SHIFT))&GIS_DEBUG0_CMD_OPCODE_MASK)
13230 #define GIS_DEBUG0_PXP_BUSY_MASK                 0x2000000u
13231 #define GIS_DEBUG0_PXP_BUSY_SHIFT                25
13232 #define GIS_DEBUG0_PXP_IRQ_MASK                  0x4000000u
13233 #define GIS_DEBUG0_PXP_IRQ_SHIFT                 26
13234 #define GIS_DEBUG0_CSI_IRQ_MASK                  0x8000000u
13235 #define GIS_DEBUG0_CSI_IRQ_SHIFT                 27
13236 #define GIS_DEBUG0_CSI_FB_REG_MASK               0x30000000u
13237 #define GIS_DEBUG0_CSI_FB_REG_SHIFT              28
13238 #define GIS_DEBUG0_CSI_FB_REG(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CSI_FB_REG_SHIFT))&GIS_DEBUG0_CSI_FB_REG_MASK)
13239 /* DEBUG1 Bit Fields */
13240 #define GIS_DEBUG1_CSI_FB_MASK                   0xFFu
13241 #define GIS_DEBUG1_CSI_FB_SHIFT                  0
13242 #define GIS_DEBUG1_CSI_FB(x)                     (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_CSI_FB_SHIFT))&GIS_DEBUG1_CSI_FB_MASK)
13243 #define GIS_DEBUG1_PXP_OUT_FB_MASK               0xFF00u
13244 #define GIS_DEBUG1_PXP_OUT_FB_SHIFT              8
13245 #define GIS_DEBUG1_PXP_OUT_FB(x)                 (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_PXP_OUT_FB_SHIFT))&GIS_DEBUG1_PXP_OUT_FB_MASK)
13246 #define GIS_DEBUG1_PXP_IN_FB_MASK                0x30000u
13247 #define GIS_DEBUG1_PXP_IN_FB_SHIFT               16
13248 #define GIS_DEBUG1_PXP_IN_FB(x)                  (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_PXP_IN_FB_SHIFT))&GIS_DEBUG1_PXP_IN_FB_MASK)
13249 #define GIS_DEBUG1_LCDIF_FB_MASK                 0xC0000u
13250 #define GIS_DEBUG1_LCDIF_FB_SHIFT                18
13251 #define GIS_DEBUG1_LCDIF_FB(x)                   (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_LCDIF_FB_SHIFT))&GIS_DEBUG1_LCDIF_FB_MASK)
13252 /* VERSION Bit Fields */
13253 #define GIS_VERSION_STEP_MASK                    0xFFFFu
13254 #define GIS_VERSION_STEP_SHIFT                   0
13255 #define GIS_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_STEP_SHIFT))&GIS_VERSION_STEP_MASK)
13256 #define GIS_VERSION_MINOR_MASK                   0xFF0000u
13257 #define GIS_VERSION_MINOR_SHIFT                  16
13258 #define GIS_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_MINOR_SHIFT))&GIS_VERSION_MINOR_MASK)
13259 #define GIS_VERSION_MAJOR_MASK                   0xFF000000u
13260 #define GIS_VERSION_MAJOR_SHIFT                  24
13261 #define GIS_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_MAJOR_SHIFT))&GIS_VERSION_MAJOR_MASK)
13262 
13263 /*!
13264  * @}
13265  */ /* end of group GIS_Register_Masks */
13266 
13267 /* GIS - Peripheral instance base addresses */
13268 /** Peripheral GIS base address */
13269 #define GIS_BASE                                 (0x42204000u)
13270 /** Peripheral GIS base pointer */
13271 #define GIS                                      ((GIS_Type *)GIS_BASE)
13272 #define GIS_BASE_PTR                             (GIS)
13273 /** Array initializer of GIS peripheral base addresses */
13274 #define GIS_BASE_ADDRS                           { GIS_BASE }
13275 /** Array initializer of GIS peripheral base pointers */
13276 #define GIS_BASE_PTRS                            { GIS }
13277 
13278 /* ----------------------------------------------------------------------------
13279    -- GIS - Register accessor macros
13280    ---------------------------------------------------------------------------- */
13281 
13282 /*!
13283  * @addtogroup GIS_Register_Accessor_Macros GIS - Register accessor macros
13284  * @{
13285  */
13286 
13287 /* GIS - Register instance definitions */
13288 /* GIS */
13289 #define GIS_CTRL                                 GIS_CTRL_REG(GIS_BASE_PTR)
13290 #define GIS_CTRL_SET                             GIS_CTRL_SET_REG(GIS_BASE_PTR)
13291 #define GIS_CTRL_CLR                             GIS_CTRL_CLR_REG(GIS_BASE_PTR)
13292 #define GIS_CTRL_TOG                             GIS_CTRL_TOG_REG(GIS_BASE_PTR)
13293 #define GIS_CONFIG0                              GIS_CONFIG0_REG(GIS_BASE_PTR)
13294 #define GIS_CONFIG0_SET                          GIS_CONFIG0_SET_REG(GIS_BASE_PTR)
13295 #define GIS_CONFIG0_CLR                          GIS_CONFIG0_CLR_REG(GIS_BASE_PTR)
13296 #define GIS_CONFIG0_TOG                          GIS_CONFIG0_TOG_REG(GIS_BASE_PTR)
13297 #define GIS_CONFIG1                              GIS_CONFIG1_REG(GIS_BASE_PTR)
13298 #define GIS_CONFIG1_SET                          GIS_CONFIG1_SET_REG(GIS_BASE_PTR)
13299 #define GIS_CONFIG1_CLR                          GIS_CONFIG1_CLR_REG(GIS_BASE_PTR)
13300 #define GIS_CONFIG1_TOG                          GIS_CONFIG1_TOG_REG(GIS_BASE_PTR)
13301 #define GIS_FB0                                  GIS_FB0_REG(GIS_BASE_PTR)
13302 #define GIS_FB1                                  GIS_FB1_REG(GIS_BASE_PTR)
13303 #define GIS_PXP_FB0                              GIS_PXP_FB0_REG(GIS_BASE_PTR)
13304 #define GIS_PXP_FB1                              GIS_PXP_FB1_REG(GIS_BASE_PTR)
13305 #define GIS_CH0_CTRL                             GIS_CH0_CTRL_REG(GIS_BASE_PTR)
13306 #define GIS_CH0_CTRL_SET                         GIS_CH0_CTRL_SET_REG(GIS_BASE_PTR)
13307 #define GIS_CH0_CTRL_CLR                         GIS_CH0_CTRL_CLR_REG(GIS_BASE_PTR)
13308 #define GIS_CH0_CTRL_TOG                         GIS_CH0_CTRL_TOG_REG(GIS_BASE_PTR)
13309 #define GIS_CH0_ADDR0                            GIS_CH0_ADDR0_REG(GIS_BASE_PTR)
13310 #define GIS_CH0_ADDR0_SET                        GIS_CH0_ADDR0_SET_REG(GIS_BASE_PTR)
13311 #define GIS_CH0_ADDR0_CLR                        GIS_CH0_ADDR0_CLR_REG(GIS_BASE_PTR)
13312 #define GIS_CH0_ADDR0_TOG                        GIS_CH0_ADDR0_TOG_REG(GIS_BASE_PTR)
13313 #define GIS_CH0_DATA0                            GIS_CH0_DATA0_REG(GIS_BASE_PTR)
13314 #define GIS_CH0_ADDR1                            GIS_CH0_ADDR1_REG(GIS_BASE_PTR)
13315 #define GIS_CH0_ADDR1_SET                        GIS_CH0_ADDR1_SET_REG(GIS_BASE_PTR)
13316 #define GIS_CH0_ADDR1_CLR                        GIS_CH0_ADDR1_CLR_REG(GIS_BASE_PTR)
13317 #define GIS_CH0_ADDR1_TOG                        GIS_CH0_ADDR1_TOG_REG(GIS_BASE_PTR)
13318 #define GIS_CH0_DATA1                            GIS_CH0_DATA1_REG(GIS_BASE_PTR)
13319 #define GIS_CH0_ADDR2                            GIS_CH0_ADDR2_REG(GIS_BASE_PTR)
13320 #define GIS_CH0_ADDR2_SET                        GIS_CH0_ADDR2_SET_REG(GIS_BASE_PTR)
13321 #define GIS_CH0_ADDR2_CLR                        GIS_CH0_ADDR2_CLR_REG(GIS_BASE_PTR)
13322 #define GIS_CH0_ADDR2_TOG                        GIS_CH0_ADDR2_TOG_REG(GIS_BASE_PTR)
13323 #define GIS_CH0_DATA2                            GIS_CH0_DATA2_REG(GIS_BASE_PTR)
13324 #define GIS_CH0_ADDR3                            GIS_CH0_ADDR3_REG(GIS_BASE_PTR)
13325 #define GIS_CH0_ADDR3_SET                        GIS_CH0_ADDR3_SET_REG(GIS_BASE_PTR)
13326 #define GIS_CH0_ADDR3_CLR                        GIS_CH0_ADDR3_CLR_REG(GIS_BASE_PTR)
13327 #define GIS_CH0_ADDR3_TOG                        GIS_CH0_ADDR3_TOG_REG(GIS_BASE_PTR)
13328 #define GIS_CH0_DATA3                            GIS_CH0_DATA3_REG(GIS_BASE_PTR)
13329 #define GIS_CH1_CTRL                             GIS_CH1_CTRL_REG(GIS_BASE_PTR)
13330 #define GIS_CH1_CTRL_SET                         GIS_CH1_CTRL_SET_REG(GIS_BASE_PTR)
13331 #define GIS_CH1_CTRL_CLR                         GIS_CH1_CTRL_CLR_REG(GIS_BASE_PTR)
13332 #define GIS_CH1_CTRL_TOG                         GIS_CH1_CTRL_TOG_REG(GIS_BASE_PTR)
13333 #define GIS_CH1_ADDR0                            GIS_CH1_ADDR0_REG(GIS_BASE_PTR)
13334 #define GIS_CH1_ADDR0_SET                        GIS_CH1_ADDR0_SET_REG(GIS_BASE_PTR)
13335 #define GIS_CH1_ADDR0_CLR                        GIS_CH1_ADDR0_CLR_REG(GIS_BASE_PTR)
13336 #define GIS_CH1_ADDR0_TOG                        GIS_CH1_ADDR0_TOG_REG(GIS_BASE_PTR)
13337 #define GIS_CH1_DATA0                            GIS_CH1_DATA0_REG(GIS_BASE_PTR)
13338 #define GIS_CH1_ADDR1                            GIS_CH1_ADDR1_REG(GIS_BASE_PTR)
13339 #define GIS_CH1_ADDR1_SET                        GIS_CH1_ADDR1_SET_REG(GIS_BASE_PTR)
13340 #define GIS_CH1_ADDR1_CLR                        GIS_CH1_ADDR1_CLR_REG(GIS_BASE_PTR)
13341 #define GIS_CH1_ADDR1_TOG                        GIS_CH1_ADDR1_TOG_REG(GIS_BASE_PTR)
13342 #define GIS_CH1_DATA1                            GIS_CH1_DATA1_REG(GIS_BASE_PTR)
13343 #define GIS_CH1_ADDR2                            GIS_CH1_ADDR2_REG(GIS_BASE_PTR)
13344 #define GIS_CH1_ADDR2_SET                        GIS_CH1_ADDR2_SET_REG(GIS_BASE_PTR)
13345 #define GIS_CH1_ADDR2_CLR                        GIS_CH1_ADDR2_CLR_REG(GIS_BASE_PTR)
13346 #define GIS_CH1_ADDR2_TOG                        GIS_CH1_ADDR2_TOG_REG(GIS_BASE_PTR)
13347 #define GIS_CH1_DATA2                            GIS_CH1_DATA2_REG(GIS_BASE_PTR)
13348 #define GIS_CH1_ADDR3                            GIS_CH1_ADDR3_REG(GIS_BASE_PTR)
13349 #define GIS_CH1_ADDR3_SET                        GIS_CH1_ADDR3_SET_REG(GIS_BASE_PTR)
13350 #define GIS_CH1_ADDR3_CLR                        GIS_CH1_ADDR3_CLR_REG(GIS_BASE_PTR)
13351 #define GIS_CH1_ADDR3_TOG                        GIS_CH1_ADDR3_TOG_REG(GIS_BASE_PTR)
13352 #define GIS_CH1_DATA3                            GIS_CH1_DATA3_REG(GIS_BASE_PTR)
13353 #define GIS_CH2_CTRL                             GIS_CH2_CTRL_REG(GIS_BASE_PTR)
13354 #define GIS_CH2_CTRL_SET                         GIS_CH2_CTRL_SET_REG(GIS_BASE_PTR)
13355 #define GIS_CH2_CTRL_CLR                         GIS_CH2_CTRL_CLR_REG(GIS_BASE_PTR)
13356 #define GIS_CH2_CTRL_TOG                         GIS_CH2_CTRL_TOG_REG(GIS_BASE_PTR)
13357 #define GIS_CH2_ADDR0                            GIS_CH2_ADDR0_REG(GIS_BASE_PTR)
13358 #define GIS_CH2_ADDR0_SET                        GIS_CH2_ADDR0_SET_REG(GIS_BASE_PTR)
13359 #define GIS_CH2_ADDR0_CLR                        GIS_CH2_ADDR0_CLR_REG(GIS_BASE_PTR)
13360 #define GIS_CH2_ADDR0_TOG                        GIS_CH2_ADDR0_TOG_REG(GIS_BASE_PTR)
13361 #define GIS_CH2_DATA0                            GIS_CH2_DATA0_REG(GIS_BASE_PTR)
13362 #define GIS_CH2_ADDR1                            GIS_CH2_ADDR1_REG(GIS_BASE_PTR)
13363 #define GIS_CH2_ADDR1_SET                        GIS_CH2_ADDR1_SET_REG(GIS_BASE_PTR)
13364 #define GIS_CH2_ADDR1_CLR                        GIS_CH2_ADDR1_CLR_REG(GIS_BASE_PTR)
13365 #define GIS_CH2_ADDR1_TOG                        GIS_CH2_ADDR1_TOG_REG(GIS_BASE_PTR)
13366 #define GIS_CH2_DATA1                            GIS_CH2_DATA1_REG(GIS_BASE_PTR)
13367 #define GIS_CH2_ADDR2                            GIS_CH2_ADDR2_REG(GIS_BASE_PTR)
13368 #define GIS_CH2_ADDR2_SET                        GIS_CH2_ADDR2_SET_REG(GIS_BASE_PTR)
13369 #define GIS_CH2_ADDR2_CLR                        GIS_CH2_ADDR2_CLR_REG(GIS_BASE_PTR)
13370 #define GIS_CH2_ADDR2_TOG                        GIS_CH2_ADDR2_TOG_REG(GIS_BASE_PTR)
13371 #define GIS_CH2_DATA2                            GIS_CH2_DATA2_REG(GIS_BASE_PTR)
13372 #define GIS_CH2_ADDR3                            GIS_CH2_ADDR3_REG(GIS_BASE_PTR)
13373 #define GIS_CH2_ADDR3_SET                        GIS_CH2_ADDR3_SET_REG(GIS_BASE_PTR)
13374 #define GIS_CH2_ADDR3_CLR                        GIS_CH2_ADDR3_CLR_REG(GIS_BASE_PTR)
13375 #define GIS_CH2_ADDR3_TOG                        GIS_CH2_ADDR3_TOG_REG(GIS_BASE_PTR)
13376 #define GIS_CH2_DATA3                            GIS_CH2_DATA3_REG(GIS_BASE_PTR)
13377 #define GIS_CH3_CTRL                             GIS_CH3_CTRL_REG(GIS_BASE_PTR)
13378 #define GIS_CH3_CTRL_SET                         GIS_CH3_CTRL_SET_REG(GIS_BASE_PTR)
13379 #define GIS_CH3_CTRL_CLR                         GIS_CH3_CTRL_CLR_REG(GIS_BASE_PTR)
13380 #define GIS_CH3_CTRL_TOG                         GIS_CH3_CTRL_TOG_REG(GIS_BASE_PTR)
13381 #define GIS_CH3_ADDR0                            GIS_CH3_ADDR0_REG(GIS_BASE_PTR)
13382 #define GIS_CH3_ADDR0_SET                        GIS_CH3_ADDR0_SET_REG(GIS_BASE_PTR)
13383 #define GIS_CH3_ADDR0_CLR                        GIS_CH3_ADDR0_CLR_REG(GIS_BASE_PTR)
13384 #define GIS_CH3_ADDR0_TOG                        GIS_CH3_ADDR0_TOG_REG(GIS_BASE_PTR)
13385 #define GIS_CH3_DATA0                            GIS_CH3_DATA0_REG(GIS_BASE_PTR)
13386 #define GIS_CH3_ADDR1                            GIS_CH3_ADDR1_REG(GIS_BASE_PTR)
13387 #define GIS_CH3_ADDR1_SET                        GIS_CH3_ADDR1_SET_REG(GIS_BASE_PTR)
13388 #define GIS_CH3_ADDR1_CLR                        GIS_CH3_ADDR1_CLR_REG(GIS_BASE_PTR)
13389 #define GIS_CH3_ADDR1_TOG                        GIS_CH3_ADDR1_TOG_REG(GIS_BASE_PTR)
13390 #define GIS_CH3_DATA1                            GIS_CH3_DATA1_REG(GIS_BASE_PTR)
13391 #define GIS_CH3_ADDR2                            GIS_CH3_ADDR2_REG(GIS_BASE_PTR)
13392 #define GIS_CH3_ADDR2_SET                        GIS_CH3_ADDR2_SET_REG(GIS_BASE_PTR)
13393 #define GIS_CH3_ADDR2_CLR                        GIS_CH3_ADDR2_CLR_REG(GIS_BASE_PTR)
13394 #define GIS_CH3_ADDR2_TOG                        GIS_CH3_ADDR2_TOG_REG(GIS_BASE_PTR)
13395 #define GIS_CH3_DATA2                            GIS_CH3_DATA2_REG(GIS_BASE_PTR)
13396 #define GIS_CH3_ADDR3                            GIS_CH3_ADDR3_REG(GIS_BASE_PTR)
13397 #define GIS_CH3_ADDR3_SET                        GIS_CH3_ADDR3_SET_REG(GIS_BASE_PTR)
13398 #define GIS_CH3_ADDR3_CLR                        GIS_CH3_ADDR3_CLR_REG(GIS_BASE_PTR)
13399 #define GIS_CH3_ADDR3_TOG                        GIS_CH3_ADDR3_TOG_REG(GIS_BASE_PTR)
13400 #define GIS_CH3_DATA3                            GIS_CH3_DATA3_REG(GIS_BASE_PTR)
13401 #define GIS_CH4_CTRL                             GIS_CH4_CTRL_REG(GIS_BASE_PTR)
13402 #define GIS_CH4_CTRL_SET                         GIS_CH4_CTRL_SET_REG(GIS_BASE_PTR)
13403 #define GIS_CH4_CTRL_CLR                         GIS_CH4_CTRL_CLR_REG(GIS_BASE_PTR)
13404 #define GIS_CH4_CTRL_TOG                         GIS_CH4_CTRL_TOG_REG(GIS_BASE_PTR)
13405 #define GIS_CH4_ADDR0                            GIS_CH4_ADDR0_REG(GIS_BASE_PTR)
13406 #define GIS_CH4_ADDR0_SET                        GIS_CH4_ADDR0_SET_REG(GIS_BASE_PTR)
13407 #define GIS_CH4_ADDR0_CLR                        GIS_CH4_ADDR0_CLR_REG(GIS_BASE_PTR)
13408 #define GIS_CH4_ADDR0_TOG                        GIS_CH4_ADDR0_TOG_REG(GIS_BASE_PTR)
13409 #define GIS_CH4_DATA0                            GIS_CH4_DATA0_REG(GIS_BASE_PTR)
13410 #define GIS_CH4_ADDR1                            GIS_CH4_ADDR1_REG(GIS_BASE_PTR)
13411 #define GIS_CH4_ADDR1_SET                        GIS_CH4_ADDR1_SET_REG(GIS_BASE_PTR)
13412 #define GIS_CH4_ADDR1_CLR                        GIS_CH4_ADDR1_CLR_REG(GIS_BASE_PTR)
13413 #define GIS_CH4_ADDR1_TOG                        GIS_CH4_ADDR1_TOG_REG(GIS_BASE_PTR)
13414 #define GIS_CH4_DATA1                            GIS_CH4_DATA1_REG(GIS_BASE_PTR)
13415 #define GIS_CH4_ADDR2                            GIS_CH4_ADDR2_REG(GIS_BASE_PTR)
13416 #define GIS_CH4_ADDR2_SET                        GIS_CH4_ADDR2_SET_REG(GIS_BASE_PTR)
13417 #define GIS_CH4_ADDR2_CLR                        GIS_CH4_ADDR2_CLR_REG(GIS_BASE_PTR)
13418 #define GIS_CH4_ADDR2_TOG                        GIS_CH4_ADDR2_TOG_REG(GIS_BASE_PTR)
13419 #define GIS_CH4_DATA2                            GIS_CH4_DATA2_REG(GIS_BASE_PTR)
13420 #define GIS_CH4_ADDR3                            GIS_CH4_ADDR3_REG(GIS_BASE_PTR)
13421 #define GIS_CH4_ADDR3_SET                        GIS_CH4_ADDR3_SET_REG(GIS_BASE_PTR)
13422 #define GIS_CH4_ADDR3_CLR                        GIS_CH4_ADDR3_CLR_REG(GIS_BASE_PTR)
13423 #define GIS_CH4_ADDR3_TOG                        GIS_CH4_ADDR3_TOG_REG(GIS_BASE_PTR)
13424 #define GIS_CH4_DATA3                            GIS_CH4_DATA3_REG(GIS_BASE_PTR)
13425 #define GIS_CH5_CTRL                             GIS_CH5_CTRL_REG(GIS_BASE_PTR)
13426 #define GIS_CH5_CTRL_SET                         GIS_CH5_CTRL_SET_REG(GIS_BASE_PTR)
13427 #define GIS_CH5_CTRL_CLR                         GIS_CH5_CTRL_CLR_REG(GIS_BASE_PTR)
13428 #define GIS_CH5_CTRL_TOG                         GIS_CH5_CTRL_TOG_REG(GIS_BASE_PTR)
13429 #define GIS_CH5_ADDR0                            GIS_CH5_ADDR0_REG(GIS_BASE_PTR)
13430 #define GIS_CH5_ADDR0_SET                        GIS_CH5_ADDR0_SET_REG(GIS_BASE_PTR)
13431 #define GIS_CH5_ADDR0_CLR                        GIS_CH5_ADDR0_CLR_REG(GIS_BASE_PTR)
13432 #define GIS_CH5_ADDR0_TOG                        GIS_CH5_ADDR0_TOG_REG(GIS_BASE_PTR)
13433 #define GIS_CH5_DATA0                            GIS_CH5_DATA0_REG(GIS_BASE_PTR)
13434 #define GIS_CH5_ADDR1                            GIS_CH5_ADDR1_REG(GIS_BASE_PTR)
13435 #define GIS_CH5_ADDR1_SET                        GIS_CH5_ADDR1_SET_REG(GIS_BASE_PTR)
13436 #define GIS_CH5_ADDR1_CLR                        GIS_CH5_ADDR1_CLR_REG(GIS_BASE_PTR)
13437 #define GIS_CH5_ADDR1_TOG                        GIS_CH5_ADDR1_TOG_REG(GIS_BASE_PTR)
13438 #define GIS_CH5_DATA1                            GIS_CH5_DATA1_REG(GIS_BASE_PTR)
13439 #define GIS_CH5_ADDR2                            GIS_CH5_ADDR2_REG(GIS_BASE_PTR)
13440 #define GIS_CH5_ADDR2_SET                        GIS_CH5_ADDR2_SET_REG(GIS_BASE_PTR)
13441 #define GIS_CH5_ADDR2_CLR                        GIS_CH5_ADDR2_CLR_REG(GIS_BASE_PTR)
13442 #define GIS_CH5_ADDR2_TOG                        GIS_CH5_ADDR2_TOG_REG(GIS_BASE_PTR)
13443 #define GIS_CH5_DATA2                            GIS_CH5_DATA2_REG(GIS_BASE_PTR)
13444 #define GIS_CH5_ADDR3                            GIS_CH5_ADDR3_REG(GIS_BASE_PTR)
13445 #define GIS_CH5_ADDR3_SET                        GIS_CH5_ADDR3_SET_REG(GIS_BASE_PTR)
13446 #define GIS_CH5_ADDR3_CLR                        GIS_CH5_ADDR3_CLR_REG(GIS_BASE_PTR)
13447 #define GIS_CH5_ADDR3_TOG                        GIS_CH5_ADDR3_TOG_REG(GIS_BASE_PTR)
13448 #define GIS_CH5_DATA3                            GIS_CH5_DATA3_REG(GIS_BASE_PTR)
13449 #define GIS_DEBUG0                               GIS_DEBUG0_REG(GIS_BASE_PTR)
13450 #define GIS_DEBUG1                               GIS_DEBUG1_REG(GIS_BASE_PTR)
13451 #define GIS_VERSION                              GIS_VERSION_REG(GIS_BASE_PTR)
13452 
13453 /*!
13454  * @}
13455  */ /* end of group GIS_Register_Accessor_Macros */
13456 
13457 /*!
13458  * @}
13459  */ /* end of group GIS_Peripheral */
13460 
13461 /* ----------------------------------------------------------------------------
13462    -- GPC Peripheral Access Layer
13463    ---------------------------------------------------------------------------- */
13464 
13465 /*!
13466  * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
13467  * @{
13468  */
13469 
13470 /** GPC - Register Layout Typedef */
13471 typedef struct {
13472   __IO  uint32_t CNTR;                                   /**< GPC Interface control register, offset: 0x0 */
13473   __IO  uint32_t PGR;                                    /**< GPC Power Gating Register, offset: 0x4 */
13474   __IO  uint32_t IMR1;                                   /**< IRQ masking register 1, offset: 0x8 */
13475   __IO  uint32_t IMR2;                                   /**< IRQ masking register 2, offset: 0xC */
13476   __IO  uint32_t IMR3;                                   /**< IRQ masking register 3, offset: 0x10 */
13477   __IO  uint32_t IMR4;                                   /**< IRQ masking register 4, offset: 0x14 */
13478   __I   uint32_t ISR1;                                   /**< IRQ status resister 1, offset: 0x18 */
13479   __I   uint32_t ISR2;                                   /**< IRQ status resister 2, offset: 0x1C */
13480   __I   uint32_t ISR3;                                   /**< IRQ status resister 3, offset: 0x20 */
13481   __I   uint32_t ISR4;                                   /**< IRQ status resister 4, offset: 0x24 */
13482   __I   uint32_t A9_LPSR;                                /**< A9 Low Power Status Register, offset: 0x28 */
13483   __I   uint32_t M4_LPSR;                                /**< M4 Low Power Status Register, offset: 0x2C */
13484   __I   uint32_t DR;                                     /**< GPC Debug Register, offset: 0x30 */
13485 } GPC_Type, *GPC_MemMapPtr;
13486 
13487 /* ----------------------------------------------------------------------------
13488    -- GPC - Register accessor macros
13489    ---------------------------------------------------------------------------- */
13490 
13491 /*!
13492  * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros
13493  * @{
13494  */
13495 
13496 /* GPC - Register accessors */
13497 #define GPC_CNTR_REG(base)                       ((base)->CNTR)
13498 #define GPC_PGR_REG(base)                        ((base)->PGR)
13499 #define GPC_IMR1_REG(base)                       ((base)->IMR1)
13500 #define GPC_IMR2_REG(base)                       ((base)->IMR2)
13501 #define GPC_IMR3_REG(base)                       ((base)->IMR3)
13502 #define GPC_IMR4_REG(base)                       ((base)->IMR4)
13503 #define GPC_ISR1_REG(base)                       ((base)->ISR1)
13504 #define GPC_ISR2_REG(base)                       ((base)->ISR2)
13505 #define GPC_ISR3_REG(base)                       ((base)->ISR3)
13506 #define GPC_ISR4_REG(base)                       ((base)->ISR4)
13507 #define GPC_A9_LPSR_REG(base)                    ((base)->A9_LPSR)
13508 #define GPC_M4_LPSR_REG(base)                    ((base)->M4_LPSR)
13509 #define GPC_DR_REG(base)                         ((base)->DR)
13510 
13511 /*!
13512  * @}
13513  */ /* end of group GPC_Register_Accessor_Macros */
13514 
13515 /* ----------------------------------------------------------------------------
13516    -- GPC Register Masks
13517    ---------------------------------------------------------------------------- */
13518 
13519 /*!
13520  * @addtogroup GPC_Register_Masks GPC Register Masks
13521  * @{
13522  */
13523 
13524 /* CNTR Bit Fields */
13525 #define GPC_CNTR_gpu_vpu_pdn_req_MASK            0x1u
13526 #define GPC_CNTR_gpu_vpu_pdn_req_SHIFT           0
13527 #define GPC_CNTR_gpu_vpu_pup_req_MASK            0x2u
13528 #define GPC_CNTR_gpu_vpu_pup_req_SHIFT           1
13529 #define GPC_CNTR_MEGA_PDN_REQ_MASK               0x4u
13530 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT              2
13531 #define GPC_CNTR_MEGA_PUP_REQ_MASK               0x8u
13532 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT              3
13533 #define GPC_CNTR_DISPLAY_PDN_REQ_MASK            0x10u
13534 #define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT           4
13535 #define GPC_CNTR_DISPLAY_PUP_REQ_MASK            0x20u
13536 #define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT           5
13537 #define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK           0x40u
13538 #define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT          6
13539 #define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK           0x80u
13540 #define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT          7
13541 #define GPC_CNTR_DVFS0CR_MASK                    0x10000u
13542 #define GPC_CNTR_DVFS0CR_SHIFT                   16
13543 #define GPC_CNTR_VADC_ANALOG_OFF_MASK            0x20000u
13544 #define GPC_CNTR_VADC_ANALOG_OFF_SHIFT           17
13545 #define GPC_CNTR_VADC_EXT_PWD_N_MASK             0x40000u
13546 #define GPC_CNTR_VADC_EXT_PWD_N_SHIFT            18
13547 #define GPC_CNTR_GPCIRQM_MASK                    0x200000u
13548 #define GPC_CNTR_GPCIRQM_SHIFT                   21
13549 #define GPC_CNTR_L2_PGE_MASK                     0x400000u
13550 #define GPC_CNTR_L2_PGE_SHIFT                    22
13551 /* PGR Bit Fields */
13552 #define GPC_PGR_DRCIC_MASK                       0x60000000u
13553 #define GPC_PGR_DRCIC_SHIFT                      29
13554 #define GPC_PGR_DRCIC(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_PGR_DRCIC_SHIFT))&GPC_PGR_DRCIC_MASK)
13555 /* IMR1 Bit Fields */
13556 #define GPC_IMR1_IMR1_MASK                       0xFFFFFFFFu
13557 #define GPC_IMR1_IMR1_SHIFT                      0
13558 #define GPC_IMR1_IMR1(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_IMR1_SHIFT))&GPC_IMR1_IMR1_MASK)
13559 /* IMR2 Bit Fields */
13560 #define GPC_IMR2_IMR2_MASK                       0xFFFFFFFFu
13561 #define GPC_IMR2_IMR2_SHIFT                      0
13562 #define GPC_IMR2_IMR2(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_IMR2_SHIFT))&GPC_IMR2_IMR2_MASK)
13563 /* IMR3 Bit Fields */
13564 #define GPC_IMR3_IMR3_MASK                       0xFFFFFFFFu
13565 #define GPC_IMR3_IMR3_SHIFT                      0
13566 #define GPC_IMR3_IMR3(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_IMR3_SHIFT))&GPC_IMR3_IMR3_MASK)
13567 /* IMR4 Bit Fields */
13568 #define GPC_IMR4_IMR4_MASK                       0xFFFFFFFFu
13569 #define GPC_IMR4_IMR4_SHIFT                      0
13570 #define GPC_IMR4_IMR4(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_IMR4_SHIFT))&GPC_IMR4_IMR4_MASK)
13571 /* ISR1 Bit Fields */
13572 #define GPC_ISR1_ISR1_MASK                       0xFFFFFFFFu
13573 #define GPC_ISR1_ISR1_SHIFT                      0
13574 #define GPC_ISR1_ISR1(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_ISR1_SHIFT))&GPC_ISR1_ISR1_MASK)
13575 /* ISR2 Bit Fields */
13576 #define GPC_ISR2_ISR2_MASK                       0xFFFFFFFFu
13577 #define GPC_ISR2_ISR2_SHIFT                      0
13578 #define GPC_ISR2_ISR2(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_ISR2_SHIFT))&GPC_ISR2_ISR2_MASK)
13579 /* ISR3 Bit Fields */
13580 #define GPC_ISR3_ISR3_MASK                       0xFFFFFFFFu
13581 #define GPC_ISR3_ISR3_SHIFT                      0
13582 #define GPC_ISR3_ISR3(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_ISR3_SHIFT))&GPC_ISR3_ISR3_MASK)
13583 /* ISR4 Bit Fields */
13584 #define GPC_ISR4_ISR4_MASK                       0xFFFFFFFFu
13585 #define GPC_ISR4_ISR4_SHIFT                      0
13586 #define GPC_ISR4_ISR4(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_ISR4_SHIFT))&GPC_ISR4_ISR4_MASK)
13587 /* A9_LPSR Bit Fields */
13588 #define GPC_A9_LPSR_A9_STANDBY_WFI_MASK          0x1u
13589 #define GPC_A9_LPSR_A9_STANDBY_WFI_SHIFT         0
13590 #define GPC_A9_LPSR_A9_SCU_IDLE_MASK             0x10u
13591 #define GPC_A9_LPSR_A9_SCU_IDLE_SHIFT            4
13592 #define GPC_A9_LPSR_A9_L2CC_IDLE_MASK            0x20u
13593 #define GPC_A9_LPSR_A9_L2CC_IDLE_SHIFT           5
13594 #define GPC_A9_LPSR_A9_CLK_ENABLE_MASK           0x40u
13595 #define GPC_A9_LPSR_A9_CLK_ENABLE_SHIFT          6
13596 #define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_MASK     0x80u
13597 #define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_SHIFT    7
13598 #define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_MASK     0x100u
13599 #define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_SHIFT    8
13600 #define GPC_A9_LPSR_A9_DBG_ACK_MASK              0x200u
13601 #define GPC_A9_LPSR_A9_DBG_ACK_SHIFT             9
13602 #define GPC_A9_LPSR_A9_RST_MASK                  0x400u
13603 #define GPC_A9_LPSR_A9_RST_SHIFT                 10
13604 /* M4_LPSR Bit Fields */
13605 #define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_MASK     0x1u
13606 #define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_SHIFT    0
13607 #define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_MASK     0x2u
13608 #define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_SHIFT    1
13609 #define GPC_M4_LPSR_M4_GATE_HCLK_MASK            0x4u
13610 #define GPC_M4_LPSR_M4_GATE_HCLK_SHIFT           2
13611 #define GPC_M4_LPSR_M4_SLEEP_DEEP_MASK           0x8u
13612 #define GPC_M4_LPSR_M4_SLEEP_DEEP_SHIFT          3
13613 #define GPC_M4_LPSR_M4_SLEEPING_MASK             0x10u
13614 #define GPC_M4_LPSR_M4_SLEEPING_SHIFT            4
13615 #define GPC_M4_LPSR_M4_LOCKUP_MASK               0x20u
13616 #define GPC_M4_LPSR_M4_LOCKUP_SHIFT              5
13617 #define GPC_M4_LPSR_M4_HALTED_MASK               0x40u
13618 #define GPC_M4_LPSR_M4_HALTED_SHIFT              6
13619 #define GPC_M4_LPSR_M4_PLATFORM_RESET_B_MASK     0x80u
13620 #define GPC_M4_LPSR_M4_PLATFORM_RESET_B_SHIFT    7
13621 #define GPC_M4_LPSR_M4_CORE_RESET_B_MASK         0x100u
13622 #define GPC_M4_LPSR_M4_CORE_RESET_B_SHIFT        8
13623 /* DR Bit Fields */
13624 #define GPC_DR_PCIE_PHY_RESET_B_MASK             0x1u
13625 #define GPC_DR_PCIE_PHY_RESET_B_SHIFT            0
13626 #define GPC_DR_PCIE_PHY_ISO_MASK                 0x2u
13627 #define GPC_DR_PCIE_PHY_ISO_SHIFT                1
13628 #define GPC_DR_MEGA_RESET_B_MASK                 0x4u
13629 #define GPC_DR_MEGA_RESET_B_SHIFT                2
13630 #define GPC_DR_MEGA_SWITCH_B_MASK                0x8u
13631 #define GPC_DR_MEGA_SWITCH_B_SHIFT               3
13632 #define GPC_DR_MEGA_ISO_MASK                     0x10u
13633 #define GPC_DR_MEGA_ISO_SHIFT                    4
13634 #define GPC_DR_GPC_PUP_ACK_MASK                  0x20u
13635 #define GPC_DR_GPC_PUP_ACK_SHIFT                 5
13636 #define GPC_DR_GPC_PDN_ACK_MASK                  0x40u
13637 #define GPC_DR_GPC_PDN_ACK_SHIFT                 6
13638 #define GPC_DR_GPC_DISP_RESET_B_MASK             0x80u
13639 #define GPC_DR_GPC_DISP_RESET_B_SHIFT            7
13640 #define GPC_DR_GPC_DISP_SWITCH_B_MASK            0x100u
13641 #define GPC_DR_GPC_DISP_SWITCH_B_SHIFT           8
13642 #define GPC_DR_GPC_DISP_ISO_MASK                 0x200u
13643 #define GPC_DR_GPC_DISP_ISO_SHIFT                9
13644 #define GPC_DR_GPC_GPU_RESET_B_MASK              0x400u
13645 #define GPC_DR_GPC_GPU_RESET_B_SHIFT             10
13646 #define GPC_DR_GPC_GPU_SWITCH_B_MASK             0x800u
13647 #define GPC_DR_GPC_GPU_SWITCH_B_SHIFT            11
13648 #define GPC_DR_GPC_GPU_ISO_MASK                  0x1000u
13649 #define GPC_DR_GPC_GPU_ISO_SHIFT                 12
13650 #define GPC_DR_GPC_L2SOC_ISO_MASK                0x2000u
13651 #define GPC_DR_GPC_L2SOC_ISO_SHIFT               13
13652 #define GPC_DR_GPC_L2CPU_ISO_MASK                0x4000u
13653 #define GPC_DR_GPC_L2CPU_ISO_SHIFT               14
13654 #define GPC_DR_GPC_L2_SWITCH_B_MASK              0x8000u
13655 #define GPC_DR_GPC_L2_SWITCH_B_SHIFT             15
13656 #define GPC_DR_GPC_CPU_RESET_B_MASK              0x10000u
13657 #define GPC_DR_GPC_CPU_RESET_B_SHIFT             16
13658 #define GPC_DR_GPC_CPU_SWITCH_B_MASK             0x20000u
13659 #define GPC_DR_GPC_CPU_SWITCH_B_SHIFT            17
13660 #define GPC_DR_GPC_CPU_ISO_MASK                  0x40000u
13661 #define GPC_DR_GPC_CPU_ISO_SHIFT                 18
13662 #define GPC_DR_IPG_STOP_MASK                     0x80000u
13663 #define GPC_DR_IPG_STOP_SHIFT                    19
13664 #define GPC_DR_IPG_WAIT_MASK                     0x100000u
13665 #define GPC_DR_IPG_WAIT_SHIFT                    20
13666 
13667 /*!
13668  * @}
13669  */ /* end of group GPC_Register_Masks */
13670 
13671 /* GPC - Peripheral instance base addresses */
13672 /** Peripheral GPC base address */
13673 #define GPC_BASE                                 (0x420DC000u)
13674 /** Peripheral GPC base pointer */
13675 #define GPC                                      ((GPC_Type *)GPC_BASE)
13676 #define GPC_BASE_PTR                             (GPC)
13677 /** Array initializer of GPC peripheral base addresses */
13678 #define GPC_BASE_ADDRS                           { GPC_BASE }
13679 /** Array initializer of GPC peripheral base pointers */
13680 #define GPC_BASE_PTRS                            { GPC }
13681 /** Interrupt vectors for the GPC peripheral type */
13682 #define GPC_IRQS                                 { GPC_IRQn }
13683 
13684 /* ----------------------------------------------------------------------------
13685    -- GPC - Register accessor macros
13686    ---------------------------------------------------------------------------- */
13687 
13688 /*!
13689  * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros
13690  * @{
13691  */
13692 
13693 /* GPC - Register instance definitions */
13694 /* GPC */
13695 #define GPC_CNTR                                 GPC_CNTR_REG(GPC_BASE_PTR)
13696 #define GPC_PGR                                  GPC_PGR_REG(GPC_BASE_PTR)
13697 #define GPC_IMR1                                 GPC_IMR1_REG(GPC_BASE_PTR)
13698 #define GPC_IMR2                                 GPC_IMR2_REG(GPC_BASE_PTR)
13699 #define GPC_IMR3                                 GPC_IMR3_REG(GPC_BASE_PTR)
13700 #define GPC_IMR4                                 GPC_IMR4_REG(GPC_BASE_PTR)
13701 #define GPC_ISR1                                 GPC_ISR1_REG(GPC_BASE_PTR)
13702 #define GPC_ISR2                                 GPC_ISR2_REG(GPC_BASE_PTR)
13703 #define GPC_ISR3                                 GPC_ISR3_REG(GPC_BASE_PTR)
13704 #define GPC_ISR4                                 GPC_ISR4_REG(GPC_BASE_PTR)
13705 #define GPC_A9_LPSR                              GPC_A9_LPSR_REG(GPC_BASE_PTR)
13706 #define GPC_M4_LPSR                              GPC_M4_LPSR_REG(GPC_BASE_PTR)
13707 #define GPC_DR                                   GPC_DR_REG(GPC_BASE_PTR)
13708 
13709 /*!
13710  * @}
13711  */ /* end of group GPC_Register_Accessor_Macros */
13712 
13713 /*!
13714  * @}
13715  */ /* end of group GPC_Peripheral */
13716 
13717 /* ----------------------------------------------------------------------------
13718    -- GPIO Peripheral Access Layer
13719    ---------------------------------------------------------------------------- */
13720 
13721 /*!
13722  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
13723  * @{
13724  */
13725 
13726 /** GPIO - Register Layout Typedef */
13727 typedef struct {
13728   __IO  uint32_t DR;                                     /**< GPIO data register, offset: 0x0 */
13729   __IO  uint32_t GDIR;                                   /**< GPIO direction register, offset: 0x4 */
13730   __I   uint32_t PSR;                                    /**< GPIO pad status register, offset: 0x8 */
13731   __IO  uint32_t ICR1;                                   /**< GPIO interrupt configuration register1, offset: 0xC */
13732   __IO  uint32_t ICR2;                                   /**< GPIO interrupt configuration register2, offset: 0x10 */
13733   __IO  uint32_t IMR;                                    /**< GPIO interrupt mask register, offset: 0x14 */
13734   __IO  uint32_t ISR;                                    /**< GPIO interrupt status register, offset: 0x18 */
13735   __IO  uint32_t EDGE_SEL;                               /**< GPIO edge select register, offset: 0x1C */
13736 } GPIO_Type, *GPIO_MemMapPtr;
13737 
13738 /* ----------------------------------------------------------------------------
13739    -- GPIO - Register accessor macros
13740    ---------------------------------------------------------------------------- */
13741 
13742 /*!
13743  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
13744  * @{
13745  */
13746 
13747 /* GPIO - Register accessors */
13748 #define GPIO_DR_REG(base)                        ((base)->DR)
13749 #define GPIO_GDIR_REG(base)                      ((base)->GDIR)
13750 #define GPIO_PSR_REG(base)                       ((base)->PSR)
13751 #define GPIO_ICR1_REG(base)                      ((base)->ICR1)
13752 #define GPIO_ICR2_REG(base)                      ((base)->ICR2)
13753 #define GPIO_IMR_REG(base)                       ((base)->IMR)
13754 #define GPIO_ISR_REG(base)                       ((base)->ISR)
13755 #define GPIO_EDGE_SEL_REG(base)                  ((base)->EDGE_SEL)
13756 
13757 /*!
13758  * @}
13759  */ /* end of group GPIO_Register_Accessor_Macros */
13760 
13761 /* ----------------------------------------------------------------------------
13762    -- GPIO Register Masks
13763    ---------------------------------------------------------------------------- */
13764 
13765 /*!
13766  * @addtogroup GPIO_Register_Masks GPIO Register Masks
13767  * @{
13768  */
13769 
13770 /* DR Bit Fields */
13771 #define GPIO_DR_DR_MASK                          0xFFFFFFFFu
13772 #define GPIO_DR_DR_SHIFT                         0
13773 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x))<<GPIO_DR_DR_SHIFT))&GPIO_DR_DR_MASK)
13774 /* GDIR Bit Fields */
13775 #define GPIO_GDIR_GDIR_MASK                      0xFFFFFFFFu
13776 #define GPIO_GDIR_GDIR_SHIFT                     0
13777 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_GDIR_GDIR_SHIFT))&GPIO_GDIR_GDIR_MASK)
13778 /* PSR Bit Fields */
13779 #define GPIO_PSR_PSR_MASK                        0xFFFFFFFFu
13780 #define GPIO_PSR_PSR_SHIFT                       0
13781 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_PSR_PSR_SHIFT))&GPIO_PSR_PSR_MASK)
13782 /* ICR1 Bit Fields */
13783 #define GPIO_ICR1_ICR0_MASK                      0x3u
13784 #define GPIO_ICR1_ICR0_SHIFT                     0
13785 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK)
13786 #define GPIO_ICR1_ICR1_MASK                      0xCu
13787 #define GPIO_ICR1_ICR1_SHIFT                     2
13788 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR1_SHIFT))&GPIO_ICR1_ICR1_MASK)
13789 #define GPIO_ICR1_ICR2_MASK                      0x30u
13790 #define GPIO_ICR1_ICR2_SHIFT                     4
13791 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR2_SHIFT))&GPIO_ICR1_ICR2_MASK)
13792 #define GPIO_ICR1_ICR3_MASK                      0xC0u
13793 #define GPIO_ICR1_ICR3_SHIFT                     6
13794 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR3_SHIFT))&GPIO_ICR1_ICR3_MASK)
13795 #define GPIO_ICR1_ICR4_MASK                      0x300u
13796 #define GPIO_ICR1_ICR4_SHIFT                     8
13797 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR4_SHIFT))&GPIO_ICR1_ICR4_MASK)
13798 #define GPIO_ICR1_ICR5_MASK                      0xC00u
13799 #define GPIO_ICR1_ICR5_SHIFT                     10
13800 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR5_SHIFT))&GPIO_ICR1_ICR5_MASK)
13801 #define GPIO_ICR1_ICR6_MASK                      0x3000u
13802 #define GPIO_ICR1_ICR6_SHIFT                     12
13803 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR6_SHIFT))&GPIO_ICR1_ICR6_MASK)
13804 #define GPIO_ICR1_ICR7_MASK                      0xC000u
13805 #define GPIO_ICR1_ICR7_SHIFT                     14
13806 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR7_SHIFT))&GPIO_ICR1_ICR7_MASK)
13807 #define GPIO_ICR1_ICR8_MASK                      0x30000u
13808 #define GPIO_ICR1_ICR8_SHIFT                     16
13809 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR8_SHIFT))&GPIO_ICR1_ICR8_MASK)
13810 #define GPIO_ICR1_ICR9_MASK                      0xC0000u
13811 #define GPIO_ICR1_ICR9_SHIFT                     18
13812 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR9_SHIFT))&GPIO_ICR1_ICR9_MASK)
13813 #define GPIO_ICR1_ICR10_MASK                     0x300000u
13814 #define GPIO_ICR1_ICR10_SHIFT                    20
13815 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR10_SHIFT))&GPIO_ICR1_ICR10_MASK)
13816 #define GPIO_ICR1_ICR11_MASK                     0xC00000u
13817 #define GPIO_ICR1_ICR11_SHIFT                    22
13818 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR11_SHIFT))&GPIO_ICR1_ICR11_MASK)
13819 #define GPIO_ICR1_ICR12_MASK                     0x3000000u
13820 #define GPIO_ICR1_ICR12_SHIFT                    24
13821 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR12_SHIFT))&GPIO_ICR1_ICR12_MASK)
13822 #define GPIO_ICR1_ICR13_MASK                     0xC000000u
13823 #define GPIO_ICR1_ICR13_SHIFT                    26
13824 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR13_SHIFT))&GPIO_ICR1_ICR13_MASK)
13825 #define GPIO_ICR1_ICR14_MASK                     0x30000000u
13826 #define GPIO_ICR1_ICR14_SHIFT                    28
13827 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR14_SHIFT))&GPIO_ICR1_ICR14_MASK)
13828 #define GPIO_ICR1_ICR15_MASK                     0xC0000000u
13829 #define GPIO_ICR1_ICR15_SHIFT                    30
13830 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR15_SHIFT))&GPIO_ICR1_ICR15_MASK)
13831 /* ICR2 Bit Fields */
13832 #define GPIO_ICR2_ICR16_MASK                     0x3u
13833 #define GPIO_ICR2_ICR16_SHIFT                    0
13834 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR16_SHIFT))&GPIO_ICR2_ICR16_MASK)
13835 #define GPIO_ICR2_ICR17_MASK                     0xCu
13836 #define GPIO_ICR2_ICR17_SHIFT                    2
13837 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR17_SHIFT))&GPIO_ICR2_ICR17_MASK)
13838 #define GPIO_ICR2_ICR18_MASK                     0x30u
13839 #define GPIO_ICR2_ICR18_SHIFT                    4
13840 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR18_SHIFT))&GPIO_ICR2_ICR18_MASK)
13841 #define GPIO_ICR2_ICR19_MASK                     0xC0u
13842 #define GPIO_ICR2_ICR19_SHIFT                    6
13843 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR19_SHIFT))&GPIO_ICR2_ICR19_MASK)
13844 #define GPIO_ICR2_ICR20_MASK                     0x300u
13845 #define GPIO_ICR2_ICR20_SHIFT                    8
13846 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR20_SHIFT))&GPIO_ICR2_ICR20_MASK)
13847 #define GPIO_ICR2_ICR21_MASK                     0xC00u
13848 #define GPIO_ICR2_ICR21_SHIFT                    10
13849 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR21_SHIFT))&GPIO_ICR2_ICR21_MASK)
13850 #define GPIO_ICR2_ICR22_MASK                     0x3000u
13851 #define GPIO_ICR2_ICR22_SHIFT                    12
13852 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR22_SHIFT))&GPIO_ICR2_ICR22_MASK)
13853 #define GPIO_ICR2_ICR23_MASK                     0xC000u
13854 #define GPIO_ICR2_ICR23_SHIFT                    14
13855 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR23_SHIFT))&GPIO_ICR2_ICR23_MASK)
13856 #define GPIO_ICR2_ICR24_MASK                     0x30000u
13857 #define GPIO_ICR2_ICR24_SHIFT                    16
13858 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR24_SHIFT))&GPIO_ICR2_ICR24_MASK)
13859 #define GPIO_ICR2_ICR25_MASK                     0xC0000u
13860 #define GPIO_ICR2_ICR25_SHIFT                    18
13861 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR25_SHIFT))&GPIO_ICR2_ICR25_MASK)
13862 #define GPIO_ICR2_ICR26_MASK                     0x300000u
13863 #define GPIO_ICR2_ICR26_SHIFT                    20
13864 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR26_SHIFT))&GPIO_ICR2_ICR26_MASK)
13865 #define GPIO_ICR2_ICR27_MASK                     0xC00000u
13866 #define GPIO_ICR2_ICR27_SHIFT                    22
13867 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR27_SHIFT))&GPIO_ICR2_ICR27_MASK)
13868 #define GPIO_ICR2_ICR28_MASK                     0x3000000u
13869 #define GPIO_ICR2_ICR28_SHIFT                    24
13870 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR28_SHIFT))&GPIO_ICR2_ICR28_MASK)
13871 #define GPIO_ICR2_ICR29_MASK                     0xC000000u
13872 #define GPIO_ICR2_ICR29_SHIFT                    26
13873 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR29_SHIFT))&GPIO_ICR2_ICR29_MASK)
13874 #define GPIO_ICR2_ICR30_MASK                     0x30000000u
13875 #define GPIO_ICR2_ICR30_SHIFT                    28
13876 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR30_SHIFT))&GPIO_ICR2_ICR30_MASK)
13877 #define GPIO_ICR2_ICR31_MASK                     0xC0000000u
13878 #define GPIO_ICR2_ICR31_SHIFT                    30
13879 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR31_SHIFT))&GPIO_ICR2_ICR31_MASK)
13880 /* IMR Bit Fields */
13881 #define GPIO_IMR_IMR_MASK                        0xFFFFFFFFu
13882 #define GPIO_IMR_IMR_SHIFT                       0
13883 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_IMR_IMR_SHIFT))&GPIO_IMR_IMR_MASK)
13884 /* ISR Bit Fields */
13885 #define GPIO_ISR_ISR_MASK                        0xFFFFFFFFu
13886 #define GPIO_ISR_ISR_SHIFT                       0
13887 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x))<<GPIO_ISR_ISR_SHIFT))&GPIO_ISR_ISR_MASK)
13888 /* EDGE_SEL Bit Fields */
13889 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         0xFFFFFFFFu
13890 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        0
13891 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x))<<GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT))&GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
13892 
13893 /*!
13894  * @}
13895  */ /* end of group GPIO_Register_Masks */
13896 
13897 /* GPIO - Peripheral instance base addresses */
13898 /** Peripheral GPIO1 base address */
13899 #define GPIO1_BASE                               (0x4209C000u)
13900 /** Peripheral GPIO1 base pointer */
13901 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
13902 #define GPIO1_BASE_PTR                           (GPIO1)
13903 /** Peripheral GPIO2 base address */
13904 #define GPIO2_BASE                               (0x420A0000u)
13905 /** Peripheral GPIO2 base pointer */
13906 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
13907 #define GPIO2_BASE_PTR                           (GPIO2)
13908 /** Peripheral GPIO3 base address */
13909 #define GPIO3_BASE                               (0x420A4000u)
13910 /** Peripheral GPIO3 base pointer */
13911 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
13912 #define GPIO3_BASE_PTR                           (GPIO3)
13913 /** Peripheral GPIO4 base address */
13914 #define GPIO4_BASE                               (0x420A8000u)
13915 /** Peripheral GPIO4 base pointer */
13916 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
13917 #define GPIO4_BASE_PTR                           (GPIO4)
13918 /** Peripheral GPIO5 base address */
13919 #define GPIO5_BASE                               (0x420AC000u)
13920 /** Peripheral GPIO5 base pointer */
13921 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
13922 #define GPIO5_BASE_PTR                           (GPIO5)
13923 /** Peripheral GPIO6 base address */
13924 #define GPIO6_BASE                               (0x420B0000u)
13925 /** Peripheral GPIO6 base pointer */
13926 #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
13927 #define GPIO6_BASE_PTR                           (GPIO6)
13928 /** Peripheral GPIO7 base address */
13929 #define GPIO7_BASE                               (0x420B4000u)
13930 /** Peripheral GPIO7 base pointer */
13931 #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
13932 #define GPIO7_BASE_PTR                           (GPIO7)
13933 /** Array initializer of GPIO peripheral base addresses */
13934 #define GPIO_BASE_ADDRS                          { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE }
13935 /** Array initializer of GPIO peripheral base pointers */
13936 #define GPIO_BASE_PTRS                           { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7 }
13937 
13938 /* ----------------------------------------------------------------------------
13939    -- GPIO - Register accessor macros
13940    ---------------------------------------------------------------------------- */
13941 
13942 /*!
13943  * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
13944  * @{
13945  */
13946 
13947 /* GPIO - Register instance definitions */
13948 /* GPIO1 */
13949 #define GPIO1_DR                                 GPIO_DR_REG(GPIO1_BASE_PTR)
13950 #define GPIO1_GDIR                               GPIO_GDIR_REG(GPIO1_BASE_PTR)
13951 #define GPIO1_PSR                                GPIO_PSR_REG(GPIO1_BASE_PTR)
13952 #define GPIO1_ICR1                               GPIO_ICR1_REG(GPIO1_BASE_PTR)
13953 #define GPIO1_ICR2                               GPIO_ICR2_REG(GPIO1_BASE_PTR)
13954 #define GPIO1_IMR                                GPIO_IMR_REG(GPIO1_BASE_PTR)
13955 #define GPIO1_ISR                                GPIO_ISR_REG(GPIO1_BASE_PTR)
13956 #define GPIO1_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO1_BASE_PTR)
13957 /* GPIO2 */
13958 #define GPIO2_DR                                 GPIO_DR_REG(GPIO2_BASE_PTR)
13959 #define GPIO2_GDIR                               GPIO_GDIR_REG(GPIO2_BASE_PTR)
13960 #define GPIO2_PSR                                GPIO_PSR_REG(GPIO2_BASE_PTR)
13961 #define GPIO2_ICR1                               GPIO_ICR1_REG(GPIO2_BASE_PTR)
13962 #define GPIO2_ICR2                               GPIO_ICR2_REG(GPIO2_BASE_PTR)
13963 #define GPIO2_IMR                                GPIO_IMR_REG(GPIO2_BASE_PTR)
13964 #define GPIO2_ISR                                GPIO_ISR_REG(GPIO2_BASE_PTR)
13965 #define GPIO2_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO2_BASE_PTR)
13966 /* GPIO3 */
13967 #define GPIO3_DR                                 GPIO_DR_REG(GPIO3_BASE_PTR)
13968 #define GPIO3_GDIR                               GPIO_GDIR_REG(GPIO3_BASE_PTR)
13969 #define GPIO3_PSR                                GPIO_PSR_REG(GPIO3_BASE_PTR)
13970 #define GPIO3_ICR1                               GPIO_ICR1_REG(GPIO3_BASE_PTR)
13971 #define GPIO3_ICR2                               GPIO_ICR2_REG(GPIO3_BASE_PTR)
13972 #define GPIO3_IMR                                GPIO_IMR_REG(GPIO3_BASE_PTR)
13973 #define GPIO3_ISR                                GPIO_ISR_REG(GPIO3_BASE_PTR)
13974 #define GPIO3_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO3_BASE_PTR)
13975 /* GPIO4 */
13976 #define GPIO4_DR                                 GPIO_DR_REG(GPIO4_BASE_PTR)
13977 #define GPIO4_GDIR                               GPIO_GDIR_REG(GPIO4_BASE_PTR)
13978 #define GPIO4_PSR                                GPIO_PSR_REG(GPIO4_BASE_PTR)
13979 #define GPIO4_ICR1                               GPIO_ICR1_REG(GPIO4_BASE_PTR)
13980 #define GPIO4_ICR2                               GPIO_ICR2_REG(GPIO4_BASE_PTR)
13981 #define GPIO4_IMR                                GPIO_IMR_REG(GPIO4_BASE_PTR)
13982 #define GPIO4_ISR                                GPIO_ISR_REG(GPIO4_BASE_PTR)
13983 #define GPIO4_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO4_BASE_PTR)
13984 /* GPIO5 */
13985 #define GPIO5_DR                                 GPIO_DR_REG(GPIO5_BASE_PTR)
13986 #define GPIO5_GDIR                               GPIO_GDIR_REG(GPIO5_BASE_PTR)
13987 #define GPIO5_PSR                                GPIO_PSR_REG(GPIO5_BASE_PTR)
13988 #define GPIO5_ICR1                               GPIO_ICR1_REG(GPIO5_BASE_PTR)
13989 #define GPIO5_ICR2                               GPIO_ICR2_REG(GPIO5_BASE_PTR)
13990 #define GPIO5_IMR                                GPIO_IMR_REG(GPIO5_BASE_PTR)
13991 #define GPIO5_ISR                                GPIO_ISR_REG(GPIO5_BASE_PTR)
13992 #define GPIO5_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO5_BASE_PTR)
13993 /* GPIO6 */
13994 #define GPIO6_DR                                 GPIO_DR_REG(GPIO6_BASE_PTR)
13995 #define GPIO6_GDIR                               GPIO_GDIR_REG(GPIO6_BASE_PTR)
13996 #define GPIO6_PSR                                GPIO_PSR_REG(GPIO6_BASE_PTR)
13997 #define GPIO6_ICR1                               GPIO_ICR1_REG(GPIO6_BASE_PTR)
13998 #define GPIO6_ICR2                               GPIO_ICR2_REG(GPIO6_BASE_PTR)
13999 #define GPIO6_IMR                                GPIO_IMR_REG(GPIO6_BASE_PTR)
14000 #define GPIO6_ISR                                GPIO_ISR_REG(GPIO6_BASE_PTR)
14001 #define GPIO6_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO6_BASE_PTR)
14002 /* GPIO7 */
14003 #define GPIO7_DR                                 GPIO_DR_REG(GPIO7_BASE_PTR)
14004 #define GPIO7_GDIR                               GPIO_GDIR_REG(GPIO7_BASE_PTR)
14005 #define GPIO7_PSR                                GPIO_PSR_REG(GPIO7_BASE_PTR)
14006 #define GPIO7_ICR1                               GPIO_ICR1_REG(GPIO7_BASE_PTR)
14007 #define GPIO7_ICR2                               GPIO_ICR2_REG(GPIO7_BASE_PTR)
14008 #define GPIO7_IMR                                GPIO_IMR_REG(GPIO7_BASE_PTR)
14009 #define GPIO7_ISR                                GPIO_ISR_REG(GPIO7_BASE_PTR)
14010 #define GPIO7_EDGE_SEL                           GPIO_EDGE_SEL_REG(GPIO7_BASE_PTR)
14011 
14012 /*!
14013  * @}
14014  */ /* end of group GPIO_Register_Accessor_Macros */
14015 
14016 /*!
14017  * @}
14018  */ /* end of group GPIO_Peripheral */
14019 
14020 /* ----------------------------------------------------------------------------
14021    -- GPMI Peripheral Access Layer
14022    ---------------------------------------------------------------------------- */
14023 
14024 /*!
14025  * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
14026  * @{
14027  */
14028 
14029 /** GPMI - Register Layout Typedef */
14030 typedef struct {
14031   __IO  uint32_t CTRL0;                                  /**< GPMI Control Register 0 Description, offset: 0x0 */
14032   __IO  uint32_t CTRL0_SET;                              /**< GPMI Control Register 0 Description, offset: 0x4 */
14033   __IO  uint32_t CTRL0_CLR;                              /**< GPMI Control Register 0 Description, offset: 0x8 */
14034   __IO  uint32_t CTRL0_TOG;                              /**< GPMI Control Register 0 Description, offset: 0xC */
14035   __IO  uint32_t COMPARE;                                /**< GPMI Compare Register Description, offset: 0x10 */
14036   uint8_t RESERVED_0[12];
14037   __IO  uint32_t ECCCTRL;                                /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
14038   __IO  uint32_t ECCCTRL_SET;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
14039   __IO  uint32_t ECCCTRL_CLR;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
14040   __IO  uint32_t ECCCTRL_TOG;                            /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
14041   __IO  uint32_t ECCCOUNT;                               /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
14042   uint8_t RESERVED_1[12];
14043   __IO  uint32_t PAYLOAD;                                /**< GPMI Payload Address Register Description, offset: 0x40 */
14044   uint8_t RESERVED_2[12];
14045   __IO  uint32_t AUXILIARY;                              /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
14046   uint8_t RESERVED_3[12];
14047   __IO  uint32_t CTRL1;                                  /**< GPMI Control Register 1 Description, offset: 0x60 */
14048   __IO  uint32_t CTRL1_SET;                              /**< GPMI Control Register 1 Description, offset: 0x64 */
14049   __IO  uint32_t CTRL1_CLR;                              /**< GPMI Control Register 1 Description, offset: 0x68 */
14050   __IO  uint32_t CTRL1_TOG;                              /**< GPMI Control Register 1 Description, offset: 0x6C */
14051   __IO  uint32_t TIMING0;                                /**< GPMI Timing Register 0 Description, offset: 0x70 */
14052   uint8_t RESERVED_4[12];
14053   __IO  uint32_t TIMING1;                                /**< GPMI Timing Register 1 Description, offset: 0x80 */
14054   uint8_t RESERVED_5[12];
14055   __IO  uint32_t TIMING2;                                /**< GPMI Timing Register 2 Description, offset: 0x90 */
14056   uint8_t RESERVED_6[12];
14057   __IO  uint32_t DATA;                                   /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
14058   uint8_t RESERVED_7[12];
14059   __I   uint32_t STAT;                                   /**< GPMI Status Register Description, offset: 0xB0 */
14060   uint8_t RESERVED_8[12];
14061   __I   uint32_t DEBUG;                                  /**< GPMI Debug Information Register Description, offset: 0xC0 */
14062   uint8_t RESERVED_9[12];
14063   __I   uint32_t VERSION;                                /**< GPMI Version Register Description, offset: 0xD0 */
14064   uint8_t RESERVED_10[12];
14065   __IO  uint32_t DEBUG2;                                 /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
14066   uint8_t RESERVED_11[12];
14067   __I   uint32_t DEBUG3;                                 /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
14068   uint8_t RESERVED_12[12];
14069   __IO  uint32_t READ_DDR_DLL_CTRL;                      /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
14070   uint8_t RESERVED_13[12];
14071   __IO  uint32_t WRITE_DDR_DLL_CTRL;                     /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
14072   uint8_t RESERVED_14[12];
14073   __I   uint32_t READ_DDR_DLL_STS;                       /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
14074   uint8_t RESERVED_15[12];
14075   __I   uint32_t WRITE_DDR_DLL_STS;                      /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
14076 } GPMI_Type, *GPMI_MemMapPtr;
14077 
14078 /* ----------------------------------------------------------------------------
14079    -- GPMI - Register accessor macros
14080    ---------------------------------------------------------------------------- */
14081 
14082 /*!
14083  * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros
14084  * @{
14085  */
14086 
14087 /* GPMI - Register accessors */
14088 #define GPMI_CTRL0_REG(base)                     ((base)->CTRL0)
14089 #define GPMI_CTRL0_SET_REG(base)                 ((base)->CTRL0_SET)
14090 #define GPMI_CTRL0_CLR_REG(base)                 ((base)->CTRL0_CLR)
14091 #define GPMI_CTRL0_TOG_REG(base)                 ((base)->CTRL0_TOG)
14092 #define GPMI_COMPARE_REG(base)                   ((base)->COMPARE)
14093 #define GPMI_ECCCTRL_REG(base)                   ((base)->ECCCTRL)
14094 #define GPMI_ECCCTRL_SET_REG(base)               ((base)->ECCCTRL_SET)
14095 #define GPMI_ECCCTRL_CLR_REG(base)               ((base)->ECCCTRL_CLR)
14096 #define GPMI_ECCCTRL_TOG_REG(base)               ((base)->ECCCTRL_TOG)
14097 #define GPMI_ECCCOUNT_REG(base)                  ((base)->ECCCOUNT)
14098 #define GPMI_PAYLOAD_REG(base)                   ((base)->PAYLOAD)
14099 #define GPMI_AUXILIARY_REG(base)                 ((base)->AUXILIARY)
14100 #define GPMI_CTRL1_REG(base)                     ((base)->CTRL1)
14101 #define GPMI_CTRL1_SET_REG(base)                 ((base)->CTRL1_SET)
14102 #define GPMI_CTRL1_CLR_REG(base)                 ((base)->CTRL1_CLR)
14103 #define GPMI_CTRL1_TOG_REG(base)                 ((base)->CTRL1_TOG)
14104 #define GPMI_TIMING0_REG(base)                   ((base)->TIMING0)
14105 #define GPMI_TIMING1_REG(base)                   ((base)->TIMING1)
14106 #define GPMI_TIMING2_REG(base)                   ((base)->TIMING2)
14107 #define GPMI_DATA_REG(base)                      ((base)->DATA)
14108 #define GPMI_STAT_REG(base)                      ((base)->STAT)
14109 #define GPMI_DEBUG_REG(base)                     ((base)->DEBUG)
14110 #define GPMI_VERSION_REG(base)                   ((base)->VERSION)
14111 #define GPMI_DEBUG2_REG(base)                    ((base)->DEBUG2)
14112 #define GPMI_DEBUG3_REG(base)                    ((base)->DEBUG3)
14113 #define GPMI_READ_DDR_DLL_CTRL_REG(base)         ((base)->READ_DDR_DLL_CTRL)
14114 #define GPMI_WRITE_DDR_DLL_CTRL_REG(base)        ((base)->WRITE_DDR_DLL_CTRL)
14115 #define GPMI_READ_DDR_DLL_STS_REG(base)          ((base)->READ_DDR_DLL_STS)
14116 #define GPMI_WRITE_DDR_DLL_STS_REG(base)         ((base)->WRITE_DDR_DLL_STS)
14117 
14118 /*!
14119  * @}
14120  */ /* end of group GPMI_Register_Accessor_Macros */
14121 
14122 /* ----------------------------------------------------------------------------
14123    -- GPMI Register Masks
14124    ---------------------------------------------------------------------------- */
14125 
14126 /*!
14127  * @addtogroup GPMI_Register_Masks GPMI Register Masks
14128  * @{
14129  */
14130 
14131 /* CTRL0 Bit Fields */
14132 #define GPMI_CTRL0_XFER_COUNT_MASK               0xFFFFu
14133 #define GPMI_CTRL0_XFER_COUNT_SHIFT              0
14134 #define GPMI_CTRL0_XFER_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_XFER_COUNT_SHIFT))&GPMI_CTRL0_XFER_COUNT_MASK)
14135 #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK        0x10000u
14136 #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT       16
14137 #define GPMI_CTRL0_ADDRESS_MASK                  0xE0000u
14138 #define GPMI_CTRL0_ADDRESS_SHIFT                 17
14139 #define GPMI_CTRL0_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_ADDRESS_SHIFT))&GPMI_CTRL0_ADDRESS_MASK)
14140 #define GPMI_CTRL0_CS_MASK                       0x700000u
14141 #define GPMI_CTRL0_CS_SHIFT                      20
14142 #define GPMI_CTRL0_CS(x)                         (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CS_SHIFT))&GPMI_CTRL0_CS_MASK)
14143 #define GPMI_CTRL0_WORD_LENGTH_MASK              0x800000u
14144 #define GPMI_CTRL0_WORD_LENGTH_SHIFT             23
14145 #define GPMI_CTRL0_COMMAND_MODE_MASK             0x3000000u
14146 #define GPMI_CTRL0_COMMAND_MODE_SHIFT            24
14147 #define GPMI_CTRL0_COMMAND_MODE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_COMMAND_MODE_SHIFT))&GPMI_CTRL0_COMMAND_MODE_MASK)
14148 #define GPMI_CTRL0_UDMA_MASK                     0x4000000u
14149 #define GPMI_CTRL0_UDMA_SHIFT                    26
14150 #define GPMI_CTRL0_LOCK_CS_MASK                  0x8000000u
14151 #define GPMI_CTRL0_LOCK_CS_SHIFT                 27
14152 #define GPMI_CTRL0_DEV_IRQ_EN_MASK               0x10000000u
14153 #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT              28
14154 #define GPMI_CTRL0_RUN_MASK                      0x20000000u
14155 #define GPMI_CTRL0_RUN_SHIFT                     29
14156 #define GPMI_CTRL0_CLKGATE_MASK                  0x40000000u
14157 #define GPMI_CTRL0_CLKGATE_SHIFT                 30
14158 #define GPMI_CTRL0_SFTRST_MASK                   0x80000000u
14159 #define GPMI_CTRL0_SFTRST_SHIFT                  31
14160 /* CTRL0_SET Bit Fields */
14161 #define GPMI_CTRL0_SET_XFER_COUNT_MASK           0xFFFFu
14162 #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT          0
14163 #define GPMI_CTRL0_SET_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_XFER_COUNT_SHIFT))&GPMI_CTRL0_SET_XFER_COUNT_MASK)
14164 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK    0x10000u
14165 #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT   16
14166 #define GPMI_CTRL0_SET_ADDRESS_MASK              0xE0000u
14167 #define GPMI_CTRL0_SET_ADDRESS_SHIFT             17
14168 #define GPMI_CTRL0_SET_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_ADDRESS_SHIFT))&GPMI_CTRL0_SET_ADDRESS_MASK)
14169 #define GPMI_CTRL0_SET_CS_MASK                   0x700000u
14170 #define GPMI_CTRL0_SET_CS_SHIFT                  20
14171 #define GPMI_CTRL0_SET_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_CS_SHIFT))&GPMI_CTRL0_SET_CS_MASK)
14172 #define GPMI_CTRL0_SET_WORD_LENGTH_MASK          0x800000u
14173 #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT         23
14174 #define GPMI_CTRL0_SET_COMMAND_MODE_MASK         0x3000000u
14175 #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT        24
14176 #define GPMI_CTRL0_SET_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_COMMAND_MODE_SHIFT))&GPMI_CTRL0_SET_COMMAND_MODE_MASK)
14177 #define GPMI_CTRL0_SET_UDMA_MASK                 0x4000000u
14178 #define GPMI_CTRL0_SET_UDMA_SHIFT                26
14179 #define GPMI_CTRL0_SET_LOCK_CS_MASK              0x8000000u
14180 #define GPMI_CTRL0_SET_LOCK_CS_SHIFT             27
14181 #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK           0x10000000u
14182 #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT          28
14183 #define GPMI_CTRL0_SET_RUN_MASK                  0x20000000u
14184 #define GPMI_CTRL0_SET_RUN_SHIFT                 29
14185 #define GPMI_CTRL0_SET_CLKGATE_MASK              0x40000000u
14186 #define GPMI_CTRL0_SET_CLKGATE_SHIFT             30
14187 #define GPMI_CTRL0_SET_SFTRST_MASK               0x80000000u
14188 #define GPMI_CTRL0_SET_SFTRST_SHIFT              31
14189 /* CTRL0_CLR Bit Fields */
14190 #define GPMI_CTRL0_CLR_XFER_COUNT_MASK           0xFFFFu
14191 #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT          0
14192 #define GPMI_CTRL0_CLR_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_XFER_COUNT_SHIFT))&GPMI_CTRL0_CLR_XFER_COUNT_MASK)
14193 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK    0x10000u
14194 #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT   16
14195 #define GPMI_CTRL0_CLR_ADDRESS_MASK              0xE0000u
14196 #define GPMI_CTRL0_CLR_ADDRESS_SHIFT             17
14197 #define GPMI_CTRL0_CLR_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_ADDRESS_SHIFT))&GPMI_CTRL0_CLR_ADDRESS_MASK)
14198 #define GPMI_CTRL0_CLR_CS_MASK                   0x700000u
14199 #define GPMI_CTRL0_CLR_CS_SHIFT                  20
14200 #define GPMI_CTRL0_CLR_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_CS_SHIFT))&GPMI_CTRL0_CLR_CS_MASK)
14201 #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK          0x800000u
14202 #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT         23
14203 #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK         0x3000000u
14204 #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT        24
14205 #define GPMI_CTRL0_CLR_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT))&GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
14206 #define GPMI_CTRL0_CLR_UDMA_MASK                 0x4000000u
14207 #define GPMI_CTRL0_CLR_UDMA_SHIFT                26
14208 #define GPMI_CTRL0_CLR_LOCK_CS_MASK              0x8000000u
14209 #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT             27
14210 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK           0x10000000u
14211 #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT          28
14212 #define GPMI_CTRL0_CLR_RUN_MASK                  0x20000000u
14213 #define GPMI_CTRL0_CLR_RUN_SHIFT                 29
14214 #define GPMI_CTRL0_CLR_CLKGATE_MASK              0x40000000u
14215 #define GPMI_CTRL0_CLR_CLKGATE_SHIFT             30
14216 #define GPMI_CTRL0_CLR_SFTRST_MASK               0x80000000u
14217 #define GPMI_CTRL0_CLR_SFTRST_SHIFT              31
14218 /* CTRL0_TOG Bit Fields */
14219 #define GPMI_CTRL0_TOG_XFER_COUNT_MASK           0xFFFFu
14220 #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT          0
14221 #define GPMI_CTRL0_TOG_XFER_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_XFER_COUNT_SHIFT))&GPMI_CTRL0_TOG_XFER_COUNT_MASK)
14222 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK    0x10000u
14223 #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT   16
14224 #define GPMI_CTRL0_TOG_ADDRESS_MASK              0xE0000u
14225 #define GPMI_CTRL0_TOG_ADDRESS_SHIFT             17
14226 #define GPMI_CTRL0_TOG_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_ADDRESS_SHIFT))&GPMI_CTRL0_TOG_ADDRESS_MASK)
14227 #define GPMI_CTRL0_TOG_CS_MASK                   0x700000u
14228 #define GPMI_CTRL0_TOG_CS_SHIFT                  20
14229 #define GPMI_CTRL0_TOG_CS(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_CS_SHIFT))&GPMI_CTRL0_TOG_CS_MASK)
14230 #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK          0x800000u
14231 #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT         23
14232 #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK         0x3000000u
14233 #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT        24
14234 #define GPMI_CTRL0_TOG_COMMAND_MODE(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT))&GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
14235 #define GPMI_CTRL0_TOG_UDMA_MASK                 0x4000000u
14236 #define GPMI_CTRL0_TOG_UDMA_SHIFT                26
14237 #define GPMI_CTRL0_TOG_LOCK_CS_MASK              0x8000000u
14238 #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT             27
14239 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK           0x10000000u
14240 #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT          28
14241 #define GPMI_CTRL0_TOG_RUN_MASK                  0x20000000u
14242 #define GPMI_CTRL0_TOG_RUN_SHIFT                 29
14243 #define GPMI_CTRL0_TOG_CLKGATE_MASK              0x40000000u
14244 #define GPMI_CTRL0_TOG_CLKGATE_SHIFT             30
14245 #define GPMI_CTRL0_TOG_SFTRST_MASK               0x80000000u
14246 #define GPMI_CTRL0_TOG_SFTRST_SHIFT              31
14247 /* COMPARE Bit Fields */
14248 #define GPMI_COMPARE_REFERENCE_MASK              0xFFFFu
14249 #define GPMI_COMPARE_REFERENCE_SHIFT             0
14250 #define GPMI_COMPARE_REFERENCE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_REFERENCE_SHIFT))&GPMI_COMPARE_REFERENCE_MASK)
14251 #define GPMI_COMPARE_MASK_MASK                   0xFFFF0000u
14252 #define GPMI_COMPARE_MASK_SHIFT                  16
14253 #define GPMI_COMPARE_MASK(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_MASK_SHIFT))&GPMI_COMPARE_MASK_MASK)
14254 /* ECCCTRL Bit Fields */
14255 #define GPMI_ECCCTRL_BUFFER_MASK_MASK            0x1FFu
14256 #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT           0
14257 #define GPMI_ECCCTRL_BUFFER_MASK(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_BUFFER_MASK_MASK)
14258 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK      0x800u
14259 #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT     11
14260 #define GPMI_ECCCTRL_ENABLE_ECC_MASK             0x1000u
14261 #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT            12
14262 #define GPMI_ECCCTRL_ECC_CMD_MASK                0x6000u
14263 #define GPMI_ECCCTRL_ECC_CMD_SHIFT               13
14264 #define GPMI_ECCCTRL_ECC_CMD(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_ECC_CMD_SHIFT))&GPMI_ECCCTRL_ECC_CMD_MASK)
14265 #define GPMI_ECCCTRL_RSVD2_MASK                  0x8000u
14266 #define GPMI_ECCCTRL_RSVD2_SHIFT                 15
14267 #define GPMI_ECCCTRL_HANDLE_MASK                 0xFFFF0000u
14268 #define GPMI_ECCCTRL_HANDLE_SHIFT                16
14269 #define GPMI_ECCCTRL_HANDLE(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_HANDLE_SHIFT))&GPMI_ECCCTRL_HANDLE_MASK)
14270 /* ECCCTRL_SET Bit Fields */
14271 #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK        0x1FFu
14272 #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT       0
14273 #define GPMI_ECCCTRL_SET_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
14274 #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK  0x800u
14275 #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT 11
14276 #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK         0x1000u
14277 #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT        12
14278 #define GPMI_ECCCTRL_SET_ECC_CMD_MASK            0x6000u
14279 #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT           13
14280 #define GPMI_ECCCTRL_SET_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_ECC_CMD_SHIFT))&GPMI_ECCCTRL_SET_ECC_CMD_MASK)
14281 #define GPMI_ECCCTRL_SET_RSVD2_MASK              0x8000u
14282 #define GPMI_ECCCTRL_SET_RSVD2_SHIFT             15
14283 #define GPMI_ECCCTRL_SET_HANDLE_MASK             0xFFFF0000u
14284 #define GPMI_ECCCTRL_SET_HANDLE_SHIFT            16
14285 #define GPMI_ECCCTRL_SET_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_HANDLE_SHIFT))&GPMI_ECCCTRL_SET_HANDLE_MASK)
14286 /* ECCCTRL_CLR Bit Fields */
14287 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK        0x1FFu
14288 #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT       0
14289 #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
14290 #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK  0x800u
14291 #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT 11
14292 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK         0x1000u
14293 #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT        12
14294 #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK            0x6000u
14295 #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT           13
14296 #define GPMI_ECCCTRL_CLR_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT))&GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
14297 #define GPMI_ECCCTRL_CLR_RSVD2_MASK              0x8000u
14298 #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT             15
14299 #define GPMI_ECCCTRL_CLR_HANDLE_MASK             0xFFFF0000u
14300 #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT            16
14301 #define GPMI_ECCCTRL_CLR_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_HANDLE_SHIFT))&GPMI_ECCCTRL_CLR_HANDLE_MASK)
14302 /* ECCCTRL_TOG Bit Fields */
14303 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK        0x1FFu
14304 #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT       0
14305 #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
14306 #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK  0x800u
14307 #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT 11
14308 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK         0x1000u
14309 #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT        12
14310 #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK            0x6000u
14311 #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT           13
14312 #define GPMI_ECCCTRL_TOG_ECC_CMD(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT))&GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
14313 #define GPMI_ECCCTRL_TOG_RSVD2_MASK              0x8000u
14314 #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT             15
14315 #define GPMI_ECCCTRL_TOG_HANDLE_MASK             0xFFFF0000u
14316 #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT            16
14317 #define GPMI_ECCCTRL_TOG_HANDLE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_HANDLE_SHIFT))&GPMI_ECCCTRL_TOG_HANDLE_MASK)
14318 /* ECCCOUNT Bit Fields */
14319 #define GPMI_ECCCOUNT_COUNT_MASK                 0xFFFFu
14320 #define GPMI_ECCCOUNT_COUNT_SHIFT                0
14321 #define GPMI_ECCCOUNT_COUNT(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_COUNT_SHIFT))&GPMI_ECCCOUNT_COUNT_MASK)
14322 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK       0xFF0000u
14323 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT      16
14324 #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT))&GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
14325 /* PAYLOAD Bit Fields */
14326 #define GPMI_PAYLOAD_RSVD0_MASK                  0x3u
14327 #define GPMI_PAYLOAD_RSVD0_SHIFT                 0
14328 #define GPMI_PAYLOAD_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_RSVD0_SHIFT))&GPMI_PAYLOAD_RSVD0_MASK)
14329 #define GPMI_PAYLOAD_ADDRESS_MASK                0xFFFFFFFCu
14330 #define GPMI_PAYLOAD_ADDRESS_SHIFT               2
14331 #define GPMI_PAYLOAD_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_ADDRESS_SHIFT))&GPMI_PAYLOAD_ADDRESS_MASK)
14332 /* AUXILIARY Bit Fields */
14333 #define GPMI_AUXILIARY_RSVD0_MASK                0x3u
14334 #define GPMI_AUXILIARY_RSVD0_SHIFT               0
14335 #define GPMI_AUXILIARY_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_RSVD0_SHIFT))&GPMI_AUXILIARY_RSVD0_MASK)
14336 #define GPMI_AUXILIARY_ADDRESS_MASK              0xFFFFFFFCu
14337 #define GPMI_AUXILIARY_ADDRESS_SHIFT             2
14338 #define GPMI_AUXILIARY_ADDRESS(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_ADDRESS_SHIFT))&GPMI_AUXILIARY_ADDRESS_MASK)
14339 /* CTRL1 Bit Fields */
14340 #define GPMI_CTRL1_GPMI_MODE_MASK                0x1u
14341 #define GPMI_CTRL1_GPMI_MODE_SHIFT               0
14342 #define GPMI_CTRL1_CAMERA_MODE_MASK              0x2u
14343 #define GPMI_CTRL1_CAMERA_MODE_SHIFT             1
14344 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK      0x4u
14345 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT     2
14346 #define GPMI_CTRL1_DEV_RESET_MASK                0x8u
14347 #define GPMI_CTRL1_DEV_RESET_SHIFT               3
14348 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
14349 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
14350 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
14351 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK       0x80u
14352 #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT      7
14353 #define GPMI_CTRL1_BURST_EN_MASK                 0x100u
14354 #define GPMI_CTRL1_BURST_EN_SHIFT                8
14355 #define GPMI_CTRL1_TIMEOUT_IRQ_MASK              0x200u
14356 #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT             9
14357 #define GPMI_CTRL1_DEV_IRQ_MASK                  0x400u
14358 #define GPMI_CTRL1_DEV_IRQ_SHIFT                 10
14359 #define GPMI_CTRL1_DMA2ECC_MODE_MASK             0x800u
14360 #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT            11
14361 #define GPMI_CTRL1_RDN_DELAY_MASK                0xF000u
14362 #define GPMI_CTRL1_RDN_DELAY_SHIFT               12
14363 #define GPMI_CTRL1_RDN_DELAY(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_RDN_DELAY_SHIFT))&GPMI_CTRL1_RDN_DELAY_MASK)
14364 #define GPMI_CTRL1_HALF_PERIOD_MASK              0x10000u
14365 #define GPMI_CTRL1_HALF_PERIOD_SHIFT             16
14366 #define GPMI_CTRL1_DLL_ENABLE_MASK               0x20000u
14367 #define GPMI_CTRL1_DLL_ENABLE_SHIFT              17
14368 #define GPMI_CTRL1_BCH_MODE_MASK                 0x40000u
14369 #define GPMI_CTRL1_BCH_MODE_SHIFT                18
14370 #define GPMI_CTRL1_GANGED_RDYBUSY_MASK           0x80000u
14371 #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT          19
14372 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK           0x100000u
14373 #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT          20
14374 #define GPMI_CTRL1_TEST_TRIGGER_MASK             0x200000u
14375 #define GPMI_CTRL1_TEST_TRIGGER_SHIFT            21
14376 #define GPMI_CTRL1_WRN_DLY_SEL_MASK              0xC00000u
14377 #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT             22
14378 #define GPMI_CTRL1_WRN_DLY_SEL(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_WRN_DLY_SEL_MASK)
14379 #define GPMI_CTRL1_DECOUPLE_CS_MASK              0x1000000u
14380 #define GPMI_CTRL1_DECOUPLE_CS_SHIFT             24
14381 #define GPMI_CTRL1_SSYNCMODE_MASK                0x2000000u
14382 #define GPMI_CTRL1_SSYNCMODE_SHIFT               25
14383 #define GPMI_CTRL1_UPDATE_CS_MASK                0x4000000u
14384 #define GPMI_CTRL1_UPDATE_CS_SHIFT               26
14385 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK         0x8000000u
14386 #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT        27
14387 #define GPMI_CTRL1_TOGGLE_MODE_MASK              0x10000000u
14388 #define GPMI_CTRL1_TOGGLE_MODE_SHIFT             28
14389 #define GPMI_CTRL1_WRITE_CLK_STOP_MASK           0x20000000u
14390 #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT          29
14391 #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK           0x40000000u
14392 #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT          30
14393 #define GPMI_CTRL1_DEV_CLK_STOP_MASK             0x80000000u
14394 #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT            31
14395 /* CTRL1_SET Bit Fields */
14396 #define GPMI_CTRL1_SET_GPMI_MODE_MASK            0x1u
14397 #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT           0
14398 #define GPMI_CTRL1_SET_CAMERA_MODE_MASK          0x2u
14399 #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT         1
14400 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK  0x4u
14401 #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT 2
14402 #define GPMI_CTRL1_SET_DEV_RESET_MASK            0x8u
14403 #define GPMI_CTRL1_SET_DEV_RESET_SHIFT           3
14404 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
14405 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
14406 #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
14407 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK   0x80u
14408 #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT  7
14409 #define GPMI_CTRL1_SET_BURST_EN_MASK             0x100u
14410 #define GPMI_CTRL1_SET_BURST_EN_SHIFT            8
14411 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK          0x200u
14412 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT         9
14413 #define GPMI_CTRL1_SET_DEV_IRQ_MASK              0x400u
14414 #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT             10
14415 #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK         0x800u
14416 #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT        11
14417 #define GPMI_CTRL1_SET_RDN_DELAY_MASK            0xF000u
14418 #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT           12
14419 #define GPMI_CTRL1_SET_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_RDN_DELAY_SHIFT))&GPMI_CTRL1_SET_RDN_DELAY_MASK)
14420 #define GPMI_CTRL1_SET_HALF_PERIOD_MASK          0x10000u
14421 #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT         16
14422 #define GPMI_CTRL1_SET_DLL_ENABLE_MASK           0x20000u
14423 #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT          17
14424 #define GPMI_CTRL1_SET_BCH_MODE_MASK             0x40000u
14425 #define GPMI_CTRL1_SET_BCH_MODE_SHIFT            18
14426 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK       0x80000u
14427 #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT      19
14428 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK       0x100000u
14429 #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT      20
14430 #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK         0x200000u
14431 #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT        21
14432 #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK          0xC00000u
14433 #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT         22
14434 #define GPMI_CTRL1_SET_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
14435 #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK          0x1000000u
14436 #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT         24
14437 #define GPMI_CTRL1_SET_SSYNCMODE_MASK            0x2000000u
14438 #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT           25
14439 #define GPMI_CTRL1_SET_UPDATE_CS_MASK            0x4000000u
14440 #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT           26
14441 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK     0x8000000u
14442 #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT    27
14443 #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK          0x10000000u
14444 #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT         28
14445 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK       0x20000000u
14446 #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT      29
14447 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK       0x40000000u
14448 #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT      30
14449 #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK         0x80000000u
14450 #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT        31
14451 /* CTRL1_CLR Bit Fields */
14452 #define GPMI_CTRL1_CLR_GPMI_MODE_MASK            0x1u
14453 #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT           0
14454 #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK          0x2u
14455 #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT         1
14456 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK  0x4u
14457 #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT 2
14458 #define GPMI_CTRL1_CLR_DEV_RESET_MASK            0x8u
14459 #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT           3
14460 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
14461 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
14462 #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
14463 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK   0x80u
14464 #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT  7
14465 #define GPMI_CTRL1_CLR_BURST_EN_MASK             0x100u
14466 #define GPMI_CTRL1_CLR_BURST_EN_SHIFT            8
14467 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK          0x200u
14468 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT         9
14469 #define GPMI_CTRL1_CLR_DEV_IRQ_MASK              0x400u
14470 #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT             10
14471 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK         0x800u
14472 #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT        11
14473 #define GPMI_CTRL1_CLR_RDN_DELAY_MASK            0xF000u
14474 #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT           12
14475 #define GPMI_CTRL1_CLR_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_RDN_DELAY_SHIFT))&GPMI_CTRL1_CLR_RDN_DELAY_MASK)
14476 #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK          0x10000u
14477 #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT         16
14478 #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK           0x20000u
14479 #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT          17
14480 #define GPMI_CTRL1_CLR_BCH_MODE_MASK             0x40000u
14481 #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT            18
14482 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK       0x80000u
14483 #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT      19
14484 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK       0x100000u
14485 #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT      20
14486 #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK         0x200000u
14487 #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT        21
14488 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK          0xC00000u
14489 #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT         22
14490 #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
14491 #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK          0x1000000u
14492 #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT         24
14493 #define GPMI_CTRL1_CLR_SSYNCMODE_MASK            0x2000000u
14494 #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT           25
14495 #define GPMI_CTRL1_CLR_UPDATE_CS_MASK            0x4000000u
14496 #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT           26
14497 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK     0x8000000u
14498 #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT    27
14499 #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK          0x10000000u
14500 #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT         28
14501 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK       0x20000000u
14502 #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT      29
14503 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK       0x40000000u
14504 #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT      30
14505 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK         0x80000000u
14506 #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT        31
14507 /* CTRL1_TOG Bit Fields */
14508 #define GPMI_CTRL1_TOG_GPMI_MODE_MASK            0x1u
14509 #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT           0
14510 #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK          0x2u
14511 #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT         1
14512 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK  0x4u
14513 #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT 2
14514 #define GPMI_CTRL1_TOG_DEV_RESET_MASK            0x8u
14515 #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT           3
14516 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u
14517 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4
14518 #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
14519 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK   0x80u
14520 #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT  7
14521 #define GPMI_CTRL1_TOG_BURST_EN_MASK             0x100u
14522 #define GPMI_CTRL1_TOG_BURST_EN_SHIFT            8
14523 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK          0x200u
14524 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT         9
14525 #define GPMI_CTRL1_TOG_DEV_IRQ_MASK              0x400u
14526 #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT             10
14527 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK         0x800u
14528 #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT        11
14529 #define GPMI_CTRL1_TOG_RDN_DELAY_MASK            0xF000u
14530 #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT           12
14531 #define GPMI_CTRL1_TOG_RDN_DELAY(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_RDN_DELAY_SHIFT))&GPMI_CTRL1_TOG_RDN_DELAY_MASK)
14532 #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK          0x10000u
14533 #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT         16
14534 #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK           0x20000u
14535 #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT          17
14536 #define GPMI_CTRL1_TOG_BCH_MODE_MASK             0x40000u
14537 #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT            18
14538 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK       0x80000u
14539 #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT      19
14540 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK       0x100000u
14541 #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT      20
14542 #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK         0x200000u
14543 #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT        21
14544 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK          0xC00000u
14545 #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT         22
14546 #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
14547 #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK          0x1000000u
14548 #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT         24
14549 #define GPMI_CTRL1_TOG_SSYNCMODE_MASK            0x2000000u
14550 #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT           25
14551 #define GPMI_CTRL1_TOG_UPDATE_CS_MASK            0x4000000u
14552 #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT           26
14553 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK     0x8000000u
14554 #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT    27
14555 #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK          0x10000000u
14556 #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT         28
14557 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK       0x20000000u
14558 #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT      29
14559 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK       0x40000000u
14560 #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT      30
14561 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK         0x80000000u
14562 #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT        31
14563 /* TIMING0 Bit Fields */
14564 #define GPMI_TIMING0_DATA_SETUP_MASK             0xFFu
14565 #define GPMI_TIMING0_DATA_SETUP_SHIFT            0
14566 #define GPMI_TIMING0_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_SETUP_SHIFT))&GPMI_TIMING0_DATA_SETUP_MASK)
14567 #define GPMI_TIMING0_DATA_HOLD_MASK              0xFF00u
14568 #define GPMI_TIMING0_DATA_HOLD_SHIFT             8
14569 #define GPMI_TIMING0_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_HOLD_SHIFT))&GPMI_TIMING0_DATA_HOLD_MASK)
14570 #define GPMI_TIMING0_ADDRESS_SETUP_MASK          0xFF0000u
14571 #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT         16
14572 #define GPMI_TIMING0_ADDRESS_SETUP(x)            (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_ADDRESS_SETUP_SHIFT))&GPMI_TIMING0_ADDRESS_SETUP_MASK)
14573 #define GPMI_TIMING0_RSVD1_MASK                  0xFF000000u
14574 #define GPMI_TIMING0_RSVD1_SHIFT                 24
14575 #define GPMI_TIMING0_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_RSVD1_SHIFT))&GPMI_TIMING0_RSVD1_MASK)
14576 /* TIMING1 Bit Fields */
14577 #define GPMI_TIMING1_RSVD1_MASK                  0xFFFFu
14578 #define GPMI_TIMING1_RSVD1_SHIFT                 0
14579 #define GPMI_TIMING1_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_RSVD1_SHIFT))&GPMI_TIMING1_RSVD1_MASK)
14580 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK    0xFFFF0000u
14581 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT   16
14582 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT))&GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
14583 /* TIMING2 Bit Fields */
14584 #define GPMI_TIMING2_DATA_PAUSE_MASK             0xFu
14585 #define GPMI_TIMING2_DATA_PAUSE_SHIFT            0
14586 #define GPMI_TIMING2_DATA_PAUSE(x)               (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_DATA_PAUSE_SHIFT))&GPMI_TIMING2_DATA_PAUSE_MASK)
14587 #define GPMI_TIMING2_CMDADD_PAUSE_MASK           0xF0u
14588 #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT          4
14589 #define GPMI_TIMING2_CMDADD_PAUSE(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CMDADD_PAUSE_SHIFT))&GPMI_TIMING2_CMDADD_PAUSE_MASK)
14590 #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK        0xF00u
14591 #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT       8
14592 #define GPMI_TIMING2_POSTAMBLE_DELAY(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT))&GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
14593 #define GPMI_TIMING2_PREAMBLE_DELAY_MASK         0xF000u
14594 #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT        12
14595 #define GPMI_TIMING2_PREAMBLE_DELAY(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_PREAMBLE_DELAY_SHIFT))&GPMI_TIMING2_PREAMBLE_DELAY_MASK)
14596 #define GPMI_TIMING2_CE_DELAY_MASK               0x1F0000u
14597 #define GPMI_TIMING2_CE_DELAY_SHIFT              16
14598 #define GPMI_TIMING2_CE_DELAY(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CE_DELAY_SHIFT))&GPMI_TIMING2_CE_DELAY_MASK)
14599 #define GPMI_TIMING2_RSVD0_MASK                  0xE00000u
14600 #define GPMI_TIMING2_RSVD0_SHIFT                 21
14601 #define GPMI_TIMING2_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_RSVD0_SHIFT))&GPMI_TIMING2_RSVD0_MASK)
14602 #define GPMI_TIMING2_READ_LATENCY_MASK           0x7000000u
14603 #define GPMI_TIMING2_READ_LATENCY_SHIFT          24
14604 #define GPMI_TIMING2_READ_LATENCY(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_READ_LATENCY_SHIFT))&GPMI_TIMING2_READ_LATENCY_MASK)
14605 #define GPMI_TIMING2_TCR_MASK                    0x18000000u
14606 #define GPMI_TIMING2_TCR_SHIFT                   27
14607 #define GPMI_TIMING2_TCR(x)                      (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TCR_SHIFT))&GPMI_TIMING2_TCR_MASK)
14608 #define GPMI_TIMING2_TRPSTH_MASK                 0xE0000000u
14609 #define GPMI_TIMING2_TRPSTH_SHIFT                29
14610 #define GPMI_TIMING2_TRPSTH(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TRPSTH_SHIFT))&GPMI_TIMING2_TRPSTH_MASK)
14611 /* DATA Bit Fields */
14612 #define GPMI_DATA_DATA_MASK                      0xFFFFFFFFu
14613 #define GPMI_DATA_DATA_SHIFT                     0
14614 #define GPMI_DATA_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<GPMI_DATA_DATA_SHIFT))&GPMI_DATA_DATA_MASK)
14615 /* STAT Bit Fields */
14616 #define GPMI_STAT_PRESENT_MASK                   0x1u
14617 #define GPMI_STAT_PRESENT_SHIFT                  0
14618 #define GPMI_STAT_FIFO_FULL_MASK                 0x2u
14619 #define GPMI_STAT_FIFO_FULL_SHIFT                1
14620 #define GPMI_STAT_FIFO_EMPTY_MASK                0x4u
14621 #define GPMI_STAT_FIFO_EMPTY_SHIFT               2
14622 #define GPMI_STAT_INVALID_BUFFER_MASK_MASK       0x8u
14623 #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT      3
14624 #define GPMI_STAT_ATA_IRQ_MASK                   0x10u
14625 #define GPMI_STAT_ATA_IRQ_SHIFT                  4
14626 #define GPMI_STAT_RSVD1_MASK                     0xE0u
14627 #define GPMI_STAT_RSVD1_SHIFT                    5
14628 #define GPMI_STAT_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RSVD1_SHIFT))&GPMI_STAT_RSVD1_MASK)
14629 #define GPMI_STAT_DEV0_ERROR_MASK                0x100u
14630 #define GPMI_STAT_DEV0_ERROR_SHIFT               8
14631 #define GPMI_STAT_DEV1_ERROR_MASK                0x200u
14632 #define GPMI_STAT_DEV1_ERROR_SHIFT               9
14633 #define GPMI_STAT_DEV2_ERROR_MASK                0x400u
14634 #define GPMI_STAT_DEV2_ERROR_SHIFT               10
14635 #define GPMI_STAT_DEV3_ERROR_MASK                0x800u
14636 #define GPMI_STAT_DEV3_ERROR_SHIFT               11
14637 #define GPMI_STAT_DEV4_ERROR_MASK                0x1000u
14638 #define GPMI_STAT_DEV4_ERROR_SHIFT               12
14639 #define GPMI_STAT_DEV5_ERROR_MASK                0x2000u
14640 #define GPMI_STAT_DEV5_ERROR_SHIFT               13
14641 #define GPMI_STAT_DEV6_ERROR_MASK                0x4000u
14642 #define GPMI_STAT_DEV6_ERROR_SHIFT               14
14643 #define GPMI_STAT_DEV7_ERROR_MASK                0x8000u
14644 #define GPMI_STAT_DEV7_ERROR_SHIFT               15
14645 #define GPMI_STAT_RDY_TIMEOUT_MASK               0xFF0000u
14646 #define GPMI_STAT_RDY_TIMEOUT_SHIFT              16
14647 #define GPMI_STAT_RDY_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RDY_TIMEOUT_SHIFT))&GPMI_STAT_RDY_TIMEOUT_MASK)
14648 #define GPMI_STAT_READY_BUSY_MASK                0xFF000000u
14649 #define GPMI_STAT_READY_BUSY_SHIFT               24
14650 #define GPMI_STAT_READY_BUSY(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_READY_BUSY_SHIFT))&GPMI_STAT_READY_BUSY_MASK)
14651 /* DEBUG Bit Fields */
14652 #define GPMI_DEBUG_CMD_END_MASK                  0xFFu
14653 #define GPMI_DEBUG_CMD_END_SHIFT                 0
14654 #define GPMI_DEBUG_CMD_END(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_CMD_END_SHIFT))&GPMI_DEBUG_CMD_END_MASK)
14655 #define GPMI_DEBUG_DMAREQ_MASK                   0xFF00u
14656 #define GPMI_DEBUG_DMAREQ_SHIFT                  8
14657 #define GPMI_DEBUG_DMAREQ(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMAREQ_SHIFT))&GPMI_DEBUG_DMAREQ_MASK)
14658 #define GPMI_DEBUG_DMA_SENSE_MASK                0xFF0000u
14659 #define GPMI_DEBUG_DMA_SENSE_SHIFT               16
14660 #define GPMI_DEBUG_DMA_SENSE(x)                  (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMA_SENSE_SHIFT))&GPMI_DEBUG_DMA_SENSE_MASK)
14661 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK       0xFF000000u
14662 #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT      24
14663 #define GPMI_DEBUG_WAIT_FOR_READY_END(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT))&GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
14664 /* VERSION Bit Fields */
14665 #define GPMI_VERSION_STEP_MASK                   0xFFFFu
14666 #define GPMI_VERSION_STEP_SHIFT                  0
14667 #define GPMI_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_STEP_SHIFT))&GPMI_VERSION_STEP_MASK)
14668 #define GPMI_VERSION_MINOR_MASK                  0xFF0000u
14669 #define GPMI_VERSION_MINOR_SHIFT                 16
14670 #define GPMI_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MINOR_SHIFT))&GPMI_VERSION_MINOR_MASK)
14671 #define GPMI_VERSION_MAJOR_MASK                  0xFF000000u
14672 #define GPMI_VERSION_MAJOR_SHIFT                 24
14673 #define GPMI_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MAJOR_SHIFT))&GPMI_VERSION_MAJOR_MASK)
14674 /* DEBUG2 Bit Fields */
14675 #define GPMI_DEBUG2_RDN_TAP_MASK                 0x3Fu
14676 #define GPMI_DEBUG2_RDN_TAP_SHIFT                0
14677 #define GPMI_DEBUG2_RDN_TAP(x)                   (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RDN_TAP_SHIFT))&GPMI_DEBUG2_RDN_TAP_MASK)
14678 #define GPMI_DEBUG2_UPDATE_WINDOW_MASK           0x40u
14679 #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT          6
14680 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK        0x80u
14681 #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT       7
14682 #define GPMI_DEBUG2_SYND2GPMI_READY_MASK         0x100u
14683 #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT        8
14684 #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK         0x200u
14685 #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT        9
14686 #define GPMI_DEBUG2_GPMI2SYND_READY_MASK         0x400u
14687 #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT        10
14688 #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK         0x800u
14689 #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT        11
14690 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK            0xF000u
14691 #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT           12
14692 #define GPMI_DEBUG2_SYND2GPMI_BE(x)              (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_SYND2GPMI_BE_SHIFT))&GPMI_DEBUG2_SYND2GPMI_BE_MASK)
14693 #define GPMI_DEBUG2_MAIN_STATE_MASK              0xF0000u
14694 #define GPMI_DEBUG2_MAIN_STATE_SHIFT             16
14695 #define GPMI_DEBUG2_MAIN_STATE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_MAIN_STATE_SHIFT))&GPMI_DEBUG2_MAIN_STATE_MASK)
14696 #define GPMI_DEBUG2_PIN_STATE_MASK               0x700000u
14697 #define GPMI_DEBUG2_PIN_STATE_SHIFT              20
14698 #define GPMI_DEBUG2_PIN_STATE(x)                 (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_PIN_STATE_SHIFT))&GPMI_DEBUG2_PIN_STATE_MASK)
14699 #define GPMI_DEBUG2_BUSY_MASK                    0x800000u
14700 #define GPMI_DEBUG2_BUSY_SHIFT                   23
14701 #define GPMI_DEBUG2_UDMA_STATE_MASK              0xF000000u
14702 #define GPMI_DEBUG2_UDMA_STATE_SHIFT             24
14703 #define GPMI_DEBUG2_UDMA_STATE(x)                (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_UDMA_STATE_SHIFT))&GPMI_DEBUG2_UDMA_STATE_MASK)
14704 #define GPMI_DEBUG2_RSVD1_MASK                   0xF0000000u
14705 #define GPMI_DEBUG2_RSVD1_SHIFT                  28
14706 #define GPMI_DEBUG2_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RSVD1_SHIFT))&GPMI_DEBUG2_RSVD1_MASK)
14707 /* DEBUG3 Bit Fields */
14708 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK           0xFFFFu
14709 #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT          0
14710 #define GPMI_DEBUG3_DEV_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT))&GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
14711 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK           0xFFFF0000u
14712 #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT          16
14713 #define GPMI_DEBUG3_APB_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_APB_WORD_CNTR_SHIFT))&GPMI_DEBUG3_APB_WORD_CNTR_MASK)
14714 /* READ_DDR_DLL_CTRL Bit Fields */
14715 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK       0x1u
14716 #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT      0
14717 #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK        0x2u
14718 #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT       1
14719 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
14720 #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
14721 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u
14722 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
14723 #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
14724 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK  0x80u
14725 #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7
14726 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK    0x100u
14727 #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT   8
14728 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u
14729 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9
14730 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u
14731 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10
14732 #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
14733 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK        0xC0000u
14734 #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT       18
14735 #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
14736 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
14737 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
14738 #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
14739 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
14740 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
14741 #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
14742 /* WRITE_DDR_DLL_CTRL Bit Fields */
14743 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK      0x1u
14744 #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT     0
14745 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK       0x2u
14746 #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT      1
14747 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
14748 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
14749 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u
14750 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
14751 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
14752 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK 0x80u
14753 #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7
14754 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK   0x100u
14755 #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT  8
14756 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u
14757 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9
14758 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u
14759 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10
14760 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
14761 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK       0xC0000u
14762 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT      18
14763 #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
14764 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
14765 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
14766 #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
14767 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
14768 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
14769 #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
14770 /* READ_DDR_DLL_STS Bit Fields */
14771 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK      0x1u
14772 #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT     0
14773 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK       0x1FEu
14774 #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT      1
14775 #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
14776 #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK         0xFE00u
14777 #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT        9
14778 #define GPMI_READ_DDR_DLL_STS_RSVD0(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
14779 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK      0x10000u
14780 #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT     16
14781 #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK       0x1FE0000u
14782 #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT      17
14783 #define GPMI_READ_DDR_DLL_STS_REF_SEL(x)         (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
14784 #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK         0xFE000000u
14785 #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT        25
14786 #define GPMI_READ_DDR_DLL_STS_RSVD1(x)           (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
14787 /* WRITE_DDR_DLL_STS Bit Fields */
14788 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK     0x1u
14789 #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT    0
14790 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK      0x1FEu
14791 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT     1
14792 #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x)        (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
14793 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK        0xFE00u
14794 #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT       9
14795 #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
14796 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK     0x10000u
14797 #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT    16
14798 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK      0x1FE0000u
14799 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT     17
14800 #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x)        (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
14801 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK        0xFE000000u
14802 #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT       25
14803 #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x)          (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
14804 
14805 /*!
14806  * @}
14807  */ /* end of group GPMI_Register_Masks */
14808 
14809 /* GPMI - Peripheral instance base addresses */
14810 /** Peripheral GPMI base address */
14811 #define GPMI_BASE                                (0x41806000u)
14812 /** Peripheral GPMI base pointer */
14813 #define GPMI                                     ((GPMI_Type *)GPMI_BASE)
14814 #define GPMI_BASE_PTR                            (GPMI)
14815 /** Array initializer of GPMI peripheral base addresses */
14816 #define GPMI_BASE_ADDRS                          { GPMI_BASE }
14817 /** Array initializer of GPMI peripheral base pointers */
14818 #define GPMI_BASE_PTRS                           { GPMI }
14819 /** Interrupt vectors for the GPMI peripheral type */
14820 #define GPMI_IRQS                                { GPMI_IRQn }
14821 
14822 /* ----------------------------------------------------------------------------
14823    -- GPMI - Register accessor macros
14824    ---------------------------------------------------------------------------- */
14825 
14826 /*!
14827  * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros
14828  * @{
14829  */
14830 
14831 /* GPMI - Register instance definitions */
14832 /* GPMI */
14833 #define GPMI_CTRL0                               GPMI_CTRL0_REG(GPMI_BASE_PTR)
14834 #define GPMI_CTRL0_SET                           GPMI_CTRL0_SET_REG(GPMI_BASE_PTR)
14835 #define GPMI_CTRL0_CLR                           GPMI_CTRL0_CLR_REG(GPMI_BASE_PTR)
14836 #define GPMI_CTRL0_TOG                           GPMI_CTRL0_TOG_REG(GPMI_BASE_PTR)
14837 #define GPMI_COMPARE                             GPMI_COMPARE_REG(GPMI_BASE_PTR)
14838 #define GPMI_ECCCTRL                             GPMI_ECCCTRL_REG(GPMI_BASE_PTR)
14839 #define GPMI_ECCCTRL_SET                         GPMI_ECCCTRL_SET_REG(GPMI_BASE_PTR)
14840 #define GPMI_ECCCTRL_CLR                         GPMI_ECCCTRL_CLR_REG(GPMI_BASE_PTR)
14841 #define GPMI_ECCCTRL_TOG                         GPMI_ECCCTRL_TOG_REG(GPMI_BASE_PTR)
14842 #define GPMI_ECCCOUNT                            GPMI_ECCCOUNT_REG(GPMI_BASE_PTR)
14843 #define GPMI_PAYLOAD                             GPMI_PAYLOAD_REG(GPMI_BASE_PTR)
14844 #define GPMI_AUXILIARY                           GPMI_AUXILIARY_REG(GPMI_BASE_PTR)
14845 #define GPMI_CTRL1                               GPMI_CTRL1_REG(GPMI_BASE_PTR)
14846 #define GPMI_CTRL1_SET                           GPMI_CTRL1_SET_REG(GPMI_BASE_PTR)
14847 #define GPMI_CTRL1_CLR                           GPMI_CTRL1_CLR_REG(GPMI_BASE_PTR)
14848 #define GPMI_CTRL1_TOG                           GPMI_CTRL1_TOG_REG(GPMI_BASE_PTR)
14849 #define GPMI_TIMING0                             GPMI_TIMING0_REG(GPMI_BASE_PTR)
14850 #define GPMI_TIMING1                             GPMI_TIMING1_REG(GPMI_BASE_PTR)
14851 #define GPMI_TIMING2                             GPMI_TIMING2_REG(GPMI_BASE_PTR)
14852 #define GPMI_DATA                                GPMI_DATA_REG(GPMI_BASE_PTR)
14853 #define GPMI_STAT                                GPMI_STAT_REG(GPMI_BASE_PTR)
14854 #define GPMI_DEBUG                               GPMI_DEBUG_REG(GPMI_BASE_PTR)
14855 #define GPMI_VERSION                             GPMI_VERSION_REG(GPMI_BASE_PTR)
14856 #define GPMI_DEBUG2                              GPMI_DEBUG2_REG(GPMI_BASE_PTR)
14857 #define GPMI_DEBUG3                              GPMI_DEBUG3_REG(GPMI_BASE_PTR)
14858 #define GPMI_READ_DDR_DLL_CTRL                   GPMI_READ_DDR_DLL_CTRL_REG(GPMI_BASE_PTR)
14859 #define GPMI_WRITE_DDR_DLL_CTRL                  GPMI_WRITE_DDR_DLL_CTRL_REG(GPMI_BASE_PTR)
14860 #define GPMI_READ_DDR_DLL_STS                    GPMI_READ_DDR_DLL_STS_REG(GPMI_BASE_PTR)
14861 #define GPMI_WRITE_DDR_DLL_STS                   GPMI_WRITE_DDR_DLL_STS_REG(GPMI_BASE_PTR)
14862 
14863 /*!
14864  * @}
14865  */ /* end of group GPMI_Register_Accessor_Macros */
14866 
14867 /*!
14868  * @}
14869  */ /* end of group GPMI_Peripheral */
14870 
14871 /* ----------------------------------------------------------------------------
14872    -- GPT Peripheral Access Layer
14873    ---------------------------------------------------------------------------- */
14874 
14875 /*!
14876  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
14877  * @{
14878  */
14879 
14880 /** GPT - Register Layout Typedef */
14881 typedef struct {
14882   __IO  uint32_t CR;                                     /**< GPT Control Register, offset: 0x0 */
14883   __IO  uint32_t PR;                                     /**< GPT Prescaler Register, offset: 0x4 */
14884   __IO  uint32_t SR;                                     /**< GPT Status Register, offset: 0x8 */
14885   __IO  uint32_t IR;                                     /**< GPT Interrupt Register, offset: 0xC */
14886   __IO  uint32_t OCR1;                                   /**< GPT Output Compare Register 1, offset: 0x10 */
14887   __IO  uint32_t OCR2;                                   /**< GPT Output Compare Register 2, offset: 0x14 */
14888   __IO  uint32_t OCR3;                                   /**< GPT Output Compare Register 3, offset: 0x18 */
14889   __I   uint32_t ICR1;                                   /**< GPT Input Capture Register 1, offset: 0x1C */
14890   __I   uint32_t ICR2;                                   /**< GPT Input Capture Register 2, offset: 0x20 */
14891   __I   uint32_t CNT;                                    /**< GPT Counter Register, offset: 0x24 */
14892 } GPT_Type, *GPT_MemMapPtr;
14893 
14894 /* ----------------------------------------------------------------------------
14895    -- GPT - Register accessor macros
14896    ---------------------------------------------------------------------------- */
14897 
14898 /*!
14899  * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros
14900  * @{
14901  */
14902 
14903 /* GPT - Register accessors */
14904 #define GPT_CR_REG(base)                         ((base)->CR)
14905 #define GPT_PR_REG(base)                         ((base)->PR)
14906 #define GPT_SR_REG(base)                         ((base)->SR)
14907 #define GPT_IR_REG(base)                         ((base)->IR)
14908 #define GPT_OCR1_REG(base)                       ((base)->OCR1)
14909 #define GPT_OCR2_REG(base)                       ((base)->OCR2)
14910 #define GPT_OCR3_REG(base)                       ((base)->OCR3)
14911 #define GPT_ICR1_REG(base)                       ((base)->ICR1)
14912 #define GPT_ICR2_REG(base)                       ((base)->ICR2)
14913 #define GPT_CNT_REG(base)                        ((base)->CNT)
14914 
14915 /*!
14916  * @}
14917  */ /* end of group GPT_Register_Accessor_Macros */
14918 
14919 /* ----------------------------------------------------------------------------
14920    -- GPT Register Masks
14921    ---------------------------------------------------------------------------- */
14922 
14923 /*!
14924  * @addtogroup GPT_Register_Masks GPT Register Masks
14925  * @{
14926  */
14927 
14928 /* CR Bit Fields */
14929 #define GPT_CR_EN_MASK                           0x1u
14930 #define GPT_CR_EN_SHIFT                          0
14931 #define GPT_CR_ENMOD_MASK                        0x2u
14932 #define GPT_CR_ENMOD_SHIFT                       1
14933 #define GPT_CR_DBGEN_MASK                        0x4u
14934 #define GPT_CR_DBGEN_SHIFT                       2
14935 #define GPT_CR_WAITEN_MASK                       0x8u
14936 #define GPT_CR_WAITEN_SHIFT                      3
14937 #define GPT_CR_DOZEEN_MASK                       0x10u
14938 #define GPT_CR_DOZEEN_SHIFT                      4
14939 #define GPT_CR_STOPEN_MASK                       0x20u
14940 #define GPT_CR_STOPEN_SHIFT                      5
14941 #define GPT_CR_CLKSRC_MASK                       0x1C0u
14942 #define GPT_CR_CLKSRC_SHIFT                      6
14943 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_CR_CLKSRC_SHIFT))&GPT_CR_CLKSRC_MASK)
14944 #define GPT_CR_FRR_MASK                          0x200u
14945 #define GPT_CR_FRR_SHIFT                         9
14946 #define GPT_CR_EN_24M_MASK                       0x400u
14947 #define GPT_CR_EN_24M_SHIFT                      10
14948 #define GPT_CR_SWR_MASK                          0x8000u
14949 #define GPT_CR_SWR_SHIFT                         15
14950 #define GPT_CR_IM1_MASK                          0x30000u
14951 #define GPT_CR_IM1_SHIFT                         16
14952 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM1_SHIFT))&GPT_CR_IM1_MASK)
14953 #define GPT_CR_IM2_MASK                          0xC0000u
14954 #define GPT_CR_IM2_SHIFT                         18
14955 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM2_SHIFT))&GPT_CR_IM2_MASK)
14956 #define GPT_CR_OM1_MASK                          0x700000u
14957 #define GPT_CR_OM1_SHIFT                         20
14958 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM1_SHIFT))&GPT_CR_OM1_MASK)
14959 #define GPT_CR_OM2_MASK                          0x3800000u
14960 #define GPT_CR_OM2_SHIFT                         23
14961 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM2_SHIFT))&GPT_CR_OM2_MASK)
14962 #define GPT_CR_OM3_MASK                          0x1C000000u
14963 #define GPT_CR_OM3_SHIFT                         26
14964 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM3_SHIFT))&GPT_CR_OM3_MASK)
14965 #define GPT_CR_FO1_MASK                          0x20000000u
14966 #define GPT_CR_FO1_SHIFT                         29
14967 #define GPT_CR_FO2_MASK                          0x40000000u
14968 #define GPT_CR_FO2_SHIFT                         30
14969 #define GPT_CR_FO3_MASK                          0x80000000u
14970 #define GPT_CR_FO3_SHIFT                         31
14971 /* PR Bit Fields */
14972 #define GPT_PR_PRESCALER_MASK                    0xFFFu
14973 #define GPT_PR_PRESCALER_SHIFT                   0
14974 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER_SHIFT))&GPT_PR_PRESCALER_MASK)
14975 #define GPT_PR_PRESCALER24M_MASK                 0xF000u
14976 #define GPT_PR_PRESCALER24M_SHIFT                12
14977 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER24M_SHIFT))&GPT_PR_PRESCALER24M_MASK)
14978 /* SR Bit Fields */
14979 #define GPT_SR_OF1_MASK                          0x1u
14980 #define GPT_SR_OF1_SHIFT                         0
14981 #define GPT_SR_OF2_MASK                          0x2u
14982 #define GPT_SR_OF2_SHIFT                         1
14983 #define GPT_SR_OF3_MASK                          0x4u
14984 #define GPT_SR_OF3_SHIFT                         2
14985 #define GPT_SR_IF1_MASK                          0x8u
14986 #define GPT_SR_IF1_SHIFT                         3
14987 #define GPT_SR_IF2_MASK                          0x10u
14988 #define GPT_SR_IF2_SHIFT                         4
14989 #define GPT_SR_ROV_MASK                          0x20u
14990 #define GPT_SR_ROV_SHIFT                         5
14991 /* IR Bit Fields */
14992 #define GPT_IR_OF1IE_MASK                        0x1u
14993 #define GPT_IR_OF1IE_SHIFT                       0
14994 #define GPT_IR_OF2IE_MASK                        0x2u
14995 #define GPT_IR_OF2IE_SHIFT                       1
14996 #define GPT_IR_OF3IE_MASK                        0x4u
14997 #define GPT_IR_OF3IE_SHIFT                       2
14998 #define GPT_IR_IF1IE_MASK                        0x8u
14999 #define GPT_IR_IF1IE_SHIFT                       3
15000 #define GPT_IR_IF2IE_MASK                        0x10u
15001 #define GPT_IR_IF2IE_SHIFT                       4
15002 #define GPT_IR_ROVIE_MASK                        0x20u
15003 #define GPT_IR_ROVIE_SHIFT                       5
15004 /* OCR1 Bit Fields */
15005 #define GPT_OCR1_COMP_MASK                       0xFFFFFFFFu
15006 #define GPT_OCR1_COMP_SHIFT                      0
15007 #define GPT_OCR1_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR1_COMP_SHIFT))&GPT_OCR1_COMP_MASK)
15008 /* OCR2 Bit Fields */
15009 #define GPT_OCR2_COMP_MASK                       0xFFFFFFFFu
15010 #define GPT_OCR2_COMP_SHIFT                      0
15011 #define GPT_OCR2_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR2_COMP_SHIFT))&GPT_OCR2_COMP_MASK)
15012 /* OCR3 Bit Fields */
15013 #define GPT_OCR3_COMP_MASK                       0xFFFFFFFFu
15014 #define GPT_OCR3_COMP_SHIFT                      0
15015 #define GPT_OCR3_COMP(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_OCR3_COMP_SHIFT))&GPT_OCR3_COMP_MASK)
15016 /* ICR1 Bit Fields */
15017 #define GPT_ICR1_CAPT_MASK                       0xFFFFFFFFu
15018 #define GPT_ICR1_CAPT_SHIFT                      0
15019 #define GPT_ICR1_CAPT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_ICR1_CAPT_SHIFT))&GPT_ICR1_CAPT_MASK)
15020 /* ICR2 Bit Fields */
15021 #define GPT_ICR2_CAPT_MASK                       0xFFFFFFFFu
15022 #define GPT_ICR2_CAPT_SHIFT                      0
15023 #define GPT_ICR2_CAPT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_ICR2_CAPT_SHIFT))&GPT_ICR2_CAPT_MASK)
15024 /* CNT Bit Fields */
15025 #define GPT_CNT_COUNT_MASK                       0xFFFFFFFFu
15026 #define GPT_CNT_COUNT_SHIFT                      0
15027 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<GPT_CNT_COUNT_SHIFT))&GPT_CNT_COUNT_MASK)
15028 
15029 /*!
15030  * @}
15031  */ /* end of group GPT_Register_Masks */
15032 
15033 /* GPT - Peripheral instance base addresses */
15034 /** Peripheral GPT base address */
15035 #define GPT_BASE                                 (0x42098000u)
15036 /** Peripheral GPT base pointer */
15037 #define GPT                                      ((GPT_Type *)GPT_BASE)
15038 #define GPT_BASE_PTR                             (GPT)
15039 /** Array initializer of GPT peripheral base addresses */
15040 #define GPT_BASE_ADDRS                           { GPT_BASE }
15041 /** Array initializer of GPT peripheral base pointers */
15042 #define GPT_BASE_PTRS                            { GPT }
15043 /** Interrupt vectors for the GPT peripheral type */
15044 #define GPT_IRQS                                 { GPT_IRQn }
15045 
15046 /* ----------------------------------------------------------------------------
15047    -- GPT - Register accessor macros
15048    ---------------------------------------------------------------------------- */
15049 
15050 /*!
15051  * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros
15052  * @{
15053  */
15054 
15055 /* GPT - Register instance definitions */
15056 /* GPT */
15057 #define GPT_CR                                   GPT_CR_REG(GPT_BASE_PTR)
15058 #define GPT_PR                                   GPT_PR_REG(GPT_BASE_PTR)
15059 #define GPT_SR                                   GPT_SR_REG(GPT_BASE_PTR)
15060 #define GPT_IR                                   GPT_IR_REG(GPT_BASE_PTR)
15061 #define GPT_OCR1                                 GPT_OCR1_REG(GPT_BASE_PTR)
15062 #define GPT_OCR2                                 GPT_OCR2_REG(GPT_BASE_PTR)
15063 #define GPT_OCR3                                 GPT_OCR3_REG(GPT_BASE_PTR)
15064 #define GPT_ICR1                                 GPT_ICR1_REG(GPT_BASE_PTR)
15065 #define GPT_ICR2                                 GPT_ICR2_REG(GPT_BASE_PTR)
15066 #define GPT_CNT                                  GPT_CNT_REG(GPT_BASE_PTR)
15067 
15068 /*!
15069  * @}
15070  */ /* end of group GPT_Register_Accessor_Macros */
15071 
15072 /*!
15073  * @}
15074  */ /* end of group GPT_Peripheral */
15075 
15076 /* ----------------------------------------------------------------------------
15077    -- I2C Peripheral Access Layer
15078    ---------------------------------------------------------------------------- */
15079 
15080 /*!
15081  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
15082  * @{
15083  */
15084 
15085 /** I2C - Register Layout Typedef */
15086 typedef struct {
15087   __IO  uint16_t IADR;                                   /**< I2C Address Register, offset: 0x0 */
15088   uint8_t RESERVED_0[2];
15089   __IO  uint16_t IFDR;                                   /**< I2C Frequency Divider Register, offset: 0x4 */
15090   uint8_t RESERVED_1[2];
15091   __IO  uint16_t I2CR;                                   /**< I2C Control Register, offset: 0x8 */
15092   uint8_t RESERVED_2[2];
15093   __IO  uint16_t I2SR;                                   /**< I2C Status Register, offset: 0xC */
15094   uint8_t RESERVED_3[2];
15095   __IO  uint16_t I2DR;                                   /**< I2C Data I/O Register, offset: 0x10 */
15096 } I2C_Type, *I2C_MemMapPtr;
15097 
15098 /* ----------------------------------------------------------------------------
15099    -- I2C - Register accessor macros
15100    ---------------------------------------------------------------------------- */
15101 
15102 /*!
15103  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
15104  * @{
15105  */
15106 
15107 /* I2C - Register accessors */
15108 #define I2C_IADR_REG(base)                       ((base)->IADR)
15109 #define I2C_IFDR_REG(base)                       ((base)->IFDR)
15110 #define I2C_I2CR_REG(base)                       ((base)->I2CR)
15111 #define I2C_I2SR_REG(base)                       ((base)->I2SR)
15112 #define I2C_I2DR_REG(base)                       ((base)->I2DR)
15113 
15114 /*!
15115  * @}
15116  */ /* end of group I2C_Register_Accessor_Macros */
15117 
15118 /* ----------------------------------------------------------------------------
15119    -- I2C Register Masks
15120    ---------------------------------------------------------------------------- */
15121 
15122 /*!
15123  * @addtogroup I2C_Register_Masks I2C Register Masks
15124  * @{
15125  */
15126 
15127 /* IADR Bit Fields */
15128 #define I2C_IADR_ADR_MASK                        0xFEu
15129 #define I2C_IADR_ADR_SHIFT                       1
15130 #define I2C_IADR_ADR(x)                          (((uint16_t)(((uint16_t)(x))<<I2C_IADR_ADR_SHIFT))&I2C_IADR_ADR_MASK)
15131 /* IFDR Bit Fields */
15132 #define I2C_IFDR_IC_MASK                         0x3Fu
15133 #define I2C_IFDR_IC_SHIFT                        0
15134 #define I2C_IFDR_IC(x)                           (((uint16_t)(((uint16_t)(x))<<I2C_IFDR_IC_SHIFT))&I2C_IFDR_IC_MASK)
15135 /* I2CR Bit Fields */
15136 #define I2C_I2CR_RSTA_MASK                       0x4u
15137 #define I2C_I2CR_RSTA_SHIFT                      2
15138 #define I2C_I2CR_TXAK_MASK                       0x8u
15139 #define I2C_I2CR_TXAK_SHIFT                      3
15140 #define I2C_I2CR_MTX_MASK                        0x10u
15141 #define I2C_I2CR_MTX_SHIFT                       4
15142 #define I2C_I2CR_MSTA_MASK                       0x20u
15143 #define I2C_I2CR_MSTA_SHIFT                      5
15144 #define I2C_I2CR_IIEN_MASK                       0x40u
15145 #define I2C_I2CR_IIEN_SHIFT                      6
15146 #define I2C_I2CR_IEN_MASK                        0x80u
15147 #define I2C_I2CR_IEN_SHIFT                       7
15148 /* I2SR Bit Fields */
15149 #define I2C_I2SR_RXAK_MASK                       0x1u
15150 #define I2C_I2SR_RXAK_SHIFT                      0
15151 #define I2C_I2SR_IIF_MASK                        0x2u
15152 #define I2C_I2SR_IIF_SHIFT                       1
15153 #define I2C_I2SR_SRW_MASK                        0x4u
15154 #define I2C_I2SR_SRW_SHIFT                       2
15155 #define I2C_I2SR_IAL_MASK                        0x10u
15156 #define I2C_I2SR_IAL_SHIFT                       4
15157 #define I2C_I2SR_IBB_MASK                        0x20u
15158 #define I2C_I2SR_IBB_SHIFT                       5
15159 #define I2C_I2SR_IAAS_MASK                       0x40u
15160 #define I2C_I2SR_IAAS_SHIFT                      6
15161 #define I2C_I2SR_ICF_MASK                        0x80u
15162 #define I2C_I2SR_ICF_SHIFT                       7
15163 /* I2DR Bit Fields */
15164 #define I2C_I2DR_DATA_MASK                       0xFFu
15165 #define I2C_I2DR_DATA_SHIFT                      0
15166 #define I2C_I2DR_DATA(x)                         (((uint16_t)(((uint16_t)(x))<<I2C_I2DR_DATA_SHIFT))&I2C_I2DR_DATA_MASK)
15167 
15168 /*!
15169  * @}
15170  */ /* end of group I2C_Register_Masks */
15171 
15172 /* I2C - Peripheral instance base addresses */
15173 /** Peripheral I2C1 base address */
15174 #define I2C1_BASE                                (0x421A0000u)
15175 /** Peripheral I2C1 base pointer */
15176 #define I2C1                                     ((I2C_Type *)I2C1_BASE)
15177 #define I2C1_BASE_PTR                            (I2C1)
15178 /** Peripheral I2C2 base address */
15179 #define I2C2_BASE                                (0x421A4000u)
15180 /** Peripheral I2C2 base pointer */
15181 #define I2C2                                     ((I2C_Type *)I2C2_BASE)
15182 #define I2C2_BASE_PTR                            (I2C2)
15183 /** Peripheral I2C3 base address */
15184 #define I2C3_BASE                                (0x421A8000u)
15185 /** Peripheral I2C3 base pointer */
15186 #define I2C3                                     ((I2C_Type *)I2C3_BASE)
15187 #define I2C3_BASE_PTR                            (I2C3)
15188 /** Peripheral I2C4 base address */
15189 #define I2C4_BASE                                (0x421F8000u)
15190 /** Peripheral I2C4 base pointer */
15191 #define I2C4                                     ((I2C_Type *)I2C4_BASE)
15192 #define I2C4_BASE_PTR                            (I2C4)
15193 /** Array initializer of I2C peripheral base addresses */
15194 #define I2C_BASE_ADDRS                           { I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE }
15195 /** Array initializer of I2C peripheral base pointers */
15196 #define I2C_BASE_PTRS                            { I2C1, I2C2, I2C3, I2C4 }
15197 /** Interrupt vectors for the I2C peripheral type */
15198 #define I2C_IRQS                                 { I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn }
15199 
15200 /* ----------------------------------------------------------------------------
15201    -- I2C - Register accessor macros
15202    ---------------------------------------------------------------------------- */
15203 
15204 /*!
15205  * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
15206  * @{
15207  */
15208 
15209 /* I2C - Register instance definitions */
15210 /* I2C1 */
15211 #define I2C1_IADR                                I2C_IADR_REG(I2C1_BASE_PTR)
15212 #define I2C1_IFDR                                I2C_IFDR_REG(I2C1_BASE_PTR)
15213 #define I2C1_I2CR                                I2C_I2CR_REG(I2C1_BASE_PTR)
15214 #define I2C1_I2SR                                I2C_I2SR_REG(I2C1_BASE_PTR)
15215 #define I2C1_I2DR                                I2C_I2DR_REG(I2C1_BASE_PTR)
15216 /* I2C2 */
15217 #define I2C2_IADR                                I2C_IADR_REG(I2C2_BASE_PTR)
15218 #define I2C2_IFDR                                I2C_IFDR_REG(I2C2_BASE_PTR)
15219 #define I2C2_I2CR                                I2C_I2CR_REG(I2C2_BASE_PTR)
15220 #define I2C2_I2SR                                I2C_I2SR_REG(I2C2_BASE_PTR)
15221 #define I2C2_I2DR                                I2C_I2DR_REG(I2C2_BASE_PTR)
15222 /* I2C3 */
15223 #define I2C3_IADR                                I2C_IADR_REG(I2C3_BASE_PTR)
15224 #define I2C3_IFDR                                I2C_IFDR_REG(I2C3_BASE_PTR)
15225 #define I2C3_I2CR                                I2C_I2CR_REG(I2C3_BASE_PTR)
15226 #define I2C3_I2SR                                I2C_I2SR_REG(I2C3_BASE_PTR)
15227 #define I2C3_I2DR                                I2C_I2DR_REG(I2C3_BASE_PTR)
15228 /* I2C4 */
15229 #define I2C4_IADR                                I2C_IADR_REG(I2C4_BASE_PTR)
15230 #define I2C4_IFDR                                I2C_IFDR_REG(I2C4_BASE_PTR)
15231 #define I2C4_I2CR                                I2C_I2CR_REG(I2C4_BASE_PTR)
15232 #define I2C4_I2SR                                I2C_I2SR_REG(I2C4_BASE_PTR)
15233 #define I2C4_I2DR                                I2C_I2DR_REG(I2C4_BASE_PTR)
15234 
15235 /*!
15236  * @}
15237  */ /* end of group I2C_Register_Accessor_Macros */
15238 
15239 /*!
15240  * @}
15241  */ /* end of group I2C_Peripheral */
15242 
15243 /* ----------------------------------------------------------------------------
15244    -- I2S Peripheral Access Layer
15245    ---------------------------------------------------------------------------- */
15246 
15247 /*!
15248  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
15249  * @{
15250  */
15251 
15252 /** I2S - Register Layout Typedef */
15253 typedef struct {
15254   __IO  uint32_t TCSR;                                   /**< SAI Transmit Control Register, offset: 0x0 */
15255   __IO  uint32_t TCR1;                                   /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
15256   __IO  uint32_t TCR2;                                   /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
15257   __IO  uint32_t TCR3;                                   /**< SAI Transmit Configuration 3 Register, offset: 0xC */
15258   __IO  uint32_t TCR4;                                   /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
15259   __IO  uint32_t TCR5;                                   /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
15260   uint8_t RESERVED_0[8];
15261   __O     uint32_t TDR[1];                                 /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
15262   uint8_t RESERVED_1[28];
15263   __I     uint32_t TFR[1];                                 /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
15264   uint8_t RESERVED_2[28];
15265   __IO  uint32_t TMR;                                    /**< SAI Transmit Mask Register, offset: 0x60 */
15266   uint8_t RESERVED_3[28];
15267   __IO  uint32_t RCSR;                                   /**< SAI Receive Control Register, offset: 0x80 */
15268   __IO  uint32_t RCR1;                                   /**< SAI Receive Configuration 1 Register, offset: 0x84 */
15269   __IO  uint32_t RCR2;                                   /**< SAI Receive Configuration 2 Register, offset: 0x88 */
15270   __IO  uint32_t RCR3;                                   /**< SAI Receive Configuration 3 Register, offset: 0x8C */
15271   __IO  uint32_t RCR4;                                   /**< SAI Receive Configuration 4 Register, offset: 0x90 */
15272   __IO  uint32_t RCR5;                                   /**< SAI Receive Configuration 5 Register, offset: 0x94 */
15273   uint8_t RESERVED_4[8];
15274   __I     uint32_t RDR[1];                                 /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
15275   uint8_t RESERVED_5[28];
15276   __I     uint32_t RFR[1];                                 /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
15277   uint8_t RESERVED_6[28];
15278   __IO  uint32_t RMR;                                    /**< SAI Receive Mask Register, offset: 0xE0 */
15279 } I2S_Type, *I2S_MemMapPtr;
15280 
15281 /* ----------------------------------------------------------------------------
15282    -- I2S - Register accessor macros
15283    ---------------------------------------------------------------------------- */
15284 
15285 /*!
15286  * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
15287  * @{
15288  */
15289 
15290 /* I2S - Register accessors */
15291 #define I2S_TCSR_REG(base)                       ((base)->TCSR)
15292 #define I2S_TCR1_REG(base)                       ((base)->TCR1)
15293 #define I2S_TCR2_REG(base)                       ((base)->TCR2)
15294 #define I2S_TCR3_REG(base)                       ((base)->TCR3)
15295 #define I2S_TCR4_REG(base)                       ((base)->TCR4)
15296 #define I2S_TCR5_REG(base)                       ((base)->TCR5)
15297 #define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
15298 #define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
15299 #define I2S_TMR_REG(base)                        ((base)->TMR)
15300 #define I2S_RCSR_REG(base)                       ((base)->RCSR)
15301 #define I2S_RCR1_REG(base)                       ((base)->RCR1)
15302 #define I2S_RCR2_REG(base)                       ((base)->RCR2)
15303 #define I2S_RCR3_REG(base)                       ((base)->RCR3)
15304 #define I2S_RCR4_REG(base)                       ((base)->RCR4)
15305 #define I2S_RCR5_REG(base)                       ((base)->RCR5)
15306 #define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
15307 #define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
15308 #define I2S_RMR_REG(base)                        ((base)->RMR)
15309 
15310 /*!
15311  * @}
15312  */ /* end of group I2S_Register_Accessor_Macros */
15313 
15314 /* ----------------------------------------------------------------------------
15315    -- I2S Register Masks
15316    ---------------------------------------------------------------------------- */
15317 
15318 /*!
15319  * @addtogroup I2S_Register_Masks I2S Register Masks
15320  * @{
15321  */
15322 
15323 /* TCSR Bit Fields */
15324 #define I2S_TCSR_FRDE_MASK                       0x1u
15325 #define I2S_TCSR_FRDE_SHIFT                      0
15326 #define I2S_TCSR_FWDE_MASK                       0x2u
15327 #define I2S_TCSR_FWDE_SHIFT                      1
15328 #define I2S_TCSR_FRIE_MASK                       0x100u
15329 #define I2S_TCSR_FRIE_SHIFT                      8
15330 #define I2S_TCSR_FWIE_MASK                       0x200u
15331 #define I2S_TCSR_FWIE_SHIFT                      9
15332 #define I2S_TCSR_FEIE_MASK                       0x400u
15333 #define I2S_TCSR_FEIE_SHIFT                      10
15334 #define I2S_TCSR_SEIE_MASK                       0x800u
15335 #define I2S_TCSR_SEIE_SHIFT                      11
15336 #define I2S_TCSR_WSIE_MASK                       0x1000u
15337 #define I2S_TCSR_WSIE_SHIFT                      12
15338 #define I2S_TCSR_FRF_MASK                        0x10000u
15339 #define I2S_TCSR_FRF_SHIFT                       16
15340 #define I2S_TCSR_FWF_MASK                        0x20000u
15341 #define I2S_TCSR_FWF_SHIFT                       17
15342 #define I2S_TCSR_FEF_MASK                        0x40000u
15343 #define I2S_TCSR_FEF_SHIFT                       18
15344 #define I2S_TCSR_SEF_MASK                        0x80000u
15345 #define I2S_TCSR_SEF_SHIFT                       19
15346 #define I2S_TCSR_WSF_MASK                        0x100000u
15347 #define I2S_TCSR_WSF_SHIFT                       20
15348 #define I2S_TCSR_SR_MASK                         0x1000000u
15349 #define I2S_TCSR_SR_SHIFT                        24
15350 #define I2S_TCSR_FR_MASK                         0x2000000u
15351 #define I2S_TCSR_FR_SHIFT                        25
15352 #define I2S_TCSR_BCE_MASK                        0x10000000u
15353 #define I2S_TCSR_BCE_SHIFT                       28
15354 #define I2S_TCSR_DBGE_MASK                       0x20000000u
15355 #define I2S_TCSR_DBGE_SHIFT                      29
15356 #define I2S_TCSR_STOPE_MASK                      0x40000000u
15357 #define I2S_TCSR_STOPE_SHIFT                     30
15358 #define I2S_TCSR_TE_MASK                         0x80000000u
15359 #define I2S_TCSR_TE_SHIFT                        31
15360 /* TCR1 Bit Fields */
15361 #define I2S_TCR1_TFW_MASK                        0x1Fu
15362 #define I2S_TCR1_TFW_SHIFT                       0
15363 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
15364 /* TCR2 Bit Fields */
15365 #define I2S_TCR2_DIV_MASK                        0xFFu
15366 #define I2S_TCR2_DIV_SHIFT                       0
15367 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
15368 #define I2S_TCR2_BCD_MASK                        0x1000000u
15369 #define I2S_TCR2_BCD_SHIFT                       24
15370 #define I2S_TCR2_BCP_MASK                        0x2000000u
15371 #define I2S_TCR2_BCP_SHIFT                       25
15372 #define I2S_TCR2_MSEL_MASK                       0xC000000u
15373 #define I2S_TCR2_MSEL_SHIFT                      26
15374 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
15375 #define I2S_TCR2_BCI_MASK                        0x10000000u
15376 #define I2S_TCR2_BCI_SHIFT                       28
15377 #define I2S_TCR2_BCS_MASK                        0x20000000u
15378 #define I2S_TCR2_BCS_SHIFT                       29
15379 #define I2S_TCR2_SYNC_MASK                       0xC0000000u
15380 #define I2S_TCR2_SYNC_SHIFT                      30
15381 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
15382 /* TCR3 Bit Fields */
15383 #define I2S_TCR3_WDFL_MASK                       0x1Fu
15384 #define I2S_TCR3_WDFL_SHIFT                      0
15385 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
15386 #define I2S_TCR3_TCE_MASK                        0x10000u
15387 #define I2S_TCR3_TCE_SHIFT                       16
15388 /* TCR4 Bit Fields */
15389 #define I2S_TCR4_FSD_MASK                        0x1u
15390 #define I2S_TCR4_FSD_SHIFT                       0
15391 #define I2S_TCR4_FSP_MASK                        0x2u
15392 #define I2S_TCR4_FSP_SHIFT                       1
15393 #define I2S_TCR4_FSE_MASK                        0x8u
15394 #define I2S_TCR4_FSE_SHIFT                       3
15395 #define I2S_TCR4_MF_MASK                         0x10u
15396 #define I2S_TCR4_MF_SHIFT                        4
15397 #define I2S_TCR4_SYWD_MASK                       0x1F00u
15398 #define I2S_TCR4_SYWD_SHIFT                      8
15399 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
15400 #define I2S_TCR4_FRSZ_MASK                       0x1F0000u
15401 #define I2S_TCR4_FRSZ_SHIFT                      16
15402 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
15403 /* TCR5 Bit Fields */
15404 #define I2S_TCR5_FBT_MASK                        0x1F00u
15405 #define I2S_TCR5_FBT_SHIFT                       8
15406 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
15407 #define I2S_TCR5_W0W_MASK                        0x1F0000u
15408 #define I2S_TCR5_W0W_SHIFT                       16
15409 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
15410 #define I2S_TCR5_WNW_MASK                        0x1F000000u
15411 #define I2S_TCR5_WNW_SHIFT                       24
15412 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
15413 /* TDR Bit Fields */
15414 #define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
15415 #define I2S_TDR_TDR_SHIFT                        0
15416 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
15417 /* TFR Bit Fields */
15418 #define I2S_TFR_RFP_MASK                         0x3Fu
15419 #define I2S_TFR_RFP_SHIFT                        0
15420 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
15421 #define I2S_TFR_WFP_MASK                         0x3F0000u
15422 #define I2S_TFR_WFP_SHIFT                        16
15423 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
15424 /* TMR Bit Fields */
15425 #define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
15426 #define I2S_TMR_TWM_SHIFT                        0
15427 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
15428 /* RCSR Bit Fields */
15429 #define I2S_RCSR_FRDE_MASK                       0x1u
15430 #define I2S_RCSR_FRDE_SHIFT                      0
15431 #define I2S_RCSR_FWDE_MASK                       0x2u
15432 #define I2S_RCSR_FWDE_SHIFT                      1
15433 #define I2S_RCSR_FRIE_MASK                       0x100u
15434 #define I2S_RCSR_FRIE_SHIFT                      8
15435 #define I2S_RCSR_FWIE_MASK                       0x200u
15436 #define I2S_RCSR_FWIE_SHIFT                      9
15437 #define I2S_RCSR_FEIE_MASK                       0x400u
15438 #define I2S_RCSR_FEIE_SHIFT                      10
15439 #define I2S_RCSR_SEIE_MASK                       0x800u
15440 #define I2S_RCSR_SEIE_SHIFT                      11
15441 #define I2S_RCSR_WSIE_MASK                       0x1000u
15442 #define I2S_RCSR_WSIE_SHIFT                      12
15443 #define I2S_RCSR_FRF_MASK                        0x10000u
15444 #define I2S_RCSR_FRF_SHIFT                       16
15445 #define I2S_RCSR_FWF_MASK                        0x20000u
15446 #define I2S_RCSR_FWF_SHIFT                       17
15447 #define I2S_RCSR_FEF_MASK                        0x40000u
15448 #define I2S_RCSR_FEF_SHIFT                       18
15449 #define I2S_RCSR_SEF_MASK                        0x80000u
15450 #define I2S_RCSR_SEF_SHIFT                       19
15451 #define I2S_RCSR_WSF_MASK                        0x100000u
15452 #define I2S_RCSR_WSF_SHIFT                       20
15453 #define I2S_RCSR_SR_MASK                         0x1000000u
15454 #define I2S_RCSR_SR_SHIFT                        24
15455 #define I2S_RCSR_FR_MASK                         0x2000000u
15456 #define I2S_RCSR_FR_SHIFT                        25
15457 #define I2S_RCSR_BCE_MASK                        0x10000000u
15458 #define I2S_RCSR_BCE_SHIFT                       28
15459 #define I2S_RCSR_DBGE_MASK                       0x20000000u
15460 #define I2S_RCSR_DBGE_SHIFT                      29
15461 #define I2S_RCSR_STOPE_MASK                      0x40000000u
15462 #define I2S_RCSR_STOPE_SHIFT                     30
15463 #define I2S_RCSR_RE_MASK                         0x80000000u
15464 #define I2S_RCSR_RE_SHIFT                        31
15465 /* RCR1 Bit Fields */
15466 #define I2S_RCR1_RFW_MASK                        0x1Fu
15467 #define I2S_RCR1_RFW_SHIFT                       0
15468 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
15469 /* RCR2 Bit Fields */
15470 #define I2S_RCR2_DIV_MASK                        0xFFu
15471 #define I2S_RCR2_DIV_SHIFT                       0
15472 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
15473 #define I2S_RCR2_BCD_MASK                        0x1000000u
15474 #define I2S_RCR2_BCD_SHIFT                       24
15475 #define I2S_RCR2_BCP_MASK                        0x2000000u
15476 #define I2S_RCR2_BCP_SHIFT                       25
15477 #define I2S_RCR2_MSEL_MASK                       0xC000000u
15478 #define I2S_RCR2_MSEL_SHIFT                      26
15479 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
15480 #define I2S_RCR2_BCI_MASK                        0x10000000u
15481 #define I2S_RCR2_BCI_SHIFT                       28
15482 #define I2S_RCR2_BCS_MASK                        0x20000000u
15483 #define I2S_RCR2_BCS_SHIFT                       29
15484 #define I2S_RCR2_SYNC_MASK                       0xC0000000u
15485 #define I2S_RCR2_SYNC_SHIFT                      30
15486 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
15487 /* RCR3 Bit Fields */
15488 #define I2S_RCR3_WDFL_MASK                       0x1Fu
15489 #define I2S_RCR3_WDFL_SHIFT                      0
15490 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
15491 #define I2S_RCR3_RCE_MASK                        0x10000u
15492 #define I2S_RCR3_RCE_SHIFT                       16
15493 /* RCR4 Bit Fields */
15494 #define I2S_RCR4_FSD_MASK                        0x1u
15495 #define I2S_RCR4_FSD_SHIFT                       0
15496 #define I2S_RCR4_FSP_MASK                        0x2u
15497 #define I2S_RCR4_FSP_SHIFT                       1
15498 #define I2S_RCR4_FSE_MASK                        0x8u
15499 #define I2S_RCR4_FSE_SHIFT                       3
15500 #define I2S_RCR4_MF_MASK                         0x10u
15501 #define I2S_RCR4_MF_SHIFT                        4
15502 #define I2S_RCR4_SYWD_MASK                       0x1F00u
15503 #define I2S_RCR4_SYWD_SHIFT                      8
15504 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
15505 #define I2S_RCR4_FRSZ_MASK                       0x1F0000u
15506 #define I2S_RCR4_FRSZ_SHIFT                      16
15507 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
15508 /* RCR5 Bit Fields */
15509 #define I2S_RCR5_FBT_MASK                        0x1F00u
15510 #define I2S_RCR5_FBT_SHIFT                       8
15511 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
15512 #define I2S_RCR5_W0W_MASK                        0x1F0000u
15513 #define I2S_RCR5_W0W_SHIFT                       16
15514 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
15515 #define I2S_RCR5_WNW_MASK                        0x1F000000u
15516 #define I2S_RCR5_WNW_SHIFT                       24
15517 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
15518 /* RDR Bit Fields */
15519 #define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
15520 #define I2S_RDR_RDR_SHIFT                        0
15521 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
15522 /* RFR Bit Fields */
15523 #define I2S_RFR_RFP_MASK                         0x3Fu
15524 #define I2S_RFR_RFP_SHIFT                        0
15525 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
15526 #define I2S_RFR_WFP_MASK                         0x3F0000u
15527 #define I2S_RFR_WFP_SHIFT                        16
15528 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
15529 /* RMR Bit Fields */
15530 #define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
15531 #define I2S_RMR_RWM_SHIFT                        0
15532 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
15533 
15534 /*!
15535  * @}
15536  */ /* end of group I2S_Register_Masks */
15537 
15538 /* I2S - Peripheral instance base addresses */
15539 /** Peripheral I2S1 base address */
15540 #define I2S1_BASE                                (0x421D4000u)
15541 /** Peripheral I2S1 base pointer */
15542 #define I2S1                                     ((I2S_Type *)I2S1_BASE)
15543 #define I2S1_BASE_PTR                            (I2S1)
15544 /** Peripheral I2S2 base address */
15545 #define I2S2_BASE                                (0x421DC000u)
15546 /** Peripheral I2S2 base pointer */
15547 #define I2S2                                     ((I2S_Type *)I2S2_BASE)
15548 #define I2S2_BASE_PTR                            (I2S2)
15549 /** Array initializer of I2S peripheral base addresses */
15550 #define I2S_BASE_ADDRS                           { I2S1_BASE, I2S2_BASE }
15551 /** Array initializer of I2S peripheral base pointers */
15552 #define I2S_BASE_PTRS                            { I2S1, I2S2 }
15553 /** Interrupt vectors for the I2S peripheral type */
15554 #define SAI_IRQS                                 { SAI1_IRQn, SAI2_IRQn }
15555 
15556 /* ----------------------------------------------------------------------------
15557    -- I2S - Register accessor macros
15558    ---------------------------------------------------------------------------- */
15559 
15560 /*!
15561  * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
15562  * @{
15563  */
15564 
15565 /* I2S - Register instance definitions */
15566 /* I2S1 */
15567 #define I2S1_TCSR                                I2S_TCSR_REG(I2S1_BASE_PTR)
15568 #define I2S1_TCR1                                I2S_TCR1_REG(I2S1_BASE_PTR)
15569 #define I2S1_TCR2                                I2S_TCR2_REG(I2S1_BASE_PTR)
15570 #define I2S1_TCR3                                I2S_TCR3_REG(I2S1_BASE_PTR)
15571 #define I2S1_TCR4                                I2S_TCR4_REG(I2S1_BASE_PTR)
15572 #define I2S1_TCR5                                I2S_TCR5_REG(I2S1_BASE_PTR)
15573 #define I2S1_TDR0                                I2S_TDR_REG(I2S1_BASE_PTR,0)
15574 #define I2S1_TFR0                                I2S_TFR_REG(I2S1_BASE_PTR,0)
15575 #define I2S1_TMR                                 I2S_TMR_REG(I2S1_BASE_PTR)
15576 #define I2S1_RCSR                                I2S_RCSR_REG(I2S1_BASE_PTR)
15577 #define I2S1_RCR1                                I2S_RCR1_REG(I2S1_BASE_PTR)
15578 #define I2S1_RCR2                                I2S_RCR2_REG(I2S1_BASE_PTR)
15579 #define I2S1_RCR3                                I2S_RCR3_REG(I2S1_BASE_PTR)
15580 #define I2S1_RCR4                                I2S_RCR4_REG(I2S1_BASE_PTR)
15581 #define I2S1_RCR5                                I2S_RCR5_REG(I2S1_BASE_PTR)
15582 #define I2S1_RDR0                                I2S_RDR_REG(I2S1_BASE_PTR,0)
15583 #define I2S1_RFR0                                I2S_RFR_REG(I2S1_BASE_PTR,0)
15584 #define I2S1_RMR                                 I2S_RMR_REG(I2S1_BASE_PTR)
15585 /* I2S2 */
15586 #define I2S2_TCSR                                I2S_TCSR_REG(I2S2_BASE_PTR)
15587 #define I2S2_TCR1                                I2S_TCR1_REG(I2S2_BASE_PTR)
15588 #define I2S2_TCR2                                I2S_TCR2_REG(I2S2_BASE_PTR)
15589 #define I2S2_TCR3                                I2S_TCR3_REG(I2S2_BASE_PTR)
15590 #define I2S2_TCR4                                I2S_TCR4_REG(I2S2_BASE_PTR)
15591 #define I2S2_TCR5                                I2S_TCR5_REG(I2S2_BASE_PTR)
15592 #define I2S2_TDR0                                I2S_TDR_REG(I2S2_BASE_PTR,0)
15593 #define I2S2_TFR0                                I2S_TFR_REG(I2S2_BASE_PTR,0)
15594 #define I2S2_TMR                                 I2S_TMR_REG(I2S2_BASE_PTR)
15595 #define I2S2_RCSR                                I2S_RCSR_REG(I2S2_BASE_PTR)
15596 #define I2S2_RCR1                                I2S_RCR1_REG(I2S2_BASE_PTR)
15597 #define I2S2_RCR2                                I2S_RCR2_REG(I2S2_BASE_PTR)
15598 #define I2S2_RCR3                                I2S_RCR3_REG(I2S2_BASE_PTR)
15599 #define I2S2_RCR4                                I2S_RCR4_REG(I2S2_BASE_PTR)
15600 #define I2S2_RCR5                                I2S_RCR5_REG(I2S2_BASE_PTR)
15601 #define I2S2_RDR0                                I2S_RDR_REG(I2S2_BASE_PTR,0)
15602 #define I2S2_RFR0                                I2S_RFR_REG(I2S2_BASE_PTR,0)
15603 #define I2S2_RMR                                 I2S_RMR_REG(I2S2_BASE_PTR)
15604 /* I2S - Register array accessors */
15605 #define I2S1_TDR(index)                          I2S_TDR_REG(I2S1_BASE_PTR,index)
15606 #define I2S2_TDR(index)                          I2S_TDR_REG(I2S2_BASE_PTR,index)
15607 #define I2S1_TFR(index)                          I2S_TFR_REG(I2S1_BASE_PTR,index)
15608 #define I2S2_TFR(index)                          I2S_TFR_REG(I2S2_BASE_PTR,index)
15609 #define I2S1_RDR(index)                          I2S_RDR_REG(I2S1_BASE_PTR,index)
15610 #define I2S2_RDR(index)                          I2S_RDR_REG(I2S2_BASE_PTR,index)
15611 #define I2S1_RFR(index)                          I2S_RFR_REG(I2S1_BASE_PTR,index)
15612 #define I2S2_RFR(index)                          I2S_RFR_REG(I2S2_BASE_PTR,index)
15613 
15614 /*!
15615  * @}
15616  */ /* end of group I2S_Register_Accessor_Macros */
15617 
15618 /*!
15619  * @}
15620  */ /* end of group I2S_Peripheral */
15621 
15622 /* ----------------------------------------------------------------------------
15623    -- IOMUXC Peripheral Access Layer
15624    ---------------------------------------------------------------------------- */
15625 
15626 /*!
15627  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
15628  * @{
15629  */
15630 
15631 /** IOMUXC - Register Layout Typedef */
15632 typedef struct {
15633   uint8_t RESERVED_0[20];
15634   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO00;              /**< Pad Mux Register, offset: 0x14 */
15635   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO01;              /**< Pad Mux Register, offset: 0x18 */
15636   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO02;              /**< Pad Mux Register, offset: 0x1C */
15637   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO03;              /**< Pad Mux Register, offset: 0x20 */
15638   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO04;              /**< Pad Mux Register, offset: 0x24 */
15639   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO05;              /**< Pad Mux Register, offset: 0x28 */
15640   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO06;              /**< Pad Mux Register, offset: 0x2C */
15641   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO07;              /**< Pad Mux Register, offset: 0x30 */
15642   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO08;              /**< Pad Mux Register, offset: 0x34 */
15643   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO09;              /**< Pad Mux Register, offset: 0x38 */
15644   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO10;              /**< Pad Mux Register, offset: 0x3C */
15645   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO11;              /**< Pad Mux Register, offset: 0x40 */
15646   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO12;              /**< Pad Mux Register, offset: 0x44 */
15647   __IO  uint32_t SW_MUX_CTL_PAD_GPIO1_IO13;              /**< Pad Mux Register, offset: 0x48 */
15648   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA00;              /**< Pad Mux Register, offset: 0x4C */
15649   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA01;              /**< Pad Mux Register, offset: 0x50 */
15650   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA02;              /**< Pad Mux Register, offset: 0x54 */
15651   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA03;              /**< Pad Mux Register, offset: 0x58 */
15652   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA04;              /**< Pad Mux Register, offset: 0x5C */
15653   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA05;              /**< Pad Mux Register, offset: 0x60 */
15654   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA06;              /**< Pad Mux Register, offset: 0x64 */
15655   __IO  uint32_t SW_MUX_CTL_PAD_CSI_DATA07;              /**< Pad Mux Register, offset: 0x68 */
15656   __IO  uint32_t SW_MUX_CTL_PAD_CSI_HSYNC;               /**< Pad Mux Register, offset: 0x6C */
15657   __IO  uint32_t SW_MUX_CTL_PAD_CSI_MCLK;                /**< Pad Mux Register, offset: 0x70 */
15658   __IO  uint32_t SW_MUX_CTL_PAD_CSI_PIXCLK;              /**< Pad Mux Register, offset: 0x74 */
15659   __IO  uint32_t SW_MUX_CTL_PAD_CSI_VSYNC;               /**< Pad Mux Register, offset: 0x78 */
15660   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_COL;               /**< Pad Mux Register, offset: 0x7C */
15661   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_CRS;               /**< Pad Mux Register, offset: 0x80 */
15662   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_MDC;               /**< Pad Mux Register, offset: 0x84 */
15663   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_MDIO;              /**< Pad Mux Register, offset: 0x88 */
15664   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_RX_CLK;            /**< Pad Mux Register, offset: 0x8C */
15665   __IO  uint32_t SW_MUX_CTL_PAD_ENET1_TX_CLK;            /**< Pad Mux Register, offset: 0x90 */
15666   __IO  uint32_t SW_MUX_CTL_PAD_ENET2_COL;               /**< Pad Mux Register, offset: 0x94 */
15667   __IO  uint32_t SW_MUX_CTL_PAD_ENET2_CRS;               /**< Pad Mux Register, offset: 0x98 */
15668   __IO  uint32_t SW_MUX_CTL_PAD_ENET2_RX_CLK;            /**< Pad Mux Register, offset: 0x9C */
15669   __IO  uint32_t SW_MUX_CTL_PAD_ENET2_TX_CLK;            /**< Pad Mux Register, offset: 0xA0 */
15670   __IO  uint32_t SW_MUX_CTL_PAD_KEY_COL0;                /**< Pad Mux Register, offset: 0xA4 */
15671   __IO  uint32_t SW_MUX_CTL_PAD_KEY_COL1;                /**< Pad Mux Register, offset: 0xA8 */
15672   __IO  uint32_t SW_MUX_CTL_PAD_KEY_COL2;                /**< Pad Mux Register, offset: 0xAC */
15673   __IO  uint32_t SW_MUX_CTL_PAD_KEY_COL3;                /**< Pad Mux Register, offset: 0xB0 */
15674   __IO  uint32_t SW_MUX_CTL_PAD_KEY_COL4;                /**< Pad Mux Register, offset: 0xB4 */
15675   __IO  uint32_t SW_MUX_CTL_PAD_KEY_ROW0;                /**< Pad Mux Register, offset: 0xB8 */
15676   __IO  uint32_t SW_MUX_CTL_PAD_KEY_ROW1;                /**< Pad Mux Register, offset: 0xBC */
15677   __IO  uint32_t SW_MUX_CTL_PAD_KEY_ROW2;                /**< Pad Mux Register, offset: 0xC0 */
15678   __IO  uint32_t SW_MUX_CTL_PAD_KEY_ROW3;                /**< Pad Mux Register, offset: 0xC4 */
15679   __IO  uint32_t SW_MUX_CTL_PAD_KEY_ROW4;                /**< Pad Mux Register, offset: 0xC8 */
15680   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_CLK;                /**< Pad Mux Register, offset: 0xCC */
15681   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA00;             /**< Pad Mux Register, offset: 0xD0 */
15682   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA01;             /**< Pad Mux Register, offset: 0xD4 */
15683   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA02;             /**< Pad Mux Register, offset: 0xD8 */
15684   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA03;             /**< Pad Mux Register, offset: 0xDC */
15685   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA04;             /**< Pad Mux Register, offset: 0xE0 */
15686   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA05;             /**< Pad Mux Register, offset: 0xE4 */
15687   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA06;             /**< Pad Mux Register, offset: 0xE8 */
15688   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA07;             /**< Pad Mux Register, offset: 0xEC */
15689   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA08;             /**< Pad Mux Register, offset: 0xF0 */
15690   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA09;             /**< Pad Mux Register, offset: 0xF4 */
15691   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA10;             /**< Pad Mux Register, offset: 0xF8 */
15692   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA11;             /**< Pad Mux Register, offset: 0xFC */
15693   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA12;             /**< Pad Mux Register, offset: 0x100 */
15694   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA13;             /**< Pad Mux Register, offset: 0x104 */
15695   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA14;             /**< Pad Mux Register, offset: 0x108 */
15696   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA15;             /**< Pad Mux Register, offset: 0x10C */
15697   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA16;             /**< Pad Mux Register, offset: 0x110 */
15698   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA17;             /**< Pad Mux Register, offset: 0x114 */
15699   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA18;             /**< Pad Mux Register, offset: 0x118 */
15700   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA19;             /**< Pad Mux Register, offset: 0x11C */
15701   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA20;             /**< Pad Mux Register, offset: 0x120 */
15702   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA21;             /**< Pad Mux Register, offset: 0x124 */
15703   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA22;             /**< Pad Mux Register, offset: 0x128 */
15704   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_DATA23;             /**< Pad Mux Register, offset: 0x12C */
15705   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_ENABLE;             /**< Pad Mux Register, offset: 0x130 */
15706   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_HSYNC;              /**< Pad Mux Register, offset: 0x134 */
15707   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_RESET;              /**< Pad Mux Register, offset: 0x138 */
15708   __IO  uint32_t SW_MUX_CTL_PAD_LCD1_VSYNC;              /**< Pad Mux Register, offset: 0x13C */
15709   __IO  uint32_t SW_MUX_CTL_PAD_NAND_ALE;                /**< Pad Mux Register, offset: 0x140 */
15710   __IO  uint32_t SW_MUX_CTL_PAD_NAND_CE0_B;              /**< Pad Mux Register, offset: 0x144 */
15711   __IO  uint32_t SW_MUX_CTL_PAD_NAND_CE1_B;              /**< Pad Mux Register, offset: 0x148 */
15712   __IO  uint32_t SW_MUX_CTL_PAD_NAND_CLE;                /**< Pad Mux Register, offset: 0x14C */
15713   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA00;             /**< Pad Mux Register, offset: 0x150 */
15714   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA01;             /**< Pad Mux Register, offset: 0x154 */
15715   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA02;             /**< Pad Mux Register, offset: 0x158 */
15716   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA03;             /**< Pad Mux Register, offset: 0x15C */
15717   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA04;             /**< Pad Mux Register, offset: 0x160 */
15718   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA05;             /**< Pad Mux Register, offset: 0x164 */
15719   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA06;             /**< Pad Mux Register, offset: 0x168 */
15720   __IO  uint32_t SW_MUX_CTL_PAD_NAND_DATA07;             /**< Pad Mux Register, offset: 0x16C */
15721   __IO  uint32_t SW_MUX_CTL_PAD_NAND_RE_B;               /**< Pad Mux Register, offset: 0x170 */
15722   __IO  uint32_t SW_MUX_CTL_PAD_NAND_READY_B;            /**< Pad Mux Register, offset: 0x174 */
15723   __IO  uint32_t SW_MUX_CTL_PAD_NAND_WE_B;               /**< Pad Mux Register, offset: 0x178 */
15724   __IO  uint32_t SW_MUX_CTL_PAD_NAND_WP_B;               /**< Pad Mux Register, offset: 0x17C */
15725   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA0;            /**< Pad Mux Register, offset: 0x180 */
15726   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA1;            /**< Pad Mux Register, offset: 0x184 */
15727   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA2;            /**< Pad Mux Register, offset: 0x188 */
15728   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA3;            /**< Pad Mux Register, offset: 0x18C */
15729   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_DQS;              /**< Pad Mux Register, offset: 0x190 */
15730   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_SCLK;             /**< Pad Mux Register, offset: 0x194 */
15731   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_SS0_B;            /**< Pad Mux Register, offset: 0x198 */
15732   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1A_SS1_B;            /**< Pad Mux Register, offset: 0x19C */
15733   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA0;            /**< Pad Mux Register, offset: 0x1A0 */
15734   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA1;            /**< Pad Mux Register, offset: 0x1A4 */
15735   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA2;            /**< Pad Mux Register, offset: 0x1A8 */
15736   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA3;            /**< Pad Mux Register, offset: 0x1AC */
15737   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_DQS;              /**< Pad Mux Register, offset: 0x1B0 */
15738   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_SCLK;             /**< Pad Mux Register, offset: 0x1B4 */
15739   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_SS0_B;            /**< Pad Mux Register, offset: 0x1B8 */
15740   __IO  uint32_t SW_MUX_CTL_PAD_QSPI1B_SS1_B;            /**< Pad Mux Register, offset: 0x1BC */
15741   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RD0;              /**< Pad Mux Register, offset: 0x1C0 */
15742   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RD1;              /**< Pad Mux Register, offset: 0x1C4 */
15743   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RD2;              /**< Pad Mux Register, offset: 0x1C8 */
15744   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RD3;              /**< Pad Mux Register, offset: 0x1CC */
15745   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RX_CTL;           /**< Pad Mux Register, offset: 0x1D0 */
15746   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_RXC;              /**< Pad Mux Register, offset: 0x1D4 */
15747   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TD0;              /**< Pad Mux Register, offset: 0x1D8 */
15748   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TD1;              /**< Pad Mux Register, offset: 0x1DC */
15749   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TD2;              /**< Pad Mux Register, offset: 0x1E0 */
15750   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TD3;              /**< Pad Mux Register, offset: 0x1E4 */
15751   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TX_CTL;           /**< Pad Mux Register, offset: 0x1E8 */
15752   __IO  uint32_t SW_MUX_CTL_PAD_RGMII1_TXC;              /**< Pad Mux Register, offset: 0x1EC */
15753   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RD0;              /**< Pad Mux Register, offset: 0x1F0 */
15754   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RD1;              /**< Pad Mux Register, offset: 0x1F4 */
15755   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RD2;              /**< Pad Mux Register, offset: 0x1F8 */
15756   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RD3;              /**< Pad Mux Register, offset: 0x1FC */
15757   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RX_CTL;           /**< Pad Mux Register, offset: 0x200 */
15758   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_RXC;              /**< Pad Mux Register, offset: 0x204 */
15759   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TD0;              /**< Pad Mux Register, offset: 0x208 */
15760   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TD1;              /**< Pad Mux Register, offset: 0x20C */
15761   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TD2;              /**< Pad Mux Register, offset: 0x210 */
15762   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TD3;              /**< Pad Mux Register, offset: 0x214 */
15763   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TX_CTL;           /**< Pad Mux Register, offset: 0x218 */
15764   __IO  uint32_t SW_MUX_CTL_PAD_RGMII2_TXC;              /**< Pad Mux Register, offset: 0x21C */
15765   __IO  uint32_t SW_MUX_CTL_PAD_SD1_CLK;                 /**< Pad Mux Register, offset: 0x220 */
15766   __IO  uint32_t SW_MUX_CTL_PAD_SD1_CMD;                 /**< Pad Mux Register, offset: 0x224 */
15767   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA0;               /**< Pad Mux Register, offset: 0x228 */
15768   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA1;               /**< Pad Mux Register, offset: 0x22C */
15769   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA2;               /**< Pad Mux Register, offset: 0x230 */
15770   __IO  uint32_t SW_MUX_CTL_PAD_SD1_DATA3;               /**< Pad Mux Register, offset: 0x234 */
15771   __IO  uint32_t SW_MUX_CTL_PAD_SD2_CLK;                 /**< Pad Mux Register, offset: 0x238 */
15772   __IO  uint32_t SW_MUX_CTL_PAD_SD2_CMD;                 /**< Pad Mux Register, offset: 0x23C */
15773   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA0;               /**< Pad Mux Register, offset: 0x240 */
15774   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA1;               /**< Pad Mux Register, offset: 0x244 */
15775   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA2;               /**< Pad Mux Register, offset: 0x248 */
15776   __IO  uint32_t SW_MUX_CTL_PAD_SD2_DATA3;               /**< Pad Mux Register, offset: 0x24C */
15777   __IO  uint32_t SW_MUX_CTL_PAD_SD3_CLK;                 /**< Pad Mux Register, offset: 0x250 */
15778   __IO  uint32_t SW_MUX_CTL_PAD_SD3_CMD;                 /**< Pad Mux Register, offset: 0x254 */
15779   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA0;               /**< Pad Mux Register, offset: 0x258 */
15780   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA1;               /**< Pad Mux Register, offset: 0x25C */
15781   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA2;               /**< Pad Mux Register, offset: 0x260 */
15782   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA3;               /**< Pad Mux Register, offset: 0x264 */
15783   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA4;               /**< Pad Mux Register, offset: 0x268 */
15784   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA5;               /**< Pad Mux Register, offset: 0x26C */
15785   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA6;               /**< Pad Mux Register, offset: 0x270 */
15786   __IO  uint32_t SW_MUX_CTL_PAD_SD3_DATA7;               /**< Pad Mux Register, offset: 0x274 */
15787   __IO  uint32_t SW_MUX_CTL_PAD_SD4_CLK;                 /**< Pad Mux Register, offset: 0x278 */
15788   __IO  uint32_t SW_MUX_CTL_PAD_SD4_CMD;                 /**< Pad Mux Register, offset: 0x27C */
15789   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA0;               /**< Pad Mux Register, offset: 0x280 */
15790   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA1;               /**< Pad Mux Register, offset: 0x284 */
15791   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA2;               /**< Pad Mux Register, offset: 0x288 */
15792   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA3;               /**< Pad Mux Register, offset: 0x28C */
15793   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA4;               /**< Pad Mux Register, offset: 0x290 */
15794   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA5;               /**< Pad Mux Register, offset: 0x294 */
15795   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA6;               /**< Pad Mux Register, offset: 0x298 */
15796   __IO  uint32_t SW_MUX_CTL_PAD_SD4_DATA7;               /**< Pad Mux Register, offset: 0x29C */
15797   __IO  uint32_t SW_MUX_CTL_PAD_SD4_RESET_B;             /**< Pad Mux Register, offset: 0x2A0 */
15798   __IO  uint32_t SW_MUX_CTL_PAD_USB_H_DATA;              /**< Pad Mux Register, offset: 0x2A4 */
15799   __IO  uint32_t SW_MUX_CTL_PAD_USB_H_STROBE;            /**< Pad Mux Register, offset: 0x2A8 */
15800   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR00;             /**< Pad Control Register, offset: 0x2AC */
15801   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR01;             /**< Pad Control Register, offset: 0x2B0 */
15802   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR02;             /**< Pad Control Register, offset: 0x2B4 */
15803   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR03;             /**< Pad Control Register, offset: 0x2B8 */
15804   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR04;             /**< Pad Control Register, offset: 0x2BC */
15805   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR05;             /**< Pad Control Register, offset: 0x2C0 */
15806   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR06;             /**< Pad Control Register, offset: 0x2C4 */
15807   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR07;             /**< Pad Control Register, offset: 0x2C8 */
15808   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR08;             /**< Pad Control Register, offset: 0x2CC */
15809   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR09;             /**< Pad Control Register, offset: 0x2D0 */
15810   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR10;             /**< Pad Control Register, offset: 0x2D4 */
15811   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR11;             /**< Pad Control Register, offset: 0x2D8 */
15812   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR12;             /**< Pad Control Register, offset: 0x2DC */
15813   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR13;             /**< Pad Control Register, offset: 0x2E0 */
15814   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR14;             /**< Pad Control Register, offset: 0x2E4 */
15815   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ADDR15;             /**< Pad Control Register, offset: 0x2E8 */
15816   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_DQM0;               /**< Pad Control Register, offset: 0x2EC */
15817   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_DQM1;               /**< Pad Control Register, offset: 0x2F0 */
15818   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_DQM2;               /**< Pad Control Register, offset: 0x2F4 */
15819   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_DQM3;               /**< Pad Control Register, offset: 0x2F8 */
15820   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_RAS_B;              /**< Pad Control Register, offset: 0x2FC */
15821   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_CAS_B;              /**< Pad Control Register, offset: 0x300 */
15822   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_CS0_B;              /**< Pad Control Register, offset: 0x304 */
15823   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_CS1_B;              /**< Pad Control Register, offset: 0x308 */
15824   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDWE_B;             /**< Pad Control Register, offset: 0x30C */
15825   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ODT0;               /**< Pad Control Register, offset: 0x310 */
15826   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_ODT1;               /**< Pad Control Register, offset: 0x314 */
15827   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDBA0;              /**< Pad Control Register, offset: 0x318 */
15828   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDBA1;              /**< Pad Control Register, offset: 0x31C */
15829   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDBA2;              /**< Pad Control Register, offset: 0x320 */
15830   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDCKE0;             /**< Pad Control Register, offset: 0x324 */
15831   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDCKE1;             /**< Pad Control Register, offset: 0x328 */
15832   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDCLK0_P;           /**< Pad Control Register, offset: 0x32C */
15833   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDQS0_P;            /**< Pad Control Register, offset: 0x330 */
15834   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDQS1_P;            /**< Pad Control Register, offset: 0x334 */
15835   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDQS2_P;            /**< Pad Control Register, offset: 0x338 */
15836   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_SDQS3_P;            /**< Pad Control Register, offset: 0x33C */
15837   __IO  uint32_t SW_PAD_CTL_PAD_DRAM_RESET;              /**< Pad Control Register, offset: 0x340 */
15838   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_MOD;                /**< Pad Control Register, offset: 0x344 */
15839   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TCK;                /**< Pad Control Register, offset: 0x348 */
15840   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TDI;                /**< Pad Control Register, offset: 0x34C */
15841   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TDO;                /**< Pad Control Register, offset: 0x350 */
15842   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TMS;                /**< Pad Control Register, offset: 0x354 */
15843   __IO  uint32_t SW_PAD_CTL_PAD_JTAG_TRST_B;             /**< Pad Control Register, offset: 0x358 */
15844   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO00;              /**< Pad Control Register, offset: 0x35C */
15845   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO01;              /**< Pad Control Register, offset: 0x360 */
15846   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO02;              /**< Pad Control Register, offset: 0x364 */
15847   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO03;              /**< Pad Control Register, offset: 0x368 */
15848   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO04;              /**< Pad Control Register, offset: 0x36C */
15849   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO05;              /**< Pad Control Register, offset: 0x370 */
15850   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO06;              /**< Pad Control Register, offset: 0x374 */
15851   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO07;              /**< Pad Control Register, offset: 0x378 */
15852   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO08;              /**< Pad Control Register, offset: 0x37C */
15853   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO09;              /**< Pad Control Register, offset: 0x380 */
15854   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO10;              /**< Pad Control Register, offset: 0x384 */
15855   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO11;              /**< Pad Control Register, offset: 0x388 */
15856   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO12;              /**< Pad Control Register, offset: 0x38C */
15857   __IO  uint32_t SW_PAD_CTL_PAD_GPIO1_IO13;              /**< Pad Control Register, offset: 0x390 */
15858   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA00;              /**< Pad Control Register, offset: 0x394 */
15859   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA01;              /**< Pad Control Register, offset: 0x398 */
15860   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA02;              /**< Pad Control Register, offset: 0x39C */
15861   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA03;              /**< Pad Control Register, offset: 0x3A0 */
15862   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA04;              /**< Pad Control Register, offset: 0x3A4 */
15863   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA05;              /**< Pad Control Register, offset: 0x3A8 */
15864   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA06;              /**< Pad Control Register, offset: 0x3AC */
15865   __IO  uint32_t SW_PAD_CTL_PAD_CSI_DATA07;              /**< Pad Control Register, offset: 0x3B0 */
15866   __IO  uint32_t SW_PAD_CTL_PAD_CSI_HSYNC;               /**< Pad Control Register, offset: 0x3B4 */
15867   __IO  uint32_t SW_PAD_CTL_PAD_CSI_MCLK;                /**< Pad Control Register, offset: 0x3B8 */
15868   __IO  uint32_t SW_PAD_CTL_PAD_CSI_PIXCLK;              /**< Pad Control Register, offset: 0x3BC */
15869   __IO  uint32_t SW_PAD_CTL_PAD_CSI_VSYNC;               /**< Pad Control Register, offset: 0x3C0 */
15870   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_COL;               /**< Pad Control Register, offset: 0x3C4 */
15871   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_CRS;               /**< Pad Control Register, offset: 0x3C8 */
15872   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_MDC;               /**< Pad Control Register, offset: 0x3CC */
15873   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_MDIO;              /**< Pad Control Register, offset: 0x3D0 */
15874   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_RX_CLK;            /**< Pad Control Register, offset: 0x3D4 */
15875   __IO  uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK;            /**< Pad Control Register, offset: 0x3D8 */
15876   __IO  uint32_t SW_PAD_CTL_PAD_ENET2_COL;               /**< Pad Control Register, offset: 0x3DC */
15877   __IO  uint32_t SW_PAD_CTL_PAD_ENET2_CRS;               /**< Pad Control Register, offset: 0x3E0 */
15878   __IO  uint32_t SW_PAD_CTL_PAD_ENET2_RX_CLK;            /**< Pad Control Register, offset: 0x3E4 */
15879   __IO  uint32_t SW_PAD_CTL_PAD_ENET2_TX_CLK;            /**< Pad Control Register, offset: 0x3E8 */
15880   __IO  uint32_t SW_PAD_CTL_PAD_KEY_COL0;                /**< Pad Control Register, offset: 0x3EC */
15881   __IO  uint32_t SW_PAD_CTL_PAD_KEY_COL1;                /**< Pad Control Register, offset: 0x3F0 */
15882   __IO  uint32_t SW_PAD_CTL_PAD_KEY_COL2;                /**< Pad Control Register, offset: 0x3F4 */
15883   __IO  uint32_t SW_PAD_CTL_PAD_KEY_COL3;                /**< Pad Control Register, offset: 0x3F8 */
15884   __IO  uint32_t SW_PAD_CTL_PAD_KEY_COL4;                /**< Pad Control Register, offset: 0x3FC */
15885   __IO  uint32_t SW_PAD_CTL_PAD_KEY_ROW0;                /**< Pad Control Register, offset: 0x400 */
15886   __IO  uint32_t SW_PAD_CTL_PAD_KEY_ROW1;                /**< Pad Control Register, offset: 0x404 */
15887   __IO  uint32_t SW_PAD_CTL_PAD_KEY_ROW2;                /**< Pad Control Register, offset: 0x408 */
15888   __IO  uint32_t SW_PAD_CTL_PAD_KEY_ROW3;                /**< Pad Control Register, offset: 0x40C */
15889   __IO  uint32_t SW_PAD_CTL_PAD_KEY_ROW4;                /**< Pad Control Register, offset: 0x410 */
15890   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_CLK;                /**< Pad Control Register, offset: 0x414 */
15891   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA00;             /**< Pad Control Register, offset: 0x418 */
15892   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA01;             /**< Pad Control Register, offset: 0x41C */
15893   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA02;             /**< Pad Control Register, offset: 0x420 */
15894   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA03;             /**< Pad Control Register, offset: 0x424 */
15895   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA04;             /**< Pad Control Register, offset: 0x428 */
15896   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA05;             /**< Pad Control Register, offset: 0x42C */
15897   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA06;             /**< Pad Control Register, offset: 0x430 */
15898   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA07;             /**< Pad Control Register, offset: 0x434 */
15899   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA08;             /**< Pad Control Register, offset: 0x438 */
15900   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA09;             /**< Pad Control Register, offset: 0x43C */
15901   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA10;             /**< Pad Control Register, offset: 0x440 */
15902   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA11;             /**< Pad Control Register, offset: 0x444 */
15903   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA12;             /**< Pad Control Register, offset: 0x448 */
15904   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA13;             /**< Pad Control Register, offset: 0x44C */
15905   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA14;             /**< Pad Control Register, offset: 0x450 */
15906   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA15;             /**< Pad Control Register, offset: 0x454 */
15907   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA16;             /**< Pad Control Register, offset: 0x458 */
15908   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA17;             /**< Pad Control Register, offset: 0x45C */
15909   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA18;             /**< Pad Control Register, offset: 0x460 */
15910   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA19;             /**< Pad Control Register, offset: 0x464 */
15911   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA20;             /**< Pad Control Register, offset: 0x468 */
15912   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA21;             /**< Pad Control Register, offset: 0x46C */
15913   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA22;             /**< Pad Control Register, offset: 0x470 */
15914   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_DATA23;             /**< Pad Control Register, offset: 0x474 */
15915   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_ENABLE;             /**< Pad Control Register, offset: 0x478 */
15916   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_HSYNC;              /**< Pad Control Register, offset: 0x47C */
15917   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_RESET;              /**< Pad Control Register, offset: 0x480 */
15918   __IO  uint32_t SW_PAD_CTL_PAD_LCD1_VSYNC;              /**< Pad Control Register, offset: 0x484 */
15919   __IO  uint32_t SW_PAD_CTL_PAD_NAND_ALE;                /**< Pad Control Register, offset: 0x488 */
15920   __IO  uint32_t SW_PAD_CTL_PAD_NAND_CE0_B;              /**< Pad Control Register, offset: 0x48C */
15921   __IO  uint32_t SW_PAD_CTL_PAD_NAND_CE1_B;              /**< Pad Control Register, offset: 0x490 */
15922   __IO  uint32_t SW_PAD_CTL_PAD_NAND_CLE;                /**< Pad Control Register, offset: 0x494 */
15923   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA00;             /**< Pad Control Register, offset: 0x498 */
15924   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA01;             /**< Pad Control Register, offset: 0x49C */
15925   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA02;             /**< Pad Control Register, offset: 0x4A0 */
15926   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA03;             /**< Pad Control Register, offset: 0x4A4 */
15927   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA04;             /**< Pad Control Register, offset: 0x4A8 */
15928   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA05;             /**< Pad Control Register, offset: 0x4AC */
15929   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA06;             /**< Pad Control Register, offset: 0x4B0 */
15930   __IO  uint32_t SW_PAD_CTL_PAD_NAND_DATA07;             /**< Pad Control Register, offset: 0x4B4 */
15931   __IO  uint32_t SW_PAD_CTL_PAD_NAND_RE_B;               /**< Pad Control Register, offset: 0x4B8 */
15932   __IO  uint32_t SW_PAD_CTL_PAD_NAND_READY_B;            /**< Pad Control Register, offset: 0x4BC */
15933   __IO  uint32_t SW_PAD_CTL_PAD_NAND_WE_B;               /**< Pad Control Register, offset: 0x4C0 */
15934   __IO  uint32_t SW_PAD_CTL_PAD_NAND_WP_B;               /**< Pad Control Register, offset: 0x4C4 */
15935   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA0;            /**< Pad Control Register, offset: 0x4C8 */
15936   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA1;            /**< Pad Control Register, offset: 0x4CC */
15937   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA2;            /**< Pad Control Register, offset: 0x4D0 */
15938   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA3;            /**< Pad Control Register, offset: 0x4D4 */
15939   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_DQS;              /**< Pad Control Register, offset: 0x4D8 */
15940   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_SCLK;             /**< Pad Control Register, offset: 0x4DC */
15941   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_SS0_B;            /**< Pad Control Register, offset: 0x4E0 */
15942   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1A_SS1_B;            /**< Pad Control Register, offset: 0x4E4 */
15943   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA0;            /**< Pad Control Register, offset: 0x4E8 */
15944   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA1;            /**< Pad Control Register, offset: 0x4EC */
15945   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA2;            /**< Pad Control Register, offset: 0x4F0 */
15946   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA3;            /**< Pad Control Register, offset: 0x4F4 */
15947   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_DQS;              /**< Pad Control Register, offset: 0x4F8 */
15948   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_SCLK;             /**< Pad Control Register, offset: 0x4FC */
15949   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_SS0_B;            /**< Pad Control Register, offset: 0x500 */
15950   __IO  uint32_t SW_PAD_CTL_PAD_QSPI1B_SS1_B;            /**< Pad Control Register, offset: 0x504 */
15951   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RD0;              /**< Pad Control Register, offset: 0x508 */
15952   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RD1;              /**< Pad Control Register, offset: 0x50C */
15953   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RD2;              /**< Pad Control Register, offset: 0x510 */
15954   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RD3;              /**< Pad Control Register, offset: 0x514 */
15955   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RX_CTL;           /**< Pad Control Register, offset: 0x518 */
15956   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_RXC;              /**< Pad Control Register, offset: 0x51C */
15957   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TD0;              /**< Pad Control Register, offset: 0x520 */
15958   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TD1;              /**< Pad Control Register, offset: 0x524 */
15959   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TD2;              /**< Pad Control Register, offset: 0x528 */
15960   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TD3;              /**< Pad Control Register, offset: 0x52C */
15961   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TX_CTL;           /**< Pad Control Register, offset: 0x530 */
15962   __IO  uint32_t SW_PAD_CTL_PAD_RGMII1_TXC;              /**< Pad Control Register, offset: 0x534 */
15963   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RD0;              /**< Pad Control Register, offset: 0x538 */
15964   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RD1;              /**< Pad Control Register, offset: 0x53C */
15965   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RD2;              /**< Pad Control Register, offset: 0x540 */
15966   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RD3;              /**< Pad Control Register, offset: 0x544 */
15967   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RX_CTL;           /**< Pad Control Register, offset: 0x548 */
15968   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_RXC;              /**< Pad Control Register, offset: 0x54C */
15969   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TD0;              /**< Pad Control Register, offset: 0x550 */
15970   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TD1;              /**< Pad Control Register, offset: 0x554 */
15971   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TD2;              /**< Pad Control Register, offset: 0x558 */
15972   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TD3;              /**< Pad Control Register, offset: 0x55C */
15973   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TX_CTL;           /**< Pad Control Register, offset: 0x560 */
15974   __IO  uint32_t SW_PAD_CTL_PAD_RGMII2_TXC;              /**< Pad Control Register, offset: 0x564 */
15975   __IO  uint32_t SW_PAD_CTL_PAD_SD1_CLK;                 /**< Pad Control Register, offset: 0x568 */
15976   __IO  uint32_t SW_PAD_CTL_PAD_SD1_CMD;                 /**< Pad Control Register, offset: 0x56C */
15977   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA0;               /**< Pad Control Register, offset: 0x570 */
15978   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA1;               /**< Pad Control Register, offset: 0x574 */
15979   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA2;               /**< Pad Control Register, offset: 0x578 */
15980   __IO  uint32_t SW_PAD_CTL_PAD_SD1_DATA3;               /**< Pad Control Register, offset: 0x57C */
15981   __IO  uint32_t SW_PAD_CTL_PAD_SD2_CLK;                 /**< Pad Control Register, offset: 0x580 */
15982   __IO  uint32_t SW_PAD_CTL_PAD_SD2_CMD;                 /**< Pad Control Register, offset: 0x584 */
15983   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA0;               /**< Pad Control Register, offset: 0x588 */
15984   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA1;               /**< Pad Control Register, offset: 0x58C */
15985   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA2;               /**< Pad Control Register, offset: 0x590 */
15986   __IO  uint32_t SW_PAD_CTL_PAD_SD2_DATA3;               /**< Pad Control Register, offset: 0x594 */
15987   __IO  uint32_t SW_PAD_CTL_PAD_SD3_CLK;                 /**< Pad Control Register, offset: 0x598 */
15988   __IO  uint32_t SW_PAD_CTL_PAD_SD3_CMD;                 /**< Pad Control Register, offset: 0x59C */
15989   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA0;               /**< Pad Control Register, offset: 0x5A0 */
15990   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA1;               /**< Pad Control Register, offset: 0x5A4 */
15991   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA2;               /**< Pad Control Register, offset: 0x5A8 */
15992   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA3;               /**< Pad Control Register, offset: 0x5AC */
15993   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA4;               /**< Pad Control Register, offset: 0x5B0 */
15994   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA5;               /**< Pad Control Register, offset: 0x5B4 */
15995   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA6;               /**< Pad Control Register, offset: 0x5B8 */
15996   __IO  uint32_t SW_PAD_CTL_PAD_SD3_DATA7;               /**< Pad Control Register, offset: 0x5BC */
15997   __IO  uint32_t SW_PAD_CTL_PAD_SD4_CLK;                 /**< Pad Control Register, offset: 0x5C0 */
15998   __IO  uint32_t SW_PAD_CTL_PAD_SD4_CMD;                 /**< Pad Control Register, offset: 0x5C4 */
15999   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA0;               /**< Pad Control Register, offset: 0x5C8 */
16000   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA1;               /**< Pad Control Register, offset: 0x5CC */
16001   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA2;               /**< Pad Control Register, offset: 0x5D0 */
16002   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA3;               /**< Pad Control Register, offset: 0x5D4 */
16003   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA4;               /**< Pad Control Register, offset: 0x5D8 */
16004   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA5;               /**< Pad Control Register, offset: 0x5DC */
16005   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA6;               /**< Pad Control Register, offset: 0x5E0 */
16006   __IO  uint32_t SW_PAD_CTL_PAD_SD4_DATA7;               /**< Pad Control Register, offset: 0x5E4 */
16007   __IO  uint32_t SW_PAD_CTL_PAD_SD4_RESET_B;             /**< Pad Control Register, offset: 0x5E8 */
16008   __IO  uint32_t SW_PAD_CTL_PAD_USB_H_DATA;              /**< Pad Control Register, offset: 0x5EC */
16009   __IO  uint32_t SW_PAD_CTL_PAD_USB_H_STROBE;            /**< Pad Control Register, offset: 0x5F0 */
16010   __IO  uint32_t SW_PAD_CTL_GRP_ADDDS;                   /**< Pad Group Control Register, offset: 0x5F4 */
16011   __IO  uint32_t SW_PAD_CTL_GRP_DDRMODE_CTL;             /**< Pad Group Control Register, offset: 0x5F8 */
16012   __IO  uint32_t SW_PAD_CTL_GRP_DDRPKE;                  /**< Pad Group Control Register, offset: 0x5FC */
16013   __IO  uint32_t SW_PAD_CTL_GRP_DDRPK;                   /**< Pad Group Control Register, offset: 0x600 */
16014   __IO  uint32_t SW_PAD_CTL_GRP_DDRHYS;                  /**< Pad Group Control Register, offset: 0x604 */
16015   __IO  uint32_t SW_PAD_CTL_GRP_DDRMODE;                 /**< Pad Group Control Register, offset: 0x608 */
16016   __IO  uint32_t SW_PAD_CTL_GRP_B0DS;                    /**< Pad Group Control Register, offset: 0x60C */
16017   __IO  uint32_t SW_PAD_CTL_GRP_B1DS;                    /**< Pad Group Control Register, offset: 0x610 */
16018   __IO  uint32_t SW_PAD_CTL_GRP_CTLDS;                   /**< Pad Group Control Register, offset: 0x614 */
16019   __IO  uint32_t SW_PAD_CTL_GRP_DDR_TYPE;                /**< Pad Group Control Register, offset: 0x618 */
16020   __IO  uint32_t SW_PAD_CTL_GRP_B2DS;                    /**< Pad Group Control Register, offset: 0x61C */
16021   __IO  uint32_t SW_PAD_CTL_GRP_B3DS;                    /**< Pad Group Control Register, offset: 0x620 */
16022   __IO  uint32_t ANATOP_USB_OTG_ID_SELECT_INPUT;         /**< Select Input Register, offset: 0x624 */
16023   __IO  uint32_t ANATOP_USB_UH1_ID_SELECT_INPUT;         /**< Select Input Register, offset: 0x628 */
16024   __IO  uint32_t AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x62C */
16025   __IO  uint32_t AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x630 */
16026   __IO  uint32_t AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x634 */
16027   __IO  uint32_t AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x638 */
16028   __IO  uint32_t AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x63C */
16029   __IO  uint32_t AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x640 */
16030   __IO  uint32_t AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x644 */
16031   __IO  uint32_t AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x648 */
16032   __IO  uint32_t AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x64C */
16033   __IO  uint32_t AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x650 */
16034   __IO  uint32_t AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x654 */
16035   __IO  uint32_t AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x658 */
16036   __IO  uint32_t AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x65C */
16037   __IO  uint32_t AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x660 */
16038   __IO  uint32_t AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x664 */
16039   __IO  uint32_t AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x668 */
16040   __IO  uint32_t AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x66C */
16041   __IO  uint32_t AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x670 */
16042   __IO  uint32_t AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x674 */
16043   __IO  uint32_t AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT;    /**< Select Input Register, offset: 0x678 */
16044   __IO  uint32_t AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x67C */
16045   __IO  uint32_t AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x680 */
16046   __IO  uint32_t AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x684 */
16047   __IO  uint32_t AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT;  /**< Select Input Register, offset: 0x688 */
16048   __IO  uint32_t CAN1_IPP_IND_CANRX_SELECT_INPUT;        /**< Select Input Register, offset: 0x68C */
16049   __IO  uint32_t CAN2_IPP_IND_CANRX_SELECT_INPUT;        /**< Select Input Register, offset: 0x690 */
16050   uint8_t RESERVED_1[8];
16051   __IO  uint32_t CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT; /**< Select Input Register, offset: 0x69C */
16052   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_0;          /**< Select Input Register, offset: 0x6A0 */
16053   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_1;          /**< Select Input Register, offset: 0x6A4 */
16054   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_2;          /**< Select Input Register, offset: 0x6A8 */
16055   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_3;          /**< Select Input Register, offset: 0x6AC */
16056   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_4;          /**< Select Input Register, offset: 0x6B0 */
16057   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_5;          /**< Select Input Register, offset: 0x6B4 */
16058   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_6;          /**< Select Input Register, offset: 0x6B8 */
16059   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_7;          /**< Select Input Register, offset: 0x6BC */
16060   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_8;          /**< Select Input Register, offset: 0x6C0 */
16061   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_9;          /**< Select Input Register, offset: 0x6C4 */
16062   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_11;         /**< Select Input Register, offset: 0x6C8 */
16063   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_12;         /**< Select Input Register, offset: 0x6CC */
16064   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_13;         /**< Select Input Register, offset: 0x6D0 */
16065   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_14;         /**< Select Input Register, offset: 0x6D4 */
16066   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_15;         /**< Select Input Register, offset: 0x6D8 */
16067   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_16;         /**< Select Input Register, offset: 0x6DC */
16068   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_17;         /**< Select Input Register, offset: 0x6E0 */
16069   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_18;         /**< Select Input Register, offset: 0x6E4 */
16070   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_19;         /**< Select Input Register, offset: 0x6E8 */
16071   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_20;         /**< Select Input Register, offset: 0x6EC */
16072   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_21;         /**< Select Input Register, offset: 0x6F0 */
16073   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_22;         /**< Select Input Register, offset: 0x6F4 */
16074   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_23;         /**< Select Input Register, offset: 0x6F8 */
16075   __IO  uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_10;         /**< Select Input Register, offset: 0x6FC */
16076   __IO  uint32_t CSI1_IPP_CSI_HSYNC_SELECT_INPUT;        /**< Select Input Register, offset: 0x700 */
16077   __IO  uint32_t CSI1_IPP_CSI_PIXCLK_SELECT_INPUT;       /**< Select Input Register, offset: 0x704 */
16078   __IO  uint32_t CSI1_IPP_CSI_VSYNC_SELECT_INPUT;        /**< Select Input Register, offset: 0x708 */
16079   __IO  uint32_t CSI1_TVDECODER_IN_FIELD_SELECT_INPUT;   /**< Select Input Register, offset: 0x70C */
16080   __IO  uint32_t ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT;    /**< Select Input Register, offset: 0x710 */
16081   __IO  uint32_t ECSPI1_IPP_IND_MISO_SELECT_INPUT;       /**< Select Input Register, offset: 0x714 */
16082   __IO  uint32_t ECSPI1_IPP_IND_MOSI_SELECT_INPUT;       /**< Select Input Register, offset: 0x718 */
16083   __IO  uint32_t ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0;     /**< Select Input Register, offset: 0x71C */
16084   __IO  uint32_t ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT;    /**< Select Input Register, offset: 0x720 */
16085   __IO  uint32_t ECSPI2_IPP_IND_MISO_SELECT_INPUT;       /**< Select Input Register, offset: 0x724 */
16086   __IO  uint32_t ECSPI2_IPP_IND_MOSI_SELECT_INPUT;       /**< Select Input Register, offset: 0x728 */
16087   __IO  uint32_t ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0;     /**< Select Input Register, offset: 0x72C */
16088   __IO  uint32_t ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT;    /**< Select Input Register, offset: 0x730 */
16089   __IO  uint32_t ECSPI3_IPP_IND_MISO_SELECT_INPUT;       /**< Select Input Register, offset: 0x734 */
16090   __IO  uint32_t ECSPI3_IPP_IND_MOSI_SELECT_INPUT;       /**< Select Input Register, offset: 0x738 */
16091   __IO  uint32_t ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0;     /**< Select Input Register, offset: 0x73C */
16092   __IO  uint32_t ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT;    /**< Select Input Register, offset: 0x740 */
16093   __IO  uint32_t ECSPI4_IPP_IND_MISO_SELECT_INPUT;       /**< Select Input Register, offset: 0x744 */
16094   __IO  uint32_t ECSPI4_IPP_IND_MOSI_SELECT_INPUT;       /**< Select Input Register, offset: 0x748 */
16095   __IO  uint32_t ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0;     /**< Select Input Register, offset: 0x74C */
16096   __IO  uint32_t ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT;    /**< Select Input Register, offset: 0x750 */
16097   __IO  uint32_t ECSPI5_IPP_IND_MISO_SELECT_INPUT;       /**< Select Input Register, offset: 0x754 */
16098   __IO  uint32_t ECSPI5_IPP_IND_MOSI_SELECT_INPUT;       /**< Select Input Register, offset: 0x758 */
16099   __IO  uint32_t ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0;     /**< Select Input Register, offset: 0x75C */
16100   __IO  uint32_t ENET1_IPG_CLK_RMII_SELECT_INPUT;        /**< Select Input Register, offset: 0x760 */
16101   __IO  uint32_t ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT;   /**< Select Input Register, offset: 0x764 */
16102   __IO  uint32_t ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT;  /**< Select Input Register, offset: 0x768 */
16103   __IO  uint32_t ENET2_IPG_CLK_RMII_SELECT_INPUT;        /**< Select Input Register, offset: 0x76C */
16104   __IO  uint32_t ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT;   /**< Select Input Register, offset: 0x770 */
16105   __IO  uint32_t ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT;  /**< Select Input Register, offset: 0x774 */
16106   __IO  uint32_t ESAI_IPP_IND_FSR_SELECT_INPUT;          /**< Select Input Register, offset: 0x778 */
16107   __IO  uint32_t ESAI_IPP_IND_FST_SELECT_INPUT;          /**< Select Input Register, offset: 0x77C */
16108   __IO  uint32_t ESAI_IPP_IND_HCKR_SELECT_INPUT;         /**< Select Input Register, offset: 0x780 */
16109   __IO  uint32_t ESAI_IPP_IND_HCKT_SELECT_INPUT;         /**< Select Input Register, offset: 0x784 */
16110   __IO  uint32_t ESAI_IPP_IND_SCKR_SELECT_INPUT;         /**< Select Input Register, offset: 0x788 */
16111   __IO  uint32_t ESAI_IPP_IND_SCKT_SELECT_INPUT;         /**< Select Input Register, offset: 0x78C */
16112   __IO  uint32_t ESAI_IPP_IND_SDO0_SELECT_INPUT;         /**< Select Input Register, offset: 0x790 */
16113   __IO  uint32_t ESAI_IPP_IND_SDO1_SELECT_INPUT;         /**< Select Input Register, offset: 0x794 */
16114   __IO  uint32_t ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT;    /**< Select Input Register, offset: 0x798 */
16115   __IO  uint32_t ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT;    /**< Select Input Register, offset: 0x79C */
16116   __IO  uint32_t ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT;    /**< Select Input Register, offset: 0x7A0 */
16117   __IO  uint32_t ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT;    /**< Select Input Register, offset: 0x7A4 */
16118   __IO  uint32_t I2C1_IPP_SCL_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7A8 */
16119   __IO  uint32_t I2C1_IPP_SDA_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7AC */
16120   __IO  uint32_t I2C2_IPP_SCL_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7B0 */
16121   __IO  uint32_t I2C2_IPP_SDA_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7B4 */
16122   __IO  uint32_t I2C3_IPP_SCL_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7B8 */
16123   __IO  uint32_t I2C3_IPP_SDA_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7BC */
16124   __IO  uint32_t I2C4_IPP_SCL_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7C0 */
16125   __IO  uint32_t I2C4_IPP_SDA_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7C4 */
16126   __IO  uint32_t KPP_IPP_IND_COL_SELECT_INPUT_5;         /**< Select Input Register, offset: 0x7C8 */
16127   __IO  uint32_t KPP_IPP_IND_COL_SELECT_INPUT_6;         /**< Select Input Register, offset: 0x7CC */
16128   __IO  uint32_t KPP_IPP_IND_COL_SELECT_INPUT_7;         /**< Select Input Register, offset: 0x7D0 */
16129   __IO  uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_5;         /**< Select Input Register, offset: 0x7D4 */
16130   __IO  uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_6;         /**< Select Input Register, offset: 0x7D8 */
16131   __IO  uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_7;         /**< Select Input Register, offset: 0x7DC */
16132   __IO  uint32_t LCD1_BUSY_SELECT_INPUT;                 /**< Select Input Register, offset: 0x7E0 */
16133   __IO  uint32_t LCD2_BUSY_SELECT_INPUT;                 /**< Select Input Register, offset: 0x7E4 */
16134   __IO  uint32_t MLB_MLB_CLK_IN_SELECT_INPUT;            /**< Select Input Register, offset: 0x7E8 */
16135   __IO  uint32_t MLB_MLB_DATA_IN_SELECT_INPUT;           /**< Select Input Register, offset: 0x7EC */
16136   __IO  uint32_t MLB_MLB_SIG_IN_SELECT_INPUT;            /**< Select Input Register, offset: 0x7F0 */
16137   __IO  uint32_t SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT;   /**< Select Input Register, offset: 0x7F4 */
16138   __IO  uint32_t SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0; /**< Select Input Register, offset: 0x7F8 */
16139   __IO  uint32_t SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT;   /**< Select Input Register, offset: 0x7FC */
16140   __IO  uint32_t SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT;   /**< Select Input Register, offset: 0x800 */
16141   __IO  uint32_t SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT;   /**< Select Input Register, offset: 0x804 */
16142   __IO  uint32_t SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT;   /**< Select Input Register, offset: 0x808 */
16143   __IO  uint32_t SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0; /**< Select Input Register, offset: 0x80C */
16144   __IO  uint32_t SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT;   /**< Select Input Register, offset: 0x810 */
16145   __IO  uint32_t SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT;   /**< Select Input Register, offset: 0x814 */
16146   __IO  uint32_t SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT;   /**< Select Input Register, offset: 0x818 */
16147   __IO  uint32_t SDMA_EVENTS_SELECT_INPUT_14;            /**< Select Input Register, offset: 0x81C */
16148   __IO  uint32_t SDMA_EVENTS_SELECT_INPUT_15;            /**< Select Input Register, offset: 0x820 */
16149   __IO  uint32_t SPDIF_SPDIF_IN1_SELECT_INPUT;           /**< Select Input Register, offset: 0x824 */
16150   __IO  uint32_t SPDIF_TX_CLK2_SELECT_INPUT;             /**< Select Input Register, offset: 0x828 */
16151   __IO  uint32_t UART1_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x82C */
16152   __IO  uint32_t UART1_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x830 */
16153   __IO  uint32_t UART2_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x834 */
16154   __IO  uint32_t UART2_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x838 */
16155   __IO  uint32_t UART3_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x83C */
16156   __IO  uint32_t UART3_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x840 */
16157   __IO  uint32_t UART4_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x844 */
16158   __IO  uint32_t UART4_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x848 */
16159   __IO  uint32_t UART5_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x84C */
16160   __IO  uint32_t UART5_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x850 */
16161   __IO  uint32_t UART6_IPP_UART_RTS_B_SELECT_INPUT;      /**< Select Input Register, offset: 0x854 */
16162   __IO  uint32_t UART6_IPP_UART_RXD_MUX_SELECT_INPUT;    /**< Select Input Register, offset: 0x858 */
16163   __IO  uint32_t USB_IPP_IND_OTG2_OC_SELECT_INPUT;       /**< Select Input Register, offset: 0x85C */
16164   __IO  uint32_t USB_IPP_IND_OTG_OC_SELECT_INPUT;        /**< Select Input Register, offset: 0x860 */
16165   __IO  uint32_t USDHC1_IPP_CARD_DET_SELECT_INPUT;       /**< Select Input Register, offset: 0x864 */
16166   __IO  uint32_t USDHC1_IPP_WP_ON_SELECT_INPUT;          /**< Select Input Register, offset: 0x868 */
16167   __IO  uint32_t USDHC2_IPP_CARD_DET_SELECT_INPUT;       /**< Select Input Register, offset: 0x86C */
16168   __IO  uint32_t USDHC2_IPP_WP_ON_SELECT_INPUT;          /**< Select Input Register, offset: 0x870 */
16169   __IO  uint32_t USDHC4_IPP_CARD_DET_SELECT_INPUT;       /**< Select Input Register, offset: 0x874 */
16170   __IO  uint32_t USDHC4_IPP_WP_ON_SELECT_INPUT;          /**< Select Input Register, offset: 0x878 */
16171 } IOMUXC_Type, *IOMUXC_MemMapPtr;
16172 
16173 /* ----------------------------------------------------------------------------
16174    -- IOMUXC - Register accessor macros
16175    ---------------------------------------------------------------------------- */
16176 
16177 /*!
16178  * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros
16179  * @{
16180  */
16181 
16182 /* IOMUXC - Register accessors */
16183 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO00)
16184 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01)
16185 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02)
16186 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03)
16187 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04)
16188 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05)
16189 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06)
16190 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07)
16191 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08)
16192 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09)
16193 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10)
16194 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11)
16195 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12)
16196 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13)
16197 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA00)
16198 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA01)
16199 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA02)
16200 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA03)
16201 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA04)
16202 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA05)
16203 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA06)
16204 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA07)
16205 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_HSYNC)
16206 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_MCLK)
16207 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_PIXCLK)
16208 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_VSYNC)
16209 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL)
16210 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS)
16211 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDC)
16212 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDIO)
16213 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK)
16214 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK)
16215 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_COL)
16216 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_CRS)
16217 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_RX_CLK)
16218 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_TX_CLK)
16219 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL0)
16220 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL1)
16221 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL2)
16222 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL3)
16223 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL4)
16224 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW0)
16225 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW1)
16226 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW2)
16227 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW3)
16228 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW4)
16229 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_CLK)
16230 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA00)
16231 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA01)
16232 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA02)
16233 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA03)
16234 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA04)
16235 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA05)
16236 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA06)
16237 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA07)
16238 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA08)
16239 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA09)
16240 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA10)
16241 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA11)
16242 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA12)
16243 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA13)
16244 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA14)
16245 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA15)
16246 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA16)
16247 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA17)
16248 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA18)
16249 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA19)
16250 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA20)
16251 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA21)
16252 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA22)
16253 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA23)
16254 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_ENABLE)
16255 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_HSYNC)
16256 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_RESET)
16257 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_VSYNC)
16258 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_ALE)
16259 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE0_B)
16260 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE1_B)
16261 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CLE)
16262 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA00)
16263 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA01)
16264 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA02)
16265 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA03)
16266 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA04)
16267 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA05)
16268 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA06)
16269 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA07)
16270 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_RE_B)
16271 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_READY_B)
16272 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WE_B)
16273 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WP_B)
16274 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA0)
16275 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA1)
16276 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA2)
16277 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA3)
16278 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DQS)
16279 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SCLK)
16280 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS0_B)
16281 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS1_B)
16282 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA0)
16283 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA1)
16284 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA2)
16285 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA3)
16286 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DQS)
16287 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SCLK)
16288 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS0_B)
16289 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS1_B)
16290 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD0)
16291 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD1)
16292 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD2)
16293 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD3)
16294 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RX_CTL)
16295 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RXC)
16296 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD0)
16297 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD1)
16298 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD2)
16299 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD3)
16300 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TX_CTL)
16301 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TXC)
16302 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD0)
16303 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD1)
16304 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD2)
16305 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD3)
16306 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RX_CTL)
16307 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RXC)
16308 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD0)
16309 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD1)
16310 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD2)
16311 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD3)
16312 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TX_CTL)
16313 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TXC)
16314 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD1_CLK)
16315 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD1_CMD)
16316 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0)
16317 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1)
16318 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2)
16319 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3)
16320 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD2_CLK)
16321 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD2_CMD)
16322 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0)
16323 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1)
16324 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2)
16325 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3)
16326 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD3_CLK)
16327 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD3_CMD)
16328 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0)
16329 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1)
16330 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2)
16331 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3)
16332 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4)
16333 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5)
16334 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6)
16335 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7)
16336 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(base)  ((base)->SW_MUX_CTL_PAD_SD4_CLK)
16337 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(base)  ((base)->SW_MUX_CTL_PAD_SD4_CMD)
16338 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA0)
16339 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA1)
16340 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA2)
16341 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA3)
16342 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA4)
16343 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA5)
16344 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA6)
16345 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA7)
16346 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_RESET_B)
16347 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_DATA)
16348 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_STROBE)
16349 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR00)
16350 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR01)
16351 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR02)
16352 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR03)
16353 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR04)
16354 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05)
16355 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR06)
16356 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR07)
16357 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR08)
16358 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR09)
16359 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR10)
16360 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR11)
16361 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR12)
16362 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR13)
16363 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR14)
16364 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR15)
16365 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM0)
16366 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM1)
16367 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2)
16368 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM3)
16369 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RAS_B)
16370 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CAS_B)
16371 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS0_B)
16372 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS1_B)
16373 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDWE_B)
16374 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT0)
16375 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT1)
16376 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA0)
16377 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1)
16378 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA2)
16379 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE0)
16380 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE1)
16381 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCLK0_P)
16382 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS0_P)
16383 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS1_P)
16384 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS2_P)
16385 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P)
16386 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RESET)
16387 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD)
16388 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK)
16389 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI)
16390 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO)
16391 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS)
16392 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B)
16393 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00)
16394 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01)
16395 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02)
16396 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03)
16397 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04)
16398 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05)
16399 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06)
16400 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07)
16401 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08)
16402 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09)
16403 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10)
16404 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11)
16405 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12)
16406 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13)
16407 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA00)
16408 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA01)
16409 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA02)
16410 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA03)
16411 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA04)
16412 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA05)
16413 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA06)
16414 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA07)
16415 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_HSYNC)
16416 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_MCLK)
16417 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_PIXCLK)
16418 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_VSYNC)
16419 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL)
16420 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS)
16421 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDC)
16422 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDIO)
16423 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK)
16424 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK)
16425 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_COL)
16426 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_CRS)
16427 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_RX_CLK)
16428 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_TX_CLK)
16429 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL0)
16430 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL1)
16431 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL2)
16432 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL3)
16433 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL4)
16434 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW0)
16435 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW1)
16436 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW2)
16437 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW3)
16438 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW4)
16439 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_CLK)
16440 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA00)
16441 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA01)
16442 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA02)
16443 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA03)
16444 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA04)
16445 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA05)
16446 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA06)
16447 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA07)
16448 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA08)
16449 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA09)
16450 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA10)
16451 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA11)
16452 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA12)
16453 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA13)
16454 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA14)
16455 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA15)
16456 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA16)
16457 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA17)
16458 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA18)
16459 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA19)
16460 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA20)
16461 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA21)
16462 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA22)
16463 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA23)
16464 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_ENABLE)
16465 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_HSYNC)
16466 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_RESET)
16467 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_VSYNC)
16468 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_ALE)
16469 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE0_B)
16470 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE1_B)
16471 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CLE)
16472 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA00)
16473 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA01)
16474 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA02)
16475 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA03)
16476 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA04)
16477 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA05)
16478 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA06)
16479 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA07)
16480 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_RE_B)
16481 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_READY_B)
16482 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WE_B)
16483 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WP_B)
16484 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA0)
16485 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA1)
16486 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA2)
16487 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA3)
16488 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DQS)
16489 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SCLK)
16490 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS0_B)
16491 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS1_B)
16492 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA0)
16493 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA1)
16494 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA2)
16495 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA3)
16496 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DQS)
16497 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SCLK)
16498 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS0_B)
16499 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS1_B)
16500 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD0)
16501 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD1)
16502 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD2)
16503 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD3)
16504 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RX_CTL)
16505 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RXC)
16506 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD0)
16507 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD1)
16508 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD2)
16509 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD3)
16510 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TX_CTL)
16511 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TXC)
16512 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD0)
16513 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD1)
16514 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD2)
16515 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD3)
16516 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RX_CTL)
16517 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RXC)
16518 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD0)
16519 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD1)
16520 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD2)
16521 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD3)
16522 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TX_CTL)
16523 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TXC)
16524 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD1_CLK)
16525 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD1_CMD)
16526 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0)
16527 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1)
16528 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2)
16529 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3)
16530 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD2_CLK)
16531 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD2_CMD)
16532 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0)
16533 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1)
16534 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2)
16535 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3)
16536 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD3_CLK)
16537 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD3_CMD)
16538 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0)
16539 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1)
16540 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2)
16541 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3)
16542 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4)
16543 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5)
16544 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6)
16545 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7)
16546 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(base)  ((base)->SW_PAD_CTL_PAD_SD4_CLK)
16547 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(base)  ((base)->SW_PAD_CTL_PAD_SD4_CMD)
16548 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA0)
16549 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA1)
16550 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA2)
16551 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA3)
16552 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA4)
16553 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA5)
16554 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA6)
16555 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA7)
16556 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_RESET_B)
16557 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_DATA)
16558 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_STROBE)
16559 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(base)    ((base)->SW_PAD_CTL_GRP_ADDDS)
16560 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE_CTL)
16561 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(base)   ((base)->SW_PAD_CTL_GRP_DDRPKE)
16562 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(base)    ((base)->SW_PAD_CTL_GRP_DDRPK)
16563 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(base)   ((base)->SW_PAD_CTL_GRP_DDRHYS)
16564 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(base)  ((base)->SW_PAD_CTL_GRP_DDRMODE)
16565 #define IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(base)     ((base)->SW_PAD_CTL_GRP_B0DS)
16566 #define IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(base)     ((base)->SW_PAD_CTL_GRP_B1DS)
16567 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(base)    ((base)->SW_PAD_CTL_GRP_CTLDS)
16568 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(base) ((base)->SW_PAD_CTL_GRP_DDR_TYPE)
16569 #define IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(base)     ((base)->SW_PAD_CTL_GRP_B2DS)
16570 #define IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(base)     ((base)->SW_PAD_CTL_GRP_B3DS)
16571 #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_OTG_ID_SELECT_INPUT)
16572 #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_UH1_ID_SELECT_INPUT)
16573 #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT)
16574 #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT)
16575 #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT)
16576 #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT)
16577 #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT)
16578 #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT)
16579 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT)
16580 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT)
16581 #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT)
16582 #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT)
16583 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT)
16584 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT)
16585 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT)
16586 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT)
16587 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT)
16588 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT)
16589 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT)
16590 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT)
16591 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT)
16592 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT)
16593 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT)
16594 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT)
16595 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT)
16596 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT)
16597 #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN1_IPP_IND_CANRX_SELECT_INPUT)
16598 #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN2_IPP_IND_CANRX_SELECT_INPUT)
16599 #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT)
16600 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_0)
16601 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_1)
16602 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_2)
16603 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_3)
16604 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_4)
16605 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_5)
16606 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_6)
16607 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_7)
16608 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_8)
16609 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_9)
16610 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_11)
16611 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_12)
16612 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_13)
16613 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_14)
16614 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_15)
16615 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_16)
16616 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_17)
16617 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_18)
16618 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_19)
16619 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_20)
16620 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_21)
16621 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_22)
16622 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_23)
16623 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_10)
16624 #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_HSYNC_SELECT_INPUT)
16625 #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_PIXCLK_SELECT_INPUT)
16626 #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_VSYNC_SELECT_INPUT)
16627 #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(base) ((base)->CSI1_TVDECODER_IN_FIELD_SELECT_INPUT)
16628 #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT)
16629 #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MISO_SELECT_INPUT)
16630 #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MOSI_SELECT_INPUT)
16631 #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0)
16632 #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT)
16633 #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MISO_SELECT_INPUT)
16634 #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MOSI_SELECT_INPUT)
16635 #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0)
16636 #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT)
16637 #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MISO_SELECT_INPUT)
16638 #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MOSI_SELECT_INPUT)
16639 #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0)
16640 #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT)
16641 #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MISO_SELECT_INPUT)
16642 #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MOSI_SELECT_INPUT)
16643 #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0)
16644 #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT)
16645 #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MISO_SELECT_INPUT)
16646 #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MOSI_SELECT_INPUT)
16647 #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0)
16648 #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET1_IPG_CLK_RMII_SELECT_INPUT)
16649 #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT)
16650 #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT)
16651 #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET2_IPG_CLK_RMII_SELECT_INPUT)
16652 #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT)
16653 #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT)
16654 #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FSR_SELECT_INPUT)
16655 #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FST_SELECT_INPUT)
16656 #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKR_SELECT_INPUT)
16657 #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKT_SELECT_INPUT)
16658 #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKR_SELECT_INPUT)
16659 #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKT_SELECT_INPUT)
16660 #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO0_SELECT_INPUT)
16661 #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO1_SELECT_INPUT)
16662 #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT)
16663 #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT)
16664 #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT)
16665 #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT)
16666 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SCL_IN_SELECT_INPUT)
16667 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SDA_IN_SELECT_INPUT)
16668 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SCL_IN_SELECT_INPUT)
16669 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SDA_IN_SELECT_INPUT)
16670 #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SCL_IN_SELECT_INPUT)
16671 #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SDA_IN_SELECT_INPUT)
16672 #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SCL_IN_SELECT_INPUT)
16673 #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SDA_IN_SELECT_INPUT)
16674 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_5)
16675 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_6)
16676 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_7)
16677 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_5)
16678 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_6)
16679 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_7)
16680 #define IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(base)  ((base)->LCD1_BUSY_SELECT_INPUT)
16681 #define IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(base)  ((base)->LCD2_BUSY_SELECT_INPUT)
16682 #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_CLK_IN_SELECT_INPUT)
16683 #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_DATA_IN_SELECT_INPUT)
16684 #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_SIG_IN_SELECT_INPUT)
16685 #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT)
16686 #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0)
16687 #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT)
16688 #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT)
16689 #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
16690 #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT)
16691 #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0)
16692 #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT)
16693 #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT)
16694 #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
16695 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_14)
16696 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_15)
16697 #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(base) ((base)->SPDIF_SPDIF_IN1_SELECT_INPUT)
16698 #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(base) ((base)->SPDIF_TX_CLK2_SELECT_INPUT)
16699 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RTS_B_SELECT_INPUT)
16700 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RXD_MUX_SELECT_INPUT)
16701 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RTS_B_SELECT_INPUT)
16702 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RXD_MUX_SELECT_INPUT)
16703 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RTS_B_SELECT_INPUT)
16704 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RXD_MUX_SELECT_INPUT)
16705 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RTS_B_SELECT_INPUT)
16706 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RXD_MUX_SELECT_INPUT)
16707 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RTS_B_SELECT_INPUT)
16708 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RXD_MUX_SELECT_INPUT)
16709 #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RTS_B_SELECT_INPUT)
16710 #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RXD_MUX_SELECT_INPUT)
16711 #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG2_OC_SELECT_INPUT)
16712 #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG_OC_SELECT_INPUT)
16713 #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_CARD_DET_SELECT_INPUT)
16714 #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_WP_ON_SELECT_INPUT)
16715 #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_CARD_DET_SELECT_INPUT)
16716 #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_WP_ON_SELECT_INPUT)
16717 #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_CARD_DET_SELECT_INPUT)
16718 #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_WP_ON_SELECT_INPUT)
16719 
16720 /*!
16721  * @}
16722  */ /* end of group IOMUXC_Register_Accessor_Macros */
16723 
16724 /* ----------------------------------------------------------------------------
16725    -- IOMUXC Register Masks
16726    ---------------------------------------------------------------------------- */
16727 
16728 /*!
16729  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
16730  * @{
16731  */
16732 
16733 /* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */
16734 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u
16735 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0
16736 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK)
16737 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_SION_MASK 0x10u
16738 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_SION_SHIFT 4
16739 /* SW_MUX_CTL_PAD_GPIO1_IO01 Bit Fields */
16740 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK 0x7u
16741 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT 0
16742 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK)
16743 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_SION_MASK 0x10u
16744 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_SION_SHIFT 4
16745 /* SW_MUX_CTL_PAD_GPIO1_IO02 Bit Fields */
16746 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK 0x7u
16747 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT 0
16748 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK)
16749 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK 0x10u
16750 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_SHIFT 4
16751 /* SW_MUX_CTL_PAD_GPIO1_IO03 Bit Fields */
16752 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK 0x7u
16753 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT 0
16754 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK)
16755 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK 0x10u
16756 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_SHIFT 4
16757 /* SW_MUX_CTL_PAD_GPIO1_IO04 Bit Fields */
16758 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK 0x7u
16759 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT 0
16760 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK)
16761 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_SION_MASK 0x10u
16762 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_SION_SHIFT 4
16763 /* SW_MUX_CTL_PAD_GPIO1_IO05 Bit Fields */
16764 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK 0x7u
16765 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT 0
16766 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK)
16767 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_SION_MASK 0x10u
16768 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_SION_SHIFT 4
16769 /* SW_MUX_CTL_PAD_GPIO1_IO06 Bit Fields */
16770 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK 0x7u
16771 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT 0
16772 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK)
16773 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_SION_MASK 0x10u
16774 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_SION_SHIFT 4
16775 /* SW_MUX_CTL_PAD_GPIO1_IO07 Bit Fields */
16776 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK 0x7u
16777 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT 0
16778 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK)
16779 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_SION_MASK 0x10u
16780 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_SION_SHIFT 4
16781 /* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */
16782 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u
16783 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0
16784 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK)
16785 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_MASK 0x10u
16786 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_SHIFT 4
16787 /* SW_MUX_CTL_PAD_GPIO1_IO09 Bit Fields */
16788 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK 0x7u
16789 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT 0
16790 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK)
16791 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_MASK 0x10u
16792 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_SHIFT 4
16793 /* SW_MUX_CTL_PAD_GPIO1_IO10 Bit Fields */
16794 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK 0x7u
16795 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT 0
16796 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK)
16797 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_MASK 0x10u
16798 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_SHIFT 4
16799 /* SW_MUX_CTL_PAD_GPIO1_IO11 Bit Fields */
16800 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK 0x7u
16801 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT 0
16802 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK)
16803 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_MASK 0x10u
16804 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_SHIFT 4
16805 /* SW_MUX_CTL_PAD_GPIO1_IO12 Bit Fields */
16806 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK 0x7u
16807 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT 0
16808 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK)
16809 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_MASK 0x10u
16810 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_SHIFT 4
16811 /* SW_MUX_CTL_PAD_GPIO1_IO13 Bit Fields */
16812 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK 0x7u
16813 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT 0
16814 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK)
16815 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_MASK 0x10u
16816 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_SHIFT 4
16817 /* SW_MUX_CTL_PAD_CSI_DATA00 Bit Fields */
16818 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_MASK 0x7u
16819 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_SHIFT 0
16820 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_MASK)
16821 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_SION_MASK 0x10u
16822 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_SION_SHIFT 4
16823 /* SW_MUX_CTL_PAD_CSI_DATA01 Bit Fields */
16824 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_MASK 0x7u
16825 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_SHIFT 0
16826 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_MASK)
16827 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_SION_MASK 0x10u
16828 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_SION_SHIFT 4
16829 /* SW_MUX_CTL_PAD_CSI_DATA02 Bit Fields */
16830 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_MASK 0x7u
16831 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_SHIFT 0
16832 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_MASK)
16833 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_SION_MASK 0x10u
16834 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_SION_SHIFT 4
16835 /* SW_MUX_CTL_PAD_CSI_DATA03 Bit Fields */
16836 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_MASK 0x7u
16837 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_SHIFT 0
16838 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_MASK)
16839 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_SION_MASK 0x10u
16840 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_SION_SHIFT 4
16841 /* SW_MUX_CTL_PAD_CSI_DATA04 Bit Fields */
16842 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_MASK 0x7u
16843 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_SHIFT 0
16844 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_MASK)
16845 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_SION_MASK 0x10u
16846 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_SION_SHIFT 4
16847 /* SW_MUX_CTL_PAD_CSI_DATA05 Bit Fields */
16848 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_MASK 0x7u
16849 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_SHIFT 0
16850 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_MASK)
16851 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_SION_MASK 0x10u
16852 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_SION_SHIFT 4
16853 /* SW_MUX_CTL_PAD_CSI_DATA06 Bit Fields */
16854 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_MASK 0x7u
16855 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_SHIFT 0
16856 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_MASK)
16857 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SION_MASK 0x10u
16858 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SION_SHIFT 4
16859 /* SW_MUX_CTL_PAD_CSI_DATA07 Bit Fields */
16860 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_MASK 0x7u
16861 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_SHIFT 0
16862 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_MASK)
16863 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SION_MASK 0x10u
16864 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SION_SHIFT 4
16865 /* SW_MUX_CTL_PAD_CSI_HSYNC Bit Fields */
16866 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_MASK 0x7u
16867 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_SHIFT 0
16868 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_MASK)
16869 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_SION_MASK 0x10u
16870 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_SION_SHIFT 4
16871 /* SW_MUX_CTL_PAD_CSI_MCLK Bit Fields */
16872 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_MASK 0x7u
16873 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_SHIFT 0
16874 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_MASK)
16875 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_SION_MASK 0x10u
16876 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_SION_SHIFT 4
16877 /* SW_MUX_CTL_PAD_CSI_PIXCLK Bit Fields */
16878 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_MASK 0x7u
16879 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_SHIFT 0
16880 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_MASK)
16881 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_SION_MASK 0x10u
16882 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_SION_SHIFT 4
16883 /* SW_MUX_CTL_PAD_CSI_VSYNC Bit Fields */
16884 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_MASK 0x7u
16885 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_SHIFT 0
16886 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_MASK)
16887 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_SION_MASK 0x10u
16888 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_SION_SHIFT 4
16889 /* SW_MUX_CTL_PAD_ENET1_COL Bit Fields */
16890 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK 0x7u
16891 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT 0
16892 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK)
16893 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_MASK 0x10u
16894 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_SHIFT 4
16895 /* SW_MUX_CTL_PAD_ENET1_CRS Bit Fields */
16896 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK 0x7u
16897 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT 0
16898 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK)
16899 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_MASK 0x10u
16900 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_SHIFT 4
16901 /* SW_MUX_CTL_PAD_ENET1_MDC Bit Fields */
16902 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_MASK 0x7u
16903 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_SHIFT 0
16904 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_MASK)
16905 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_SION_MASK 0x10u
16906 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_SION_SHIFT 4
16907 /* SW_MUX_CTL_PAD_ENET1_MDIO Bit Fields */
16908 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_MASK 0x7u
16909 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_SHIFT 0
16910 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_MASK)
16911 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_SION_MASK 0x10u
16912 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_SION_SHIFT 4
16913 /* SW_MUX_CTL_PAD_ENET1_RX_CLK Bit Fields */
16914 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK 0x7u
16915 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT 0
16916 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK)
16917 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_MASK 0x10u
16918 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_SHIFT 4
16919 /* SW_MUX_CTL_PAD_ENET1_TX_CLK Bit Fields */
16920 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK 0x7u
16921 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT 0
16922 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK)
16923 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_MASK 0x10u
16924 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_SHIFT 4
16925 /* SW_MUX_CTL_PAD_ENET2_COL Bit Fields */
16926 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_MASK 0x7u
16927 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_SHIFT 0
16928 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_MASK)
16929 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_SION_MASK 0x10u
16930 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_SION_SHIFT 4
16931 /* SW_MUX_CTL_PAD_ENET2_CRS Bit Fields */
16932 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_MASK 0x7u
16933 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_SHIFT 0
16934 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_MASK)
16935 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_SION_MASK 0x10u
16936 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_SION_SHIFT 4
16937 /* SW_MUX_CTL_PAD_ENET2_RX_CLK Bit Fields */
16938 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_MASK 0x7u
16939 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_SHIFT 0
16940 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_MASK)
16941 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_SION_MASK 0x10u
16942 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_SION_SHIFT 4
16943 /* SW_MUX_CTL_PAD_ENET2_TX_CLK Bit Fields */
16944 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_MASK 0x7u
16945 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_SHIFT 0
16946 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_MASK)
16947 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_SION_MASK 0x10u
16948 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_SION_SHIFT 4
16949 /* SW_MUX_CTL_PAD_KEY_COL0 Bit Fields */
16950 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_MASK 0x7u
16951 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_SHIFT 0
16952 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_MASK)
16953 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_MASK 0x10u
16954 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_SHIFT 4
16955 /* SW_MUX_CTL_PAD_KEY_COL1 Bit Fields */
16956 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_MASK 0x7u
16957 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_SHIFT 0
16958 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_MASK)
16959 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_MASK 0x10u
16960 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_SHIFT 4
16961 /* SW_MUX_CTL_PAD_KEY_COL2 Bit Fields */
16962 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_MASK 0x7u
16963 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_SHIFT 0
16964 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_MASK)
16965 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_MASK 0x10u
16966 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_SHIFT 4
16967 /* SW_MUX_CTL_PAD_KEY_COL3 Bit Fields */
16968 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_MASK 0x7u
16969 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_SHIFT 0
16970 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_MASK)
16971 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_MASK 0x10u
16972 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_SHIFT 4
16973 /* SW_MUX_CTL_PAD_KEY_COL4 Bit Fields */
16974 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_MASK 0x7u
16975 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_SHIFT 0
16976 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_MASK)
16977 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_MASK 0x10u
16978 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_SHIFT 4
16979 /* SW_MUX_CTL_PAD_KEY_ROW0 Bit Fields */
16980 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_MASK 0x7u
16981 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_SHIFT 0
16982 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_MASK)
16983 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_MASK 0x10u
16984 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_SHIFT 4
16985 /* SW_MUX_CTL_PAD_KEY_ROW1 Bit Fields */
16986 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_MASK 0x7u
16987 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_SHIFT 0
16988 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_MASK)
16989 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_MASK 0x10u
16990 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_SHIFT 4
16991 /* SW_MUX_CTL_PAD_KEY_ROW2 Bit Fields */
16992 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_MASK 0x7u
16993 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_SHIFT 0
16994 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_MASK)
16995 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_MASK 0x10u
16996 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_SHIFT 4
16997 /* SW_MUX_CTL_PAD_KEY_ROW3 Bit Fields */
16998 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_MASK 0x7u
16999 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_SHIFT 0
17000 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_MASK)
17001 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_MASK 0x10u
17002 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_SHIFT 4
17003 /* SW_MUX_CTL_PAD_KEY_ROW4 Bit Fields */
17004 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_MASK 0x7u
17005 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_SHIFT 0
17006 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_MASK)
17007 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_MASK 0x10u
17008 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_SHIFT 4
17009 /* SW_MUX_CTL_PAD_LCD1_CLK Bit Fields */
17010 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_MASK 0x7u
17011 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_SHIFT 0
17012 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_MASK)
17013 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_SION_MASK 0x10u
17014 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_SION_SHIFT 4
17015 /* SW_MUX_CTL_PAD_LCD1_DATA00 Bit Fields */
17016 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_MASK 0x7u
17017 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_SHIFT 0
17018 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_MASK)
17019 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_SION_MASK 0x10u
17020 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_SION_SHIFT 4
17021 /* SW_MUX_CTL_PAD_LCD1_DATA01 Bit Fields */
17022 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_MASK 0x7u
17023 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_SHIFT 0
17024 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_MASK)
17025 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_SION_MASK 0x10u
17026 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_SION_SHIFT 4
17027 /* SW_MUX_CTL_PAD_LCD1_DATA02 Bit Fields */
17028 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_MASK 0x7u
17029 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_SHIFT 0
17030 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_MASK)
17031 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_SION_MASK 0x10u
17032 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_SION_SHIFT 4
17033 /* SW_MUX_CTL_PAD_LCD1_DATA03 Bit Fields */
17034 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_MASK 0x7u
17035 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_SHIFT 0
17036 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_MASK)
17037 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_SION_MASK 0x10u
17038 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_SION_SHIFT 4
17039 /* SW_MUX_CTL_PAD_LCD1_DATA04 Bit Fields */
17040 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_MASK 0x7u
17041 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_SHIFT 0
17042 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_MASK)
17043 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_SION_MASK 0x10u
17044 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_SION_SHIFT 4
17045 /* SW_MUX_CTL_PAD_LCD1_DATA05 Bit Fields */
17046 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_MASK 0x7u
17047 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_SHIFT 0
17048 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_MASK)
17049 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_SION_MASK 0x10u
17050 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_SION_SHIFT 4
17051 /* SW_MUX_CTL_PAD_LCD1_DATA06 Bit Fields */
17052 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_MASK 0x7u
17053 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_SHIFT 0
17054 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_MASK)
17055 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_SION_MASK 0x10u
17056 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_SION_SHIFT 4
17057 /* SW_MUX_CTL_PAD_LCD1_DATA07 Bit Fields */
17058 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_MASK 0x7u
17059 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_SHIFT 0
17060 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_MASK)
17061 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_SION_MASK 0x10u
17062 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_SION_SHIFT 4
17063 /* SW_MUX_CTL_PAD_LCD1_DATA08 Bit Fields */
17064 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_MASK 0x7u
17065 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_SHIFT 0
17066 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_MASK)
17067 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_SION_MASK 0x10u
17068 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_SION_SHIFT 4
17069 /* SW_MUX_CTL_PAD_LCD1_DATA09 Bit Fields */
17070 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_MASK 0x7u
17071 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_SHIFT 0
17072 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_MASK)
17073 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_SION_MASK 0x10u
17074 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_SION_SHIFT 4
17075 /* SW_MUX_CTL_PAD_LCD1_DATA10 Bit Fields */
17076 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_MASK 0x7u
17077 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_SHIFT 0
17078 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_MASK)
17079 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_SION_MASK 0x10u
17080 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_SION_SHIFT 4
17081 /* SW_MUX_CTL_PAD_LCD1_DATA11 Bit Fields */
17082 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_MASK 0x7u
17083 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_SHIFT 0
17084 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_MASK)
17085 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_SION_MASK 0x10u
17086 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_SION_SHIFT 4
17087 /* SW_MUX_CTL_PAD_LCD1_DATA12 Bit Fields */
17088 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_MASK 0x7u
17089 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_SHIFT 0
17090 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_MASK)
17091 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_SION_MASK 0x10u
17092 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_SION_SHIFT 4
17093 /* SW_MUX_CTL_PAD_LCD1_DATA13 Bit Fields */
17094 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_MASK 0x7u
17095 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_SHIFT 0
17096 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_MASK)
17097 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_SION_MASK 0x10u
17098 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_SION_SHIFT 4
17099 /* SW_MUX_CTL_PAD_LCD1_DATA14 Bit Fields */
17100 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_MASK 0x7u
17101 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_SHIFT 0
17102 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_MASK)
17103 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_SION_MASK 0x10u
17104 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_SION_SHIFT 4
17105 /* SW_MUX_CTL_PAD_LCD1_DATA15 Bit Fields */
17106 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_MASK 0x7u
17107 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_SHIFT 0
17108 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_MASK)
17109 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_SION_MASK 0x10u
17110 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_SION_SHIFT 4
17111 /* SW_MUX_CTL_PAD_LCD1_DATA16 Bit Fields */
17112 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_MASK 0x7u
17113 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_SHIFT 0
17114 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_MASK)
17115 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_SION_MASK 0x10u
17116 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_SION_SHIFT 4
17117 /* SW_MUX_CTL_PAD_LCD1_DATA17 Bit Fields */
17118 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_MASK 0x7u
17119 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_SHIFT 0
17120 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_MASK)
17121 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_SION_MASK 0x10u
17122 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_SION_SHIFT 4
17123 /* SW_MUX_CTL_PAD_LCD1_DATA18 Bit Fields */
17124 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_MASK 0x7u
17125 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_SHIFT 0
17126 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_MASK)
17127 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_SION_MASK 0x10u
17128 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_SION_SHIFT 4
17129 /* SW_MUX_CTL_PAD_LCD1_DATA19 Bit Fields */
17130 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_MASK 0x7u
17131 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_SHIFT 0
17132 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_MASK)
17133 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_SION_MASK 0x10u
17134 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_SION_SHIFT 4
17135 /* SW_MUX_CTL_PAD_LCD1_DATA20 Bit Fields */
17136 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_MASK 0x7u
17137 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_SHIFT 0
17138 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_MASK)
17139 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_SION_MASK 0x10u
17140 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_SION_SHIFT 4
17141 /* SW_MUX_CTL_PAD_LCD1_DATA21 Bit Fields */
17142 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_MASK 0x7u
17143 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_SHIFT 0
17144 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_MASK)
17145 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_SION_MASK 0x10u
17146 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_SION_SHIFT 4
17147 /* SW_MUX_CTL_PAD_LCD1_DATA22 Bit Fields */
17148 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_MASK 0x7u
17149 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_SHIFT 0
17150 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_MASK)
17151 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_SION_MASK 0x10u
17152 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_SION_SHIFT 4
17153 /* SW_MUX_CTL_PAD_LCD1_DATA23 Bit Fields */
17154 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_MASK 0x7u
17155 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_SHIFT 0
17156 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_MASK)
17157 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_SION_MASK 0x10u
17158 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_SION_SHIFT 4
17159 /* SW_MUX_CTL_PAD_LCD1_ENABLE Bit Fields */
17160 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_MASK 0x7u
17161 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_SHIFT 0
17162 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_MASK)
17163 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_SION_MASK 0x10u
17164 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_SION_SHIFT 4
17165 /* SW_MUX_CTL_PAD_LCD1_HSYNC Bit Fields */
17166 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_MASK 0x7u
17167 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_SHIFT 0
17168 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_MASK)
17169 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_SION_MASK 0x10u
17170 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_SION_SHIFT 4
17171 /* SW_MUX_CTL_PAD_LCD1_RESET Bit Fields */
17172 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_MASK 0x7u
17173 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_SHIFT 0
17174 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_MASK)
17175 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_SION_MASK 0x10u
17176 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_SION_SHIFT 4
17177 /* SW_MUX_CTL_PAD_LCD1_VSYNC Bit Fields */
17178 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_MASK 0x7u
17179 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_SHIFT 0
17180 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_MASK)
17181 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_SION_MASK 0x10u
17182 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_SION_SHIFT 4
17183 /* SW_MUX_CTL_PAD_NAND_ALE Bit Fields */
17184 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_MASK 0x7u
17185 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_SHIFT 0
17186 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_MASK)
17187 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_MASK 0x10u
17188 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_SHIFT 4
17189 /* SW_MUX_CTL_PAD_NAND_CE0_B Bit Fields */
17190 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_MASK 0x7u
17191 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_SHIFT 0
17192 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_MASK)
17193 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_SION_MASK 0x10u
17194 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_SION_SHIFT 4
17195 /* SW_MUX_CTL_PAD_NAND_CE1_B Bit Fields */
17196 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_MASK 0x7u
17197 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_SHIFT 0
17198 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_MASK)
17199 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_SION_MASK 0x10u
17200 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_SION_SHIFT 4
17201 /* SW_MUX_CTL_PAD_NAND_CLE Bit Fields */
17202 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_MASK 0x7u
17203 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_SHIFT 0
17204 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_MASK)
17205 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_MASK 0x10u
17206 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_SHIFT 4
17207 /* SW_MUX_CTL_PAD_NAND_DATA00 Bit Fields */
17208 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_MASK 0x7u
17209 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_SHIFT 0
17210 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_MASK)
17211 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_MASK 0x10u
17212 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_SHIFT 4
17213 /* SW_MUX_CTL_PAD_NAND_DATA01 Bit Fields */
17214 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_MASK 0x7u
17215 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_SHIFT 0
17216 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_MASK)
17217 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_MASK 0x10u
17218 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_SHIFT 4
17219 /* SW_MUX_CTL_PAD_NAND_DATA02 Bit Fields */
17220 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_MASK 0x7u
17221 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_SHIFT 0
17222 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_MASK)
17223 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_MASK 0x10u
17224 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_SHIFT 4
17225 /* SW_MUX_CTL_PAD_NAND_DATA03 Bit Fields */
17226 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_MASK 0x7u
17227 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_SHIFT 0
17228 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_MASK)
17229 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_MASK 0x10u
17230 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_SHIFT 4
17231 /* SW_MUX_CTL_PAD_NAND_DATA04 Bit Fields */
17232 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_MASK 0x7u
17233 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_SHIFT 0
17234 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_MASK)
17235 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_MASK 0x10u
17236 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_SHIFT 4
17237 /* SW_MUX_CTL_PAD_NAND_DATA05 Bit Fields */
17238 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_MASK 0x7u
17239 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_SHIFT 0
17240 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_MASK)
17241 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_MASK 0x10u
17242 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_SHIFT 4
17243 /* SW_MUX_CTL_PAD_NAND_DATA06 Bit Fields */
17244 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_MASK 0x7u
17245 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_SHIFT 0
17246 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_MASK)
17247 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_MASK 0x10u
17248 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_SHIFT 4
17249 /* SW_MUX_CTL_PAD_NAND_DATA07 Bit Fields */
17250 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_MASK 0x7u
17251 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_SHIFT 0
17252 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_MASK)
17253 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_MASK 0x10u
17254 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_SHIFT 4
17255 /* SW_MUX_CTL_PAD_NAND_RE_B Bit Fields */
17256 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_MASK 0x7u
17257 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_SHIFT 0
17258 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_MASK)
17259 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_SION_MASK 0x10u
17260 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_SION_SHIFT 4
17261 /* SW_MUX_CTL_PAD_NAND_READY_B Bit Fields */
17262 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_MASK 0x7u
17263 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_SHIFT 0
17264 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_MASK)
17265 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_SION_MASK 0x10u
17266 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_SION_SHIFT 4
17267 /* SW_MUX_CTL_PAD_NAND_WE_B Bit Fields */
17268 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_MASK 0x7u
17269 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_SHIFT 0
17270 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_MASK)
17271 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_SION_MASK 0x10u
17272 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_SION_SHIFT 4
17273 /* SW_MUX_CTL_PAD_NAND_WP_B Bit Fields */
17274 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_MASK 0x7u
17275 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_SHIFT 0
17276 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_MASK)
17277 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_MASK 0x10u
17278 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_SHIFT 4
17279 /* SW_MUX_CTL_PAD_QSPI1A_DATA0 Bit Fields */
17280 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_MASK 0x7u
17281 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_SHIFT 0
17282 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_MASK)
17283 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_SION_MASK 0x10u
17284 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_SION_SHIFT 4
17285 /* SW_MUX_CTL_PAD_QSPI1A_DATA1 Bit Fields */
17286 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_MASK 0x7u
17287 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_SHIFT 0
17288 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_MASK)
17289 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_SION_MASK 0x10u
17290 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_SION_SHIFT 4
17291 /* SW_MUX_CTL_PAD_QSPI1A_DATA2 Bit Fields */
17292 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_MASK 0x7u
17293 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_SHIFT 0
17294 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_MASK)
17295 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_SION_MASK 0x10u
17296 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_SION_SHIFT 4
17297 /* SW_MUX_CTL_PAD_QSPI1A_DATA3 Bit Fields */
17298 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_MASK 0x7u
17299 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_SHIFT 0
17300 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_MASK)
17301 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_SION_MASK 0x10u
17302 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_SION_SHIFT 4
17303 /* SW_MUX_CTL_PAD_QSPI1A_DQS Bit Fields */
17304 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_MASK 0x7u
17305 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_SHIFT 0
17306 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_MASK)
17307 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_SION_MASK 0x10u
17308 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_SION_SHIFT 4
17309 /* SW_MUX_CTL_PAD_QSPI1A_SCLK Bit Fields */
17310 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_MASK 0x7u
17311 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_SHIFT 0
17312 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_MASK)
17313 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_SION_MASK 0x10u
17314 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_SION_SHIFT 4
17315 /* SW_MUX_CTL_PAD_QSPI1A_SS0_B Bit Fields */
17316 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_MASK 0x7u
17317 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_SHIFT 0
17318 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_MASK)
17319 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_SION_MASK 0x10u
17320 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_SION_SHIFT 4
17321 /* SW_MUX_CTL_PAD_QSPI1A_SS1_B Bit Fields */
17322 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_MASK 0x7u
17323 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_SHIFT 0
17324 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_MASK)
17325 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_SION_MASK 0x10u
17326 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_SION_SHIFT 4
17327 /* SW_MUX_CTL_PAD_QSPI1B_DATA0 Bit Fields */
17328 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_MASK 0x7u
17329 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_SHIFT 0
17330 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_MASK)
17331 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_SION_MASK 0x10u
17332 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_SION_SHIFT 4
17333 /* SW_MUX_CTL_PAD_QSPI1B_DATA1 Bit Fields */
17334 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_MASK 0x7u
17335 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_SHIFT 0
17336 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_MASK)
17337 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_SION_MASK 0x10u
17338 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_SION_SHIFT 4
17339 /* SW_MUX_CTL_PAD_QSPI1B_DATA2 Bit Fields */
17340 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_MASK 0x7u
17341 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_SHIFT 0
17342 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_MASK)
17343 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_SION_MASK 0x10u
17344 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_SION_SHIFT 4
17345 /* SW_MUX_CTL_PAD_QSPI1B_DATA3 Bit Fields */
17346 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_MASK 0x7u
17347 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_SHIFT 0
17348 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_MASK)
17349 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_SION_MASK 0x10u
17350 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_SION_SHIFT 4
17351 /* SW_MUX_CTL_PAD_QSPI1B_DQS Bit Fields */
17352 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_MASK 0x7u
17353 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_SHIFT 0
17354 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_MASK)
17355 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_SION_MASK 0x10u
17356 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_SION_SHIFT 4
17357 /* SW_MUX_CTL_PAD_QSPI1B_SCLK Bit Fields */
17358 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_MASK 0x7u
17359 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_SHIFT 0
17360 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_MASK)
17361 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_SION_MASK 0x10u
17362 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_SION_SHIFT 4
17363 /* SW_MUX_CTL_PAD_QSPI1B_SS0_B Bit Fields */
17364 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_MASK 0x7u
17365 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_SHIFT 0
17366 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_MASK)
17367 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_SION_MASK 0x10u
17368 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_SION_SHIFT 4
17369 /* SW_MUX_CTL_PAD_QSPI1B_SS1_B Bit Fields */
17370 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_MASK 0x7u
17371 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_SHIFT 0
17372 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_MASK)
17373 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_SION_MASK 0x10u
17374 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_SION_SHIFT 4
17375 /* SW_MUX_CTL_PAD_RGMII1_RD0 Bit Fields */
17376 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_MASK 0x7u
17377 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_SHIFT 0
17378 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_MASK)
17379 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_SION_MASK 0x10u
17380 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_SION_SHIFT 4
17381 /* SW_MUX_CTL_PAD_RGMII1_RD1 Bit Fields */
17382 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_MASK 0x7u
17383 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_SHIFT 0
17384 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_MASK)
17385 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_SION_MASK 0x10u
17386 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_SION_SHIFT 4
17387 /* SW_MUX_CTL_PAD_RGMII1_RD2 Bit Fields */
17388 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_MASK 0x7u
17389 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_SHIFT 0
17390 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_MASK)
17391 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_SION_MASK 0x10u
17392 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_SION_SHIFT 4
17393 /* SW_MUX_CTL_PAD_RGMII1_RD3 Bit Fields */
17394 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_MASK 0x7u
17395 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_SHIFT 0
17396 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_MASK)
17397 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_SION_MASK 0x10u
17398 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_SION_SHIFT 4
17399 /* SW_MUX_CTL_PAD_RGMII1_RX_CTL Bit Fields */
17400 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_MASK 0x7u
17401 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_SHIFT 0
17402 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_MASK)
17403 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_SION_MASK 0x10u
17404 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_SION_SHIFT 4
17405 /* SW_MUX_CTL_PAD_RGMII1_RXC Bit Fields */
17406 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_MASK 0x7u
17407 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_SHIFT 0
17408 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_MASK)
17409 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_SION_MASK 0x10u
17410 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_SION_SHIFT 4
17411 /* SW_MUX_CTL_PAD_RGMII1_TD0 Bit Fields */
17412 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_MASK 0x7u
17413 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_SHIFT 0
17414 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_MASK)
17415 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_SION_MASK 0x10u
17416 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_SION_SHIFT 4
17417 /* SW_MUX_CTL_PAD_RGMII1_TD1 Bit Fields */
17418 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_MASK 0x7u
17419 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_SHIFT 0
17420 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_MASK)
17421 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_SION_MASK 0x10u
17422 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_SION_SHIFT 4
17423 /* SW_MUX_CTL_PAD_RGMII1_TD2 Bit Fields */
17424 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_MASK 0x7u
17425 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_SHIFT 0
17426 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_MASK)
17427 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_SION_MASK 0x10u
17428 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_SION_SHIFT 4
17429 /* SW_MUX_CTL_PAD_RGMII1_TD3 Bit Fields */
17430 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_MASK 0x7u
17431 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_SHIFT 0
17432 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_MASK)
17433 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_SION_MASK 0x10u
17434 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_SION_SHIFT 4
17435 /* SW_MUX_CTL_PAD_RGMII1_TX_CTL Bit Fields */
17436 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_MASK 0x7u
17437 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_SHIFT 0
17438 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_MASK)
17439 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_SION_MASK 0x10u
17440 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_SION_SHIFT 4
17441 /* SW_MUX_CTL_PAD_RGMII1_TXC Bit Fields */
17442 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_MASK 0x7u
17443 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_SHIFT 0
17444 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_MASK)
17445 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_SION_MASK 0x10u
17446 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_SION_SHIFT 4
17447 /* SW_MUX_CTL_PAD_RGMII2_RD0 Bit Fields */
17448 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_MASK 0x7u
17449 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_SHIFT 0
17450 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_MASK)
17451 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_SION_MASK 0x10u
17452 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_SION_SHIFT 4
17453 /* SW_MUX_CTL_PAD_RGMII2_RD1 Bit Fields */
17454 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_MASK 0x7u
17455 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_SHIFT 0
17456 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_MASK)
17457 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_SION_MASK 0x10u
17458 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_SION_SHIFT 4
17459 /* SW_MUX_CTL_PAD_RGMII2_RD2 Bit Fields */
17460 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_MASK 0x7u
17461 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_SHIFT 0
17462 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_MASK)
17463 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_SION_MASK 0x10u
17464 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_SION_SHIFT 4
17465 /* SW_MUX_CTL_PAD_RGMII2_RD3 Bit Fields */
17466 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_MASK 0x7u
17467 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_SHIFT 0
17468 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_MASK)
17469 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_SION_MASK 0x10u
17470 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_SION_SHIFT 4
17471 /* SW_MUX_CTL_PAD_RGMII2_RX_CTL Bit Fields */
17472 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_MASK 0x7u
17473 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_SHIFT 0
17474 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_MASK)
17475 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_SION_MASK 0x10u
17476 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_SION_SHIFT 4
17477 /* SW_MUX_CTL_PAD_RGMII2_RXC Bit Fields */
17478 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_MASK 0x7u
17479 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_SHIFT 0
17480 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_MASK)
17481 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_SION_MASK 0x10u
17482 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_SION_SHIFT 4
17483 /* SW_MUX_CTL_PAD_RGMII2_TD0 Bit Fields */
17484 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_MASK 0x7u
17485 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_SHIFT 0
17486 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_MASK)
17487 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_SION_MASK 0x10u
17488 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_SION_SHIFT 4
17489 /* SW_MUX_CTL_PAD_RGMII2_TD1 Bit Fields */
17490 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_MASK 0x7u
17491 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_SHIFT 0
17492 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_MASK)
17493 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_SION_MASK 0x10u
17494 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_SION_SHIFT 4
17495 /* SW_MUX_CTL_PAD_RGMII2_TD2 Bit Fields */
17496 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_MASK 0x7u
17497 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_SHIFT 0
17498 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_MASK)
17499 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_SION_MASK 0x10u
17500 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_SION_SHIFT 4
17501 /* SW_MUX_CTL_PAD_RGMII2_TD3 Bit Fields */
17502 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_MASK 0x7u
17503 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_SHIFT 0
17504 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_MASK)
17505 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_SION_MASK 0x10u
17506 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_SION_SHIFT 4
17507 /* SW_MUX_CTL_PAD_RGMII2_TX_CTL Bit Fields */
17508 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_MASK 0x7u
17509 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_SHIFT 0
17510 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_MASK)
17511 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_SION_MASK 0x10u
17512 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_SION_SHIFT 4
17513 /* SW_MUX_CTL_PAD_RGMII2_TXC Bit Fields */
17514 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_MASK 0x7u
17515 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_SHIFT 0
17516 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_MASK)
17517 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_SION_MASK 0x10u
17518 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_SION_SHIFT 4
17519 /* SW_MUX_CTL_PAD_SD1_CLK Bit Fields */
17520 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK 0x7u
17521 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT 0
17522 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK)
17523 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_MASK  0x10u
17524 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_SHIFT 4
17525 /* SW_MUX_CTL_PAD_SD1_CMD Bit Fields */
17526 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK 0x7u
17527 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT 0
17528 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK)
17529 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_MASK  0x10u
17530 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_SHIFT 4
17531 /* SW_MUX_CTL_PAD_SD1_DATA0 Bit Fields */
17532 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK 0x7u
17533 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT 0
17534 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK)
17535 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_MASK 0x10u
17536 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_SHIFT 4
17537 /* SW_MUX_CTL_PAD_SD1_DATA1 Bit Fields */
17538 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK 0x7u
17539 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT 0
17540 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK)
17541 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_MASK 0x10u
17542 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_SHIFT 4
17543 /* SW_MUX_CTL_PAD_SD1_DATA2 Bit Fields */
17544 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK 0x7u
17545 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT 0
17546 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK)
17547 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_MASK 0x10u
17548 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_SHIFT 4
17549 /* SW_MUX_CTL_PAD_SD1_DATA3 Bit Fields */
17550 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK 0x7u
17551 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT 0
17552 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK)
17553 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_MASK 0x10u
17554 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_SHIFT 4
17555 /* SW_MUX_CTL_PAD_SD2_CLK Bit Fields */
17556 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK 0x7u
17557 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT 0
17558 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK)
17559 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_MASK  0x10u
17560 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_SHIFT 4
17561 /* SW_MUX_CTL_PAD_SD2_CMD Bit Fields */
17562 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK 0x7u
17563 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT 0
17564 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK)
17565 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_MASK  0x10u
17566 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_SHIFT 4
17567 /* SW_MUX_CTL_PAD_SD2_DATA0 Bit Fields */
17568 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK 0x7u
17569 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT 0
17570 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK)
17571 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_MASK 0x10u
17572 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_SHIFT 4
17573 /* SW_MUX_CTL_PAD_SD2_DATA1 Bit Fields */
17574 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK 0x7u
17575 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT 0
17576 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK)
17577 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_MASK 0x10u
17578 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_SHIFT 4
17579 /* SW_MUX_CTL_PAD_SD2_DATA2 Bit Fields */
17580 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK 0x7u
17581 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT 0
17582 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK)
17583 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_MASK 0x10u
17584 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_SHIFT 4
17585 /* SW_MUX_CTL_PAD_SD2_DATA3 Bit Fields */
17586 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK 0x7u
17587 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT 0
17588 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK)
17589 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_MASK 0x10u
17590 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_SHIFT 4
17591 /* SW_MUX_CTL_PAD_SD3_CLK Bit Fields */
17592 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK 0x7u
17593 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT 0
17594 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK)
17595 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_MASK  0x10u
17596 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_SHIFT 4
17597 /* SW_MUX_CTL_PAD_SD3_CMD Bit Fields */
17598 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK 0x7u
17599 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT 0
17600 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK)
17601 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_MASK  0x10u
17602 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_SHIFT 4
17603 /* SW_MUX_CTL_PAD_SD3_DATA0 Bit Fields */
17604 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK 0x7u
17605 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT 0
17606 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK)
17607 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_MASK 0x10u
17608 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_SHIFT 4
17609 /* SW_MUX_CTL_PAD_SD3_DATA1 Bit Fields */
17610 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK 0x7u
17611 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT 0
17612 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK)
17613 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_MASK 0x10u
17614 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_SHIFT 4
17615 /* SW_MUX_CTL_PAD_SD3_DATA2 Bit Fields */
17616 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK 0x7u
17617 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT 0
17618 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK)
17619 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_MASK 0x10u
17620 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_SHIFT 4
17621 /* SW_MUX_CTL_PAD_SD3_DATA3 Bit Fields */
17622 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK 0x7u
17623 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT 0
17624 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK)
17625 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_MASK 0x10u
17626 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_SHIFT 4
17627 /* SW_MUX_CTL_PAD_SD3_DATA4 Bit Fields */
17628 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK 0x7u
17629 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT 0
17630 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK)
17631 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_MASK 0x10u
17632 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_SHIFT 4
17633 /* SW_MUX_CTL_PAD_SD3_DATA5 Bit Fields */
17634 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK 0x7u
17635 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT 0
17636 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK)
17637 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_MASK 0x10u
17638 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_SHIFT 4
17639 /* SW_MUX_CTL_PAD_SD3_DATA6 Bit Fields */
17640 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK 0x7u
17641 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT 0
17642 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK)
17643 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_MASK 0x10u
17644 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_SHIFT 4
17645 /* SW_MUX_CTL_PAD_SD3_DATA7 Bit Fields */
17646 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK 0x7u
17647 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT 0
17648 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK)
17649 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_MASK 0x10u
17650 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_SHIFT 4
17651 /* SW_MUX_CTL_PAD_SD4_CLK Bit Fields */
17652 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_MASK 0x7u
17653 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_SHIFT 0
17654 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_MASK)
17655 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_MASK  0x10u
17656 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_SHIFT 4
17657 /* SW_MUX_CTL_PAD_SD4_CMD Bit Fields */
17658 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_MASK 0x7u
17659 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_SHIFT 0
17660 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_MASK)
17661 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_MASK  0x10u
17662 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_SHIFT 4
17663 /* SW_MUX_CTL_PAD_SD4_DATA0 Bit Fields */
17664 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_MASK 0x7u
17665 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_SHIFT 0
17666 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_MASK)
17667 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_MASK 0x10u
17668 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_SHIFT 4
17669 /* SW_MUX_CTL_PAD_SD4_DATA1 Bit Fields */
17670 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_MASK 0x7u
17671 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_SHIFT 0
17672 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_MASK)
17673 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_MASK 0x10u
17674 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_SHIFT 4
17675 /* SW_MUX_CTL_PAD_SD4_DATA2 Bit Fields */
17676 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_MASK 0x7u
17677 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_SHIFT 0
17678 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_MASK)
17679 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_MASK 0x10u
17680 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_SHIFT 4
17681 /* SW_MUX_CTL_PAD_SD4_DATA3 Bit Fields */
17682 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_MASK 0x7u
17683 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_SHIFT 0
17684 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_MASK)
17685 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_MASK 0x10u
17686 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_SHIFT 4
17687 /* SW_MUX_CTL_PAD_SD4_DATA4 Bit Fields */
17688 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_MASK 0x7u
17689 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_SHIFT 0
17690 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_MASK)
17691 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_MASK 0x10u
17692 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_SHIFT 4
17693 /* SW_MUX_CTL_PAD_SD4_DATA5 Bit Fields */
17694 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_MASK 0x7u
17695 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_SHIFT 0
17696 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_MASK)
17697 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_MASK 0x10u
17698 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_SHIFT 4
17699 /* SW_MUX_CTL_PAD_SD4_DATA6 Bit Fields */
17700 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_MASK 0x7u
17701 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_SHIFT 0
17702 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_MASK)
17703 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_MASK 0x10u
17704 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_SHIFT 4
17705 /* SW_MUX_CTL_PAD_SD4_DATA7 Bit Fields */
17706 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_MASK 0x7u
17707 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_SHIFT 0
17708 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_MASK)
17709 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_MASK 0x10u
17710 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_SHIFT 4
17711 /* SW_MUX_CTL_PAD_SD4_RESET_B Bit Fields */
17712 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_MASK 0x7u
17713 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_SHIFT 0
17714 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_MASK)
17715 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_SION_MASK 0x10u
17716 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_SION_SHIFT 4
17717 /* SW_MUX_CTL_PAD_USB_H_DATA Bit Fields */
17718 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_MASK 0x7u
17719 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_SHIFT 0
17720 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_MASK)
17721 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_SION_MASK 0x10u
17722 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_SION_SHIFT 4
17723 /* SW_MUX_CTL_PAD_USB_H_STROBE Bit Fields */
17724 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_MASK 0x7u
17725 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_SHIFT 0
17726 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_MASK)
17727 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_SION_MASK 0x10u
17728 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_SION_SHIFT 4
17729 /* SW_PAD_CTL_PAD_DRAM_ADDR00 Bit Fields */
17730 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_MASK 0x38u
17731 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_SHIFT 3
17732 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_MASK)
17733 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_MASK 0x700u
17734 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_SHIFT 8
17735 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_MASK)
17736 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE_MASK 0x1000u
17737 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE_SHIFT 12
17738 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE_MASK 0x2000u
17739 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE_SHIFT 13
17740 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_MASK 0xC000u
17741 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_SHIFT 14
17742 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_MASK)
17743 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_MASK 0x10000u
17744 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_SHIFT 16
17745 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_MASK 0x20000u
17746 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_SHIFT 17
17747 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_MASK 0xC0000u
17748 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_SHIFT 18
17749 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_MASK)
17750 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_MASK 0x300000u
17751 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_SHIFT 20
17752 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_MASK)
17753 /* SW_PAD_CTL_PAD_DRAM_ADDR01 Bit Fields */
17754 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_MASK 0x38u
17755 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_SHIFT 3
17756 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_MASK)
17757 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_MASK 0x700u
17758 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_SHIFT 8
17759 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_MASK)
17760 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE_MASK 0x1000u
17761 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE_SHIFT 12
17762 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE_MASK 0x2000u
17763 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE_SHIFT 13
17764 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_MASK 0xC000u
17765 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_SHIFT 14
17766 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_MASK)
17767 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_MASK 0x10000u
17768 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_SHIFT 16
17769 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_MASK 0x20000u
17770 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_SHIFT 17
17771 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_MASK 0xC0000u
17772 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_SHIFT 18
17773 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_MASK)
17774 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_MASK 0x300000u
17775 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_SHIFT 20
17776 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_MASK)
17777 /* SW_PAD_CTL_PAD_DRAM_ADDR02 Bit Fields */
17778 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_MASK 0x38u
17779 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_SHIFT 3
17780 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_MASK)
17781 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_MASK 0x700u
17782 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_SHIFT 8
17783 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_MASK)
17784 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE_MASK 0x1000u
17785 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE_SHIFT 12
17786 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE_MASK 0x2000u
17787 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE_SHIFT 13
17788 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_MASK 0xC000u
17789 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_SHIFT 14
17790 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_MASK)
17791 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_MASK 0x10000u
17792 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_SHIFT 16
17793 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_MASK 0x20000u
17794 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_SHIFT 17
17795 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_MASK 0xC0000u
17796 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_SHIFT 18
17797 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_MASK)
17798 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_MASK 0x300000u
17799 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_SHIFT 20
17800 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_MASK)
17801 /* SW_PAD_CTL_PAD_DRAM_ADDR03 Bit Fields */
17802 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_MASK 0x38u
17803 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_SHIFT 3
17804 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_MASK)
17805 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_MASK 0x700u
17806 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_SHIFT 8
17807 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_MASK)
17808 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE_MASK 0x1000u
17809 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE_SHIFT 12
17810 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE_MASK 0x2000u
17811 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE_SHIFT 13
17812 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_MASK 0xC000u
17813 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_SHIFT 14
17814 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_MASK)
17815 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_MASK 0x10000u
17816 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_SHIFT 16
17817 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_MASK 0x20000u
17818 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_SHIFT 17
17819 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_MASK 0xC0000u
17820 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_SHIFT 18
17821 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_MASK)
17822 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_MASK 0x300000u
17823 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_SHIFT 20
17824 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_MASK)
17825 /* SW_PAD_CTL_PAD_DRAM_ADDR04 Bit Fields */
17826 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_MASK 0x38u
17827 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_SHIFT 3
17828 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_MASK)
17829 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_MASK 0x700u
17830 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_SHIFT 8
17831 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_MASK)
17832 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE_MASK 0x1000u
17833 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE_SHIFT 12
17834 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE_MASK 0x2000u
17835 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE_SHIFT 13
17836 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_MASK 0xC000u
17837 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_SHIFT 14
17838 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_MASK)
17839 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_MASK 0x10000u
17840 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_SHIFT 16
17841 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_MASK 0x20000u
17842 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_SHIFT 17
17843 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_MASK 0xC0000u
17844 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_SHIFT 18
17845 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_MASK)
17846 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_MASK 0x300000u
17847 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_SHIFT 20
17848 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_MASK)
17849 /* SW_PAD_CTL_PAD_DRAM_ADDR05 Bit Fields */
17850 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_MASK 0x38u
17851 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_SHIFT 3
17852 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_MASK)
17853 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_MASK 0x700u
17854 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_SHIFT 8
17855 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_MASK)
17856 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE_MASK 0x1000u
17857 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE_SHIFT 12
17858 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE_MASK 0x2000u
17859 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE_SHIFT 13
17860 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_MASK 0xC000u
17861 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_SHIFT 14
17862 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_MASK)
17863 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_MASK 0x10000u
17864 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_SHIFT 16
17865 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_MASK 0x20000u
17866 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_SHIFT 17
17867 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_MASK 0xC0000u
17868 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_SHIFT 18
17869 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_MASK)
17870 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_MASK 0x300000u
17871 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_SHIFT 20
17872 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_MASK)
17873 /* SW_PAD_CTL_PAD_DRAM_ADDR06 Bit Fields */
17874 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_MASK 0x38u
17875 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_SHIFT 3
17876 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_MASK)
17877 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_MASK 0x700u
17878 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_SHIFT 8
17879 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_MASK)
17880 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE_MASK 0x1000u
17881 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE_SHIFT 12
17882 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE_MASK 0x2000u
17883 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE_SHIFT 13
17884 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_MASK 0xC000u
17885 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_SHIFT 14
17886 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_MASK)
17887 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_MASK 0x10000u
17888 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_SHIFT 16
17889 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_MASK 0x20000u
17890 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_SHIFT 17
17891 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_MASK 0xC0000u
17892 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_SHIFT 18
17893 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_MASK)
17894 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_MASK 0x300000u
17895 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_SHIFT 20
17896 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_MASK)
17897 /* SW_PAD_CTL_PAD_DRAM_ADDR07 Bit Fields */
17898 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_MASK 0x38u
17899 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_SHIFT 3
17900 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_MASK)
17901 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_MASK 0x700u
17902 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_SHIFT 8
17903 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_MASK)
17904 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE_MASK 0x1000u
17905 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE_SHIFT 12
17906 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE_MASK 0x2000u
17907 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE_SHIFT 13
17908 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_MASK 0xC000u
17909 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_SHIFT 14
17910 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_MASK)
17911 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_MASK 0x10000u
17912 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_SHIFT 16
17913 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_MASK 0x20000u
17914 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_SHIFT 17
17915 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_MASK 0xC0000u
17916 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_SHIFT 18
17917 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_MASK)
17918 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_MASK 0x300000u
17919 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_SHIFT 20
17920 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_MASK)
17921 /* SW_PAD_CTL_PAD_DRAM_ADDR08 Bit Fields */
17922 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_MASK 0x38u
17923 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_SHIFT 3
17924 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_MASK)
17925 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_MASK 0x700u
17926 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_SHIFT 8
17927 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_MASK)
17928 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE_MASK 0x1000u
17929 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE_SHIFT 12
17930 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE_MASK 0x2000u
17931 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE_SHIFT 13
17932 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_MASK 0xC000u
17933 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_SHIFT 14
17934 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_MASK)
17935 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_MASK 0x10000u
17936 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_SHIFT 16
17937 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_MASK 0x20000u
17938 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_SHIFT 17
17939 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_MASK 0xC0000u
17940 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_SHIFT 18
17941 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_MASK)
17942 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_MASK 0x300000u
17943 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_SHIFT 20
17944 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_MASK)
17945 /* SW_PAD_CTL_PAD_DRAM_ADDR09 Bit Fields */
17946 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_MASK 0x38u
17947 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_SHIFT 3
17948 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_MASK)
17949 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_MASK 0x700u
17950 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_SHIFT 8
17951 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_MASK)
17952 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE_MASK 0x1000u
17953 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE_SHIFT 12
17954 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_MASK 0x2000u
17955 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_SHIFT 13
17956 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_MASK 0xC000u
17957 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_SHIFT 14
17958 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_MASK)
17959 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_MASK 0x10000u
17960 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_SHIFT 16
17961 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_MASK 0x20000u
17962 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_SHIFT 17
17963 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_MASK 0xC0000u
17964 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_SHIFT 18
17965 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_MASK)
17966 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_MASK 0x300000u
17967 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_SHIFT 20
17968 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_MASK)
17969 /* SW_PAD_CTL_PAD_DRAM_ADDR10 Bit Fields */
17970 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_MASK 0x38u
17971 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_SHIFT 3
17972 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_MASK)
17973 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_MASK 0x700u
17974 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_SHIFT 8
17975 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_MASK)
17976 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE_MASK 0x1000u
17977 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE_SHIFT 12
17978 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE_MASK 0x2000u
17979 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE_SHIFT 13
17980 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_MASK 0xC000u
17981 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_SHIFT 14
17982 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_MASK)
17983 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_MASK 0x10000u
17984 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_SHIFT 16
17985 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_MASK 0x20000u
17986 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_SHIFT 17
17987 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_MASK 0xC0000u
17988 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_SHIFT 18
17989 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_MASK)
17990 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_MASK 0x300000u
17991 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_SHIFT 20
17992 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_MASK)
17993 /* SW_PAD_CTL_PAD_DRAM_ADDR11 Bit Fields */
17994 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_MASK 0x38u
17995 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_SHIFT 3
17996 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_MASK)
17997 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_MASK 0x700u
17998 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_SHIFT 8
17999 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_MASK)
18000 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE_MASK 0x1000u
18001 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE_SHIFT 12
18002 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE_MASK 0x2000u
18003 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE_SHIFT 13
18004 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_MASK 0xC000u
18005 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_SHIFT 14
18006 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_MASK)
18007 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_MASK 0x10000u
18008 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_SHIFT 16
18009 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_MASK 0x20000u
18010 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_SHIFT 17
18011 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_MASK 0xC0000u
18012 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_SHIFT 18
18013 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_MASK)
18014 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_MASK 0x300000u
18015 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_SHIFT 20
18016 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_MASK)
18017 /* SW_PAD_CTL_PAD_DRAM_ADDR12 Bit Fields */
18018 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_MASK 0x38u
18019 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_SHIFT 3
18020 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_MASK)
18021 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_MASK 0x700u
18022 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_SHIFT 8
18023 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_MASK)
18024 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE_MASK 0x1000u
18025 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE_SHIFT 12
18026 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE_MASK 0x2000u
18027 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE_SHIFT 13
18028 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_MASK 0xC000u
18029 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_SHIFT 14
18030 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_MASK)
18031 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_MASK 0x10000u
18032 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_SHIFT 16
18033 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_MASK 0x20000u
18034 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_SHIFT 17
18035 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_MASK 0xC0000u
18036 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_SHIFT 18
18037 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_MASK)
18038 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_MASK 0x300000u
18039 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_SHIFT 20
18040 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_MASK)
18041 /* SW_PAD_CTL_PAD_DRAM_ADDR13 Bit Fields */
18042 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_MASK 0x38u
18043 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_SHIFT 3
18044 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_MASK)
18045 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_MASK 0x700u
18046 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_SHIFT 8
18047 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_MASK)
18048 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE_MASK 0x1000u
18049 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE_SHIFT 12
18050 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE_MASK 0x2000u
18051 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE_SHIFT 13
18052 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_MASK 0xC000u
18053 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_SHIFT 14
18054 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_MASK)
18055 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_MASK 0x10000u
18056 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_SHIFT 16
18057 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_MASK 0x20000u
18058 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_SHIFT 17
18059 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_MASK 0xC0000u
18060 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_SHIFT 18
18061 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_MASK)
18062 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_MASK 0x300000u
18063 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_SHIFT 20
18064 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_MASK)
18065 /* SW_PAD_CTL_PAD_DRAM_ADDR14 Bit Fields */
18066 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_MASK 0x38u
18067 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_SHIFT 3
18068 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_MASK)
18069 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_MASK 0x700u
18070 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_SHIFT 8
18071 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_MASK)
18072 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE_MASK 0x1000u
18073 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE_SHIFT 12
18074 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE_MASK 0x2000u
18075 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE_SHIFT 13
18076 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_MASK 0xC000u
18077 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_SHIFT 14
18078 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_MASK)
18079 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_MASK 0x10000u
18080 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_SHIFT 16
18081 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_MASK 0x20000u
18082 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_SHIFT 17
18083 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_MASK 0xC0000u
18084 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_SHIFT 18
18085 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_MASK)
18086 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_MASK 0x300000u
18087 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_SHIFT 20
18088 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_MASK)
18089 /* SW_PAD_CTL_PAD_DRAM_ADDR15 Bit Fields */
18090 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_MASK 0x38u
18091 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_SHIFT 3
18092 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_MASK)
18093 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_MASK 0x700u
18094 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_SHIFT 8
18095 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_MASK)
18096 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE_MASK 0x1000u
18097 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE_SHIFT 12
18098 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE_MASK 0x2000u
18099 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE_SHIFT 13
18100 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_MASK 0xC000u
18101 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_SHIFT 14
18102 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_MASK)
18103 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_MASK 0x10000u
18104 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_SHIFT 16
18105 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_MASK 0x20000u
18106 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_SHIFT 17
18107 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_MASK 0xC0000u
18108 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_SHIFT 18
18109 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_MASK)
18110 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_MASK 0x300000u
18111 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_SHIFT 20
18112 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_MASK)
18113 /* SW_PAD_CTL_PAD_DRAM_DQM0 Bit Fields */
18114 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_MASK 0x38u
18115 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_SHIFT 3
18116 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_MASK)
18117 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_MASK 0x700u
18118 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_SHIFT 8
18119 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_MASK)
18120 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE_MASK 0x1000u
18121 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE_SHIFT 12
18122 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE_MASK 0x2000u
18123 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE_SHIFT 13
18124 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_MASK 0xC000u
18125 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_SHIFT 14
18126 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_MASK)
18127 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_MASK 0x10000u
18128 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_SHIFT 16
18129 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_MASK 0x20000u
18130 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_SHIFT 17
18131 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_MASK 0xC0000u
18132 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_SHIFT 18
18133 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_MASK)
18134 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_MASK 0x300000u
18135 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_SHIFT 20
18136 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_MASK)
18137 /* SW_PAD_CTL_PAD_DRAM_DQM1 Bit Fields */
18138 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_MASK 0x38u
18139 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_SHIFT 3
18140 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_MASK)
18141 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_MASK 0x700u
18142 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_SHIFT 8
18143 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_MASK)
18144 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE_MASK 0x1000u
18145 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE_SHIFT 12
18146 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE_MASK 0x2000u
18147 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE_SHIFT 13
18148 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_MASK 0xC000u
18149 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_SHIFT 14
18150 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_MASK)
18151 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_MASK 0x10000u
18152 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_SHIFT 16
18153 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_MASK 0x20000u
18154 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_SHIFT 17
18155 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_MASK 0xC0000u
18156 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_SHIFT 18
18157 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_MASK)
18158 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_MASK 0x300000u
18159 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_SHIFT 20
18160 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_MASK)
18161 /* SW_PAD_CTL_PAD_DRAM_DQM2 Bit Fields */
18162 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_MASK 0x38u
18163 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_SHIFT 3
18164 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_MASK)
18165 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_MASK 0x700u
18166 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_SHIFT 8
18167 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_MASK)
18168 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE_MASK 0x1000u
18169 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE_SHIFT 12
18170 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE_MASK 0x2000u
18171 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE_SHIFT 13
18172 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_MASK 0xC000u
18173 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_SHIFT 14
18174 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_MASK)
18175 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_MASK 0x10000u
18176 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_SHIFT 16
18177 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_MASK 0x20000u
18178 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_SHIFT 17
18179 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_MASK 0xC0000u
18180 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_SHIFT 18
18181 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_MASK)
18182 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_MASK 0x300000u
18183 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_SHIFT 20
18184 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_MASK)
18185 /* SW_PAD_CTL_PAD_DRAM_DQM3 Bit Fields */
18186 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_MASK 0x38u
18187 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_SHIFT 3
18188 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_MASK)
18189 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_MASK 0x700u
18190 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_SHIFT 8
18191 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_MASK)
18192 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE_MASK 0x1000u
18193 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE_SHIFT 12
18194 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE_MASK 0x2000u
18195 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE_SHIFT 13
18196 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_MASK 0xC000u
18197 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_SHIFT 14
18198 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_MASK)
18199 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_MASK 0x10000u
18200 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_SHIFT 16
18201 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_MASK 0x20000u
18202 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_SHIFT 17
18203 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_MASK 0xC0000u
18204 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_SHIFT 18
18205 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_MASK)
18206 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_MASK 0x300000u
18207 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_SHIFT 20
18208 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_MASK)
18209 /* SW_PAD_CTL_PAD_DRAM_RAS_B Bit Fields */
18210 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_MASK 0x38u
18211 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_SHIFT 3
18212 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_MASK)
18213 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_MASK 0x700u
18214 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_SHIFT 8
18215 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_MASK)
18216 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PKE_MASK 0x1000u
18217 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PKE_SHIFT 12
18218 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUE_MASK 0x2000u
18219 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUE_SHIFT 13
18220 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_MASK 0xC000u
18221 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_SHIFT 14
18222 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_MASK)
18223 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_HYS_MASK 0x10000u
18224 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_HYS_SHIFT 16
18225 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_INPUT_MASK 0x20000u
18226 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_INPUT_SHIFT 17
18227 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_MASK 0xC0000u
18228 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_SHIFT 18
18229 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_MASK)
18230 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_MASK 0x300000u
18231 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_SHIFT 20
18232 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_MASK)
18233 /* SW_PAD_CTL_PAD_DRAM_CAS_B Bit Fields */
18234 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_MASK 0x38u
18235 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_SHIFT 3
18236 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_MASK)
18237 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_MASK 0x700u
18238 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_SHIFT 8
18239 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_MASK)
18240 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PKE_MASK 0x1000u
18241 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PKE_SHIFT 12
18242 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUE_MASK 0x2000u
18243 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUE_SHIFT 13
18244 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_MASK 0xC000u
18245 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_SHIFT 14
18246 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_MASK)
18247 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_HYS_MASK 0x10000u
18248 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_HYS_SHIFT 16
18249 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_INPUT_MASK 0x20000u
18250 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_INPUT_SHIFT 17
18251 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_MASK 0xC0000u
18252 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_SHIFT 18
18253 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_MASK)
18254 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_MASK 0x300000u
18255 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_SHIFT 20
18256 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_MASK)
18257 /* SW_PAD_CTL_PAD_DRAM_CS0_B Bit Fields */
18258 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_MASK 0x38u
18259 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_SHIFT 3
18260 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_MASK)
18261 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_MASK 0x700u
18262 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_SHIFT 8
18263 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_MASK)
18264 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PKE_MASK 0x1000u
18265 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PKE_SHIFT 12
18266 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUE_MASK 0x2000u
18267 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUE_SHIFT 13
18268 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_MASK 0xC000u
18269 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_SHIFT 14
18270 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_MASK)
18271 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_HYS_MASK 0x10000u
18272 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_HYS_SHIFT 16
18273 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_INPUT_MASK 0x20000u
18274 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_INPUT_SHIFT 17
18275 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_MASK 0xC0000u
18276 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_SHIFT 18
18277 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_MASK)
18278 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_MASK 0x300000u
18279 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_SHIFT 20
18280 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_MASK)
18281 /* SW_PAD_CTL_PAD_DRAM_CS1_B Bit Fields */
18282 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_MASK 0x38u
18283 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_SHIFT 3
18284 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_MASK)
18285 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_MASK 0x700u
18286 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_SHIFT 8
18287 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_MASK)
18288 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PKE_MASK 0x1000u
18289 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PKE_SHIFT 12
18290 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUE_MASK 0x2000u
18291 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUE_SHIFT 13
18292 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_MASK 0xC000u
18293 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_SHIFT 14
18294 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_MASK)
18295 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_HYS_MASK 0x10000u
18296 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_HYS_SHIFT 16
18297 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_INPUT_MASK 0x20000u
18298 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_INPUT_SHIFT 17
18299 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_MASK 0xC0000u
18300 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_SHIFT 18
18301 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_MASK)
18302 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_MASK 0x300000u
18303 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_SHIFT 20
18304 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_MASK)
18305 /* SW_PAD_CTL_PAD_DRAM_SDWE_B Bit Fields */
18306 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_MASK 0x38u
18307 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_SHIFT 3
18308 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_MASK)
18309 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_MASK 0x700u
18310 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_SHIFT 8
18311 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_MASK)
18312 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PKE_MASK 0x1000u
18313 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PKE_SHIFT 12
18314 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUE_MASK 0x2000u
18315 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUE_SHIFT 13
18316 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_MASK 0xC000u
18317 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_SHIFT 14
18318 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_MASK)
18319 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_HYS_MASK 0x10000u
18320 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_HYS_SHIFT 16
18321 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_INPUT_MASK 0x20000u
18322 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_INPUT_SHIFT 17
18323 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_MASK 0xC0000u
18324 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_SHIFT 18
18325 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_MASK)
18326 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_MASK 0x300000u
18327 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_SHIFT 20
18328 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_MASK)
18329 /* SW_PAD_CTL_PAD_DRAM_ODT0 Bit Fields */
18330 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_MASK 0x38u
18331 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_SHIFT 3
18332 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_MASK)
18333 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_MASK 0x700u
18334 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_SHIFT 8
18335 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_MASK)
18336 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_MASK 0x1000u
18337 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_SHIFT 12
18338 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_MASK 0x2000u
18339 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_SHIFT 13
18340 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_MASK 0xC000u
18341 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_SHIFT 14
18342 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_MASK)
18343 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_MASK 0x10000u
18344 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_SHIFT 16
18345 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_MASK 0x20000u
18346 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_SHIFT 17
18347 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_MASK 0xC0000u
18348 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_SHIFT 18
18349 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_MASK)
18350 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_MASK 0x300000u
18351 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_SHIFT 20
18352 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_MASK)
18353 /* SW_PAD_CTL_PAD_DRAM_ODT1 Bit Fields */
18354 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_MASK 0x38u
18355 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_SHIFT 3
18356 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_MASK)
18357 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_MASK 0x700u
18358 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_SHIFT 8
18359 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_MASK)
18360 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_MASK 0x1000u
18361 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_SHIFT 12
18362 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_MASK 0x2000u
18363 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_SHIFT 13
18364 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_MASK 0xC000u
18365 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_SHIFT 14
18366 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_MASK)
18367 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_MASK 0x10000u
18368 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_SHIFT 16
18369 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_MASK 0x20000u
18370 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_SHIFT 17
18371 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_MASK 0xC0000u
18372 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_SHIFT 18
18373 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_MASK)
18374 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_MASK 0x300000u
18375 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_SHIFT 20
18376 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_MASK)
18377 /* SW_PAD_CTL_PAD_DRAM_SDBA0 Bit Fields */
18378 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_MASK 0x38u
18379 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_SHIFT 3
18380 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_MASK)
18381 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_MASK 0x700u
18382 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_SHIFT 8
18383 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_MASK)
18384 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE_MASK 0x1000u
18385 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE_SHIFT 12
18386 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE_MASK 0x2000u
18387 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE_SHIFT 13
18388 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_MASK 0xC000u
18389 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_SHIFT 14
18390 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_MASK)
18391 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_MASK 0x10000u
18392 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_SHIFT 16
18393 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_MASK 0x20000u
18394 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_SHIFT 17
18395 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_MASK 0xC0000u
18396 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_SHIFT 18
18397 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_MASK)
18398 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_MASK 0x300000u
18399 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_SHIFT 20
18400 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_MASK)
18401 /* SW_PAD_CTL_PAD_DRAM_SDBA1 Bit Fields */
18402 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_MASK 0x38u
18403 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_SHIFT 3
18404 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_MASK)
18405 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_MASK 0x700u
18406 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_SHIFT 8
18407 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_MASK)
18408 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE_MASK 0x1000u
18409 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE_SHIFT 12
18410 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE_MASK 0x2000u
18411 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE_SHIFT 13
18412 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_MASK 0xC000u
18413 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_SHIFT 14
18414 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_MASK)
18415 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_MASK 0x10000u
18416 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_SHIFT 16
18417 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_MASK 0x20000u
18418 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_SHIFT 17
18419 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_MASK 0xC0000u
18420 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_SHIFT 18
18421 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_MASK)
18422 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_MASK 0x300000u
18423 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_SHIFT 20
18424 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_MASK)
18425 /* SW_PAD_CTL_PAD_DRAM_SDBA2 Bit Fields */
18426 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_MASK 0x38u
18427 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_SHIFT 3
18428 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_MASK)
18429 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_MASK 0x700u
18430 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_SHIFT 8
18431 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_MASK)
18432 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_MASK 0x1000u
18433 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_SHIFT 12
18434 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_MASK 0x2000u
18435 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_SHIFT 13
18436 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_MASK 0xC000u
18437 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_SHIFT 14
18438 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_MASK)
18439 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_MASK 0x10000u
18440 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_SHIFT 16
18441 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_MASK 0x20000u
18442 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_SHIFT 17
18443 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_MASK 0xC0000u
18444 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_SHIFT 18
18445 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_MASK)
18446 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_MASK 0x300000u
18447 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_SHIFT 20
18448 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_MASK)
18449 /* SW_PAD_CTL_PAD_DRAM_SDCKE0 Bit Fields */
18450 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_MASK 0x38u
18451 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_SHIFT 3
18452 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_MASK)
18453 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_MASK 0x700u
18454 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_SHIFT 8
18455 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_MASK)
18456 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_MASK 0x1000u
18457 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_SHIFT 12
18458 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_MASK 0x2000u
18459 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_SHIFT 13
18460 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_MASK 0xC000u
18461 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_SHIFT 14
18462 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_MASK)
18463 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_MASK 0x10000u
18464 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_SHIFT 16
18465 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_MASK 0x20000u
18466 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_SHIFT 17
18467 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_MASK 0xC0000u
18468 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_SHIFT 18
18469 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_MASK)
18470 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_MASK 0x300000u
18471 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_SHIFT 20
18472 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_MASK)
18473 /* SW_PAD_CTL_PAD_DRAM_SDCKE1 Bit Fields */
18474 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_MASK 0x38u
18475 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_SHIFT 3
18476 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_MASK)
18477 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_MASK 0x700u
18478 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_SHIFT 8
18479 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_MASK)
18480 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_MASK 0x1000u
18481 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_SHIFT 12
18482 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_MASK 0x2000u
18483 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_SHIFT 13
18484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_MASK 0xC000u
18485 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_SHIFT 14
18486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_MASK)
18487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_MASK 0x10000u
18488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_SHIFT 16
18489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_MASK 0x20000u
18490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_SHIFT 17
18491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_MASK 0xC0000u
18492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_SHIFT 18
18493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_MASK)
18494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_MASK 0x300000u
18495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_SHIFT 20
18496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_MASK)
18497 /* SW_PAD_CTL_PAD_DRAM_SDCLK0_P Bit Fields */
18498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_MASK 0x38u
18499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_SHIFT 3
18500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_MASK)
18501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_MASK 0x700u
18502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_SHIFT 8
18503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_MASK)
18504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE_MASK 0x1000u
18505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE_SHIFT 12
18506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE_MASK 0x2000u
18507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE_SHIFT 13
18508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_MASK 0xC000u
18509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_SHIFT 14
18510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_MASK)
18511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_MASK 0x10000u
18512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_SHIFT 16
18513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_MASK 0x20000u
18514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_SHIFT 17
18515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_MASK 0xC0000u
18516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_SHIFT 18
18517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_MASK)
18518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_MASK 0x300000u
18519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_SHIFT 20
18520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_MASK)
18521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_MASK 0x3000000u
18522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_SHIFT 24
18523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_MASK)
18524 /* SW_PAD_CTL_PAD_DRAM_SDQS0_P Bit Fields */
18525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_MASK 0x38u
18526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_SHIFT 3
18527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_MASK)
18528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_MASK 0x700u
18529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_SHIFT 8
18530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_MASK)
18531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_MASK 0x1000u
18532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_SHIFT 12
18533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_MASK 0x2000u
18534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_SHIFT 13
18535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_MASK 0xC000u
18536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_SHIFT 14
18537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_MASK)
18538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS_MASK 0x10000u
18539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS_SHIFT 16
18540 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT_MASK 0x20000u
18541 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT_SHIFT 17
18542 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_MASK 0xC0000u
18543 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_SHIFT 18
18544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_MASK)
18545 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_MASK 0x300000u
18546 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_SHIFT 20
18547 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_MASK)
18548 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_MASK 0x3000000u
18549 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_SHIFT 24
18550 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_MASK)
18551 /* SW_PAD_CTL_PAD_DRAM_SDQS1_P Bit Fields */
18552 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_MASK 0x38u
18553 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_SHIFT 3
18554 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_MASK)
18555 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_MASK 0x700u
18556 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_SHIFT 8
18557 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_MASK)
18558 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_MASK 0x1000u
18559 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_SHIFT 12
18560 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_MASK 0x2000u
18561 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_SHIFT 13
18562 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_MASK 0xC000u
18563 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_SHIFT 14
18564 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_MASK)
18565 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS_MASK 0x10000u
18566 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS_SHIFT 16
18567 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT_MASK 0x20000u
18568 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT_SHIFT 17
18569 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_MASK 0xC0000u
18570 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_SHIFT 18
18571 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_MASK)
18572 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_MASK 0x300000u
18573 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_SHIFT 20
18574 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_MASK)
18575 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_MASK 0x3000000u
18576 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_SHIFT 24
18577 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_MASK)
18578 /* SW_PAD_CTL_PAD_DRAM_SDQS2_P Bit Fields */
18579 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_MASK 0x38u
18580 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_SHIFT 3
18581 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_MASK)
18582 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_MASK 0x700u
18583 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_SHIFT 8
18584 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_MASK)
18585 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_MASK 0x1000u
18586 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_SHIFT 12
18587 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_MASK 0x2000u
18588 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_SHIFT 13
18589 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_MASK 0xC000u
18590 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_SHIFT 14
18591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_MASK)
18592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS_MASK 0x10000u
18593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS_SHIFT 16
18594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT_MASK 0x20000u
18595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT_SHIFT 17
18596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_MASK 0xC0000u
18597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_SHIFT 18
18598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_MASK)
18599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_MASK 0x300000u
18600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_SHIFT 20
18601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_MASK)
18602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_MASK 0x3000000u
18603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_SHIFT 24
18604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_MASK)
18605 /* SW_PAD_CTL_PAD_DRAM_SDQS3_P Bit Fields */
18606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_MASK 0x38u
18607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_SHIFT 3
18608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_MASK)
18609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_MASK 0x700u
18610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_SHIFT 8
18611 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_MASK)
18612 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_MASK 0x1000u
18613 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_SHIFT 12
18614 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_MASK 0x2000u
18615 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_SHIFT 13
18616 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_MASK 0xC000u
18617 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_SHIFT 14
18618 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_MASK)
18619 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS_MASK 0x10000u
18620 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS_SHIFT 16
18621 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT_MASK 0x20000u
18622 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT_SHIFT 17
18623 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_MASK 0xC0000u
18624 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_SHIFT 18
18625 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_MASK)
18626 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_MASK 0x300000u
18627 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_SHIFT 20
18628 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_MASK)
18629 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_MASK 0x3000000u
18630 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_SHIFT 24
18631 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_MASK)
18632 /* SW_PAD_CTL_PAD_DRAM_RESET Bit Fields */
18633 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_MASK 0x38u
18634 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_SHIFT 3
18635 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_MASK)
18636 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_MASK 0x700u
18637 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_SHIFT 8
18638 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_MASK)
18639 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_MASK 0x1000u
18640 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_SHIFT 12
18641 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_MASK 0x2000u
18642 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_SHIFT 13
18643 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_MASK 0xC000u
18644 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_SHIFT 14
18645 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_MASK)
18646 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_MASK 0x10000u
18647 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_SHIFT 16
18648 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_MASK 0x20000u
18649 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_SHIFT 17
18650 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_MASK 0xC0000u
18651 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_SHIFT 18
18652 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_MASK)
18653 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_MASK 0x300000u
18654 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_SHIFT 20
18655 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_MASK)
18656 /* SW_PAD_CTL_PAD_JTAG_MOD Bit Fields */
18657 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_MASK  0x1u
18658 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_SHIFT 0
18659 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK  0x38u
18660 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT 3
18661 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK)
18662 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_MASK 0xC0u
18663 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_SHIFT 6
18664 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_MASK)
18665 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE_MASK  0x800u
18666 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE_SHIFT 11
18667 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_MASK  0x1000u
18668 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_SHIFT 12
18669 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE_MASK  0x2000u
18670 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE_SHIFT 13
18671 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_MASK  0xC000u
18672 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_SHIFT 14
18673 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_MASK)
18674 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_MASK  0x10000u
18675 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_SHIFT 16
18676 /* SW_PAD_CTL_PAD_JTAG_TCK Bit Fields */
18677 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_MASK  0x1u
18678 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_SHIFT 0
18679 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK  0x38u
18680 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT 3
18681 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK)
18682 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_MASK 0xC0u
18683 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_SHIFT 6
18684 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_MASK)
18685 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE_MASK  0x800u
18686 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE_SHIFT 11
18687 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_MASK  0x1000u
18688 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_SHIFT 12
18689 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE_MASK  0x2000u
18690 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE_SHIFT 13
18691 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_MASK  0xC000u
18692 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_SHIFT 14
18693 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_MASK)
18694 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_MASK  0x10000u
18695 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_SHIFT 16
18696 /* SW_PAD_CTL_PAD_JTAG_TDI Bit Fields */
18697 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_MASK  0x1u
18698 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_SHIFT 0
18699 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK  0x38u
18700 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT 3
18701 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK)
18702 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_MASK 0xC0u
18703 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_SHIFT 6
18704 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_MASK)
18705 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE_MASK  0x800u
18706 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE_SHIFT 11
18707 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_MASK  0x1000u
18708 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_SHIFT 12
18709 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE_MASK  0x2000u
18710 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE_SHIFT 13
18711 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_MASK  0xC000u
18712 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_SHIFT 14
18713 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_MASK)
18714 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_MASK  0x10000u
18715 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_SHIFT 16
18716 /* SW_PAD_CTL_PAD_JTAG_TDO Bit Fields */
18717 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_MASK  0x1u
18718 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_SHIFT 0
18719 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK  0x38u
18720 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT 3
18721 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK)
18722 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_MASK 0xC0u
18723 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_SHIFT 6
18724 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_MASK)
18725 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE_MASK  0x800u
18726 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE_SHIFT 11
18727 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_MASK  0x1000u
18728 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_SHIFT 12
18729 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE_MASK  0x2000u
18730 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE_SHIFT 13
18731 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_MASK  0xC000u
18732 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_SHIFT 14
18733 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_MASK)
18734 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_MASK  0x10000u
18735 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_SHIFT 16
18736 /* SW_PAD_CTL_PAD_JTAG_TMS Bit Fields */
18737 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_MASK  0x1u
18738 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_SHIFT 0
18739 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK  0x38u
18740 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT 3
18741 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK)
18742 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_MASK 0xC0u
18743 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_SHIFT 6
18744 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_MASK)
18745 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE_MASK  0x800u
18746 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE_SHIFT 11
18747 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_MASK  0x1000u
18748 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_SHIFT 12
18749 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE_MASK  0x2000u
18750 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE_SHIFT 13
18751 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_MASK  0xC000u
18752 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_SHIFT 14
18753 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_MASK)
18754 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_MASK  0x10000u
18755 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_SHIFT 16
18756 /* SW_PAD_CTL_PAD_JTAG_TRST_B Bit Fields */
18757 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_MASK 0x1u
18758 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_SHIFT 0
18759 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK 0x38u
18760 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT 3
18761 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK)
18762 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_MASK 0xC0u
18763 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_SHIFT 6
18764 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_MASK)
18765 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_ODE_MASK 0x800u
18766 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_ODE_SHIFT 11
18767 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PKE_MASK 0x1000u
18768 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PKE_SHIFT 12
18769 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUE_MASK 0x2000u
18770 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUE_SHIFT 13
18771 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_MASK 0xC000u
18772 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_SHIFT 14
18773 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_MASK)
18774 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_MASK 0x10000u
18775 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_SHIFT 16
18776 /* SW_PAD_CTL_PAD_GPIO1_IO00 Bit Fields */
18777 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_MASK 0x1u
18778 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_SHIFT 0
18779 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK 0x38u
18780 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT 3
18781 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK)
18782 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_MASK 0xC0u
18783 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_SHIFT 6
18784 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_MASK)
18785 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_ODE_MASK 0x800u
18786 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_ODE_SHIFT 11
18787 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PKE_MASK 0x1000u
18788 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PKE_SHIFT 12
18789 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUE_MASK 0x2000u
18790 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUE_SHIFT 13
18791 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_MASK 0xC000u
18792 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_SHIFT 14
18793 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_MASK)
18794 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_MASK 0x10000u
18795 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_SHIFT 16
18796 /* SW_PAD_CTL_PAD_GPIO1_IO01 Bit Fields */
18797 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_MASK 0x1u
18798 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_SHIFT 0
18799 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK 0x38u
18800 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT 3
18801 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK)
18802 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_MASK 0xC0u
18803 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_SHIFT 6
18804 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_MASK)
18805 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_ODE_MASK 0x800u
18806 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_ODE_SHIFT 11
18807 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PKE_MASK 0x1000u
18808 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PKE_SHIFT 12
18809 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUE_MASK 0x2000u
18810 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUE_SHIFT 13
18811 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_MASK 0xC000u
18812 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_SHIFT 14
18813 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_MASK)
18814 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_MASK 0x10000u
18815 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_SHIFT 16
18816 /* SW_PAD_CTL_PAD_GPIO1_IO02 Bit Fields */
18817 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK 0x1u
18818 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_SHIFT 0
18819 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK 0x38u
18820 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT 3
18821 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK)
18822 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_MASK 0xC0u
18823 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_SHIFT 6
18824 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_MASK)
18825 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_MASK 0x800u
18826 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_SHIFT 11
18827 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_MASK 0x1000u
18828 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_SHIFT 12
18829 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_MASK 0x2000u
18830 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_SHIFT 13
18831 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_MASK 0xC000u
18832 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_SHIFT 14
18833 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_MASK)
18834 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK 0x10000u
18835 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_SHIFT 16
18836 /* SW_PAD_CTL_PAD_GPIO1_IO03 Bit Fields */
18837 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK 0x1u
18838 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_SHIFT 0
18839 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK 0x38u
18840 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT 3
18841 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK)
18842 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_MASK 0xC0u
18843 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_SHIFT 6
18844 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_MASK)
18845 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_MASK 0x800u
18846 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_SHIFT 11
18847 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_MASK 0x1000u
18848 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_SHIFT 12
18849 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_MASK 0x2000u
18850 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_SHIFT 13
18851 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_MASK 0xC000u
18852 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_SHIFT 14
18853 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_MASK)
18854 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK 0x10000u
18855 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_SHIFT 16
18856 /* SW_PAD_CTL_PAD_GPIO1_IO04 Bit Fields */
18857 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_MASK 0x1u
18858 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_SHIFT 0
18859 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK 0x38u
18860 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT 3
18861 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK)
18862 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_MASK 0xC0u
18863 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_SHIFT 6
18864 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_MASK)
18865 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_ODE_MASK 0x800u
18866 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_ODE_SHIFT 11
18867 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PKE_MASK 0x1000u
18868 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PKE_SHIFT 12
18869 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUE_MASK 0x2000u
18870 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUE_SHIFT 13
18871 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_MASK 0xC000u
18872 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_SHIFT 14
18873 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_MASK)
18874 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_MASK 0x10000u
18875 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_SHIFT 16
18876 /* SW_PAD_CTL_PAD_GPIO1_IO05 Bit Fields */
18877 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_MASK 0x1u
18878 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_SHIFT 0
18879 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK 0x38u
18880 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT 3
18881 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK)
18882 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_MASK 0xC0u
18883 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_SHIFT 6
18884 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_MASK)
18885 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_ODE_MASK 0x800u
18886 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_ODE_SHIFT 11
18887 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PKE_MASK 0x1000u
18888 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PKE_SHIFT 12
18889 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUE_MASK 0x2000u
18890 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUE_SHIFT 13
18891 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_MASK 0xC000u
18892 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_SHIFT 14
18893 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_MASK)
18894 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_MASK 0x10000u
18895 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_SHIFT 16
18896 /* SW_PAD_CTL_PAD_GPIO1_IO06 Bit Fields */
18897 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_MASK 0x1u
18898 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_SHIFT 0
18899 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK 0x38u
18900 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT 3
18901 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK)
18902 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_MASK 0xC0u
18903 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_SHIFT 6
18904 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_MASK)
18905 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_ODE_MASK 0x800u
18906 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_ODE_SHIFT 11
18907 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PKE_MASK 0x1000u
18908 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PKE_SHIFT 12
18909 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUE_MASK 0x2000u
18910 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUE_SHIFT 13
18911 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_MASK 0xC000u
18912 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_SHIFT 14
18913 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_MASK)
18914 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_MASK 0x10000u
18915 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_SHIFT 16
18916 /* SW_PAD_CTL_PAD_GPIO1_IO07 Bit Fields */
18917 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_MASK 0x1u
18918 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_SHIFT 0
18919 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK 0x38u
18920 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT 3
18921 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK)
18922 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_MASK 0xC0u
18923 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_SHIFT 6
18924 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_MASK)
18925 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_ODE_MASK 0x800u
18926 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_ODE_SHIFT 11
18927 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PKE_MASK 0x1000u
18928 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PKE_SHIFT 12
18929 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUE_MASK 0x2000u
18930 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUE_SHIFT 13
18931 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_MASK 0xC000u
18932 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_SHIFT 14
18933 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_MASK)
18934 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_MASK 0x10000u
18935 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_SHIFT 16
18936 /* SW_PAD_CTL_PAD_GPIO1_IO08 Bit Fields */
18937 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_MASK 0x1u
18938 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_SHIFT 0
18939 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK 0x38u
18940 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT 3
18941 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK)
18942 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_MASK 0xC0u
18943 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_SHIFT 6
18944 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_MASK)
18945 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_ODE_MASK 0x800u
18946 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_ODE_SHIFT 11
18947 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PKE_MASK 0x1000u
18948 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PKE_SHIFT 12
18949 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUE_MASK 0x2000u
18950 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUE_SHIFT 13
18951 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_MASK 0xC000u
18952 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_SHIFT 14
18953 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_MASK)
18954 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_MASK 0x10000u
18955 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_SHIFT 16
18956 /* SW_PAD_CTL_PAD_GPIO1_IO09 Bit Fields */
18957 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_MASK 0x1u
18958 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_SHIFT 0
18959 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK 0x38u
18960 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT 3
18961 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK)
18962 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_MASK 0xC0u
18963 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_SHIFT 6
18964 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_MASK)
18965 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_ODE_MASK 0x800u
18966 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_ODE_SHIFT 11
18967 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PKE_MASK 0x1000u
18968 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PKE_SHIFT 12
18969 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUE_MASK 0x2000u
18970 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUE_SHIFT 13
18971 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_MASK 0xC000u
18972 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_SHIFT 14
18973 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_MASK)
18974 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_MASK 0x10000u
18975 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_SHIFT 16
18976 /* SW_PAD_CTL_PAD_GPIO1_IO10 Bit Fields */
18977 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_MASK 0x1u
18978 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_SHIFT 0
18979 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK 0x38u
18980 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT 3
18981 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK)
18982 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_MASK 0xC0u
18983 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_SHIFT 6
18984 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_MASK)
18985 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_ODE_MASK 0x800u
18986 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_ODE_SHIFT 11
18987 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PKE_MASK 0x1000u
18988 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PKE_SHIFT 12
18989 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUE_MASK 0x2000u
18990 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUE_SHIFT 13
18991 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_MASK 0xC000u
18992 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_SHIFT 14
18993 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_MASK)
18994 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_MASK 0x10000u
18995 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_SHIFT 16
18996 /* SW_PAD_CTL_PAD_GPIO1_IO11 Bit Fields */
18997 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_MASK 0x1u
18998 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_SHIFT 0
18999 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK 0x38u
19000 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT 3
19001 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK)
19002 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_MASK 0xC0u
19003 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_SHIFT 6
19004 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_MASK)
19005 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_ODE_MASK 0x800u
19006 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_ODE_SHIFT 11
19007 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PKE_MASK 0x1000u
19008 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PKE_SHIFT 12
19009 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUE_MASK 0x2000u
19010 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUE_SHIFT 13
19011 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_MASK 0xC000u
19012 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_SHIFT 14
19013 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_MASK)
19014 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_MASK 0x10000u
19015 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_SHIFT 16
19016 /* SW_PAD_CTL_PAD_GPIO1_IO12 Bit Fields */
19017 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_MASK 0x1u
19018 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_SHIFT 0
19019 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK 0x38u
19020 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT 3
19021 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK)
19022 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_MASK 0xC0u
19023 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_SHIFT 6
19024 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_MASK)
19025 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_ODE_MASK 0x800u
19026 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_ODE_SHIFT 11
19027 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PKE_MASK 0x1000u
19028 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PKE_SHIFT 12
19029 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUE_MASK 0x2000u
19030 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUE_SHIFT 13
19031 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_MASK 0xC000u
19032 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_SHIFT 14
19033 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_MASK)
19034 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_MASK 0x10000u
19035 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_SHIFT 16
19036 /* SW_PAD_CTL_PAD_GPIO1_IO13 Bit Fields */
19037 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_MASK 0x1u
19038 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_SHIFT 0
19039 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK 0x38u
19040 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT 3
19041 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK)
19042 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_MASK 0xC0u
19043 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_SHIFT 6
19044 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_MASK)
19045 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_ODE_MASK 0x800u
19046 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_ODE_SHIFT 11
19047 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PKE_MASK 0x1000u
19048 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PKE_SHIFT 12
19049 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUE_MASK 0x2000u
19050 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUE_SHIFT 13
19051 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_MASK 0xC000u
19052 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_SHIFT 14
19053 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_MASK)
19054 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_MASK 0x10000u
19055 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_SHIFT 16
19056 /* SW_PAD_CTL_PAD_CSI_DATA00 Bit Fields */
19057 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SRE_MASK 0x1u
19058 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SRE_SHIFT 0
19059 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_MASK 0x38u
19060 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_SHIFT 3
19061 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_MASK)
19062 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_MASK 0xC0u
19063 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_SHIFT 6
19064 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_MASK)
19065 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_ODE_MASK 0x800u
19066 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_ODE_SHIFT 11
19067 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PKE_MASK 0x1000u
19068 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PKE_SHIFT 12
19069 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUE_MASK 0x2000u
19070 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUE_SHIFT 13
19071 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_MASK 0xC000u
19072 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_SHIFT 14
19073 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_MASK)
19074 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_HYS_MASK 0x10000u
19075 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_HYS_SHIFT 16
19076 /* SW_PAD_CTL_PAD_CSI_DATA01 Bit Fields */
19077 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SRE_MASK 0x1u
19078 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SRE_SHIFT 0
19079 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_MASK 0x38u
19080 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_SHIFT 3
19081 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_MASK)
19082 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_MASK 0xC0u
19083 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_SHIFT 6
19084 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_MASK)
19085 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_ODE_MASK 0x800u
19086 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_ODE_SHIFT 11
19087 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PKE_MASK 0x1000u
19088 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PKE_SHIFT 12
19089 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUE_MASK 0x2000u
19090 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUE_SHIFT 13
19091 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_MASK 0xC000u
19092 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_SHIFT 14
19093 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_MASK)
19094 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_HYS_MASK 0x10000u
19095 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_HYS_SHIFT 16
19096 /* SW_PAD_CTL_PAD_CSI_DATA02 Bit Fields */
19097 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SRE_MASK 0x1u
19098 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SRE_SHIFT 0
19099 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_MASK 0x38u
19100 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_SHIFT 3
19101 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_MASK)
19102 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_MASK 0xC0u
19103 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_SHIFT 6
19104 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_MASK)
19105 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_ODE_MASK 0x800u
19106 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_ODE_SHIFT 11
19107 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PKE_MASK 0x1000u
19108 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PKE_SHIFT 12
19109 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUE_MASK 0x2000u
19110 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUE_SHIFT 13
19111 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_MASK 0xC000u
19112 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_SHIFT 14
19113 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_MASK)
19114 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_HYS_MASK 0x10000u
19115 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_HYS_SHIFT 16
19116 /* SW_PAD_CTL_PAD_CSI_DATA03 Bit Fields */
19117 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SRE_MASK 0x1u
19118 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SRE_SHIFT 0
19119 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_MASK 0x38u
19120 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_SHIFT 3
19121 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_MASK)
19122 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_MASK 0xC0u
19123 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_SHIFT 6
19124 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_MASK)
19125 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_ODE_MASK 0x800u
19126 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_ODE_SHIFT 11
19127 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PKE_MASK 0x1000u
19128 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PKE_SHIFT 12
19129 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUE_MASK 0x2000u
19130 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUE_SHIFT 13
19131 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_MASK 0xC000u
19132 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_SHIFT 14
19133 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_MASK)
19134 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_HYS_MASK 0x10000u
19135 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_HYS_SHIFT 16
19136 /* SW_PAD_CTL_PAD_CSI_DATA04 Bit Fields */
19137 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SRE_MASK 0x1u
19138 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SRE_SHIFT 0
19139 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_MASK 0x38u
19140 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_SHIFT 3
19141 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_MASK)
19142 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_MASK 0xC0u
19143 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_SHIFT 6
19144 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_MASK)
19145 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_ODE_MASK 0x800u
19146 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_ODE_SHIFT 11
19147 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PKE_MASK 0x1000u
19148 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PKE_SHIFT 12
19149 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUE_MASK 0x2000u
19150 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUE_SHIFT 13
19151 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_MASK 0xC000u
19152 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_SHIFT 14
19153 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_MASK)
19154 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_HYS_MASK 0x10000u
19155 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_HYS_SHIFT 16
19156 /* SW_PAD_CTL_PAD_CSI_DATA05 Bit Fields */
19157 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SRE_MASK 0x1u
19158 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SRE_SHIFT 0
19159 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_MASK 0x38u
19160 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_SHIFT 3
19161 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_MASK)
19162 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_MASK 0xC0u
19163 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_SHIFT 6
19164 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_MASK)
19165 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_ODE_MASK 0x800u
19166 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_ODE_SHIFT 11
19167 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PKE_MASK 0x1000u
19168 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PKE_SHIFT 12
19169 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUE_MASK 0x2000u
19170 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUE_SHIFT 13
19171 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_MASK 0xC000u
19172 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_SHIFT 14
19173 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_MASK)
19174 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_HYS_MASK 0x10000u
19175 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_HYS_SHIFT 16
19176 /* SW_PAD_CTL_PAD_CSI_DATA06 Bit Fields */
19177 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SRE_MASK 0x1u
19178 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SRE_SHIFT 0
19179 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_MASK 0x38u
19180 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_SHIFT 3
19181 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_MASK)
19182 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_MASK 0xC0u
19183 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_SHIFT 6
19184 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_MASK)
19185 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_ODE_MASK 0x800u
19186 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_ODE_SHIFT 11
19187 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PKE_MASK 0x1000u
19188 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PKE_SHIFT 12
19189 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUE_MASK 0x2000u
19190 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUE_SHIFT 13
19191 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_MASK 0xC000u
19192 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_SHIFT 14
19193 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_MASK)
19194 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_HYS_MASK 0x10000u
19195 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_HYS_SHIFT 16
19196 /* SW_PAD_CTL_PAD_CSI_DATA07 Bit Fields */
19197 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SRE_MASK 0x1u
19198 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SRE_SHIFT 0
19199 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_MASK 0x38u
19200 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_SHIFT 3
19201 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_MASK)
19202 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_MASK 0xC0u
19203 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_SHIFT 6
19204 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_MASK)
19205 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_ODE_MASK 0x800u
19206 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_ODE_SHIFT 11
19207 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PKE_MASK 0x1000u
19208 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PKE_SHIFT 12
19209 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUE_MASK 0x2000u
19210 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUE_SHIFT 13
19211 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_MASK 0xC000u
19212 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_SHIFT 14
19213 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_MASK)
19214 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_HYS_MASK 0x10000u
19215 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_HYS_SHIFT 16
19216 /* SW_PAD_CTL_PAD_CSI_HSYNC Bit Fields */
19217 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SRE_MASK 0x1u
19218 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SRE_SHIFT 0
19219 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_MASK 0x38u
19220 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_SHIFT 3
19221 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_MASK)
19222 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_MASK 0xC0u
19223 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_SHIFT 6
19224 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_MASK)
19225 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_ODE_MASK 0x800u
19226 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_ODE_SHIFT 11
19227 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PKE_MASK 0x1000u
19228 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PKE_SHIFT 12
19229 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUE_MASK 0x2000u
19230 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUE_SHIFT 13
19231 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_MASK 0xC000u
19232 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_SHIFT 14
19233 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_MASK)
19234 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_HYS_MASK 0x10000u
19235 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_HYS_SHIFT 16
19236 /* SW_PAD_CTL_PAD_CSI_MCLK Bit Fields */
19237 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SRE_MASK  0x1u
19238 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SRE_SHIFT 0
19239 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_MASK  0x38u
19240 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_SHIFT 3
19241 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_MASK)
19242 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_MASK 0xC0u
19243 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_SHIFT 6
19244 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_MASK)
19245 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_ODE_MASK  0x800u
19246 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_ODE_SHIFT 11
19247 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PKE_MASK  0x1000u
19248 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PKE_SHIFT 12
19249 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUE_MASK  0x2000u
19250 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUE_SHIFT 13
19251 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_MASK  0xC000u
19252 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_SHIFT 14
19253 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_MASK)
19254 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_HYS_MASK  0x10000u
19255 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_HYS_SHIFT 16
19256 /* SW_PAD_CTL_PAD_CSI_PIXCLK Bit Fields */
19257 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SRE_MASK 0x1u
19258 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SRE_SHIFT 0
19259 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_MASK 0x38u
19260 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_SHIFT 3
19261 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_MASK)
19262 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_MASK 0xC0u
19263 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_SHIFT 6
19264 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_MASK)
19265 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_ODE_MASK 0x800u
19266 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_ODE_SHIFT 11
19267 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PKE_MASK 0x1000u
19268 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PKE_SHIFT 12
19269 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUE_MASK 0x2000u
19270 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUE_SHIFT 13
19271 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_MASK 0xC000u
19272 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_SHIFT 14
19273 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_MASK)
19274 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_HYS_MASK 0x10000u
19275 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_HYS_SHIFT 16
19276 /* SW_PAD_CTL_PAD_CSI_VSYNC Bit Fields */
19277 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SRE_MASK 0x1u
19278 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SRE_SHIFT 0
19279 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_MASK 0x38u
19280 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_SHIFT 3
19281 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_MASK)
19282 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_MASK 0xC0u
19283 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_SHIFT 6
19284 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_MASK)
19285 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_ODE_MASK 0x800u
19286 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_ODE_SHIFT 11
19287 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PKE_MASK 0x1000u
19288 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PKE_SHIFT 12
19289 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUE_MASK 0x2000u
19290 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUE_SHIFT 13
19291 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_MASK 0xC000u
19292 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_SHIFT 14
19293 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_MASK)
19294 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_HYS_MASK 0x10000u
19295 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_HYS_SHIFT 16
19296 /* SW_PAD_CTL_PAD_ENET1_COL Bit Fields */
19297 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_MASK 0x1u
19298 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_SHIFT 0
19299 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK 0x38u
19300 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT 3
19301 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK)
19302 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_MASK 0xC0u
19303 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_SHIFT 6
19304 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_MASK)
19305 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_ODE_MASK 0x800u
19306 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_ODE_SHIFT 11
19307 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PKE_MASK 0x1000u
19308 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PKE_SHIFT 12
19309 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUE_MASK 0x2000u
19310 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUE_SHIFT 13
19311 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_MASK 0xC000u
19312 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_SHIFT 14
19313 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_MASK)
19314 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_MASK 0x10000u
19315 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_SHIFT 16
19316 /* SW_PAD_CTL_PAD_ENET1_CRS Bit Fields */
19317 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_MASK 0x1u
19318 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_SHIFT 0
19319 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK 0x38u
19320 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT 3
19321 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK)
19322 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_MASK 0xC0u
19323 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_SHIFT 6
19324 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_MASK)
19325 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_ODE_MASK 0x800u
19326 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_ODE_SHIFT 11
19327 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PKE_MASK 0x1000u
19328 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PKE_SHIFT 12
19329 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUE_MASK 0x2000u
19330 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUE_SHIFT 13
19331 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_MASK 0xC000u
19332 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_SHIFT 14
19333 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_MASK)
19334 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_MASK 0x10000u
19335 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_SHIFT 16
19336 /* SW_PAD_CTL_PAD_ENET1_MDC Bit Fields */
19337 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SRE_MASK 0x1u
19338 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SRE_SHIFT 0
19339 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_MASK 0x38u
19340 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_SHIFT 3
19341 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_MASK)
19342 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_MASK 0xC0u
19343 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_SHIFT 6
19344 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_MASK)
19345 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_ODE_MASK 0x800u
19346 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_ODE_SHIFT 11
19347 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PKE_MASK 0x1000u
19348 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PKE_SHIFT 12
19349 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUE_MASK 0x2000u
19350 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUE_SHIFT 13
19351 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_MASK 0xC000u
19352 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_SHIFT 14
19353 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_MASK)
19354 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_HYS_MASK 0x10000u
19355 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_HYS_SHIFT 16
19356 /* SW_PAD_CTL_PAD_ENET1_MDIO Bit Fields */
19357 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SRE_MASK 0x1u
19358 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SRE_SHIFT 0
19359 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_MASK 0x38u
19360 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_SHIFT 3
19361 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_MASK)
19362 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_MASK 0xC0u
19363 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_SHIFT 6
19364 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_MASK)
19365 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_ODE_MASK 0x800u
19366 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_ODE_SHIFT 11
19367 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PKE_MASK 0x1000u
19368 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PKE_SHIFT 12
19369 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUE_MASK 0x2000u
19370 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUE_SHIFT 13
19371 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_MASK 0xC000u
19372 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_SHIFT 14
19373 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_MASK)
19374 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_HYS_MASK 0x10000u
19375 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_HYS_SHIFT 16
19376 /* SW_PAD_CTL_PAD_ENET1_RX_CLK Bit Fields */
19377 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_MASK 0x1u
19378 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_SHIFT 0
19379 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK 0x38u
19380 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT 3
19381 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK)
19382 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_MASK 0xC0u
19383 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_SHIFT 6
19384 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_MASK)
19385 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_ODE_MASK 0x800u
19386 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_ODE_SHIFT 11
19387 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PKE_MASK 0x1000u
19388 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PKE_SHIFT 12
19389 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUE_MASK 0x2000u
19390 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUE_SHIFT 13
19391 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_MASK 0xC000u
19392 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_SHIFT 14
19393 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_MASK)
19394 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_MASK 0x10000u
19395 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_SHIFT 16
19396 /* SW_PAD_CTL_PAD_ENET1_TX_CLK Bit Fields */
19397 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_MASK 0x1u
19398 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_SHIFT 0
19399 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK 0x38u
19400 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT 3
19401 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK)
19402 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_MASK 0xC0u
19403 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_SHIFT 6
19404 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_MASK)
19405 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_ODE_MASK 0x800u
19406 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_ODE_SHIFT 11
19407 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PKE_MASK 0x1000u
19408 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PKE_SHIFT 12
19409 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUE_MASK 0x2000u
19410 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUE_SHIFT 13
19411 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_MASK 0xC000u
19412 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_SHIFT 14
19413 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_MASK)
19414 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_MASK 0x10000u
19415 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_SHIFT 16
19416 /* SW_PAD_CTL_PAD_ENET2_COL Bit Fields */
19417 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SRE_MASK 0x1u
19418 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SRE_SHIFT 0
19419 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_MASK 0x38u
19420 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_SHIFT 3
19421 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_MASK)
19422 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_MASK 0xC0u
19423 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_SHIFT 6
19424 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_MASK)
19425 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_ODE_MASK 0x800u
19426 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_ODE_SHIFT 11
19427 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PKE_MASK 0x1000u
19428 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PKE_SHIFT 12
19429 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUE_MASK 0x2000u
19430 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUE_SHIFT 13
19431 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_MASK 0xC000u
19432 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_SHIFT 14
19433 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_MASK)
19434 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_HYS_MASK 0x10000u
19435 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_HYS_SHIFT 16
19436 /* SW_PAD_CTL_PAD_ENET2_CRS Bit Fields */
19437 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SRE_MASK 0x1u
19438 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SRE_SHIFT 0
19439 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_MASK 0x38u
19440 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_SHIFT 3
19441 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_MASK)
19442 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_MASK 0xC0u
19443 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_SHIFT 6
19444 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_MASK)
19445 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_ODE_MASK 0x800u
19446 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_ODE_SHIFT 11
19447 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PKE_MASK 0x1000u
19448 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PKE_SHIFT 12
19449 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUE_MASK 0x2000u
19450 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUE_SHIFT 13
19451 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_MASK 0xC000u
19452 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_SHIFT 14
19453 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_MASK)
19454 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_HYS_MASK 0x10000u
19455 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_HYS_SHIFT 16
19456 /* SW_PAD_CTL_PAD_ENET2_RX_CLK Bit Fields */
19457 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SRE_MASK 0x1u
19458 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SRE_SHIFT 0
19459 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_MASK 0x38u
19460 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_SHIFT 3
19461 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_MASK)
19462 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_MASK 0xC0u
19463 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_SHIFT 6
19464 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_MASK)
19465 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_ODE_MASK 0x800u
19466 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_ODE_SHIFT 11
19467 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PKE_MASK 0x1000u
19468 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PKE_SHIFT 12
19469 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUE_MASK 0x2000u
19470 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUE_SHIFT 13
19471 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_MASK 0xC000u
19472 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_SHIFT 14
19473 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_MASK)
19474 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_HYS_MASK 0x10000u
19475 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_HYS_SHIFT 16
19476 /* SW_PAD_CTL_PAD_ENET2_TX_CLK Bit Fields */
19477 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SRE_MASK 0x1u
19478 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SRE_SHIFT 0
19479 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_MASK 0x38u
19480 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_SHIFT 3
19481 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_MASK)
19482 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_MASK 0xC0u
19483 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_SHIFT 6
19484 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_MASK)
19485 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_ODE_MASK 0x800u
19486 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_ODE_SHIFT 11
19487 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PKE_MASK 0x1000u
19488 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PKE_SHIFT 12
19489 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUE_MASK 0x2000u
19490 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUE_SHIFT 13
19491 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_MASK 0xC000u
19492 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_SHIFT 14
19493 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_MASK)
19494 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_HYS_MASK 0x10000u
19495 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_HYS_SHIFT 16
19496 /* SW_PAD_CTL_PAD_KEY_COL0 Bit Fields */
19497 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_MASK  0x1u
19498 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_SHIFT 0
19499 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_MASK  0x38u
19500 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_SHIFT 3
19501 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_MASK)
19502 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_MASK 0xC0u
19503 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_SHIFT 6
19504 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_MASK)
19505 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_MASK  0x800u
19506 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_SHIFT 11
19507 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_MASK  0x1000u
19508 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_SHIFT 12
19509 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_MASK  0x2000u
19510 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_SHIFT 13
19511 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_MASK  0xC000u
19512 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_SHIFT 14
19513 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_MASK)
19514 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_MASK  0x10000u
19515 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_SHIFT 16
19516 /* SW_PAD_CTL_PAD_KEY_COL1 Bit Fields */
19517 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_MASK  0x1u
19518 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_SHIFT 0
19519 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_MASK  0x38u
19520 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_SHIFT 3
19521 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_MASK)
19522 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_MASK 0xC0u
19523 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_SHIFT 6
19524 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_MASK)
19525 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_MASK  0x800u
19526 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_SHIFT 11
19527 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_MASK  0x1000u
19528 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_SHIFT 12
19529 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_MASK  0x2000u
19530 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_SHIFT 13
19531 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_MASK  0xC000u
19532 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_SHIFT 14
19533 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_MASK)
19534 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_MASK  0x10000u
19535 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_SHIFT 16
19536 /* SW_PAD_CTL_PAD_KEY_COL2 Bit Fields */
19537 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_MASK  0x1u
19538 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_SHIFT 0
19539 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_MASK  0x38u
19540 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_SHIFT 3
19541 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_MASK)
19542 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_MASK 0xC0u
19543 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_SHIFT 6
19544 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_MASK)
19545 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_MASK  0x800u
19546 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_SHIFT 11
19547 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_MASK  0x1000u
19548 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_SHIFT 12
19549 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_MASK  0x2000u
19550 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_SHIFT 13
19551 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_MASK  0xC000u
19552 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_SHIFT 14
19553 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_MASK)
19554 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_MASK  0x10000u
19555 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_SHIFT 16
19556 /* SW_PAD_CTL_PAD_KEY_COL3 Bit Fields */
19557 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_MASK  0x1u
19558 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_SHIFT 0
19559 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_MASK  0x38u
19560 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_SHIFT 3
19561 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_MASK)
19562 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_MASK 0xC0u
19563 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_SHIFT 6
19564 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_MASK)
19565 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_MASK  0x800u
19566 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_SHIFT 11
19567 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_MASK  0x1000u
19568 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_SHIFT 12
19569 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_MASK  0x2000u
19570 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_SHIFT 13
19571 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_MASK  0xC000u
19572 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_SHIFT 14
19573 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_MASK)
19574 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_MASK  0x10000u
19575 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_SHIFT 16
19576 /* SW_PAD_CTL_PAD_KEY_COL4 Bit Fields */
19577 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_MASK  0x1u
19578 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_SHIFT 0
19579 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_MASK  0x38u
19580 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_SHIFT 3
19581 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_MASK)
19582 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_MASK 0xC0u
19583 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_SHIFT 6
19584 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_MASK)
19585 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_MASK  0x800u
19586 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_SHIFT 11
19587 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_MASK  0x1000u
19588 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_SHIFT 12
19589 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_MASK  0x2000u
19590 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_SHIFT 13
19591 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_MASK  0xC000u
19592 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_SHIFT 14
19593 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_MASK)
19594 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_MASK  0x10000u
19595 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_SHIFT 16
19596 /* SW_PAD_CTL_PAD_KEY_ROW0 Bit Fields */
19597 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_MASK  0x1u
19598 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_SHIFT 0
19599 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_MASK  0x38u
19600 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_SHIFT 3
19601 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_MASK)
19602 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_MASK 0xC0u
19603 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_SHIFT 6
19604 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_MASK)
19605 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_MASK  0x800u
19606 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_SHIFT 11
19607 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_MASK  0x1000u
19608 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_SHIFT 12
19609 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_MASK  0x2000u
19610 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_SHIFT 13
19611 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_MASK  0xC000u
19612 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_SHIFT 14
19613 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_MASK)
19614 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_MASK  0x10000u
19615 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_SHIFT 16
19616 /* SW_PAD_CTL_PAD_KEY_ROW1 Bit Fields */
19617 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_MASK  0x1u
19618 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_SHIFT 0
19619 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_MASK  0x38u
19620 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_SHIFT 3
19621 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_MASK)
19622 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_MASK 0xC0u
19623 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_SHIFT 6
19624 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_MASK)
19625 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_MASK  0x800u
19626 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_SHIFT 11
19627 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_MASK  0x1000u
19628 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_SHIFT 12
19629 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_MASK  0x2000u
19630 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_SHIFT 13
19631 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_MASK  0xC000u
19632 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_SHIFT 14
19633 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_MASK)
19634 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_MASK  0x10000u
19635 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_SHIFT 16
19636 /* SW_PAD_CTL_PAD_KEY_ROW2 Bit Fields */
19637 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_MASK  0x1u
19638 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_SHIFT 0
19639 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_MASK  0x38u
19640 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_SHIFT 3
19641 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_MASK)
19642 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_MASK 0xC0u
19643 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_SHIFT 6
19644 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_MASK)
19645 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_MASK  0x800u
19646 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_SHIFT 11
19647 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_MASK  0x1000u
19648 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_SHIFT 12
19649 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_MASK  0x2000u
19650 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_SHIFT 13
19651 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_MASK  0xC000u
19652 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_SHIFT 14
19653 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_MASK)
19654 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_MASK  0x10000u
19655 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_SHIFT 16
19656 /* SW_PAD_CTL_PAD_KEY_ROW3 Bit Fields */
19657 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_MASK  0x1u
19658 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_SHIFT 0
19659 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_MASK  0x38u
19660 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_SHIFT 3
19661 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_MASK)
19662 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_MASK 0xC0u
19663 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_SHIFT 6
19664 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_MASK)
19665 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_MASK  0x800u
19666 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_SHIFT 11
19667 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_MASK  0x1000u
19668 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_SHIFT 12
19669 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_MASK  0x2000u
19670 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_SHIFT 13
19671 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_MASK  0xC000u
19672 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_SHIFT 14
19673 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_MASK)
19674 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_MASK  0x10000u
19675 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_SHIFT 16
19676 /* SW_PAD_CTL_PAD_KEY_ROW4 Bit Fields */
19677 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_MASK  0x1u
19678 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_SHIFT 0
19679 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_MASK  0x38u
19680 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_SHIFT 3
19681 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_MASK)
19682 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_MASK 0xC0u
19683 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_SHIFT 6
19684 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_MASK)
19685 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_MASK  0x800u
19686 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_SHIFT 11
19687 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_MASK  0x1000u
19688 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_SHIFT 12
19689 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_MASK  0x2000u
19690 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_SHIFT 13
19691 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_MASK  0xC000u
19692 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_SHIFT 14
19693 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_MASK)
19694 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_MASK  0x10000u
19695 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_SHIFT 16
19696 /* SW_PAD_CTL_PAD_LCD1_CLK Bit Fields */
19697 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SRE_MASK  0x1u
19698 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SRE_SHIFT 0
19699 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_MASK  0x38u
19700 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_SHIFT 3
19701 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_MASK)
19702 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_MASK 0xC0u
19703 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_SHIFT 6
19704 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_MASK)
19705 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_ODE_MASK  0x800u
19706 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_ODE_SHIFT 11
19707 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PKE_MASK  0x1000u
19708 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PKE_SHIFT 12
19709 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUE_MASK  0x2000u
19710 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUE_SHIFT 13
19711 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_MASK  0xC000u
19712 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_SHIFT 14
19713 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_MASK)
19714 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_HYS_MASK  0x10000u
19715 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_HYS_SHIFT 16
19716 /* SW_PAD_CTL_PAD_LCD1_DATA00 Bit Fields */
19717 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SRE_MASK 0x1u
19718 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SRE_SHIFT 0
19719 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_MASK 0x38u
19720 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_SHIFT 3
19721 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_MASK)
19722 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_MASK 0xC0u
19723 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_SHIFT 6
19724 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_MASK)
19725 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_ODE_MASK 0x800u
19726 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_ODE_SHIFT 11
19727 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PKE_MASK 0x1000u
19728 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PKE_SHIFT 12
19729 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUE_MASK 0x2000u
19730 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUE_SHIFT 13
19731 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_MASK 0xC000u
19732 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_SHIFT 14
19733 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_MASK)
19734 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_HYS_MASK 0x10000u
19735 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_HYS_SHIFT 16
19736 /* SW_PAD_CTL_PAD_LCD1_DATA01 Bit Fields */
19737 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SRE_MASK 0x1u
19738 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SRE_SHIFT 0
19739 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_MASK 0x38u
19740 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_SHIFT 3
19741 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_MASK)
19742 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_MASK 0xC0u
19743 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_SHIFT 6
19744 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_MASK)
19745 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_ODE_MASK 0x800u
19746 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_ODE_SHIFT 11
19747 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PKE_MASK 0x1000u
19748 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PKE_SHIFT 12
19749 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUE_MASK 0x2000u
19750 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUE_SHIFT 13
19751 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_MASK 0xC000u
19752 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_SHIFT 14
19753 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_MASK)
19754 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_HYS_MASK 0x10000u
19755 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_HYS_SHIFT 16
19756 /* SW_PAD_CTL_PAD_LCD1_DATA02 Bit Fields */
19757 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SRE_MASK 0x1u
19758 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SRE_SHIFT 0
19759 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_MASK 0x38u
19760 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_SHIFT 3
19761 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_MASK)
19762 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_MASK 0xC0u
19763 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_SHIFT 6
19764 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_MASK)
19765 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_ODE_MASK 0x800u
19766 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_ODE_SHIFT 11
19767 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PKE_MASK 0x1000u
19768 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PKE_SHIFT 12
19769 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUE_MASK 0x2000u
19770 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUE_SHIFT 13
19771 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_MASK 0xC000u
19772 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_SHIFT 14
19773 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_MASK)
19774 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_HYS_MASK 0x10000u
19775 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_HYS_SHIFT 16
19776 /* SW_PAD_CTL_PAD_LCD1_DATA03 Bit Fields */
19777 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SRE_MASK 0x1u
19778 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SRE_SHIFT 0
19779 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_MASK 0x38u
19780 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_SHIFT 3
19781 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_MASK)
19782 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_MASK 0xC0u
19783 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_SHIFT 6
19784 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_MASK)
19785 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_ODE_MASK 0x800u
19786 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_ODE_SHIFT 11
19787 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PKE_MASK 0x1000u
19788 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PKE_SHIFT 12
19789 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUE_MASK 0x2000u
19790 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUE_SHIFT 13
19791 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_MASK 0xC000u
19792 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_SHIFT 14
19793 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_MASK)
19794 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_HYS_MASK 0x10000u
19795 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_HYS_SHIFT 16
19796 /* SW_PAD_CTL_PAD_LCD1_DATA04 Bit Fields */
19797 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SRE_MASK 0x1u
19798 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SRE_SHIFT 0
19799 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_MASK 0x38u
19800 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_SHIFT 3
19801 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_MASK)
19802 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_MASK 0xC0u
19803 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_SHIFT 6
19804 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_MASK)
19805 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_ODE_MASK 0x800u
19806 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_ODE_SHIFT 11
19807 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PKE_MASK 0x1000u
19808 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PKE_SHIFT 12
19809 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUE_MASK 0x2000u
19810 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUE_SHIFT 13
19811 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_MASK 0xC000u
19812 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_SHIFT 14
19813 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_MASK)
19814 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_HYS_MASK 0x10000u
19815 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_HYS_SHIFT 16
19816 /* SW_PAD_CTL_PAD_LCD1_DATA05 Bit Fields */
19817 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SRE_MASK 0x1u
19818 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SRE_SHIFT 0
19819 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_MASK 0x38u
19820 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_SHIFT 3
19821 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_MASK)
19822 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_MASK 0xC0u
19823 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_SHIFT 6
19824 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_MASK)
19825 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_ODE_MASK 0x800u
19826 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_ODE_SHIFT 11
19827 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PKE_MASK 0x1000u
19828 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PKE_SHIFT 12
19829 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUE_MASK 0x2000u
19830 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUE_SHIFT 13
19831 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_MASK 0xC000u
19832 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_SHIFT 14
19833 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_MASK)
19834 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_HYS_MASK 0x10000u
19835 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_HYS_SHIFT 16
19836 /* SW_PAD_CTL_PAD_LCD1_DATA06 Bit Fields */
19837 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SRE_MASK 0x1u
19838 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SRE_SHIFT 0
19839 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_MASK 0x38u
19840 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_SHIFT 3
19841 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_MASK)
19842 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_MASK 0xC0u
19843 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_SHIFT 6
19844 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_MASK)
19845 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_ODE_MASK 0x800u
19846 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_ODE_SHIFT 11
19847 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PKE_MASK 0x1000u
19848 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PKE_SHIFT 12
19849 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUE_MASK 0x2000u
19850 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUE_SHIFT 13
19851 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_MASK 0xC000u
19852 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_SHIFT 14
19853 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_MASK)
19854 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_HYS_MASK 0x10000u
19855 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_HYS_SHIFT 16
19856 /* SW_PAD_CTL_PAD_LCD1_DATA07 Bit Fields */
19857 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SRE_MASK 0x1u
19858 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SRE_SHIFT 0
19859 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_MASK 0x38u
19860 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_SHIFT 3
19861 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_MASK)
19862 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_MASK 0xC0u
19863 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_SHIFT 6
19864 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_MASK)
19865 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_ODE_MASK 0x800u
19866 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_ODE_SHIFT 11
19867 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PKE_MASK 0x1000u
19868 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PKE_SHIFT 12
19869 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUE_MASK 0x2000u
19870 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUE_SHIFT 13
19871 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_MASK 0xC000u
19872 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_SHIFT 14
19873 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_MASK)
19874 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_HYS_MASK 0x10000u
19875 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_HYS_SHIFT 16
19876 /* SW_PAD_CTL_PAD_LCD1_DATA08 Bit Fields */
19877 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SRE_MASK 0x1u
19878 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SRE_SHIFT 0
19879 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_MASK 0x38u
19880 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_SHIFT 3
19881 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_MASK)
19882 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_MASK 0xC0u
19883 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_SHIFT 6
19884 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_MASK)
19885 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_ODE_MASK 0x800u
19886 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_ODE_SHIFT 11
19887 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PKE_MASK 0x1000u
19888 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PKE_SHIFT 12
19889 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUE_MASK 0x2000u
19890 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUE_SHIFT 13
19891 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_MASK 0xC000u
19892 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_SHIFT 14
19893 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_MASK)
19894 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_HYS_MASK 0x10000u
19895 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_HYS_SHIFT 16
19896 /* SW_PAD_CTL_PAD_LCD1_DATA09 Bit Fields */
19897 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SRE_MASK 0x1u
19898 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SRE_SHIFT 0
19899 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_MASK 0x38u
19900 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_SHIFT 3
19901 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_MASK)
19902 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_MASK 0xC0u
19903 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_SHIFT 6
19904 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_MASK)
19905 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_ODE_MASK 0x800u
19906 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_ODE_SHIFT 11
19907 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PKE_MASK 0x1000u
19908 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PKE_SHIFT 12
19909 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUE_MASK 0x2000u
19910 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUE_SHIFT 13
19911 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_MASK 0xC000u
19912 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_SHIFT 14
19913 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_MASK)
19914 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_HYS_MASK 0x10000u
19915 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_HYS_SHIFT 16
19916 /* SW_PAD_CTL_PAD_LCD1_DATA10 Bit Fields */
19917 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SRE_MASK 0x1u
19918 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SRE_SHIFT 0
19919 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_MASK 0x38u
19920 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_SHIFT 3
19921 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_MASK)
19922 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_MASK 0xC0u
19923 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_SHIFT 6
19924 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_MASK)
19925 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_ODE_MASK 0x800u
19926 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_ODE_SHIFT 11
19927 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PKE_MASK 0x1000u
19928 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PKE_SHIFT 12
19929 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUE_MASK 0x2000u
19930 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUE_SHIFT 13
19931 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_MASK 0xC000u
19932 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_SHIFT 14
19933 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_MASK)
19934 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_HYS_MASK 0x10000u
19935 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_HYS_SHIFT 16
19936 /* SW_PAD_CTL_PAD_LCD1_DATA11 Bit Fields */
19937 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SRE_MASK 0x1u
19938 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SRE_SHIFT 0
19939 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_MASK 0x38u
19940 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_SHIFT 3
19941 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_MASK)
19942 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_MASK 0xC0u
19943 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_SHIFT 6
19944 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_MASK)
19945 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_ODE_MASK 0x800u
19946 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_ODE_SHIFT 11
19947 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PKE_MASK 0x1000u
19948 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PKE_SHIFT 12
19949 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUE_MASK 0x2000u
19950 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUE_SHIFT 13
19951 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_MASK 0xC000u
19952 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_SHIFT 14
19953 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_MASK)
19954 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_HYS_MASK 0x10000u
19955 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_HYS_SHIFT 16
19956 /* SW_PAD_CTL_PAD_LCD1_DATA12 Bit Fields */
19957 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SRE_MASK 0x1u
19958 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SRE_SHIFT 0
19959 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_MASK 0x38u
19960 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_SHIFT 3
19961 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_MASK)
19962 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_MASK 0xC0u
19963 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_SHIFT 6
19964 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_MASK)
19965 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_ODE_MASK 0x800u
19966 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_ODE_SHIFT 11
19967 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PKE_MASK 0x1000u
19968 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PKE_SHIFT 12
19969 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUE_MASK 0x2000u
19970 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUE_SHIFT 13
19971 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_MASK 0xC000u
19972 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_SHIFT 14
19973 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_MASK)
19974 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_HYS_MASK 0x10000u
19975 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_HYS_SHIFT 16
19976 /* SW_PAD_CTL_PAD_LCD1_DATA13 Bit Fields */
19977 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SRE_MASK 0x1u
19978 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SRE_SHIFT 0
19979 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_MASK 0x38u
19980 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_SHIFT 3
19981 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_MASK)
19982 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_MASK 0xC0u
19983 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_SHIFT 6
19984 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_MASK)
19985 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_ODE_MASK 0x800u
19986 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_ODE_SHIFT 11
19987 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PKE_MASK 0x1000u
19988 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PKE_SHIFT 12
19989 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUE_MASK 0x2000u
19990 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUE_SHIFT 13
19991 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_MASK 0xC000u
19992 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_SHIFT 14
19993 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_MASK)
19994 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_HYS_MASK 0x10000u
19995 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_HYS_SHIFT 16
19996 /* SW_PAD_CTL_PAD_LCD1_DATA14 Bit Fields */
19997 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SRE_MASK 0x1u
19998 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SRE_SHIFT 0
19999 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_MASK 0x38u
20000 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_SHIFT 3
20001 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_MASK)
20002 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_MASK 0xC0u
20003 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_SHIFT 6
20004 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_MASK)
20005 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_ODE_MASK 0x800u
20006 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_ODE_SHIFT 11
20007 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PKE_MASK 0x1000u
20008 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PKE_SHIFT 12
20009 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUE_MASK 0x2000u
20010 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUE_SHIFT 13
20011 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_MASK 0xC000u
20012 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_SHIFT 14
20013 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_MASK)
20014 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_HYS_MASK 0x10000u
20015 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_HYS_SHIFT 16
20016 /* SW_PAD_CTL_PAD_LCD1_DATA15 Bit Fields */
20017 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SRE_MASK 0x1u
20018 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SRE_SHIFT 0
20019 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_MASK 0x38u
20020 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_SHIFT 3
20021 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_MASK)
20022 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_MASK 0xC0u
20023 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_SHIFT 6
20024 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_MASK)
20025 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_ODE_MASK 0x800u
20026 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_ODE_SHIFT 11
20027 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PKE_MASK 0x1000u
20028 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PKE_SHIFT 12
20029 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUE_MASK 0x2000u
20030 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUE_SHIFT 13
20031 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_MASK 0xC000u
20032 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_SHIFT 14
20033 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_MASK)
20034 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_HYS_MASK 0x10000u
20035 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_HYS_SHIFT 16
20036 /* SW_PAD_CTL_PAD_LCD1_DATA16 Bit Fields */
20037 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SRE_MASK 0x1u
20038 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SRE_SHIFT 0
20039 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_MASK 0x38u
20040 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_SHIFT 3
20041 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_MASK)
20042 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_MASK 0xC0u
20043 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_SHIFT 6
20044 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_MASK)
20045 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_ODE_MASK 0x800u
20046 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_ODE_SHIFT 11
20047 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PKE_MASK 0x1000u
20048 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PKE_SHIFT 12
20049 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUE_MASK 0x2000u
20050 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUE_SHIFT 13
20051 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_MASK 0xC000u
20052 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_SHIFT 14
20053 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_MASK)
20054 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_HYS_MASK 0x10000u
20055 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_HYS_SHIFT 16
20056 /* SW_PAD_CTL_PAD_LCD1_DATA17 Bit Fields */
20057 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SRE_MASK 0x1u
20058 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SRE_SHIFT 0
20059 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_MASK 0x38u
20060 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_SHIFT 3
20061 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_MASK)
20062 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_MASK 0xC0u
20063 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_SHIFT 6
20064 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_MASK)
20065 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_ODE_MASK 0x800u
20066 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_ODE_SHIFT 11
20067 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PKE_MASK 0x1000u
20068 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PKE_SHIFT 12
20069 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUE_MASK 0x2000u
20070 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUE_SHIFT 13
20071 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_MASK 0xC000u
20072 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_SHIFT 14
20073 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_MASK)
20074 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_HYS_MASK 0x10000u
20075 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_HYS_SHIFT 16
20076 /* SW_PAD_CTL_PAD_LCD1_DATA18 Bit Fields */
20077 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SRE_MASK 0x1u
20078 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SRE_SHIFT 0
20079 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_MASK 0x38u
20080 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_SHIFT 3
20081 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_MASK)
20082 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_MASK 0xC0u
20083 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_SHIFT 6
20084 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_MASK)
20085 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_ODE_MASK 0x800u
20086 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_ODE_SHIFT 11
20087 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PKE_MASK 0x1000u
20088 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PKE_SHIFT 12
20089 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUE_MASK 0x2000u
20090 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUE_SHIFT 13
20091 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_MASK 0xC000u
20092 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_SHIFT 14
20093 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_MASK)
20094 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_HYS_MASK 0x10000u
20095 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_HYS_SHIFT 16
20096 /* SW_PAD_CTL_PAD_LCD1_DATA19 Bit Fields */
20097 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SRE_MASK 0x1u
20098 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SRE_SHIFT 0
20099 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_MASK 0x38u
20100 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_SHIFT 3
20101 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_MASK)
20102 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_MASK 0xC0u
20103 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_SHIFT 6
20104 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_MASK)
20105 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_ODE_MASK 0x800u
20106 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_ODE_SHIFT 11
20107 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PKE_MASK 0x1000u
20108 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PKE_SHIFT 12
20109 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUE_MASK 0x2000u
20110 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUE_SHIFT 13
20111 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_MASK 0xC000u
20112 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_SHIFT 14
20113 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_MASK)
20114 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_HYS_MASK 0x10000u
20115 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_HYS_SHIFT 16
20116 /* SW_PAD_CTL_PAD_LCD1_DATA20 Bit Fields */
20117 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SRE_MASK 0x1u
20118 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SRE_SHIFT 0
20119 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_MASK 0x38u
20120 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_SHIFT 3
20121 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_MASK)
20122 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_MASK 0xC0u
20123 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_SHIFT 6
20124 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_MASK)
20125 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_ODE_MASK 0x800u
20126 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_ODE_SHIFT 11
20127 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PKE_MASK 0x1000u
20128 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PKE_SHIFT 12
20129 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUE_MASK 0x2000u
20130 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUE_SHIFT 13
20131 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_MASK 0xC000u
20132 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_SHIFT 14
20133 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_MASK)
20134 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_HYS_MASK 0x10000u
20135 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_HYS_SHIFT 16
20136 /* SW_PAD_CTL_PAD_LCD1_DATA21 Bit Fields */
20137 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SRE_MASK 0x1u
20138 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SRE_SHIFT 0
20139 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_MASK 0x38u
20140 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_SHIFT 3
20141 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_MASK)
20142 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_MASK 0xC0u
20143 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_SHIFT 6
20144 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_MASK)
20145 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_ODE_MASK 0x800u
20146 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_ODE_SHIFT 11
20147 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PKE_MASK 0x1000u
20148 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PKE_SHIFT 12
20149 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUE_MASK 0x2000u
20150 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUE_SHIFT 13
20151 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_MASK 0xC000u
20152 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_SHIFT 14
20153 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_MASK)
20154 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_HYS_MASK 0x10000u
20155 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_HYS_SHIFT 16
20156 /* SW_PAD_CTL_PAD_LCD1_DATA22 Bit Fields */
20157 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SRE_MASK 0x1u
20158 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SRE_SHIFT 0
20159 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_MASK 0x38u
20160 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_SHIFT 3
20161 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_MASK)
20162 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_MASK 0xC0u
20163 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_SHIFT 6
20164 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_MASK)
20165 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_ODE_MASK 0x800u
20166 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_ODE_SHIFT 11
20167 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PKE_MASK 0x1000u
20168 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PKE_SHIFT 12
20169 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUE_MASK 0x2000u
20170 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUE_SHIFT 13
20171 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_MASK 0xC000u
20172 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_SHIFT 14
20173 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_MASK)
20174 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_HYS_MASK 0x10000u
20175 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_HYS_SHIFT 16
20176 /* SW_PAD_CTL_PAD_LCD1_DATA23 Bit Fields */
20177 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SRE_MASK 0x1u
20178 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SRE_SHIFT 0
20179 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_MASK 0x38u
20180 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_SHIFT 3
20181 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_MASK)
20182 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_MASK 0xC0u
20183 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_SHIFT 6
20184 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_MASK)
20185 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_ODE_MASK 0x800u
20186 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_ODE_SHIFT 11
20187 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PKE_MASK 0x1000u
20188 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PKE_SHIFT 12
20189 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUE_MASK 0x2000u
20190 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUE_SHIFT 13
20191 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_MASK 0xC000u
20192 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_SHIFT 14
20193 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_MASK)
20194 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_HYS_MASK 0x10000u
20195 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_HYS_SHIFT 16
20196 /* SW_PAD_CTL_PAD_LCD1_ENABLE Bit Fields */
20197 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SRE_MASK 0x1u
20198 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SRE_SHIFT 0
20199 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_MASK 0x38u
20200 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_SHIFT 3
20201 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_MASK)
20202 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_MASK 0xC0u
20203 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_SHIFT 6
20204 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_MASK)
20205 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_ODE_MASK 0x800u
20206 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_ODE_SHIFT 11
20207 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PKE_MASK 0x1000u
20208 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PKE_SHIFT 12
20209 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUE_MASK 0x2000u
20210 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUE_SHIFT 13
20211 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_MASK 0xC000u
20212 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_SHIFT 14
20213 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_MASK)
20214 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_HYS_MASK 0x10000u
20215 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_HYS_SHIFT 16
20216 /* SW_PAD_CTL_PAD_LCD1_HSYNC Bit Fields */
20217 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SRE_MASK 0x1u
20218 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SRE_SHIFT 0
20219 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_MASK 0x38u
20220 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_SHIFT 3
20221 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_MASK)
20222 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_MASK 0xC0u
20223 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_SHIFT 6
20224 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_MASK)
20225 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_ODE_MASK 0x800u
20226 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_ODE_SHIFT 11
20227 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PKE_MASK 0x1000u
20228 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PKE_SHIFT 12
20229 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUE_MASK 0x2000u
20230 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUE_SHIFT 13
20231 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_MASK 0xC000u
20232 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_SHIFT 14
20233 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_MASK)
20234 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_HYS_MASK 0x10000u
20235 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_HYS_SHIFT 16
20236 /* SW_PAD_CTL_PAD_LCD1_RESET Bit Fields */
20237 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SRE_MASK 0x1u
20238 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SRE_SHIFT 0
20239 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_MASK 0x38u
20240 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_SHIFT 3
20241 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_MASK)
20242 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_MASK 0xC0u
20243 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_SHIFT 6
20244 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_MASK)
20245 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_ODE_MASK 0x800u
20246 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_ODE_SHIFT 11
20247 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PKE_MASK 0x1000u
20248 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PKE_SHIFT 12
20249 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUE_MASK 0x2000u
20250 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUE_SHIFT 13
20251 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_MASK 0xC000u
20252 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_SHIFT 14
20253 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_MASK)
20254 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_HYS_MASK 0x10000u
20255 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_HYS_SHIFT 16
20256 /* SW_PAD_CTL_PAD_LCD1_VSYNC Bit Fields */
20257 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SRE_MASK 0x1u
20258 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SRE_SHIFT 0
20259 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_MASK 0x38u
20260 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_SHIFT 3
20261 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_MASK)
20262 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_MASK 0xC0u
20263 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_SHIFT 6
20264 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_MASK)
20265 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_ODE_MASK 0x800u
20266 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_ODE_SHIFT 11
20267 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PKE_MASK 0x1000u
20268 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PKE_SHIFT 12
20269 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUE_MASK 0x2000u
20270 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUE_SHIFT 13
20271 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_MASK 0xC000u
20272 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_SHIFT 14
20273 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_MASK)
20274 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_HYS_MASK 0x10000u
20275 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_HYS_SHIFT 16
20276 /* SW_PAD_CTL_PAD_NAND_ALE Bit Fields */
20277 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_MASK  0x1u
20278 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_SHIFT 0
20279 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_MASK  0x38u
20280 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_SHIFT 3
20281 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_MASK)
20282 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_MASK 0xC0u
20283 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_SHIFT 6
20284 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_MASK)
20285 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_MASK  0x800u
20286 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_SHIFT 11
20287 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_MASK  0x1000u
20288 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_SHIFT 12
20289 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_MASK  0x2000u
20290 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_SHIFT 13
20291 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_MASK  0xC000u
20292 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_SHIFT 14
20293 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_MASK)
20294 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_MASK  0x10000u
20295 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_SHIFT 16
20296 /* SW_PAD_CTL_PAD_NAND_CE0_B Bit Fields */
20297 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SRE_MASK 0x1u
20298 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SRE_SHIFT 0
20299 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_MASK 0x38u
20300 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_SHIFT 3
20301 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_MASK)
20302 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_MASK 0xC0u
20303 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_SHIFT 6
20304 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_MASK)
20305 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_ODE_MASK 0x800u
20306 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_ODE_SHIFT 11
20307 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PKE_MASK 0x1000u
20308 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PKE_SHIFT 12
20309 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUE_MASK 0x2000u
20310 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUE_SHIFT 13
20311 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_MASK 0xC000u
20312 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_SHIFT 14
20313 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_MASK)
20314 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_HYS_MASK 0x10000u
20315 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_HYS_SHIFT 16
20316 /* SW_PAD_CTL_PAD_NAND_CE1_B Bit Fields */
20317 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SRE_MASK 0x1u
20318 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SRE_SHIFT 0
20319 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_MASK 0x38u
20320 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_SHIFT 3
20321 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_MASK)
20322 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_MASK 0xC0u
20323 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_SHIFT 6
20324 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_MASK)
20325 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_ODE_MASK 0x800u
20326 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_ODE_SHIFT 11
20327 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PKE_MASK 0x1000u
20328 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PKE_SHIFT 12
20329 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUE_MASK 0x2000u
20330 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUE_SHIFT 13
20331 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_MASK 0xC000u
20332 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_SHIFT 14
20333 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_MASK)
20334 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_HYS_MASK 0x10000u
20335 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_HYS_SHIFT 16
20336 /* SW_PAD_CTL_PAD_NAND_CLE Bit Fields */
20337 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_MASK  0x1u
20338 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_SHIFT 0
20339 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_MASK  0x38u
20340 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_SHIFT 3
20341 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_MASK)
20342 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_MASK 0xC0u
20343 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_SHIFT 6
20344 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_MASK)
20345 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_MASK  0x800u
20346 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_SHIFT 11
20347 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_MASK  0x1000u
20348 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_SHIFT 12
20349 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_MASK  0x2000u
20350 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_SHIFT 13
20351 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_MASK  0xC000u
20352 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_SHIFT 14
20353 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_MASK)
20354 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_MASK  0x10000u
20355 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_SHIFT 16
20356 /* SW_PAD_CTL_PAD_NAND_DATA00 Bit Fields */
20357 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_MASK 0x1u
20358 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_SHIFT 0
20359 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_MASK 0x38u
20360 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_SHIFT 3
20361 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_MASK)
20362 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_MASK 0xC0u
20363 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_SHIFT 6
20364 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_MASK)
20365 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_MASK 0x800u
20366 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_SHIFT 11
20367 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_MASK 0x1000u
20368 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_SHIFT 12
20369 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_MASK 0x2000u
20370 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_SHIFT 13
20371 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_MASK 0xC000u
20372 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_SHIFT 14
20373 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_MASK)
20374 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_MASK 0x10000u
20375 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_SHIFT 16
20376 /* SW_PAD_CTL_PAD_NAND_DATA01 Bit Fields */
20377 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_MASK 0x1u
20378 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_SHIFT 0
20379 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_MASK 0x38u
20380 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_SHIFT 3
20381 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_MASK)
20382 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_MASK 0xC0u
20383 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_SHIFT 6
20384 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_MASK)
20385 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_MASK 0x800u
20386 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_SHIFT 11
20387 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_MASK 0x1000u
20388 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_SHIFT 12
20389 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_MASK 0x2000u
20390 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_SHIFT 13
20391 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_MASK 0xC000u
20392 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_SHIFT 14
20393 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_MASK)
20394 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_MASK 0x10000u
20395 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_SHIFT 16
20396 /* SW_PAD_CTL_PAD_NAND_DATA02 Bit Fields */
20397 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_MASK 0x1u
20398 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_SHIFT 0
20399 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_MASK 0x38u
20400 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_SHIFT 3
20401 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_MASK)
20402 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_MASK 0xC0u
20403 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_SHIFT 6
20404 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_MASK)
20405 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_MASK 0x800u
20406 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_SHIFT 11
20407 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_MASK 0x1000u
20408 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_SHIFT 12
20409 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_MASK 0x2000u
20410 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_SHIFT 13
20411 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_MASK 0xC000u
20412 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_SHIFT 14
20413 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_MASK)
20414 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_MASK 0x10000u
20415 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_SHIFT 16
20416 /* SW_PAD_CTL_PAD_NAND_DATA03 Bit Fields */
20417 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_MASK 0x1u
20418 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_SHIFT 0
20419 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_MASK 0x38u
20420 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_SHIFT 3
20421 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_MASK)
20422 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_MASK 0xC0u
20423 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_SHIFT 6
20424 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_MASK)
20425 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_MASK 0x800u
20426 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_SHIFT 11
20427 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_MASK 0x1000u
20428 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_SHIFT 12
20429 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_MASK 0x2000u
20430 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_SHIFT 13
20431 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_MASK 0xC000u
20432 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_SHIFT 14
20433 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_MASK)
20434 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_MASK 0x10000u
20435 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_SHIFT 16
20436 /* SW_PAD_CTL_PAD_NAND_DATA04 Bit Fields */
20437 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_MASK 0x1u
20438 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_SHIFT 0
20439 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_MASK 0x38u
20440 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_SHIFT 3
20441 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_MASK)
20442 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_MASK 0xC0u
20443 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_SHIFT 6
20444 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_MASK)
20445 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_MASK 0x800u
20446 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_SHIFT 11
20447 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_MASK 0x1000u
20448 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_SHIFT 12
20449 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_MASK 0x2000u
20450 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_SHIFT 13
20451 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_MASK 0xC000u
20452 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_SHIFT 14
20453 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_MASK)
20454 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_MASK 0x10000u
20455 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_SHIFT 16
20456 /* SW_PAD_CTL_PAD_NAND_DATA05 Bit Fields */
20457 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_MASK 0x1u
20458 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_SHIFT 0
20459 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_MASK 0x38u
20460 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_SHIFT 3
20461 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_MASK)
20462 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_MASK 0xC0u
20463 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_SHIFT 6
20464 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_MASK)
20465 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_MASK 0x800u
20466 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_SHIFT 11
20467 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_MASK 0x1000u
20468 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_SHIFT 12
20469 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_MASK 0x2000u
20470 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_SHIFT 13
20471 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_MASK 0xC000u
20472 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_SHIFT 14
20473 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_MASK)
20474 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_MASK 0x10000u
20475 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_SHIFT 16
20476 /* SW_PAD_CTL_PAD_NAND_DATA06 Bit Fields */
20477 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_MASK 0x1u
20478 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_SHIFT 0
20479 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_MASK 0x38u
20480 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_SHIFT 3
20481 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_MASK)
20482 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_MASK 0xC0u
20483 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_SHIFT 6
20484 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_MASK)
20485 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_MASK 0x800u
20486 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_SHIFT 11
20487 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_MASK 0x1000u
20488 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_SHIFT 12
20489 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_MASK 0x2000u
20490 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_SHIFT 13
20491 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_MASK 0xC000u
20492 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_SHIFT 14
20493 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_MASK)
20494 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_MASK 0x10000u
20495 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_SHIFT 16
20496 /* SW_PAD_CTL_PAD_NAND_DATA07 Bit Fields */
20497 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_MASK 0x1u
20498 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_SHIFT 0
20499 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_MASK 0x38u
20500 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_SHIFT 3
20501 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_MASK)
20502 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_MASK 0xC0u
20503 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_SHIFT 6
20504 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_MASK)
20505 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_MASK 0x800u
20506 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_SHIFT 11
20507 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_MASK 0x1000u
20508 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_SHIFT 12
20509 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_MASK 0x2000u
20510 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_SHIFT 13
20511 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_MASK 0xC000u
20512 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_SHIFT 14
20513 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_MASK)
20514 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_MASK 0x10000u
20515 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_SHIFT 16
20516 /* SW_PAD_CTL_PAD_NAND_RE_B Bit Fields */
20517 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SRE_MASK 0x1u
20518 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SRE_SHIFT 0
20519 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_MASK 0x38u
20520 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_SHIFT 3
20521 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_MASK)
20522 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_MASK 0xC0u
20523 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_SHIFT 6
20524 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_MASK)
20525 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_ODE_MASK 0x800u
20526 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_ODE_SHIFT 11
20527 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PKE_MASK 0x1000u
20528 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PKE_SHIFT 12
20529 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUE_MASK 0x2000u
20530 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUE_SHIFT 13
20531 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_MASK 0xC000u
20532 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_SHIFT 14
20533 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_MASK)
20534 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_HYS_MASK 0x10000u
20535 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_HYS_SHIFT 16
20536 /* SW_PAD_CTL_PAD_NAND_READY_B Bit Fields */
20537 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SRE_MASK 0x1u
20538 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SRE_SHIFT 0
20539 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_MASK 0x38u
20540 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_SHIFT 3
20541 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_MASK)
20542 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_MASK 0xC0u
20543 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_SHIFT 6
20544 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_MASK)
20545 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_ODE_MASK 0x800u
20546 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_ODE_SHIFT 11
20547 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PKE_MASK 0x1000u
20548 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PKE_SHIFT 12
20549 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUE_MASK 0x2000u
20550 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUE_SHIFT 13
20551 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_MASK 0xC000u
20552 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_SHIFT 14
20553 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_MASK)
20554 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_HYS_MASK 0x10000u
20555 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_HYS_SHIFT 16
20556 /* SW_PAD_CTL_PAD_NAND_WE_B Bit Fields */
20557 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SRE_MASK 0x1u
20558 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SRE_SHIFT 0
20559 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_MASK 0x38u
20560 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_SHIFT 3
20561 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_MASK)
20562 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_MASK 0xC0u
20563 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_SHIFT 6
20564 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_MASK)
20565 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_ODE_MASK 0x800u
20566 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_ODE_SHIFT 11
20567 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PKE_MASK 0x1000u
20568 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PKE_SHIFT 12
20569 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUE_MASK 0x2000u
20570 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUE_SHIFT 13
20571 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_MASK 0xC000u
20572 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_SHIFT 14
20573 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_MASK)
20574 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_HYS_MASK 0x10000u
20575 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_HYS_SHIFT 16
20576 /* SW_PAD_CTL_PAD_NAND_WP_B Bit Fields */
20577 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_MASK 0x1u
20578 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_SHIFT 0
20579 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_MASK 0x38u
20580 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_SHIFT 3
20581 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_MASK)
20582 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_MASK 0xC0u
20583 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_SHIFT 6
20584 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_MASK)
20585 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_MASK 0x800u
20586 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_SHIFT 11
20587 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_MASK 0x1000u
20588 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_SHIFT 12
20589 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_MASK 0x2000u
20590 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_SHIFT 13
20591 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_MASK 0xC000u
20592 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_SHIFT 14
20593 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_MASK)
20594 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_MASK 0x10000u
20595 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_SHIFT 16
20596 /* SW_PAD_CTL_PAD_QSPI1A_DATA0 Bit Fields */
20597 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SRE_MASK 0x1u
20598 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SRE_SHIFT 0
20599 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_MASK 0x38u
20600 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_SHIFT 3
20601 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_MASK)
20602 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_MASK 0xC0u
20603 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_SHIFT 6
20604 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_MASK)
20605 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_ODE_MASK 0x800u
20606 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_ODE_SHIFT 11
20607 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PKE_MASK 0x1000u
20608 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PKE_SHIFT 12
20609 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUE_MASK 0x2000u
20610 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUE_SHIFT 13
20611 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_MASK 0xC000u
20612 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_SHIFT 14
20613 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_MASK)
20614 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_HYS_MASK 0x10000u
20615 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_HYS_SHIFT 16
20616 /* SW_PAD_CTL_PAD_QSPI1A_DATA1 Bit Fields */
20617 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SRE_MASK 0x1u
20618 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SRE_SHIFT 0
20619 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_MASK 0x38u
20620 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_SHIFT 3
20621 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_MASK)
20622 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_MASK 0xC0u
20623 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_SHIFT 6
20624 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_MASK)
20625 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_ODE_MASK 0x800u
20626 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_ODE_SHIFT 11
20627 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PKE_MASK 0x1000u
20628 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PKE_SHIFT 12
20629 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUE_MASK 0x2000u
20630 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUE_SHIFT 13
20631 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_MASK 0xC000u
20632 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_SHIFT 14
20633 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_MASK)
20634 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_HYS_MASK 0x10000u
20635 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_HYS_SHIFT 16
20636 /* SW_PAD_CTL_PAD_QSPI1A_DATA2 Bit Fields */
20637 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SRE_MASK 0x1u
20638 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SRE_SHIFT 0
20639 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_MASK 0x38u
20640 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_SHIFT 3
20641 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_MASK)
20642 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_MASK 0xC0u
20643 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_SHIFT 6
20644 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_MASK)
20645 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_ODE_MASK 0x800u
20646 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_ODE_SHIFT 11
20647 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PKE_MASK 0x1000u
20648 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PKE_SHIFT 12
20649 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUE_MASK 0x2000u
20650 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUE_SHIFT 13
20651 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_MASK 0xC000u
20652 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_SHIFT 14
20653 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_MASK)
20654 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_HYS_MASK 0x10000u
20655 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_HYS_SHIFT 16
20656 /* SW_PAD_CTL_PAD_QSPI1A_DATA3 Bit Fields */
20657 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SRE_MASK 0x1u
20658 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SRE_SHIFT 0
20659 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_MASK 0x38u
20660 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_SHIFT 3
20661 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_MASK)
20662 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_MASK 0xC0u
20663 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_SHIFT 6
20664 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_MASK)
20665 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_ODE_MASK 0x800u
20666 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_ODE_SHIFT 11
20667 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PKE_MASK 0x1000u
20668 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PKE_SHIFT 12
20669 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUE_MASK 0x2000u
20670 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUE_SHIFT 13
20671 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_MASK 0xC000u
20672 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_SHIFT 14
20673 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_MASK)
20674 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_HYS_MASK 0x10000u
20675 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_HYS_SHIFT 16
20676 /* SW_PAD_CTL_PAD_QSPI1A_DQS Bit Fields */
20677 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SRE_MASK 0x1u
20678 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SRE_SHIFT 0
20679 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_MASK 0x38u
20680 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_SHIFT 3
20681 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_MASK)
20682 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_MASK 0xC0u
20683 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_SHIFT 6
20684 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_MASK)
20685 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_ODE_MASK 0x800u
20686 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_ODE_SHIFT 11
20687 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PKE_MASK 0x1000u
20688 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PKE_SHIFT 12
20689 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUE_MASK 0x2000u
20690 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUE_SHIFT 13
20691 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_MASK 0xC000u
20692 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_SHIFT 14
20693 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_MASK)
20694 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_HYS_MASK 0x10000u
20695 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_HYS_SHIFT 16
20696 /* SW_PAD_CTL_PAD_QSPI1A_SCLK Bit Fields */
20697 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SRE_MASK 0x1u
20698 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SRE_SHIFT 0
20699 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_MASK 0x38u
20700 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_SHIFT 3
20701 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_MASK)
20702 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_MASK 0xC0u
20703 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_SHIFT 6
20704 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_MASK)
20705 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_ODE_MASK 0x800u
20706 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_ODE_SHIFT 11
20707 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PKE_MASK 0x1000u
20708 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PKE_SHIFT 12
20709 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUE_MASK 0x2000u
20710 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUE_SHIFT 13
20711 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_MASK 0xC000u
20712 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_SHIFT 14
20713 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_MASK)
20714 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_HYS_MASK 0x10000u
20715 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_HYS_SHIFT 16
20716 /* SW_PAD_CTL_PAD_QSPI1A_SS0_B Bit Fields */
20717 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SRE_MASK 0x1u
20718 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SRE_SHIFT 0
20719 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_MASK 0x38u
20720 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_SHIFT 3
20721 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_MASK)
20722 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_MASK 0xC0u
20723 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_SHIFT 6
20724 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_MASK)
20725 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_ODE_MASK 0x800u
20726 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_ODE_SHIFT 11
20727 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PKE_MASK 0x1000u
20728 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PKE_SHIFT 12
20729 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUE_MASK 0x2000u
20730 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUE_SHIFT 13
20731 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_MASK 0xC000u
20732 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_SHIFT 14
20733 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_MASK)
20734 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_HYS_MASK 0x10000u
20735 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_HYS_SHIFT 16
20736 /* SW_PAD_CTL_PAD_QSPI1A_SS1_B Bit Fields */
20737 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SRE_MASK 0x1u
20738 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SRE_SHIFT 0
20739 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_MASK 0x38u
20740 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_SHIFT 3
20741 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_MASK)
20742 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_MASK 0xC0u
20743 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_SHIFT 6
20744 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_MASK)
20745 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_ODE_MASK 0x800u
20746 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_ODE_SHIFT 11
20747 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PKE_MASK 0x1000u
20748 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PKE_SHIFT 12
20749 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUE_MASK 0x2000u
20750 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUE_SHIFT 13
20751 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_MASK 0xC000u
20752 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_SHIFT 14
20753 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_MASK)
20754 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_HYS_MASK 0x10000u
20755 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_HYS_SHIFT 16
20756 /* SW_PAD_CTL_PAD_QSPI1B_DATA0 Bit Fields */
20757 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SRE_MASK 0x1u
20758 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SRE_SHIFT 0
20759 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_MASK 0x38u
20760 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_SHIFT 3
20761 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_MASK)
20762 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_MASK 0xC0u
20763 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_SHIFT 6
20764 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_MASK)
20765 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_ODE_MASK 0x800u
20766 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_ODE_SHIFT 11
20767 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PKE_MASK 0x1000u
20768 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PKE_SHIFT 12
20769 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUE_MASK 0x2000u
20770 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUE_SHIFT 13
20771 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_MASK 0xC000u
20772 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_SHIFT 14
20773 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_MASK)
20774 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_HYS_MASK 0x10000u
20775 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_HYS_SHIFT 16
20776 /* SW_PAD_CTL_PAD_QSPI1B_DATA1 Bit Fields */
20777 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SRE_MASK 0x1u
20778 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SRE_SHIFT 0
20779 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_MASK 0x38u
20780 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_SHIFT 3
20781 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_MASK)
20782 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_MASK 0xC0u
20783 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_SHIFT 6
20784 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_MASK)
20785 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_ODE_MASK 0x800u
20786 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_ODE_SHIFT 11
20787 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PKE_MASK 0x1000u
20788 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PKE_SHIFT 12
20789 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUE_MASK 0x2000u
20790 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUE_SHIFT 13
20791 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_MASK 0xC000u
20792 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_SHIFT 14
20793 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_MASK)
20794 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_HYS_MASK 0x10000u
20795 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_HYS_SHIFT 16
20796 /* SW_PAD_CTL_PAD_QSPI1B_DATA2 Bit Fields */
20797 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SRE_MASK 0x1u
20798 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SRE_SHIFT 0
20799 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_MASK 0x38u
20800 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_SHIFT 3
20801 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_MASK)
20802 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_MASK 0xC0u
20803 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_SHIFT 6
20804 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_MASK)
20805 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_ODE_MASK 0x800u
20806 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_ODE_SHIFT 11
20807 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PKE_MASK 0x1000u
20808 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PKE_SHIFT 12
20809 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUE_MASK 0x2000u
20810 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUE_SHIFT 13
20811 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_MASK 0xC000u
20812 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_SHIFT 14
20813 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_MASK)
20814 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_HYS_MASK 0x10000u
20815 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_HYS_SHIFT 16
20816 /* SW_PAD_CTL_PAD_QSPI1B_DATA3 Bit Fields */
20817 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SRE_MASK 0x1u
20818 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SRE_SHIFT 0
20819 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_MASK 0x38u
20820 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_SHIFT 3
20821 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_MASK)
20822 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_MASK 0xC0u
20823 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_SHIFT 6
20824 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_MASK)
20825 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_ODE_MASK 0x800u
20826 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_ODE_SHIFT 11
20827 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PKE_MASK 0x1000u
20828 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PKE_SHIFT 12
20829 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUE_MASK 0x2000u
20830 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUE_SHIFT 13
20831 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_MASK 0xC000u
20832 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_SHIFT 14
20833 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_MASK)
20834 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_HYS_MASK 0x10000u
20835 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_HYS_SHIFT 16
20836 /* SW_PAD_CTL_PAD_QSPI1B_DQS Bit Fields */
20837 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SRE_MASK 0x1u
20838 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SRE_SHIFT 0
20839 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_MASK 0x38u
20840 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_SHIFT 3
20841 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_MASK)
20842 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_MASK 0xC0u
20843 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_SHIFT 6
20844 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_MASK)
20845 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_ODE_MASK 0x800u
20846 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_ODE_SHIFT 11
20847 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PKE_MASK 0x1000u
20848 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PKE_SHIFT 12
20849 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUE_MASK 0x2000u
20850 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUE_SHIFT 13
20851 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_MASK 0xC000u
20852 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_SHIFT 14
20853 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_MASK)
20854 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_HYS_MASK 0x10000u
20855 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_HYS_SHIFT 16
20856 /* SW_PAD_CTL_PAD_QSPI1B_SCLK Bit Fields */
20857 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SRE_MASK 0x1u
20858 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SRE_SHIFT 0
20859 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_MASK 0x38u
20860 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_SHIFT 3
20861 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_MASK)
20862 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_MASK 0xC0u
20863 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_SHIFT 6
20864 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_MASK)
20865 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_ODE_MASK 0x800u
20866 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_ODE_SHIFT 11
20867 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PKE_MASK 0x1000u
20868 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PKE_SHIFT 12
20869 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUE_MASK 0x2000u
20870 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUE_SHIFT 13
20871 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_MASK 0xC000u
20872 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_SHIFT 14
20873 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_MASK)
20874 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_HYS_MASK 0x10000u
20875 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_HYS_SHIFT 16
20876 /* SW_PAD_CTL_PAD_QSPI1B_SS0_B Bit Fields */
20877 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SRE_MASK 0x1u
20878 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SRE_SHIFT 0
20879 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_MASK 0x38u
20880 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_SHIFT 3
20881 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_MASK)
20882 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_MASK 0xC0u
20883 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_SHIFT 6
20884 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_MASK)
20885 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_ODE_MASK 0x800u
20886 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_ODE_SHIFT 11
20887 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PKE_MASK 0x1000u
20888 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PKE_SHIFT 12
20889 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUE_MASK 0x2000u
20890 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUE_SHIFT 13
20891 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_MASK 0xC000u
20892 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_SHIFT 14
20893 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_MASK)
20894 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_HYS_MASK 0x10000u
20895 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_HYS_SHIFT 16
20896 /* SW_PAD_CTL_PAD_QSPI1B_SS1_B Bit Fields */
20897 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SRE_MASK 0x1u
20898 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SRE_SHIFT 0
20899 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_MASK 0x38u
20900 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_SHIFT 3
20901 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_MASK)
20902 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_MASK 0xC0u
20903 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_SHIFT 6
20904 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_MASK)
20905 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_ODE_MASK 0x800u
20906 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_ODE_SHIFT 11
20907 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PKE_MASK 0x1000u
20908 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PKE_SHIFT 12
20909 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUE_MASK 0x2000u
20910 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUE_SHIFT 13
20911 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_MASK 0xC000u
20912 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_SHIFT 14
20913 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_MASK)
20914 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_HYS_MASK 0x10000u
20915 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_HYS_SHIFT 16
20916 /* SW_PAD_CTL_PAD_RGMII1_RD0 Bit Fields */
20917 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SRE_MASK 0x1u
20918 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SRE_SHIFT 0
20919 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_MASK 0x38u
20920 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_SHIFT 3
20921 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_MASK)
20922 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_MASK 0xC0u
20923 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_SHIFT 6
20924 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_MASK)
20925 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_ODE_MASK 0x800u
20926 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_ODE_SHIFT 11
20927 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PKE_MASK 0x1000u
20928 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PKE_SHIFT 12
20929 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUE_MASK 0x2000u
20930 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUE_SHIFT 13
20931 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_MASK 0xC000u
20932 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_SHIFT 14
20933 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_MASK)
20934 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_HYS_MASK 0x10000u
20935 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_HYS_SHIFT 16
20936 /* SW_PAD_CTL_PAD_RGMII1_RD1 Bit Fields */
20937 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SRE_MASK 0x1u
20938 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SRE_SHIFT 0
20939 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_MASK 0x38u
20940 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_SHIFT 3
20941 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_MASK)
20942 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_MASK 0xC0u
20943 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_SHIFT 6
20944 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_MASK)
20945 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_ODE_MASK 0x800u
20946 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_ODE_SHIFT 11
20947 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PKE_MASK 0x1000u
20948 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PKE_SHIFT 12
20949 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUE_MASK 0x2000u
20950 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUE_SHIFT 13
20951 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_MASK 0xC000u
20952 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_SHIFT 14
20953 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_MASK)
20954 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_HYS_MASK 0x10000u
20955 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_HYS_SHIFT 16
20956 /* SW_PAD_CTL_PAD_RGMII1_RD2 Bit Fields */
20957 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SRE_MASK 0x1u
20958 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SRE_SHIFT 0
20959 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_MASK 0x38u
20960 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_SHIFT 3
20961 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_MASK)
20962 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_MASK 0xC0u
20963 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_SHIFT 6
20964 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_MASK)
20965 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_ODE_MASK 0x800u
20966 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_ODE_SHIFT 11
20967 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PKE_MASK 0x1000u
20968 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PKE_SHIFT 12
20969 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUE_MASK 0x2000u
20970 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUE_SHIFT 13
20971 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_MASK 0xC000u
20972 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_SHIFT 14
20973 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_MASK)
20974 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_HYS_MASK 0x10000u
20975 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_HYS_SHIFT 16
20976 /* SW_PAD_CTL_PAD_RGMII1_RD3 Bit Fields */
20977 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SRE_MASK 0x1u
20978 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SRE_SHIFT 0
20979 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_MASK 0x38u
20980 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_SHIFT 3
20981 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_MASK)
20982 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_MASK 0xC0u
20983 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_SHIFT 6
20984 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_MASK)
20985 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_ODE_MASK 0x800u
20986 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_ODE_SHIFT 11
20987 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PKE_MASK 0x1000u
20988 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PKE_SHIFT 12
20989 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUE_MASK 0x2000u
20990 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUE_SHIFT 13
20991 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_MASK 0xC000u
20992 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_SHIFT 14
20993 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_MASK)
20994 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_HYS_MASK 0x10000u
20995 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_HYS_SHIFT 16
20996 /* SW_PAD_CTL_PAD_RGMII1_RX_CTL Bit Fields */
20997 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SRE_MASK 0x1u
20998 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SRE_SHIFT 0
20999 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_MASK 0x38u
21000 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_SHIFT 3
21001 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_MASK)
21002 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_MASK 0xC0u
21003 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_SHIFT 6
21004 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_MASK)
21005 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_ODE_MASK 0x800u
21006 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_ODE_SHIFT 11
21007 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PKE_MASK 0x1000u
21008 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PKE_SHIFT 12
21009 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUE_MASK 0x2000u
21010 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUE_SHIFT 13
21011 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_MASK 0xC000u
21012 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_SHIFT 14
21013 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_MASK)
21014 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_HYS_MASK 0x10000u
21015 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_HYS_SHIFT 16
21016 /* SW_PAD_CTL_PAD_RGMII1_RXC Bit Fields */
21017 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SRE_MASK 0x1u
21018 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SRE_SHIFT 0
21019 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_MASK 0x38u
21020 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_SHIFT 3
21021 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_MASK)
21022 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_MASK 0xC0u
21023 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_SHIFT 6
21024 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_MASK)
21025 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_ODE_MASK 0x800u
21026 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_ODE_SHIFT 11
21027 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PKE_MASK 0x1000u
21028 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PKE_SHIFT 12
21029 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUE_MASK 0x2000u
21030 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUE_SHIFT 13
21031 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_MASK 0xC000u
21032 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_SHIFT 14
21033 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_MASK)
21034 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_HYS_MASK 0x10000u
21035 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_HYS_SHIFT 16
21036 /* SW_PAD_CTL_PAD_RGMII1_TD0 Bit Fields */
21037 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SRE_MASK 0x1u
21038 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SRE_SHIFT 0
21039 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_MASK 0x38u
21040 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_SHIFT 3
21041 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_MASK)
21042 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_MASK 0xC0u
21043 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_SHIFT 6
21044 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_MASK)
21045 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_ODE_MASK 0x800u
21046 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_ODE_SHIFT 11
21047 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PKE_MASK 0x1000u
21048 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PKE_SHIFT 12
21049 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUE_MASK 0x2000u
21050 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUE_SHIFT 13
21051 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_MASK 0xC000u
21052 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_SHIFT 14
21053 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_MASK)
21054 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_HYS_MASK 0x10000u
21055 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_HYS_SHIFT 16
21056 /* SW_PAD_CTL_PAD_RGMII1_TD1 Bit Fields */
21057 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SRE_MASK 0x1u
21058 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SRE_SHIFT 0
21059 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_MASK 0x38u
21060 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_SHIFT 3
21061 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_MASK)
21062 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_MASK 0xC0u
21063 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_SHIFT 6
21064 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_MASK)
21065 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_ODE_MASK 0x800u
21066 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_ODE_SHIFT 11
21067 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PKE_MASK 0x1000u
21068 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PKE_SHIFT 12
21069 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUE_MASK 0x2000u
21070 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUE_SHIFT 13
21071 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_MASK 0xC000u
21072 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_SHIFT 14
21073 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_MASK)
21074 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_HYS_MASK 0x10000u
21075 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_HYS_SHIFT 16
21076 /* SW_PAD_CTL_PAD_RGMII1_TD2 Bit Fields */
21077 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SRE_MASK 0x1u
21078 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SRE_SHIFT 0
21079 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_MASK 0x38u
21080 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_SHIFT 3
21081 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_MASK)
21082 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_MASK 0xC0u
21083 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_SHIFT 6
21084 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_MASK)
21085 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_ODE_MASK 0x800u
21086 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_ODE_SHIFT 11
21087 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PKE_MASK 0x1000u
21088 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PKE_SHIFT 12
21089 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUE_MASK 0x2000u
21090 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUE_SHIFT 13
21091 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_MASK 0xC000u
21092 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_SHIFT 14
21093 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_MASK)
21094 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_HYS_MASK 0x10000u
21095 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_HYS_SHIFT 16
21096 /* SW_PAD_CTL_PAD_RGMII1_TD3 Bit Fields */
21097 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SRE_MASK 0x1u
21098 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SRE_SHIFT 0
21099 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_MASK 0x38u
21100 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_SHIFT 3
21101 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_MASK)
21102 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_MASK 0xC0u
21103 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_SHIFT 6
21104 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_MASK)
21105 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_ODE_MASK 0x800u
21106 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_ODE_SHIFT 11
21107 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PKE_MASK 0x1000u
21108 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PKE_SHIFT 12
21109 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUE_MASK 0x2000u
21110 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUE_SHIFT 13
21111 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_MASK 0xC000u
21112 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_SHIFT 14
21113 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_MASK)
21114 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_HYS_MASK 0x10000u
21115 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_HYS_SHIFT 16
21116 /* SW_PAD_CTL_PAD_RGMII1_TX_CTL Bit Fields */
21117 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SRE_MASK 0x1u
21118 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SRE_SHIFT 0
21119 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_MASK 0x38u
21120 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_SHIFT 3
21121 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_MASK)
21122 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_MASK 0xC0u
21123 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_SHIFT 6
21124 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_MASK)
21125 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_ODE_MASK 0x800u
21126 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_ODE_SHIFT 11
21127 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PKE_MASK 0x1000u
21128 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PKE_SHIFT 12
21129 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUE_MASK 0x2000u
21130 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUE_SHIFT 13
21131 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_MASK 0xC000u
21132 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_SHIFT 14
21133 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_MASK)
21134 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_HYS_MASK 0x10000u
21135 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_HYS_SHIFT 16
21136 /* SW_PAD_CTL_PAD_RGMII1_TXC Bit Fields */
21137 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SRE_MASK 0x1u
21138 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SRE_SHIFT 0
21139 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_MASK 0x38u
21140 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_SHIFT 3
21141 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_MASK)
21142 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_MASK 0xC0u
21143 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_SHIFT 6
21144 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_MASK)
21145 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_ODE_MASK 0x800u
21146 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_ODE_SHIFT 11
21147 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PKE_MASK 0x1000u
21148 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PKE_SHIFT 12
21149 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUE_MASK 0x2000u
21150 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUE_SHIFT 13
21151 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_MASK 0xC000u
21152 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_SHIFT 14
21153 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_MASK)
21154 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_HYS_MASK 0x10000u
21155 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_HYS_SHIFT 16
21156 /* SW_PAD_CTL_PAD_RGMII2_RD0 Bit Fields */
21157 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SRE_MASK 0x1u
21158 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SRE_SHIFT 0
21159 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_MASK 0x38u
21160 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_SHIFT 3
21161 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_MASK)
21162 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_MASK 0xC0u
21163 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_SHIFT 6
21164 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_MASK)
21165 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_ODE_MASK 0x800u
21166 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_ODE_SHIFT 11
21167 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PKE_MASK 0x1000u
21168 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PKE_SHIFT 12
21169 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUE_MASK 0x2000u
21170 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUE_SHIFT 13
21171 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_MASK 0xC000u
21172 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_SHIFT 14
21173 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_MASK)
21174 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_HYS_MASK 0x10000u
21175 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_HYS_SHIFT 16
21176 /* SW_PAD_CTL_PAD_RGMII2_RD1 Bit Fields */
21177 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SRE_MASK 0x1u
21178 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SRE_SHIFT 0
21179 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_MASK 0x38u
21180 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_SHIFT 3
21181 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_MASK)
21182 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_MASK 0xC0u
21183 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_SHIFT 6
21184 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_MASK)
21185 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_ODE_MASK 0x800u
21186 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_ODE_SHIFT 11
21187 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PKE_MASK 0x1000u
21188 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PKE_SHIFT 12
21189 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUE_MASK 0x2000u
21190 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUE_SHIFT 13
21191 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_MASK 0xC000u
21192 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_SHIFT 14
21193 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_MASK)
21194 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_HYS_MASK 0x10000u
21195 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_HYS_SHIFT 16
21196 /* SW_PAD_CTL_PAD_RGMII2_RD2 Bit Fields */
21197 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SRE_MASK 0x1u
21198 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SRE_SHIFT 0
21199 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_MASK 0x38u
21200 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_SHIFT 3
21201 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_MASK)
21202 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_MASK 0xC0u
21203 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_SHIFT 6
21204 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_MASK)
21205 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_ODE_MASK 0x800u
21206 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_ODE_SHIFT 11
21207 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK 0x1000u
21208 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_SHIFT 12
21209 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK 0x2000u
21210 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_SHIFT 13
21211 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_MASK 0xC000u
21212 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_SHIFT 14
21213 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_MASK)
21214 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_HYS_MASK 0x10000u
21215 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_HYS_SHIFT 16
21216 /* SW_PAD_CTL_PAD_RGMII2_RD3 Bit Fields */
21217 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SRE_MASK 0x1u
21218 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SRE_SHIFT 0
21219 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_MASK 0x38u
21220 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_SHIFT 3
21221 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_MASK)
21222 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_MASK 0xC0u
21223 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_SHIFT 6
21224 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_MASK)
21225 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_ODE_MASK 0x800u
21226 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_ODE_SHIFT 11
21227 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK 0x1000u
21228 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_SHIFT 12
21229 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK 0x2000u
21230 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_SHIFT 13
21231 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_MASK 0xC000u
21232 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_SHIFT 14
21233 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_MASK)
21234 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_HYS_MASK 0x10000u
21235 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_HYS_SHIFT 16
21236 /* SW_PAD_CTL_PAD_RGMII2_RX_CTL Bit Fields */
21237 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SRE_MASK 0x1u
21238 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SRE_SHIFT 0
21239 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_MASK 0x38u
21240 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_SHIFT 3
21241 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_MASK)
21242 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_MASK 0xC0u
21243 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_SHIFT 6
21244 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_MASK)
21245 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_ODE_MASK 0x800u
21246 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_ODE_SHIFT 11
21247 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PKE_MASK 0x1000u
21248 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PKE_SHIFT 12
21249 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUE_MASK 0x2000u
21250 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUE_SHIFT 13
21251 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_MASK 0xC000u
21252 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_SHIFT 14
21253 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_MASK)
21254 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_HYS_MASK 0x10000u
21255 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_HYS_SHIFT 16
21256 /* SW_PAD_CTL_PAD_RGMII2_RXC Bit Fields */
21257 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SRE_MASK 0x1u
21258 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SRE_SHIFT 0
21259 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_MASK 0x38u
21260 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_SHIFT 3
21261 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_MASK)
21262 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_MASK 0xC0u
21263 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_SHIFT 6
21264 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_MASK)
21265 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_ODE_MASK 0x800u
21266 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_ODE_SHIFT 11
21267 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PKE_MASK 0x1000u
21268 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PKE_SHIFT 12
21269 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUE_MASK 0x2000u
21270 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUE_SHIFT 13
21271 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_MASK 0xC000u
21272 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_SHIFT 14
21273 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_MASK)
21274 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_HYS_MASK 0x10000u
21275 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_HYS_SHIFT 16
21276 /* SW_PAD_CTL_PAD_RGMII2_TD0 Bit Fields */
21277 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SRE_MASK 0x1u
21278 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SRE_SHIFT 0
21279 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_MASK 0x38u
21280 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_SHIFT 3
21281 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_MASK)
21282 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_MASK 0xC0u
21283 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_SHIFT 6
21284 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_MASK)
21285 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_ODE_MASK 0x800u
21286 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_ODE_SHIFT 11
21287 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PKE_MASK 0x1000u
21288 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PKE_SHIFT 12
21289 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUE_MASK 0x2000u
21290 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUE_SHIFT 13
21291 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_MASK 0xC000u
21292 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_SHIFT 14
21293 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_MASK)
21294 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_HYS_MASK 0x10000u
21295 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_HYS_SHIFT 16
21296 /* SW_PAD_CTL_PAD_RGMII2_TD1 Bit Fields */
21297 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SRE_MASK 0x1u
21298 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SRE_SHIFT 0
21299 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_MASK 0x38u
21300 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_SHIFT 3
21301 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_MASK)
21302 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_MASK 0xC0u
21303 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_SHIFT 6
21304 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_MASK)
21305 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_ODE_MASK 0x800u
21306 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_ODE_SHIFT 11
21307 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PKE_MASK 0x1000u
21308 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PKE_SHIFT 12
21309 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUE_MASK 0x2000u
21310 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUE_SHIFT 13
21311 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_MASK 0xC000u
21312 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_SHIFT 14
21313 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_MASK)
21314 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_HYS_MASK 0x10000u
21315 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_HYS_SHIFT 16
21316 /* SW_PAD_CTL_PAD_RGMII2_TD2 Bit Fields */
21317 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SRE_MASK 0x1u
21318 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SRE_SHIFT 0
21319 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_MASK 0x38u
21320 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_SHIFT 3
21321 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_MASK)
21322 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_MASK 0xC0u
21323 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_SHIFT 6
21324 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_MASK)
21325 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_ODE_MASK 0x800u
21326 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_ODE_SHIFT 11
21327 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PKE_MASK 0x1000u
21328 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PKE_SHIFT 12
21329 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUE_MASK 0x2000u
21330 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUE_SHIFT 13
21331 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_MASK 0xC000u
21332 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_SHIFT 14
21333 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_MASK)
21334 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_HYS_MASK 0x10000u
21335 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_HYS_SHIFT 16
21336 /* SW_PAD_CTL_PAD_RGMII2_TD3 Bit Fields */
21337 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SRE_MASK 0x1u
21338 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SRE_SHIFT 0
21339 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_MASK 0x38u
21340 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_SHIFT 3
21341 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_MASK)
21342 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_MASK 0xC0u
21343 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_SHIFT 6
21344 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_MASK)
21345 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_ODE_MASK 0x800u
21346 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_ODE_SHIFT 11
21347 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PKE_MASK 0x1000u
21348 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PKE_SHIFT 12
21349 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUE_MASK 0x2000u
21350 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUE_SHIFT 13
21351 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_MASK 0xC000u
21352 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_SHIFT 14
21353 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_MASK)
21354 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_HYS_MASK 0x10000u
21355 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_HYS_SHIFT 16
21356 /* SW_PAD_CTL_PAD_RGMII2_TX_CTL Bit Fields */
21357 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SRE_MASK 0x1u
21358 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SRE_SHIFT 0
21359 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_MASK 0x38u
21360 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_SHIFT 3
21361 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_MASK)
21362 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_MASK 0xC0u
21363 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_SHIFT 6
21364 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_MASK)
21365 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_ODE_MASK 0x800u
21366 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_ODE_SHIFT 11
21367 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PKE_MASK 0x1000u
21368 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PKE_SHIFT 12
21369 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUE_MASK 0x2000u
21370 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUE_SHIFT 13
21371 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_MASK 0xC000u
21372 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_SHIFT 14
21373 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_MASK)
21374 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_HYS_MASK 0x10000u
21375 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_HYS_SHIFT 16
21376 /* SW_PAD_CTL_PAD_RGMII2_TXC Bit Fields */
21377 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SRE_MASK 0x1u
21378 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SRE_SHIFT 0
21379 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_MASK 0x38u
21380 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_SHIFT 3
21381 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_MASK)
21382 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_MASK 0xC0u
21383 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_SHIFT 6
21384 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_MASK)
21385 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_ODE_MASK 0x800u
21386 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_ODE_SHIFT 11
21387 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PKE_MASK 0x1000u
21388 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PKE_SHIFT 12
21389 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUE_MASK 0x2000u
21390 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUE_SHIFT 13
21391 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_MASK 0xC000u
21392 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_SHIFT 14
21393 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_MASK)
21394 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_HYS_MASK 0x10000u
21395 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_HYS_SHIFT 16
21396 /* SW_PAD_CTL_PAD_SD1_CLK Bit Fields */
21397 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_MASK   0x1u
21398 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_SHIFT  0
21399 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK   0x38u
21400 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT  3
21401 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK)
21402 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_MASK 0xC0u
21403 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_SHIFT 6
21404 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_MASK)
21405 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_MASK   0x800u
21406 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_SHIFT  11
21407 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_MASK   0x1000u
21408 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_SHIFT  12
21409 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_MASK   0x2000u
21410 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_SHIFT  13
21411 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_MASK   0xC000u
21412 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_SHIFT  14
21413 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_MASK)
21414 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_MASK   0x10000u
21415 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_SHIFT  16
21416 /* SW_PAD_CTL_PAD_SD1_CMD Bit Fields */
21417 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_MASK   0x1u
21418 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_SHIFT  0
21419 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK   0x38u
21420 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT  3
21421 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK)
21422 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_MASK 0xC0u
21423 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_SHIFT 6
21424 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_MASK)
21425 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_MASK   0x800u
21426 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_SHIFT  11
21427 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_MASK   0x1000u
21428 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_SHIFT  12
21429 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_MASK   0x2000u
21430 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_SHIFT  13
21431 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_MASK   0xC000u
21432 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_SHIFT  14
21433 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_MASK)
21434 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_MASK   0x10000u
21435 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_SHIFT  16
21436 /* SW_PAD_CTL_PAD_SD1_DATA0 Bit Fields */
21437 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_MASK 0x1u
21438 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_SHIFT 0
21439 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK 0x38u
21440 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT 3
21441 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK)
21442 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_MASK 0xC0u
21443 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_SHIFT 6
21444 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_MASK)
21445 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_MASK 0x800u
21446 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_SHIFT 11
21447 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_MASK 0x1000u
21448 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_SHIFT 12
21449 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_MASK 0x2000u
21450 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_SHIFT 13
21451 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_MASK 0xC000u
21452 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_SHIFT 14
21453 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_MASK)
21454 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_MASK 0x10000u
21455 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_SHIFT 16
21456 /* SW_PAD_CTL_PAD_SD1_DATA1 Bit Fields */
21457 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_MASK 0x1u
21458 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_SHIFT 0
21459 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK 0x38u
21460 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT 3
21461 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK)
21462 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_MASK 0xC0u
21463 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_SHIFT 6
21464 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_MASK)
21465 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_MASK 0x800u
21466 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_SHIFT 11
21467 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_MASK 0x1000u
21468 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_SHIFT 12
21469 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_MASK 0x2000u
21470 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_SHIFT 13
21471 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_MASK 0xC000u
21472 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_SHIFT 14
21473 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_MASK)
21474 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_MASK 0x10000u
21475 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_SHIFT 16
21476 /* SW_PAD_CTL_PAD_SD1_DATA2 Bit Fields */
21477 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_MASK 0x1u
21478 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_SHIFT 0
21479 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK 0x38u
21480 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT 3
21481 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK)
21482 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_MASK 0xC0u
21483 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_SHIFT 6
21484 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_MASK)
21485 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_MASK 0x800u
21486 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_SHIFT 11
21487 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_MASK 0x1000u
21488 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_SHIFT 12
21489 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_MASK 0x2000u
21490 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_SHIFT 13
21491 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_MASK 0xC000u
21492 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_SHIFT 14
21493 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_MASK)
21494 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_MASK 0x10000u
21495 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_SHIFT 16
21496 /* SW_PAD_CTL_PAD_SD1_DATA3 Bit Fields */
21497 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_MASK 0x1u
21498 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_SHIFT 0
21499 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK 0x38u
21500 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT 3
21501 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK)
21502 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_MASK 0xC0u
21503 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_SHIFT 6
21504 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_MASK)
21505 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_MASK 0x800u
21506 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_SHIFT 11
21507 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_MASK 0x1000u
21508 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_SHIFT 12
21509 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_MASK 0x2000u
21510 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_SHIFT 13
21511 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_MASK 0xC000u
21512 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_SHIFT 14
21513 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_MASK)
21514 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_MASK 0x10000u
21515 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_SHIFT 16
21516 /* SW_PAD_CTL_PAD_SD2_CLK Bit Fields */
21517 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_MASK   0x1u
21518 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_SHIFT  0
21519 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK   0x38u
21520 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT  3
21521 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK)
21522 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_MASK 0xC0u
21523 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_SHIFT 6
21524 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_MASK)
21525 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_MASK   0x800u
21526 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_SHIFT  11
21527 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_MASK   0x1000u
21528 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_SHIFT  12
21529 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_MASK   0x2000u
21530 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_SHIFT  13
21531 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_MASK   0xC000u
21532 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_SHIFT  14
21533 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_MASK)
21534 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_MASK   0x10000u
21535 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_SHIFT  16
21536 /* SW_PAD_CTL_PAD_SD2_CMD Bit Fields */
21537 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_MASK   0x1u
21538 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_SHIFT  0
21539 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK   0x38u
21540 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT  3
21541 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK)
21542 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_MASK 0xC0u
21543 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_SHIFT 6
21544 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_MASK)
21545 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_MASK   0x800u
21546 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_SHIFT  11
21547 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_MASK   0x1000u
21548 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_SHIFT  12
21549 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_MASK   0x2000u
21550 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_SHIFT  13
21551 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_MASK   0xC000u
21552 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_SHIFT  14
21553 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_MASK)
21554 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_MASK   0x10000u
21555 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_SHIFT  16
21556 /* SW_PAD_CTL_PAD_SD2_DATA0 Bit Fields */
21557 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_MASK 0x1u
21558 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_SHIFT 0
21559 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK 0x38u
21560 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT 3
21561 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK)
21562 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_MASK 0xC0u
21563 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_SHIFT 6
21564 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_MASK)
21565 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_MASK 0x800u
21566 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_SHIFT 11
21567 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_MASK 0x1000u
21568 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_SHIFT 12
21569 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_MASK 0x2000u
21570 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_SHIFT 13
21571 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_MASK 0xC000u
21572 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_SHIFT 14
21573 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_MASK)
21574 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_MASK 0x10000u
21575 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_SHIFT 16
21576 /* SW_PAD_CTL_PAD_SD2_DATA1 Bit Fields */
21577 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_MASK 0x1u
21578 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_SHIFT 0
21579 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK 0x38u
21580 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT 3
21581 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK)
21582 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_MASK 0xC0u
21583 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_SHIFT 6
21584 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_MASK)
21585 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_MASK 0x800u
21586 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_SHIFT 11
21587 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_MASK 0x1000u
21588 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_SHIFT 12
21589 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_MASK 0x2000u
21590 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_SHIFT 13
21591 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_MASK 0xC000u
21592 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_SHIFT 14
21593 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_MASK)
21594 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_MASK 0x10000u
21595 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_SHIFT 16
21596 /* SW_PAD_CTL_PAD_SD2_DATA2 Bit Fields */
21597 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_MASK 0x1u
21598 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_SHIFT 0
21599 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK 0x38u
21600 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT 3
21601 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK)
21602 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_MASK 0xC0u
21603 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_SHIFT 6
21604 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_MASK)
21605 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_MASK 0x800u
21606 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_SHIFT 11
21607 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_MASK 0x1000u
21608 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_SHIFT 12
21609 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_MASK 0x2000u
21610 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_SHIFT 13
21611 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_MASK 0xC000u
21612 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_SHIFT 14
21613 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_MASK)
21614 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_MASK 0x10000u
21615 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_SHIFT 16
21616 /* SW_PAD_CTL_PAD_SD2_DATA3 Bit Fields */
21617 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_MASK 0x1u
21618 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_SHIFT 0
21619 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK 0x38u
21620 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT 3
21621 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK)
21622 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_MASK 0xC0u
21623 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_SHIFT 6
21624 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_MASK)
21625 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_MASK 0x800u
21626 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_SHIFT 11
21627 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_MASK 0x1000u
21628 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_SHIFT 12
21629 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_MASK 0x2000u
21630 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_SHIFT 13
21631 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_MASK 0xC000u
21632 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_SHIFT 14
21633 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_MASK)
21634 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_MASK 0x10000u
21635 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_SHIFT 16
21636 /* SW_PAD_CTL_PAD_SD3_CLK Bit Fields */
21637 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_MASK   0x1u
21638 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_SHIFT  0
21639 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK   0x38u
21640 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT  3
21641 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK)
21642 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_MASK 0xC0u
21643 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_SHIFT 6
21644 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_MASK)
21645 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_MASK   0x800u
21646 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_SHIFT  11
21647 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_MASK   0x1000u
21648 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_SHIFT  12
21649 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_MASK   0x2000u
21650 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_SHIFT  13
21651 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_MASK   0xC000u
21652 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_SHIFT  14
21653 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_MASK)
21654 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_MASK   0x10000u
21655 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_SHIFT  16
21656 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_LVE_MASK   0x400000u
21657 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_LVE_SHIFT  22
21658 /* SW_PAD_CTL_PAD_SD3_CMD Bit Fields */
21659 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_MASK   0x1u
21660 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_SHIFT  0
21661 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK   0x38u
21662 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT  3
21663 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK)
21664 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_MASK 0xC0u
21665 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_SHIFT 6
21666 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_MASK)
21667 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_MASK   0x800u
21668 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_SHIFT  11
21669 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_MASK   0x1000u
21670 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_SHIFT  12
21671 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_MASK   0x2000u
21672 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_SHIFT  13
21673 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_MASK   0xC000u
21674 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_SHIFT  14
21675 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_MASK)
21676 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_MASK   0x10000u
21677 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_SHIFT  16
21678 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_LVE_MASK   0x400000u
21679 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_LVE_SHIFT  22
21680 /* SW_PAD_CTL_PAD_SD3_DATA0 Bit Fields */
21681 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_MASK 0x1u
21682 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_SHIFT 0
21683 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK 0x38u
21684 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT 3
21685 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK)
21686 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_MASK 0xC0u
21687 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_SHIFT 6
21688 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_MASK)
21689 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_MASK 0x800u
21690 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_SHIFT 11
21691 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_MASK 0x1000u
21692 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_SHIFT 12
21693 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_MASK 0x2000u
21694 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_SHIFT 13
21695 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_MASK 0xC000u
21696 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_SHIFT 14
21697 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_MASK)
21698 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_MASK 0x10000u
21699 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_SHIFT 16
21700 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_LVE_MASK 0x400000u
21701 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_LVE_SHIFT 22
21702 /* SW_PAD_CTL_PAD_SD3_DATA1 Bit Fields */
21703 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_MASK 0x1u
21704 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_SHIFT 0
21705 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK 0x38u
21706 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT 3
21707 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK)
21708 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_MASK 0xC0u
21709 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_SHIFT 6
21710 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_MASK)
21711 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_MASK 0x800u
21712 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_SHIFT 11
21713 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_MASK 0x1000u
21714 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_SHIFT 12
21715 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_MASK 0x2000u
21716 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_SHIFT 13
21717 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_MASK 0xC000u
21718 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_SHIFT 14
21719 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_MASK)
21720 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_MASK 0x10000u
21721 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_SHIFT 16
21722 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_LVE_MASK 0x400000u
21723 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_LVE_SHIFT 22
21724 /* SW_PAD_CTL_PAD_SD3_DATA2 Bit Fields */
21725 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_MASK 0x1u
21726 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_SHIFT 0
21727 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK 0x38u
21728 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT 3
21729 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK)
21730 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_MASK 0xC0u
21731 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_SHIFT 6
21732 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_MASK)
21733 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_MASK 0x800u
21734 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_SHIFT 11
21735 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_MASK 0x1000u
21736 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_SHIFT 12
21737 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_MASK 0x2000u
21738 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_SHIFT 13
21739 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_MASK 0xC000u
21740 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_SHIFT 14
21741 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_MASK)
21742 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_MASK 0x10000u
21743 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_SHIFT 16
21744 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_LVE_MASK 0x400000u
21745 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_LVE_SHIFT 22
21746 /* SW_PAD_CTL_PAD_SD3_DATA3 Bit Fields */
21747 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_MASK 0x1u
21748 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_SHIFT 0
21749 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK 0x38u
21750 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT 3
21751 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK)
21752 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_MASK 0xC0u
21753 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_SHIFT 6
21754 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_MASK)
21755 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_MASK 0x800u
21756 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_SHIFT 11
21757 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_MASK 0x1000u
21758 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_SHIFT 12
21759 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_MASK 0x2000u
21760 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_SHIFT 13
21761 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_MASK 0xC000u
21762 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_SHIFT 14
21763 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_MASK)
21764 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_MASK 0x10000u
21765 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_SHIFT 16
21766 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_LVE_MASK 0x400000u
21767 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_LVE_SHIFT 22
21768 /* SW_PAD_CTL_PAD_SD3_DATA4 Bit Fields */
21769 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_MASK 0x1u
21770 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_SHIFT 0
21771 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK 0x38u
21772 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT 3
21773 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK)
21774 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_MASK 0xC0u
21775 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_SHIFT 6
21776 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_MASK)
21777 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_MASK 0x800u
21778 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_SHIFT 11
21779 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_MASK 0x1000u
21780 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_SHIFT 12
21781 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_MASK 0x2000u
21782 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_SHIFT 13
21783 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_MASK 0xC000u
21784 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_SHIFT 14
21785 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_MASK)
21786 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_MASK 0x10000u
21787 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_SHIFT 16
21788 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_LVE_MASK 0x400000u
21789 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_LVE_SHIFT 22
21790 /* SW_PAD_CTL_PAD_SD3_DATA5 Bit Fields */
21791 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_MASK 0x1u
21792 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_SHIFT 0
21793 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK 0x38u
21794 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT 3
21795 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK)
21796 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_MASK 0xC0u
21797 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_SHIFT 6
21798 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_MASK)
21799 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_MASK 0x800u
21800 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_SHIFT 11
21801 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_MASK 0x1000u
21802 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_SHIFT 12
21803 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_MASK 0x2000u
21804 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_SHIFT 13
21805 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_MASK 0xC000u
21806 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_SHIFT 14
21807 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_MASK)
21808 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_MASK 0x10000u
21809 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_SHIFT 16
21810 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_LVE_MASK 0x400000u
21811 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_LVE_SHIFT 22
21812 /* SW_PAD_CTL_PAD_SD3_DATA6 Bit Fields */
21813 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_MASK 0x1u
21814 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_SHIFT 0
21815 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK 0x38u
21816 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT 3
21817 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK)
21818 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_MASK 0xC0u
21819 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_SHIFT 6
21820 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_MASK)
21821 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_MASK 0x800u
21822 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_SHIFT 11
21823 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_MASK 0x1000u
21824 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_SHIFT 12
21825 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_MASK 0x2000u
21826 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_SHIFT 13
21827 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_MASK 0xC000u
21828 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_SHIFT 14
21829 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_MASK)
21830 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_MASK 0x10000u
21831 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_SHIFT 16
21832 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_LVE_MASK 0x400000u
21833 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_LVE_SHIFT 22
21834 /* SW_PAD_CTL_PAD_SD3_DATA7 Bit Fields */
21835 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_MASK 0x1u
21836 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_SHIFT 0
21837 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK 0x38u
21838 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT 3
21839 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK)
21840 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_MASK 0xC0u
21841 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_SHIFT 6
21842 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_MASK)
21843 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_MASK 0x800u
21844 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_SHIFT 11
21845 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_MASK 0x1000u
21846 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_SHIFT 12
21847 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_MASK 0x2000u
21848 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_SHIFT 13
21849 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_MASK 0xC000u
21850 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_SHIFT 14
21851 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_MASK)
21852 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_MASK 0x10000u
21853 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_SHIFT 16
21854 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_LVE_MASK 0x400000u
21855 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_LVE_SHIFT 22
21856 /* SW_PAD_CTL_PAD_SD4_CLK Bit Fields */
21857 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_MASK   0x1u
21858 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_SHIFT  0
21859 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_MASK   0x38u
21860 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_SHIFT  3
21861 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_MASK)
21862 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_MASK 0xC0u
21863 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_SHIFT 6
21864 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_MASK)
21865 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_MASK   0x800u
21866 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_SHIFT  11
21867 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_MASK   0x1000u
21868 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_SHIFT  12
21869 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_MASK   0x2000u
21870 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_SHIFT  13
21871 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_MASK   0xC000u
21872 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_SHIFT  14
21873 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_MASK)
21874 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_MASK   0x10000u
21875 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_SHIFT  16
21876 /* SW_PAD_CTL_PAD_SD4_CMD Bit Fields */
21877 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_MASK   0x1u
21878 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_SHIFT  0
21879 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_MASK   0x38u
21880 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_SHIFT  3
21881 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_MASK)
21882 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_MASK 0xC0u
21883 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_SHIFT 6
21884 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_MASK)
21885 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_MASK   0x800u
21886 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_SHIFT  11
21887 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_MASK   0x1000u
21888 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_SHIFT  12
21889 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_MASK   0x2000u
21890 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_SHIFT  13
21891 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_MASK   0xC000u
21892 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_SHIFT  14
21893 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_MASK)
21894 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_MASK   0x10000u
21895 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_SHIFT  16
21896 /* SW_PAD_CTL_PAD_SD4_DATA0 Bit Fields */
21897 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_MASK 0x1u
21898 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_SHIFT 0
21899 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_MASK 0x38u
21900 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_SHIFT 3
21901 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_MASK)
21902 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_MASK 0xC0u
21903 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_SHIFT 6
21904 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_MASK)
21905 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_MASK 0x800u
21906 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_SHIFT 11
21907 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_MASK 0x1000u
21908 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_SHIFT 12
21909 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_MASK 0x2000u
21910 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_SHIFT 13
21911 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_MASK 0xC000u
21912 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_SHIFT 14
21913 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_MASK)
21914 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_MASK 0x10000u
21915 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_SHIFT 16
21916 /* SW_PAD_CTL_PAD_SD4_DATA1 Bit Fields */
21917 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_MASK 0x1u
21918 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_SHIFT 0
21919 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_MASK 0x38u
21920 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_SHIFT 3
21921 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_MASK)
21922 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_MASK 0xC0u
21923 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_SHIFT 6
21924 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_MASK)
21925 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_MASK 0x800u
21926 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_SHIFT 11
21927 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_MASK 0x1000u
21928 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_SHIFT 12
21929 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_MASK 0x2000u
21930 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_SHIFT 13
21931 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_MASK 0xC000u
21932 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_SHIFT 14
21933 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_MASK)
21934 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_MASK 0x10000u
21935 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_SHIFT 16
21936 /* SW_PAD_CTL_PAD_SD4_DATA2 Bit Fields */
21937 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_MASK 0x1u
21938 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_SHIFT 0
21939 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_MASK 0x38u
21940 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_SHIFT 3
21941 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_MASK)
21942 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_MASK 0xC0u
21943 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_SHIFT 6
21944 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_MASK)
21945 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_MASK 0x800u
21946 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_SHIFT 11
21947 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_MASK 0x1000u
21948 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_SHIFT 12
21949 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_MASK 0x2000u
21950 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_SHIFT 13
21951 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_MASK 0xC000u
21952 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_SHIFT 14
21953 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_MASK)
21954 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_MASK 0x10000u
21955 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_SHIFT 16
21956 /* SW_PAD_CTL_PAD_SD4_DATA3 Bit Fields */
21957 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_MASK 0x1u
21958 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_SHIFT 0
21959 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_MASK 0x38u
21960 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_SHIFT 3
21961 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_MASK)
21962 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_MASK 0xC0u
21963 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_SHIFT 6
21964 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_MASK)
21965 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_MASK 0x800u
21966 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_SHIFT 11
21967 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_MASK 0x1000u
21968 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_SHIFT 12
21969 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_MASK 0x2000u
21970 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_SHIFT 13
21971 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_MASK 0xC000u
21972 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_SHIFT 14
21973 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_MASK)
21974 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_MASK 0x10000u
21975 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_SHIFT 16
21976 /* SW_PAD_CTL_PAD_SD4_DATA4 Bit Fields */
21977 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_MASK 0x1u
21978 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_SHIFT 0
21979 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_MASK 0x38u
21980 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_SHIFT 3
21981 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_MASK)
21982 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_MASK 0xC0u
21983 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_SHIFT 6
21984 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_MASK)
21985 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_MASK 0x800u
21986 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_SHIFT 11
21987 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_MASK 0x1000u
21988 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_SHIFT 12
21989 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_MASK 0x2000u
21990 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_SHIFT 13
21991 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_MASK 0xC000u
21992 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_SHIFT 14
21993 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_MASK)
21994 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_MASK 0x10000u
21995 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_SHIFT 16
21996 /* SW_PAD_CTL_PAD_SD4_DATA5 Bit Fields */
21997 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_MASK 0x1u
21998 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_SHIFT 0
21999 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_MASK 0x38u
22000 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_SHIFT 3
22001 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_MASK)
22002 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_MASK 0xC0u
22003 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_SHIFT 6
22004 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_MASK)
22005 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_MASK 0x800u
22006 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_SHIFT 11
22007 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_MASK 0x1000u
22008 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_SHIFT 12
22009 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_MASK 0x2000u
22010 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_SHIFT 13
22011 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_MASK 0xC000u
22012 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_SHIFT 14
22013 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_MASK)
22014 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_MASK 0x10000u
22015 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_SHIFT 16
22016 /* SW_PAD_CTL_PAD_SD4_DATA6 Bit Fields */
22017 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_MASK 0x1u
22018 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_SHIFT 0
22019 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_MASK 0x38u
22020 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_SHIFT 3
22021 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_MASK)
22022 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_MASK 0xC0u
22023 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_SHIFT 6
22024 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_MASK)
22025 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_MASK 0x800u
22026 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_SHIFT 11
22027 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_MASK 0x1000u
22028 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_SHIFT 12
22029 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_MASK 0x2000u
22030 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_SHIFT 13
22031 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_MASK 0xC000u
22032 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_SHIFT 14
22033 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_MASK)
22034 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_MASK 0x10000u
22035 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_SHIFT 16
22036 /* SW_PAD_CTL_PAD_SD4_DATA7 Bit Fields */
22037 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_MASK 0x1u
22038 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_SHIFT 0
22039 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_MASK 0x38u
22040 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_SHIFT 3
22041 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_MASK)
22042 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_MASK 0xC0u
22043 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_SHIFT 6
22044 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_MASK)
22045 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_MASK 0x800u
22046 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_SHIFT 11
22047 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_MASK 0x1000u
22048 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_SHIFT 12
22049 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_MASK 0x2000u
22050 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_SHIFT 13
22051 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_MASK 0xC000u
22052 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_SHIFT 14
22053 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_MASK)
22054 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_MASK 0x10000u
22055 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_SHIFT 16
22056 /* SW_PAD_CTL_PAD_SD4_RESET_B Bit Fields */
22057 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SRE_MASK 0x1u
22058 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SRE_SHIFT 0
22059 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_MASK 0x38u
22060 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_SHIFT 3
22061 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_MASK)
22062 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_MASK 0xC0u
22063 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_SHIFT 6
22064 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_MASK)
22065 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_ODE_MASK 0x800u
22066 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_ODE_SHIFT 11
22067 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PKE_MASK 0x1000u
22068 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PKE_SHIFT 12
22069 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUE_MASK 0x2000u
22070 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUE_SHIFT 13
22071 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_MASK 0xC000u
22072 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_SHIFT 14
22073 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_MASK)
22074 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_HYS_MASK 0x10000u
22075 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_HYS_SHIFT 16
22076 /* SW_PAD_CTL_PAD_USB_H_DATA Bit Fields */
22077 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_MASK 0x38u
22078 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_SHIFT 3
22079 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_MASK)
22080 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_MASK 0x700u
22081 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_SHIFT 8
22082 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_MASK)
22083 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PKE_MASK 0x1000u
22084 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PKE_SHIFT 12
22085 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUE_MASK 0x2000u
22086 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUE_SHIFT 13
22087 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_MASK 0xC000u
22088 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_SHIFT 14
22089 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_MASK)
22090 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_HYS_MASK 0x10000u
22091 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_HYS_SHIFT 16
22092 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_INPUT_MASK 0x20000u
22093 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_INPUT_SHIFT 17
22094 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_MASK 0xC0000u
22095 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_SHIFT 18
22096 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_MASK)
22097 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_MASK 0x300000u
22098 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_SHIFT 20
22099 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_MASK)
22100 /* SW_PAD_CTL_PAD_USB_H_STROBE Bit Fields */
22101 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_MASK 0x38u
22102 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_SHIFT 3
22103 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_MASK)
22104 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_MASK 0x700u
22105 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_SHIFT 8
22106 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_MASK)
22107 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PKE_MASK 0x1000u
22108 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PKE_SHIFT 12
22109 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUE_MASK 0x2000u
22110 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUE_SHIFT 13
22111 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_MASK 0xC000u
22112 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_SHIFT 14
22113 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_MASK)
22114 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_HYS_MASK 0x10000u
22115 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_HYS_SHIFT 16
22116 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_INPUT_MASK 0x20000u
22117 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_INPUT_SHIFT 17
22118 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_MASK 0xC0000u
22119 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_SHIFT 18
22120 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_MASK)
22121 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_MASK 0x300000u
22122 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_SHIFT 20
22123 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_MASK)
22124 /* SW_PAD_CTL_GRP_ADDDS Bit Fields */
22125 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_MASK     0x38u
22126 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_SHIFT    3
22127 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_MASK)
22128 /* SW_PAD_CTL_GRP_DDRMODE_CTL Bit Fields */
22129 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_MASK 0x20000u
22130 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_SHIFT 17
22131 /* SW_PAD_CTL_GRP_DDRPKE Bit Fields */
22132 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_MASK    0x1000u
22133 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_SHIFT   12
22134 /* SW_PAD_CTL_GRP_DDRPK Bit Fields */
22135 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_MASK     0x2000u
22136 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_SHIFT    13
22137 /* SW_PAD_CTL_GRP_DDRHYS Bit Fields */
22138 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_MASK    0x10000u
22139 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_SHIFT   16
22140 /* SW_PAD_CTL_GRP_DDRMODE Bit Fields */
22141 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_MASK 0x20000u
22142 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_SHIFT 17
22143 /* SW_PAD_CTL_GRP_B0DS Bit Fields */
22144 #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_MASK      0x38u
22145 #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_SHIFT     3
22146 #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_MASK)
22147 /* SW_PAD_CTL_GRP_B1DS Bit Fields */
22148 #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_MASK      0x38u
22149 #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_SHIFT     3
22150 #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_MASK)
22151 /* SW_PAD_CTL_GRP_CTLDS Bit Fields */
22152 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_MASK     0x38u
22153 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_SHIFT    3
22154 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_MASK)
22155 /* SW_PAD_CTL_GRP_DDR_TYPE Bit Fields */
22156 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_MASK 0xC0000u
22157 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_SHIFT 18
22158 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_MASK)
22159 /* SW_PAD_CTL_GRP_B2DS Bit Fields */
22160 #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_MASK      0x38u
22161 #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_SHIFT     3
22162 #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_MASK)
22163 /* SW_PAD_CTL_GRP_B3DS Bit Fields */
22164 #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_MASK      0x38u
22165 #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_SHIFT     3
22166 #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_MASK)
22167 /* ANATOP_USB_OTG_ID_SELECT_INPUT Bit Fields */
22168 #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_MASK 0x3u
22169 #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_SHIFT 0
22170 #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_MASK)
22171 /* ANATOP_USB_UH1_ID_SELECT_INPUT Bit Fields */
22172 #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_MASK 0x3u
22173 #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_SHIFT 0
22174 #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_MASK)
22175 /* AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT Bit Fields */
22176 #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22177 #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0
22178 /* AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT Bit Fields */
22179 #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22180 #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0
22181 /* AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */
22182 #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22183 #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22184 /* AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */
22185 #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22186 #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22187 /* AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */
22188 #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22189 #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22190 /* AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */
22191 #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22192 #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22193 /* AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT Bit Fields */
22194 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22195 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0
22196 /* AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT Bit Fields */
22197 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22198 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0
22199 /* AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */
22200 #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22201 #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22202 /* AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */
22203 #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22204 #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22205 /* AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */
22206 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22207 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22208 /* AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */
22209 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22210 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22211 /* AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT Bit Fields */
22212 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22213 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0
22214 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK)
22215 /* AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT Bit Fields */
22216 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22217 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0
22218 /* AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */
22219 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22220 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22221 /* AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */
22222 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22223 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22224 /* AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */
22225 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22226 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22227 /* AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */
22228 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u
22229 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22230 /* AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT Bit Fields */
22231 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22232 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0
22233 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK)
22234 /* AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT Bit Fields */
22235 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22236 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0
22237 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK)
22238 /* AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */
22239 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22240 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22241 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK)
22242 /* AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */
22243 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22244 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22245 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK)
22246 /* AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */
22247 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22248 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0
22249 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK)
22250 /* AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */
22251 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x3u
22252 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0
22253 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK)
22254 /* CAN1_IPP_IND_CANRX_SELECT_INPUT Bit Fields */
22255 #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK 0x3u
22256 #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT 0
22257 #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK)
22258 /* CAN2_IPP_IND_CANRX_SELECT_INPUT Bit Fields */
22259 #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK 0x3u
22260 #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT 0
22261 #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK)
22262 /* CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT Bit Fields */
22263 #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_MASK 0x3u
22264 #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_SHIFT 0
22265 #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_MASK)
22266 /* CSI1_IPP_CSI_D_SELECT_INPUT_0 Bit Fields */
22267 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_DAISY_MASK 0x1u
22268 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_DAISY_SHIFT 0
22269 /* CSI1_IPP_CSI_D_SELECT_INPUT_1 Bit Fields */
22270 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_DAISY_MASK 0x1u
22271 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_DAISY_SHIFT 0
22272 /* CSI1_IPP_CSI_D_SELECT_INPUT_2 Bit Fields */
22273 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_DAISY_MASK 0x1u
22274 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_DAISY_SHIFT 0
22275 /* CSI1_IPP_CSI_D_SELECT_INPUT_3 Bit Fields */
22276 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_DAISY_MASK 0x1u
22277 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_DAISY_SHIFT 0
22278 /* CSI1_IPP_CSI_D_SELECT_INPUT_4 Bit Fields */
22279 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_DAISY_MASK 0x1u
22280 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_DAISY_SHIFT 0
22281 /* CSI1_IPP_CSI_D_SELECT_INPUT_5 Bit Fields */
22282 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_DAISY_MASK 0x1u
22283 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_DAISY_SHIFT 0
22284 /* CSI1_IPP_CSI_D_SELECT_INPUT_6 Bit Fields */
22285 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_DAISY_MASK 0x1u
22286 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_DAISY_SHIFT 0
22287 /* CSI1_IPP_CSI_D_SELECT_INPUT_7 Bit Fields */
22288 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_DAISY_MASK 0x1u
22289 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_DAISY_SHIFT 0
22290 /* CSI1_IPP_CSI_D_SELECT_INPUT_8 Bit Fields */
22291 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_DAISY_MASK 0x1u
22292 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_DAISY_SHIFT 0
22293 /* CSI1_IPP_CSI_D_SELECT_INPUT_9 Bit Fields */
22294 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_DAISY_MASK 0x1u
22295 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_DAISY_SHIFT 0
22296 /* CSI1_IPP_CSI_D_SELECT_INPUT_11 Bit Fields */
22297 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_DAISY_MASK 0x1u
22298 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_DAISY_SHIFT 0
22299 /* CSI1_IPP_CSI_D_SELECT_INPUT_12 Bit Fields */
22300 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_DAISY_MASK 0x1u
22301 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_DAISY_SHIFT 0
22302 /* CSI1_IPP_CSI_D_SELECT_INPUT_13 Bit Fields */
22303 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_DAISY_MASK 0x1u
22304 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_DAISY_SHIFT 0
22305 /* CSI1_IPP_CSI_D_SELECT_INPUT_14 Bit Fields */
22306 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_DAISY_MASK 0x1u
22307 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_DAISY_SHIFT 0
22308 /* CSI1_IPP_CSI_D_SELECT_INPUT_15 Bit Fields */
22309 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_DAISY_MASK 0x1u
22310 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_DAISY_SHIFT 0
22311 /* CSI1_IPP_CSI_D_SELECT_INPUT_16 Bit Fields */
22312 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_DAISY_MASK 0x1u
22313 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_DAISY_SHIFT 0
22314 /* CSI1_IPP_CSI_D_SELECT_INPUT_17 Bit Fields */
22315 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_DAISY_MASK 0x1u
22316 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_DAISY_SHIFT 0
22317 /* CSI1_IPP_CSI_D_SELECT_INPUT_18 Bit Fields */
22318 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_DAISY_MASK 0x1u
22319 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_DAISY_SHIFT 0
22320 /* CSI1_IPP_CSI_D_SELECT_INPUT_19 Bit Fields */
22321 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_DAISY_MASK 0x1u
22322 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_DAISY_SHIFT 0
22323 /* CSI1_IPP_CSI_D_SELECT_INPUT_20 Bit Fields */
22324 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_DAISY_MASK 0x1u
22325 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_DAISY_SHIFT 0
22326 /* CSI1_IPP_CSI_D_SELECT_INPUT_21 Bit Fields */
22327 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_DAISY_MASK 0x1u
22328 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_DAISY_SHIFT 0
22329 /* CSI1_IPP_CSI_D_SELECT_INPUT_22 Bit Fields */
22330 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_DAISY_MASK 0x1u
22331 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_DAISY_SHIFT 0
22332 /* CSI1_IPP_CSI_D_SELECT_INPUT_23 Bit Fields */
22333 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_DAISY_MASK 0x1u
22334 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_DAISY_SHIFT 0
22335 /* CSI1_IPP_CSI_D_SELECT_INPUT_10 Bit Fields */
22336 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_DAISY_MASK 0x1u
22337 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_DAISY_SHIFT 0
22338 /* CSI1_IPP_CSI_HSYNC_SELECT_INPUT Bit Fields */
22339 #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22340 #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_DAISY_SHIFT 0
22341 /* CSI1_IPP_CSI_PIXCLK_SELECT_INPUT Bit Fields */
22342 #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_DAISY_MASK 0x1u
22343 #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_DAISY_SHIFT 0
22344 /* CSI1_IPP_CSI_VSYNC_SELECT_INPUT Bit Fields */
22345 #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22346 #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_DAISY_SHIFT 0
22347 /* CSI1_TVDECODER_IN_FIELD_SELECT_INPUT Bit Fields */
22348 #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_DAISY_MASK 0x1u
22349 #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_DAISY_SHIFT 0
22350 /* ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */
22351 #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
22352 #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22353 /* ECSPI1_IPP_IND_MISO_SELECT_INPUT Bit Fields */
22354 #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u
22355 #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0
22356 /* ECSPI1_IPP_IND_MOSI_SELECT_INPUT Bit Fields */
22357 #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
22358 #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0
22359 /* ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */
22360 #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u
22361 #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0
22362 /* ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */
22363 #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
22364 #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22365 /* ECSPI2_IPP_IND_MISO_SELECT_INPUT Bit Fields */
22366 #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u
22367 #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0
22368 /* ECSPI2_IPP_IND_MOSI_SELECT_INPUT Bit Fields */
22369 #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
22370 #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0
22371 /* ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */
22372 #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u
22373 #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0
22374 /* ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */
22375 #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
22376 #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22377 /* ECSPI3_IPP_IND_MISO_SELECT_INPUT Bit Fields */
22378 #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u
22379 #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0
22380 /* ECSPI3_IPP_IND_MOSI_SELECT_INPUT Bit Fields */
22381 #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
22382 #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0
22383 /* ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */
22384 #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u
22385 #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0
22386 /* ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */
22387 #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
22388 #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22389 /* ECSPI4_IPP_IND_MISO_SELECT_INPUT Bit Fields */
22390 #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u
22391 #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0
22392 /* ECSPI4_IPP_IND_MOSI_SELECT_INPUT Bit Fields */
22393 #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
22394 #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0
22395 /* ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */
22396 #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u
22397 #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0
22398 /* ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */
22399 #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
22400 #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22401 /* ECSPI5_IPP_IND_MISO_SELECT_INPUT Bit Fields */
22402 #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u
22403 #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0
22404 /* ECSPI5_IPP_IND_MOSI_SELECT_INPUT Bit Fields */
22405 #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u
22406 #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0
22407 /* ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */
22408 #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u
22409 #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0
22410 /* ENET1_IPG_CLK_RMII_SELECT_INPUT Bit Fields */
22411 #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_DAISY_MASK 0x1u
22412 #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_DAISY_SHIFT 0
22413 /* ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT Bit Fields */
22414 #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK 0x3u
22415 #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT 0
22416 #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK)
22417 /* ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT Bit Fields */
22418 #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_MASK 0x1u
22419 #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_SHIFT 0
22420 /* ENET2_IPG_CLK_RMII_SELECT_INPUT Bit Fields */
22421 #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_DAISY_MASK 0x1u
22422 #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_DAISY_SHIFT 0
22423 /* ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT Bit Fields */
22424 #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK 0x3u
22425 #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT 0
22426 #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK)
22427 /* ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT Bit Fields */
22428 #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_MASK 0x1u
22429 #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_SHIFT 0
22430 /* ESAI_IPP_IND_FSR_SELECT_INPUT Bit Fields */
22431 #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_MASK 0x3u
22432 #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_SHIFT 0
22433 #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_MASK)
22434 /* ESAI_IPP_IND_FST_SELECT_INPUT Bit Fields */
22435 #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK 0x3u
22436 #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT 0
22437 #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK)
22438 /* ESAI_IPP_IND_HCKR_SELECT_INPUT Bit Fields */
22439 #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_MASK 0x3u
22440 #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_SHIFT 0
22441 #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_MASK)
22442 /* ESAI_IPP_IND_HCKT_SELECT_INPUT Bit Fields */
22443 #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_MASK 0x3u
22444 #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_SHIFT 0
22445 #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_MASK)
22446 /* ESAI_IPP_IND_SCKR_SELECT_INPUT Bit Fields */
22447 #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_MASK 0x3u
22448 #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_SHIFT 0
22449 #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_MASK)
22450 /* ESAI_IPP_IND_SCKT_SELECT_INPUT Bit Fields */
22451 #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK 0x3u
22452 #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT 0
22453 #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK)
22454 /* ESAI_IPP_IND_SDO0_SELECT_INPUT Bit Fields */
22455 #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK 0x3u
22456 #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT 0
22457 #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK)
22458 /* ESAI_IPP_IND_SDO1_SELECT_INPUT Bit Fields */
22459 #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK 0x3u
22460 #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT 0
22461 #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK)
22462 /* ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT Bit Fields */
22463 #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_MASK 0x3u
22464 #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_SHIFT 0
22465 #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_MASK)
22466 /* ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT Bit Fields */
22467 #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_MASK 0x3u
22468 #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_SHIFT 0
22469 #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_MASK)
22470 /* ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT Bit Fields */
22471 #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_MASK 0x3u
22472 #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_SHIFT 0
22473 #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_MASK)
22474 /* ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT Bit Fields */
22475 #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK 0x3u
22476 #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT 0
22477 #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK)
22478 /* I2C1_IPP_SCL_IN_SELECT_INPUT Bit Fields */
22479 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x1u
22480 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0
22481 /* I2C1_IPP_SDA_IN_SELECT_INPUT Bit Fields */
22482 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x1u
22483 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0
22484 /* I2C2_IPP_SCL_IN_SELECT_INPUT Bit Fields */
22485 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u
22486 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0
22487 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK)
22488 /* I2C2_IPP_SDA_IN_SELECT_INPUT Bit Fields */
22489 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u
22490 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0
22491 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK)
22492 /* I2C3_IPP_SCL_IN_SELECT_INPUT Bit Fields */
22493 #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u
22494 #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0
22495 #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK)
22496 /* I2C3_IPP_SDA_IN_SELECT_INPUT Bit Fields */
22497 #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u
22498 #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0
22499 #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK)
22500 /* I2C4_IPP_SCL_IN_SELECT_INPUT Bit Fields */
22501 #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u
22502 #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0
22503 #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK)
22504 /* I2C4_IPP_SDA_IN_SELECT_INPUT Bit Fields */
22505 #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u
22506 #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0
22507 #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK)
22508 /* KPP_IPP_IND_COL_SELECT_INPUT_5 Bit Fields */
22509 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_DAISY_MASK 0x1u
22510 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_DAISY_SHIFT 0
22511 /* KPP_IPP_IND_COL_SELECT_INPUT_6 Bit Fields */
22512 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_DAISY_MASK 0x1u
22513 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_DAISY_SHIFT 0
22514 /* KPP_IPP_IND_COL_SELECT_INPUT_7 Bit Fields */
22515 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_DAISY_MASK 0x1u
22516 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_DAISY_SHIFT 0
22517 /* KPP_IPP_IND_ROW_SELECT_INPUT_5 Bit Fields */
22518 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_DAISY_MASK 0x1u
22519 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_DAISY_SHIFT 0
22520 /* KPP_IPP_IND_ROW_SELECT_INPUT_6 Bit Fields */
22521 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_DAISY_MASK 0x1u
22522 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_DAISY_SHIFT 0
22523 /* KPP_IPP_IND_ROW_SELECT_INPUT_7 Bit Fields */
22524 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_DAISY_MASK 0x1u
22525 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_DAISY_SHIFT 0
22526 /* LCD1_BUSY_SELECT_INPUT Bit Fields */
22527 #define IOMUXC_LCD1_BUSY_SELECT_INPUT_DAISY_MASK 0x1u
22528 #define IOMUXC_LCD1_BUSY_SELECT_INPUT_DAISY_SHIFT 0
22529 /* LCD2_BUSY_SELECT_INPUT Bit Fields */
22530 #define IOMUXC_LCD2_BUSY_SELECT_INPUT_DAISY_MASK 0x1u
22531 #define IOMUXC_LCD2_BUSY_SELECT_INPUT_DAISY_SHIFT 0
22532 /* MLB_MLB_CLK_IN_SELECT_INPUT Bit Fields */
22533 #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_MASK 0x3u
22534 #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0
22535 #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_MASK)
22536 /* MLB_MLB_DATA_IN_SELECT_INPUT Bit Fields */
22537 #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_MASK 0x3u
22538 #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_SHIFT 0
22539 #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_MASK)
22540 /* MLB_MLB_SIG_IN_SELECT_INPUT Bit Fields */
22541 #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_MASK 0x3u
22542 #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_SHIFT 0
22543 #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_MASK)
22544 /* SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT Bit Fields */
22545 #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK 0x1u
22546 #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT 0
22547 /* SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 Bit Fields */
22548 #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_MASK 0x1u
22549 #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_SHIFT 0
22550 /* SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT Bit Fields */
22551 #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22552 #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT 0
22553 /* SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT Bit Fields */
22554 #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_MASK 0x1u
22555 #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_SHIFT 0
22556 /* SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */
22557 #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22558 #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0
22559 /* SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT Bit Fields */
22560 #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK 0x1u
22561 #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT 0
22562 /* SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 Bit Fields */
22563 #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_MASK 0x1u
22564 #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_SHIFT 0
22565 /* SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT Bit Fields */
22566 #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22567 #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT 0
22568 /* SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT Bit Fields */
22569 #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_MASK 0x1u
22570 #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_SHIFT 0
22571 /* SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */
22572 #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
22573 #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0
22574 /* SDMA_EVENTS_SELECT_INPUT_14 Bit Fields */
22575 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_MASK 0x3u
22576 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_SHIFT 0
22577 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_MASK)
22578 /* SDMA_EVENTS_SELECT_INPUT_15 Bit Fields */
22579 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_DAISY_MASK 0x1u
22580 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_DAISY_SHIFT 0
22581 /* SPDIF_SPDIF_IN1_SELECT_INPUT Bit Fields */
22582 #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_MASK 0x7u
22583 #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_SHIFT 0
22584 #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_MASK)
22585 /* SPDIF_TX_CLK2_SELECT_INPUT Bit Fields */
22586 #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_MASK 0x1u
22587 #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_SHIFT 0
22588 /* UART1_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22589 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
22590 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22591 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22592 /* UART1_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22593 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u
22594 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22595 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22596 /* UART2_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22597 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
22598 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22599 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22600 /* UART2_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22601 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u
22602 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22603 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22604 /* UART3_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22605 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u
22606 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22607 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22608 /* UART3_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22609 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u
22610 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22611 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22612 /* UART4_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22613 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
22614 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22615 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22616 /* UART4_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22617 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u
22618 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22619 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22620 /* UART5_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22621 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
22622 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22623 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22624 /* UART5_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22625 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u
22626 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22627 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22628 /* UART6_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */
22629 #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u
22630 #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0
22631 #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK)
22632 /* UART6_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */
22633 #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u
22634 #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0
22635 #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK)
22636 /* USB_IPP_IND_OTG2_OC_SELECT_INPUT Bit Fields */
22637 #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_MASK 0x3u
22638 #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_SHIFT 0
22639 #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_MASK)
22640 /* USB_IPP_IND_OTG_OC_SELECT_INPUT Bit Fields */
22641 #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_MASK 0x3u
22642 #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_SHIFT 0
22643 #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_MASK)
22644 /* USDHC1_IPP_CARD_DET_SELECT_INPUT Bit Fields */
22645 #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u
22646 #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0
22647 /* USDHC1_IPP_WP_ON_SELECT_INPUT Bit Fields */
22648 #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u
22649 #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0
22650 /* USDHC2_IPP_CARD_DET_SELECT_INPUT Bit Fields */
22651 #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u
22652 #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0
22653 /* USDHC2_IPP_WP_ON_SELECT_INPUT Bit Fields */
22654 #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u
22655 #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0
22656 /* USDHC4_IPP_CARD_DET_SELECT_INPUT Bit Fields */
22657 #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u
22658 #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0
22659 /* USDHC4_IPP_WP_ON_SELECT_INPUT Bit Fields */
22660 #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u
22661 #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0
22662 
22663 /*!
22664  * @}
22665  */ /* end of group IOMUXC_Register_Masks */
22666 
22667 /* IOMUXC - Peripheral instance base addresses */
22668 /** Peripheral IOMUXC base address */
22669 #define IOMUXC_BASE                              (0x420E0000u)
22670 /** Peripheral IOMUXC base pointer */
22671 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
22672 #define IOMUXC_BASE_PTR                          (IOMUXC)
22673 /** Array initializer of IOMUXC peripheral base addresses */
22674 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
22675 /** Array initializer of IOMUXC peripheral base pointers */
22676 #define IOMUXC_BASE_PTRS                         { IOMUXC }
22677 
22678 /* ----------------------------------------------------------------------------
22679    -- IOMUXC - Register accessor macros
22680    ---------------------------------------------------------------------------- */
22681 
22682 /*!
22683  * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros
22684  * @{
22685  */
22686 
22687 /* IOMUXC - Register instance definitions */
22688 /* IOMUXC */
22689 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR)
22690 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR)
22691 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR)
22692 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR)
22693 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR)
22694 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR)
22695 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR)
22696 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR)
22697 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
22698 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
22699 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
22700 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
22701 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
22702 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13         IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
22703 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR)
22704 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR)
22705 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR)
22706 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR)
22707 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR)
22708 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR)
22709 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR)
22710 #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07         IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR)
22711 #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC          IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR)
22712 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK           IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR)
22713 #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK         IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR)
22714 #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC          IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR)
22715 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL          IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
22716 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS          IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
22717 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC          IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR)
22718 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO         IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR)
22719 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
22720 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
22721 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL          IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR)
22722 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS          IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR)
22723 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR)
22724 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK       IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR)
22725 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0           IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR)
22726 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1           IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR)
22727 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2           IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR)
22728 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3           IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR)
22729 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4           IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR)
22730 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0           IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR)
22731 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1           IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR)
22732 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2           IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR)
22733 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3           IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR)
22734 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4           IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR)
22735 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK           IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR)
22736 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR)
22737 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR)
22738 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR)
22739 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR)
22740 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR)
22741 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR)
22742 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR)
22743 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR)
22744 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR)
22745 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR)
22746 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR)
22747 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR)
22748 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR)
22749 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR)
22750 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR)
22751 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR)
22752 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR)
22753 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR)
22754 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR)
22755 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR)
22756 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR)
22757 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR)
22758 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR)
22759 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23        IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR)
22760 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE        IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR)
22761 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC         IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR)
22762 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET         IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR)
22763 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC         IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR)
22764 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE           IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR)
22765 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B         IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR)
22766 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B         IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR)
22767 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE           IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR)
22768 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR)
22769 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR)
22770 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR)
22771 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR)
22772 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR)
22773 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR)
22774 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR)
22775 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07        IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR)
22776 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B          IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR)
22777 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B       IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR)
22778 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B          IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR)
22779 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B          IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR)
22780 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR)
22781 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR)
22782 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR)
22783 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR)
22784 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS         IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR)
22785 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK        IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR)
22786 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR)
22787 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B       IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR)
22788 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR)
22789 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR)
22790 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR)
22791 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR)
22792 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS         IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR)
22793 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK        IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR)
22794 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR)
22795 #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B       IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR)
22796 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0         IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR)
22797 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1         IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR)
22798 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2         IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR)
22799 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3         IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR)
22800 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL      IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR)
22801 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC         IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR)
22802 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0         IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR)
22803 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1         IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR)
22804 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2         IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR)
22805 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3         IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR)
22806 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL      IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR)
22807 #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC         IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR)
22808 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0         IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR)
22809 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1         IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR)
22810 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2         IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR)
22811 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3         IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR)
22812 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL      IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR)
22813 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC         IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR)
22814 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0         IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR)
22815 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1         IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR)
22816 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2         IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR)
22817 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3         IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR)
22818 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL      IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR)
22819 #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC         IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR)
22820 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK            IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
22821 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD            IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
22822 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
22823 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
22824 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
22825 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
22826 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK            IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
22827 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD            IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
22828 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
22829 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
22830 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
22831 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
22832 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK            IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
22833 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD            IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
22834 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
22835 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
22836 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
22837 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
22838 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
22839 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
22840 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
22841 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7          IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
22842 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK            IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR)
22843 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD            IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR)
22844 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR)
22845 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR)
22846 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR)
22847 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR)
22848 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR)
22849 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR)
22850 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR)
22851 #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7          IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR)
22852 #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B        IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR)
22853 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA         IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR)
22854 #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE       IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR)
22855 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(IOMUXC_BASE_PTR)
22856 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(IOMUXC_BASE_PTR)
22857 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(IOMUXC_BASE_PTR)
22858 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(IOMUXC_BASE_PTR)
22859 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(IOMUXC_BASE_PTR)
22860 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(IOMUXC_BASE_PTR)
22861 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(IOMUXC_BASE_PTR)
22862 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(IOMUXC_BASE_PTR)
22863 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(IOMUXC_BASE_PTR)
22864 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(IOMUXC_BASE_PTR)
22865 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(IOMUXC_BASE_PTR)
22866 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(IOMUXC_BASE_PTR)
22867 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(IOMUXC_BASE_PTR)
22868 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(IOMUXC_BASE_PTR)
22869 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(IOMUXC_BASE_PTR)
22870 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15        IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(IOMUXC_BASE_PTR)
22871 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0          IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(IOMUXC_BASE_PTR)
22872 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1          IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(IOMUXC_BASE_PTR)
22873 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2          IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(IOMUXC_BASE_PTR)
22874 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3          IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(IOMUXC_BASE_PTR)
22875 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B         IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(IOMUXC_BASE_PTR)
22876 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B         IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(IOMUXC_BASE_PTR)
22877 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B         IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(IOMUXC_BASE_PTR)
22878 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B         IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(IOMUXC_BASE_PTR)
22879 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B        IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(IOMUXC_BASE_PTR)
22880 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0          IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(IOMUXC_BASE_PTR)
22881 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1          IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(IOMUXC_BASE_PTR)
22882 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0         IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(IOMUXC_BASE_PTR)
22883 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1         IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(IOMUXC_BASE_PTR)
22884 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2         IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(IOMUXC_BASE_PTR)
22885 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0        IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(IOMUXC_BASE_PTR)
22886 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1        IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(IOMUXC_BASE_PTR)
22887 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P      IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(IOMUXC_BASE_PTR)
22888 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P       IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(IOMUXC_BASE_PTR)
22889 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P       IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(IOMUXC_BASE_PTR)
22890 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P       IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(IOMUXC_BASE_PTR)
22891 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P       IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(IOMUXC_BASE_PTR)
22892 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET         IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(IOMUXC_BASE_PTR)
22893 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD           IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR)
22894 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK           IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR)
22895 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI           IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR)
22896 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO           IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR)
22897 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS           IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR)
22898 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B        IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR)
22899 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR)
22900 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR)
22901 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR)
22902 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR)
22903 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR)
22904 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR)
22905 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR)
22906 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR)
22907 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
22908 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
22909 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
22910 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
22911 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
22912 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13         IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
22913 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR)
22914 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR)
22915 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR)
22916 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR)
22917 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR)
22918 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR)
22919 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR)
22920 #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07         IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR)
22921 #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC          IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR)
22922 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK           IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR)
22923 #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK         IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR)
22924 #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC          IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR)
22925 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL          IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
22926 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS          IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
22927 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC          IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR)
22928 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO         IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR)
22929 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
22930 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
22931 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL          IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR)
22932 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS          IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR)
22933 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR)
22934 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK       IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR)
22935 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0           IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR)
22936 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1           IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR)
22937 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2           IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR)
22938 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3           IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR)
22939 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4           IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR)
22940 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0           IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR)
22941 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1           IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR)
22942 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2           IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR)
22943 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3           IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR)
22944 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4           IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR)
22945 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK           IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR)
22946 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR)
22947 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR)
22948 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR)
22949 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR)
22950 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR)
22951 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR)
22952 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR)
22953 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR)
22954 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR)
22955 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR)
22956 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR)
22957 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR)
22958 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR)
22959 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR)
22960 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR)
22961 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR)
22962 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR)
22963 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR)
22964 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR)
22965 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR)
22966 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR)
22967 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR)
22968 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR)
22969 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23        IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR)
22970 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE        IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR)
22971 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC         IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR)
22972 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET         IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR)
22973 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC         IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR)
22974 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE           IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR)
22975 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B         IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR)
22976 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B         IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR)
22977 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE           IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR)
22978 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR)
22979 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR)
22980 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR)
22981 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR)
22982 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR)
22983 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR)
22984 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR)
22985 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07        IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR)
22986 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B          IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR)
22987 #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B       IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR)
22988 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B          IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR)
22989 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B          IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR)
22990 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR)
22991 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR)
22992 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR)
22993 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR)
22994 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS         IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR)
22995 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK        IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR)
22996 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR)
22997 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B       IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR)
22998 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR)
22999 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR)
23000 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR)
23001 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR)
23002 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS         IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR)
23003 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK        IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR)
23004 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR)
23005 #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B       IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR)
23006 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0         IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR)
23007 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1         IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR)
23008 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2         IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR)
23009 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3         IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR)
23010 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL      IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR)
23011 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC         IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR)
23012 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0         IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR)
23013 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1         IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR)
23014 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2         IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR)
23015 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3         IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR)
23016 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL      IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR)
23017 #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC         IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR)
23018 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0         IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR)
23019 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1         IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR)
23020 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2         IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR)
23021 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3         IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR)
23022 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL      IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR)
23023 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC         IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR)
23024 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0         IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR)
23025 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1         IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR)
23026 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2         IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR)
23027 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3         IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR)
23028 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL      IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR)
23029 #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC         IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR)
23030 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK            IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
23031 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD            IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
23032 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
23033 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
23034 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
23035 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
23036 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK            IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
23037 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD            IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
23038 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
23039 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
23040 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
23041 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
23042 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK            IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
23043 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD            IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
23044 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
23045 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
23046 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
23047 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
23048 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
23049 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
23050 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
23051 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7          IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
23052 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK            IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR)
23053 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD            IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR)
23054 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR)
23055 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR)
23056 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR)
23057 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR)
23058 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR)
23059 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR)
23060 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR)
23061 #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7          IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR)
23062 #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B        IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR)
23063 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA         IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR)
23064 #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE       IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR)
23065 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS              IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(IOMUXC_BASE_PTR)
23066 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL        IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(IOMUXC_BASE_PTR)
23067 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE             IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(IOMUXC_BASE_PTR)
23068 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK              IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(IOMUXC_BASE_PTR)
23069 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS             IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(IOMUXC_BASE_PTR)
23070 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE            IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(IOMUXC_BASE_PTR)
23071 #define IOMUXC_SW_PAD_CTL_GRP_B0DS               IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(IOMUXC_BASE_PTR)
23072 #define IOMUXC_SW_PAD_CTL_GRP_B1DS               IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(IOMUXC_BASE_PTR)
23073 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS              IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(IOMUXC_BASE_PTR)
23074 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE           IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(IOMUXC_BASE_PTR)
23075 #define IOMUXC_SW_PAD_CTL_GRP_B2DS               IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(IOMUXC_BASE_PTR)
23076 #define IOMUXC_SW_PAD_CTL_GRP_B3DS               IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(IOMUXC_BASE_PTR)
23077 #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT    IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23078 #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT    IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23079 #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23080 #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23081 #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23082 #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23083 #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23084 #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23085 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23086 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23087 #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23088 #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23089 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23090 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23091 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23092 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23093 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23094 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23095 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23096 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23097 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23098 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23099 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23100 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23101 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23102 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23103 #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT   IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23104 #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT   IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23105 #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23106 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23107 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(IOMUXC_BASE_PTR)
23108 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(IOMUXC_BASE_PTR)
23109 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(IOMUXC_BASE_PTR)
23110 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(IOMUXC_BASE_PTR)
23111 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23112 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23113 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23114 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(IOMUXC_BASE_PTR)
23115 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9     IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(IOMUXC_BASE_PTR)
23116 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(IOMUXC_BASE_PTR)
23117 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(IOMUXC_BASE_PTR)
23118 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(IOMUXC_BASE_PTR)
23119 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR)
23120 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR)
23121 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(IOMUXC_BASE_PTR)
23122 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(IOMUXC_BASE_PTR)
23123 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(IOMUXC_BASE_PTR)
23124 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(IOMUXC_BASE_PTR)
23125 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(IOMUXC_BASE_PTR)
23126 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(IOMUXC_BASE_PTR)
23127 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(IOMUXC_BASE_PTR)
23128 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(IOMUXC_BASE_PTR)
23129 #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10    IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(IOMUXC_BASE_PTR)
23130 #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT   IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23131 #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT  IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23132 #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT   IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23133 #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23134 #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23135 #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT  IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23136 #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT  IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23137 #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23138 #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23139 #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT  IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23140 #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT  IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23141 #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23142 #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23143 #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT  IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23144 #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT  IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23145 #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23146 #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23147 #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT  IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23148 #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT  IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23149 #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23150 #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23151 #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT  IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23152 #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT  IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23153 #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23154 #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT   IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23155 #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23156 #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23157 #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT   IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23158 #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23159 #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23160 #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT     IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23161 #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT     IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23162 #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23163 #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23164 #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23165 #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23166 #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23167 #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT    IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23168 #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23169 #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23170 #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23171 #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23172 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT      IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23173 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT      IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23174 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT      IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23175 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT      IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23176 #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT      IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23177 #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT      IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23178 #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT      IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23179 #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT      IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23180 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5    IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23181 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6    IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23182 #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7    IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23183 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5    IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23184 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6    IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23185 #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7    IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23186 #define IOMUXC_LCD1_BUSY_SELECT_INPUT            IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23187 #define IOMUXC_LCD2_BUSY_SELECT_INPUT            IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23188 #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT       IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23189 #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT      IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23190 #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT       IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23191 #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23192 #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23193 #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23194 #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23195 #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23196 #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23197 #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23198 #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23199 #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23200 #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23201 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14       IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR)
23202 #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15       IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR)
23203 #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT      IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23204 #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT        IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23205 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23206 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23207 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23208 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23209 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23210 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23211 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23212 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23213 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23214 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23215 #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23216 #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23217 #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT  IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23218 #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT   IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23219 #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT  IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23220 #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT     IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23221 #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT  IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23222 #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT     IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23223 #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT  IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23224 #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT     IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23225 
23226 /*!
23227  * @}
23228  */ /* end of group IOMUXC_Register_Accessor_Macros */
23229 
23230 /*!
23231  * @}
23232  */ /* end of group IOMUXC_Peripheral */
23233 
23234 /* ----------------------------------------------------------------------------
23235    -- IOMUXC_GPR Peripheral Access Layer
23236    ---------------------------------------------------------------------------- */
23237 
23238 /*!
23239  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
23240  * @{
23241  */
23242 
23243 /** IOMUXC_GPR - Register Layout Typedef */
23244 typedef struct {
23245   __IO  uint32_t GPR0;                                   /**< GPR0 General Purpose Register, offset: 0x0 */
23246   __IO  uint32_t GPR1;                                   /**< GPR1 General Purpose Register, offset: 0x4 */
23247   __IO  uint32_t GPR2;                                   /**< GPR2 General Purpose Register, offset: 0x8 */
23248   __IO  uint32_t GPR3;                                   /**< GPR3 General Purpose Register, offset: 0xC */
23249   __IO  uint32_t GPR4;                                   /**< GPR4 General Purpose Register, offset: 0x10 */
23250   __IO  uint32_t GPR5;                                   /**< GPR5 General Purpose Register, offset: 0x14 */
23251   __IO  uint32_t GPR6;                                   /**< GPR6 General Purpose Register, offset: 0x18 */
23252   __IO  uint32_t GPR7;                                   /**< GPR7 General Purpose Register, offset: 0x1C */
23253   __IO  uint32_t GPR8;                                   /**< GPR8 General Purpose Register, offset: 0x20 */
23254   __IO  uint32_t GPR9;                                   /**< GPR9 General Purpose Register, offset: 0x24 */
23255   __IO  uint32_t GPR10;                                  /**< GPR10 General Purpose Register, offset: 0x28 */
23256   __IO  uint32_t GPR11;                                  /**< GPR11 General Purpose Register, offset: 0x2C */
23257   __IO  uint32_t GPR12;                                  /**< GPR12 General Purpose Register, offset: 0x30 */
23258   __IO  uint32_t GPR13;                                  /**< GPR13 General Purpose Register, offset: 0x34 */
23259 } IOMUXC_GPR_Type, *IOMUXC_GPR_MemMapPtr;
23260 
23261 /* ----------------------------------------------------------------------------
23262    -- IOMUXC_GPR - Register accessor macros
23263    ---------------------------------------------------------------------------- */
23264 
23265 /*!
23266  * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros
23267  * @{
23268  */
23269 
23270 /* IOMUXC_GPR - Register accessors */
23271 #define IOMUXC_GPR_GPR0_REG(base)                ((base)->GPR0)
23272 #define IOMUXC_GPR_GPR1_REG(base)                ((base)->GPR1)
23273 #define IOMUXC_GPR_GPR2_REG(base)                ((base)->GPR2)
23274 #define IOMUXC_GPR_GPR3_REG(base)                ((base)->GPR3)
23275 #define IOMUXC_GPR_GPR4_REG(base)                ((base)->GPR4)
23276 #define IOMUXC_GPR_GPR5_REG(base)                ((base)->GPR5)
23277 #define IOMUXC_GPR_GPR6_REG(base)                ((base)->GPR6)
23278 #define IOMUXC_GPR_GPR7_REG(base)                ((base)->GPR7)
23279 #define IOMUXC_GPR_GPR8_REG(base)                ((base)->GPR8)
23280 #define IOMUXC_GPR_GPR9_REG(base)                ((base)->GPR9)
23281 #define IOMUXC_GPR_GPR10_REG(base)               ((base)->GPR10)
23282 #define IOMUXC_GPR_GPR11_REG(base)               ((base)->GPR11)
23283 #define IOMUXC_GPR_GPR12_REG(base)               ((base)->GPR12)
23284 #define IOMUXC_GPR_GPR13_REG(base)               ((base)->GPR13)
23285 
23286 /*!
23287  * @}
23288  */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */
23289 
23290 /* ----------------------------------------------------------------------------
23291    -- IOMUXC_GPR Register Masks
23292    ---------------------------------------------------------------------------- */
23293 
23294 /*!
23295  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
23296  * @{
23297  */
23298 
23299 /* GPR0 Bit Fields */
23300 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u
23301 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT    0
23302 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK     0x2u
23303 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT    1
23304 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK     0x4u
23305 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT    2
23306 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK     0x8u
23307 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT    3
23308 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK     0x10u
23309 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT    4
23310 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK     0x20u
23311 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
23312 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
23313 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
23314 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK     0x80u
23315 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT    7
23316 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK     0x100u
23317 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT    8
23318 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK     0x200u
23319 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT    9
23320 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK    0x400u
23321 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT   10
23322 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK    0x800u
23323 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT   11
23324 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK    0x1000u
23325 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT   12
23326 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK    0x2000u
23327 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT   13
23328 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK    0x4000u
23329 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT   14
23330 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK    0x8000u
23331 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT   15
23332 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK    0x10000u
23333 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT   16
23334 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK    0x20000u
23335 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT   17
23336 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK    0x40000u
23337 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT   18
23338 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK    0x80000u
23339 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT   19
23340 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK    0x100000u
23341 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT   20
23342 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK    0x200000u
23343 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT   21
23344 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK    0x400000u
23345 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT   22
23346 /* GPR1 Bit Fields */
23347 #define IOMUXC_GPR_GPR1_ACT_CS0_MASK             0x1u
23348 #define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT            0
23349 #define IOMUXC_GPR_GPR1_ADDRS0_MASK              0x6u
23350 #define IOMUXC_GPR_GPR1_ADDRS0_SHIFT             1
23351 #define IOMUXC_GPR_GPR1_ADDRS0(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_ADDRS0_MASK)
23352 #define IOMUXC_GPR_GPR1_ACT_CS1_MASK             0x8u
23353 #define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT            3
23354 #define IOMUXC_GPR_GPR1_ADDRS1_MASK              0x30u
23355 #define IOMUXC_GPR_GPR1_ADDRS1_SHIFT             4
23356 #define IOMUXC_GPR_GPR1_ADDRS1(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_ADDRS1_MASK)
23357 #define IOMUXC_GPR_GPR1_ACT_CS2_MASK             0x40u
23358 #define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT            6
23359 #define IOMUXC_GPR_GPR1_ADDRS2_MASK              0x180u
23360 #define IOMUXC_GPR_GPR1_ADDRS2_SHIFT             7
23361 #define IOMUXC_GPR_GPR1_ADDRS2(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_ADDRS2_MASK)
23362 #define IOMUXC_GPR_GPR1_ACT_CS3_MASK             0x200u
23363 #define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT            9
23364 #define IOMUXC_GPR_GPR1_ADDRS3_MASK              0xC00u
23365 #define IOMUXC_GPR_GPR1_ADDRS3_SHIFT             10
23366 #define IOMUXC_GPR_GPR1_ADDRS3(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_ADDRS3_MASK)
23367 #define IOMUXC_GPR_GPR1_GINT_MASK                0x1000u
23368 #define IOMUXC_GPR_GPR1_GINT_SHIFT               12
23369 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK       0x2000u
23370 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT      13
23371 #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK       0x4000u
23372 #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT      14
23373 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK        0x8000u
23374 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT       15
23375 #define IOMUXC_GPR_GPR1_ADD_DS_MASK              0x10000u
23376 #define IOMUXC_GPR_GPR1_ADD_DS_SHIFT             16
23377 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK    0x20000u
23378 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT   17
23379 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK    0x40000u
23380 #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT   18
23381 #define IOMUXC_GPR_GPR1_VADC_SW_RST_MASK         0x80000u
23382 #define IOMUXC_GPR_GPR1_VADC_SW_RST_SHIFT        19
23383 #define IOMUXC_GPR_GPR1_VDEC_SW_RST_MASK         0x100000u
23384 #define IOMUXC_GPR_GPR1_VDEC_SW_RST_SHIFT        20
23385 #define IOMUXC_GPR_GPR1_EXC_MON_MASK             0x400000u
23386 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT            22
23387 #define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK    0x800000u
23388 #define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT   23
23389 #define IOMUXC_GPR_GPR1_ARMA9_CLK_APB_DBG_EN_MASK 0x1000000u
23390 #define IOMUXC_GPR_GPR1_ARMA9_CLK_APB_DBG_EN_SHIFT 24
23391 #define IOMUXC_GPR_GPR1_ARMA9_CLK_ATB_EN_MASK    0x2000000u
23392 #define IOMUXC_GPR_GPR1_ARMA9_CLK_ATB_EN_SHIFT   25
23393 #define IOMUXC_GPR_GPR1_ARMA9_CLK_AHB_EN_MASK    0x4000000u
23394 #define IOMUXC_GPR_GPR1_ARMA9_CLK_AHB_EN_SHIFT   26
23395 #define IOMUXC_GPR_GPR1_ARMA9_IPG_CLK_EN_MASK    0x8000000u
23396 #define IOMUXC_GPR_GPR1_ARMA9_IPG_CLK_EN_SHIFT   27
23397 /* GPR2 Bit Fields */
23398 #define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK 0x1u
23399 #define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT 0
23400 #define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK    0x2u
23401 #define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT   1
23402 #define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK   0x4u
23403 #define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT  2
23404 #define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK  0x8u
23405 #define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT 3
23406 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK 0x10u
23407 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT 4
23408 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK 0x20u
23409 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT 5
23410 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK 0x40u
23411 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT 6
23412 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK 0x80u
23413 #define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT 7
23414 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK 0x100u
23415 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT 8
23416 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK 0x200u
23417 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT 9
23418 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK 0x400u
23419 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT 10
23420 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK 0x800u
23421 #define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT 11
23422 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK 0x1000u
23423 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT 12
23424 #define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK     0x2000u
23425 #define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT    13
23426 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK    0x4000u
23427 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   14
23428 #define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK   0x8000u
23429 #define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT  15
23430 #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK   0x8000000u
23431 #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT  27
23432 #define IOMUXC_GPR_GPR2_DRAM_RESET_MASK          0x10000000u
23433 #define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT         28
23434 #define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK           0x20000000u
23435 #define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT          29
23436 #define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK           0x40000000u
23437 #define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT          30
23438 #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK     0x80000000u
23439 #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT    31
23440 /* GPR3 Bit Fields */
23441 #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK           0xFu
23442 #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT          0
23443 #define IOMUXC_GPR_GPR3_OCRAM_CTL(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
23444 #define IOMUXC_GPR_GPR3_OCRAM_S_CTL_MASK         0xF0u
23445 #define IOMUXC_GPR_GPR3_OCRAM_S_CTL_SHIFT        4
23446 #define IOMUXC_GPR_GPR3_OCRAM_S_CTL(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_S_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_S_CTL_MASK)
23447 #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL_MASK        0xF00u
23448 #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL_SHIFT       8
23449 #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL(x)          (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_L2_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_L2_CTL_MASK)
23450 #define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK     0x2000u
23451 #define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT    13
23452 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK        0xF0000u
23453 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT       16
23454 #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x)          (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
23455 #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS_MASK      0xF00000u
23456 #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS_SHIFT     20
23457 #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_S_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_S_STATUS_MASK)
23458 #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_MASK     0xF000000u
23459 #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_SHIFT    24
23460 #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_MASK)
23461 /* GPR4 Bit Fields */
23462 #define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK       0x1u
23463 #define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT      0
23464 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK       0x2u
23465 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT      1
23466 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK       0x4u
23467 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT      2
23468 #define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK      0x8u
23469 #define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT     3
23470 #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK      0x10u
23471 #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT     4
23472 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK       0x20u
23473 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT      5
23474 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK       0x40u
23475 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT      6
23476 #define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK       0x10000u
23477 #define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT      16
23478 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK       0x20000u
23479 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT      17
23480 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK       0x40000u
23481 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT      18
23482 #define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK      0x80000u
23483 #define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT     19
23484 #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK      0x100000u
23485 #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT     20
23486 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK       0x200000u
23487 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT      21
23488 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK       0x400000u
23489 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT      22
23490 #define IOMUXC_GPR_GPR4_L2_CLK_STOP_MASK         0x20000000u
23491 #define IOMUXC_GPR_GPR4_L2_CLK_STOP_SHIFT        29
23492 #define IOMUXC_GPR_GPR4_ARM_WFI_MASK             0x40000000u
23493 #define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT            30
23494 #define IOMUXC_GPR_GPR4_ARM_WFE_MASK             0x80000000u
23495 #define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT            31
23496 /* GPR5 Bit Fields */
23497 #define IOMUXC_GPR_GPR5_SVADC_TEST_GPR1_MASK     0x1u
23498 #define IOMUXC_GPR_GPR5_SVADC_TEST_GPR1_SHIFT    0
23499 #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC1_CTRL_MASK 0x2u
23500 #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC1_CTRL_SHIFT 1
23501 #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC2_CTRL_MASK 0x4u
23502 #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC2_CTRL_SHIFT 2
23503 #define IOMUXC_GPR_GPR5_DISP_MUX_LDB_CTRL_MASK   0x8u
23504 #define IOMUXC_GPR_GPR5_DISP_MUX_LDB_CTRL_SHIFT  3
23505 #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_MASK       0x30u
23506 #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_SHIFT      4
23507 #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL(x)         (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_SHIFT))&IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_MASK)
23508 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK          0x40u
23509 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT         6
23510 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK          0x80u
23511 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT         7
23512 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_MASK 0x300u
23513 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_SHIFT 8
23514 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_MASK)
23515 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_MASK 0xC00u
23516 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_SHIFT 10
23517 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_MASK)
23518 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_MASK 0x3000u
23519 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_SHIFT 12
23520 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_MASK)
23521 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_MASK 0xC000u
23522 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_SHIFT 14
23523 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_MASK)
23524 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK 0x30000u
23525 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT 16
23526 #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK)
23527 #define IOMUXC_GPR_GPR5_PCIE_PERST_MASK          0x40000u
23528 #define IOMUXC_GPR_GPR5_PCIE_PERST_SHIFT         18
23529 #define IOMUXC_GPR_GPR5_PCIE_BTNRST_MASK         0x80000u
23530 #define IOMUXC_GPR_GPR5_PCIE_BTNRST_SHIFT        19
23531 #define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK          0x100000u
23532 #define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT         20
23533 #define IOMUXC_GPR_GPR5_LCDIF1_CSI_VSYNC_SEL_MASK 0x200000u
23534 #define IOMUXC_GPR_GPR5_LCDIF1_CSI_VSYNC_SEL_SHIFT 21
23535 #define IOMUXC_GPR_GPR5_LCDIF2_CSI_VSYNC_SEL_MASK 0x400000u
23536 #define IOMUXC_GPR_GPR5_LCDIF2_CSI_VSYNC_SEL_SHIFT 22
23537 #define IOMUXC_GPR_GPR5_VADC_TEST_GPR3_MASK      0x800000u
23538 #define IOMUXC_GPR_GPR5_VADC_TEST_GPR3_SHIFT     23
23539 #define IOMUXC_GPR_GPR5_VADC_TEST_6SX_GPR5_MASK  0x1000000u
23540 #define IOMUXC_GPR_GPR5_VADC_TEST_6SX_GPR5_SHIFT 24
23541 #define IOMUXC_GPR_GPR5_VADC_TEST_GPR2_MASK      0x2000000u
23542 #define IOMUXC_GPR_GPR5_VADC_TEST_GPR2_SHIFT     25
23543 #define IOMUXC_GPR_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK 0x4000000u
23544 #define IOMUXC_GPR_GPR5_VADC_TO_CSI_CAPTURE_EN_SHIFT 26
23545 #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_MASK       0x18000000u
23546 #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_SHIFT      27
23547 #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL(x)         (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_SHIFT))&IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_MASK)
23548 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT_MASK     0x20000000u
23549 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT_SHIFT    29
23550 #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK    0x40000000u
23551 #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT   30
23552 #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK    0x80000000u
23553 #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT   31
23554 /* GPR6 Bit Fields */
23555 #define IOMUXC_GPR_GPR6_CH0_MODE_MASK            0x3u
23556 #define IOMUXC_GPR_GPR6_CH0_MODE_SHIFT           0
23557 #define IOMUXC_GPR_GPR6_CH0_MODE(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_CH0_MODE_SHIFT))&IOMUXC_GPR_GPR6_CH0_MODE_MASK)
23558 #define IOMUXC_GPR_GPR6_DATA_WIDTH_CH0_MASK      0x20u
23559 #define IOMUXC_GPR_GPR6_DATA_WIDTH_CH0_SHIFT     5
23560 #define IOMUXC_GPR_GPR6_BIT_MAPPING_CH0_MASK     0x40u
23561 #define IOMUXC_GPR_GPR6_BIT_MAPPING_CH0_SHIFT    6
23562 #define IOMUXC_GPR_GPR6_LCDIF_VS_POLARITY_MASK   0x200u
23563 #define IOMUXC_GPR_GPR6_LCDIF_VS_POLARITY_SHIFT  9
23564 #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_MASK      0x70000u
23565 #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_SHIFT     16
23566 #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_SHIFT))&IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_MASK)
23567 #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_MASK   0x300000u
23568 #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_SHIFT  20
23569 #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_SHIFT))&IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_MASK)
23570 /* GPR7 Bit Fields */
23571 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_MASK    0x3u
23572 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_SHIFT   0
23573 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_MASK)
23574 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_MASK    0xCu
23575 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_SHIFT   2
23576 #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_MASK)
23577 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_MASK    0x30u
23578 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_SHIFT   4
23579 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_MASK)
23580 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_MASK    0xC0u
23581 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_SHIFT   6
23582 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_MASK)
23583 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_MASK    0x300u
23584 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_SHIFT   8
23585 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_MASK)
23586 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_MASK    0xC00u
23587 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_SHIFT   10
23588 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_MASK)
23589 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_MASK    0x3000u
23590 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_SHIFT   12
23591 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_MASK)
23592 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_MASK    0xC000u
23593 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_SHIFT   14
23594 #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_MASK)
23595 #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_MASK   0x30000u
23596 #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_SHIFT  16
23597 #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_MASK)
23598 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_1_MASK      0x40000u
23599 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_1_SHIFT     18
23600 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_4_MASK      0x80000u
23601 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_4_SHIFT     19
23602 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_9_MASK      0x100000u
23603 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_9_SHIFT     20
23604 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_C_MASK      0x200000u
23605 #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_C_SHIFT     21
23606 /* GPR8 Bit Fields */
23607 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_MASK  0x3Fu
23608 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_SHIFT 0
23609 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_MASK)
23610 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK 0xFC0u
23611 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT 6
23612 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK)
23613 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK 0x3F000u
23614 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT 12
23615 #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK)
23616 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_MASK   0x1FC0000u
23617 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_SHIFT  18
23618 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_MASK)
23619 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_MASK    0xFE000000u
23620 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_SHIFT   25
23621 #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_MASK)
23622 /* GPR9 Bit Fields */
23623 #define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK          0x1u
23624 #define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT         0
23625 /* GPR10 Bit Fields */
23626 #define IOMUXC_GPR_GPR10_DBG_EN_MASK             0x1u
23627 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT            0
23628 #define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK         0x2u
23629 #define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT        1
23630 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK       0x4u
23631 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT      2
23632 #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_EN_MASK     0x8u
23633 #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_EN_SHIFT    3
23634 #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_MASK   0x3F0u
23635 #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_SHIFT  4
23636 #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_MASK)
23637 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK        0x400u
23638 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT       10
23639 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK      0xF800u
23640 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT     11
23641 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
23642 /* GPR11 Bit Fields */
23643 #define IOMUXC_GPR_GPR11_OCRAM_L2_EN_MASK        0x2u
23644 #define IOMUXC_GPR_GPR11_OCRAM_L2_EN_SHIFT       1
23645 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_MASK      0x400u
23646 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_SHIFT     10
23647 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK    0x1800u
23648 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT   11
23649 #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR(x)      (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK)
23650 /* GPR12 Bit Fields */
23651 #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ_MASK        0x7u
23652 #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ_SHIFT       0
23653 #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ(x)          (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_RX0_EQ_SHIFT))&IOMUXC_GPR_GPR12_PCIE_RX0_EQ_MASK)
23654 #define IOMUXC_GPR_GPR12_LOS_LEVEL_MASK          0x1F0u
23655 #define IOMUXC_GPR_GPR12_LOS_LEVEL_SHIFT         4
23656 #define IOMUXC_GPR_GPR12_LOS_LEVEL(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_LOS_LEVEL_SHIFT))&IOMUXC_GPR_GPR12_LOS_LEVEL_MASK)
23657 #define IOMUXC_GPR_GPR12_APPS_PM_XMT_PME_MASK    0x200u
23658 #define IOMUXC_GPR_GPR12_APPS_PM_XMT_PME_SHIFT   9
23659 #define IOMUXC_GPR_GPR12_APP_LTSSM_ENABLE_MASK   0x400u
23660 #define IOMUXC_GPR_GPR12_APP_LTSSM_ENABLE_SHIFT  10
23661 #define IOMUXC_GPR_GPR12_APP_INIT_RST_MASK       0x800u
23662 #define IOMUXC_GPR_GPR12_APP_INIT_RST_SHIFT      11
23663 #define IOMUXC_GPR_GPR12_DEVICE_TYPE_MASK        0xF000u
23664 #define IOMUXC_GPR_GPR12_DEVICE_TYPE_SHIFT       12
23665 #define IOMUXC_GPR_GPR12_DEVICE_TYPE(x)          (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_DEVICE_TYPE_MASK)
23666 #define IOMUXC_GPR_GPR12_APPS_PM_XMT_TURNOFF_MASK 0x10000u
23667 #define IOMUXC_GPR_GPR12_APPS_PM_XMT_TURNOFF_SHIFT 16
23668 #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
23669 #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_SHIFT 17
23670 #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_MASK)
23671 #define IOMUXC_GPR_GPR12_PCIe_CTL_7_MASK         0xE00000u
23672 #define IOMUXC_GPR_GPR12_PCIe_CTL_7_SHIFT        21
23673 #define IOMUXC_GPR_GPR12_PCIe_CTL_7(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIe_CTL_7_SHIFT))&IOMUXC_GPR_GPR12_PCIe_CTL_7_MASK)
23674 #define IOMUXC_GPR_GPR12_SYS_INT_MASK            0x1000000u
23675 #define IOMUXC_GPR_GPR12_SYS_INT_SHIFT           24
23676 #define IOMUXC_GPR_GPR12_APP_REQ_ENTR_L1_MASK    0x2000000u
23677 #define IOMUXC_GPR_GPR12_APP_REQ_ENTR_L1_SHIFT   25
23678 #define IOMUXC_GPR_GPR12_APP_REQ_EXIT_L1_MASK    0x4000000u
23679 #define IOMUXC_GPR_GPR12_APP_REQ_EXIT_L1_SHIFT   26
23680 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK 0x8000000u
23681 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT 27
23682 #define IOMUXC_GPR_GPR12_APP_READY_ENTR_L23_MASK 0x10000000u
23683 #define IOMUXC_GPR_GPR12_APP_READY_ENTR_L23_SHIFT 28
23684 #define IOMUXC_GPR_GPR12_APP_CLK_REQ_N_MASK      0x20000000u
23685 #define IOMUXC_GPR_GPR12_APP_CLK_REQ_N_SHIFT     29
23686 #define IOMUXC_GPR_GPR12_TEST_POWERDOWN_MASK     0x40000000u
23687 #define IOMUXC_GPR_GPR12_TEST_POWERDOWN_SHIFT    30
23688 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN_MASK 0x80000000u
23689 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN_SHIFT 31
23690 /* GPR13 Bit Fields */
23691 #define IOMUXC_GPR_GPR13_USDHC_RD_CACHE_VAL_MASK 0x1u
23692 #define IOMUXC_GPR_GPR13_USDHC_RD_CACHE_VAL_SHIFT 0
23693 #define IOMUXC_GPR_GPR13_USDHC_WR_CACHE_VAL_MASK 0x2u
23694 #define IOMUXC_GPR_GPR13_USDHC_WR_CACHE_VAL_SHIFT 1
23695 #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_VAL_MASK   0x4u
23696 #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_VAL_SHIFT  2
23697 #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_VAL_MASK   0x8u
23698 #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_VAL_SHIFT  3
23699 #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_VAL_MASK  0x10u
23700 #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_VAL_SHIFT 4
23701 #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_VAL_MASK  0x20u
23702 #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_VAL_SHIFT 5
23703 #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_VAL_MASK 0x40u
23704 #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_VAL_SHIFT 6
23705 #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_VAL_MASK 0x80u
23706 #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_VAL_SHIFT 7
23707 #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_SEL_MASK   0x100u
23708 #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_SEL_SHIFT  8
23709 #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_SEL_MASK   0x200u
23710 #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_SEL_SHIFT  9
23711 #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_SEL_MASK  0x400u
23712 #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_SEL_SHIFT 10
23713 #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_SEL_MASK  0x800u
23714 #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_SEL_SHIFT 11
23715 #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_SEL_MASK 0x1000u
23716 #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_SEL_SHIFT 12
23717 #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_SEL_MASK 0x2000u
23718 #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_SEL_SHIFT 13
23719 #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE_MASK 0x4000u
23720 #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE_SHIFT 14
23721 #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_PERST_DISABLE_MASK 0x8000u
23722 #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_PERST_DISABLE_SHIFT 15
23723 
23724 /*!
23725  * @}
23726  */ /* end of group IOMUXC_GPR_Register_Masks */
23727 
23728 /* IOMUXC_GPR - Peripheral instance base addresses */
23729 /** Peripheral IOMUXC_GPR base address */
23730 #define IOMUXC_GPR_BASE                          (0x420E4000u)
23731 /** Peripheral IOMUXC_GPR base pointer */
23732 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
23733 #define IOMUXC_GPR_BASE_PTR                      (IOMUXC_GPR)
23734 /** Array initializer of IOMUXC_GPR peripheral base addresses */
23735 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
23736 /** Array initializer of IOMUXC_GPR peripheral base pointers */
23737 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
23738 
23739 /* ----------------------------------------------------------------------------
23740    -- IOMUXC_GPR - Register accessor macros
23741    ---------------------------------------------------------------------------- */
23742 
23743 /*!
23744  * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros
23745  * @{
23746  */
23747 
23748 /* IOMUXC_GPR - Register instance definitions */
23749 /* IOMUXC_GPR */
23750 #define IOMUXC_GPR_GPR0                          IOMUXC_GPR_GPR0_REG(IOMUXC_GPR_BASE_PTR)
23751 #define IOMUXC_GPR_GPR1                          IOMUXC_GPR_GPR1_REG(IOMUXC_GPR_BASE_PTR)
23752 #define IOMUXC_GPR_GPR2                          IOMUXC_GPR_GPR2_REG(IOMUXC_GPR_BASE_PTR)
23753 #define IOMUXC_GPR_GPR3                          IOMUXC_GPR_GPR3_REG(IOMUXC_GPR_BASE_PTR)
23754 #define IOMUXC_GPR_GPR4                          IOMUXC_GPR_GPR4_REG(IOMUXC_GPR_BASE_PTR)
23755 #define IOMUXC_GPR_GPR5                          IOMUXC_GPR_GPR5_REG(IOMUXC_GPR_BASE_PTR)
23756 #define IOMUXC_GPR_GPR6                          IOMUXC_GPR_GPR6_REG(IOMUXC_GPR_BASE_PTR)
23757 #define IOMUXC_GPR_GPR7                          IOMUXC_GPR_GPR7_REG(IOMUXC_GPR_BASE_PTR)
23758 #define IOMUXC_GPR_GPR8                          IOMUXC_GPR_GPR8_REG(IOMUXC_GPR_BASE_PTR)
23759 #define IOMUXC_GPR_GPR9                          IOMUXC_GPR_GPR9_REG(IOMUXC_GPR_BASE_PTR)
23760 #define IOMUXC_GPR_GPR10                         IOMUXC_GPR_GPR10_REG(IOMUXC_GPR_BASE_PTR)
23761 #define IOMUXC_GPR_GPR11                         IOMUXC_GPR_GPR11_REG(IOMUXC_GPR_BASE_PTR)
23762 #define IOMUXC_GPR_GPR12                         IOMUXC_GPR_GPR12_REG(IOMUXC_GPR_BASE_PTR)
23763 #define IOMUXC_GPR_GPR13                         IOMUXC_GPR_GPR13_REG(IOMUXC_GPR_BASE_PTR)
23764 
23765 /*!
23766  * @}
23767  */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */
23768 
23769 /*!
23770  * @}
23771  */ /* end of group IOMUXC_GPR_Peripheral */
23772 
23773 /* ----------------------------------------------------------------------------
23774    -- KPP Peripheral Access Layer
23775    ---------------------------------------------------------------------------- */
23776 
23777 /*!
23778  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
23779  * @{
23780  */
23781 
23782 /** KPP - Register Layout Typedef */
23783 typedef struct {
23784   __IO  uint16_t KPCR;                                   /**< Keypad Control Register, offset: 0x0 */
23785   __IO  uint16_t KPSR;                                   /**< Keypad Status Register, offset: 0x2 */
23786   __IO  uint16_t KDDR;                                   /**< Keypad Data Direction Register, offset: 0x4 */
23787   __IO  uint16_t KPDR;                                   /**< Keypad Data Register, offset: 0x6 */
23788 } KPP_Type, *KPP_MemMapPtr;
23789 
23790 /* ----------------------------------------------------------------------------
23791    -- KPP - Register accessor macros
23792    ---------------------------------------------------------------------------- */
23793 
23794 /*!
23795  * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros
23796  * @{
23797  */
23798 
23799 /* KPP - Register accessors */
23800 #define KPP_KPCR_REG(base)                       ((base)->KPCR)
23801 #define KPP_KPSR_REG(base)                       ((base)->KPSR)
23802 #define KPP_KDDR_REG(base)                       ((base)->KDDR)
23803 #define KPP_KPDR_REG(base)                       ((base)->KPDR)
23804 
23805 /*!
23806  * @}
23807  */ /* end of group KPP_Register_Accessor_Macros */
23808 
23809 /* ----------------------------------------------------------------------------
23810    -- KPP Register Masks
23811    ---------------------------------------------------------------------------- */
23812 
23813 /*!
23814  * @addtogroup KPP_Register_Masks KPP Register Masks
23815  * @{
23816  */
23817 
23818 /* KPCR Bit Fields */
23819 #define KPP_KPCR_KRE_MASK                        0xFFu
23820 #define KPP_KPCR_KRE_SHIFT                       0
23821 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KRE_SHIFT))&KPP_KPCR_KRE_MASK)
23822 #define KPP_KPCR_KCO_MASK                        0xFF00u
23823 #define KPP_KPCR_KCO_SHIFT                       8
23824 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KCO_SHIFT))&KPP_KPCR_KCO_MASK)
23825 /* KPSR Bit Fields */
23826 #define KPP_KPSR_KPKD_MASK                       0x1u
23827 #define KPP_KPSR_KPKD_SHIFT                      0
23828 #define KPP_KPSR_KPKR_MASK                       0x2u
23829 #define KPP_KPSR_KPKR_SHIFT                      1
23830 #define KPP_KPSR_KDSC_MASK                       0x4u
23831 #define KPP_KPSR_KDSC_SHIFT                      2
23832 #define KPP_KPSR_KRSS_MASK                       0x8u
23833 #define KPP_KPSR_KRSS_SHIFT                      3
23834 #define KPP_KPSR_KDIE_MASK                       0x100u
23835 #define KPP_KPSR_KDIE_SHIFT                      8
23836 #define KPP_KPSR_KRIE_MASK                       0x200u
23837 #define KPP_KPSR_KRIE_SHIFT                      9
23838 /* KDDR Bit Fields */
23839 #define KPP_KDDR_KRDD_MASK                       0xFFu
23840 #define KPP_KDDR_KRDD_SHIFT                      0
23841 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KRDD_SHIFT))&KPP_KDDR_KRDD_MASK)
23842 #define KPP_KDDR_KCDD_MASK                       0xFF00u
23843 #define KPP_KDDR_KCDD_SHIFT                      8
23844 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KCDD_SHIFT))&KPP_KDDR_KCDD_MASK)
23845 /* KPDR Bit Fields */
23846 #define KPP_KPDR_KRD_MASK                        0xFFu
23847 #define KPP_KPDR_KRD_SHIFT                       0
23848 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KRD_SHIFT))&KPP_KPDR_KRD_MASK)
23849 #define KPP_KPDR_KCD_MASK                        0xFF00u
23850 #define KPP_KPDR_KCD_SHIFT                       8
23851 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KCD_SHIFT))&KPP_KPDR_KCD_MASK)
23852 
23853 /*!
23854  * @}
23855  */ /* end of group KPP_Register_Masks */
23856 
23857 /* KPP - Peripheral instance base addresses */
23858 /** Peripheral KPP base address */
23859 #define KPP_BASE                                 (0x420B8000u)
23860 /** Peripheral KPP base pointer */
23861 #define KPP                                      ((KPP_Type *)KPP_BASE)
23862 #define KPP_BASE_PTR                             (KPP)
23863 /** Array initializer of KPP peripheral base addresses */
23864 #define KPP_BASE_ADDRS                           { KPP_BASE }
23865 /** Array initializer of KPP peripheral base pointers */
23866 #define KPP_BASE_PTRS                            { KPP }
23867 /** Interrupt vectors for the KPP peripheral type */
23868 #define KPP_IRQS                                 { KPP_IRQn }
23869 
23870 /* ----------------------------------------------------------------------------
23871    -- KPP - Register accessor macros
23872    ---------------------------------------------------------------------------- */
23873 
23874 /*!
23875  * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros
23876  * @{
23877  */
23878 
23879 /* KPP - Register instance definitions */
23880 /* KPP */
23881 #define KPP_KPCR                                 KPP_KPCR_REG(KPP_BASE_PTR)
23882 #define KPP_KPSR                                 KPP_KPSR_REG(KPP_BASE_PTR)
23883 #define KPP_KDDR                                 KPP_KDDR_REG(KPP_BASE_PTR)
23884 #define KPP_KPDR                                 KPP_KPDR_REG(KPP_BASE_PTR)
23885 /*!
23886  * @}
23887  */ /* end of group KPP_Register_Accessor_Macros */
23888 
23889 /*!
23890  * @}
23891  */ /* end of group KPP_Peripheral */
23892 
23893 /* ----------------------------------------------------------------------------
23894    -- LCDIF Peripheral Access Layer
23895    ---------------------------------------------------------------------------- */
23896 
23897 /*!
23898  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
23899  * @{
23900  */
23901 
23902 /** LCDIF - Register Layout Typedef */
23903 typedef struct {
23904   __IO  uint32_t RL;                                     /**< eLCDIF General Control Register, offset: 0x0 */
23905   __IO  uint32_t RL_SET;                                 /**< eLCDIF General Control Register, offset: 0x4 */
23906   __IO  uint32_t RL_CLR;                                 /**< eLCDIF General Control Register, offset: 0x8 */
23907   __IO  uint32_t RL_TOG;                                 /**< eLCDIF General Control Register, offset: 0xC */
23908   __IO  uint32_t CTRL1;                                  /**< eLCDIF General Control1 Register, offset: 0x10 */
23909   __IO  uint32_t CTRL1_SET;                              /**< eLCDIF General Control1 Register, offset: 0x14 */
23910   __IO  uint32_t CTRL1_CLR;                              /**< eLCDIF General Control1 Register, offset: 0x18 */
23911   __IO  uint32_t CTRL1_TOG;                              /**< eLCDIF General Control1 Register, offset: 0x1C */
23912   __IO  uint32_t CTRL2;                                  /**< eLCDIF General Control2 Register, offset: 0x20 */
23913   __IO  uint32_t CTRL2_SET;                              /**< eLCDIF General Control2 Register, offset: 0x24 */
23914   __IO  uint32_t CTRL2_CLR;                              /**< eLCDIF General Control2 Register, offset: 0x28 */
23915   __IO  uint32_t CTRL2_TOG;                              /**< eLCDIF General Control2 Register, offset: 0x2C */
23916   __IO  uint32_t TRANSFER_COUNT;                         /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
23917   uint8_t RESERVED_0[12];
23918   __IO  uint32_t CUR_BUF;                                /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
23919   uint8_t RESERVED_1[12];
23920   __IO  uint32_t NEXT_BUF;                               /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
23921   uint8_t RESERVED_2[12];
23922   __IO  uint32_t TIMING;                                 /**< LCD Interface Timing Register, offset: 0x60 */
23923   uint8_t RESERVED_3[12];
23924   __IO  uint32_t VDCTRL0;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
23925   __IO  uint32_t VDCTRL0_SET;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
23926   __IO  uint32_t VDCTRL0_CLR;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
23927   __IO  uint32_t VDCTRL0_TOG;                            /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
23928   __IO  uint32_t VDCTRL1;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
23929   uint8_t RESERVED_4[12];
23930   __IO  uint32_t VDCTRL2;                                /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
23931   uint8_t RESERVED_5[12];
23932   __IO  uint32_t VDCTRL3;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
23933   uint8_t RESERVED_6[12];
23934   __IO  uint32_t VDCTRL4;                                /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
23935   uint8_t RESERVED_7[12];
23936   __IO  uint32_t DVICTRL0;                               /**< Digital Video Interface Control0 Register, offset: 0xC0 */
23937   uint8_t RESERVED_8[12];
23938   __IO  uint32_t DVICTRL1;                               /**< Digital Video Interface Control1 Register, offset: 0xD0 */
23939   uint8_t RESERVED_9[12];
23940   __IO  uint32_t DVICTRL2;                               /**< Digital Video Interface Control2 Register, offset: 0xE0 */
23941   uint8_t RESERVED_10[12];
23942   __IO  uint32_t DVICTRL3;                               /**< Digital Video Interface Control3 Register, offset: 0xF0 */
23943   uint8_t RESERVED_11[12];
23944   __IO  uint32_t DVICTRL4;                               /**< Digital Video Interface Control4 Register, offset: 0x100 */
23945   uint8_t RESERVED_12[12];
23946   __IO  uint32_t CSC_COEFF0;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */
23947   uint8_t RESERVED_13[12];
23948   __IO  uint32_t CSC_COEFF1;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */
23949   uint8_t RESERVED_14[12];
23950   __IO  uint32_t CSC_COEFF2;                             /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */
23951   uint8_t RESERVED_15[12];
23952   __IO  uint32_t CSC_COEFF3;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */
23953   uint8_t RESERVED_16[12];
23954   __IO  uint32_t CSC_COEFF4;                             /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */
23955   uint8_t RESERVED_17[12];
23956   __IO  uint32_t CSC_OFFSET;                             /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */
23957   uint8_t RESERVED_18[12];
23958   __IO  uint32_t CSC_LIMIT;                              /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */
23959   uint8_t RESERVED_19[12];
23960   __IO  uint32_t DATA;                                   /**< LCD Interface Data Register, offset: 0x180 */
23961   uint8_t RESERVED_20[12];
23962   __IO  uint32_t BM_ERROR_STAT;                          /**< Bus Master Error Status Register, offset: 0x190 */
23963   uint8_t RESERVED_21[12];
23964   __IO  uint32_t CRC_STAT;                               /**< CRC Status Register, offset: 0x1A0 */
23965   uint8_t RESERVED_22[12];
23966   __I   uint32_t STAT;                                   /**< LCD Interface Status Register, offset: 0x1B0 */
23967   uint8_t RESERVED_23[12];
23968   __I   uint32_t VERSION;                                /**< LCD Interface Version Register, offset: 0x1C0 */
23969   uint8_t RESERVED_24[12];
23970   __I   uint32_t DEBUG0;                                 /**< LCD Interface Debug0 Register, offset: 0x1D0 */
23971   uint8_t RESERVED_25[12];
23972   __I   uint32_t DEBUG1;                                 /**< LCD Interface Debug1 Register, offset: 0x1E0 */
23973   uint8_t RESERVED_26[12];
23974   __I   uint32_t DEBUG2;                                 /**< LCD Interface Debug2 Register, offset: 0x1F0 */
23975   uint8_t RESERVED_27[12];
23976   __IO  uint32_t THRES;                                  /**< eLCDIF Threshold Register, offset: 0x200 */
23977   uint8_t RESERVED_28[12];
23978   __IO  uint32_t AS_CTRL;                                /**< eLCDIF AS Buffer Control Register, offset: 0x210 */
23979   uint8_t RESERVED_29[12];
23980   __IO  uint32_t AS_BUF;                                 /**< Alpha Surface Buffer Pointer, offset: 0x220 */
23981   uint8_t RESERVED_30[12];
23982   __IO  uint32_t AS_NEXT_BUF;                            /**< , offset: 0x230 */
23983   uint8_t RESERVED_31[12];
23984   __IO  uint32_t AS_CLRKEYLOW;                           /**< eLCDIF Overlay Color Key Low, offset: 0x240 */
23985   uint8_t RESERVED_32[12];
23986   __IO  uint32_t AS_CLRKEYHIGH;                          /**< eLCDIF Overlay Color Key High, offset: 0x250 */
23987   uint8_t RESERVED_33[12];
23988   __IO  uint32_t SYNC_DELAY;                             /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */
23989   uint8_t RESERVED_34[12];
23990   __IO  uint32_t DEBUG3;                                 /**< eLCDIF Interface Debug3 Register, offset: 0x270 */
23991   uint8_t RESERVED_35[12];
23992   __IO  uint32_t DEBUG4;                                 /**< LCD Interface Debug4 , offset: 0x280 */
23993   uint8_t RESERVED_36[12];
23994   __IO  uint32_t DEBUG5;                                 /**< LCD Interface Debug5 , offset: 0x290 */
23995 } LCDIF_Type, *LCDIF_MemMapPtr;
23996 
23997 /* ----------------------------------------------------------------------------
23998    -- LCDIF - Register accessor macros
23999    ---------------------------------------------------------------------------- */
24000 
24001 /*!
24002  * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros
24003  * @{
24004  */
24005 
24006 /* LCDIF - Register accessors */
24007 #define LCDIF_RL_REG(base)                       ((base)->RL)
24008 #define LCDIF_RL_SET_REG(base)                   ((base)->RL_SET)
24009 #define LCDIF_RL_CLR_REG(base)                   ((base)->RL_CLR)
24010 #define LCDIF_RL_TOG_REG(base)                   ((base)->RL_TOG)
24011 #define LCDIF_CTRL1_REG(base)                    ((base)->CTRL1)
24012 #define LCDIF_CTRL1_SET_REG(base)                ((base)->CTRL1_SET)
24013 #define LCDIF_CTRL1_CLR_REG(base)                ((base)->CTRL1_CLR)
24014 #define LCDIF_CTRL1_TOG_REG(base)                ((base)->CTRL1_TOG)
24015 #define LCDIF_CTRL2_REG(base)                    ((base)->CTRL2)
24016 #define LCDIF_CTRL2_SET_REG(base)                ((base)->CTRL2_SET)
24017 #define LCDIF_CTRL2_CLR_REG(base)                ((base)->CTRL2_CLR)
24018 #define LCDIF_CTRL2_TOG_REG(base)                ((base)->CTRL2_TOG)
24019 #define LCDIF_TRANSFER_COUNT_REG(base)           ((base)->TRANSFER_COUNT)
24020 #define LCDIF_CUR_BUF_REG(base)                  ((base)->CUR_BUF)
24021 #define LCDIF_NEXT_BUF_REG(base)                 ((base)->NEXT_BUF)
24022 #define LCDIF_TIMING_REG(base)                   ((base)->TIMING)
24023 #define LCDIF_VDCTRL0_REG(base)                  ((base)->VDCTRL0)
24024 #define LCDIF_VDCTRL0_SET_REG(base)              ((base)->VDCTRL0_SET)
24025 #define LCDIF_VDCTRL0_CLR_REG(base)              ((base)->VDCTRL0_CLR)
24026 #define LCDIF_VDCTRL0_TOG_REG(base)              ((base)->VDCTRL0_TOG)
24027 #define LCDIF_VDCTRL1_REG(base)                  ((base)->VDCTRL1)
24028 #define LCDIF_VDCTRL2_REG(base)                  ((base)->VDCTRL2)
24029 #define LCDIF_VDCTRL3_REG(base)                  ((base)->VDCTRL3)
24030 #define LCDIF_VDCTRL4_REG(base)                  ((base)->VDCTRL4)
24031 #define LCDIF_DVICTRL0_REG(base)                 ((base)->DVICTRL0)
24032 #define LCDIF_DVICTRL1_REG(base)                 ((base)->DVICTRL1)
24033 #define LCDIF_DVICTRL2_REG(base)                 ((base)->DVICTRL2)
24034 #define LCDIF_DVICTRL3_REG(base)                 ((base)->DVICTRL3)
24035 #define LCDIF_DVICTRL4_REG(base)                 ((base)->DVICTRL4)
24036 #define LCDIF_CSC_COEFF0_REG(base)               ((base)->CSC_COEFF0)
24037 #define LCDIF_CSC_COEFF1_REG(base)               ((base)->CSC_COEFF1)
24038 #define LCDIF_CSC_COEFF2_REG(base)               ((base)->CSC_COEFF2)
24039 #define LCDIF_CSC_COEFF3_REG(base)               ((base)->CSC_COEFF3)
24040 #define LCDIF_CSC_COEFF4_REG(base)               ((base)->CSC_COEFF4)
24041 #define LCDIF_CSC_OFFSET_REG(base)               ((base)->CSC_OFFSET)
24042 #define LCDIF_CSC_LIMIT_REG(base)                ((base)->CSC_LIMIT)
24043 #define LCDIF_DATA_REG(base)                     ((base)->DATA)
24044 #define LCDIF_BM_ERROR_STAT_REG(base)            ((base)->BM_ERROR_STAT)
24045 #define LCDIF_CRC_STAT_REG(base)                 ((base)->CRC_STAT)
24046 #define LCDIF_STAT_REG(base)                     ((base)->STAT)
24047 #define LCDIF_VERSION_REG(base)                  ((base)->VERSION)
24048 #define LCDIF_DEBUG0_REG(base)                   ((base)->DEBUG0)
24049 #define LCDIF_DEBUG1_REG(base)                   ((base)->DEBUG1)
24050 #define LCDIF_DEBUG2_REG(base)                   ((base)->DEBUG2)
24051 #define LCDIF_THRES_REG(base)                    ((base)->THRES)
24052 #define LCDIF_AS_CTRL_REG(base)                  ((base)->AS_CTRL)
24053 #define LCDIF_AS_BUF_REG(base)                   ((base)->AS_BUF)
24054 #define LCDIF_AS_NEXT_BUF_REG(base)              ((base)->AS_NEXT_BUF)
24055 #define LCDIF_AS_CLRKEYLOW_REG(base)             ((base)->AS_CLRKEYLOW)
24056 #define LCDIF_AS_CLRKEYHIGH_REG(base)            ((base)->AS_CLRKEYHIGH)
24057 #define LCDIF_SYNC_DELAY_REG(base)               ((base)->SYNC_DELAY)
24058 #define LCDIF_DEBUG3_REG(base)                   ((base)->DEBUG3)
24059 #define LCDIF_DEBUG4_REG(base)                   ((base)->DEBUG4)
24060 #define LCDIF_DEBUG5_REG(base)                   ((base)->DEBUG5)
24061 
24062 /*!
24063  * @}
24064  */ /* end of group LCDIF_Register_Accessor_Macros */
24065 
24066 /* ----------------------------------------------------------------------------
24067    -- LCDIF Register Masks
24068    ---------------------------------------------------------------------------- */
24069 
24070 /*!
24071  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
24072  * @{
24073  */
24074 
24075 /* RL Bit Fields */
24076 #define LCDIF_RL_RUN_MASK                        0x1u
24077 #define LCDIF_RL_RUN_SHIFT                       0
24078 #define LCDIF_RL_DATA_FORMAT_24_BIT_MASK         0x2u
24079 #define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT        1
24080 #define LCDIF_RL_DATA_FORMAT_18_BIT_MASK         0x4u
24081 #define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT        2
24082 #define LCDIF_RL_DATA_FORMAT_16_BIT_MASK         0x8u
24083 #define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT        3
24084 #define LCDIF_RL_RSRVD0_MASK                     0x10u
24085 #define LCDIF_RL_RSRVD0_SHIFT                    4
24086 #define LCDIF_RL_MASTER_MASK                     0x20u
24087 #define LCDIF_RL_MASTER_SHIFT                    5
24088 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK       0x40u
24089 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT      6
24090 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK        0x80u
24091 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT       7
24092 #define LCDIF_RL_WORD_LENGTH_MASK                0x300u
24093 #define LCDIF_RL_WORD_LENGTH_SHIFT               8
24094 #define LCDIF_RL_WORD_LENGTH(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_WORD_LENGTH_SHIFT))&LCDIF_RL_WORD_LENGTH_MASK)
24095 #define LCDIF_RL_LCD_DATABUS_WIDTH_MASK          0xC00u
24096 #define LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT         10
24097 #define LCDIF_RL_LCD_DATABUS_WIDTH(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_LCD_DATABUS_WIDTH_MASK)
24098 #define LCDIF_RL_CSC_DATA_SWIZZLE_MASK           0x3000u
24099 #define LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT          12
24100 #define LCDIF_RL_CSC_DATA_SWIZZLE(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CSC_DATA_SWIZZLE_MASK)
24101 #define LCDIF_RL_INPUT_DATA_SWIZZLE_MASK         0xC000u
24102 #define LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT        14
24103 #define LCDIF_RL_INPUT_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_INPUT_DATA_SWIZZLE_MASK)
24104 #define LCDIF_RL_DATA_SELECT_MASK                0x10000u
24105 #define LCDIF_RL_DATA_SELECT_SHIFT               16
24106 #define LCDIF_RL_DOTCLK_MODE_MASK                0x20000u
24107 #define LCDIF_RL_DOTCLK_MODE_SHIFT               17
24108 #define LCDIF_RL_VSYNC_MODE_MASK                 0x40000u
24109 #define LCDIF_RL_VSYNC_MODE_SHIFT                18
24110 #define LCDIF_RL_BYPASS_COUNT_MASK               0x80000u
24111 #define LCDIF_RL_BYPASS_COUNT_SHIFT              19
24112 #define LCDIF_RL_DVI_MODE_MASK                   0x100000u
24113 #define LCDIF_RL_DVI_MODE_SHIFT                  20
24114 #define LCDIF_RL_SHIFT_NUM_BITS_MASK             0x3E00000u
24115 #define LCDIF_RL_SHIFT_NUM_BITS_SHIFT            21
24116 #define LCDIF_RL_SHIFT_NUM_BITS(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SHIFT_NUM_BITS_MASK)
24117 #define LCDIF_RL_DATA_SHIFT_DIR_MASK             0x4000000u
24118 #define LCDIF_RL_DATA_SHIFT_DIR_SHIFT            26
24119 #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_MASK        0x8000000u
24120 #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_SHIFT       27
24121 #define LCDIF_RL_READ_WRITEB_MASK                0x10000000u
24122 #define LCDIF_RL_READ_WRITEB_SHIFT               28
24123 #define LCDIF_RL_YCBCR422_INPUT_MASK             0x20000000u
24124 #define LCDIF_RL_YCBCR422_INPUT_SHIFT            29
24125 #define LCDIF_RL_CLKGATE_MASK                    0x40000000u
24126 #define LCDIF_RL_CLKGATE_SHIFT                   30
24127 #define LCDIF_RL_SFTRST_MASK                     0x80000000u
24128 #define LCDIF_RL_SFTRST_SHIFT                    31
24129 /* RL_SET Bit Fields */
24130 #define LCDIF_RL_SET_RUN_MASK                    0x1u
24131 #define LCDIF_RL_SET_RUN_SHIFT                   0
24132 #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_MASK     0x2u
24133 #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_SHIFT    1
24134 #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_MASK     0x4u
24135 #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_SHIFT    2
24136 #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_MASK     0x8u
24137 #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_SHIFT    3
24138 #define LCDIF_RL_SET_RSRVD0_MASK                 0x10u
24139 #define LCDIF_RL_SET_RSRVD0_SHIFT                4
24140 #define LCDIF_RL_SET_MASTER_MASK                 0x20u
24141 #define LCDIF_RL_SET_MASTER_SHIFT                5
24142 #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_MASK   0x40u
24143 #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_SHIFT  6
24144 #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_MASK    0x80u
24145 #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_SHIFT   7
24146 #define LCDIF_RL_SET_WORD_LENGTH_MASK            0x300u
24147 #define LCDIF_RL_SET_WORD_LENGTH_SHIFT           8
24148 #define LCDIF_RL_SET_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_WORD_LENGTH_SHIFT))&LCDIF_RL_SET_WORD_LENGTH_MASK)
24149 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK      0xC00u
24150 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT     10
24151 #define LCDIF_RL_SET_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK)
24152 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK       0x3000u
24153 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT      12
24154 #define LCDIF_RL_SET_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK)
24155 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK     0xC000u
24156 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT    14
24157 #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK)
24158 #define LCDIF_RL_SET_DATA_SELECT_MASK            0x10000u
24159 #define LCDIF_RL_SET_DATA_SELECT_SHIFT           16
24160 #define LCDIF_RL_SET_DOTCLK_MODE_MASK            0x20000u
24161 #define LCDIF_RL_SET_DOTCLK_MODE_SHIFT           17
24162 #define LCDIF_RL_SET_VSYNC_MODE_MASK             0x40000u
24163 #define LCDIF_RL_SET_VSYNC_MODE_SHIFT            18
24164 #define LCDIF_RL_SET_BYPASS_COUNT_MASK           0x80000u
24165 #define LCDIF_RL_SET_BYPASS_COUNT_SHIFT          19
24166 #define LCDIF_RL_SET_DVI_MODE_MASK               0x100000u
24167 #define LCDIF_RL_SET_DVI_MODE_SHIFT              20
24168 #define LCDIF_RL_SET_SHIFT_NUM_BITS_MASK         0x3E00000u
24169 #define LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT        21
24170 #define LCDIF_RL_SET_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SET_SHIFT_NUM_BITS_MASK)
24171 #define LCDIF_RL_SET_DATA_SHIFT_DIR_MASK         0x4000000u
24172 #define LCDIF_RL_SET_DATA_SHIFT_DIR_SHIFT        26
24173 #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
24174 #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT   27
24175 #define LCDIF_RL_SET_READ_WRITEB_MASK            0x10000000u
24176 #define LCDIF_RL_SET_READ_WRITEB_SHIFT           28
24177 #define LCDIF_RL_SET_YCBCR422_INPUT_MASK         0x20000000u
24178 #define LCDIF_RL_SET_YCBCR422_INPUT_SHIFT        29
24179 #define LCDIF_RL_SET_CLKGATE_MASK                0x40000000u
24180 #define LCDIF_RL_SET_CLKGATE_SHIFT               30
24181 #define LCDIF_RL_SET_SFTRST_MASK                 0x80000000u
24182 #define LCDIF_RL_SET_SFTRST_SHIFT                31
24183 /* RL_CLR Bit Fields */
24184 #define LCDIF_RL_CLR_RUN_MASK                    0x1u
24185 #define LCDIF_RL_CLR_RUN_SHIFT                   0
24186 #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_MASK     0x2u
24187 #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_SHIFT    1
24188 #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_MASK     0x4u
24189 #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_SHIFT    2
24190 #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_MASK     0x8u
24191 #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_SHIFT    3
24192 #define LCDIF_RL_CLR_RSRVD0_MASK                 0x10u
24193 #define LCDIF_RL_CLR_RSRVD0_SHIFT                4
24194 #define LCDIF_RL_CLR_MASTER_MASK                 0x20u
24195 #define LCDIF_RL_CLR_MASTER_SHIFT                5
24196 #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_MASK   0x40u
24197 #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT  6
24198 #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_MASK    0x80u
24199 #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_SHIFT   7
24200 #define LCDIF_RL_CLR_WORD_LENGTH_MASK            0x300u
24201 #define LCDIF_RL_CLR_WORD_LENGTH_SHIFT           8
24202 #define LCDIF_RL_CLR_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_WORD_LENGTH_SHIFT))&LCDIF_RL_CLR_WORD_LENGTH_MASK)
24203 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK      0xC00u
24204 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT     10
24205 #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK)
24206 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK       0x3000u
24207 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT      12
24208 #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK)
24209 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK     0xC000u
24210 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT    14
24211 #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK)
24212 #define LCDIF_RL_CLR_DATA_SELECT_MASK            0x10000u
24213 #define LCDIF_RL_CLR_DATA_SELECT_SHIFT           16
24214 #define LCDIF_RL_CLR_DOTCLK_MODE_MASK            0x20000u
24215 #define LCDIF_RL_CLR_DOTCLK_MODE_SHIFT           17
24216 #define LCDIF_RL_CLR_VSYNC_MODE_MASK             0x40000u
24217 #define LCDIF_RL_CLR_VSYNC_MODE_SHIFT            18
24218 #define LCDIF_RL_CLR_BYPASS_COUNT_MASK           0x80000u
24219 #define LCDIF_RL_CLR_BYPASS_COUNT_SHIFT          19
24220 #define LCDIF_RL_CLR_DVI_MODE_MASK               0x100000u
24221 #define LCDIF_RL_CLR_DVI_MODE_SHIFT              20
24222 #define LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK         0x3E00000u
24223 #define LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT        21
24224 #define LCDIF_RL_CLR_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK)
24225 #define LCDIF_RL_CLR_DATA_SHIFT_DIR_MASK         0x4000000u
24226 #define LCDIF_RL_CLR_DATA_SHIFT_DIR_SHIFT        26
24227 #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
24228 #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT   27
24229 #define LCDIF_RL_CLR_READ_WRITEB_MASK            0x10000000u
24230 #define LCDIF_RL_CLR_READ_WRITEB_SHIFT           28
24231 #define LCDIF_RL_CLR_YCBCR422_INPUT_MASK         0x20000000u
24232 #define LCDIF_RL_CLR_YCBCR422_INPUT_SHIFT        29
24233 #define LCDIF_RL_CLR_CLKGATE_MASK                0x40000000u
24234 #define LCDIF_RL_CLR_CLKGATE_SHIFT               30
24235 #define LCDIF_RL_CLR_SFTRST_MASK                 0x80000000u
24236 #define LCDIF_RL_CLR_SFTRST_SHIFT                31
24237 /* RL_TOG Bit Fields */
24238 #define LCDIF_RL_TOG_RUN_MASK                    0x1u
24239 #define LCDIF_RL_TOG_RUN_SHIFT                   0
24240 #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_MASK     0x2u
24241 #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_SHIFT    1
24242 #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_MASK     0x4u
24243 #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_SHIFT    2
24244 #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_MASK     0x8u
24245 #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_SHIFT    3
24246 #define LCDIF_RL_TOG_RSRVD0_MASK                 0x10u
24247 #define LCDIF_RL_TOG_RSRVD0_SHIFT                4
24248 #define LCDIF_RL_TOG_MASTER_MASK                 0x20u
24249 #define LCDIF_RL_TOG_MASTER_SHIFT                5
24250 #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_MASK   0x40u
24251 #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT  6
24252 #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_MASK    0x80u
24253 #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_SHIFT   7
24254 #define LCDIF_RL_TOG_WORD_LENGTH_MASK            0x300u
24255 #define LCDIF_RL_TOG_WORD_LENGTH_SHIFT           8
24256 #define LCDIF_RL_TOG_WORD_LENGTH(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_WORD_LENGTH_SHIFT))&LCDIF_RL_TOG_WORD_LENGTH_MASK)
24257 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK      0xC00u
24258 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT     10
24259 #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK)
24260 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK       0x3000u
24261 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT      12
24262 #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK)
24263 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK     0xC000u
24264 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT    14
24265 #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK)
24266 #define LCDIF_RL_TOG_DATA_SELECT_MASK            0x10000u
24267 #define LCDIF_RL_TOG_DATA_SELECT_SHIFT           16
24268 #define LCDIF_RL_TOG_DOTCLK_MODE_MASK            0x20000u
24269 #define LCDIF_RL_TOG_DOTCLK_MODE_SHIFT           17
24270 #define LCDIF_RL_TOG_VSYNC_MODE_MASK             0x40000u
24271 #define LCDIF_RL_TOG_VSYNC_MODE_SHIFT            18
24272 #define LCDIF_RL_TOG_BYPASS_COUNT_MASK           0x80000u
24273 #define LCDIF_RL_TOG_BYPASS_COUNT_SHIFT          19
24274 #define LCDIF_RL_TOG_DVI_MODE_MASK               0x100000u
24275 #define LCDIF_RL_TOG_DVI_MODE_SHIFT              20
24276 #define LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK         0x3E00000u
24277 #define LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT        21
24278 #define LCDIF_RL_TOG_SHIFT_NUM_BITS(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK)
24279 #define LCDIF_RL_TOG_DATA_SHIFT_DIR_MASK         0x4000000u
24280 #define LCDIF_RL_TOG_DATA_SHIFT_DIR_SHIFT        26
24281 #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_MASK    0x8000000u
24282 #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT   27
24283 #define LCDIF_RL_TOG_READ_WRITEB_MASK            0x10000000u
24284 #define LCDIF_RL_TOG_READ_WRITEB_SHIFT           28
24285 #define LCDIF_RL_TOG_YCBCR422_INPUT_MASK         0x20000000u
24286 #define LCDIF_RL_TOG_YCBCR422_INPUT_SHIFT        29
24287 #define LCDIF_RL_TOG_CLKGATE_MASK                0x40000000u
24288 #define LCDIF_RL_TOG_CLKGATE_SHIFT               30
24289 #define LCDIF_RL_TOG_SFTRST_MASK                 0x80000000u
24290 #define LCDIF_RL_TOG_SFTRST_SHIFT                31
24291 /* CTRL1 Bit Fields */
24292 #define LCDIF_CTRL1_RESET_MASK                   0x1u
24293 #define LCDIF_CTRL1_RESET_SHIFT                  0
24294 #define LCDIF_CTRL1_MODE86_MASK                  0x2u
24295 #define LCDIF_CTRL1_MODE86_SHIFT                 1
24296 #define LCDIF_CTRL1_BUSY_ENABLE_MASK             0x4u
24297 #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT            2
24298 #define LCDIF_CTRL1_RSRVD0_MASK                  0xF8u
24299 #define LCDIF_CTRL1_RSRVD0_SHIFT                 3
24300 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD0_SHIFT))&LCDIF_CTRL1_RSRVD0_MASK)
24301 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          0x100u
24302 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         8
24303 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      0x200u
24304 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     9
24305 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           0x400u
24306 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          10
24307 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            0x800u
24308 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           11
24309 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       0x1000u
24310 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      12
24311 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   0x2000u
24312 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  13
24313 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        0x4000u
24314 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       14
24315 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         0x8000u
24316 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        15
24317 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     0xF0000u
24318 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    16
24319 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
24320 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
24321 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
24322 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              0x200000u
24323 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             21
24324 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
24325 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
24326 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        0x800000u
24327 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       23
24328 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    0x1000000u
24329 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   24
24330 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            0x2000000u
24331 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           25
24332 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         0x4000000u
24333 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        26
24334 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK     0x8000000u
24335 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT    27
24336 #define LCDIF_CTRL1_RSRVD1_MASK                  0xF0000000u
24337 #define LCDIF_CTRL1_RSRVD1_SHIFT                 28
24338 #define LCDIF_CTRL1_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD1_SHIFT))&LCDIF_CTRL1_RSRVD1_MASK)
24339 /* CTRL1_SET Bit Fields */
24340 #define LCDIF_CTRL1_SET_RESET_MASK               0x1u
24341 #define LCDIF_CTRL1_SET_RESET_SHIFT              0
24342 #define LCDIF_CTRL1_SET_MODE86_MASK              0x2u
24343 #define LCDIF_CTRL1_SET_MODE86_SHIFT             1
24344 #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK         0x4u
24345 #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT        2
24346 #define LCDIF_CTRL1_SET_RSRVD0_MASK              0xF8u
24347 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             3
24348 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD0_SHIFT))&LCDIF_CTRL1_SET_RSRVD0_MASK)
24349 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      0x100u
24350 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     8
24351 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  0x200u
24352 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT 9
24353 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       0x400u
24354 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      10
24355 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        0x800u
24356 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       11
24357 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
24358 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  12
24359 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
24360 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
24361 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    0x4000u
24362 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   14
24363 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     0x8000u
24364 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    15
24365 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK 0xF0000u
24366 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT 16
24367 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
24368 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
24369 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
24370 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          0x200000u
24371 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         21
24372 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
24373 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
24374 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    0x800000u
24375 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   23
24376 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
24377 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT 24
24378 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        0x2000000u
24379 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       25
24380 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     0x4000000u
24381 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    26
24382 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK 0x8000000u
24383 #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT 27
24384 #define LCDIF_CTRL1_SET_RSRVD1_MASK              0xF0000000u
24385 #define LCDIF_CTRL1_SET_RSRVD1_SHIFT             28
24386 #define LCDIF_CTRL1_SET_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD1_SHIFT))&LCDIF_CTRL1_SET_RSRVD1_MASK)
24387 /* CTRL1_CLR Bit Fields */
24388 #define LCDIF_CTRL1_CLR_RESET_MASK               0x1u
24389 #define LCDIF_CTRL1_CLR_RESET_SHIFT              0
24390 #define LCDIF_CTRL1_CLR_MODE86_MASK              0x2u
24391 #define LCDIF_CTRL1_CLR_MODE86_SHIFT             1
24392 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK         0x4u
24393 #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT        2
24394 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              0xF8u
24395 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             3
24396 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK)
24397 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      0x100u
24398 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     8
24399 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  0x200u
24400 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT 9
24401 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       0x400u
24402 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      10
24403 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        0x800u
24404 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       11
24405 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
24406 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  12
24407 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
24408 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
24409 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    0x4000u
24410 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   14
24411 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     0x8000u
24412 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    15
24413 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK 0xF0000u
24414 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT 16
24415 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
24416 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
24417 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
24418 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          0x200000u
24419 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         21
24420 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
24421 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
24422 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    0x800000u
24423 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   23
24424 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
24425 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT 24
24426 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        0x2000000u
24427 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       25
24428 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     0x4000000u
24429 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    26
24430 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK 0x8000000u
24431 #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT 27
24432 #define LCDIF_CTRL1_CLR_RSRVD1_MASK              0xF0000000u
24433 #define LCDIF_CTRL1_CLR_RSRVD1_SHIFT             28
24434 #define LCDIF_CTRL1_CLR_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD1_SHIFT))&LCDIF_CTRL1_CLR_RSRVD1_MASK)
24435 /* CTRL1_TOG Bit Fields */
24436 #define LCDIF_CTRL1_TOG_RESET_MASK               0x1u
24437 #define LCDIF_CTRL1_TOG_RESET_SHIFT              0
24438 #define LCDIF_CTRL1_TOG_MODE86_MASK              0x2u
24439 #define LCDIF_CTRL1_TOG_MODE86_SHIFT             1
24440 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK         0x4u
24441 #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT        2
24442 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              0xF8u
24443 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             3
24444 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD0_SHIFT))&LCDIF_CTRL1_TOG_RSRVD0_MASK)
24445 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      0x100u
24446 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     8
24447 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  0x200u
24448 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT 9
24449 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       0x400u
24450 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      10
24451 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        0x800u
24452 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       11
24453 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   0x1000u
24454 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  12
24455 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u
24456 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT 13
24457 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    0x4000u
24458 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   14
24459 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     0x8000u
24460 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    15
24461 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK 0xF0000u
24462 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT 16
24463 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
24464 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u
24465 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20
24466 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          0x200000u
24467 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         21
24468 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u
24469 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22
24470 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    0x800000u
24471 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   23
24472 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK 0x1000000u
24473 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT 24
24474 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        0x2000000u
24475 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       25
24476 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     0x4000000u
24477 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    26
24478 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK 0x8000000u
24479 #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT 27
24480 #define LCDIF_CTRL1_TOG_RSRVD1_MASK              0xF0000000u
24481 #define LCDIF_CTRL1_TOG_RSRVD1_SHIFT             28
24482 #define LCDIF_CTRL1_TOG_RSRVD1(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD1_SHIFT))&LCDIF_CTRL1_TOG_RSRVD1_MASK)
24483 /* CTRL2 Bit Fields */
24484 #define LCDIF_CTRL2_RSRVD0_MASK                  0x1u
24485 #define LCDIF_CTRL2_RSRVD0_SHIFT                 0
24486 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK      0xEu
24487 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT     1
24488 #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK)
24489 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
24490 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
24491 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
24492 #define LCDIF_CTRL2_RSRVD1_MASK                  0x80u
24493 #define LCDIF_CTRL2_RSRVD1_SHIFT                 7
24494 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK   0x100u
24495 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT  8
24496 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
24497 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
24498 #define LCDIF_CTRL2_READ_PACK_DIR_MASK           0x400u
24499 #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT          10
24500 #define LCDIF_CTRL2_RSRVD2_MASK                  0x800u
24501 #define LCDIF_CTRL2_RSRVD2_SHIFT                 11
24502 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       0x7000u
24503 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      12
24504 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
24505 #define LCDIF_CTRL2_RSRVD3_MASK                  0x8000u
24506 #define LCDIF_CTRL2_RSRVD3_SHIFT                 15
24507 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        0x70000u
24508 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       16
24509 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
24510 #define LCDIF_CTRL2_RSRVD4_MASK                  0x80000u
24511 #define LCDIF_CTRL2_RSRVD4_SHIFT                 19
24512 #define LCDIF_CTRL2_BURST_LEN_8_MASK             0x100000u
24513 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            20
24514 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        0xE00000u
24515 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       21
24516 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
24517 #define LCDIF_CTRL2_RSRVD5_MASK                  0xFF000000u
24518 #define LCDIF_CTRL2_RSRVD5_SHIFT                 24
24519 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_RSRVD5_SHIFT))&LCDIF_CTRL2_RSRVD5_MASK)
24520 /* CTRL2_SET Bit Fields */
24521 #define LCDIF_CTRL2_SET_RSRVD0_MASK              0x1u
24522 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             0
24523 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK  0xEu
24524 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT 1
24525 #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK)
24526 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
24527 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
24528 #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
24529 #define LCDIF_CTRL2_SET_RSRVD1_MASK              0x80u
24530 #define LCDIF_CTRL2_SET_RSRVD1_SHIFT             7
24531 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK 0x100u
24532 #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT 8
24533 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
24534 #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
24535 #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK       0x400u
24536 #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT      10
24537 #define LCDIF_CTRL2_SET_RSRVD2_MASK              0x800u
24538 #define LCDIF_CTRL2_SET_RSRVD2_SHIFT             11
24539 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   0x7000u
24540 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  12
24541 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
24542 #define LCDIF_CTRL2_SET_RSRVD3_MASK              0x8000u
24543 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             15
24544 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    0x70000u
24545 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   16
24546 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
24547 #define LCDIF_CTRL2_SET_RSRVD4_MASK              0x80000u
24548 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             19
24549 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         0x100000u
24550 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        20
24551 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    0xE00000u
24552 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   21
24553 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
24554 #define LCDIF_CTRL2_SET_RSRVD5_MASK              0xFF000000u
24555 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             24
24556 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_RSRVD5_SHIFT))&LCDIF_CTRL2_SET_RSRVD5_MASK)
24557 /* CTRL2_CLR Bit Fields */
24558 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              0x1u
24559 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             0
24560 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK  0xEu
24561 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT 1
24562 #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK)
24563 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
24564 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
24565 #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
24566 #define LCDIF_CTRL2_CLR_RSRVD1_MASK              0x80u
24567 #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT             7
24568 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK 0x100u
24569 #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT 8
24570 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
24571 #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
24572 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK       0x400u
24573 #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT      10
24574 #define LCDIF_CTRL2_CLR_RSRVD2_MASK              0x800u
24575 #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT             11
24576 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   0x7000u
24577 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  12
24578 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
24579 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              0x8000u
24580 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             15
24581 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    0x70000u
24582 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   16
24583 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
24584 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              0x80000u
24585 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             19
24586 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         0x100000u
24587 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        20
24588 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    0xE00000u
24589 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   21
24590 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
24591 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              0xFF000000u
24592 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             24
24593 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_RSRVD5_SHIFT))&LCDIF_CTRL2_CLR_RSRVD5_MASK)
24594 /* CTRL2_TOG Bit Fields */
24595 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              0x1u
24596 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             0
24597 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK  0xEu
24598 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT 1
24599 #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK)
24600 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u
24601 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4
24602 #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
24603 #define LCDIF_CTRL2_TOG_RSRVD1_MASK              0x80u
24604 #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT             7
24605 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK 0x100u
24606 #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT 8
24607 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u
24608 #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9
24609 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK       0x400u
24610 #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT      10
24611 #define LCDIF_CTRL2_TOG_RSRVD2_MASK              0x800u
24612 #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT             11
24613 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   0x7000u
24614 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  12
24615 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
24616 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              0x8000u
24617 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             15
24618 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    0x70000u
24619 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   16
24620 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
24621 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              0x80000u
24622 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             19
24623 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         0x100000u
24624 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        20
24625 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    0xE00000u
24626 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   21
24627 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
24628 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              0xFF000000u
24629 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             24
24630 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK)
24631 /* TRANSFER_COUNT Bit Fields */
24632 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        0xFFFFu
24633 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       0
24634 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
24635 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        0xFFFF0000u
24636 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       16
24637 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
24638 /* CUR_BUF Bit Fields */
24639 #define LCDIF_CUR_BUF_ADDR_MASK                  0xFFFFFFFFu
24640 #define LCDIF_CUR_BUF_ADDR_SHIFT                 0
24641 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_CUR_BUF_ADDR_SHIFT))&LCDIF_CUR_BUF_ADDR_MASK)
24642 /* NEXT_BUF Bit Fields */
24643 #define LCDIF_NEXT_BUF_ADDR_MASK                 0xFFFFFFFFu
24644 #define LCDIF_NEXT_BUF_ADDR_SHIFT                0
24645 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_NEXT_BUF_ADDR_SHIFT))&LCDIF_NEXT_BUF_ADDR_MASK)
24646 /* TIMING Bit Fields */
24647 #define LCDIF_TIMING_DATA_SETUP_MASK             0xFFu
24648 #define LCDIF_TIMING_DATA_SETUP_SHIFT            0
24649 #define LCDIF_TIMING_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_SETUP_SHIFT))&LCDIF_TIMING_DATA_SETUP_MASK)
24650 #define LCDIF_TIMING_DATA_HOLD_MASK              0xFF00u
24651 #define LCDIF_TIMING_DATA_HOLD_SHIFT             8
24652 #define LCDIF_TIMING_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_HOLD_SHIFT))&LCDIF_TIMING_DATA_HOLD_MASK)
24653 #define LCDIF_TIMING_CMD_SETUP_MASK              0xFF0000u
24654 #define LCDIF_TIMING_CMD_SETUP_SHIFT             16
24655 #define LCDIF_TIMING_CMD_SETUP(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_SETUP_SHIFT))&LCDIF_TIMING_CMD_SETUP_MASK)
24656 #define LCDIF_TIMING_CMD_HOLD_MASK               0xFF000000u
24657 #define LCDIF_TIMING_CMD_HOLD_SHIFT              24
24658 #define LCDIF_TIMING_CMD_HOLD(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_HOLD_SHIFT))&LCDIF_TIMING_CMD_HOLD_MASK)
24659 /* VDCTRL0 Bit Fields */
24660 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     0x3FFFFu
24661 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    0
24662 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
24663 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        0x40000u
24664 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       18
24665 #define LCDIF_VDCTRL0_HALF_LINE_MASK             0x80000u
24666 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            19
24667 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
24668 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
24669 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     0x200000u
24670 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    21
24671 #define LCDIF_VDCTRL0_RSRVD1_MASK                0xC00000u
24672 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               22
24673 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD1_SHIFT))&LCDIF_VDCTRL0_RSRVD1_MASK)
24674 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            0x1000000u
24675 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           24
24676 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            0x2000000u
24677 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           25
24678 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             0x4000000u
24679 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            26
24680 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             0x8000000u
24681 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            27
24682 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        0x10000000u
24683 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       28
24684 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             0x20000000u
24685 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            29
24686 #define LCDIF_VDCTRL0_RSRVD2_MASK                0xC0000000u
24687 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               30
24688 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD2_SHIFT))&LCDIF_VDCTRL0_RSRVD2_MASK)
24689 /* VDCTRL0_SET Bit Fields */
24690 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
24691 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT 0
24692 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
24693 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    0x40000u
24694 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   18
24695 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         0x80000u
24696 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        19
24697 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
24698 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
24699 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK 0x200000u
24700 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT 21
24701 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            0xC00000u
24702 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           22
24703 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD1_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD1_MASK)
24704 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        0x1000000u
24705 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       24
24706 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        0x2000000u
24707 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       25
24708 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         0x4000000u
24709 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        26
24710 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         0x8000000u
24711 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        27
24712 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    0x10000000u
24713 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   28
24714 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         0x20000000u
24715 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        29
24716 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            0xC0000000u
24717 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           30
24718 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD2_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD2_MASK)
24719 /* VDCTRL0_CLR Bit Fields */
24720 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
24721 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT 0
24722 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
24723 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    0x40000u
24724 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   18
24725 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         0x80000u
24726 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        19
24727 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
24728 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
24729 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK 0x200000u
24730 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT 21
24731 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            0xC00000u
24732 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           22
24733 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
24734 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        0x1000000u
24735 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       24
24736 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        0x2000000u
24737 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       25
24738 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         0x4000000u
24739 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        26
24740 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         0x8000000u
24741 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        27
24742 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    0x10000000u
24743 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   28
24744 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         0x20000000u
24745 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        29
24746 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            0xC0000000u
24747 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           30
24748 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
24749 /* VDCTRL0_TOG Bit Fields */
24750 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu
24751 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT 0
24752 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
24753 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    0x40000u
24754 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   18
24755 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         0x80000u
24756 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        19
24757 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u
24758 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20
24759 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK 0x200000u
24760 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT 21
24761 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            0xC00000u
24762 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           22
24763 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
24764 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        0x1000000u
24765 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       24
24766 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        0x2000000u
24767 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       25
24768 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         0x4000000u
24769 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        26
24770 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         0x8000000u
24771 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        27
24772 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    0x10000000u
24773 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   28
24774 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         0x20000000u
24775 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        29
24776 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            0xC0000000u
24777 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           30
24778 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
24779 /* VDCTRL1 Bit Fields */
24780 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          0xFFFFFFFFu
24781 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         0
24782 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
24783 /* VDCTRL2 Bit Fields */
24784 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          0x3FFFFu
24785 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         0
24786 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
24787 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     0xFFFC0000u
24788 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    18
24789 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
24790 /* VDCTRL3 Bit Fields */
24791 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     0xFFFFu
24792 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    0
24793 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
24794 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   0xFFF0000u
24795 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  16
24796 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
24797 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            0x10000000u
24798 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           28
24799 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      0x20000000u
24800 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     29
24801 #define LCDIF_VDCTRL3_RSRVD0_MASK                0xC0000000u
24802 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               30
24803 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK)
24804 /* VDCTRL4 Bit Fields */
24805 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3FFFFu
24806 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT 0
24807 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT))&LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
24808 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       0x40000u
24809 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      18
24810 #define LCDIF_VDCTRL4_RSRVD0_MASK                0x1FF80000u
24811 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               19
24812 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_RSRVD0_SHIFT))&LCDIF_VDCTRL4_RSRVD0_MASK)
24813 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        0xE0000000u
24814 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       29
24815 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT))&LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
24816 /* DVICTRL0 Bit Fields */
24817 #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK       0xFFFu
24818 #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT      0
24819 #define LCDIF_DVICTRL0_H_BLANKING_CNT(x)         (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT))&LCDIF_DVICTRL0_H_BLANKING_CNT_MASK)
24820 #define LCDIF_DVICTRL0_RSRVD0_MASK               0xF000u
24821 #define LCDIF_DVICTRL0_RSRVD0_SHIFT              12
24822 #define LCDIF_DVICTRL0_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD0_SHIFT))&LCDIF_DVICTRL0_RSRVD0_MASK)
24823 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK         0xFFF0000u
24824 #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT        16
24825 #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT))&LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK)
24826 #define LCDIF_DVICTRL0_RSRVD1_MASK               0xF0000000u
24827 #define LCDIF_DVICTRL0_RSRVD1_SHIFT              28
24828 #define LCDIF_DVICTRL0_RSRVD1(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD1_SHIFT))&LCDIF_DVICTRL0_RSRVD1_MASK)
24829 /* DVICTRL1 Bit Fields */
24830 #define LCDIF_DVICTRL1_F2_START_LINE_MASK        0x3FFu
24831 #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT       0
24832 #define LCDIF_DVICTRL1_F2_START_LINE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F2_START_LINE_SHIFT))&LCDIF_DVICTRL1_F2_START_LINE_MASK)
24833 #define LCDIF_DVICTRL1_F1_END_LINE_MASK          0xFFC00u
24834 #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT         10
24835 #define LCDIF_DVICTRL1_F1_END_LINE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_END_LINE_SHIFT))&LCDIF_DVICTRL1_F1_END_LINE_MASK)
24836 #define LCDIF_DVICTRL1_F1_START_LINE_MASK        0x3FF00000u
24837 #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT       20
24838 #define LCDIF_DVICTRL1_F1_START_LINE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_START_LINE_SHIFT))&LCDIF_DVICTRL1_F1_START_LINE_MASK)
24839 #define LCDIF_DVICTRL1_RSRVD0_MASK               0xC0000000u
24840 #define LCDIF_DVICTRL1_RSRVD0_SHIFT              30
24841 #define LCDIF_DVICTRL1_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_RSRVD0_SHIFT))&LCDIF_DVICTRL1_RSRVD0_MASK)
24842 /* DVICTRL2 Bit Fields */
24843 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK    0x3FFu
24844 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT   0
24845 #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK)
24846 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK  0xFFC00u
24847 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT 10
24848 #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK)
24849 #define LCDIF_DVICTRL2_F2_END_LINE_MASK          0x3FF00000u
24850 #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT         20
24851 #define LCDIF_DVICTRL2_F2_END_LINE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_F2_END_LINE_SHIFT))&LCDIF_DVICTRL2_F2_END_LINE_MASK)
24852 #define LCDIF_DVICTRL2_RSRVD0_MASK               0xC0000000u
24853 #define LCDIF_DVICTRL2_RSRVD0_SHIFT              30
24854 #define LCDIF_DVICTRL2_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_RSRVD0_SHIFT))&LCDIF_DVICTRL2_RSRVD0_MASK)
24855 /* DVICTRL3 Bit Fields */
24856 #define LCDIF_DVICTRL3_V_LINES_CNT_MASK          0x3FFu
24857 #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT         0
24858 #define LCDIF_DVICTRL3_V_LINES_CNT(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V_LINES_CNT_SHIFT))&LCDIF_DVICTRL3_V_LINES_CNT_MASK)
24859 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK    0xFFC00u
24860 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT   10
24861 #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK)
24862 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK  0x3FF00000u
24863 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT 20
24864 #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x)    (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK)
24865 #define LCDIF_DVICTRL3_RSRVD0_MASK               0xC0000000u
24866 #define LCDIF_DVICTRL3_RSRVD0_SHIFT              30
24867 #define LCDIF_DVICTRL3_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_RSRVD0_SHIFT))&LCDIF_DVICTRL3_RSRVD0_MASK)
24868 /* DVICTRL4 Bit Fields */
24869 #define LCDIF_DVICTRL4_H_FILL_CNT_MASK           0xFFu
24870 #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT          0
24871 #define LCDIF_DVICTRL4_H_FILL_CNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_H_FILL_CNT_SHIFT))&LCDIF_DVICTRL4_H_FILL_CNT_MASK)
24872 #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK        0xFF00u
24873 #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT       8
24874 #define LCDIF_DVICTRL4_CR_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CR_FILL_VALUE_MASK)
24875 #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK        0xFF0000u
24876 #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT       16
24877 #define LCDIF_DVICTRL4_CB_FILL_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CB_FILL_VALUE_MASK)
24878 #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK         0xFF000000u
24879 #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT        24
24880 #define LCDIF_DVICTRL4_Y_FILL_VALUE(x)           (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_Y_FILL_VALUE_MASK)
24881 /* CSC_COEFF0 Bit Fields */
24882 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK 0x3u
24883 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT 0
24884 #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT))&LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK)
24885 #define LCDIF_CSC_COEFF0_RSRVD0_MASK             0xFFFCu
24886 #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT            2
24887 #define LCDIF_CSC_COEFF0_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD0_SHIFT))&LCDIF_CSC_COEFF0_RSRVD0_MASK)
24888 #define LCDIF_CSC_COEFF0_C0_MASK                 0x3FF0000u
24889 #define LCDIF_CSC_COEFF0_C0_SHIFT                16
24890 #define LCDIF_CSC_COEFF0_C0(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_C0_SHIFT))&LCDIF_CSC_COEFF0_C0_MASK)
24891 #define LCDIF_CSC_COEFF0_RSRVD1_MASK             0xFC000000u
24892 #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT            26
24893 #define LCDIF_CSC_COEFF0_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD1_SHIFT))&LCDIF_CSC_COEFF0_RSRVD1_MASK)
24894 /* CSC_COEFF1 Bit Fields */
24895 #define LCDIF_CSC_COEFF1_C1_MASK                 0x3FFu
24896 #define LCDIF_CSC_COEFF1_C1_SHIFT                0
24897 #define LCDIF_CSC_COEFF1_C1(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C1_SHIFT))&LCDIF_CSC_COEFF1_C1_MASK)
24898 #define LCDIF_CSC_COEFF1_RSRVD0_MASK             0xFC00u
24899 #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT            10
24900 #define LCDIF_CSC_COEFF1_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD0_SHIFT))&LCDIF_CSC_COEFF1_RSRVD0_MASK)
24901 #define LCDIF_CSC_COEFF1_C2_MASK                 0x3FF0000u
24902 #define LCDIF_CSC_COEFF1_C2_SHIFT                16
24903 #define LCDIF_CSC_COEFF1_C2(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C2_SHIFT))&LCDIF_CSC_COEFF1_C2_MASK)
24904 #define LCDIF_CSC_COEFF1_RSRVD1_MASK             0xFC000000u
24905 #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT            26
24906 #define LCDIF_CSC_COEFF1_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD1_SHIFT))&LCDIF_CSC_COEFF1_RSRVD1_MASK)
24907 /* CSC_COEFF2 Bit Fields */
24908 #define LCDIF_CSC_COEFF2_C3_MASK                 0x3FFu
24909 #define LCDIF_CSC_COEFF2_C3_SHIFT                0
24910 #define LCDIF_CSC_COEFF2_C3(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C3_SHIFT))&LCDIF_CSC_COEFF2_C3_MASK)
24911 #define LCDIF_CSC_COEFF2_RSRVD0_MASK             0xFC00u
24912 #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT            10
24913 #define LCDIF_CSC_COEFF2_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD0_SHIFT))&LCDIF_CSC_COEFF2_RSRVD0_MASK)
24914 #define LCDIF_CSC_COEFF2_C4_MASK                 0x3FF0000u
24915 #define LCDIF_CSC_COEFF2_C4_SHIFT                16
24916 #define LCDIF_CSC_COEFF2_C4(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C4_SHIFT))&LCDIF_CSC_COEFF2_C4_MASK)
24917 #define LCDIF_CSC_COEFF2_RSRVD1_MASK             0xFC000000u
24918 #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT            26
24919 #define LCDIF_CSC_COEFF2_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD1_SHIFT))&LCDIF_CSC_COEFF2_RSRVD1_MASK)
24920 /* CSC_COEFF3 Bit Fields */
24921 #define LCDIF_CSC_COEFF3_C5_MASK                 0x3FFu
24922 #define LCDIF_CSC_COEFF3_C5_SHIFT                0
24923 #define LCDIF_CSC_COEFF3_C5(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C5_SHIFT))&LCDIF_CSC_COEFF3_C5_MASK)
24924 #define LCDIF_CSC_COEFF3_RSRVD0_MASK             0xFC00u
24925 #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT            10
24926 #define LCDIF_CSC_COEFF3_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD0_SHIFT))&LCDIF_CSC_COEFF3_RSRVD0_MASK)
24927 #define LCDIF_CSC_COEFF3_C6_MASK                 0x3FF0000u
24928 #define LCDIF_CSC_COEFF3_C6_SHIFT                16
24929 #define LCDIF_CSC_COEFF3_C6(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C6_SHIFT))&LCDIF_CSC_COEFF3_C6_MASK)
24930 #define LCDIF_CSC_COEFF3_RSRVD1_MASK             0xFC000000u
24931 #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT            26
24932 #define LCDIF_CSC_COEFF3_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD1_SHIFT))&LCDIF_CSC_COEFF3_RSRVD1_MASK)
24933 /* CSC_COEFF4 Bit Fields */
24934 #define LCDIF_CSC_COEFF4_C7_MASK                 0x3FFu
24935 #define LCDIF_CSC_COEFF4_C7_SHIFT                0
24936 #define LCDIF_CSC_COEFF4_C7(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C7_SHIFT))&LCDIF_CSC_COEFF4_C7_MASK)
24937 #define LCDIF_CSC_COEFF4_RSRVD0_MASK             0xFC00u
24938 #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT            10
24939 #define LCDIF_CSC_COEFF4_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD0_SHIFT))&LCDIF_CSC_COEFF4_RSRVD0_MASK)
24940 #define LCDIF_CSC_COEFF4_C8_MASK                 0x3FF0000u
24941 #define LCDIF_CSC_COEFF4_C8_SHIFT                16
24942 #define LCDIF_CSC_COEFF4_C8(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C8_SHIFT))&LCDIF_CSC_COEFF4_C8_MASK)
24943 #define LCDIF_CSC_COEFF4_RSRVD1_MASK             0xFC000000u
24944 #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT            26
24945 #define LCDIF_CSC_COEFF4_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD1_SHIFT))&LCDIF_CSC_COEFF4_RSRVD1_MASK)
24946 /* CSC_OFFSET Bit Fields */
24947 #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK           0x1FFu
24948 #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT          0
24949 #define LCDIF_CSC_OFFSET_Y_OFFSET(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_Y_OFFSET_MASK)
24950 #define LCDIF_CSC_OFFSET_RSRVD0_MASK             0xFE00u
24951 #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT            9
24952 #define LCDIF_CSC_OFFSET_RSRVD0(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD0_SHIFT))&LCDIF_CSC_OFFSET_RSRVD0_MASK)
24953 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK        0x1FF0000u
24954 #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT       16
24955 #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK)
24956 #define LCDIF_CSC_OFFSET_RSRVD1_MASK             0xFE000000u
24957 #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT            25
24958 #define LCDIF_CSC_OFFSET_RSRVD1(x)               (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD1_SHIFT))&LCDIF_CSC_OFFSET_RSRVD1_MASK)
24959 /* CSC_LIMIT Bit Fields */
24960 #define LCDIF_CSC_LIMIT_Y_MAX_MASK               0xFFu
24961 #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT              0
24962 #define LCDIF_CSC_LIMIT_Y_MAX(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MAX_SHIFT))&LCDIF_CSC_LIMIT_Y_MAX_MASK)
24963 #define LCDIF_CSC_LIMIT_Y_MIN_MASK               0xFF00u
24964 #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT              8
24965 #define LCDIF_CSC_LIMIT_Y_MIN(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MIN_SHIFT))&LCDIF_CSC_LIMIT_Y_MIN_MASK)
24966 #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK            0xFF0000u
24967 #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT           16
24968 #define LCDIF_CSC_LIMIT_CBCR_MAX(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MAX_MASK)
24969 #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK            0xFF000000u
24970 #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT           24
24971 #define LCDIF_CSC_LIMIT_CBCR_MIN(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MIN_MASK)
24972 /* DATA Bit Fields */
24973 #define LCDIF_DATA_DATA_ZERO_MASK                0xFFu
24974 #define LCDIF_DATA_DATA_ZERO_SHIFT               0
24975 #define LCDIF_DATA_DATA_ZERO(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ZERO_SHIFT))&LCDIF_DATA_DATA_ZERO_MASK)
24976 #define LCDIF_DATA_DATA_ONE_MASK                 0xFF00u
24977 #define LCDIF_DATA_DATA_ONE_SHIFT                8
24978 #define LCDIF_DATA_DATA_ONE(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ONE_SHIFT))&LCDIF_DATA_DATA_ONE_MASK)
24979 #define LCDIF_DATA_DATA_TWO_MASK                 0xFF0000u
24980 #define LCDIF_DATA_DATA_TWO_SHIFT                16
24981 #define LCDIF_DATA_DATA_TWO(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_TWO_SHIFT))&LCDIF_DATA_DATA_TWO_MASK)
24982 #define LCDIF_DATA_DATA_THREE_MASK               0xFF000000u
24983 #define LCDIF_DATA_DATA_THREE_SHIFT              24
24984 #define LCDIF_DATA_DATA_THREE(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_THREE_SHIFT))&LCDIF_DATA_DATA_THREE_MASK)
24985 /* BM_ERROR_STAT Bit Fields */
24986 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            0xFFFFFFFFu
24987 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           0
24988 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_BM_ERROR_STAT_ADDR_SHIFT))&LCDIF_BM_ERROR_STAT_ADDR_MASK)
24989 /* CRC_STAT Bit Fields */
24990 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            0xFFFFFFFFu
24991 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           0
24992 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_CRC_STAT_CRC_VALUE_SHIFT))&LCDIF_CRC_STAT_CRC_VALUE_MASK)
24993 /* STAT Bit Fields */
24994 #define LCDIF_STAT_LFIFO_COUNT_MASK              0x1FFu
24995 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             0
24996 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_LFIFO_COUNT_SHIFT))&LCDIF_STAT_LFIFO_COUNT_MASK)
24997 #define LCDIF_STAT_RSRVD0_MASK                   0xFFFE00u
24998 #define LCDIF_STAT_RSRVD0_SHIFT                  9
24999 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_RSRVD0_SHIFT))&LCDIF_STAT_RSRVD0_MASK)
25000 #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK        0x1000000u
25001 #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT       24
25002 #define LCDIF_STAT_BUSY_MASK                     0x2000000u
25003 #define LCDIF_STAT_BUSY_SHIFT                    25
25004 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             0x4000000u
25005 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            26
25006 #define LCDIF_STAT_TXFIFO_FULL_MASK              0x8000000u
25007 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             27
25008 #define LCDIF_STAT_LFIFO_EMPTY_MASK              0x10000000u
25009 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             28
25010 #define LCDIF_STAT_LFIFO_FULL_MASK               0x20000000u
25011 #define LCDIF_STAT_LFIFO_FULL_SHIFT              29
25012 #define LCDIF_STAT_PRESENT_MASK                  0x80000000u
25013 #define LCDIF_STAT_PRESENT_SHIFT                 31
25014 /* VERSION Bit Fields */
25015 #define LCDIF_VERSION_STEP_MASK                  0xFFFFu
25016 #define LCDIF_VERSION_STEP_SHIFT                 0
25017 #define LCDIF_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_STEP_SHIFT))&LCDIF_VERSION_STEP_MASK)
25018 #define LCDIF_VERSION_MINOR_MASK                 0xFF0000u
25019 #define LCDIF_VERSION_MINOR_SHIFT                16
25020 #define LCDIF_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MINOR_SHIFT))&LCDIF_VERSION_MINOR_MASK)
25021 #define LCDIF_VERSION_MAJOR_MASK                 0xFF000000u
25022 #define LCDIF_VERSION_MAJOR_SHIFT                24
25023 #define LCDIF_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MAJOR_SHIFT))&LCDIF_VERSION_MAJOR_MASK)
25024 /* DEBUG0 Bit Fields */
25025 #define LCDIF_DEBUG0_MST_WORDS_MASK              0xFu
25026 #define LCDIF_DEBUG0_MST_WORDS_SHIFT             0
25027 #define LCDIF_DEBUG0_MST_WORDS(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_WORDS_SHIFT))&LCDIF_DEBUG0_MST_WORDS_MASK)
25028 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK   0x1F0u
25029 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT  4
25030 #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK)
25031 #define LCDIF_DEBUG0_MST_AVALID_MASK             0x200u
25032 #define LCDIF_DEBUG0_MST_AVALID_SHIFT            9
25033 #define LCDIF_DEBUG0_CUR_REQ_STATE_MASK          0xC00u
25034 #define LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT         10
25035 #define LCDIF_DEBUG0_CUR_REQ_STATE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG0_CUR_REQ_STATE_MASK)
25036 #define LCDIF_DEBUG0_PXP_B1_DONE_MASK            0x1000u
25037 #define LCDIF_DEBUG0_PXP_B1_DONE_SHIFT           12
25038 #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_MASK     0x2000u
25039 #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_SHIFT    13
25040 #define LCDIF_DEBUG0_PXP_B0_DONE_MASK            0x4000u
25041 #define LCDIF_DEBUG0_PXP_B0_DONE_SHIFT           14
25042 #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_MASK     0x8000u
25043 #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_SHIFT    15
25044 #define LCDIF_DEBUG0_CUR_STATE_MASK              0x7F0000u
25045 #define LCDIF_DEBUG0_CUR_STATE_SHIFT             16
25046 #define LCDIF_DEBUG0_CUR_STATE(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_STATE_SHIFT))&LCDIF_DEBUG0_CUR_STATE_MASK)
25047 #define LCDIF_DEBUG0_EMPTY_WORD_MASK             0x800000u
25048 #define LCDIF_DEBUG0_EMPTY_WORD_SHIFT            23
25049 #define LCDIF_DEBUG0_CUR_FRAME_TX_MASK           0x1000000u
25050 #define LCDIF_DEBUG0_CUR_FRAME_TX_SHIFT          24
25051 #define LCDIF_DEBUG0_VSYNC_MASK                  0x2000000u
25052 #define LCDIF_DEBUG0_VSYNC_SHIFT                 25
25053 #define LCDIF_DEBUG0_HSYNC_MASK                  0x4000000u
25054 #define LCDIF_DEBUG0_HSYNC_SHIFT                 26
25055 #define LCDIF_DEBUG0_ENABLE_MASK                 0x8000000u
25056 #define LCDIF_DEBUG0_ENABLE_SHIFT                27
25057 #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_MASK    0x20000000u
25058 #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_SHIFT   29
25059 #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_MASK 0x40000000u
25060 #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_SHIFT 30
25061 #define LCDIF_DEBUG0_STREAMING_END_DETECTED_MASK 0x80000000u
25062 #define LCDIF_DEBUG0_STREAMING_END_DETECTED_SHIFT 31
25063 /* DEBUG1 Bit Fields */
25064 #define LCDIF_DEBUG1_V_DATA_COUNT_MASK           0xFFFFu
25065 #define LCDIF_DEBUG1_V_DATA_COUNT_SHIFT          0
25066 #define LCDIF_DEBUG1_V_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_V_DATA_COUNT_MASK)
25067 #define LCDIF_DEBUG1_H_DATA_COUNT_MASK           0xFFFF0000u
25068 #define LCDIF_DEBUG1_H_DATA_COUNT_SHIFT          16
25069 #define LCDIF_DEBUG1_H_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_H_DATA_COUNT_MASK)
25070 /* DEBUG2 Bit Fields */
25071 #define LCDIF_DEBUG2_MST_ADDRESS_MASK            0xFFFFFFFFu
25072 #define LCDIF_DEBUG2_MST_ADDRESS_SHIFT           0
25073 #define LCDIF_DEBUG2_MST_ADDRESS(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG2_MST_ADDRESS_SHIFT))&LCDIF_DEBUG2_MST_ADDRESS_MASK)
25074 /* THRES Bit Fields */
25075 #define LCDIF_THRES_PANIC_MASK                   0x1FFu
25076 #define LCDIF_THRES_PANIC_SHIFT                  0
25077 #define LCDIF_THRES_PANIC(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_PANIC_SHIFT))&LCDIF_THRES_PANIC_MASK)
25078 #define LCDIF_THRES_RSRVD1_MASK                  0xFE00u
25079 #define LCDIF_THRES_RSRVD1_SHIFT                 9
25080 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD1_SHIFT))&LCDIF_THRES_RSRVD1_MASK)
25081 #define LCDIF_THRES_FASTCLOCK_MASK               0x1FF0000u
25082 #define LCDIF_THRES_FASTCLOCK_SHIFT              16
25083 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_FASTCLOCK_SHIFT))&LCDIF_THRES_FASTCLOCK_MASK)
25084 #define LCDIF_THRES_RSRVD2_MASK                  0xFE000000u
25085 #define LCDIF_THRES_RSRVD2_SHIFT                 25
25086 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD2_SHIFT))&LCDIF_THRES_RSRVD2_MASK)
25087 /* AS_CTRL Bit Fields */
25088 #define LCDIF_AS_CTRL_AS_ENABLE_MASK             0x1u
25089 #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT            0
25090 #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK            0x6u
25091 #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT           1
25092 #define LCDIF_AS_CTRL_ALPHA_CTRL(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT))&LCDIF_AS_CTRL_ALPHA_CTRL_MASK)
25093 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK       0x8u
25094 #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT      3
25095 #define LCDIF_AS_CTRL_FORMAT_MASK                0xF0u
25096 #define LCDIF_AS_CTRL_FORMAT_SHIFT               4
25097 #define LCDIF_AS_CTRL_FORMAT(x)                  (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_FORMAT_SHIFT))&LCDIF_AS_CTRL_FORMAT_MASK)
25098 #define LCDIF_AS_CTRL_ALPHA_MASK                 0xFF00u
25099 #define LCDIF_AS_CTRL_ALPHA_SHIFT                8
25100 #define LCDIF_AS_CTRL_ALPHA(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_SHIFT))&LCDIF_AS_CTRL_ALPHA_MASK)
25101 #define LCDIF_AS_CTRL_ROP_MASK                   0xF0000u
25102 #define LCDIF_AS_CTRL_ROP_SHIFT                  16
25103 #define LCDIF_AS_CTRL_ROP(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ROP_SHIFT))&LCDIF_AS_CTRL_ROP_MASK)
25104 #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK          0x100000u
25105 #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT         20
25106 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK    0x600000u
25107 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT   21
25108 #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x)      (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK)
25109 #define LCDIF_AS_CTRL_PS_DISABLE_MASK            0x800000u
25110 #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT           23
25111 #define LCDIF_AS_CTRL_RVDS1_MASK                 0x7000000u
25112 #define LCDIF_AS_CTRL_RVDS1_SHIFT                24
25113 #define LCDIF_AS_CTRL_RVDS1(x)                   (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_RVDS1_SHIFT))&LCDIF_AS_CTRL_RVDS1_MASK)
25114 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK       0x8000000u
25115 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT      27
25116 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK    0x10000000u
25117 #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT   28
25118 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK        0x20000000u
25119 #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT       29
25120 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK         0x40000000u
25121 #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT        30
25122 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK      0x80000000u
25123 #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT     31
25124 /* AS_BUF Bit Fields */
25125 #define LCDIF_AS_BUF_ADDR_MASK                   0xFFFFFFFFu
25126 #define LCDIF_AS_BUF_ADDR_SHIFT                  0
25127 #define LCDIF_AS_BUF_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_BUF_ADDR_SHIFT))&LCDIF_AS_BUF_ADDR_MASK)
25128 /* AS_NEXT_BUF Bit Fields */
25129 #define LCDIF_AS_NEXT_BUF_ADDR_MASK              0xFFFFFFFFu
25130 #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT             0
25131 #define LCDIF_AS_NEXT_BUF_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_NEXT_BUF_ADDR_SHIFT))&LCDIF_AS_NEXT_BUF_ADDR_MASK)
25132 /* AS_CLRKEYLOW Bit Fields */
25133 #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK            0xFFFFFFu
25134 #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT           0
25135 #define LCDIF_AS_CLRKEYLOW_PIXEL(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT))&LCDIF_AS_CLRKEYLOW_PIXEL_MASK)
25136 #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK            0xFF000000u
25137 #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT           24
25138 #define LCDIF_AS_CLRKEYLOW_RSVD1(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT))&LCDIF_AS_CLRKEYLOW_RSVD1_MASK)
25139 /* AS_CLRKEYHIGH Bit Fields */
25140 #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK           0xFFFFFFu
25141 #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT          0
25142 #define LCDIF_AS_CLRKEYHIGH_PIXEL(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT))&LCDIF_AS_CLRKEYHIGH_PIXEL_MASK)
25143 #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK           0xFF000000u
25144 #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT          24
25145 #define LCDIF_AS_CLRKEYHIGH_RSVD1(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT))&LCDIF_AS_CLRKEYHIGH_RSVD1_MASK)
25146 /* SYNC_DELAY Bit Fields */
25147 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK      0xFFFFu
25148 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT     0
25149 #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK)
25150 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK      0xFFFF0000u
25151 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT     16
25152 #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK)
25153 /* DEBUG3 Bit Fields */
25154 #define LCDIF_DEBUG3_MST_WORDS_MASK              0xFu
25155 #define LCDIF_DEBUG3_MST_WORDS_SHIFT             0
25156 #define LCDIF_DEBUG3_MST_WORDS(x)                (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_WORDS_SHIFT))&LCDIF_DEBUG3_MST_WORDS_MASK)
25157 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK   0x1F0u
25158 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT  4
25159 #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS(x)     (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK)
25160 #define LCDIF_DEBUG3_MST_AVALID_MASK             0x200u
25161 #define LCDIF_DEBUG3_MST_AVALID_SHIFT            9
25162 #define LCDIF_DEBUG3_CUR_REQ_STATE_MASK          0xC00u
25163 #define LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT         10
25164 #define LCDIF_DEBUG3_CUR_REQ_STATE(x)            (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG3_CUR_REQ_STATE_MASK)
25165 #define LCDIF_DEBUG3_RSVD0_MASK                  0xFFFFF000u
25166 #define LCDIF_DEBUG3_RSVD0_SHIFT                 12
25167 #define LCDIF_DEBUG3_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_RSVD0_SHIFT))&LCDIF_DEBUG3_RSVD0_MASK)
25168 /* DEBUG4 Bit Fields */
25169 #define LCDIF_DEBUG4_V_DATA_COUNT_MASK           0xFFFFu
25170 #define LCDIF_DEBUG4_V_DATA_COUNT_SHIFT          0
25171 #define LCDIF_DEBUG4_V_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_V_DATA_COUNT_MASK)
25172 #define LCDIF_DEBUG4_H_DATA_COUNT_MASK           0xFFFF0000u
25173 #define LCDIF_DEBUG4_H_DATA_COUNT_SHIFT          16
25174 #define LCDIF_DEBUG4_H_DATA_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_H_DATA_COUNT_MASK)
25175 /* DEBUG5 Bit Fields */
25176 #define LCDIF_DEBUG5_MST_ADDRESS_MASK            0xFFFFFFFFu
25177 #define LCDIF_DEBUG5_MST_ADDRESS_SHIFT           0
25178 #define LCDIF_DEBUG5_MST_ADDRESS(x)              (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG5_MST_ADDRESS_SHIFT))&LCDIF_DEBUG5_MST_ADDRESS_MASK)
25179 
25180 /*!
25181  * @}
25182  */ /* end of group LCDIF_Register_Masks */
25183 
25184 /* LCDIF - Peripheral instance base addresses */
25185 /** Peripheral LCDIF1 base address */
25186 #define LCDIF1_BASE                              (0x42220000u)
25187 /** Peripheral LCDIF1 base pointer */
25188 #define LCDIF1                                   ((LCDIF_Type *)LCDIF1_BASE)
25189 #define LCDIF1_BASE_PTR                          (LCDIF1)
25190 /** Peripheral LCDIF2 base address */
25191 #define LCDIF2_BASE                              (0x42224000u)
25192 /** Peripheral LCDIF2 base pointer */
25193 #define LCDIF2                                   ((LCDIF_Type *)LCDIF2_BASE)
25194 #define LCDIF2_BASE_PTR                          (LCDIF2)
25195 /** Array initializer of LCDIF peripheral base addresses */
25196 #define LCDIF_BASE_ADDRS                         { LCDIF1_BASE, LCDIF2_BASE }
25197 /** Array initializer of LCDIF peripheral base pointers */
25198 #define LCDIF_BASE_PTRS                          { LCDIF1, LCDIF2 }
25199 /** Interrupt vectors for the LCDIF peripheral type */
25200 #define LCDIF_IRQS                               { LCDIF1_IRQn, LCDIF2_IRQn }
25201 
25202 /* ----------------------------------------------------------------------------
25203    -- LCDIF - Register accessor macros
25204    ---------------------------------------------------------------------------- */
25205 
25206 /*!
25207  * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros
25208  * @{
25209  */
25210 
25211 /* LCDIF - Register instance definitions */
25212 /* LCDIF1 */
25213 #define LCDIF1_RL                                LCDIF_RL_REG(LCDIF1_BASE_PTR)
25214 #define LCDIF1_RL_SET                            LCDIF_RL_SET_REG(LCDIF1_BASE_PTR)
25215 #define LCDIF1_RL_CLR                            LCDIF_RL_CLR_REG(LCDIF1_BASE_PTR)
25216 #define LCDIF1_RL_TOG                            LCDIF_RL_TOG_REG(LCDIF1_BASE_PTR)
25217 #define LCDIF1_CTRL1                             LCDIF_CTRL1_REG(LCDIF1_BASE_PTR)
25218 #define LCDIF1_CTRL1_SET                         LCDIF_CTRL1_SET_REG(LCDIF1_BASE_PTR)
25219 #define LCDIF1_CTRL1_CLR                         LCDIF_CTRL1_CLR_REG(LCDIF1_BASE_PTR)
25220 #define LCDIF1_CTRL1_TOG                         LCDIF_CTRL1_TOG_REG(LCDIF1_BASE_PTR)
25221 #define LCDIF1_CTRL2                             LCDIF_CTRL2_REG(LCDIF1_BASE_PTR)
25222 #define LCDIF1_CTRL2_SET                         LCDIF_CTRL2_SET_REG(LCDIF1_BASE_PTR)
25223 #define LCDIF1_CTRL2_CLR                         LCDIF_CTRL2_CLR_REG(LCDIF1_BASE_PTR)
25224 #define LCDIF1_CTRL2_TOG                         LCDIF_CTRL2_TOG_REG(LCDIF1_BASE_PTR)
25225 #define LCDIF1_TRANSFER_COUNT                    LCDIF_TRANSFER_COUNT_REG(LCDIF1_BASE_PTR)
25226 #define LCDIF1_CUR_BUF                           LCDIF_CUR_BUF_REG(LCDIF1_BASE_PTR)
25227 #define LCDIF1_NEXT_BUF                          LCDIF_NEXT_BUF_REG(LCDIF1_BASE_PTR)
25228 #define LCDIF1_TIMING                            LCDIF_TIMING_REG(LCDIF1_BASE_PTR)
25229 #define LCDIF1_VDCTRL0                           LCDIF_VDCTRL0_REG(LCDIF1_BASE_PTR)
25230 #define LCDIF1_VDCTRL0_SET                       LCDIF_VDCTRL0_SET_REG(LCDIF1_BASE_PTR)
25231 #define LCDIF1_VDCTRL0_CLR                       LCDIF_VDCTRL0_CLR_REG(LCDIF1_BASE_PTR)
25232 #define LCDIF1_VDCTRL0_TOG                       LCDIF_VDCTRL0_TOG_REG(LCDIF1_BASE_PTR)
25233 #define LCDIF1_VDCTRL1                           LCDIF_VDCTRL1_REG(LCDIF1_BASE_PTR)
25234 #define LCDIF1_VDCTRL2                           LCDIF_VDCTRL2_REG(LCDIF1_BASE_PTR)
25235 #define LCDIF1_VDCTRL3                           LCDIF_VDCTRL3_REG(LCDIF1_BASE_PTR)
25236 #define LCDIF1_VDCTRL4                           LCDIF_VDCTRL4_REG(LCDIF1_BASE_PTR)
25237 #define LCDIF1_DVICTRL0                          LCDIF_DVICTRL0_REG(LCDIF1_BASE_PTR)
25238 #define LCDIF1_DVICTRL1                          LCDIF_DVICTRL1_REG(LCDIF1_BASE_PTR)
25239 #define LCDIF1_DVICTRL2                          LCDIF_DVICTRL2_REG(LCDIF1_BASE_PTR)
25240 #define LCDIF1_DVICTRL3                          LCDIF_DVICTRL3_REG(LCDIF1_BASE_PTR)
25241 #define LCDIF1_DVICTRL4                          LCDIF_DVICTRL4_REG(LCDIF1_BASE_PTR)
25242 #define LCDIF1_CSC_COEFF0                        LCDIF_CSC_COEFF0_REG(LCDIF1_BASE_PTR)
25243 #define LCDIF1_CSC_COEFF1                        LCDIF_CSC_COEFF1_REG(LCDIF1_BASE_PTR)
25244 #define LCDIF1_CSC_COEFF2                        LCDIF_CSC_COEFF2_REG(LCDIF1_BASE_PTR)
25245 #define LCDIF1_CSC_COEFF3                        LCDIF_CSC_COEFF3_REG(LCDIF1_BASE_PTR)
25246 #define LCDIF1_CSC_COEFF4                        LCDIF_CSC_COEFF4_REG(LCDIF1_BASE_PTR)
25247 #define LCDIF1_CSC_OFFSET                        LCDIF_CSC_OFFSET_REG(LCDIF1_BASE_PTR)
25248 #define LCDIF1_CSC_LIMIT                         LCDIF_CSC_LIMIT_REG(LCDIF1_BASE_PTR)
25249 #define LCDIF1_DATA                              LCDIF_DATA_REG(LCDIF1_BASE_PTR)
25250 #define LCDIF1_BM_ERROR_STAT                     LCDIF_BM_ERROR_STAT_REG(LCDIF1_BASE_PTR)
25251 #define LCDIF1_CRC_STAT                          LCDIF_CRC_STAT_REG(LCDIF1_BASE_PTR)
25252 #define LCDIF1_STAT                              LCDIF_STAT_REG(LCDIF1_BASE_PTR)
25253 #define LCDIF1_VERSION                           LCDIF_VERSION_REG(LCDIF1_BASE_PTR)
25254 #define LCDIF1_DEBUG0                            LCDIF_DEBUG0_REG(LCDIF1_BASE_PTR)
25255 #define LCDIF1_DEBUG1                            LCDIF_DEBUG1_REG(LCDIF1_BASE_PTR)
25256 #define LCDIF1_DEBUG2                            LCDIF_DEBUG2_REG(LCDIF1_BASE_PTR)
25257 #define LCDIF1_THRES                             LCDIF_THRES_REG(LCDIF1_BASE_PTR)
25258 #define LCDIF1_AS_CTRL                           LCDIF_AS_CTRL_REG(LCDIF1_BASE_PTR)
25259 #define LCDIF1_AS_BUF                            LCDIF_AS_BUF_REG(LCDIF1_BASE_PTR)
25260 #define LCDIF1_AS_NEXT_BUF                       LCDIF_AS_NEXT_BUF_REG(LCDIF1_BASE_PTR)
25261 #define LCDIF1_AS_CLRKEYLOW                      LCDIF_AS_CLRKEYLOW_REG(LCDIF1_BASE_PTR)
25262 #define LCDIF1_AS_CLRKEYHIGH                     LCDIF_AS_CLRKEYHIGH_REG(LCDIF1_BASE_PTR)
25263 #define LCDIF1_SYNC_DELAY                        LCDIF_SYNC_DELAY_REG(LCDIF1_BASE_PTR)
25264 #define LCDIF1_DEBUG3                            LCDIF_DEBUG3_REG(LCDIF1_BASE_PTR)
25265 #define LCDIF1_DEBUG4                            LCDIF_DEBUG4_REG(LCDIF1_BASE_PTR)
25266 #define LCDIF1_DEBUG5                            LCDIF_DEBUG5_REG(LCDIF1_BASE_PTR)
25267 /* LCDIF2 */
25268 #define LCDIF2_RL                                LCDIF_RL_REG(LCDIF2_BASE_PTR)
25269 #define LCDIF2_RL_SET                            LCDIF_RL_SET_REG(LCDIF2_BASE_PTR)
25270 #define LCDIF2_RL_CLR                            LCDIF_RL_CLR_REG(LCDIF2_BASE_PTR)
25271 #define LCDIF2_RL_TOG                            LCDIF_RL_TOG_REG(LCDIF2_BASE_PTR)
25272 #define LCDIF2_CTRL1                             LCDIF_CTRL1_REG(LCDIF2_BASE_PTR)
25273 #define LCDIF2_CTRL1_SET                         LCDIF_CTRL1_SET_REG(LCDIF2_BASE_PTR)
25274 #define LCDIF2_CTRL1_CLR                         LCDIF_CTRL1_CLR_REG(LCDIF2_BASE_PTR)
25275 #define LCDIF2_CTRL1_TOG                         LCDIF_CTRL1_TOG_REG(LCDIF2_BASE_PTR)
25276 #define LCDIF2_CTRL2                             LCDIF_CTRL2_REG(LCDIF2_BASE_PTR)
25277 #define LCDIF2_CTRL2_SET                         LCDIF_CTRL2_SET_REG(LCDIF2_BASE_PTR)
25278 #define LCDIF2_CTRL2_CLR                         LCDIF_CTRL2_CLR_REG(LCDIF2_BASE_PTR)
25279 #define LCDIF2_CTRL2_TOG                         LCDIF_CTRL2_TOG_REG(LCDIF2_BASE_PTR)
25280 #define LCDIF2_TRANSFER_COUNT                    LCDIF_TRANSFER_COUNT_REG(LCDIF2_BASE_PTR)
25281 #define LCDIF2_CUR_BUF                           LCDIF_CUR_BUF_REG(LCDIF2_BASE_PTR)
25282 #define LCDIF2_NEXT_BUF                          LCDIF_NEXT_BUF_REG(LCDIF2_BASE_PTR)
25283 #define LCDIF2_TIMING                            LCDIF_TIMING_REG(LCDIF2_BASE_PTR)
25284 #define LCDIF2_VDCTRL0                           LCDIF_VDCTRL0_REG(LCDIF2_BASE_PTR)
25285 #define LCDIF2_VDCTRL0_SET                       LCDIF_VDCTRL0_SET_REG(LCDIF2_BASE_PTR)
25286 #define LCDIF2_VDCTRL0_CLR                       LCDIF_VDCTRL0_CLR_REG(LCDIF2_BASE_PTR)
25287 #define LCDIF2_VDCTRL0_TOG                       LCDIF_VDCTRL0_TOG_REG(LCDIF2_BASE_PTR)
25288 #define LCDIF2_VDCTRL1                           LCDIF_VDCTRL1_REG(LCDIF2_BASE_PTR)
25289 #define LCDIF2_VDCTRL2                           LCDIF_VDCTRL2_REG(LCDIF2_BASE_PTR)
25290 #define LCDIF2_VDCTRL3                           LCDIF_VDCTRL3_REG(LCDIF2_BASE_PTR)
25291 #define LCDIF2_VDCTRL4                           LCDIF_VDCTRL4_REG(LCDIF2_BASE_PTR)
25292 #define LCDIF2_DVICTRL0                          LCDIF_DVICTRL0_REG(LCDIF2_BASE_PTR)
25293 #define LCDIF2_DVICTRL1                          LCDIF_DVICTRL1_REG(LCDIF2_BASE_PTR)
25294 #define LCDIF2_DVICTRL2                          LCDIF_DVICTRL2_REG(LCDIF2_BASE_PTR)
25295 #define LCDIF2_DVICTRL3                          LCDIF_DVICTRL3_REG(LCDIF2_BASE_PTR)
25296 #define LCDIF2_DVICTRL4                          LCDIF_DVICTRL4_REG(LCDIF2_BASE_PTR)
25297 #define LCDIF2_CSC_COEFF0                        LCDIF_CSC_COEFF0_REG(LCDIF2_BASE_PTR)
25298 #define LCDIF2_CSC_COEFF1                        LCDIF_CSC_COEFF1_REG(LCDIF2_BASE_PTR)
25299 #define LCDIF2_CSC_COEFF2                        LCDIF_CSC_COEFF2_REG(LCDIF2_BASE_PTR)
25300 #define LCDIF2_CSC_COEFF3                        LCDIF_CSC_COEFF3_REG(LCDIF2_BASE_PTR)
25301 #define LCDIF2_CSC_COEFF4                        LCDIF_CSC_COEFF4_REG(LCDIF2_BASE_PTR)
25302 #define LCDIF2_CSC_OFFSET                        LCDIF_CSC_OFFSET_REG(LCDIF2_BASE_PTR)
25303 #define LCDIF2_CSC_LIMIT                         LCDIF_CSC_LIMIT_REG(LCDIF2_BASE_PTR)
25304 #define LCDIF2_DATA                              LCDIF_DATA_REG(LCDIF2_BASE_PTR)
25305 #define LCDIF2_BM_ERROR_STAT                     LCDIF_BM_ERROR_STAT_REG(LCDIF2_BASE_PTR)
25306 #define LCDIF2_CRC_STAT                          LCDIF_CRC_STAT_REG(LCDIF2_BASE_PTR)
25307 #define LCDIF2_STAT                              LCDIF_STAT_REG(LCDIF2_BASE_PTR)
25308 #define LCDIF2_VERSION                           LCDIF_VERSION_REG(LCDIF2_BASE_PTR)
25309 #define LCDIF2_DEBUG0                            LCDIF_DEBUG0_REG(LCDIF2_BASE_PTR)
25310 #define LCDIF2_DEBUG1                            LCDIF_DEBUG1_REG(LCDIF2_BASE_PTR)
25311 #define LCDIF2_DEBUG2                            LCDIF_DEBUG2_REG(LCDIF2_BASE_PTR)
25312 #define LCDIF2_THRES                             LCDIF_THRES_REG(LCDIF2_BASE_PTR)
25313 #define LCDIF2_AS_CTRL                           LCDIF_AS_CTRL_REG(LCDIF2_BASE_PTR)
25314 #define LCDIF2_AS_BUF                            LCDIF_AS_BUF_REG(LCDIF2_BASE_PTR)
25315 #define LCDIF2_AS_NEXT_BUF                       LCDIF_AS_NEXT_BUF_REG(LCDIF2_BASE_PTR)
25316 #define LCDIF2_AS_CLRKEYLOW                      LCDIF_AS_CLRKEYLOW_REG(LCDIF2_BASE_PTR)
25317 #define LCDIF2_AS_CLRKEYHIGH                     LCDIF_AS_CLRKEYHIGH_REG(LCDIF2_BASE_PTR)
25318 #define LCDIF2_SYNC_DELAY                        LCDIF_SYNC_DELAY_REG(LCDIF2_BASE_PTR)
25319 #define LCDIF2_DEBUG3                            LCDIF_DEBUG3_REG(LCDIF2_BASE_PTR)
25320 #define LCDIF2_DEBUG4                            LCDIF_DEBUG4_REG(LCDIF2_BASE_PTR)
25321 #define LCDIF2_DEBUG5                            LCDIF_DEBUG5_REG(LCDIF2_BASE_PTR)
25322 
25323 /*!
25324  * @}
25325  */ /* end of group LCDIF_Register_Accessor_Macros */
25326 
25327 /*!
25328  * @}
25329  */ /* end of group LCDIF_Peripheral */
25330 
25331 /* ----------------------------------------------------------------------------
25332    -- LDB Peripheral Access Layer
25333    ---------------------------------------------------------------------------- */
25334 
25335 /*!
25336  * @addtogroup LDB_Peripheral_Access_Layer LDB Peripheral Access Layer
25337  * @{
25338  */
25339 
25340 /** LDB - Register Layout Typedef */
25341 typedef struct {
25342   __IO  uint32_t CTRL;                                   /**< LDB Control Register, offset: 0x0 */
25343 } LDB_Type, *LDB_MemMapPtr;
25344 
25345 /* ----------------------------------------------------------------------------
25346    -- LDB - Register accessor macros
25347    ---------------------------------------------------------------------------- */
25348 
25349 /*!
25350  * @addtogroup LDB_Register_Accessor_Macros LDB - Register accessor macros
25351  * @{
25352  */
25353 
25354 /* LDB - Register accessors */
25355 #define LDB_CTRL_REG(base)                       ((base)->CTRL)
25356 
25357 /*!
25358  * @}
25359  */ /* end of group LDB_Register_Accessor_Macros */
25360 
25361 /* ----------------------------------------------------------------------------
25362    -- LDB Register Masks
25363    ---------------------------------------------------------------------------- */
25364 
25365 /*!
25366  * @addtogroup LDB_Register_Masks LDB Register Masks
25367  * @{
25368  */
25369 
25370 /* CTRL Bit Fields */
25371 #define LDB_CTRL_ch0_mode_MASK                   0x3u
25372 #define LDB_CTRL_ch0_mode_SHIFT                  0
25373 #define LDB_CTRL_ch0_mode(x)                     (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_ch0_mode_SHIFT))&LDB_CTRL_ch0_mode_MASK)
25374 #define LDB_CTRL_data_width_ch0_MASK             0x20u
25375 #define LDB_CTRL_data_width_ch0_SHIFT            5
25376 #define LDB_CTRL_bit_mapping_ch0_MASK            0x40u
25377 #define LDB_CTRL_bit_mapping_ch0_SHIFT           6
25378 #define LDB_CTRL_lcdif1_vs_polarity_MASK         0x200u
25379 #define LDB_CTRL_lcdif1_vs_polarity_SHIFT        9
25380 #define LDB_CTRL_lvds_clk_shift_MASK             0x70000u
25381 #define LDB_CTRL_lvds_clk_shift_SHIFT            16
25382 #define LDB_CTRL_lvds_clk_shift(x)               (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_lvds_clk_shift_SHIFT))&LDB_CTRL_lvds_clk_shift_MASK)
25383 #define LDB_CTRL_counter_reset_val_MASK          0x300000u
25384 #define LDB_CTRL_counter_reset_val_SHIFT         20
25385 #define LDB_CTRL_counter_reset_val(x)            (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_counter_reset_val_SHIFT))&LDB_CTRL_counter_reset_val_MASK)
25386 
25387 /*!
25388  * @}
25389  */ /* end of group LDB_Register_Masks */
25390 
25391 /* LDB - Peripheral instance base addresses */
25392 /** Peripheral LDB base address */
25393 #define LDB_BASE                                 (0x420E0014u)
25394 /** Peripheral LDB base pointer */
25395 #define LDB                                      ((LDB_Type *)LDB_BASE)
25396 #define LDB_BASE_PTR                             (LDB)
25397 /** Array initializer of LDB peripheral base addresses */
25398 #define LDB_BASE_ADDRS                           { LDB_BASE }
25399 /** Array initializer of LDB peripheral base pointers */
25400 #define LDB_BASE_PTRS                            { LDB }
25401 
25402 /* ----------------------------------------------------------------------------
25403    -- LDB - Register accessor macros
25404    ---------------------------------------------------------------------------- */
25405 
25406 /*!
25407  * @addtogroup LDB_Register_Accessor_Macros LDB - Register accessor macros
25408  * @{
25409  */
25410 
25411 /* LDB - Register instance definitions */
25412 /* LDB */
25413 #define LDB_CTRL                                 LDB_CTRL_REG(LDB_BASE_PTR)
25414 
25415 /*!
25416  * @}
25417  */ /* end of group LDB_Register_Accessor_Macros */
25418 
25419 /*!
25420  * @}
25421  */ /* end of group LDB_Peripheral */
25422 
25423 /* ----------------------------------------------------------------------------
25424    -- LMEM Peripheral Access Layer
25425    ---------------------------------------------------------------------------- */
25426 
25427 /*!
25428  * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
25429  * @{
25430  */
25431 
25432 /** LMEM - Register Layout Typedef */
25433 typedef struct {
25434   __IO  uint32_t PCCCR;                                  /**< Cache control register, offset: 0x0 */
25435   __IO  uint32_t PCCLCR;                                 /**< Cache line control register, offset: 0x4 */
25436   __IO  uint32_t PCCSAR;                                 /**< Cache search address register, offset: 0x8 */
25437   __IO  uint32_t PCCCVR;                                 /**< Cache read/write value register, offset: 0xC */
25438   uint8_t RESERVED_0[2032];
25439   __IO  uint32_t PSCCR;                                  /**< Cache control register, offset: 0x800 */
25440   __IO  uint32_t PSCLCR;                                 /**< Cache line control register, offset: 0x804 */
25441   __IO  uint32_t PSCSAR;                                 /**< Cache search address register, offset: 0x808 */
25442   __IO  uint32_t PSCCVR;                                 /**< Cache read/write value register, offset: 0x80C */
25443 } LMEM_Type, *LMEM_MemMapPtr;
25444 
25445 /* ----------------------------------------------------------------------------
25446    -- LMEM - Register accessor macros
25447    ---------------------------------------------------------------------------- */
25448 
25449 /*!
25450  * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros
25451  * @{
25452  */
25453 
25454 /* LMEM - Register accessors */
25455 #define LMEM_PCCCR_REG(base)                     ((base)->PCCCR)
25456 #define LMEM_PCCLCR_REG(base)                    ((base)->PCCLCR)
25457 #define LMEM_PCCSAR_REG(base)                    ((base)->PCCSAR)
25458 #define LMEM_PCCCVR_REG(base)                    ((base)->PCCCVR)
25459 #define LMEM_PSCCR_REG(base)                     ((base)->PSCCR)
25460 #define LMEM_PSCLCR_REG(base)                    ((base)->PSCLCR)
25461 #define LMEM_PSCSAR_REG(base)                    ((base)->PSCSAR)
25462 #define LMEM_PSCCVR_REG(base)                    ((base)->PSCCVR)
25463 
25464 /*!
25465  * @}
25466  */ /* end of group LMEM_Register_Accessor_Macros */
25467 /* ----------------------------------------------------------------------------
25468    -- LMEM Register Masks
25469    ---------------------------------------------------------------------------- */
25470 
25471 /*!
25472  * @addtogroup LMEM_Register_Masks LMEM Register Masks
25473  * @{
25474  */
25475 
25476 /* PCCCR Bit Fields */
25477 #define LMEM_PCCCR_ENCACHE_MASK                  0x1u
25478 #define LMEM_PCCCR_ENCACHE_SHIFT                 0
25479 #define LMEM_PCCCR_ENWRBUF_MASK                  0x2u
25480 #define LMEM_PCCCR_ENWRBUF_SHIFT                 1
25481 #define LMEM_PCCCR_PCCR2_MASK                    0x4u
25482 #define LMEM_PCCCR_PCCR2_SHIFT                   2
25483 #define LMEM_PCCCR_PCCR3_MASK                    0x8u
25484 #define LMEM_PCCCR_PCCR3_SHIFT                   3
25485 #define LMEM_PCCCR_INVW0_MASK                    0x1000000u
25486 #define LMEM_PCCCR_INVW0_SHIFT                   24
25487 #define LMEM_PCCCR_PUSHW0_MASK                   0x2000000u
25488 #define LMEM_PCCCR_PUSHW0_SHIFT                  25
25489 #define LMEM_PCCCR_INVW1_MASK                    0x4000000u
25490 #define LMEM_PCCCR_INVW1_SHIFT                   26
25491 #define LMEM_PCCCR_PUSHW1_MASK                   0x8000000u
25492 #define LMEM_PCCCR_PUSHW1_SHIFT                  27
25493 #define LMEM_PCCCR_GO_MASK                       0x80000000u
25494 #define LMEM_PCCCR_GO_SHIFT                      31
25495 /* PCCLCR Bit Fields */
25496 #define LMEM_PCCLCR_LGO_MASK                     0x1u
25497 #define LMEM_PCCLCR_LGO_SHIFT                    0
25498 #define LMEM_PCCLCR_CACHEADDR_MASK               0x1FFCu
25499 #define LMEM_PCCLCR_CACHEADDR_SHIFT              2
25500 #define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
25501 #define LMEM_PCCLCR_WSEL_MASK                    0x4000u
25502 #define LMEM_PCCLCR_WSEL_SHIFT                   14
25503 #define LMEM_PCCLCR_TDSEL_MASK                   0x10000u
25504 #define LMEM_PCCLCR_TDSEL_SHIFT                  16
25505 #define LMEM_PCCLCR_LCIVB_MASK                   0x100000u
25506 #define LMEM_PCCLCR_LCIVB_SHIFT                  20
25507 #define LMEM_PCCLCR_LCIMB_MASK                   0x200000u
25508 #define LMEM_PCCLCR_LCIMB_SHIFT                  21
25509 #define LMEM_PCCLCR_LCWAY_MASK                   0x400000u
25510 #define LMEM_PCCLCR_LCWAY_SHIFT                  22
25511 #define LMEM_PCCLCR_LCMD_MASK                    0x3000000u
25512 #define LMEM_PCCLCR_LCMD_SHIFT                   24
25513 #define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
25514 #define LMEM_PCCLCR_LADSEL_MASK                  0x4000000u
25515 #define LMEM_PCCLCR_LADSEL_SHIFT                 26
25516 #define LMEM_PCCLCR_LACC_MASK                    0x8000000u
25517 #define LMEM_PCCLCR_LACC_SHIFT                   27
25518 /* PCCSAR Bit Fields */
25519 #define LMEM_PCCSAR_LGO_MASK                     0x1u
25520 #define LMEM_PCCSAR_LGO_SHIFT                    0
25521 #define LMEM_PCCSAR_PHYADDR_MASK                 0xFFFFFFFCu
25522 #define LMEM_PCCSAR_PHYADDR_SHIFT                2
25523 #define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
25524 /* PCCCVR Bit Fields */
25525 #define LMEM_PCCCVR_DATA_MASK                    0xFFFFFFFFu
25526 #define LMEM_PCCCVR_DATA_SHIFT                   0
25527 #define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
25528 /* PSCCR Bit Fields */
25529 #define LMEM_PSCCR_ENCACHE_MASK                  0x1u
25530 #define LMEM_PSCCR_ENCACHE_SHIFT                 0
25531 #define LMEM_PSCCR_ENWRBUF_MASK                  0x2u
25532 #define LMEM_PSCCR_ENWRBUF_SHIFT                 1
25533 #define LMEM_PSCCR_INVW0_MASK                    0x1000000u
25534 #define LMEM_PSCCR_INVW0_SHIFT                   24
25535 #define LMEM_PSCCR_PUSHW0_MASK                   0x2000000u
25536 #define LMEM_PSCCR_PUSHW0_SHIFT                  25
25537 #define LMEM_PSCCR_INVW1_MASK                    0x4000000u
25538 #define LMEM_PSCCR_INVW1_SHIFT                   26
25539 #define LMEM_PSCCR_PUSHW1_MASK                   0x8000000u
25540 #define LMEM_PSCCR_PUSHW1_SHIFT                  27
25541 #define LMEM_PSCCR_GO_MASK                       0x80000000u
25542 #define LMEM_PSCCR_GO_SHIFT                      31
25543 /* PSCLCR Bit Fields */
25544 #define LMEM_PSCLCR_LGO_MASK                     0x1u
25545 #define LMEM_PSCLCR_LGO_SHIFT                    0
25546 #define LMEM_PSCLCR_CACHEADDR_MASK               0x1FFCu
25547 #define LMEM_PSCLCR_CACHEADDR_SHIFT              2
25548 #define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK)
25549 #define LMEM_PSCLCR_WSEL_MASK                    0x4000u
25550 #define LMEM_PSCLCR_WSEL_SHIFT                   14
25551 #define LMEM_PSCLCR_TDSEL_MASK                   0x10000u
25552 #define LMEM_PSCLCR_TDSEL_SHIFT                  16
25553 #define LMEM_PSCLCR_LCIVB_MASK                   0x100000u
25554 #define LMEM_PSCLCR_LCIVB_SHIFT                  20
25555 #define LMEM_PSCLCR_LCIMB_MASK                   0x200000u
25556 #define LMEM_PSCLCR_LCIMB_SHIFT                  21
25557 #define LMEM_PSCLCR_LCWAY_MASK                   0x400000u
25558 #define LMEM_PSCLCR_LCWAY_SHIFT                  22
25559 #define LMEM_PSCLCR_LCMD_MASK                    0x3000000u
25560 #define LMEM_PSCLCR_LCMD_SHIFT                   24
25561 #define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK)
25562 #define LMEM_PSCLCR_LADSEL_MASK                  0x4000000u
25563 #define LMEM_PSCLCR_LADSEL_SHIFT                 26
25564 #define LMEM_PSCLCR_LACC_MASK                    0x8000000u
25565 #define LMEM_PSCLCR_LACC_SHIFT                   27
25566 /* PSCSAR Bit Fields */
25567 #define LMEM_PSCSAR_LGO_MASK                     0x1u
25568 #define LMEM_PSCSAR_LGO_SHIFT                    0
25569 #define LMEM_PSCSAR_PHYADDR_MASK                 0xFFFFFFFCu
25570 #define LMEM_PSCSAR_PHYADDR_SHIFT                2
25571 #define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK)
25572 /* PSCCVR Bit Fields */
25573 #define LMEM_PSCCVR_DATA_MASK                    0xFFFFFFFFu
25574 #define LMEM_PSCCVR_DATA_SHIFT                   0
25575 #define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK)
25576 
25577 /*!
25578  * @}
25579  */ /* end of group LMEM_Register_Masks */
25580 
25581 /* LMEM - Peripheral instance base addresses */
25582 /** Peripheral LMEM base address */
25583 #define LMEM_BASE                                (0xE0082000u)
25584 /** Peripheral LMEM base pointer */
25585 #define LMEM                                     ((LMEM_Type *)LMEM_BASE)
25586 #define LMEM_BASE_PTR                            (LMEM)
25587 /** Array initializer of LMEM peripheral base addresses */
25588 #define LMEM_BASE_ADDRS                          { LMEM_BASE }
25589 /** Array initializer of LMEM peripheral base pointers */
25590 #define LMEM_BASE_PTRS                           { LMEM }
25591 
25592 /* ----------------------------------------------------------------------------
25593    -- LMEM - Register accessor macros
25594    ---------------------------------------------------------------------------- */
25595 
25596 /*!
25597  * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros
25598  * @{
25599  */
25600 
25601 /* LMEM - Register instance definitions */
25602 /* LMEM */
25603 #define LMEM_PCCCR                               LMEM_PCCCR_REG(LMEM_BASE_PTR)
25604 #define LMEM_PCCLCR                              LMEM_PCCLCR_REG(LMEM_BASE_PTR)
25605 #define LMEM_PCCSAR                              LMEM_PCCSAR_REG(LMEM_BASE_PTR)
25606 #define LMEM_PCCCVR                              LMEM_PCCCVR_REG(LMEM_BASE_PTR)
25607 #define LMEM_PSCCR                               LMEM_PSCCR_REG(LMEM_BASE_PTR)
25608 #define LMEM_PSCLCR                              LMEM_PSCLCR_REG(LMEM_BASE_PTR)
25609 #define LMEM_PSCSAR                              LMEM_PSCSAR_REG(LMEM_BASE_PTR)
25610 #define LMEM_PSCCVR                              LMEM_PSCCVR_REG(LMEM_BASE_PTR)
25611 
25612 /*!
25613  * @}
25614  */ /* end of group LMEM_Register_Accessor_Macros */
25615 
25616 /*!
25617  * @}
25618  */ /* end of group LMEM_Peripheral */
25619 
25620 /* ----------------------------------------------------------------------------
25621    -- MCM Peripheral Access Layer
25622    ---------------------------------------------------------------------------- */
25623 
25624 /*!
25625  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
25626  * @{
25627  */
25628 
25629 /** MCM - Register Layout Typedef */
25630 typedef struct {
25631   uint8_t RESERVED_0[8];
25632   __I   uint16_t PLASC;                                  /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
25633   __I   uint16_t PLAMC;                                  /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
25634   uint8_t RESERVED_1[20];
25635   __I   uint32_t FADR;                                   /**< Fault address register, offset: 0x20 */
25636   __I   uint32_t FATR;                                   /**< Fault attributes register, offset: 0x24 */
25637   __I   uint32_t FDR;                                    /**< Fault data register, offset: 0x28 */
25638 } MCM_Type, *MCM_MemMapPtr;
25639 
25640 /* ----------------------------------------------------------------------------
25641    -- MCM - Register accessor macros
25642    ---------------------------------------------------------------------------- */
25643 
25644 /*!
25645  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
25646  * @{
25647  */
25648 
25649 /* MCM - Register accessors */
25650 #define MCM_PLASC_REG(base)                      ((base)->PLASC)
25651 #define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
25652 #define MCM_FADR_REG(base)                       ((base)->FADR)
25653 #define MCM_FATR_REG(base)                       ((base)->FATR)
25654 #define MCM_FDR_REG(base)                        ((base)->FDR)
25655 
25656 /*!
25657  * @}
25658  */ /* end of group MCM_Register_Accessor_Macros */
25659 
25660 /* ----------------------------------------------------------------------------
25661    -- MCM Register Masks
25662    ---------------------------------------------------------------------------- */
25663 
25664 /*!
25665  * @addtogroup MCM_Register_Masks MCM Register Masks
25666  * @{
25667  */
25668 
25669 /* PLASC Bit Fields */
25670 #define MCM_PLASC_ASC_MASK                       0xFFu
25671 #define MCM_PLASC_ASC_SHIFT                      0
25672 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
25673 /* PLAMC Bit Fields */
25674 #define MCM_PLAMC_AMC_MASK                       0xFFu
25675 #define MCM_PLAMC_AMC_SHIFT                      0
25676 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
25677 /* FADR Bit Fields */
25678 #define MCM_FADR_ADDRESS_MASK                    0xFFFFFFFFu
25679 #define MCM_FADR_ADDRESS_SHIFT                   0
25680 #define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_FADR_ADDRESS_SHIFT))&MCM_FADR_ADDRESS_MASK)
25681 /* FATR Bit Fields */
25682 #define MCM_FATR_BEDA_MASK                       0x1u
25683 #define MCM_FATR_BEDA_SHIFT                      0
25684 #define MCM_FATR_BEMD_MASK                       0x2u
25685 #define MCM_FATR_BEMD_SHIFT                      1
25686 #define MCM_FATR_BESZ_MASK                       0x30u
25687 #define MCM_FATR_BESZ_SHIFT                      4
25688 #define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK)
25689 #define MCM_FATR_BEWT_MASK                       0x80u
25690 #define MCM_FATR_BEWT_SHIFT                      7
25691 #define MCM_FATR_BEMN_MASK                       0xF00u
25692 #define MCM_FATR_BEMN_SHIFT                      8
25693 #define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK)
25694 #define MCM_FATR_BEOVR_MASK                      0x80000000u
25695 #define MCM_FATR_BEOVR_SHIFT                     31
25696 /* FDR Bit Fields */
25697 #define MCM_FDR_DATA_MASK                        0xFFFFFFFFu
25698 #define MCM_FDR_DATA_SHIFT                       0
25699 #define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK)
25700 
25701 /*!
25702  * @}
25703  */ /* end of group MCM_Register_Masks */
25704 
25705 /* MCM - Peripheral instance base addresses */
25706 /** Peripheral MCM base address */
25707 #define MCM_BASE                                 (0xE0000000u)
25708 /** Peripheral MCM base pointer */
25709 #define MCM                                      ((MCM_Type *)MCM_BASE)
25710 #define MCM_BASE_PTR                             (MCM)
25711 /** Array initializer of MCM peripheral base addresses */
25712 #define MCM_BASE_ADDRS                           { MCM_BASE }
25713 /** Array initializer of MCM peripheral base pointers */
25714 #define MCM_BASE_PTRS                            { MCM }
25715 
25716 /* ----------------------------------------------------------------------------
25717    -- MCM - Register accessor macros
25718    ---------------------------------------------------------------------------- */
25719 
25720 /*!
25721  * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
25722  * @{
25723  */
25724 
25725 /* MCM - Register instance definitions */
25726 /* MCM */
25727 #define MCM_PLASC                                MCM_PLASC_REG(MCM_BASE_PTR)
25728 #define MCM_PLAMC                                MCM_PLAMC_REG(MCM_BASE_PTR)
25729 #define MCM_FADR                                 MCM_FADR_REG(MCM_BASE_PTR)
25730 #define MCM_FATR                                 MCM_FATR_REG(MCM_BASE_PTR)
25731 #define MCM_FDR                                  MCM_FDR_REG(MCM_BASE_PTR)
25732 
25733 /*!
25734  * @}
25735  */ /* end of group MCM_Register_Accessor_Macros */
25736 
25737 /*!
25738  * @}
25739  */ /* end of group MCM_Peripheral */
25740 
25741 /* ----------------------------------------------------------------------------
25742    -- MLB Peripheral Access Layer
25743    ---------------------------------------------------------------------------- */
25744 
25745 /*!
25746  * @addtogroup MLB_Peripheral_Access_Layer MLB Peripheral Access Layer
25747  * @{
25748  */
25749 
25750 /** MLB - Register Layout Typedef */
25751 typedef struct {
25752   __IO  uint32_t MLBC0;                                  /**< MediaLB Control 0 Register, offset: 0x0 */
25753   uint8_t RESERVED_0[8];
25754   union {                                          /* offset: 0xC */
25755   __I     uint32_t MS0;                                         /**< MediaLB Channel Status 0 Register,offset: 0xC */
25756   struct {                                         /* offset: 0xD */
25757       uint8_t RESERVED_0[1];
25758   __I     uint32_t MLBPC2;                                      /**< MediaLB 6-pin Control 2 Register,offset: 0xD */
25759     } MLBPC2;
25760   };
25761   uint8_t RESERVED_1[3];
25762   __I   uint32_t MS1;                                    /**< MediaLB Channel Status1 Register, offset: 0x14 */
25763   uint8_t RESERVED_2[8];
25764   __I   uint32_t MSS;                                    /**< MediaLB System Status Register, offset: 0x20 */
25765   __I   uint32_t MSD;                                    /**< MediaLB System Data Register, offset: 0x24 */
25766   uint8_t RESERVED_3[4];
25767   __IO  uint32_t MIEN;                                   /**< MediaLB Interrupt Enable Register, offset: 0x2C */
25768   uint8_t RESERVED_4[12];
25769   __I   uint32_t MLBC1;                                  /**< MediaLB Control 1 Register, offset: 0x3C */
25770   uint8_t RESERVED_5[64];
25771   __IO  uint32_t HCTL;                                   /**< HBI Control Register, offset: 0x80 */
25772   uint8_t RESERVED_6[4];
25773   __IO  uint32_t HCMR0;                                  /**< HBI Channel Mask 0 Register, offset: 0x88 */
25774   __IO  uint32_t HCMR1;                                  /**< HBI Channel Mask 1 Register, offset: 0x8C */
25775   __I   uint32_t HCER0;                                  /**< HBI Channel Error 0 Register, offset: 0x90 */
25776   __I   uint32_t HCER1;                                  /**< HBI Channel Error 1 Register, offset: 0x94 */
25777   __I   uint32_t HCBR0;                                  /**< HBI Channel Busy 0 Register, offset: 0x98 */
25778   __I   uint32_t HCBR1;                                  /**< HBI Channel Busy 1 Register, offset: 0x9C */
25779   uint8_t RESERVED_7[32];
25780   __IO  uint32_t MDAT0;                                  /**< MIF Data 0 Register, offset: 0xC0 */
25781   __IO  uint32_t MDAT1;                                  /**< MIF Data 1 Register, offset: 0xC4 */
25782   __IO  uint32_t MDAT2;                                  /**< MIF Data 2 Register, offset: 0xC8 */
25783   __IO  uint32_t MDAT3;                                  /**< MIF Data 3 Register, offset: 0xCC */
25784   __IO  uint32_t MDWE0;                                  /**< MIF Data Write Enable 0 Register, offset: 0xD0 */
25785   __IO  uint32_t MDWE1;                                  /**< MIF Data Write Enable 1 Register, offset: 0xD4 */
25786   __IO  uint32_t MDWE2;                                  /**< MIF Data Write Enable 2 Register, offset: 0xD8 */
25787   __IO  uint32_t MDWE3;                                  /**< MIF Data Write Enable 3 Register, offset: 0xDC */
25788   __I   uint32_t MCTL;                                   /**< MIF Control Register, offset: 0xE0 */
25789   __IO  uint32_t MADR;                                   /**< MIF Address Register, offset: 0xE4 */
25790   uint8_t RESERVED_8[728];
25791   __IO  uint32_t ACTL;                                   /**< AHB Control Register, offset: 0x3C0 */
25792   uint8_t RESERVED_9[12];
25793   __I   uint32_t ACSR0;                                  /**< AHB Channel Status 0 Register, offset: 0x3D0 */
25794   __I   uint32_t ACSR1;                                  /**< AHB Channel Status 1 Register, offset: 0x3D4 */
25795   __IO  uint32_t ACMR0;                                  /**< AHB Channel Mask 0 Register, offset: 0x3D8 */
25796   __IO  uint32_t ACMR1;                                  /**< AHB Channel Mask 1 Register, offset: 0x3DC */
25797 } MLB_Type, *MLB_MemMapPtr;
25798 
25799 /* ----------------------------------------------------------------------------
25800    -- MLB - Register accessor macros
25801    ---------------------------------------------------------------------------- */
25802 
25803 /*!
25804  * @addtogroup MLB_Register_Accessor_Macros MLB - Register accessor macros
25805  * @{
25806  */
25807 
25808 /* MLB - Register accessors */
25809 #define MLB_MLBC0_REG(base)                      ((base)->MLBC0)
25810 #define MLB_MS0_REG(base)                        ((base)->MS0)
25811 #define MLB_MLBPC2_REG(base)                     ((base)->MLBPC2.MLBPC2)
25812 #define MLB_MS1_REG(base)                        ((base)->MS1)
25813 #define MLB_MSS_REG(base)                        ((base)->MSS)
25814 #define MLB_MSD_REG(base)                        ((base)->MSD)
25815 #define MLB_MIEN_REG(base)                       ((base)->MIEN)
25816 #define MLB_MLBC1_REG(base)                      ((base)->MLBC1)
25817 #define MLB_HCTL_REG(base)                       ((base)->HCTL)
25818 #define MLB_HCMR0_REG(base)                      ((base)->HCMR0)
25819 #define MLB_HCMR1_REG(base)                      ((base)->HCMR1)
25820 #define MLB_HCER0_REG(base)                      ((base)->HCER0)
25821 #define MLB_HCER1_REG(base)                      ((base)->HCER1)
25822 #define MLB_HCBR0_REG(base)                      ((base)->HCBR0)
25823 #define MLB_HCBR1_REG(base)                      ((base)->HCBR1)
25824 #define MLB_MDAT0_REG(base)                      ((base)->MDAT0)
25825 #define MLB_MDAT1_REG(base)                      ((base)->MDAT1)
25826 #define MLB_MDAT2_REG(base)                      ((base)->MDAT2)
25827 #define MLB_MDAT3_REG(base)                      ((base)->MDAT3)
25828 #define MLB_MDWE0_REG(base)                      ((base)->MDWE0)
25829 #define MLB_MDWE1_REG(base)                      ((base)->MDWE1)
25830 #define MLB_MDWE2_REG(base)                      ((base)->MDWE2)
25831 #define MLB_MDWE3_REG(base)                      ((base)->MDWE3)
25832 #define MLB_MCTL_REG(base)                       ((base)->MCTL)
25833 #define MLB_MADR_REG(base)                       ((base)->MADR)
25834 #define MLB_ACTL_REG(base)                       ((base)->ACTL)
25835 #define MLB_ACSR0_REG(base)                      ((base)->ACSR0)
25836 #define MLB_ACSR1_REG(base)                      ((base)->ACSR1)
25837 #define MLB_ACMR0_REG(base)                      ((base)->ACMR0)
25838 #define MLB_ACMR1_REG(base)                      ((base)->ACMR1)
25839 
25840 /*!
25841  * @}
25842  */ /* end of group MLB_Register_Accessor_Macros */
25843 
25844 /* ----------------------------------------------------------------------------
25845    -- MLB Register Masks
25846    ---------------------------------------------------------------------------- */
25847 
25848 /*!
25849  * @addtogroup MLB_Register_Masks MLB Register Masks
25850  * @{
25851  */
25852 
25853 /* MLBC0 Bit Fields */
25854 #define MLB_MLBC0_MLBEN_MASK                     0x1u
25855 #define MLB_MLBC0_MLBEN_SHIFT                    0
25856 #define MLB_MLBC0_MLBCLK_2_0_MASK                0x1Cu
25857 #define MLB_MLBC0_MLBCLK_2_0_SHIFT               2
25858 #define MLB_MLBC0_MLBCLK_2_0(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_MLBC0_MLBCLK_2_0_SHIFT))&MLB_MLBC0_MLBCLK_2_0_MASK)
25859 #define MLB_MLBC0_MLBLK_MASK                     0x80u
25860 #define MLB_MLBC0_MLBLK_SHIFT                    7
25861 #define MLB_MLBC0_ASYRETRY_MASK                  0x1000u
25862 #define MLB_MLBC0_ASYRETRY_SHIFT                 12
25863 #define MLB_MLBC0_CTLRETRY_MASK                  0x4000u
25864 #define MLB_MLBC0_CTLRETRY_SHIFT                 14
25865 #define MLB_MLBC0_FCNT_MASK                      0x38000u
25866 #define MLB_MLBC0_FCNT_SHIFT                     15
25867 #define MLB_MLBC0_FCNT(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_MLBC0_FCNT_SHIFT))&MLB_MLBC0_FCNT_MASK)
25868 /* MS0 Bit Fields */
25869 #define MLB_MS0_MCS_31_0_MASK                    0xFFFFFFFFu
25870 #define MLB_MS0_MCS_31_0_SHIFT                   0
25871 #define MLB_MS0_MCS_31_0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_MS0_MCS_31_0_SHIFT))&MLB_MS0_MCS_31_0_MASK)
25872 /* MLBPC2 Bit Fields */
25873 #define MLB_MLBPC2_SDOPC_MASK                    0x1u
25874 #define MLB_MLBPC2_SDOPC_SHIFT                   0
25875 #define MLB_MLBPC2_MORCD_MASK                    0x7F00u
25876 #define MLB_MLBPC2_MORCD_SHIFT                   8
25877 #define MLB_MLBPC2_MORCD(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_MLBPC2_MORCD_SHIFT))&MLB_MLBPC2_MORCD_MASK)
25878 #define MLB_MLBPC2_MORCE_MASK                    0x8000u
25879 #define MLB_MLBPC2_MORCE_SHIFT                   15
25880 /* MS1 Bit Fields */
25881 #define MLB_MS1_MCS_63_32_MASK                   0xFFFFFFFFu
25882 #define MLB_MS1_MCS_63_32_SHIFT                  0
25883 #define MLB_MS1_MCS_63_32(x)                     (((uint32_t)(((uint32_t)(x))<<MLB_MS1_MCS_63_32_SHIFT))&MLB_MS1_MCS_63_32_MASK)
25884 /* MSS Bit Fields */
25885 #define MLB_MSS_RSTSYSCMD_MASK                   0x1u
25886 #define MLB_MSS_RSTSYSCMD_SHIFT                  0
25887 #define MLB_MSS_LKSYSCMD_MASK                    0x2u
25888 #define MLB_MSS_LKSYSCMD_SHIFT                   1
25889 #define MLB_MSS_ULKSYSCMD_MASK                   0x4u
25890 #define MLB_MSS_ULKSYSCMD_SHIFT                  2
25891 #define MLB_MSS_CSSYSCMD_MASK                    0x8u
25892 #define MLB_MSS_CSSYSCMD_SHIFT                   3
25893 #define MLB_MSS_SWSYSCMD_MASK                    0x10u
25894 #define MLB_MSS_SWSYSCMD_SHIFT                   4
25895 #define MLB_MSS_SERVREQ_MASK                     0x20u
25896 #define MLB_MSS_SERVREQ_SHIFT                    5
25897 /* MSD Bit Fields */
25898 #define MLB_MSD_SD0_7_0_MASK                     0xFFu
25899 #define MLB_MSD_SD0_7_0_SHIFT                    0
25900 #define MLB_MSD_SD0_7_0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD0_7_0_SHIFT))&MLB_MSD_SD0_7_0_MASK)
25901 #define MLB_MSD_SD1_7_0_MASK                     0xFF00u
25902 #define MLB_MSD_SD1_7_0_SHIFT                    8
25903 #define MLB_MSD_SD1_7_0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD1_7_0_SHIFT))&MLB_MSD_SD1_7_0_MASK)
25904 #define MLB_MSD_SD2_7_0_MASK                     0xFF0000u
25905 #define MLB_MSD_SD2_7_0_SHIFT                    16
25906 #define MLB_MSD_SD2_7_0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD2_7_0_SHIFT))&MLB_MSD_SD2_7_0_MASK)
25907 #define MLB_MSD_SD3_7_0_MASK                     0xFF000000u
25908 #define MLB_MSD_SD3_7_0_SHIFT                    24
25909 #define MLB_MSD_SD3_7_0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD3_7_0_SHIFT))&MLB_MSD_SD3_7_0_MASK)
25910 /* MIEN Bit Fields */
25911 #define MLB_MIEN_ISOC_PE_MASK                    0x1u
25912 #define MLB_MIEN_ISOC_PE_SHIFT                   0
25913 #define MLB_MIEN_ISOC_BUFO_MASK                  0x2u
25914 #define MLB_MIEN_ISOC_BUFO_SHIFT                 1
25915 #define MLB_MIEN_SYNC_PE_MASK                    0x10000u
25916 #define MLB_MIEN_SYNC_PE_SHIFT                   16
25917 #define MLB_MIEN_ARX_DONE_MASK                   0x20000u
25918 #define MLB_MIEN_ARX_DONE_SHIFT                  17
25919 #define MLB_MIEN_ARX_PE_MASK                     0x40000u
25920 #define MLB_MIEN_ARX_PE_SHIFT                    18
25921 #define MLB_MIEN_ARX_BREAK_MASK                  0x80000u
25922 #define MLB_MIEN_ARX_BREAK_SHIFT                 19
25923 #define MLB_MIEN_ATX_DONE_MASK                   0x100000u
25924 #define MLB_MIEN_ATX_DONE_SHIFT                  20
25925 #define MLB_MIEN_ATX_PE_MASK                     0x200000u
25926 #define MLB_MIEN_ATX_PE_SHIFT                    21
25927 #define MLB_MIEN_ATX_BREAK_MASK                  0x400000u
25928 #define MLB_MIEN_ATX_BREAK_SHIFT                 22
25929 #define MLB_MIEN_CRX_DONE_MASK                   0x1000000u
25930 #define MLB_MIEN_CRX_DONE_SHIFT                  24
25931 #define MLB_MIEN_CRX_PE_MASK                     0x2000000u
25932 #define MLB_MIEN_CRX_PE_SHIFT                    25
25933 #define MLB_MIEN_CRX_BREAK_MASK                  0x4000000u
25934 #define MLB_MIEN_CRX_BREAK_SHIFT                 26
25935 #define MLB_MIEN_CTX_DONE_MASK                   0x8000000u
25936 #define MLB_MIEN_CTX_DONE_SHIFT                  27
25937 #define MLB_MIEN_CTX_PE_MASK                     0x10000000u
25938 #define MLB_MIEN_CTX_PE_SHIFT                    28
25939 #define MLB_MIEN_CTX_BREAK_MASK                  0x20000000u
25940 #define MLB_MIEN_CTX_BREAK_SHIFT                 29
25941 /* MLBC1 Bit Fields */
25942 #define MLB_MLBC1_LOCK_MASK                      0x40u
25943 #define MLB_MLBC1_LOCK_SHIFT                     6
25944 #define MLB_MLBC1_CLKM_MASK                      0x80u
25945 #define MLB_MLBC1_CLKM_SHIFT                     7
25946 #define MLB_MLBC1_NDA_7_0_MASK                   0xFF00u
25947 #define MLB_MLBC1_NDA_7_0_SHIFT                  8
25948 #define MLB_MLBC1_NDA_7_0(x)                     (((uint32_t)(((uint32_t)(x))<<MLB_MLBC1_NDA_7_0_SHIFT))&MLB_MLBC1_NDA_7_0_MASK)
25949 /* HCTL Bit Fields */
25950 #define MLB_HCTL_RST0_MASK                       0x1u
25951 #define MLB_HCTL_RST0_SHIFT                      0
25952 #define MLB_HCTL_RST1_MASK                       0x2u
25953 #define MLB_HCTL_RST1_SHIFT                      1
25954 #define MLB_HCTL_EN_MASK                         0x8000u
25955 #define MLB_HCTL_EN_SHIFT                        15
25956 /* HCMR0 Bit Fields */
25957 #define MLB_HCMR0_CHM_31_0_P_MASK                0xFFFFFFFFu
25958 #define MLB_HCMR0_CHM_31_0_P_SHIFT               0
25959 #define MLB_HCMR0_CHM_31_0_P(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_HCMR0_CHM_31_0_P_SHIFT))&MLB_HCMR0_CHM_31_0_P_MASK)
25960 /* HCMR1 Bit Fields */
25961 #define MLB_HCMR1_CHM_63_32_MASK                 0xFFFFFFFFu
25962 #define MLB_HCMR1_CHM_63_32_SHIFT                0
25963 #define MLB_HCMR1_CHM_63_32(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_HCMR1_CHM_63_32_SHIFT))&MLB_HCMR1_CHM_63_32_MASK)
25964 /* HCER0 Bit Fields */
25965 #define MLB_HCER0_CERR_31_0_MASK                 0xFFFFFFFFu
25966 #define MLB_HCER0_CERR_31_0_SHIFT                0
25967 #define MLB_HCER0_CERR_31_0(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_HCER0_CERR_31_0_SHIFT))&MLB_HCER0_CERR_31_0_MASK)
25968 /* HCER1 Bit Fields */
25969 #define MLB_HCER1_CERR_63_32_MASK                0xFFFFFFFFu
25970 #define MLB_HCER1_CERR_63_32_SHIFT               0
25971 #define MLB_HCER1_CERR_63_32(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_HCER1_CERR_63_32_SHIFT))&MLB_HCER1_CERR_63_32_MASK)
25972 /* HCBR0 Bit Fields */
25973 #define MLB_HCBR0_CHB_31_0_MASK                  0xFFFFFFFFu
25974 #define MLB_HCBR0_CHB_31_0_SHIFT                 0
25975 #define MLB_HCBR0_CHB_31_0(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_HCBR0_CHB_31_0_SHIFT))&MLB_HCBR0_CHB_31_0_MASK)
25976 /* HCBR1 Bit Fields */
25977 #define MLB_HCBR1_CHB_63_32_MASK                 0xFFFFFFFFu
25978 #define MLB_HCBR1_CHB_63_32_SHIFT                0
25979 #define MLB_HCBR1_CHB_63_32(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_HCBR1_CHB_63_32_SHIFT))&MLB_HCBR1_CHB_63_32_MASK)
25980 /* MDAT0 Bit Fields */
25981 #define MLB_MDAT0_DATA_31_0_MASK                 0xFFFFFFFFu
25982 #define MLB_MDAT0_DATA_31_0_SHIFT                0
25983 #define MLB_MDAT0_DATA_31_0(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_MDAT0_DATA_31_0_SHIFT))&MLB_MDAT0_DATA_31_0_MASK)
25984 /* MDAT1 Bit Fields */
25985 #define MLB_MDAT1_DATA_63_32_MASK                0xFFFFFFFFu
25986 #define MLB_MDAT1_DATA_63_32_SHIFT               0
25987 #define MLB_MDAT1_DATA_63_32(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_MDAT1_DATA_63_32_SHIFT))&MLB_MDAT1_DATA_63_32_MASK)
25988 /* MDAT2 Bit Fields */
25989 #define MLB_MDAT2_DATA_95_64_MASK                0xFFFFFFFFu
25990 #define MLB_MDAT2_DATA_95_64_SHIFT               0
25991 #define MLB_MDAT2_DATA_95_64(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_MDAT2_DATA_95_64_SHIFT))&MLB_MDAT2_DATA_95_64_MASK)
25992 /* MDAT3 Bit Fields */
25993 #define MLB_MDAT3_DATA_127_96_MASK               0xFFFFFFFFu
25994 #define MLB_MDAT3_DATA_127_96_SHIFT              0
25995 #define MLB_MDAT3_DATA_127_96(x)                 (((uint32_t)(((uint32_t)(x))<<MLB_MDAT3_DATA_127_96_SHIFT))&MLB_MDAT3_DATA_127_96_MASK)
25996 /* MDWE0 Bit Fields */
25997 #define MLB_MDWE0_MASK_31_0_MASK                 0xFFFFFFFFu
25998 #define MLB_MDWE0_MASK_31_0_SHIFT                0
25999 #define MLB_MDWE0_MASK_31_0(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_MDWE0_MASK_31_0_SHIFT))&MLB_MDWE0_MASK_31_0_MASK)
26000 /* MDWE1 Bit Fields */
26001 #define MLB_MDWE1_MASK_63_32_MASK                0xFFFFFFFFu
26002 #define MLB_MDWE1_MASK_63_32_SHIFT               0
26003 #define MLB_MDWE1_MASK_63_32(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_MDWE1_MASK_63_32_SHIFT))&MLB_MDWE1_MASK_63_32_MASK)
26004 /* MDWE2 Bit Fields */
26005 #define MLB_MDWE2_MASK_95_64_MASK                0xFFFFFFFFu
26006 #define MLB_MDWE2_MASK_95_64_SHIFT               0
26007 #define MLB_MDWE2_MASK_95_64(x)                  (((uint32_t)(((uint32_t)(x))<<MLB_MDWE2_MASK_95_64_SHIFT))&MLB_MDWE2_MASK_95_64_MASK)
26008 /* MDWE3 Bit Fields */
26009 #define MLB_MDWE3_MASK_127_96_MASK               0xFFFFFFFFu
26010 #define MLB_MDWE3_MASK_127_96_SHIFT              0
26011 #define MLB_MDWE3_MASK_127_96(x)                 (((uint32_t)(((uint32_t)(x))<<MLB_MDWE3_MASK_127_96_SHIFT))&MLB_MDWE3_MASK_127_96_MASK)
26012 /* MCTL Bit Fields */
26013 #define MLB_MCTL_XCMP_MASK                       0x1u
26014 #define MLB_MCTL_XCMP_SHIFT                      0
26015 /* MADR Bit Fields */
26016 #define MLB_MADR_ADDR_7_0_MASK                   0xFFu
26017 #define MLB_MADR_ADDR_7_0_SHIFT                  0
26018 #define MLB_MADR_ADDR_7_0(x)                     (((uint32_t)(((uint32_t)(x))<<MLB_MADR_ADDR_7_0_SHIFT))&MLB_MADR_ADDR_7_0_MASK)
26019 #define MLB_MADR_ADDR_13_8_MASK                  0x3F00u
26020 #define MLB_MADR_ADDR_13_8_SHIFT                 8
26021 #define MLB_MADR_ADDR_13_8(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_MADR_ADDR_13_8_SHIFT))&MLB_MADR_ADDR_13_8_MASK)
26022 #define MLB_MADR_TB_MASK                         0x40000000u
26023 #define MLB_MADR_TB_SHIFT                        30
26024 #define MLB_MADR_WNR_MASK                        0x80000000u
26025 #define MLB_MADR_WNR_SHIFT                       31
26026 /* ACTL Bit Fields */
26027 #define MLB_ACTL_SCE_MASK                        0x1u
26028 #define MLB_ACTL_SCE_SHIFT                       0
26029 #define MLB_ACTL_SMX_MASK                        0x2u
26030 #define MLB_ACTL_SMX_SHIFT                       1
26031 #define MLB_ACTL_DMA_MODE_MASK                   0x4u
26032 #define MLB_ACTL_DMA_MODE_SHIFT                  2
26033 #define MLB_ACTL_MPB_MASK                        0x10u
26034 #define MLB_ACTL_MPB_SHIFT                       4
26035 /* ACSR0 Bit Fields */
26036 #define MLB_ACSR0_CHS_MASK                       0xFFFFFFFFu
26037 #define MLB_ACSR0_CHS_SHIFT                      0
26038 #define MLB_ACSR0_CHS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_ACSR0_CHS_SHIFT))&MLB_ACSR0_CHS_MASK)
26039 /* ACSR1 Bit Fields */
26040 #define MLB_ACSR1_CHS_MASK                       0xFFFFFFFFu
26041 #define MLB_ACSR1_CHS_SHIFT                      0
26042 #define MLB_ACSR1_CHS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_ACSR1_CHS_SHIFT))&MLB_ACSR1_CHS_MASK)
26043 /* ACMR0 Bit Fields */
26044 #define MLB_ACMR0_CHM_31_0_MASK                  0xFFFFFFFFu
26045 #define MLB_ACMR0_CHM_31_0_SHIFT                 0
26046 #define MLB_ACMR0_CHM_31_0(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_ACMR0_CHM_31_0_SHIFT))&MLB_ACMR0_CHM_31_0_MASK)
26047 /* ACMR1 Bit Fields */
26048 #define MLB_ACMR1_CHM_MASK                       0xFFFFFFFFu
26049 #define MLB_ACMR1_CHM_SHIFT                      0
26050 #define MLB_ACMR1_CHM(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_ACMR1_CHM_SHIFT))&MLB_ACMR1_CHM_MASK)
26051 
26052 /*!
26053  * @}
26054  */ /* end of group MLB_Register_Masks */
26055 
26056 /* MLB - Peripheral instance base addresses */
26057 /** Peripheral MLB base address */
26058 #define MLB_BASE                                 (0x4218C000u)
26059 /** Peripheral MLB base pointer */
26060 #define MLB                                      ((MLB_Type *)MLB_BASE)
26061 #define MLB_BASE_PTR                             (MLB)
26062 /** Array initializer of MLB peripheral base addresses */
26063 #define MLB_BASE_ADDRS                           { MLB_BASE }
26064 /** Array initializer of MLB peripheral base pointers */
26065 #define MLB_BASE_PTRS                            { MLB }
26066 
26067 /* ----------------------------------------------------------------------------
26068    -- MLB - Register accessor macros
26069    ---------------------------------------------------------------------------- */
26070 
26071 /*!
26072  * @addtogroup MLB_Register_Accessor_Macros MLB - Register accessor macros
26073  * @{
26074  */
26075 
26076 /* MLB - Register instance definitions */
26077 /* MLB */
26078 #define MLB_MLBC0                                MLB_MLBC0_REG(MLB_BASE_PTR)
26079 #define MLB_MS0                                  MLB_MS0_REG(MLB_BASE_PTR)
26080 #define MLB_MLBPC2                               MLB_MLBPC2_REG(MLB_BASE_PTR)
26081 #define MLB_MS1                                  MLB_MS1_REG(MLB_BASE_PTR)
26082 #define MLB_MSS                                  MLB_MSS_REG(MLB_BASE_PTR)
26083 #define MLB_MSD                                  MLB_MSD_REG(MLB_BASE_PTR)
26084 #define MLB_MIEN                                 MLB_MIEN_REG(MLB_BASE_PTR)
26085 #define MLB_MLBC1                                MLB_MLBC1_REG(MLB_BASE_PTR)
26086 #define MLB_HCTL                                 MLB_HCTL_REG(MLB_BASE_PTR)
26087 #define MLB_HCMR0                                MLB_HCMR0_REG(MLB_BASE_PTR)
26088 #define MLB_HCMR1                                MLB_HCMR1_REG(MLB_BASE_PTR)
26089 #define MLB_HCER0                                MLB_HCER0_REG(MLB_BASE_PTR)
26090 #define MLB_HCER1                                MLB_HCER1_REG(MLB_BASE_PTR)
26091 #define MLB_HCBR0                                MLB_HCBR0_REG(MLB_BASE_PTR)
26092 #define MLB_HCBR1                                MLB_HCBR1_REG(MLB_BASE_PTR)
26093 #define MLB_MDAT0                                MLB_MDAT0_REG(MLB_BASE_PTR)
26094 #define MLB_MDAT1                                MLB_MDAT1_REG(MLB_BASE_PTR)
26095 #define MLB_MDAT2                                MLB_MDAT2_REG(MLB_BASE_PTR)
26096 #define MLB_MDAT3                                MLB_MDAT3_REG(MLB_BASE_PTR)
26097 #define MLB_MDWE0                                MLB_MDWE0_REG(MLB_BASE_PTR)
26098 #define MLB_MDWE1                                MLB_MDWE1_REG(MLB_BASE_PTR)
26099 #define MLB_MDWE2                                MLB_MDWE2_REG(MLB_BASE_PTR)
26100 #define MLB_MDWE3                                MLB_MDWE3_REG(MLB_BASE_PTR)
26101 #define MLB_MCTL                                 MLB_MCTL_REG(MLB_BASE_PTR)
26102 #define MLB_MADR                                 MLB_MADR_REG(MLB_BASE_PTR)
26103 #define MLB_ACTL                                 MLB_ACTL_REG(MLB_BASE_PTR)
26104 #define MLB_ACSR0                                MLB_ACSR0_REG(MLB_BASE_PTR)
26105 #define MLB_ACSR1                                MLB_ACSR1_REG(MLB_BASE_PTR)
26106 #define MLB_ACMR0                                MLB_ACMR0_REG(MLB_BASE_PTR)
26107 #define MLB_ACMR1                                MLB_ACMR1_REG(MLB_BASE_PTR)
26108 
26109 /*!
26110  * @}
26111  */ /* end of group MLB_Register_Accessor_Macros */
26112 
26113 /*!
26114  * @}
26115  */ /* end of group MLB_Peripheral */
26116 
26117 /* ----------------------------------------------------------------------------
26118    -- MMDC Peripheral Access Layer
26119    ---------------------------------------------------------------------------- */
26120 
26121 /*!
26122  * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer
26123  * @{
26124  */
26125 
26126 /** MMDC - Register Layout Typedef */
26127 typedef struct {
26128   __IO  uint32_t MDCTL;                                  /**< MMDC Core Control Register, offset: 0x0 */
26129   __IO  uint32_t MDPDC;                                  /**< MMDC Core Power Down Control Register, offset: 0x4 */
26130   __IO  uint32_t MDOTC;                                  /**< MMDC Core ODT Timing Control Register, offset: 0x8 */
26131   __IO  uint32_t MDCFG0;                                 /**< MMDC Core Timing Configuration Register 0, offset: 0xC */
26132   __IO  uint32_t MDCFG1;                                 /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */
26133   __IO  uint32_t MDCFG2;                                 /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */
26134   __IO  uint32_t MDMISC;                                 /**< MMDC Core Miscellaneous Register, offset: 0x18 */
26135   __IO  uint32_t MDSCR;                                  /**< MMDC Core Special Command Register, offset: 0x1C */
26136   __IO  uint32_t MDREF;                                  /**< MMDC Core Refresh Control Register, offset: 0x20 */
26137   uint8_t RESERVED_0[8];
26138   __IO  uint32_t MDRWD;                                  /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */
26139   __IO  uint32_t MDOR;                                   /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */
26140   __I   uint32_t MDMRR;                                  /**< MMDC Core MRR Data Register, offset: 0x34 */
26141   __IO  uint32_t MDCFG3LP;                               /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */
26142   __IO  uint32_t MDMR4;                                  /**< MMDC Core MR4 Derating Register, offset: 0x3C */
26143   __IO  uint32_t MDASP;                                  /**< MMDC Core Address Space Partition Register, offset: 0x40 */
26144   uint8_t RESERVED_1[956];
26145   __IO  uint32_t MAARCR;                                 /**< MMDC Core AXI Reordering Control Regsiter, offset: 0x400 */
26146   __IO  uint32_t MAPSR;                                  /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */
26147   __IO  uint32_t MAEXIDR0;                               /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */
26148   __IO  uint32_t MAEXIDR1;                               /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */
26149   __IO  uint32_t MADPCR0;                                /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */
26150   __IO  uint32_t MADPCR1;                                /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */
26151   __I   uint32_t MADPSR0;                                /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */
26152   __I   uint32_t MADPSR1;                                /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */
26153   __I   uint32_t MADPSR2;                                /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */
26154   __I   uint32_t MADPSR3;                                /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */
26155   __I   uint32_t MADPSR4;                                /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */
26156   __I   uint32_t MADPSR5;                                /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */
26157   __I   uint32_t MASBS0;                                 /**< MMDC Core Step By Step Address Register, offset: 0x430 */
26158   __I   uint32_t MASBS1;                                 /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */
26159   uint8_t RESERVED_2[8];
26160   __IO  uint32_t MAGENP;                                 /**< MMDC Core General Purpose Register, offset: 0x440 */
26161   uint8_t RESERVED_3[956];
26162   __IO  uint32_t MPZQHWCTRL;                             /**< MMDC PHY ZQ HW control register, offset: 0x800 */
26163   __IO  uint32_t MPZQSWCTRL;                             /**< MMDC PHY ZQ SW control register, offset: 0x804 */
26164   __IO  uint32_t MPWLGCR;                                /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */
26165   __IO  uint32_t MPWLDECTRL0;                            /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */
26166   __IO  uint32_t MPWLDECTRL1;                            /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */
26167   __I   uint32_t MPWLDLST;                               /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */
26168   __IO  uint32_t MPODTCTRL;                              /**< MMDC PHY ODT control register, offset: 0x818 */
26169   __IO  uint32_t MPRDDQBY0DL;                            /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */
26170   __IO  uint32_t MPRDDQBY1DL;                            /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */
26171   __IO  uint32_t MPRDDQBY2DL;                            /**< MMDC PHY Read DQ Byte2 Delay Register, offset: 0x824 */
26172   __IO  uint32_t MPRDDQBY3DL;                            /**< MMDC PHY Read DQ Byte3 Delay Register, offset: 0x828 */
26173   __IO  uint32_t MPWRDQBY0DL;                            /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */
26174   __IO  uint32_t MPWRDQBY1DL;                            /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */
26175   __IO  uint32_t MPWRDQBY2DL;                            /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */
26176   __IO  uint32_t MPWRDQBY3DL;                            /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */
26177   __IO  uint32_t MPDGCTRL0;                              /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */
26178   __IO  uint32_t MPDGCTRL1;                              /**< MMDC PHY Read DQS Gating Control Register 1, offset: 0x840 */
26179   __I   uint32_t MPDGDLST0;                              /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */
26180   __IO  uint32_t MPRDDLCTL;                              /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */
26181   __I   uint32_t MPRDDLST;                               /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */
26182   __IO  uint32_t MPWRDLCTL;                              /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */
26183   __I   uint32_t MPWRDLST;                               /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */
26184   __IO  uint32_t MPSDCTRL;                               /**< MMDC PHY CK Control Register, offset: 0x858 */
26185   __IO  uint32_t MPZQLP2CTL;                             /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */
26186   __IO  uint32_t MPRDDLHWCTL;                            /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */
26187   __IO  uint32_t MPWRDLHWCTL;                            /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */
26188   __I   uint32_t MPRDDLHWST0;                            /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */
26189   __I   uint32_t MPRDDLHWST1;                            /**< MMDC PHY Read Delay HW Calibration Status Register 1, offset: 0x86C */
26190   __I   uint32_t MPWRDLHWST0;                            /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */
26191   __I   uint32_t MPWRDLHWST1;                            /**< MMDC PHY Write Delay HW Calibration Status Register 1, offset: 0x874 */
26192   __IO  uint32_t MPWLHWERR;                              /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */
26193   __I   uint32_t MPDGHWST0;                              /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */
26194   __I   uint32_t MPDGHWST1;                              /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */
26195   __I   uint32_t MPDGHWST2;                              /**< MMDC PHY Read DQS Gating HW Status Register 2, offset: 0x884 */
26196   __I   uint32_t MPDGHWST3;                              /**< MMDC PHY Read DQS Gating HW Status Register 3, offset: 0x888 */
26197   __IO  uint32_t MPPDCMPR1;                              /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */
26198   __IO  uint32_t MPPDCMPR2;                              /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */
26199   __IO  uint32_t MPSWDAR0;                               /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */
26200   __I   uint32_t MPSWDRDR0;                              /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */
26201   __I   uint32_t MPSWDRDR1;                              /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */
26202   __I   uint32_t MPSWDRDR2;                              /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */
26203   __I   uint32_t MPSWDRDR3;                              /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */
26204   __I   uint32_t MPSWDRDR4;                              /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */
26205   __I   uint32_t MPSWDRDR5;                              /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */
26206   __I   uint32_t MPSWDRDR6;                              /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */
26207   __I   uint32_t MPSWDRDR7;                              /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */
26208   __IO  uint32_t MPMUR0;                                 /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */
26209   __IO  uint32_t MPWRCADL;                               /**< MMDC Write CA delay-line controller, offset: 0x8BC */
26210   __IO  uint32_t MPDCCR;                                 /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */
26211 } MMDC_Type, *MMDC_MemMapPtr;
26212 
26213 /* ----------------------------------------------------------------------------
26214    -- MMDC - Register accessor macros
26215    ---------------------------------------------------------------------------- */
26216 
26217 /*!
26218  * @addtogroup MMDC_Register_Accessor_Macros MMDC - Register accessor macros
26219  * @{
26220  */
26221 
26222 /* MMDC - Register accessors */
26223 #define MMDC_MDCTL_REG(base)                     ((base)->MDCTL)
26224 #define MMDC_MDPDC_REG(base)                     ((base)->MDPDC)
26225 #define MMDC_MDOTC_REG(base)                     ((base)->MDOTC)
26226 #define MMDC_MDCFG0_REG(base)                    ((base)->MDCFG0)
26227 #define MMDC_MDCFG1_REG(base)                    ((base)->MDCFG1)
26228 #define MMDC_MDCFG2_REG(base)                    ((base)->MDCFG2)
26229 #define MMDC_MDMISC_REG(base)                    ((base)->MDMISC)
26230 #define MMDC_MDSCR_REG(base)                     ((base)->MDSCR)
26231 #define MMDC_MDREF_REG(base)                     ((base)->MDREF)
26232 #define MMDC_MDRWD_REG(base)                     ((base)->MDRWD)
26233 #define MMDC_MDOR_REG(base)                      ((base)->MDOR)
26234 #define MMDC_MDMRR_REG(base)                     ((base)->MDMRR)
26235 #define MMDC_MDCFG3LP_REG(base)                  ((base)->MDCFG3LP)
26236 #define MMDC_MDMR4_REG(base)                     ((base)->MDMR4)
26237 #define MMDC_MDASP_REG(base)                     ((base)->MDASP)
26238 #define MMDC_MAARCR_REG(base)                    ((base)->MAARCR)
26239 #define MMDC_MAPSR_REG(base)                     ((base)->MAPSR)
26240 #define MMDC_MAEXIDR0_REG(base)                  ((base)->MAEXIDR0)
26241 #define MMDC_MAEXIDR1_REG(base)                  ((base)->MAEXIDR1)
26242 #define MMDC_MADPCR0_REG(base)                   ((base)->MADPCR0)
26243 #define MMDC_MADPCR1_REG(base)                   ((base)->MADPCR1)
26244 #define MMDC_MADPSR0_REG(base)                   ((base)->MADPSR0)
26245 #define MMDC_MADPSR1_REG(base)                   ((base)->MADPSR1)
26246 #define MMDC_MADPSR2_REG(base)                   ((base)->MADPSR2)
26247 #define MMDC_MADPSR3_REG(base)                   ((base)->MADPSR3)
26248 #define MMDC_MADPSR4_REG(base)                   ((base)->MADPSR4)
26249 #define MMDC_MADPSR5_REG(base)                   ((base)->MADPSR5)
26250 #define MMDC_MASBS0_REG(base)                    ((base)->MASBS0)
26251 #define MMDC_MASBS1_REG(base)                    ((base)->MASBS1)
26252 #define MMDC_MAGENP_REG(base)                    ((base)->MAGENP)
26253 #define MMDC_MPZQHWCTRL_REG(base)                ((base)->MPZQHWCTRL)
26254 #define MMDC_MPZQSWCTRL_REG(base)                ((base)->MPZQSWCTRL)
26255 #define MMDC_MPWLGCR_REG(base)                   ((base)->MPWLGCR)
26256 #define MMDC_MPWLDECTRL0_REG(base)               ((base)->MPWLDECTRL0)
26257 #define MMDC_MPWLDECTRL1_REG(base)               ((base)->MPWLDECTRL1)
26258 #define MMDC_MPWLDLST_REG(base)                  ((base)->MPWLDLST)
26259 #define MMDC_MPODTCTRL_REG(base)                 ((base)->MPODTCTRL)
26260 #define MMDC_MPRDDQBY0DL_REG(base)               ((base)->MPRDDQBY0DL)
26261 #define MMDC_MPRDDQBY1DL_REG(base)               ((base)->MPRDDQBY1DL)
26262 #define MMDC_MPRDDQBY2DL_REG(base)               ((base)->MPRDDQBY2DL)
26263 #define MMDC_MPRDDQBY3DL_REG(base)               ((base)->MPRDDQBY3DL)
26264 #define MMDC_MPWRDQBY0DL_REG(base)               ((base)->MPWRDQBY0DL)
26265 #define MMDC_MPWRDQBY1DL_REG(base)               ((base)->MPWRDQBY1DL)
26266 #define MMDC_MPWRDQBY2DL_REG(base)               ((base)->MPWRDQBY2DL)
26267 #define MMDC_MPWRDQBY3DL_REG(base)               ((base)->MPWRDQBY3DL)
26268 #define MMDC_MPDGCTRL0_REG(base)                 ((base)->MPDGCTRL0)
26269 #define MMDC_MPDGCTRL1_REG(base)                 ((base)->MPDGCTRL1)
26270 #define MMDC_MPDGDLST0_REG(base)                 ((base)->MPDGDLST0)
26271 #define MMDC_MPRDDLCTL_REG(base)                 ((base)->MPRDDLCTL)
26272 #define MMDC_MPRDDLST_REG(base)                  ((base)->MPRDDLST)
26273 #define MMDC_MPWRDLCTL_REG(base)                 ((base)->MPWRDLCTL)
26274 #define MMDC_MPWRDLST_REG(base)                  ((base)->MPWRDLST)
26275 #define MMDC_MPSDCTRL_REG(base)                  ((base)->MPSDCTRL)
26276 #define MMDC_MPZQLP2CTL_REG(base)                ((base)->MPZQLP2CTL)
26277 #define MMDC_MPRDDLHWCTL_REG(base)               ((base)->MPRDDLHWCTL)
26278 #define MMDC_MPWRDLHWCTL_REG(base)               ((base)->MPWRDLHWCTL)
26279 #define MMDC_MPRDDLHWST0_REG(base)               ((base)->MPRDDLHWST0)
26280 #define MMDC_MPRDDLHWST1_REG(base)               ((base)->MPRDDLHWST1)
26281 #define MMDC_MPWRDLHWST0_REG(base)               ((base)->MPWRDLHWST0)
26282 #define MMDC_MPWRDLHWST1_REG(base)               ((base)->MPWRDLHWST1)
26283 #define MMDC_MPWLHWERR_REG(base)                 ((base)->MPWLHWERR)
26284 #define MMDC_MPDGHWST0_REG(base)                 ((base)->MPDGHWST0)
26285 #define MMDC_MPDGHWST1_REG(base)                 ((base)->MPDGHWST1)
26286 #define MMDC_MPDGHWST2_REG(base)                 ((base)->MPDGHWST2)
26287 #define MMDC_MPDGHWST3_REG(base)                 ((base)->MPDGHWST3)
26288 #define MMDC_MPPDCMPR1_REG(base)                 ((base)->MPPDCMPR1)
26289 #define MMDC_MPPDCMPR2_REG(base)                 ((base)->MPPDCMPR2)
26290 #define MMDC_MPSWDAR0_REG(base)                  ((base)->MPSWDAR0)
26291 #define MMDC_MPSWDRDR0_REG(base)                 ((base)->MPSWDRDR0)
26292 #define MMDC_MPSWDRDR1_REG(base)                 ((base)->MPSWDRDR1)
26293 #define MMDC_MPSWDRDR2_REG(base)                 ((base)->MPSWDRDR2)
26294 #define MMDC_MPSWDRDR3_REG(base)                 ((base)->MPSWDRDR3)
26295 #define MMDC_MPSWDRDR4_REG(base)                 ((base)->MPSWDRDR4)
26296 #define MMDC_MPSWDRDR5_REG(base)                 ((base)->MPSWDRDR5)
26297 #define MMDC_MPSWDRDR6_REG(base)                 ((base)->MPSWDRDR6)
26298 #define MMDC_MPSWDRDR7_REG(base)                 ((base)->MPSWDRDR7)
26299 #define MMDC_MPMUR0_REG(base)                    ((base)->MPMUR0)
26300 #define MMDC_MPWRCADL_REG(base)                  ((base)->MPWRCADL)
26301 #define MMDC_MPDCCR_REG(base)                    ((base)->MPDCCR)
26302 
26303 /*!
26304  * @}
26305  */ /* end of group MMDC_Register_Accessor_Macros */
26306 
26307 /* ----------------------------------------------------------------------------
26308    -- MMDC Register Masks
26309    ---------------------------------------------------------------------------- */
26310 
26311 /*!
26312  * @addtogroup MMDC_Register_Masks MMDC Register Masks
26313  * @{
26314  */
26315 
26316 /* MDCTL Bit Fields */
26317 #define MMDC_MDCTL_DSIZ_MASK                     0x30000u
26318 #define MMDC_MDCTL_DSIZ_SHIFT                    16
26319 #define MMDC_MDCTL_DSIZ(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_DSIZ_SHIFT))&MMDC_MDCTL_DSIZ_MASK)
26320 #define MMDC_MDCTL_BL_MASK                       0x80000u
26321 #define MMDC_MDCTL_BL_SHIFT                      19
26322 #define MMDC_MDCTL_COL_MASK                      0x700000u
26323 #define MMDC_MDCTL_COL_SHIFT                     20
26324 #define MMDC_MDCTL_COL(x)                        (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_COL_SHIFT))&MMDC_MDCTL_COL_MASK)
26325 #define MMDC_MDCTL_ROW_MASK                      0x7000000u
26326 #define MMDC_MDCTL_ROW_SHIFT                     24
26327 #define MMDC_MDCTL_ROW(x)                        (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_ROW_SHIFT))&MMDC_MDCTL_ROW_MASK)
26328 #define MMDC_MDCTL_SDE_1_MASK                    0x40000000u
26329 #define MMDC_MDCTL_SDE_1_SHIFT                   30
26330 #define MMDC_MDCTL_SDE_0_MASK                    0x80000000u
26331 #define MMDC_MDCTL_SDE_0_SHIFT                   31
26332 /* MDPDC Bit Fields */
26333 #define MMDC_MDPDC_tCKSRE_MASK                   0x7u
26334 #define MMDC_MDPDC_tCKSRE_SHIFT                  0
26335 #define MMDC_MDPDC_tCKSRE(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKSRE_SHIFT))&MMDC_MDPDC_tCKSRE_MASK)
26336 #define MMDC_MDPDC_tCKSRX_MASK                   0x38u
26337 #define MMDC_MDPDC_tCKSRX_SHIFT                  3
26338 #define MMDC_MDPDC_tCKSRX(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKSRX_SHIFT))&MMDC_MDPDC_tCKSRX_MASK)
26339 #define MMDC_MDPDC_BOTH_CS_PD_MASK               0x40u
26340 #define MMDC_MDPDC_BOTH_CS_PD_SHIFT              6
26341 #define MMDC_MDPDC_SLOW_PD_MASK                  0x80u
26342 #define MMDC_MDPDC_SLOW_PD_SHIFT                 7
26343 #define MMDC_MDPDC_PWDT_0_MASK                   0xF00u
26344 #define MMDC_MDPDC_PWDT_0_SHIFT                  8
26345 #define MMDC_MDPDC_PWDT_0(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PWDT_0_SHIFT))&MMDC_MDPDC_PWDT_0_MASK)
26346 #define MMDC_MDPDC_PWDT_1_MASK                   0xF000u
26347 #define MMDC_MDPDC_PWDT_1_SHIFT                  12
26348 #define MMDC_MDPDC_PWDT_1(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PWDT_1_SHIFT))&MMDC_MDPDC_PWDT_1_MASK)
26349 #define MMDC_MDPDC_tCKE_MASK                     0x70000u
26350 #define MMDC_MDPDC_tCKE_SHIFT                    16
26351 #define MMDC_MDPDC_tCKE(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKE_SHIFT))&MMDC_MDPDC_tCKE_MASK)
26352 #define MMDC_MDPDC_PRCT_0_MASK                   0x7000000u
26353 #define MMDC_MDPDC_PRCT_0_SHIFT                  24
26354 #define MMDC_MDPDC_PRCT_0(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PRCT_0_SHIFT))&MMDC_MDPDC_PRCT_0_MASK)
26355 #define MMDC_MDPDC_PRCT_1_MASK                   0x70000000u
26356 #define MMDC_MDPDC_PRCT_1_SHIFT                  28
26357 #define MMDC_MDPDC_PRCT_1(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PRCT_1_SHIFT))&MMDC_MDPDC_PRCT_1_MASK)
26358 /* MDOTC Bit Fields */
26359 #define MMDC_MDOTC_tODT_idle_off_MASK            0x1F0u
26360 #define MMDC_MDOTC_tODT_idle_off_SHIFT           4
26361 #define MMDC_MDOTC_tODT_idle_off(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tODT_idle_off_SHIFT))&MMDC_MDOTC_tODT_idle_off_MASK)
26362 #define MMDC_MDOTC_tODTLon_MASK                  0x7000u
26363 #define MMDC_MDOTC_tODTLon_SHIFT                 12
26364 #define MMDC_MDOTC_tODTLon(x)                    (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tODTLon_SHIFT))&MMDC_MDOTC_tODTLon_MASK)
26365 #define MMDC_MDOTC_tAXPD_MASK                    0xF0000u
26366 #define MMDC_MDOTC_tAXPD_SHIFT                   16
26367 #define MMDC_MDOTC_tAXPD(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAXPD_SHIFT))&MMDC_MDOTC_tAXPD_MASK)
26368 #define MMDC_MDOTC_tANPD_MASK                    0xF00000u
26369 #define MMDC_MDOTC_tANPD_SHIFT                   20
26370 #define MMDC_MDOTC_tANPD(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tANPD_SHIFT))&MMDC_MDOTC_tANPD_MASK)
26371 #define MMDC_MDOTC_tAONPD_MASK                   0x7000000u
26372 #define MMDC_MDOTC_tAONPD_SHIFT                  24
26373 #define MMDC_MDOTC_tAONPD(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAONPD_SHIFT))&MMDC_MDOTC_tAONPD_MASK)
26374 #define MMDC_MDOTC_tAOFPD_MASK                   0x38000000u
26375 #define MMDC_MDOTC_tAOFPD_SHIFT                  27
26376 #define MMDC_MDOTC_tAOFPD(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAOFPD_SHIFT))&MMDC_MDOTC_tAOFPD_MASK)
26377 /* MDCFG0 Bit Fields */
26378 #define MMDC_MDCFG0_tCL_MASK                     0xFu
26379 #define MMDC_MDCFG0_tCL_SHIFT                    0
26380 #define MMDC_MDCFG0_tCL(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tCL_SHIFT))&MMDC_MDCFG0_tCL_MASK)
26381 #define MMDC_MDCFG0_tFAW_MASK                    0x1F0u
26382 #define MMDC_MDCFG0_tFAW_SHIFT                   4
26383 #define MMDC_MDCFG0_tFAW(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tFAW_SHIFT))&MMDC_MDCFG0_tFAW_MASK)
26384 #define MMDC_MDCFG0_tXPDLL_MASK                  0x1E00u
26385 #define MMDC_MDCFG0_tXPDLL_SHIFT                 9
26386 #define MMDC_MDCFG0_tXPDLL(x)                    (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXPDLL_SHIFT))&MMDC_MDCFG0_tXPDLL_MASK)
26387 #define MMDC_MDCFG0_tXP_MASK                     0xE000u
26388 #define MMDC_MDCFG0_tXP_SHIFT                    13
26389 #define MMDC_MDCFG0_tXP(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXP_SHIFT))&MMDC_MDCFG0_tXP_MASK)
26390 #define MMDC_MDCFG0_tXS_MASK                     0xFF0000u
26391 #define MMDC_MDCFG0_tXS_SHIFT                    16
26392 #define MMDC_MDCFG0_tXS(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXS_SHIFT))&MMDC_MDCFG0_tXS_MASK)
26393 #define MMDC_MDCFG0_tRFC_MASK                    0xFF000000u
26394 #define MMDC_MDCFG0_tRFC_SHIFT                   24
26395 #define MMDC_MDCFG0_tRFC(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tRFC_SHIFT))&MMDC_MDCFG0_tRFC_MASK)
26396 /* MDCFG1 Bit Fields */
26397 #define MMDC_MDCFG1_tCWL_MASK                    0x7u
26398 #define MMDC_MDCFG1_tCWL_SHIFT                   0
26399 #define MMDC_MDCFG1_tCWL(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tCWL_SHIFT))&MMDC_MDCFG1_tCWL_MASK)
26400 #define MMDC_MDCFG1_tMRD_MASK                    0x1E0u
26401 #define MMDC_MDCFG1_tMRD_SHIFT                   5
26402 #define MMDC_MDCFG1_tMRD(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tMRD_SHIFT))&MMDC_MDCFG1_tMRD_MASK)
26403 #define MMDC_MDCFG1_tWR_MASK                     0xE00u
26404 #define MMDC_MDCFG1_tWR_SHIFT                    9
26405 #define MMDC_MDCFG1_tWR(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tWR_SHIFT))&MMDC_MDCFG1_tWR_MASK)
26406 #define MMDC_MDCFG1_tRPA_MASK                    0x8000u
26407 #define MMDC_MDCFG1_tRPA_SHIFT                   15
26408 #define MMDC_MDCFG1_tRAS_MASK                    0x1F0000u
26409 #define MMDC_MDCFG1_tRAS_SHIFT                   16
26410 #define MMDC_MDCFG1_tRAS(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRAS_SHIFT))&MMDC_MDCFG1_tRAS_MASK)
26411 #define MMDC_MDCFG1_tRC_MASK                     0x3E00000u
26412 #define MMDC_MDCFG1_tRC_SHIFT                    21
26413 #define MMDC_MDCFG1_tRC(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRC_SHIFT))&MMDC_MDCFG1_tRC_MASK)
26414 #define MMDC_MDCFG1_tRP_MASK                     0x1C000000u
26415 #define MMDC_MDCFG1_tRP_SHIFT                    26
26416 #define MMDC_MDCFG1_tRP(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRP_SHIFT))&MMDC_MDCFG1_tRP_MASK)
26417 #define MMDC_MDCFG1_tRCD_MASK                    0xE0000000u
26418 #define MMDC_MDCFG1_tRCD_SHIFT                   29
26419 #define MMDC_MDCFG1_tRCD(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRCD_SHIFT))&MMDC_MDCFG1_tRCD_MASK)
26420 /* MDCFG2 Bit Fields */
26421 #define MMDC_MDCFG2_tRRD_MASK                    0x7u
26422 #define MMDC_MDCFG2_tRRD_SHIFT                   0
26423 #define MMDC_MDCFG2_tRRD(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tRRD_SHIFT))&MMDC_MDCFG2_tRRD_MASK)
26424 #define MMDC_MDCFG2_tWTR_MASK                    0x38u
26425 #define MMDC_MDCFG2_tWTR_SHIFT                   3
26426 #define MMDC_MDCFG2_tWTR(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tWTR_SHIFT))&MMDC_MDCFG2_tWTR_MASK)
26427 #define MMDC_MDCFG2_tRTP_MASK                    0x1C0u
26428 #define MMDC_MDCFG2_tRTP_SHIFT                   6
26429 #define MMDC_MDCFG2_tRTP(x)                      (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tRTP_SHIFT))&MMDC_MDCFG2_tRTP_MASK)
26430 #define MMDC_MDCFG2_tDLLK_MASK                   0x1FF0000u
26431 #define MMDC_MDCFG2_tDLLK_SHIFT                  16
26432 #define MMDC_MDCFG2_tDLLK(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tDLLK_SHIFT))&MMDC_MDCFG2_tDLLK_MASK)
26433 /* MDMISC Bit Fields */
26434 #define MMDC_MDMISC_RST_MASK                     0x2u
26435 #define MMDC_MDMISC_RST_SHIFT                    1
26436 #define MMDC_MDMISC_DDR_TYPE_MASK                0x18u
26437 #define MMDC_MDMISC_DDR_TYPE_SHIFT               3
26438 #define MMDC_MDMISC_DDR_TYPE(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_DDR_TYPE_SHIFT))&MMDC_MDMISC_DDR_TYPE_MASK)
26439 #define MMDC_MDMISC_DDR_4_BANK_MASK              0x20u
26440 #define MMDC_MDMISC_DDR_4_BANK_SHIFT             5
26441 #define MMDC_MDMISC_RALAT_MASK                   0x1C0u
26442 #define MMDC_MDMISC_RALAT_SHIFT                  6
26443 #define MMDC_MDMISC_RALAT(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_RALAT_SHIFT))&MMDC_MDMISC_RALAT_MASK)
26444 #define MMDC_MDMISC_MIF3_MODE_MASK               0x600u
26445 #define MMDC_MDMISC_MIF3_MODE_SHIFT              9
26446 #define MMDC_MDMISC_MIF3_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_MIF3_MODE_SHIFT))&MMDC_MDMISC_MIF3_MODE_MASK)
26447 #define MMDC_MDMISC_LPDDR2_S2_MASK               0x800u
26448 #define MMDC_MDMISC_LPDDR2_S2_SHIFT              11
26449 #define MMDC_MDMISC_BI_ON_MASK                   0x1000u
26450 #define MMDC_MDMISC_BI_ON_SHIFT                  12
26451 #define MMDC_MDMISC_WALAT_MASK                   0x30000u
26452 #define MMDC_MDMISC_WALAT_SHIFT                  16
26453 #define MMDC_MDMISC_WALAT(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_WALAT_SHIFT))&MMDC_MDMISC_WALAT_MASK)
26454 #define MMDC_MDMISC_LHD_MASK                     0x40000u
26455 #define MMDC_MDMISC_LHD_SHIFT                    18
26456 #define MMDC_MDMISC_ADDR_MIRROR_MASK             0x80000u
26457 #define MMDC_MDMISC_ADDR_MIRROR_SHIFT            19
26458 #define MMDC_MDMISC_CALIB_PER_CS_MASK            0x100000u
26459 #define MMDC_MDMISC_CALIB_PER_CS_SHIFT           20
26460 #define MMDC_MDMISC_CK1_GATING_MASK              0x200000u
26461 #define MMDC_MDMISC_CK1_GATING_SHIFT             21
26462 #define MMDC_MDMISC_CS1_RDY_MASK                 0x40000000u
26463 #define MMDC_MDMISC_CS1_RDY_SHIFT                30
26464 #define MMDC_MDMISC_CS0_RDY_MASK                 0x80000000u
26465 #define MMDC_MDMISC_CS0_RDY_SHIFT                31
26466 /* MDSCR Bit Fields */
26467 #define MMDC_MDSCR_CMD_BA_MASK                   0x7u
26468 #define MMDC_MDSCR_CMD_BA_SHIFT                  0
26469 #define MMDC_MDSCR_CMD_BA(x)                     (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_BA_SHIFT))&MMDC_MDSCR_CMD_BA_MASK)
26470 #define MMDC_MDSCR_CMD_CS_MASK                   0x8u
26471 #define MMDC_MDSCR_CMD_CS_SHIFT                  3
26472 #define MMDC_MDSCR_CMD_MASK                      0x70u
26473 #define MMDC_MDSCR_CMD_SHIFT                     4
26474 #define MMDC_MDSCR_CMD(x)                        (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_SHIFT))&MMDC_MDSCR_CMD_MASK)
26475 #define MMDC_MDSCR_WL_EN_MASK                    0x200u
26476 #define MMDC_MDSCR_WL_EN_SHIFT                   9
26477 #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK      0x400u
26478 #define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT     10
26479 #define MMDC_MDSCR_CON_ACK_MASK                  0x4000u
26480 #define MMDC_MDSCR_CON_ACK_SHIFT                 14
26481 #define MMDC_MDSCR_CON_REQ_MASK                  0x8000u
26482 #define MMDC_MDSCR_CON_REQ_SHIFT                 15
26483 #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK     0xFF0000u
26484 #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT    16
26485 #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x)       (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT))&MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK)
26486 #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK       0xFF000000u
26487 #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT      24
26488 #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT))&MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK)
26489 /* MDREF Bit Fields */
26490 #define MMDC_MDREF_START_REF_MASK                0x1u
26491 #define MMDC_MDREF_START_REF_SHIFT               0
26492 #define MMDC_MDREF_REFR_MASK                     0x3800u
26493 #define MMDC_MDREF_REFR_SHIFT                    11
26494 #define MMDC_MDREF_REFR(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REFR_SHIFT))&MMDC_MDREF_REFR_MASK)
26495 #define MMDC_MDREF_REF_SEL_MASK                  0xC000u
26496 #define MMDC_MDREF_REF_SEL_SHIFT                 14
26497 #define MMDC_MDREF_REF_SEL(x)                    (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REF_SEL_SHIFT))&MMDC_MDREF_REF_SEL_MASK)
26498 #define MMDC_MDREF_REF_CNT_MASK                  0xFFFF0000u
26499 #define MMDC_MDREF_REF_CNT_SHIFT                 16
26500 #define MMDC_MDREF_REF_CNT(x)                    (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REF_CNT_SHIFT))&MMDC_MDREF_REF_CNT_MASK)
26501 /* MDRWD Bit Fields */
26502 #define MMDC_MDRWD_RTR_DIFF_MASK                 0x7u
26503 #define MMDC_MDRWD_RTR_DIFF_SHIFT                0
26504 #define MMDC_MDRWD_RTR_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTR_DIFF_SHIFT))&MMDC_MDRWD_RTR_DIFF_MASK)
26505 #define MMDC_MDRWD_RTW_DIFF_MASK                 0x38u
26506 #define MMDC_MDRWD_RTW_DIFF_SHIFT                3
26507 #define MMDC_MDRWD_RTW_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTW_DIFF_SHIFT))&MMDC_MDRWD_RTW_DIFF_MASK)
26508 #define MMDC_MDRWD_WTW_DIFF_MASK                 0x1C0u
26509 #define MMDC_MDRWD_WTW_DIFF_SHIFT                6
26510 #define MMDC_MDRWD_WTW_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_WTW_DIFF_SHIFT))&MMDC_MDRWD_WTW_DIFF_MASK)
26511 #define MMDC_MDRWD_WTR_DIFF_MASK                 0xE00u
26512 #define MMDC_MDRWD_WTR_DIFF_SHIFT                9
26513 #define MMDC_MDRWD_WTR_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_WTR_DIFF_SHIFT))&MMDC_MDRWD_WTR_DIFF_MASK)
26514 #define MMDC_MDRWD_RTW_SAME_MASK                 0x7000u
26515 #define MMDC_MDRWD_RTW_SAME_SHIFT                12
26516 #define MMDC_MDRWD_RTW_SAME(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTW_SAME_SHIFT))&MMDC_MDRWD_RTW_SAME_MASK)
26517 #define MMDC_MDRWD_tDAI_MASK                     0x1FFF0000u
26518 #define MMDC_MDRWD_tDAI_SHIFT                    16
26519 #define MMDC_MDRWD_tDAI(x)                       (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_tDAI_SHIFT))&MMDC_MDRWD_tDAI_MASK)
26520 /* MDOR Bit Fields */
26521 #define MMDC_MDOR_RST_to_CKE_MASK                0x3Fu
26522 #define MMDC_MDOR_RST_to_CKE_SHIFT               0
26523 #define MMDC_MDOR_RST_to_CKE(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_RST_to_CKE_SHIFT))&MMDC_MDOR_RST_to_CKE_MASK)
26524 #define MMDC_MDOR_SDE_to_RST_MASK                0x3F00u
26525 #define MMDC_MDOR_SDE_to_RST_SHIFT               8
26526 #define MMDC_MDOR_SDE_to_RST(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_SDE_to_RST_SHIFT))&MMDC_MDOR_SDE_to_RST_MASK)
26527 #define MMDC_MDOR_tXPR_MASK                      0xFF0000u
26528 #define MMDC_MDOR_tXPR_SHIFT                     16
26529 #define MMDC_MDOR_tXPR(x)                        (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_tXPR_SHIFT))&MMDC_MDOR_tXPR_MASK)
26530 /* MDMRR Bit Fields */
26531 #define MMDC_MDMRR_MRR_READ_DATA0_MASK           0xFFu
26532 #define MMDC_MDMRR_MRR_READ_DATA0_SHIFT          0
26533 #define MMDC_MDMRR_MRR_READ_DATA0(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA0_SHIFT))&MMDC_MDMRR_MRR_READ_DATA0_MASK)
26534 #define MMDC_MDMRR_MRR_READ_DATA1_MASK           0xFF00u
26535 #define MMDC_MDMRR_MRR_READ_DATA1_SHIFT          8
26536 #define MMDC_MDMRR_MRR_READ_DATA1(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA1_SHIFT))&MMDC_MDMRR_MRR_READ_DATA1_MASK)
26537 #define MMDC_MDMRR_MRR_READ_DATA2_MASK           0xFF0000u
26538 #define MMDC_MDMRR_MRR_READ_DATA2_SHIFT          16
26539 #define MMDC_MDMRR_MRR_READ_DATA2(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA2_SHIFT))&MMDC_MDMRR_MRR_READ_DATA2_MASK)
26540 #define MMDC_MDMRR_MRR_READ_DATA3_MASK           0xFF000000u
26541 #define MMDC_MDMRR_MRR_READ_DATA3_SHIFT          24
26542 #define MMDC_MDMRR_MRR_READ_DATA3(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA3_SHIFT))&MMDC_MDMRR_MRR_READ_DATA3_MASK)
26543 /* MDCFG3LP Bit Fields */
26544 #define MMDC_MDCFG3LP_tRPab_LP_MASK              0xFu
26545 #define MMDC_MDCFG3LP_tRPab_LP_SHIFT             0
26546 #define MMDC_MDCFG3LP_tRPab_LP(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRPab_LP_SHIFT))&MMDC_MDCFG3LP_tRPab_LP_MASK)
26547 #define MMDC_MDCFG3LP_tRPpb_LP_MASK              0xF0u
26548 #define MMDC_MDCFG3LP_tRPpb_LP_SHIFT             4
26549 #define MMDC_MDCFG3LP_tRPpb_LP(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRPpb_LP_SHIFT))&MMDC_MDCFG3LP_tRPpb_LP_MASK)
26550 #define MMDC_MDCFG3LP_tRCD_LP_MASK               0xF00u
26551 #define MMDC_MDCFG3LP_tRCD_LP_SHIFT              8
26552 #define MMDC_MDCFG3LP_tRCD_LP(x)                 (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRCD_LP_SHIFT))&MMDC_MDCFG3LP_tRCD_LP_MASK)
26553 #define MMDC_MDCFG3LP_RC_LP_MASK                 0x3F0000u
26554 #define MMDC_MDCFG3LP_RC_LP_SHIFT                16
26555 #define MMDC_MDCFG3LP_RC_LP(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_RC_LP_SHIFT))&MMDC_MDCFG3LP_RC_LP_MASK)
26556 /* MDMR4 Bit Fields */
26557 #define MMDC_MDMR4_UPDATE_DE_REQ_MASK            0x1u
26558 #define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT           0
26559 #define MMDC_MDMR4_UPDATE_DE_ACK_MASK            0x2u
26560 #define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT           1
26561 #define MMDC_MDMR4_tRCD_DE_MASK                  0x10u
26562 #define MMDC_MDMR4_tRCD_DE_SHIFT                 4
26563 #define MMDC_MDMR4_tRC_DE_MASK                   0x20u
26564 #define MMDC_MDMR4_tRC_DE_SHIFT                  5
26565 #define MMDC_MDMR4_tRAS_DE_MASK                  0x40u
26566 #define MMDC_MDMR4_tRAS_DE_SHIFT                 6
26567 #define MMDC_MDMR4_tRP_DE_MASK                   0x80u
26568 #define MMDC_MDMR4_tRP_DE_SHIFT                  7
26569 #define MMDC_MDMR4_tRRD_DE_MASK                  0x100u
26570 #define MMDC_MDMR4_tRRD_DE_SHIFT                 8
26571 /* MDASP Bit Fields */
26572 #define MMDC_MDASP_CS0_END_MASK                  0x7Fu
26573 #define MMDC_MDASP_CS0_END_SHIFT                 0
26574 #define MMDC_MDASP_CS0_END(x)                    (((uint32_t)(((uint32_t)(x))<<MMDC_MDASP_CS0_END_SHIFT))&MMDC_MDASP_CS0_END_MASK)
26575 /* MAARCR Bit Fields */
26576 #define MMDC_MAARCR_ARCR_GUARD_MASK              0xFu
26577 #define MMDC_MAARCR_ARCR_GUARD_SHIFT             0
26578 #define MMDC_MAARCR_ARCR_GUARD(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_GUARD_SHIFT))&MMDC_MAARCR_ARCR_GUARD_MASK)
26579 #define MMDC_MAARCR_ARCR_DYN_MAX_MASK            0xF0u
26580 #define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT           4
26581 #define MMDC_MAARCR_ARCR_DYN_MAX(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_DYN_MAX_SHIFT))&MMDC_MAARCR_ARCR_DYN_MAX_MASK)
26582 #define MMDC_MAARCR_ARCR_DYN_JMP_MASK            0xF00u
26583 #define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT           8
26584 #define MMDC_MAARCR_ARCR_DYN_JMP(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_DYN_JMP_SHIFT))&MMDC_MAARCR_ARCR_DYN_JMP_MASK)
26585 #define MMDC_MAARCR_ARCR_ACC_HIT_MASK            0x70000u
26586 #define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT           16
26587 #define MMDC_MAARCR_ARCR_ACC_HIT(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_ACC_HIT_SHIFT))&MMDC_MAARCR_ARCR_ACC_HIT_MASK)
26588 #define MMDC_MAARCR_ARCR_PAG_HIT_MASK            0x700000u
26589 #define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT           20
26590 #define MMDC_MAARCR_ARCR_PAG_HIT(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_PAG_HIT_SHIFT))&MMDC_MAARCR_ARCR_PAG_HIT_MASK)
26591 #define MMDC_MAARCR_ARCR_RCH_EN_MASK             0x1000000u
26592 #define MMDC_MAARCR_ARCR_RCH_EN_SHIFT            24
26593 #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK         0x10000000u
26594 #define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT        28
26595 #define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK         0x40000000u
26596 #define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT        30
26597 #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK       0x80000000u
26598 #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT      31
26599 /* MAPSR Bit Fields */
26600 #define MMDC_MAPSR_PSD_MASK                      0x1u
26601 #define MMDC_MAPSR_PSD_SHIFT                     0
26602 #define MMDC_MAPSR_PSS_MASK                      0x10u
26603 #define MMDC_MAPSR_PSS_SHIFT                     4
26604 #define MMDC_MAPSR_RIS_MASK                      0x20u
26605 #define MMDC_MAPSR_RIS_SHIFT                     5
26606 #define MMDC_MAPSR_WIS_MASK                      0x40u
26607 #define MMDC_MAPSR_WIS_SHIFT                     6
26608 #define MMDC_MAPSR_PST_MASK                      0xFF00u
26609 #define MMDC_MAPSR_PST_SHIFT                     8
26610 #define MMDC_MAPSR_PST(x)                        (((uint32_t)(((uint32_t)(x))<<MMDC_MAPSR_PST_SHIFT))&MMDC_MAPSR_PST_MASK)
26611 #define MMDC_MAPSR_LPMD_MASK                     0x100000u
26612 #define MMDC_MAPSR_LPMD_SHIFT                    20
26613 #define MMDC_MAPSR_DVFS_MASK                     0x200000u
26614 #define MMDC_MAPSR_DVFS_SHIFT                    21
26615 #define MMDC_MAPSR_LPACK_MASK                    0x1000000u
26616 #define MMDC_MAPSR_LPACK_SHIFT                   24
26617 #define MMDC_MAPSR_DVACK_MASK                    0x2000000u
26618 #define MMDC_MAPSR_DVACK_SHIFT                   25
26619 /* MAEXIDR0 Bit Fields */
26620 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK       0xFFFFu
26621 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT      0
26622 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT))&MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK)
26623 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK       0xFFFF0000u
26624 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT      16
26625 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT))&MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK)
26626 /* MAEXIDR1 Bit Fields */
26627 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK       0xFFFFu
26628 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT      0
26629 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT))&MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK)
26630 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK       0xFFFF0000u
26631 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT      16
26632 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT))&MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK)
26633 /* MADPCR0 Bit Fields */
26634 #define MMDC_MADPCR0_DBG_EN_MASK                 0x1u
26635 #define MMDC_MADPCR0_DBG_EN_SHIFT                0
26636 #define MMDC_MADPCR0_DBG_RST_MASK                0x2u
26637 #define MMDC_MADPCR0_DBG_RST_SHIFT               1
26638 #define MMDC_MADPCR0_PRF_FRZ_MASK                0x4u
26639 #define MMDC_MADPCR0_PRF_FRZ_SHIFT               2
26640 #define MMDC_MADPCR0_CYC_OVF_MASK                0x8u
26641 #define MMDC_MADPCR0_CYC_OVF_SHIFT               3
26642 #define MMDC_MADPCR0_SBS_EN_MASK                 0x100u
26643 #define MMDC_MADPCR0_SBS_EN_SHIFT                8
26644 #define MMDC_MADPCR0_SBS_MASK                    0x200u
26645 #define MMDC_MADPCR0_SBS_SHIFT                   9
26646 /* MADPCR1 Bit Fields */
26647 #define MMDC_MADPCR1_PRF_AXI_ID_MASK             0xFFFFu
26648 #define MMDC_MADPCR1_PRF_AXI_ID_SHIFT            0
26649 #define MMDC_MADPCR1_PRF_AXI_ID(x)               (((uint32_t)(((uint32_t)(x))<<MMDC_MADPCR1_PRF_AXI_ID_SHIFT))&MMDC_MADPCR1_PRF_AXI_ID_MASK)
26650 #define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK        0xFFFF0000u
26651 #define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT       16
26652 #define MMDC_MADPCR1_PRF_AXI_IDMASK(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MADPCR1_PRF_AXI_ID_MASK_SHIFT))&MMDC_MADPCR1_PRF_AXI_IDMASK_MASK)
26653 /* MADPSR0 Bit Fields */
26654 #define MMDC_MADPSR0_CYC_COUNT_MASK              0xFFFFFFFFu
26655 #define MMDC_MADPSR0_CYC_COUNT_SHIFT             0
26656 #define MMDC_MADPSR0_CYC_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR0_CYC_COUNT_SHIFT))&MMDC_MADPSR0_CYC_COUNT_MASK)
26657 /* MADPSR1 Bit Fields */
26658 #define MMDC_MADPSR1_BUSY_COUNT_MASK             0xFFFFFFFFu
26659 #define MMDC_MADPSR1_BUSY_COUNT_SHIFT            0
26660 #define MMDC_MADPSR1_BUSY_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR1_BUSY_COUNT_SHIFT))&MMDC_MADPSR1_BUSY_COUNT_MASK)
26661 /* MADPSR2 Bit Fields */
26662 #define MMDC_MADPSR2_RD_ACC_COUNT_MASK           0xFFFFFFFFu
26663 #define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT          0
26664 #define MMDC_MADPSR2_RD_ACC_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR2_RD_ACC_COUNT_SHIFT))&MMDC_MADPSR2_RD_ACC_COUNT_MASK)
26665 /* MADPSR3 Bit Fields */
26666 #define MMDC_MADPSR3_WR_ACC_COUNT_MASK           0xFFFFFFFFu
26667 #define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT          0
26668 #define MMDC_MADPSR3_WR_ACC_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR3_WR_ACC_COUNT_SHIFT))&MMDC_MADPSR3_WR_ACC_COUNT_MASK)
26669 /* MADPSR4 Bit Fields */
26670 #define MMDC_MADPSR4_RD_BYTES_COUNT_MASK         0xFFFFFFFFu
26671 #define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT        0
26672 #define MMDC_MADPSR4_RD_BYTES_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT))&MMDC_MADPSR4_RD_BYTES_COUNT_MASK)
26673 /* MADPSR5 Bit Fields */
26674 #define MMDC_MADPSR5_WR_BYTES_COUNT_MASK         0xFFFFFFFFu
26675 #define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT        0
26676 #define MMDC_MADPSR5_WR_BYTES_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT))&MMDC_MADPSR5_WR_BYTES_COUNT_MASK)
26677 /* MASBS0 Bit Fields */
26678 #define MMDC_MASBS0_SBS_ADDR_MASK                0xFFFFFFFFu
26679 #define MMDC_MASBS0_SBS_ADDR_SHIFT               0
26680 #define MMDC_MASBS0_SBS_ADDR(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS0_SBS_ADDR_SHIFT))&MMDC_MASBS0_SBS_ADDR_MASK)
26681 /* MASBS1 Bit Fields */
26682 #define MMDC_MASBS1_SBS_VLD_MASK                 0x1u
26683 #define MMDC_MASBS1_SBS_VLD_SHIFT                0
26684 #define MMDC_MASBS1_SBS_TYPE_MASK                0x2u
26685 #define MMDC_MASBS1_SBS_TYPE_SHIFT               1
26686 #define MMDC_MASBS1_SBS_LOCK_MASK                0xCu
26687 #define MMDC_MASBS1_SBS_LOCK_SHIFT               2
26688 #define MMDC_MASBS1_SBS_LOCK(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_LOCK_SHIFT))&MMDC_MASBS1_SBS_LOCK_MASK)
26689 #define MMDC_MASBS1_SBS_PROT_MASK                0x70u
26690 #define MMDC_MASBS1_SBS_PROT_SHIFT               4
26691 #define MMDC_MASBS1_SBS_PROT(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_PROT_SHIFT))&MMDC_MASBS1_SBS_PROT_MASK)
26692 #define MMDC_MASBS1_SBS_SIZE_MASK                0x380u
26693 #define MMDC_MASBS1_SBS_SIZE_SHIFT               7
26694 #define MMDC_MASBS1_SBS_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_SIZE_SHIFT))&MMDC_MASBS1_SBS_SIZE_MASK)
26695 #define MMDC_MASBS1_SBS_BURST_MASK               0xC00u
26696 #define MMDC_MASBS1_SBS_BURST_SHIFT              10
26697 #define MMDC_MASBS1_SBS_BURST(x)                 (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_BURST_SHIFT))&MMDC_MASBS1_SBS_BURST_MASK)
26698 #define MMDC_MASBS1_SBS_BUFF_MASK                0x1000u
26699 #define MMDC_MASBS1_SBS_BUFF_SHIFT               12
26700 #define MMDC_MASBS1_SBS_LEN_MASK                 0xE000u
26701 #define MMDC_MASBS1_SBS_LEN_SHIFT                13
26702 #define MMDC_MASBS1_SBS_LEN(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_LEN_SHIFT))&MMDC_MASBS1_SBS_LEN_MASK)
26703 #define MMDC_MASBS1_SBS_AXI_ID_MASK              0xFFFF0000u
26704 #define MMDC_MASBS1_SBS_AXI_ID_SHIFT             16
26705 #define MMDC_MASBS1_SBS_AXI_ID(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_AXI_ID_SHIFT))&MMDC_MASBS1_SBS_AXI_ID_MASK)
26706 /* MAGENP Bit Fields */
26707 #define MMDC_MAGENP_GP31_GP0_MASK                0xFFFFFFFFu
26708 #define MMDC_MAGENP_GP31_GP0_SHIFT               0
26709 #define MMDC_MAGENP_GP31_GP0(x)                  (((uint32_t)(((uint32_t)(x))<<MMDC_MAGENP_GP31_GP0_SHIFT))&MMDC_MAGENP_GP31_GP0_MASK)
26710 /* MPZQHWCTRL Bit Fields */
26711 #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK             0x3u
26712 #define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT            0
26713 #define MMDC_MPZQHWCTRL_ZQ_MODE(x)               (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT))&MMDC_MPZQHWCTRL_ZQ_MODE_MASK)
26714 #define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK           0x3Cu
26715 #define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT          2
26716 #define MMDC_MPZQHWCTRL_ZQ_HW_PER(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK)
26717 #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK        0x7C0u
26718 #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT       6
26719 #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK)
26720 #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK        0xF800u
26721 #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT       11
26722 #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK)
26723 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK           0x10000u
26724 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT          16
26725 #define MMDC_MPZQHWCTRL_TZQ_INIT_MASK            0xE0000u
26726 #define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT           17
26727 #define MMDC_MPZQHWCTRL_TZQ_INIT(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT))&MMDC_MPZQHWCTRL_TZQ_INIT_MASK)
26728 #define MMDC_MPZQHWCTRL_TZQ_OPER_MASK            0x700000u
26729 #define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT           20
26730 #define MMDC_MPZQHWCTRL_TZQ_OPER(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT))&MMDC_MPZQHWCTRL_TZQ_OPER_MASK)
26731 #define MMDC_MPZQHWCTRL_TZQ_CS_MASK              0x3800000u
26732 #define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT             23
26733 #define MMDC_MPZQHWCTRL_TZQ_CS(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_CS_SHIFT))&MMDC_MPZQHWCTRL_TZQ_CS_MASK)
26734 #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK 0xF8000000u
26735 #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT 27
26736 #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT))&MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK)
26737 /* MPZQSWCTRL Bit Fields */
26738 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK           0x1u
26739 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT          0
26740 #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK           0x2u
26741 #define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT          1
26742 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK        0x7Cu
26743 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT       2
26744 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT))&MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK)
26745 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK        0xF80u
26746 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT       7
26747 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT))&MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK)
26748 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK            0x1000u
26749 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT           12
26750 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK       0x2000u
26751 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT      13
26752 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK      0x30000u
26753 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT     16
26754 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT))&MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK)
26755 /* MPWLGCR Bit Fields */
26756 #define MMDC_MPWLGCR_HW_WL_EN_MASK               0x1u
26757 #define MMDC_MPWLGCR_HW_WL_EN_SHIFT              0
26758 #define MMDC_MPWLGCR_SW_WL_EN_MASK               0x2u
26759 #define MMDC_MPWLGCR_SW_WL_EN_SHIFT              1
26760 #define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK           0x4u
26761 #define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT          2
26762 #define MMDC_MPWLGCR_WL_SW_RES0_MASK             0x10u
26763 #define MMDC_MPWLGCR_WL_SW_RES0_SHIFT            4
26764 #define MMDC_MPWLGCR_WL_SW_RES1_MASK             0x20u
26765 #define MMDC_MPWLGCR_WL_SW_RES1_SHIFT            5
26766 #define MMDC_MPWLGCR_WL_SW_RES2_MASK             0x40u
26767 #define MMDC_MPWLGCR_WL_SW_RES2_SHIFT            6
26768 #define MMDC_MPWLGCR_WL_SW_RES3_MASK             0x80u
26769 #define MMDC_MPWLGCR_WL_SW_RES3_SHIFT            7
26770 #define MMDC_MPWLGCR_WL_HW_ERR0_MASK             0x100u
26771 #define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT            8
26772 #define MMDC_MPWLGCR_WL_HW_ERR1_MASK             0x200u
26773 #define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT            9
26774 #define MMDC_MPWLGCR_WL_HW_ERR2_MASK             0x400u
26775 #define MMDC_MPWLGCR_WL_HW_ERR2_SHIFT            10
26776 #define MMDC_MPWLGCR_WL_HW_ERR3_MASK             0x800u
26777 #define MMDC_MPWLGCR_WL_HW_ERR3_SHIFT            11
26778 /* MPWLDECTRL0 Bit Fields */
26779 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK  0x7Fu
26780 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT 0
26781 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x)    (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT))&MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK)
26782 #define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK         0x100u
26783 #define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT        8
26784 #define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK        0x600u
26785 #define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT       9
26786 #define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT))&MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK)
26787 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK  0x7F0000u
26788 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT 16
26789 #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x)    (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT))&MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK)
26790 #define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK         0x1000000u
26791 #define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT        24
26792 #define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK        0x6000000u
26793 #define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT       25
26794 #define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT))&MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK)
26795 /* MPWLDECTRL1 Bit Fields */
26796 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK  0x7Fu
26797 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT 0
26798 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x)    (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT))&MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK)
26799 #define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK         0x100u
26800 #define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT        8
26801 #define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK        0x600u
26802 #define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT       9
26803 #define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT))&MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK)
26804 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK  0x7F0000u
26805 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT 16
26806 #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x)    (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT))&MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK)
26807 #define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK         0x1000000u
26808 #define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT        24
26809 #define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK        0x6000000u
26810 #define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT       25
26811 #define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT))&MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK)
26812 /* MPWLDLST Bit Fields */
26813 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK       0x7Fu
26814 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT      0
26815 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK)
26816 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK       0x7F00u
26817 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT      8
26818 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK)
26819 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2_MASK       0x7F0000u
26820 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2_SHIFT      16
26821 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM2_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM2_MASK)
26822 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3_MASK       0x7F000000u
26823 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3_SHIFT      24
26824 #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM3_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM3_MASK)
26825 /* MPODTCTRL Bit Fields */
26826 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK        0x1u
26827 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT       0
26828 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK        0x2u
26829 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT       1
26830 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK        0x4u
26831 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT       2
26832 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK        0x8u
26833 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT       3
26834 #define MMDC_MPODTCTRL_ODT0_INT_RES_MASK         0x70u
26835 #define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT        4
26836 #define MMDC_MPODTCTRL_ODT0_INT_RES(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT0_INT_RES_MASK)
26837 #define MMDC_MPODTCTRL_ODT1_INT_RES_MASK         0x700u
26838 #define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT        8
26839 #define MMDC_MPODTCTRL_ODT1_INT_RES(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT1_INT_RES_MASK)
26840 #define MMDC_MPODTCTRL_ODT2_INT_RES_MASK         0x7000u
26841 #define MMDC_MPODTCTRL_ODT2_INT_RES_SHIFT        12
26842 #define MMDC_MPODTCTRL_ODT2_INT_RES(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT2_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT2_INT_RES_MASK)
26843 #define MMDC_MPODTCTRL_ODT3_INT_RES_MASK         0x70000u
26844 #define MMDC_MPODTCTRL_ODT3_INT_RES_SHIFT        16
26845 #define MMDC_MPODTCTRL_ODT3_INT_RES(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT3_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT3_INT_RES_MASK)
26846 /* MPRDDQBY0DL Bit Fields */
26847 #define MMDC_MPRDDQBY0DL_rd_dq0_del_MASK         0x7u
26848 #define MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT        0
26849 #define MMDC_MPRDDQBY0DL_rd_dq0_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq0_del_MASK)
26850 #define MMDC_MPRDDQBY0DL_rd_dq1_del_MASK         0x70u
26851 #define MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT        4
26852 #define MMDC_MPRDDQBY0DL_rd_dq1_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq1_del_MASK)
26853 #define MMDC_MPRDDQBY0DL_rd_dq2_del_MASK         0x700u
26854 #define MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT        8
26855 #define MMDC_MPRDDQBY0DL_rd_dq2_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq2_del_MASK)
26856 #define MMDC_MPRDDQBY0DL_rd_dq3_del_MASK         0x7000u
26857 #define MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT        12
26858 #define MMDC_MPRDDQBY0DL_rd_dq3_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq3_del_MASK)
26859 #define MMDC_MPRDDQBY0DL_rd_dq4_del_MASK         0x70000u
26860 #define MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT        16
26861 #define MMDC_MPRDDQBY0DL_rd_dq4_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq4_del_MASK)
26862 #define MMDC_MPRDDQBY0DL_rd_dq5_del_MASK         0x700000u
26863 #define MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT        20
26864 #define MMDC_MPRDDQBY0DL_rd_dq5_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq5_del_MASK)
26865 #define MMDC_MPRDDQBY0DL_rd_dq6_del_MASK         0x7000000u
26866 #define MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT        24
26867 #define MMDC_MPRDDQBY0DL_rd_dq6_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq6_del_MASK)
26868 #define MMDC_MPRDDQBY0DL_rd_dq7_del_MASK         0x70000000u
26869 #define MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT        28
26870 #define MMDC_MPRDDQBY0DL_rd_dq7_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq7_del_MASK)
26871 /* MPRDDQBY1DL Bit Fields */
26872 #define MMDC_MPRDDQBY1DL_rd_dq8_del_MASK         0x7u
26873 #define MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT        0
26874 #define MMDC_MPRDDQBY1DL_rd_dq8_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq8_del_MASK)
26875 #define MMDC_MPRDDQBY1DL_rd_dq9_del_MASK         0x70u
26876 #define MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT        4
26877 #define MMDC_MPRDDQBY1DL_rd_dq9_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq9_del_MASK)
26878 #define MMDC_MPRDDQBY1DL_rd_dq10_del_MASK        0x700u
26879 #define MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT       8
26880 #define MMDC_MPRDDQBY1DL_rd_dq10_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq10_del_MASK)
26881 #define MMDC_MPRDDQBY1DL_rd_dq11_del_MASK        0x7000u
26882 #define MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT       12
26883 #define MMDC_MPRDDQBY1DL_rd_dq11_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq11_del_MASK)
26884 #define MMDC_MPRDDQBY1DL_rd_dq12_del_MASK        0x70000u
26885 #define MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT       16
26886 #define MMDC_MPRDDQBY1DL_rd_dq12_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq12_del_MASK)
26887 #define MMDC_MPRDDQBY1DL_rd_dq13_del_MASK        0x700000u
26888 #define MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT       20
26889 #define MMDC_MPRDDQBY1DL_rd_dq13_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq13_del_MASK)
26890 #define MMDC_MPRDDQBY1DL_rd_dq14_del_MASK        0x7000000u
26891 #define MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT       24
26892 #define MMDC_MPRDDQBY1DL_rd_dq14_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq14_del_MASK)
26893 #define MMDC_MPRDDQBY1DL_rd_dq15_del_MASK        0x70000000u
26894 #define MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT       28
26895 #define MMDC_MPRDDQBY1DL_rd_dq15_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq15_del_MASK)
26896 /* MPRDDQBY2DL Bit Fields */
26897 #define MMDC_MPRDDQBY2DL_rd_dq16_del_MASK        0x7u
26898 #define MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT       0
26899 #define MMDC_MPRDDQBY2DL_rd_dq16_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq16_del_MASK)
26900 #define MMDC_MPRDDQBY2DL_rd_dq17_del_MASK        0x70u
26901 #define MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT       4
26902 #define MMDC_MPRDDQBY2DL_rd_dq17_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq17_del_MASK)
26903 #define MMDC_MPRDDQBY2DL_rd_dq18_del_MASK        0x700u
26904 #define MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT       8
26905 #define MMDC_MPRDDQBY2DL_rd_dq18_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq18_del_MASK)
26906 #define MMDC_MPRDDQBY2DL_rd_dq19_del_MASK        0x7000u
26907 #define MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT       12
26908 #define MMDC_MPRDDQBY2DL_rd_dq19_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq19_del_MASK)
26909 #define MMDC_MPRDDQBY2DL_rd_dq20_del_MASK        0x70000u
26910 #define MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT       16
26911 #define MMDC_MPRDDQBY2DL_rd_dq20_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq20_del_MASK)
26912 #define MMDC_MPRDDQBY2DL_rd_dq21_del_MASK        0x700000u
26913 #define MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT       20
26914 #define MMDC_MPRDDQBY2DL_rd_dq21_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq21_del_MASK)
26915 #define MMDC_MPRDDQBY2DL_rd_dq22_del_MASK        0x7000000u
26916 #define MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT       24
26917 #define MMDC_MPRDDQBY2DL_rd_dq22_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq22_del_MASK)
26918 #define MMDC_MPRDDQBY2DL_rd_dq23_del_MASK        0x70000000u
26919 #define MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT       28
26920 #define MMDC_MPRDDQBY2DL_rd_dq23_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq23_del_MASK)
26921 /* MPRDDQBY3DL Bit Fields */
26922 #define MMDC_MPRDDQBY3DL_rd_dq24_del_MASK        0x7u
26923 #define MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT       0
26924 #define MMDC_MPRDDQBY3DL_rd_dq24_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq24_del_MASK)
26925 #define MMDC_MPRDDQBY3DL_rd_dq25_del_MASK        0x70u
26926 #define MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT       4
26927 #define MMDC_MPRDDQBY3DL_rd_dq25_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq25_del_MASK)
26928 #define MMDC_MPRDDQBY3DL_rd_dq26_del_MASK        0x700u
26929 #define MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT       8
26930 #define MMDC_MPRDDQBY3DL_rd_dq26_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq26_del_MASK)
26931 #define MMDC_MPRDDQBY3DL_rd_dq27_del_MASK        0x7000u
26932 #define MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT       12
26933 #define MMDC_MPRDDQBY3DL_rd_dq27_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq27_del_MASK)
26934 #define MMDC_MPRDDQBY3DL_rd_dq28_del_MASK        0x70000u
26935 #define MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT       16
26936 #define MMDC_MPRDDQBY3DL_rd_dq28_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq28_del_MASK)
26937 #define MMDC_MPRDDQBY3DL_rd_dq29_del_MASK        0x700000u
26938 #define MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT       20
26939 #define MMDC_MPRDDQBY3DL_rd_dq29_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq29_del_MASK)
26940 #define MMDC_MPRDDQBY3DL_rd_dq30_del_MASK        0x7000000u
26941 #define MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT       24
26942 #define MMDC_MPRDDQBY3DL_rd_dq30_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq30_del_MASK)
26943 #define MMDC_MPRDDQBY3DL_rd_dq31_del_MASK        0x70000000u
26944 #define MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT       28
26945 #define MMDC_MPRDDQBY3DL_rd_dq31_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq31_del_MASK)
26946 /* MPWRDQBY0DL Bit Fields */
26947 #define MMDC_MPWRDQBY0DL_wr_dq0_del_MASK         0x3u
26948 #define MMDC_MPWRDQBY0DL_wr_dq0_del_SHIFT        0
26949 #define MMDC_MPWRDQBY0DL_wr_dq0_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq0_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq0_del_MASK)
26950 #define MMDC_MPWRDQBY0DL_wr_dq1_del_MASK         0x30u
26951 #define MMDC_MPWRDQBY0DL_wr_dq1_del_SHIFT        4
26952 #define MMDC_MPWRDQBY0DL_wr_dq1_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq1_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq1_del_MASK)
26953 #define MMDC_MPWRDQBY0DL_wr_dq2_del_MASK         0x300u
26954 #define MMDC_MPWRDQBY0DL_wr_dq2_del_SHIFT        8
26955 #define MMDC_MPWRDQBY0DL_wr_dq2_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq2_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq2_del_MASK)
26956 #define MMDC_MPWRDQBY0DL_wr_dq3_del_MASK         0x3000u
26957 #define MMDC_MPWRDQBY0DL_wr_dq3_del_SHIFT        12
26958 #define MMDC_MPWRDQBY0DL_wr_dq3_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq3_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq3_del_MASK)
26959 #define MMDC_MPWRDQBY0DL_wr_dq4_del_MASK         0x30000u
26960 #define MMDC_MPWRDQBY0DL_wr_dq4_del_SHIFT        16
26961 #define MMDC_MPWRDQBY0DL_wr_dq4_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq4_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq4_del_MASK)
26962 #define MMDC_MPWRDQBY0DL_wr_dq5_del_MASK         0x300000u
26963 #define MMDC_MPWRDQBY0DL_wr_dq5_del_SHIFT        20
26964 #define MMDC_MPWRDQBY0DL_wr_dq5_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq5_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq5_del_MASK)
26965 #define MMDC_MPWRDQBY0DL_wr_dq6_del_MASK         0x3000000u
26966 #define MMDC_MPWRDQBY0DL_wr_dq6_del_SHIFT        24
26967 #define MMDC_MPWRDQBY0DL_wr_dq6_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq6_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq6_del_MASK)
26968 #define MMDC_MPWRDQBY0DL_wr_dq7_del_MASK         0x30000000u
26969 #define MMDC_MPWRDQBY0DL_wr_dq7_del_SHIFT        28
26970 #define MMDC_MPWRDQBY0DL_wr_dq7_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq7_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq7_del_MASK)
26971 #define MMDC_MPWRDQBY0DL_wr_dm0_del_MASK         0xC0000000u
26972 #define MMDC_MPWRDQBY0DL_wr_dm0_del_SHIFT        30
26973 #define MMDC_MPWRDQBY0DL_wr_dm0_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dm0_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dm0_del_MASK)
26974 /* MPWRDQBY1DL Bit Fields */
26975 #define MMDC_MPWRDQBY1DL_wr_dq8_del_MASK         0x3u
26976 #define MMDC_MPWRDQBY1DL_wr_dq8_del_SHIFT        0
26977 #define MMDC_MPWRDQBY1DL_wr_dq8_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq8_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq8_del_MASK)
26978 #define MMDC_MPWRDQBY1DL_wr_dq9_del_MASK         0x30u
26979 #define MMDC_MPWRDQBY1DL_wr_dq9_del_SHIFT        4
26980 #define MMDC_MPWRDQBY1DL_wr_dq9_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq9_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq9_del_MASK)
26981 #define MMDC_MPWRDQBY1DL_wr_dq10_del_MASK        0x300u
26982 #define MMDC_MPWRDQBY1DL_wr_dq10_del_SHIFT       8
26983 #define MMDC_MPWRDQBY1DL_wr_dq10_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq10_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq10_del_MASK)
26984 #define MMDC_MPWRDQBY1DL_wr_dq11_del_MASK        0x3000u
26985 #define MMDC_MPWRDQBY1DL_wr_dq11_del_SHIFT       12
26986 #define MMDC_MPWRDQBY1DL_wr_dq11_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq11_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq11_del_MASK)
26987 #define MMDC_MPWRDQBY1DL_wr_dq12_del_MASK        0x30000u
26988 #define MMDC_MPWRDQBY1DL_wr_dq12_del_SHIFT       16
26989 #define MMDC_MPWRDQBY1DL_wr_dq12_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq12_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq12_del_MASK)
26990 #define MMDC_MPWRDQBY1DL_wr_dq13_del_MASK        0x300000u
26991 #define MMDC_MPWRDQBY1DL_wr_dq13_del_SHIFT       20
26992 #define MMDC_MPWRDQBY1DL_wr_dq13_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq13_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq13_del_MASK)
26993 #define MMDC_MPWRDQBY1DL_wr_dq14_del_MASK        0x3000000u
26994 #define MMDC_MPWRDQBY1DL_wr_dq14_del_SHIFT       24
26995 #define MMDC_MPWRDQBY1DL_wr_dq14_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq14_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq14_del_MASK)
26996 #define MMDC_MPWRDQBY1DL_wr_dq15_del_MASK        0x30000000u
26997 #define MMDC_MPWRDQBY1DL_wr_dq15_del_SHIFT       28
26998 #define MMDC_MPWRDQBY1DL_wr_dq15_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq15_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq15_del_MASK)
26999 #define MMDC_MPWRDQBY1DL_wr_dm1_del_MASK         0xC0000000u
27000 #define MMDC_MPWRDQBY1DL_wr_dm1_del_SHIFT        30
27001 #define MMDC_MPWRDQBY1DL_wr_dm1_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dm1_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dm1_del_MASK)
27002 /* MPWRDQBY2DL Bit Fields */
27003 #define MMDC_MPWRDQBY2DL_wr_dq16_del_MASK        0x3u
27004 #define MMDC_MPWRDQBY2DL_wr_dq16_del_SHIFT       0
27005 #define MMDC_MPWRDQBY2DL_wr_dq16_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq16_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq16_del_MASK)
27006 #define MMDC_MPWRDQBY2DL_wr_dq17_del_MASK        0x30u
27007 #define MMDC_MPWRDQBY2DL_wr_dq17_del_SHIFT       4
27008 #define MMDC_MPWRDQBY2DL_wr_dq17_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq17_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq17_del_MASK)
27009 #define MMDC_MPWRDQBY2DL_wr_dq18_del_MASK        0x300u
27010 #define MMDC_MPWRDQBY2DL_wr_dq18_del_SHIFT       8
27011 #define MMDC_MPWRDQBY2DL_wr_dq18_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq18_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq18_del_MASK)
27012 #define MMDC_MPWRDQBY2DL_wr_dq19_del_MASK        0x3000u
27013 #define MMDC_MPWRDQBY2DL_wr_dq19_del_SHIFT       12
27014 #define MMDC_MPWRDQBY2DL_wr_dq19_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq19_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq19_del_MASK)
27015 #define MMDC_MPWRDQBY2DL_wr_dq20_del_MASK        0x30000u
27016 #define MMDC_MPWRDQBY2DL_wr_dq20_del_SHIFT       16
27017 #define MMDC_MPWRDQBY2DL_wr_dq20_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq20_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq20_del_MASK)
27018 #define MMDC_MPWRDQBY2DL_wr_dq21_del_MASK        0x300000u
27019 #define MMDC_MPWRDQBY2DL_wr_dq21_del_SHIFT       20
27020 #define MMDC_MPWRDQBY2DL_wr_dq21_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq21_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq21_del_MASK)
27021 #define MMDC_MPWRDQBY2DL_wr_dq22_del_MASK        0x3000000u
27022 #define MMDC_MPWRDQBY2DL_wr_dq22_del_SHIFT       24
27023 #define MMDC_MPWRDQBY2DL_wr_dq22_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq22_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq22_del_MASK)
27024 #define MMDC_MPWRDQBY2DL_wr_dq23_del_MASK        0x30000000u
27025 #define MMDC_MPWRDQBY2DL_wr_dq23_del_SHIFT       28
27026 #define MMDC_MPWRDQBY2DL_wr_dq23_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq23_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq23_del_MASK)
27027 #define MMDC_MPWRDQBY2DL_wr_dm2_del_MASK         0xC0000000u
27028 #define MMDC_MPWRDQBY2DL_wr_dm2_del_SHIFT        30
27029 #define MMDC_MPWRDQBY2DL_wr_dm2_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dm2_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dm2_del_MASK)
27030 /* MPWRDQBY3DL Bit Fields */
27031 #define MMDC_MPWRDQBY3DL_wr_dq24_del_MASK        0x3u
27032 #define MMDC_MPWRDQBY3DL_wr_dq24_del_SHIFT       0
27033 #define MMDC_MPWRDQBY3DL_wr_dq24_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq24_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq24_del_MASK)
27034 #define MMDC_MPWRDQBY3DL_wr_dq25_del_MASK        0x30u
27035 #define MMDC_MPWRDQBY3DL_wr_dq25_del_SHIFT       4
27036 #define MMDC_MPWRDQBY3DL_wr_dq25_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq25_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq25_del_MASK)
27037 #define MMDC_MPWRDQBY3DL_wr_dq26_del_MASK        0x300u
27038 #define MMDC_MPWRDQBY3DL_wr_dq26_del_SHIFT       8
27039 #define MMDC_MPWRDQBY3DL_wr_dq26_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq26_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq26_del_MASK)
27040 #define MMDC_MPWRDQBY3DL_wr_dq27_del_MASK        0x3000u
27041 #define MMDC_MPWRDQBY3DL_wr_dq27_del_SHIFT       12
27042 #define MMDC_MPWRDQBY3DL_wr_dq27_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq27_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq27_del_MASK)
27043 #define MMDC_MPWRDQBY3DL_wr_dq28_del_MASK        0x30000u
27044 #define MMDC_MPWRDQBY3DL_wr_dq28_del_SHIFT       16
27045 #define MMDC_MPWRDQBY3DL_wr_dq28_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq28_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq28_del_MASK)
27046 #define MMDC_MPWRDQBY3DL_wr_dq29_del_MASK        0x300000u
27047 #define MMDC_MPWRDQBY3DL_wr_dq29_del_SHIFT       20
27048 #define MMDC_MPWRDQBY3DL_wr_dq29_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq29_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq29_del_MASK)
27049 #define MMDC_MPWRDQBY3DL_wr_dq30_del_MASK        0x3000000u
27050 #define MMDC_MPWRDQBY3DL_wr_dq30_del_SHIFT       24
27051 #define MMDC_MPWRDQBY3DL_wr_dq30_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq30_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq30_del_MASK)
27052 #define MMDC_MPWRDQBY3DL_wr_dq31_del_MASK        0x30000000u
27053 #define MMDC_MPWRDQBY3DL_wr_dq31_del_SHIFT       28
27054 #define MMDC_MPWRDQBY3DL_wr_dq31_del(x)          (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq31_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq31_del_MASK)
27055 #define MMDC_MPWRDQBY3DL_wr_dm3_del_MASK         0xC0000000u
27056 #define MMDC_MPWRDQBY3DL_wr_dm3_del_SHIFT        30
27057 #define MMDC_MPWRDQBY3DL_wr_dm3_del(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dm3_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dm3_del_MASK)
27058 /* MPDGCTRL0 Bit Fields */
27059 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK    0x7Fu
27060 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT   0
27061 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT))&MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK)
27062 #define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK           0xF00u
27063 #define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT          8
27064 #define MMDC_MPDGCTRL0_DG_HC_DEL0(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT))&MMDC_MPDGCTRL0_DG_HC_DEL0_MASK)
27065 #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK            0x1000u
27066 #define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT           12
27067 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK    0x7F0000u
27068 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT   16
27069 #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT))&MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK)
27070 #define MMDC_MPDGCTRL0_DG_EXT_UP_MASK            0x800000u
27071 #define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT           23
27072 #define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK           0xF000000u
27073 #define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT          24
27074 #define MMDC_MPDGCTRL0_DG_HC_DEL1(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT))&MMDC_MPDGCTRL0_DG_HC_DEL1_MASK)
27075 #define MMDC_MPDGCTRL0_HW_DG_EN_MASK             0x10000000u
27076 #define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT            28
27077 #define MMDC_MPDGCTRL0_DG_DIS_MASK               0x20000000u
27078 #define MMDC_MPDGCTRL0_DG_DIS_SHIFT              29
27079 #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK           0x40000000u
27080 #define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT          30
27081 #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK          0x80000000u
27082 #define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT         31
27083 /* MPDGCTRL1 Bit Fields */
27084 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_MASK    0x7Fu
27085 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT   0
27086 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT))&MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_MASK)
27087 #define MMDC_MPDGCTRL1_DG_HC_DEL2_MASK           0xF00u
27088 #define MMDC_MPDGCTRL1_DG_HC_DEL2_SHIFT          8
27089 #define MMDC_MPDGCTRL1_DG_HC_DEL2(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_HC_DEL2_SHIFT))&MMDC_MPDGCTRL1_DG_HC_DEL2_MASK)
27090 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_MASK    0x7F0000u
27091 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT   16
27092 #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT))&MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_MASK)
27093 #define MMDC_MPDGCTRL1_DG_HC_DEL3_MASK           0xF000000u
27094 #define MMDC_MPDGCTRL1_DG_HC_DEL3_SHIFT          24
27095 #define MMDC_MPDGCTRL1_DG_HC_DEL3(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_HC_DEL3_SHIFT))&MMDC_MPDGCTRL1_DG_HC_DEL3_MASK)
27096 /* MPDGDLST0 Bit Fields */
27097 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK      0x7Fu
27098 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT     0
27099 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK)
27100 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK      0x7F00u
27101 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT     8
27102 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK)
27103 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_MASK      0x7F0000u
27104 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_SHIFT     16
27105 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_MASK)
27106 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_MASK      0x7F000000u
27107 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_SHIFT     24
27108 #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_MASK)
27109 /* MPRDDLCTL Bit Fields */
27110 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK    0x7Fu
27111 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT   0
27112 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK)
27113 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK    0x7F00u
27114 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT   8
27115 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK)
27116 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK    0x7F0000u
27117 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT   16
27118 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK)
27119 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK    0x7F000000u
27120 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT   24
27121 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK)
27122 /* MPRDDLST Bit Fields */
27123 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK       0x7Fu
27124 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT      0
27125 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK)
27126 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK       0x7F00u
27127 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT      8
27128 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK)
27129 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK       0x7F0000u
27130 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT      16
27131 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK)
27132 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK       0x7F000000u
27133 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT      24
27134 #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK)
27135 /* MPWRDLCTL Bit Fields */
27136 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK    0x7Fu
27137 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT   0
27138 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK)
27139 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK    0x7F00u
27140 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT   8
27141 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK)
27142 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK    0x7F0000u
27143 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT   16
27144 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK)
27145 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK    0x7F000000u
27146 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT   24
27147 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK)
27148 /* MPWRDLST Bit Fields */
27149 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK       0x7Fu
27150 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT      0
27151 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK)
27152 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK       0x7F00u
27153 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT      8
27154 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK)
27155 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK       0x7F0000u
27156 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT      16
27157 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK)
27158 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK       0x7F000000u
27159 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT      24
27160 #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK)
27161 /* MPSDCTRL Bit Fields */
27162 #define MMDC_MPSDCTRL_SDclk0_del_MASK            0x300u
27163 #define MMDC_MPSDCTRL_SDclk0_del_SHIFT           8
27164 #define MMDC_MPSDCTRL_SDclk0_del(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPSDCTRL_SDclk0_del_SHIFT))&MMDC_MPSDCTRL_SDclk0_del_MASK)
27165 #define MMDC_MPSDCTRL_SDCLK1_del_MASK            0xC00u
27166 #define MMDC_MPSDCTRL_SDCLK1_del_SHIFT           10
27167 #define MMDC_MPSDCTRL_SDCLK1_del(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPSDCTRL_SDCLK1_del_SHIFT))&MMDC_MPSDCTRL_SDCLK1_del_MASK)
27168 /* MPZQLP2CTL Bit Fields */
27169 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK    0x1FFu
27170 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT   0
27171 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x)      (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK)
27172 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK      0xFF0000u
27173 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT     16
27174 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK)
27175 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK      0x7F000000u
27176 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT     24
27177 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK)
27178 /* MPRDDLHWCTL Bit Fields */
27179 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK      0x1u
27180 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT     0
27181 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK      0x2u
27182 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT     1
27183 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_MASK      0x4u
27184 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_SHIFT     2
27185 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_MASK      0x8u
27186 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_SHIFT     3
27187 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK        0x10u
27188 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT       4
27189 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK   0x20u
27190 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT  5
27191 /* MPWRDLHWCTL Bit Fields */
27192 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK      0x1u
27193 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT     0
27194 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK      0x2u
27195 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT     1
27196 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_MASK      0x4u
27197 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_SHIFT     2
27198 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_MASK      0x8u
27199 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_SHIFT     3
27200 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK        0x10u
27201 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT       4
27202 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK   0x20u
27203 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT  5
27204 /* MPRDDLHWST0 Bit Fields */
27205 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK      0x7Fu
27206 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT     0
27207 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK)
27208 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK       0x7F00u
27209 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT      8
27210 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK)
27211 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK      0x7F0000u
27212 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT     16
27213 #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK)
27214 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK       0x7F000000u
27215 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT      24
27216 #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK)
27217 /* MPRDDLHWST1 Bit Fields */
27218 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK      0x7Fu
27219 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT     0
27220 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK)
27221 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK       0x7F00u
27222 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT      8
27223 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK)
27224 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK      0x7F0000u
27225 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT     16
27226 #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK)
27227 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK       0x7F000000u
27228 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT      24
27229 #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK)
27230 /* MPWRDLHWST0 Bit Fields */
27231 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK      0x7Fu
27232 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT     0
27233 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK)
27234 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK       0x7F00u
27235 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT      8
27236 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK)
27237 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK      0x7F0000u
27238 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT     16
27239 #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK)
27240 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK       0x7F000000u
27241 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT      24
27242 #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK)
27243 /* MPWRDLHWST1 Bit Fields */
27244 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK      0x7Fu
27245 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT     0
27246 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK)
27247 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK       0x7F00u
27248 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT      8
27249 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK)
27250 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK      0x7F0000u
27251 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT     16
27252 #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3(x)        (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK)
27253 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK       0x7F000000u
27254 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT      24
27255 #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK)
27256 /* MPWLHWERR Bit Fields */
27257 #define MMDC_MPWLHWERR_HW_WL0_DQ_MASK            0xFFu
27258 #define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT           0
27259 #define MMDC_MPWLHWERR_HW_WL0_DQ(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL0_DQ_MASK)
27260 #define MMDC_MPWLHWERR_HW_WL1_DQ_MASK            0xFF00u
27261 #define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT           8
27262 #define MMDC_MPWLHWERR_HW_WL1_DQ(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL1_DQ_MASK)
27263 #define MMDC_MPWLHWERR_HW_WL2_DQ_MASK            0xFF0000u
27264 #define MMDC_MPWLHWERR_HW_WL2_DQ_SHIFT           16
27265 #define MMDC_MPWLHWERR_HW_WL2_DQ(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL2_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL2_DQ_MASK)
27266 #define MMDC_MPWLHWERR_HW_WL3_DQ_MASK            0xFF000000u
27267 #define MMDC_MPWLHWERR_HW_WL3_DQ_SHIFT           24
27268 #define MMDC_MPWLHWERR_HW_WL3_DQ(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL3_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL3_DQ_MASK)
27269 /* MPDGHWST0 Bit Fields */
27270 #define MMDC_MPDGHWST0_HW_DG_LOW0_MASK           0x7FFu
27271 #define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT          0
27272 #define MMDC_MPDGHWST0_HW_DG_LOW0(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT))&MMDC_MPDGHWST0_HW_DG_LOW0_MASK)
27273 #define MMDC_MPDGHWST0_HW_DG_UP0_MASK            0x7FF0000u
27274 #define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT           16
27275 #define MMDC_MPDGHWST0_HW_DG_UP0(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST0_HW_DG_UP0_SHIFT))&MMDC_MPDGHWST0_HW_DG_UP0_MASK)
27276 /* MPDGHWST1 Bit Fields */
27277 #define MMDC_MPDGHWST1_HW_DG_LOW1_MASK           0x7FFu
27278 #define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT          0
27279 #define MMDC_MPDGHWST1_HW_DG_LOW1(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT))&MMDC_MPDGHWST1_HW_DG_LOW1_MASK)
27280 #define MMDC_MPDGHWST1_HW_DG_UP1_MASK            0x7FF0000u
27281 #define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT           16
27282 #define MMDC_MPDGHWST1_HW_DG_UP1(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST1_HW_DG_UP1_SHIFT))&MMDC_MPDGHWST1_HW_DG_UP1_MASK)
27283 /* MPDGHWST2 Bit Fields */
27284 #define MMDC_MPDGHWST2_HW_DG_LOW2_MASK           0x7FFu
27285 #define MMDC_MPDGHWST2_HW_DG_LOW2_SHIFT          0
27286 #define MMDC_MPDGHWST2_HW_DG_LOW2(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST2_HW_DG_LOW2_SHIFT))&MMDC_MPDGHWST2_HW_DG_LOW2_MASK)
27287 #define MMDC_MPDGHWST2_HW_DG_UP2_MASK            0x7FF0000u
27288 #define MMDC_MPDGHWST2_HW_DG_UP2_SHIFT           16
27289 #define MMDC_MPDGHWST2_HW_DG_UP2(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST2_HW_DG_UP2_SHIFT))&MMDC_MPDGHWST2_HW_DG_UP2_MASK)
27290 /* MPDGHWST3 Bit Fields */
27291 #define MMDC_MPDGHWST3_HW_DG_LOW3_MASK           0x7FFu
27292 #define MMDC_MPDGHWST3_HW_DG_LOW3_SHIFT          0
27293 #define MMDC_MPDGHWST3_HW_DG_LOW3(x)             (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST3_HW_DG_LOW3_SHIFT))&MMDC_MPDGHWST3_HW_DG_LOW3_MASK)
27294 #define MMDC_MPDGHWST3_HW_DG_UP3_MASK            0x7FF0000u
27295 #define MMDC_MPDGHWST3_HW_DG_UP3_SHIFT           16
27296 #define MMDC_MPDGHWST3_HW_DG_UP3(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST3_HW_DG_UP3_SHIFT))&MMDC_MPDGHWST3_HW_DG_UP3_MASK)
27297 /* MPPDCMPR1 Bit Fields */
27298 #define MMDC_MPPDCMPR1_PDV1_MASK                 0xFFFFu
27299 #define MMDC_MPPDCMPR1_PDV1_SHIFT                0
27300 #define MMDC_MPPDCMPR1_PDV1(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR1_PDV1_SHIFT))&MMDC_MPPDCMPR1_PDV1_MASK)
27301 #define MMDC_MPPDCMPR1_PDV2_MASK                 0xFFFF0000u
27302 #define MMDC_MPPDCMPR1_PDV2_SHIFT                16
27303 #define MMDC_MPPDCMPR1_PDV2(x)                   (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR1_PDV2_SHIFT))&MMDC_MPPDCMPR1_PDV2_MASK)
27304 /* MPPDCMPR2 Bit Fields */
27305 #define MMDC_MPPDCMPR2_MPR_CMP_MASK              0x1u
27306 #define MMDC_MPPDCMPR2_MPR_CMP_SHIFT             0
27307 #define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK         0x2u
27308 #define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT        1
27309 #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK   0x4u
27310 #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT  2
27311 #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK     0x7F0000u
27312 #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT    16
27313 #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x)       (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT))&MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK)
27314 #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK       0x7F000000u
27315 #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT      24
27316 #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x)         (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT))&MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK)
27317 /* MPSWDAR0 Bit Fields */
27318 #define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK           0x1u
27319 #define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT          0
27320 #define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK           0x2u
27321 #define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT          1
27322 #define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK           0x4u
27323 #define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT          2
27324 #define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK           0x8u
27325 #define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT          3
27326 #define MMDC_MPSWDAR0_SW_DUM_CMP2_MASK           0x10u
27327 #define MMDC_MPSWDAR0_SW_DUM_CMP2_SHIFT          4
27328 #define MMDC_MPSWDAR0_SW_DUM_CMP3_MASK           0x20u
27329 #define MMDC_MPSWDAR0_SW_DUM_CMP3_SHIFT          5
27330 /* MPSWDRDR0 Bit Fields */
27331 #define MMDC_MPSWDRDR0_DUM_RD0_MASK              0xFFFFFFFFu
27332 #define MMDC_MPSWDRDR0_DUM_RD0_SHIFT             0
27333 #define MMDC_MPSWDRDR0_DUM_RD0(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR0_DUM_RD0_SHIFT))&MMDC_MPSWDRDR0_DUM_RD0_MASK)
27334 /* MPSWDRDR1 Bit Fields */
27335 #define MMDC_MPSWDRDR1_DUM_RD1_MASK              0xFFFFFFFFu
27336 #define MMDC_MPSWDRDR1_DUM_RD1_SHIFT             0
27337 #define MMDC_MPSWDRDR1_DUM_RD1(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR1_DUM_RD1_SHIFT))&MMDC_MPSWDRDR1_DUM_RD1_MASK)
27338 /* MPSWDRDR2 Bit Fields */
27339 #define MMDC_MPSWDRDR2_DUM_RD2_MASK              0xFFFFFFFFu
27340 #define MMDC_MPSWDRDR2_DUM_RD2_SHIFT             0
27341 #define MMDC_MPSWDRDR2_DUM_RD2(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR2_DUM_RD2_SHIFT))&MMDC_MPSWDRDR2_DUM_RD2_MASK)
27342 /* MPSWDRDR3 Bit Fields */
27343 #define MMDC_MPSWDRDR3_DUM_RD3_MASK              0xFFFFFFFFu
27344 #define MMDC_MPSWDRDR3_DUM_RD3_SHIFT             0
27345 #define MMDC_MPSWDRDR3_DUM_RD3(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR3_DUM_RD3_SHIFT))&MMDC_MPSWDRDR3_DUM_RD3_MASK)
27346 /* MPSWDRDR4 Bit Fields */
27347 #define MMDC_MPSWDRDR4_DUM_RD4_MASK              0xFFFFFFFFu
27348 #define MMDC_MPSWDRDR4_DUM_RD4_SHIFT             0
27349 #define MMDC_MPSWDRDR4_DUM_RD4(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR4_DUM_RD4_SHIFT))&MMDC_MPSWDRDR4_DUM_RD4_MASK)
27350 /* MPSWDRDR5 Bit Fields */
27351 #define MMDC_MPSWDRDR5_DUM_RD5_MASK              0xFFFFFFFFu
27352 #define MMDC_MPSWDRDR5_DUM_RD5_SHIFT             0
27353 #define MMDC_MPSWDRDR5_DUM_RD5(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR5_DUM_RD5_SHIFT))&MMDC_MPSWDRDR5_DUM_RD5_MASK)
27354 /* MPSWDRDR6 Bit Fields */
27355 #define MMDC_MPSWDRDR6_DUM_RD6_MASK              0xFFFFFFFFu
27356 #define MMDC_MPSWDRDR6_DUM_RD6_SHIFT             0
27357 #define MMDC_MPSWDRDR6_DUM_RD6(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR6_DUM_RD6_SHIFT))&MMDC_MPSWDRDR6_DUM_RD6_MASK)
27358 /* MPSWDRDR7 Bit Fields */
27359 #define MMDC_MPSWDRDR7_DUM_RD7_MASK              0xFFFFFFFFu
27360 #define MMDC_MPSWDRDR7_DUM_RD7_SHIFT             0
27361 #define MMDC_MPSWDRDR7_DUM_RD7(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR7_DUM_RD7_SHIFT))&MMDC_MPSWDRDR7_DUM_RD7_MASK)
27362 /* MPMUR0 Bit Fields */
27363 #define MMDC_MPMUR0_MU_BYP_VAL_MASK              0x3FFu
27364 #define MMDC_MPMUR0_MU_BYP_VAL_SHIFT             0
27365 #define MMDC_MPMUR0_MU_BYP_VAL(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPMUR0_MU_BYP_VAL_SHIFT))&MMDC_MPMUR0_MU_BYP_VAL_MASK)
27366 #define MMDC_MPMUR0_MU_BYP_EN_MASK               0x400u
27367 #define MMDC_MPMUR0_MU_BYP_EN_SHIFT              10
27368 #define MMDC_MPMUR0_FRC_MSR_MASK                 0x800u
27369 #define MMDC_MPMUR0_FRC_MSR_SHIFT                11
27370 #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK         0x3FF0000u
27371 #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT        16
27372 #define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x)           (((uint32_t)(((uint32_t)(x))<<MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT))&MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK)
27373 /* MPWRCADL Bit Fields */
27374 #define MMDC_MPWRCADL_WR_CA0_DEL_MASK            0x3u
27375 #define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT           0
27376 #define MMDC_MPWRCADL_WR_CA0_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA0_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA0_DEL_MASK)
27377 #define MMDC_MPWRCADL_WR_CA1_DEL_MASK            0xCu
27378 #define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT           2
27379 #define MMDC_MPWRCADL_WR_CA1_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA1_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA1_DEL_MASK)
27380 #define MMDC_MPWRCADL_WR_CA2_DEL_MASK            0x30u
27381 #define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT           4
27382 #define MMDC_MPWRCADL_WR_CA2_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA2_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA2_DEL_MASK)
27383 #define MMDC_MPWRCADL_WR_CA3_DEL_MASK            0xC0u
27384 #define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT           6
27385 #define MMDC_MPWRCADL_WR_CA3_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA3_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA3_DEL_MASK)
27386 #define MMDC_MPWRCADL_WR_CA4_DEL_MASK            0x300u
27387 #define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT           8
27388 #define MMDC_MPWRCADL_WR_CA4_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA4_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA4_DEL_MASK)
27389 #define MMDC_MPWRCADL_WR_CA5_DEL_MASK            0xC00u
27390 #define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT           10
27391 #define MMDC_MPWRCADL_WR_CA5_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA5_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA5_DEL_MASK)
27392 #define MMDC_MPWRCADL_WR_CA6_DEL_MASK            0x3000u
27393 #define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT           12
27394 #define MMDC_MPWRCADL_WR_CA6_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA6_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA6_DEL_MASK)
27395 #define MMDC_MPWRCADL_WR_CA7_DEL_MASK            0xC000u
27396 #define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT           14
27397 #define MMDC_MPWRCADL_WR_CA7_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA7_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA7_DEL_MASK)
27398 #define MMDC_MPWRCADL_WR_CA8_DEL_MASK            0x30000u
27399 #define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT           16
27400 #define MMDC_MPWRCADL_WR_CA8_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA8_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA8_DEL_MASK)
27401 #define MMDC_MPWRCADL_WR_CA9_DEL_MASK            0xC0000u
27402 #define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT           18
27403 #define MMDC_MPWRCADL_WR_CA9_DEL(x)              (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA9_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA9_DEL_MASK)
27404 /* MPDCCR Bit Fields */
27405 #define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK          0x7u
27406 #define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT         0
27407 #define MMDC_MPDCCR_WR_DQS0_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK)
27408 #define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK          0x38u
27409 #define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT         3
27410 #define MMDC_MPDCCR_WR_DQS1_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK)
27411 #define MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK          0x1C0u
27412 #define MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT         6
27413 #define MMDC_MPDCCR_WR_DQS2_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK)
27414 #define MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK          0xE00u
27415 #define MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT         9
27416 #define MMDC_MPDCCR_WR_DQS3_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK)
27417 #define MMDC_MPDCCR_CK_FT0_DCC_MASK              0x7000u
27418 #define MMDC_MPDCCR_CK_FT0_DCC_SHIFT             12
27419 #define MMDC_MPDCCR_CK_FT0_DCC(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_CK_FT0_DCC_SHIFT))&MMDC_MPDCCR_CK_FT0_DCC_MASK)
27420 #define MMDC_MPDCCR_CK_FT1_DCC_MASK              0x70000u
27421 #define MMDC_MPDCCR_CK_FT1_DCC_SHIFT             16
27422 #define MMDC_MPDCCR_CK_FT1_DCC(x)                (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_CK_FT1_DCC_SHIFT))&MMDC_MPDCCR_CK_FT1_DCC_MASK)
27423 #define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK          0x380000u
27424 #define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT         19
27425 #define MMDC_MPDCCR_RD_DQS0_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK)
27426 #define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK          0x1C00000u
27427 #define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT         22
27428 #define MMDC_MPDCCR_RD_DQS1_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK)
27429 #define MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK          0xE000000u
27430 #define MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT         25
27431 #define MMDC_MPDCCR_RD_DQS2_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK)
27432 #define MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK          0x70000000u
27433 #define MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT         28
27434 #define MMDC_MPDCCR_RD_DQS3_FT_DCC(x)            (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK)
27435 
27436 /*!
27437  * @}
27438  */ /* end of group MMDC_Register_Masks */
27439 
27440 /* MMDC - Peripheral instance base addresses */
27441 /** Peripheral MMDC base address */
27442 #define MMDC_BASE                                (0x421B0000u)
27443 /** Peripheral MMDC base pointer */
27444 #define MMDC                                     ((MMDC_Type *)MMDC_BASE)
27445 #define MMDC_BASE_PTR                            (MMDC)
27446 /** Array initializer of MMDC peripheral base addresses */
27447 #define MMDC_BASE_ADDRS                          { MMDC_BASE }
27448 /** Array initializer of MMDC peripheral base pointers */
27449 #define MMDC_BASE_PTRS                           { MMDC }
27450 
27451 /* ----------------------------------------------------------------------------
27452    -- MMDC - Register accessor macros
27453    ---------------------------------------------------------------------------- */
27454 
27455 /*!
27456  * @addtogroup MMDC_Register_Accessor_Macros MMDC - Register accessor macros
27457  * @{
27458  */
27459 
27460 /* MMDC - Register instance definitions */
27461 /* MMDC */
27462 #define MMDC_MDCTL                               MMDC_MDCTL_REG(MMDC_BASE_PTR)
27463 #define MMDC_MDPDC                               MMDC_MDPDC_REG(MMDC_BASE_PTR)
27464 #define MMDC_MDOTC                               MMDC_MDOTC_REG(MMDC_BASE_PTR)
27465 #define MMDC_MDCFG0                              MMDC_MDCFG0_REG(MMDC_BASE_PTR)
27466 #define MMDC_MDCFG1                              MMDC_MDCFG1_REG(MMDC_BASE_PTR)
27467 #define MMDC_MDCFG2                              MMDC_MDCFG2_REG(MMDC_BASE_PTR)
27468 #define MMDC_MDMISC                              MMDC_MDMISC_REG(MMDC_BASE_PTR)
27469 #define MMDC_MDSCR                               MMDC_MDSCR_REG(MMDC_BASE_PTR)
27470 #define MMDC_MDREF                               MMDC_MDREF_REG(MMDC_BASE_PTR)
27471 #define MMDC_MDRWD                               MMDC_MDRWD_REG(MMDC_BASE_PTR)
27472 #define MMDC_MDOR                                MMDC_MDOR_REG(MMDC_BASE_PTR)
27473 #define MMDC_MDMRR                               MMDC_MDMRR_REG(MMDC_BASE_PTR)
27474 #define MMDC_MDCFG3LP                            MMDC_MDCFG3LP_REG(MMDC_BASE_PTR)
27475 #define MMDC_MDMR4                               MMDC_MDMR4_REG(MMDC_BASE_PTR)
27476 #define MMDC_MDASP                               MMDC_MDASP_REG(MMDC_BASE_PTR)
27477 #define MMDC_MAARCR                              MMDC_MAARCR_REG(MMDC_BASE_PTR)
27478 #define MMDC_MAPSR                               MMDC_MAPSR_REG(MMDC_BASE_PTR)
27479 #define MMDC_MAEXIDR0                            MMDC_MAEXIDR0_REG(MMDC_BASE_PTR)
27480 #define MMDC_MAEXIDR1                            MMDC_MAEXIDR1_REG(MMDC_BASE_PTR)
27481 #define MMDC_MADPCR0                             MMDC_MADPCR0_REG(MMDC_BASE_PTR)
27482 #define MMDC_MADPCR1                             MMDC_MADPCR1_REG(MMDC_BASE_PTR)
27483 #define MMDC_MADPSR0                             MMDC_MADPSR0_REG(MMDC_BASE_PTR)
27484 #define MMDC_MADPSR1                             MMDC_MADPSR1_REG(MMDC_BASE_PTR)
27485 #define MMDC_MADPSR2                             MMDC_MADPSR2_REG(MMDC_BASE_PTR)
27486 #define MMDC_MADPSR3                             MMDC_MADPSR3_REG(MMDC_BASE_PTR)
27487 #define MMDC_MADPSR4                             MMDC_MADPSR4_REG(MMDC_BASE_PTR)
27488 #define MMDC_MADPSR5                             MMDC_MADPSR5_REG(MMDC_BASE_PTR)
27489 #define MMDC_MASBS0                              MMDC_MASBS0_REG(MMDC_BASE_PTR)
27490 #define MMDC_MASBS1                              MMDC_MASBS1_REG(MMDC_BASE_PTR)
27491 #define MMDC_MAGENP                              MMDC_MAGENP_REG(MMDC_BASE_PTR)
27492 #define MMDC_MPZQHWCTRL                          MMDC_MPZQHWCTRL_REG(MMDC_BASE_PTR)
27493 #define MMDC_MPZQSWCTRL                          MMDC_MPZQSWCTRL_REG(MMDC_BASE_PTR)
27494 #define MMDC_MPWLGCR                             MMDC_MPWLGCR_REG(MMDC_BASE_PTR)
27495 #define MMDC_MPWLDECTRL0                         MMDC_MPWLDECTRL0_REG(MMDC_BASE_PTR)
27496 #define MMDC_MPWLDECTRL1                         MMDC_MPWLDECTRL1_REG(MMDC_BASE_PTR)
27497 #define MMDC_MPWLDLST                            MMDC_MPWLDLST_REG(MMDC_BASE_PTR)
27498 #define MMDC_MPODTCTRL                           MMDC_MPODTCTRL_REG(MMDC_BASE_PTR)
27499 #define MMDC_MPRDDQBY0DL                         MMDC_MPRDDQBY0DL_REG(MMDC_BASE_PTR)
27500 #define MMDC_MPRDDQBY1DL                         MMDC_MPRDDQBY1DL_REG(MMDC_BASE_PTR)
27501 #define MMDC_MPRDDQBY2DL                         MMDC_MPRDDQBY2DL_REG(MMDC_BASE_PTR)
27502 #define MMDC_MPRDDQBY3DL                         MMDC_MPRDDQBY3DL_REG(MMDC_BASE_PTR)
27503 #define MMDC_MPWRDQBY0DL                         MMDC_MPWRDQBY0DL_REG(MMDC_BASE_PTR)
27504 #define MMDC_MPWRDQBY1DL                         MMDC_MPWRDQBY1DL_REG(MMDC_BASE_PTR)
27505 #define MMDC_MPWRDQBY2DL                         MMDC_MPWRDQBY2DL_REG(MMDC_BASE_PTR)
27506 #define MMDC_MPWRDQBY3DL                         MMDC_MPWRDQBY3DL_REG(MMDC_BASE_PTR)
27507 #define MMDC_MPDGCTRL0                           MMDC_MPDGCTRL0_REG(MMDC_BASE_PTR)
27508 #define MMDC_MPDGCTRL1                           MMDC_MPDGCTRL1_REG(MMDC_BASE_PTR)
27509 #define MMDC_MPDGDLST0                           MMDC_MPDGDLST0_REG(MMDC_BASE_PTR)
27510 #define MMDC_MPRDDLCTL                           MMDC_MPRDDLCTL_REG(MMDC_BASE_PTR)
27511 #define MMDC_MPRDDLST                            MMDC_MPRDDLST_REG(MMDC_BASE_PTR)
27512 #define MMDC_MPWRDLCTL                           MMDC_MPWRDLCTL_REG(MMDC_BASE_PTR)
27513 #define MMDC_MPWRDLST                            MMDC_MPWRDLST_REG(MMDC_BASE_PTR)
27514 #define MMDC_MPSDCTRL                            MMDC_MPSDCTRL_REG(MMDC_BASE_PTR)
27515 #define MMDC_MPZQLP2CTL                          MMDC_MPZQLP2CTL_REG(MMDC_BASE_PTR)
27516 #define MMDC_MPRDDLHWCTL                         MMDC_MPRDDLHWCTL_REG(MMDC_BASE_PTR)
27517 #define MMDC_MPWRDLHWCTL                         MMDC_MPWRDLHWCTL_REG(MMDC_BASE_PTR)
27518 #define MMDC_MPRDDLHWST0                         MMDC_MPRDDLHWST0_REG(MMDC_BASE_PTR)
27519 #define MMDC_MPRDDLHWST1                         MMDC_MPRDDLHWST1_REG(MMDC_BASE_PTR)
27520 #define MMDC_MPWRDLHWST0                         MMDC_MPWRDLHWST0_REG(MMDC_BASE_PTR)
27521 #define MMDC_MPWRDLHWST1                         MMDC_MPWRDLHWST1_REG(MMDC_BASE_PTR)
27522 #define MMDC_MPWLHWERR                           MMDC_MPWLHWERR_REG(MMDC_BASE_PTR)
27523 #define MMDC_MPDGHWST0                           MMDC_MPDGHWST0_REG(MMDC_BASE_PTR)
27524 #define MMDC_MPDGHWST1                           MMDC_MPDGHWST1_REG(MMDC_BASE_PTR)
27525 #define MMDC_MPDGHWST2                           MMDC_MPDGHWST2_REG(MMDC_BASE_PTR)
27526 #define MMDC_MPDGHWST3                           MMDC_MPDGHWST3_REG(MMDC_BASE_PTR)
27527 #define MMDC_MPPDCMPR1                           MMDC_MPPDCMPR1_REG(MMDC_BASE_PTR)
27528 #define MMDC_MPPDCMPR2                           MMDC_MPPDCMPR2_REG(MMDC_BASE_PTR)
27529 #define MMDC_MPSWDAR0                            MMDC_MPSWDAR0_REG(MMDC_BASE_PTR)
27530 #define MMDC_MPSWDRDR0                           MMDC_MPSWDRDR0_REG(MMDC_BASE_PTR)
27531 #define MMDC_MPSWDRDR1                           MMDC_MPSWDRDR1_REG(MMDC_BASE_PTR)
27532 #define MMDC_MPSWDRDR2                           MMDC_MPSWDRDR2_REG(MMDC_BASE_PTR)
27533 #define MMDC_MPSWDRDR3                           MMDC_MPSWDRDR3_REG(MMDC_BASE_PTR)
27534 #define MMDC_MPSWDRDR4                           MMDC_MPSWDRDR4_REG(MMDC_BASE_PTR)
27535 #define MMDC_MPSWDRDR5                           MMDC_MPSWDRDR5_REG(MMDC_BASE_PTR)
27536 #define MMDC_MPSWDRDR6                           MMDC_MPSWDRDR6_REG(MMDC_BASE_PTR)
27537 #define MMDC_MPSWDRDR7                           MMDC_MPSWDRDR7_REG(MMDC_BASE_PTR)
27538 #define MMDC_MPMUR0                              MMDC_MPMUR0_REG(MMDC_BASE_PTR)
27539 #define MMDC_MPWRCADL                            MMDC_MPWRCADL_REG(MMDC_BASE_PTR)
27540 #define MMDC_MPDCCR                              MMDC_MPDCCR_REG(MMDC_BASE_PTR)
27541 
27542 /*!
27543  * @}
27544  */ /* end of group MMDC_Register_Accessor_Macros */
27545 
27546 /*!
27547  * @}
27548  */ /* end of group MMDC_Peripheral */
27549 
27550 /* ----------------------------------------------------------------------------
27551    -- MU Peripheral Access Layer
27552    ---------------------------------------------------------------------------- */
27553 
27554 /*!
27555  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
27556  * @{
27557  */
27558 
27559 /** MU - Register Layout Typedef */
27560 typedef struct {
27561   __IO  uint32_t TR[4];                                  /**< Processor B Transmit Register 0, array offset: 0x0, array step: 0x4 */
27562   __I   uint32_t RR[4];                                  /**< Processor B Receive Register 0, array offset: 0x10, array step: 0x4 */
27563   __IO  uint32_t SR;                                     /**< Processor b Status Register, offset: 0x20 */
27564   __IO  uint32_t CR;                                     /**< Processor B Control Register, offset: 0x24 */
27565 } MU_Type, *MU_MemMapPtr;
27566 
27567 /* ----------------------------------------------------------------------------
27568    -- MU - Register accessor macros
27569    ---------------------------------------------------------------------------- */
27570 
27571 /*!
27572  * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros
27573  * @{
27574  */
27575 
27576 /* MU - Register accessors */
27577 #define MU_TR_REG(base,index)                    ((base)->TR[index])
27578 #define MU_TR_COUNT                              4
27579 #define MU_RR_REG(base,index)                    ((base)->RR[index])
27580 #define MU_RR_COUNT                              4
27581 #define MU_SR_REG(base)                          ((base)->SR)
27582 #define MU_CR_REG(base)                          ((base)->CR)
27583 
27584 /*!
27585  * @}
27586  */ /* end of group MU_Register_Accessor_Macros */
27587 
27588 /* ----------------------------------------------------------------------------
27589    -- MU Register Masks
27590    ---------------------------------------------------------------------------- */
27591 
27592 /*!
27593  * @addtogroup MU_Register_Masks MU Register Masks
27594  * @{
27595  */
27596 
27597 /* TR Bit Fields */
27598 #define MU_TR_TR0_MASK                           0xFFFFFFFFu
27599 #define MU_TR_TR0_SHIFT                          0
27600 #define MU_TR_TR0(x)                             (((uint32_t)(((uint32_t)(x))<<MU_TR_TR0_SHIFT))&MU_TR_TR0_MASK)
27601 /* RR Bit Fields */
27602 #define MU_RR_RR0_MASK                           0xFFFFFFFFu
27603 #define MU_RR_RR0_SHIFT                          0
27604 #define MU_RR_RR0(x)                             (((uint32_t)(((uint32_t)(x))<<MU_RR_RR0_SHIFT))&MU_RR_RR0_MASK)
27605 /* SR Bit Fields */
27606 #define MU_SR_Fn_MASK                            0x7u
27607 #define MU_SR_Fn_SHIFT                           0
27608 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x))<<MU_SR_Fn_SHIFT))&MU_SR_Fn_MASK)
27609 #define MU_SR_EP_MASK                            0x10u
27610 #define MU_SR_EP_SHIFT                           4
27611 #define MU_SR_PM_MASK                            0x60u
27612 #define MU_SR_PM_SHIFT                           5
27613 #define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x))<<MU_SR_PM_SHIFT))&MU_SR_PM_MASK)
27614 #define MU_SR_RS_MASK                            0x80u
27615 #define MU_SR_RS_SHIFT                           7
27616 #define MU_SR_FUP_MASK                           0x100u
27617 #define MU_SR_FUP_SHIFT                          8
27618 #define MU_SR_TEn_MASK                           0xF00000u
27619 #define MU_SR_TEn_SHIFT                          20
27620 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x))<<MU_SR_TEn_SHIFT))&MU_SR_TEn_MASK)
27621 #define MU_SR_RFn_MASK                           0xF000000u
27622 #define MU_SR_RFn_SHIFT                          24
27623 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x))<<MU_SR_RFn_SHIFT))&MU_SR_RFn_MASK)
27624 #define MU_SR_GIPn_MASK                          0xF0000000u
27625 #define MU_SR_GIPn_SHIFT                         28
27626 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_SR_GIPn_SHIFT))&MU_SR_GIPn_MASK)
27627 /* CR Bit Fields */
27628 #define MU_CR_Fn_MASK                            0x7u
27629 #define MU_CR_Fn_SHIFT                           0
27630 #define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x))<<MU_CR_Fn_SHIFT))&MU_CR_Fn_MASK)
27631 #define MU_CR_GIRn_MASK                          0xF0000u
27632 #define MU_CR_GIRn_SHIFT                         16
27633 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_GIRn_SHIFT))&MU_CR_GIRn_MASK)
27634 #define MU_CR_TIEn_MASK                          0xF00000u
27635 #define MU_CR_TIEn_SHIFT                         20
27636 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_TIEn_SHIFT))&MU_CR_TIEn_MASK)
27637 #define MU_CR_RIEn_MASK                          0xF000000u
27638 #define MU_CR_RIEn_SHIFT                         24
27639 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_RIEn_SHIFT))&MU_CR_RIEn_MASK)
27640 #define MU_CR_GIEn_MASK                          0xF0000000u
27641 #define MU_CR_GIEn_SHIFT                         28
27642 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x))<<MU_CR_GIEn_SHIFT))&MU_CR_GIEn_MASK)
27643 
27644 /*!
27645  * @}
27646  */ /* end of group MU_Register_Masks */
27647 
27648 /* MU - Peripheral instance base addresses */
27649 /** Peripheral MUB base address */
27650 #define MUB_BASE                                 (0x4229C000u)
27651 /** Peripheral MUB  base pointer */
27652 #define MUB                                      ((MU_Type *)MUB_BASE)
27653 #define MUB_BASE_PTR                             (MUB)
27654 /** Array initializer of MU peripheral base addresses */
27655 #define MU_BASE_ADDRS                            { MUB_BASE }
27656 /** Array initializer of MU peripheral base pointers */
27657 #define MU_BASE_PTRS                             { MUB }
27658 /** Interrupt vectors for the MU peripheral type */
27659 #define MU_IRQS                                  { MU_M4_IRQn }
27660 
27661 /* ----------------------------------------------------------------------------
27662    -- MU - Register accessor macros
27663    ---------------------------------------------------------------------------- */
27664 
27665 /*!
27666  * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros
27667  * @{
27668  */
27669 
27670 /* MU - Register instance definitions */
27671 /* MUB */
27672 #define MUB_TR0                                  MU_TR_REG(MUB_BASE_PTR,0)
27673 #define MUB_TR1                                  MU_TR_REG(MUB_BASE_PTR,1)
27674 #define MUB_TR2                                  MU_TR_REG(MUB_BASE_PTR,2)
27675 #define MUB_TR3                                  MU_TR_REG(MUB_BASE_PTR,3)
27676 #define MUB_RR0                                  MU_RR_REG(MUB_BASE_PTR,0)
27677 #define MUB_RR1                                  MU_RR_REG(MUB_BASE_PTR,1)
27678 #define MUB_RR2                                  MU_RR_REG(MUB_BASE_PTR,2)
27679 #define MUB_RR3                                  MU_RR_REG(MUB_BASE_PTR,3)
27680 #define MUB_SR                                   MU_SR_REG(MUB_BASE_PTR)
27681 #define MUB_CR                                   MU_CR_REG(MUB_BASE_PTR)
27682 /* MU - Register array accessors */
27683 #define MUB_TR(index)                            MU_TR_REG(MUB_BASE_PTR,index)
27684 #define MUB_RR(index)                            MU_RR_REG(MUB_BASE_PTR,index)
27685 
27686 /*!
27687  * @}
27688  */ /* end of group MU_Register_Accessor_Macros */
27689 
27690 /*!
27691  * @}
27692  */ /* end of group MU_Peripheral */
27693 
27694 /* ----------------------------------------------------------------------------
27695    -- OCOTP Peripheral Access Layer
27696    ---------------------------------------------------------------------------- */
27697 
27698 /*!
27699  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
27700  * @{
27701  */
27702 
27703 /** OCOTP - Register Layout Typedef */
27704 typedef struct {
27705   __IO  uint32_t CTRL;                                   /**< OTP Controller Control Register, offset: 0x0 */
27706   __IO  uint32_t CTRL_SET;                               /**< OTP Controller Control Register, offset: 0x4 */
27707   __IO  uint32_t CTRL_CLR;                               /**< OTP Controller Control Register, offset: 0x8 */
27708   __IO  uint32_t CTRL_TOG;                               /**< OTP Controller Control Register, offset: 0xC */
27709   __IO  uint32_t TIMING;                                 /**< OTP Controller Timing Register, offset: 0x10 */
27710   uint8_t RESERVED_0[12];
27711   __IO  uint32_t DATA;                                   /**< OTP Controller Write Data Register, offset: 0x20 */
27712   uint8_t RESERVED_1[12];
27713   __IO  uint32_t READ_CTRL;                              /**< OTP Controller Write Data Register, offset: 0x30 */
27714   uint8_t RESERVED_2[12];
27715   __IO  uint32_t READ_FUSE_DATA;                         /**< OTP Controller Read Data Register, offset: 0x40 */
27716   uint8_t RESERVED_3[12];
27717   __IO  uint32_t SW_STICKY;                              /**< Sticky bit Register, offset: 0x50 */
27718   uint8_t RESERVED_4[12];
27719   __IO  uint32_t SCS;                                    /**< Software Controllable Signals Register, offset: 0x60 */
27720   __IO  uint32_t SCS_SET;                                /**< Software Controllable Signals Register, offset: 0x64 */
27721   __IO  uint32_t SCS_CLR;                                /**< Software Controllable Signals Register, offset: 0x68 */
27722   __IO  uint32_t SCS_TOG;                                /**< Software Controllable Signals Register, offset: 0x6C */
27723   uint8_t RESERVED_5[32];
27724   __I   uint32_t VERSION;                                /**< OTP Controller Version Register, offset: 0x90 */
27725   uint8_t RESERVED_6[876];
27726   __I   uint32_t LOCK;                                   /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
27727   uint8_t RESERVED_7[12];
27728   __IO  uint32_t CFG0;                                   /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */
27729   uint8_t RESERVED_8[12];
27730   __IO  uint32_t CFG1;                                   /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */
27731   uint8_t RESERVED_9[12];
27732   __IO  uint32_t CFG2;                                   /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */
27733   uint8_t RESERVED_10[12];
27734   __IO  uint32_t CFG3;                                   /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */
27735   uint8_t RESERVED_11[12];
27736   __IO  uint32_t CFG4;                                   /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */
27737   uint8_t RESERVED_12[12];
27738   __IO  uint32_t CFG5;                                   /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */
27739   uint8_t RESERVED_13[12];
27740   __IO  uint32_t CFG6;                                   /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */
27741   uint8_t RESERVED_14[12];
27742   __IO  uint32_t MEM0;                                   /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */
27743   uint8_t RESERVED_15[12];
27744   __IO  uint32_t MEM1;                                   /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */
27745   uint8_t RESERVED_16[12];
27746   __IO  uint32_t MEM2;                                   /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */
27747   uint8_t RESERVED_17[12];
27748   __IO  uint32_t MEM3;                                   /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */
27749   uint8_t RESERVED_18[12];
27750   __IO  uint32_t MEM4;                                   /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */
27751   uint8_t RESERVED_19[12];
27752   __IO  uint32_t ANA0;                                   /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */
27753   uint8_t RESERVED_20[12];
27754   __IO  uint32_t ANA1;                                   /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */
27755   uint8_t RESERVED_21[12];
27756   __IO  uint32_t ANA2;                                   /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */
27757   uint8_t RESERVED_22[140];
27758   __IO  uint32_t SRK0;                                   /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */
27759   uint8_t RESERVED_23[12];
27760   __IO  uint32_t SRK1;                                   /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */
27761   uint8_t RESERVED_24[12];
27762   __IO  uint32_t SRK2;                                   /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */
27763   uint8_t RESERVED_25[12];
27764   __IO  uint32_t SRK3;                                   /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */
27765   uint8_t RESERVED_26[12];
27766   __IO  uint32_t SRK4;                                   /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */
27767   uint8_t RESERVED_27[12];
27768   __IO  uint32_t SRK5;                                   /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */
27769   uint8_t RESERVED_28[12];
27770   __IO  uint32_t SRK6;                                   /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */
27771   uint8_t RESERVED_29[12];
27772   __IO  uint32_t SRK7;                                   /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */
27773   uint8_t RESERVED_30[12];
27774   __IO  uint32_t RESP0;                                  /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */
27775   uint8_t RESERVED_31[12];
27776   __IO  uint32_t HSJC_RESP1;                             /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */
27777   uint8_t RESERVED_32[12];
27778   __IO  uint32_t MAC0;                                   /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */
27779   uint8_t RESERVED_33[12];
27780   __IO  uint32_t MAC1;                                   /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */
27781   uint8_t RESERVED_34[12];
27782   __IO  uint32_t MAC2;                                   /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */
27783   uint8_t RESERVED_35[28];
27784   __IO  uint32_t GP1;                                    /**< Value of OTP Bank4 Word6 (HW Capabilities), offset: 0x660 */
27785   uint8_t RESERVED_36[12];
27786   __IO  uint32_t GP2;                                    /**< Value of OTP Bank4 Word7 (HW Capabilities), offset: 0x670 */
27787   uint8_t RESERVED_37[92];
27788   __IO  uint32_t MISC_CONF;                              /**< Value of OTP Bank5 Word5 (HW Capabilities), offset: 0x6D0 */
27789   uint8_t RESERVED_38[12];
27790   __IO  uint32_t FIELD_RETURN;                           /**< Value of OTP Bank5 Word6 (HW Capabilities), offset: 0x6E0 */
27791   uint8_t RESERVED_39[12];
27792   __IO  uint32_t SRK_REVOKE;                             /**< Value of OTP Bank5 Word7 (HW Capabilities), offset: 0x6F0 */
27793   uint8_t RESERVED_40[796];
27794   __IO  uint32_t GP30;                                   /**< Value of OTP Bank10 Word1 (General Purpose Customer Defined Info), offset: 0xA10 */
27795   uint8_t RESERVED_41[12];
27796   __IO  uint32_t GP31;                                   /**< Value of OTP Bank10 Word2 (General Purpose Customer Defined Info), offset: 0xA20 */
27797   uint8_t RESERVED_42[12];
27798   __IO  uint32_t GP32;                                   /**< Value of OTP Bank10 Word3 (General Purpose Customer Defined Info), offset: 0xA30 */
27799   uint8_t RESERVED_43[12];
27800   __IO  uint32_t GP33;                                   /**< Value of OTP Bank10 Word4 (General Purpose Customer Defined Info), offset: 0xA40 */
27801   uint8_t RESERVED_44[12];
27802   __IO  uint32_t GP34;                                   /**< Value of OTP Bank10 Word5 (General Purpose Customer Defined Info), offset: 0xA50 */
27803   uint8_t RESERVED_45[12];
27804   __IO  uint32_t GP35;                                   /**< Value of OTP Bank10 Word6 (General Purpose Customer Defined Info), offset: 0xA60 */
27805   uint8_t RESERVED_46[12];
27806   __IO  uint32_t GP36;                                   /**< Value of OTP Bank10 Word7 (General Purpose Customer Defined Info), offset: 0xA70 */
27807 } OCOTP_Type, *OCOTP_MemMapPtr;
27808 
27809 /* ----------------------------------------------------------------------------
27810    -- OCOTP - Register accessor macros
27811    ---------------------------------------------------------------------------- */
27812 
27813 /*!
27814  * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros
27815  * @{
27816  */
27817 
27818 /* OCOTP - Register accessors */
27819 #define OCOTP_CTRL_REG(base)                     ((base)->CTRL)
27820 #define OCOTP_CTRL_SET_REG(base)                 ((base)->CTRL_SET)
27821 #define OCOTP_CTRL_CLR_REG(base)                 ((base)->CTRL_CLR)
27822 #define OCOTP_CTRL_TOG_REG(base)                 ((base)->CTRL_TOG)
27823 #define OCOTP_TIMING_REG(base)                   ((base)->TIMING)
27824 #define OCOTP_DATA_REG(base)                     ((base)->DATA)
27825 #define OCOTP_READ_CTRL_REG(base)                ((base)->READ_CTRL)
27826 #define OCOTP_READ_FUSE_DATA_REG(base)           ((base)->READ_FUSE_DATA)
27827 #define OCOTP_SW_STICKY_REG(base)                ((base)->SW_STICKY)
27828 #define OCOTP_SCS_REG(base)                      ((base)->SCS)
27829 #define OCOTP_SCS_SET_REG(base)                  ((base)->SCS_SET)
27830 #define OCOTP_SCS_CLR_REG(base)                  ((base)->SCS_CLR)
27831 #define OCOTP_SCS_TOG_REG(base)                  ((base)->SCS_TOG)
27832 #define OCOTP_VERSION_REG(base)                  ((base)->VERSION)
27833 #define OCOTP_LOCK_REG(base)                     ((base)->LOCK)
27834 #define OCOTP_CFG0_REG(base)                     ((base)->CFG0)
27835 #define OCOTP_CFG1_REG(base)                     ((base)->CFG1)
27836 #define OCOTP_CFG2_REG(base)                     ((base)->CFG2)
27837 #define OCOTP_CFG3_REG(base)                     ((base)->CFG3)
27838 #define OCOTP_CFG4_REG(base)                     ((base)->CFG4)
27839 #define OCOTP_CFG5_REG(base)                     ((base)->CFG5)
27840 #define OCOTP_CFG6_REG(base)                     ((base)->CFG6)
27841 #define OCOTP_MEM0_REG(base)                     ((base)->MEM0)
27842 #define OCOTP_MEM1_REG(base)                     ((base)->MEM1)
27843 #define OCOTP_MEM2_REG(base)                     ((base)->MEM2)
27844 #define OCOTP_MEM3_REG(base)                     ((base)->MEM3)
27845 #define OCOTP_MEM4_REG(base)                     ((base)->MEM4)
27846 #define OCOTP_ANA0_REG(base)                     ((base)->ANA0)
27847 #define OCOTP_ANA1_REG(base)                     ((base)->ANA1)
27848 #define OCOTP_ANA2_REG(base)                     ((base)->ANA2)
27849 #define OCOTP_SRK0_REG(base)                     ((base)->SRK0)
27850 #define OCOTP_SRK1_REG(base)                     ((base)->SRK1)
27851 #define OCOTP_SRK2_REG(base)                     ((base)->SRK2)
27852 #define OCOTP_SRK3_REG(base)                     ((base)->SRK3)
27853 #define OCOTP_SRK4_REG(base)                     ((base)->SRK4)
27854 #define OCOTP_SRK5_REG(base)                     ((base)->SRK5)
27855 #define OCOTP_SRK6_REG(base)                     ((base)->SRK6)
27856 #define OCOTP_SRK7_REG(base)                     ((base)->SRK7)
27857 #define OCOTP_RESP0_REG(base)                    ((base)->RESP0)
27858 #define OCOTP_HSJC_RESP1_REG(base)               ((base)->HSJC_RESP1)
27859 #define OCOTP_MAC0_REG(base)                     ((base)->MAC0)
27860 #define OCOTP_MAC1_REG(base)                     ((base)->MAC1)
27861 #define OCOTP_MAC2_REG(base)                     ((base)->MAC2)
27862 #define OCOTP_GP1_REG(base)                      ((base)->GP1)
27863 #define OCOTP_GP2_REG(base)                      ((base)->GP2)
27864 #define OCOTP_MISC_CONF_REG(base)                ((base)->MISC_CONF)
27865 #define OCOTP_FIELD_RETURN_REG(base)             ((base)->FIELD_RETURN)
27866 #define OCOTP_SRK_REVOKE_REG(base)               ((base)->SRK_REVOKE)
27867 #define OCOTP_GP30_REG(base)                     ((base)->GP30)
27868 #define OCOTP_GP31_REG(base)                     ((base)->GP31)
27869 #define OCOTP_GP32_REG(base)                     ((base)->GP32)
27870 #define OCOTP_GP33_REG(base)                     ((base)->GP33)
27871 #define OCOTP_GP34_REG(base)                     ((base)->GP34)
27872 #define OCOTP_GP35_REG(base)                     ((base)->GP35)
27873 #define OCOTP_GP36_REG(base)                     ((base)->GP36)
27874 
27875 /*!
27876  * @}
27877  */ /* end of group OCOTP_Register_Accessor_Macros */
27878 
27879 /* ----------------------------------------------------------------------------
27880    -- OCOTP Register Masks
27881    ---------------------------------------------------------------------------- */
27882 
27883 /*!
27884  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
27885  * @{
27886  */
27887 
27888 /* CTRL Bit Fields */
27889 #define OCOTP_CTRL_ADDR_MASK                     0x7Fu
27890 #define OCOTP_CTRL_ADDR_SHIFT                    0
27891 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_ADDR_SHIFT))&OCOTP_CTRL_ADDR_MASK)
27892 #define OCOTP_CTRL_BUSY_MASK                     0x100u
27893 #define OCOTP_CTRL_BUSY_SHIFT                    8
27894 #define OCOTP_CTRL_ERROR_MASK                    0x200u
27895 #define OCOTP_CTRL_ERROR_SHIFT                   9
27896 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           0x400u
27897 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          10
27898 #define OCOTP_CTRL_WR_UNLOCK_MASK                0xFFFF0000u
27899 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               16
27900 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_WR_UNLOCK_SHIFT))&OCOTP_CTRL_WR_UNLOCK_MASK)
27901 /* CTRL_SET Bit Fields */
27902 #define OCOTP_CTRL_SET_ADDR_MASK                 0x7Fu
27903 #define OCOTP_CTRL_SET_ADDR_SHIFT                0
27904 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_ADDR_SHIFT))&OCOTP_CTRL_SET_ADDR_MASK)
27905 #define OCOTP_CTRL_SET_BUSY_MASK                 0x100u
27906 #define OCOTP_CTRL_SET_BUSY_SHIFT                8
27907 #define OCOTP_CTRL_SET_ERROR_MASK                0x200u
27908 #define OCOTP_CTRL_SET_ERROR_SHIFT               9
27909 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       0x400u
27910 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      10
27911 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            0xFFFF0000u
27912 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           16
27913 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_WR_UNLOCK_SHIFT))&OCOTP_CTRL_SET_WR_UNLOCK_MASK)
27914 /* CTRL_CLR Bit Fields */
27915 #define OCOTP_CTRL_CLR_ADDR_MASK                 0x7Fu
27916 #define OCOTP_CTRL_CLR_ADDR_SHIFT                0
27917 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_ADDR_SHIFT))&OCOTP_CTRL_CLR_ADDR_MASK)
27918 #define OCOTP_CTRL_CLR_BUSY_MASK                 0x100u
27919 #define OCOTP_CTRL_CLR_BUSY_SHIFT                8
27920 #define OCOTP_CTRL_CLR_ERROR_MASK                0x200u
27921 #define OCOTP_CTRL_CLR_ERROR_SHIFT               9
27922 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       0x400u
27923 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      10
27924 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            0xFFFF0000u
27925 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           16
27926 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT))&OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
27927 /* CTRL_TOG Bit Fields */
27928 #define OCOTP_CTRL_TOG_ADDR_MASK                 0x7Fu
27929 #define OCOTP_CTRL_TOG_ADDR_SHIFT                0
27930 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_ADDR_SHIFT))&OCOTP_CTRL_TOG_ADDR_MASK)
27931 #define OCOTP_CTRL_TOG_BUSY_MASK                 0x100u
27932 #define OCOTP_CTRL_TOG_BUSY_SHIFT                8
27933 #define OCOTP_CTRL_TOG_ERROR_MASK                0x200u
27934 #define OCOTP_CTRL_TOG_ERROR_SHIFT               9
27935 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       0x400u
27936 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      10
27937 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            0xFFFF0000u
27938 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           16
27939 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT))&OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
27940 /* TIMING Bit Fields */
27941 #define OCOTP_TIMING_STROBE_PROG_MASK            0xFFFu
27942 #define OCOTP_TIMING_STROBE_PROG_SHIFT           0
27943 #define OCOTP_TIMING_STROBE_PROG(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_PROG_SHIFT))&OCOTP_TIMING_STROBE_PROG_MASK)
27944 #define OCOTP_TIMING_RELAX_MASK                  0xF000u
27945 #define OCOTP_TIMING_RELAX_SHIFT                 12
27946 #define OCOTP_TIMING_RELAX(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RELAX_SHIFT))&OCOTP_TIMING_RELAX_MASK)
27947 #define OCOTP_TIMING_STROBE_READ_MASK            0x3F0000u
27948 #define OCOTP_TIMING_STROBE_READ_SHIFT           16
27949 #define OCOTP_TIMING_STROBE_READ(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_READ_SHIFT))&OCOTP_TIMING_STROBE_READ_MASK)
27950 #define OCOTP_TIMING_WAIT_MASK                   0xFC00000u
27951 #define OCOTP_TIMING_WAIT_SHIFT                  22
27952 #define OCOTP_TIMING_WAIT(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_WAIT_SHIFT))&OCOTP_TIMING_WAIT_MASK)
27953 /* DATA Bit Fields */
27954 #define OCOTP_DATA_DATA_MASK                     0xFFFFFFFFu
27955 #define OCOTP_DATA_DATA_SHIFT                    0
27956 #define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA_DATA_SHIFT))&OCOTP_DATA_DATA_MASK)
27957 /* READ_CTRL Bit Fields */
27958 #define OCOTP_READ_CTRL_READ_FUSE_MASK           0x1u
27959 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          0
27960 /* READ_FUSE_DATA Bit Fields */
27961 #define OCOTP_READ_FUSE_DATA_DATA_MASK           0xFFFFFFFFu
27962 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT          0
27963 #define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA_DATA_SHIFT))&OCOTP_READ_FUSE_DATA_DATA_MASK)
27964 /* SW_STICKY Bit Fields */
27965 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK      0x1u
27966 #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT     0
27967 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK     0x2u
27968 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT    1
27969 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK   0x4u
27970 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT  2
27971 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK      0x8u
27972 #define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT     3
27973 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK  0x10u
27974 #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT 4
27975 /* SCS Bit Fields */
27976 #define OCOTP_SCS_HAB_JDE_MASK                   0x1u
27977 #define OCOTP_SCS_HAB_JDE_SHIFT                  0
27978 #define OCOTP_SCS_SPARE_MASK                     0x7FFFFFFEu
27979 #define OCOTP_SCS_SPARE_SHIFT                    1
27980 #define OCOTP_SCS_SPARE(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SPARE_SHIFT))&OCOTP_SCS_SPARE_MASK)
27981 #define OCOTP_SCS_LOCK_MASK                      0x80000000u
27982 #define OCOTP_SCS_LOCK_SHIFT                     31
27983 /* SCS_SET Bit Fields */
27984 #define OCOTP_SCS_SET_HAB_JDE_MASK               0x1u
27985 #define OCOTP_SCS_SET_HAB_JDE_SHIFT              0
27986 #define OCOTP_SCS_SET_SPARE_MASK                 0x7FFFFFFEu
27987 #define OCOTP_SCS_SET_SPARE_SHIFT                1
27988 #define OCOTP_SCS_SET_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SET_SPARE_SHIFT))&OCOTP_SCS_SET_SPARE_MASK)
27989 #define OCOTP_SCS_SET_LOCK_MASK                  0x80000000u
27990 #define OCOTP_SCS_SET_LOCK_SHIFT                 31
27991 /* SCS_CLR Bit Fields */
27992 #define OCOTP_SCS_CLR_HAB_JDE_MASK               0x1u
27993 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT              0
27994 #define OCOTP_SCS_CLR_SPARE_MASK                 0x7FFFFFFEu
27995 #define OCOTP_SCS_CLR_SPARE_SHIFT                1
27996 #define OCOTP_SCS_CLR_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_CLR_SPARE_SHIFT))&OCOTP_SCS_CLR_SPARE_MASK)
27997 #define OCOTP_SCS_CLR_LOCK_MASK                  0x80000000u
27998 #define OCOTP_SCS_CLR_LOCK_SHIFT                 31
27999 /* SCS_TOG Bit Fields */
28000 #define OCOTP_SCS_TOG_HAB_JDE_MASK               0x1u
28001 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT              0
28002 #define OCOTP_SCS_TOG_SPARE_MASK                 0x7FFFFFFEu
28003 #define OCOTP_SCS_TOG_SPARE_SHIFT                1
28004 #define OCOTP_SCS_TOG_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_TOG_SPARE_SHIFT))&OCOTP_SCS_TOG_SPARE_MASK)
28005 #define OCOTP_SCS_TOG_LOCK_MASK                  0x80000000u
28006 #define OCOTP_SCS_TOG_LOCK_SHIFT                 31
28007 /* VERSION Bit Fields */
28008 #define OCOTP_VERSION_STEP_MASK                  0xFFFFu
28009 #define OCOTP_VERSION_STEP_SHIFT                 0
28010 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_STEP_SHIFT))&OCOTP_VERSION_STEP_MASK)
28011 #define OCOTP_VERSION_MINOR_MASK                 0xFF0000u
28012 #define OCOTP_VERSION_MINOR_SHIFT                16
28013 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MINOR_SHIFT))&OCOTP_VERSION_MINOR_MASK)
28014 #define OCOTP_VERSION_MAJOR_MASK                 0xFF000000u
28015 #define OCOTP_VERSION_MAJOR_SHIFT                24
28016 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MAJOR_SHIFT))&OCOTP_VERSION_MAJOR_MASK)
28017 /* LOCK Bit Fields */
28018 #define OCOTP_LOCK_TESTER_MASK                   0x3u
28019 #define OCOTP_LOCK_TESTER_SHIFT                  0
28020 #define OCOTP_LOCK_TESTER(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_TESTER_SHIFT))&OCOTP_LOCK_TESTER_MASK)
28021 #define OCOTP_LOCK_BOOT_CFG_MASK                 0xCu
28022 #define OCOTP_LOCK_BOOT_CFG_SHIFT                2
28023 #define OCOTP_LOCK_BOOT_CFG(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_BOOT_CFG_SHIFT))&OCOTP_LOCK_BOOT_CFG_MASK)
28024 #define OCOTP_LOCK_MEM_TRIM_MASK                 0x30u
28025 #define OCOTP_LOCK_MEM_TRIM_SHIFT                4
28026 #define OCOTP_LOCK_MEM_TRIM(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MEM_TRIM_SHIFT))&OCOTP_LOCK_MEM_TRIM_MASK)
28027 #define OCOTP_LOCK_SJC_RESP_MASK                 0x40u
28028 #define OCOTP_LOCK_SJC_RESP_SHIFT                6
28029 #define OCOTP_LOCK_MAC_ADDR_MASK                 0x300u
28030 #define OCOTP_LOCK_MAC_ADDR_SHIFT                8
28031 #define OCOTP_LOCK_MAC_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MAC_ADDR_SHIFT))&OCOTP_LOCK_MAC_ADDR_MASK)
28032 #define OCOTP_LOCK_GP1_MASK                      0xC00u
28033 #define OCOTP_LOCK_GP1_SHIFT                     10
28034 #define OCOTP_LOCK_GP1(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP1_SHIFT))&OCOTP_LOCK_GP1_MASK)
28035 #define OCOTP_LOCK_GP2_MASK                      0x3000u
28036 #define OCOTP_LOCK_GP2_SHIFT                     12
28037 #define OCOTP_LOCK_GP2(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP2_SHIFT))&OCOTP_LOCK_GP2_MASK)
28038 #define OCOTP_LOCK_SRK_MASK                      0x4000u
28039 #define OCOTP_LOCK_SRK_SHIFT                     14
28040 #define OCOTP_LOCK_ANALOG_MASK                   0xC0000u
28041 #define OCOTP_LOCK_ANALOG_SHIFT                  18
28042 #define OCOTP_LOCK_ANALOG(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_ANALOG_SHIFT))&OCOTP_LOCK_ANALOG_MASK)
28043 #define OCOTP_LOCK_MISC_CONF_MASK                0x400000u
28044 #define OCOTP_LOCK_MISC_CONF_SHIFT               22
28045 #define OCOTP_LOCK_GP3_MASK                      0xC0000000u
28046 #define OCOTP_LOCK_GP3_SHIFT                     30
28047 #define OCOTP_LOCK_GP3(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP3_SHIFT))&OCOTP_LOCK_GP3_MASK)
28048 /* CFG0 Bit Fields */
28049 #define OCOTP_CFG0_BITS_MASK                     0xFFFFFFFFu
28050 #define OCOTP_CFG0_BITS_SHIFT                    0
28051 #define OCOTP_CFG0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG0_BITS_SHIFT))&OCOTP_CFG0_BITS_MASK)
28052 /* CFG1 Bit Fields */
28053 #define OCOTP_CFG1_BITS_MASK                     0xFFFFFFFFu
28054 #define OCOTP_CFG1_BITS_SHIFT                    0
28055 #define OCOTP_CFG1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG1_BITS_SHIFT))&OCOTP_CFG1_BITS_MASK)
28056 /* CFG2 Bit Fields */
28057 #define OCOTP_CFG2_BITS_MASK                     0xFFFFFFFFu
28058 #define OCOTP_CFG2_BITS_SHIFT                    0
28059 #define OCOTP_CFG2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG2_BITS_SHIFT))&OCOTP_CFG2_BITS_MASK)
28060 /* CFG3 Bit Fields */
28061 #define OCOTP_CFG3_BITS_MASK                     0xFFFFFFFFu
28062 #define OCOTP_CFG3_BITS_SHIFT                    0
28063 #define OCOTP_CFG3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG3_BITS_SHIFT))&OCOTP_CFG3_BITS_MASK)
28064 /* CFG4 Bit Fields */
28065 #define OCOTP_CFG4_BITS_MASK                     0xFFFFFFFFu
28066 #define OCOTP_CFG4_BITS_SHIFT                    0
28067 #define OCOTP_CFG4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BITS_SHIFT))&OCOTP_CFG4_BITS_MASK)
28068 /* CFG5 Bit Fields */
28069 #define OCOTP_CFG5_BITS_MASK                     0xFFFFFFFFu
28070 #define OCOTP_CFG5_BITS_SHIFT                    0
28071 #define OCOTP_CFG5_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG5_BITS_SHIFT))&OCOTP_CFG5_BITS_MASK)
28072 /* CFG6 Bit Fields */
28073 #define OCOTP_CFG6_BITS_MASK                     0xFFFFFFFFu
28074 #define OCOTP_CFG6_BITS_SHIFT                    0
28075 #define OCOTP_CFG6_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG6_BITS_SHIFT))&OCOTP_CFG6_BITS_MASK)
28076 /* MEM0 Bit Fields */
28077 #define OCOTP_MEM0_BITS_MASK                     0xFFFFFFFFu
28078 #define OCOTP_MEM0_BITS_SHIFT                    0
28079 #define OCOTP_MEM0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM0_BITS_SHIFT))&OCOTP_MEM0_BITS_MASK)
28080 /* MEM1 Bit Fields */
28081 #define OCOTP_MEM1_BITS_MASK                     0xFFFFFFFFu
28082 #define OCOTP_MEM1_BITS_SHIFT                    0
28083 #define OCOTP_MEM1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_BITS_SHIFT))&OCOTP_MEM1_BITS_MASK)
28084 /* MEM2 Bit Fields */
28085 #define OCOTP_MEM2_BITS_MASK                     0xFFFFFFFFu
28086 #define OCOTP_MEM2_BITS_SHIFT                    0
28087 #define OCOTP_MEM2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM2_BITS_SHIFT))&OCOTP_MEM2_BITS_MASK)
28088 /* MEM3 Bit Fields */
28089 #define OCOTP_MEM3_BITS_MASK                     0xFFFFFFFFu
28090 #define OCOTP_MEM3_BITS_SHIFT                    0
28091 #define OCOTP_MEM3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM3_BITS_SHIFT))&OCOTP_MEM3_BITS_MASK)
28092 /* MEM4 Bit Fields */
28093 #define OCOTP_MEM4_BITS_MASK                     0xFFFFFFFFu
28094 #define OCOTP_MEM4_BITS_SHIFT                    0
28095 #define OCOTP_MEM4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM4_BITS_SHIFT))&OCOTP_MEM4_BITS_MASK)
28096 /* ANA0 Bit Fields */
28097 #define OCOTP_ANA0_BITS_MASK                     0xFFFFFFFFu
28098 #define OCOTP_ANA0_BITS_SHIFT                    0
28099 #define OCOTP_ANA0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_BITS_SHIFT))&OCOTP_ANA0_BITS_MASK)
28100 /* ANA1 Bit Fields */
28101 #define OCOTP_ANA1_BITS_MASK                     0xFFFFFFFFu
28102 #define OCOTP_ANA1_BITS_SHIFT                    0
28103 #define OCOTP_ANA1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA1_BITS_SHIFT))&OCOTP_ANA1_BITS_MASK)
28104 /* ANA2 Bit Fields */
28105 #define OCOTP_ANA2_BITS_MASK                     0xFFFFFFFFu
28106 #define OCOTP_ANA2_BITS_SHIFT                    0
28107 #define OCOTP_ANA2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA2_BITS_SHIFT))&OCOTP_ANA2_BITS_MASK)
28108 /* SRK0 Bit Fields */
28109 #define OCOTP_SRK0_BITS_MASK                     0xFFFFFFFFu
28110 #define OCOTP_SRK0_BITS_SHIFT                    0
28111 #define OCOTP_SRK0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK0_BITS_SHIFT))&OCOTP_SRK0_BITS_MASK)
28112 /* SRK1 Bit Fields */
28113 #define OCOTP_SRK1_BITS_MASK                     0xFFFFFFFFu
28114 #define OCOTP_SRK1_BITS_SHIFT                    0
28115 #define OCOTP_SRK1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK1_BITS_SHIFT))&OCOTP_SRK1_BITS_MASK)
28116 /* SRK2 Bit Fields */
28117 #define OCOTP_SRK2_BITS_MASK                     0xFFFFFFFFu
28118 #define OCOTP_SRK2_BITS_SHIFT                    0
28119 #define OCOTP_SRK2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK2_BITS_SHIFT))&OCOTP_SRK2_BITS_MASK)
28120 /* SRK3 Bit Fields */
28121 #define OCOTP_SRK3_BITS_MASK                     0xFFFFFFFFu
28122 #define OCOTP_SRK3_BITS_SHIFT                    0
28123 #define OCOTP_SRK3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK3_BITS_SHIFT))&OCOTP_SRK3_BITS_MASK)
28124 /* SRK4 Bit Fields */
28125 #define OCOTP_SRK4_BITS_MASK                     0xFFFFFFFFu
28126 #define OCOTP_SRK4_BITS_SHIFT                    0
28127 #define OCOTP_SRK4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK4_BITS_SHIFT))&OCOTP_SRK4_BITS_MASK)
28128 /* SRK5 Bit Fields */
28129 #define OCOTP_SRK5_BITS_MASK                     0xFFFFFFFFu
28130 #define OCOTP_SRK5_BITS_SHIFT                    0
28131 #define OCOTP_SRK5_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK5_BITS_SHIFT))&OCOTP_SRK5_BITS_MASK)
28132 /* SRK6 Bit Fields */
28133 #define OCOTP_SRK6_BITS_MASK                     0xFFFFFFFFu
28134 #define OCOTP_SRK6_BITS_SHIFT                    0
28135 #define OCOTP_SRK6_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK6_BITS_SHIFT))&OCOTP_SRK6_BITS_MASK)
28136 /* SRK7 Bit Fields */
28137 #define OCOTP_SRK7_BITS_MASK                     0xFFFFFFFFu
28138 #define OCOTP_SRK7_BITS_SHIFT                    0
28139 #define OCOTP_SRK7_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK7_BITS_SHIFT))&OCOTP_SRK7_BITS_MASK)
28140 /* RESP0 Bit Fields */
28141 #define OCOTP_RESP0_BITS_MASK                    0xFFFFFFFFu
28142 #define OCOTP_RESP0_BITS_SHIFT                   0
28143 #define OCOTP_RESP0_BITS(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_RESP0_BITS_SHIFT))&OCOTP_RESP0_BITS_MASK)
28144 /* HSJC_RESP1 Bit Fields */
28145 #define OCOTP_HSJC_RESP1_BITS_MASK               0xFFFFFFFFu
28146 #define OCOTP_HSJC_RESP1_BITS_SHIFT              0
28147 #define OCOTP_HSJC_RESP1_BITS(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_HSJC_RESP1_BITS_SHIFT))&OCOTP_HSJC_RESP1_BITS_MASK)
28148 /* MAC0 Bit Fields */
28149 #define OCOTP_MAC0_BITS_MASK                     0xFFFFFFFFu
28150 #define OCOTP_MAC0_BITS_SHIFT                    0
28151 #define OCOTP_MAC0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC0_BITS_SHIFT))&OCOTP_MAC0_BITS_MASK)
28152 /* MAC1 Bit Fields */
28153 #define OCOTP_MAC1_BITS_MASK                     0xFFFFFFFFu
28154 #define OCOTP_MAC1_BITS_SHIFT                    0
28155 #define OCOTP_MAC1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC1_BITS_SHIFT))&OCOTP_MAC1_BITS_MASK)
28156 /* MAC2 Bit Fields */
28157 #define OCOTP_MAC2_BITS_MASK                     0xFFFFFFFFu
28158 #define OCOTP_MAC2_BITS_SHIFT                    0
28159 #define OCOTP_MAC2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC2_BITS_SHIFT))&OCOTP_MAC2_BITS_MASK)
28160 /* GP1 Bit Fields */
28161 #define OCOTP_GP1_BITS_MASK                      0xFFFFFFFFu
28162 #define OCOTP_GP1_BITS_SHIFT                     0
28163 #define OCOTP_GP1_BITS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_GP1_BITS_SHIFT))&OCOTP_GP1_BITS_MASK)
28164 /* GP2 Bit Fields */
28165 #define OCOTP_GP2_BITS_MASK                      0xFFFFFFFFu
28166 #define OCOTP_GP2_BITS_SHIFT                     0
28167 #define OCOTP_GP2_BITS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_GP2_BITS_SHIFT))&OCOTP_GP2_BITS_MASK)
28168 /* MISC_CONF Bit Fields */
28169 #define OCOTP_MISC_CONF_BITS_MASK                0xFFFFFFFFu
28170 #define OCOTP_MISC_CONF_BITS_SHIFT               0
28171 #define OCOTP_MISC_CONF_BITS(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MISC_CONF_BITS_SHIFT))&OCOTP_MISC_CONF_BITS_MASK)
28172 /* FIELD_RETURN Bit Fields */
28173 #define OCOTP_FIELD_RETURN_BITS_MASK             0xFFFFFFFFu
28174 #define OCOTP_FIELD_RETURN_BITS_SHIFT            0
28175 #define OCOTP_FIELD_RETURN_BITS(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_FIELD_RETURN_BITS_SHIFT))&OCOTP_FIELD_RETURN_BITS_MASK)
28176 /* SRK_REVOKE Bit Fields */
28177 #define OCOTP_SRK_REVOKE_BITS_MASK               0xFFFFFFFFu
28178 #define OCOTP_SRK_REVOKE_BITS_SHIFT              0
28179 #define OCOTP_SRK_REVOKE_BITS(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_BITS_SHIFT))&OCOTP_SRK_REVOKE_BITS_MASK)
28180 /* GP30 Bit Fields */
28181 #define OCOTP_GP30_BITS_MASK                     0xFFFFFFFFu
28182 #define OCOTP_GP30_BITS_SHIFT                    0
28183 #define OCOTP_GP30_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP30_BITS_SHIFT))&OCOTP_GP30_BITS_MASK)
28184 /* GP31 Bit Fields */
28185 #define OCOTP_GP31_BITS_MASK                     0xFFFFFFFFu
28186 #define OCOTP_GP31_BITS_SHIFT                    0
28187 #define OCOTP_GP31_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP31_BITS_SHIFT))&OCOTP_GP31_BITS_MASK)
28188 /* GP32 Bit Fields */
28189 #define OCOTP_GP32_BITS_MASK                     0xFFFFFFFFu
28190 #define OCOTP_GP32_BITS_SHIFT                    0
28191 #define OCOTP_GP32_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP32_BITS_SHIFT))&OCOTP_GP32_BITS_MASK)
28192 /* GP33 Bit Fields */
28193 #define OCOTP_GP33_BITS_MASK                     0xFFFFFFFFu
28194 #define OCOTP_GP33_BITS_SHIFT                    0
28195 #define OCOTP_GP33_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP33_BITS_SHIFT))&OCOTP_GP33_BITS_MASK)
28196 /* GP34 Bit Fields */
28197 #define OCOTP_GP34_BITS_MASK                     0xFFFFFFFFu
28198 #define OCOTP_GP34_BITS_SHIFT                    0
28199 #define OCOTP_GP34_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP34_BITS_SHIFT))&OCOTP_GP34_BITS_MASK)
28200 /* GP35 Bit Fields */
28201 #define OCOTP_GP35_BITS_MASK                     0xFFFFFFFFu
28202 #define OCOTP_GP35_BITS_SHIFT                    0
28203 #define OCOTP_GP35_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP35_BITS_SHIFT))&OCOTP_GP35_BITS_MASK)
28204 /* GP36 Bit Fields */
28205 #define OCOTP_GP36_BITS_MASK                     0xFFFFFFFFu
28206 #define OCOTP_GP36_BITS_SHIFT                    0
28207 #define OCOTP_GP36_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_GP36_BITS_SHIFT))&OCOTP_GP36_BITS_MASK)
28208 
28209 /*!
28210  * @}
28211  */ /* end of group OCOTP_Register_Masks */
28212 
28213 /* OCOTP - Peripheral instance base addresses */
28214 /** Peripheral OCOTP base address */
28215 #define OCOTP_BASE                               (0x421BC000u)
28216 /** Peripheral OCOTP base pointer */
28217 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
28218 #define OCOTP_BASE_PTR                           (OCOTP)
28219 /** Array initializer of OCOTP peripheral base addresses */
28220 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
28221 /** Array initializer of OCOTP peripheral base pointers */
28222 #define OCOTP_BASE_PTRS                          { OCOTP }
28223 
28224 /* ----------------------------------------------------------------------------
28225    -- OCOTP - Register accessor macros
28226    ---------------------------------------------------------------------------- */
28227 
28228 /*!
28229  * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros
28230  * @{
28231  */
28232 
28233 /* OCOTP - Register instance definitions */
28234 /* OCOTP */
28235 #define OCOTP_CTRL                               OCOTP_CTRL_REG(OCOTP_BASE_PTR)
28236 #define OCOTP_CTRL_SET                           OCOTP_CTRL_SET_REG(OCOTP_BASE_PTR)
28237 #define OCOTP_CTRL_CLR                           OCOTP_CTRL_CLR_REG(OCOTP_BASE_PTR)
28238 #define OCOTP_CTRL_TOG                           OCOTP_CTRL_TOG_REG(OCOTP_BASE_PTR)
28239 #define OCOTP_TIMING                             OCOTP_TIMING_REG(OCOTP_BASE_PTR)
28240 #define OCOTP_DATA                               OCOTP_DATA_REG(OCOTP_BASE_PTR)
28241 #define OCOTP_READ_CTRL                          OCOTP_READ_CTRL_REG(OCOTP_BASE_PTR)
28242 #define OCOTP_READ_FUSE_DATA                     OCOTP_READ_FUSE_DATA_REG(OCOTP_BASE_PTR)
28243 #define OCOTP_SW_STICKY                          OCOTP_SW_STICKY_REG(OCOTP_BASE_PTR)
28244 #define OCOTP_SCS                                OCOTP_SCS_REG(OCOTP_BASE_PTR)
28245 #define OCOTP_SCS_SET                            OCOTP_SCS_SET_REG(OCOTP_BASE_PTR)
28246 #define OCOTP_SCS_CLR                            OCOTP_SCS_CLR_REG(OCOTP_BASE_PTR)
28247 #define OCOTP_SCS_TOG                            OCOTP_SCS_TOG_REG(OCOTP_BASE_PTR)
28248 #define OCOTP_VERSION                            OCOTP_VERSION_REG(OCOTP_BASE_PTR)
28249 #define OCOTP_LOCK                               OCOTP_LOCK_REG(OCOTP_BASE_PTR)
28250 #define OCOTP_CFG0                               OCOTP_CFG0_REG(OCOTP_BASE_PTR)
28251 #define OCOTP_CFG1                               OCOTP_CFG1_REG(OCOTP_BASE_PTR)
28252 #define OCOTP_CFG2                               OCOTP_CFG2_REG(OCOTP_BASE_PTR)
28253 #define OCOTP_CFG3                               OCOTP_CFG3_REG(OCOTP_BASE_PTR)
28254 #define OCOTP_CFG4                               OCOTP_CFG4_REG(OCOTP_BASE_PTR)
28255 #define OCOTP_CFG5                               OCOTP_CFG5_REG(OCOTP_BASE_PTR)
28256 #define OCOTP_CFG6                               OCOTP_CFG6_REG(OCOTP_BASE_PTR)
28257 #define OCOTP_MEM0                               OCOTP_MEM0_REG(OCOTP_BASE_PTR)
28258 #define OCOTP_MEM1                               OCOTP_MEM1_REG(OCOTP_BASE_PTR)
28259 #define OCOTP_MEM2                               OCOTP_MEM2_REG(OCOTP_BASE_PTR)
28260 #define OCOTP_MEM3                               OCOTP_MEM3_REG(OCOTP_BASE_PTR)
28261 #define OCOTP_MEM4                               OCOTP_MEM4_REG(OCOTP_BASE_PTR)
28262 #define OCOTP_ANA0                               OCOTP_ANA0_REG(OCOTP_BASE_PTR)
28263 #define OCOTP_ANA1                               OCOTP_ANA1_REG(OCOTP_BASE_PTR)
28264 #define OCOTP_ANA2                               OCOTP_ANA2_REG(OCOTP_BASE_PTR)
28265 #define OCOTP_SRK0                               OCOTP_SRK0_REG(OCOTP_BASE_PTR)
28266 #define OCOTP_SRK1                               OCOTP_SRK1_REG(OCOTP_BASE_PTR)
28267 #define OCOTP_SRK2                               OCOTP_SRK2_REG(OCOTP_BASE_PTR)
28268 #define OCOTP_SRK3                               OCOTP_SRK3_REG(OCOTP_BASE_PTR)
28269 #define OCOTP_SRK4                               OCOTP_SRK4_REG(OCOTP_BASE_PTR)
28270 #define OCOTP_SRK5                               OCOTP_SRK5_REG(OCOTP_BASE_PTR)
28271 #define OCOTP_SRK6                               OCOTP_SRK6_REG(OCOTP_BASE_PTR)
28272 #define OCOTP_SRK7                               OCOTP_SRK7_REG(OCOTP_BASE_PTR)
28273 #define OCOTP_RESP0                              OCOTP_RESP0_REG(OCOTP_BASE_PTR)
28274 #define OCOTP_HSJC_RESP1                         OCOTP_HSJC_RESP1_REG(OCOTP_BASE_PTR)
28275 #define OCOTP_MAC0                               OCOTP_MAC0_REG(OCOTP_BASE_PTR)
28276 #define OCOTP_MAC1                               OCOTP_MAC1_REG(OCOTP_BASE_PTR)
28277 #define OCOTP_MAC2                               OCOTP_MAC2_REG(OCOTP_BASE_PTR)
28278 #define OCOTP_GP1                                OCOTP_GP1_REG(OCOTP_BASE_PTR)
28279 #define OCOTP_GP2                                OCOTP_GP2_REG(OCOTP_BASE_PTR)
28280 #define OCOTP_MISC_CONF                          OCOTP_MISC_CONF_REG(OCOTP_BASE_PTR)
28281 #define OCOTP_FIELD_RETURN                       OCOTP_FIELD_RETURN_REG(OCOTP_BASE_PTR)
28282 #define OCOTP_SRK_REVOKE                         OCOTP_SRK_REVOKE_REG(OCOTP_BASE_PTR)
28283 #define OCOTP_GP30                               OCOTP_GP30_REG(OCOTP_BASE_PTR)
28284 #define OCOTP_GP31                               OCOTP_GP31_REG(OCOTP_BASE_PTR)
28285 #define OCOTP_GP32                               OCOTP_GP32_REG(OCOTP_BASE_PTR)
28286 #define OCOTP_GP33                               OCOTP_GP33_REG(OCOTP_BASE_PTR)
28287 #define OCOTP_GP34                               OCOTP_GP34_REG(OCOTP_BASE_PTR)
28288 #define OCOTP_GP35                               OCOTP_GP35_REG(OCOTP_BASE_PTR)
28289 #define OCOTP_GP36                               OCOTP_GP36_REG(OCOTP_BASE_PTR)
28290 
28291 /*!
28292  * @}
28293  */ /* end of group OCOTP_Register_Accessor_Macros */
28294 
28295 /*!
28296  * @}
28297  */ /* end of group OCOTP_Peripheral */
28298 
28299 /* ----------------------------------------------------------------------------
28300    -- PGC Peripheral Access Layer
28301    ---------------------------------------------------------------------------- */
28302 
28303 /*!
28304  * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer
28305  * @{
28306  */
28307 
28308 /** PGC - Register Layout Typedef */
28309 typedef struct {
28310   uint8_t RESERVED_0[512];
28311   __IO  uint32_t PCIE_PHY_CTRL;                          /**< PGC Control Register, offset: 0x200 */
28312   __IO  uint32_t PCIE_PHY_PUPSCR;                        /**< Power Up Sequence Control Register, offset: 0x204 */
28313   __IO  uint32_t PCIE_PHY_PDNSCR;                        /**< Pull Down Sequence Control Register, offset: 0x208 */
28314   __IO  uint32_t PCIE_PHY_SR;                            /**< Power Gating Controller Status Register, offset: 0x20C */
28315   uint8_t RESERVED_1[16];
28316   __IO  uint32_t MEGA_CTRL;                              /**< PGC Control Register, offset: 0x220 */
28317   __IO  uint32_t MEGA_PUPSCR;                            /**< Power Up Sequence Control Register, offset: 0x224 */
28318   __IO  uint32_t MEGA_PDNSCR;                            /**< Pull Down Sequence Control Register, offset: 0x228 */
28319   __IO  uint32_t MEGA_SR;                                /**< Power Gating Controller Status Register, offset: 0x22C */
28320   uint8_t RESERVED_2[16];
28321   __IO  uint32_t DISPLAY_CTRL;                           /**< PGC Control Register, offset: 0x240 */
28322   __IO  uint32_t DISPLAY_PUPSCR;                         /**< Power Up Sequence Control Register, offset: 0x244 */
28323   __IO  uint32_t DISPLAY_PDNSCR;                         /**< Pull Down Sequence Control Register, offset: 0x248 */
28324   __IO  uint32_t DISPLAY_SR;                             /**< Power Gating Controller Status Register, offset: 0x24C */
28325   uint8_t RESERVED_3[16];
28326   __IO  uint32_t GPU_CTRL;                               /**< PGC Control Register, offset: 0x260 */
28327   __IO  uint32_t GPU_PUPSCR;                             /**< Power Up Sequence Control Register, offset: 0x264 */
28328   __IO  uint32_t GPU_PDNSCR;                             /**< Pull Down Sequence Control Register, offset: 0x268 */
28329   __IO  uint32_t GPU_SR;                                 /**< Power Gating Controller Status Register, offset: 0x26C */
28330   uint8_t RESERVED_4[48];
28331   __IO  uint32_t CPU_CTRL;                               /**< PGC Control Register, offset: 0x2A0 */
28332   __IO  uint32_t CPU_PUPSCR;                             /**< Power Up Sequence Control Register, offset: 0x2A4 */
28333   __IO  uint32_t CPU_PDNSCR;                             /**< Pull Down Sequence Control Register, offset: 0x2A8 */
28334   __IO  uint32_t CPU_SR;                                 /**< Power Gating Controller Status Register, offset: 0x2AC */
28335 } PGC_Type, *PGC_MemMapPtr;
28336 
28337 /* ----------------------------------------------------------------------------
28338    -- PGC - Register accessor macros
28339    ---------------------------------------------------------------------------- */
28340 
28341 /*!
28342  * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros
28343  * @{
28344  */
28345 
28346 /* PGC - Register accessors */
28347 #define PGC_PCIE_PHY_CTRL_REG(base)              ((base)->PCIE_PHY_CTRL)
28348 #define PGC_PCIE_PHY_PUPSCR_REG(base)            ((base)->PCIE_PHY_PUPSCR)
28349 #define PGC_PCIE_PHY_PDNSCR_REG(base)            ((base)->PCIE_PHY_PDNSCR)
28350 #define PGC_PCIE_PHY_SR_REG(base)                ((base)->PCIE_PHY_SR)
28351 #define PGC_MEGA_CTRL_REG(base)                  ((base)->MEGA_CTRL)
28352 #define PGC_MEGA_PUPSCR_REG(base)                ((base)->MEGA_PUPSCR)
28353 #define PGC_MEGA_PDNSCR_REG(base)                ((base)->MEGA_PDNSCR)
28354 #define PGC_MEGA_SR_REG(base)                    ((base)->MEGA_SR)
28355 #define PGC_DISPLAY_CTRL_REG(base)               ((base)->DISPLAY_CTRL)
28356 #define PGC_DISPLAY_PUPSCR_REG(base)             ((base)->DISPLAY_PUPSCR)
28357 #define PGC_DISPLAY_PDNSCR_REG(base)             ((base)->DISPLAY_PDNSCR)
28358 #define PGC_DISPLAY_SR_REG(base)                 ((base)->DISPLAY_SR)
28359 #define PGC_GPU_CTRL_REG(base)                   ((base)->GPU_CTRL)
28360 #define PGC_GPU_PUPSCR_REG(base)                 ((base)->GPU_PUPSCR)
28361 #define PGC_GPU_PDNSCR_REG(base)                 ((base)->GPU_PDNSCR)
28362 #define PGC_GPU_SR_REG(base)                     ((base)->GPU_SR)
28363 #define PGC_CPU_CTRL_REG(base)                   ((base)->CPU_CTRL)
28364 #define PGC_CPU_PUPSCR_REG(base)                 ((base)->CPU_PUPSCR)
28365 #define PGC_CPU_PDNSCR_REG(base)                 ((base)->CPU_PDNSCR)
28366 #define PGC_CPU_SR_REG(base)                     ((base)->CPU_SR)
28367 
28368 /*!
28369  * @}
28370  */ /* end of group PGC_Register_Accessor_Macros */
28371 
28372 /* ----------------------------------------------------------------------------
28373    -- PGC Register Masks
28374    ---------------------------------------------------------------------------- */
28375 
28376 /*!
28377  * @addtogroup PGC_Register_Masks PGC Register Masks
28378  * @{
28379  */
28380 
28381 /* PCIE_PHY_CTRL Bit Fields */
28382 #define PGC_PCIE_PHY_CTRL_PCR_MASK               0x1u
28383 #define PGC_PCIE_PHY_CTRL_PCR_SHIFT              0
28384 /* PCIE_PHY_PUPSCR Bit Fields */
28385 #define PGC_PCIE_PHY_PUPSCR_SW_MASK              0x3Fu
28386 #define PGC_PCIE_PHY_PUPSCR_SW_SHIFT             0
28387 #define PGC_PCIE_PHY_PUPSCR_SW(x)                (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PUPSCR_SW_SHIFT))&PGC_PCIE_PHY_PUPSCR_SW_MASK)
28388 #define PGC_PCIE_PHY_PUPSCR_SW2ISO_MASK          0x3F00u
28389 #define PGC_PCIE_PHY_PUPSCR_SW2ISO_SHIFT         8
28390 #define PGC_PCIE_PHY_PUPSCR_SW2ISO(x)            (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PUPSCR_SW2ISO_SHIFT))&PGC_PCIE_PHY_PUPSCR_SW2ISO_MASK)
28391 /* PCIE_PHY_PDNSCR Bit Fields */
28392 #define PGC_PCIE_PHY_PDNSCR_ISO_MASK             0x3Fu
28393 #define PGC_PCIE_PHY_PDNSCR_ISO_SHIFT            0
28394 #define PGC_PCIE_PHY_PDNSCR_ISO(x)               (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PDNSCR_ISO_SHIFT))&PGC_PCIE_PHY_PDNSCR_ISO_MASK)
28395 #define PGC_PCIE_PHY_PDNSCR_ISO2SW_MASK          0x3F00u
28396 #define PGC_PCIE_PHY_PDNSCR_ISO2SW_SHIFT         8
28397 #define PGC_PCIE_PHY_PDNSCR_ISO2SW(x)            (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PDNSCR_ISO2SW_SHIFT))&PGC_PCIE_PHY_PDNSCR_ISO2SW_MASK)
28398 /* PCIE_PHY_SR Bit Fields */
28399 #define PGC_PCIE_PHY_SR_PSR_MASK                 0x1u
28400 #define PGC_PCIE_PHY_SR_PSR_SHIFT                0
28401 /* MEGA_CTRL Bit Fields */
28402 #define PGC_MEGA_CTRL_PCR_MASK                   0x1u
28403 #define PGC_MEGA_CTRL_PCR_SHIFT                  0
28404 /* MEGA_PUPSCR Bit Fields */
28405 #define PGC_MEGA_PUPSCR_SW_MASK                  0x3Fu
28406 #define PGC_MEGA_PUPSCR_SW_SHIFT                 0
28407 #define PGC_MEGA_PUPSCR_SW(x)                    (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PUPSCR_SW_SHIFT))&PGC_MEGA_PUPSCR_SW_MASK)
28408 #define PGC_MEGA_PUPSCR_SW2ISO_MASK              0x3F00u
28409 #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT             8
28410 #define PGC_MEGA_PUPSCR_SW2ISO(x)                (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PUPSCR_SW2ISO_SHIFT))&PGC_MEGA_PUPSCR_SW2ISO_MASK)
28411 /* MEGA_PDNSCR Bit Fields */
28412 #define PGC_MEGA_PDNSCR_ISO_MASK                 0x3Fu
28413 #define PGC_MEGA_PDNSCR_ISO_SHIFT                0
28414 #define PGC_MEGA_PDNSCR_ISO(x)                   (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PDNSCR_ISO_SHIFT))&PGC_MEGA_PDNSCR_ISO_MASK)
28415 #define PGC_MEGA_PDNSCR_ISO2SW_MASK              0x3F00u
28416 #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT             8
28417 #define PGC_MEGA_PDNSCR_ISO2SW(x)                (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PDNSCR_ISO2SW_SHIFT))&PGC_MEGA_PDNSCR_ISO2SW_MASK)
28418 /* MEGA_SR Bit Fields */
28419 #define PGC_MEGA_SR_PSR_MASK                     0x1u
28420 #define PGC_MEGA_SR_PSR_SHIFT                    0
28421 /* DISPLAY_CTRL Bit Fields */
28422 #define PGC_DISPLAY_CTRL_PCR_MASK                0x1u
28423 #define PGC_DISPLAY_CTRL_PCR_SHIFT               0
28424 /* DISPLAY_PUPSCR Bit Fields */
28425 #define PGC_DISPLAY_PUPSCR_SW_MASK               0x3Fu
28426 #define PGC_DISPLAY_PUPSCR_SW_SHIFT              0
28427 #define PGC_DISPLAY_PUPSCR_SW(x)                 (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PUPSCR_SW_SHIFT))&PGC_DISPLAY_PUPSCR_SW_MASK)
28428 #define PGC_DISPLAY_PUPSCR_SW2ISO_MASK           0x3F00u
28429 #define PGC_DISPLAY_PUPSCR_SW2ISO_SHIFT          8
28430 #define PGC_DISPLAY_PUPSCR_SW2ISO(x)             (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PUPSCR_SW2ISO_SHIFT))&PGC_DISPLAY_PUPSCR_SW2ISO_MASK)
28431 /* DISPLAY_PDNSCR Bit Fields */
28432 #define PGC_DISPLAY_PDNSCR_ISO_MASK              0x3Fu
28433 #define PGC_DISPLAY_PDNSCR_ISO_SHIFT             0
28434 #define PGC_DISPLAY_PDNSCR_ISO(x)                (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PDNSCR_ISO_SHIFT))&PGC_DISPLAY_PDNSCR_ISO_MASK)
28435 #define PGC_DISPLAY_PDNSCR_ISO2SW_MASK           0x3F00u
28436 #define PGC_DISPLAY_PDNSCR_ISO2SW_SHIFT          8
28437 #define PGC_DISPLAY_PDNSCR_ISO2SW(x)             (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PDNSCR_ISO2SW_SHIFT))&PGC_DISPLAY_PDNSCR_ISO2SW_MASK)
28438 /* DISPLAY_SR Bit Fields */
28439 #define PGC_DISPLAY_SR_PSR_MASK                  0x1u
28440 #define PGC_DISPLAY_SR_PSR_SHIFT                 0
28441 /* GPU_CTRL Bit Fields */
28442 #define PGC_GPU_CTRL_PCR_MASK                    0x1u
28443 #define PGC_GPU_CTRL_PCR_SHIFT                   0
28444 /* GPU_PUPSCR Bit Fields */
28445 #define PGC_GPU_PUPSCR_SW_MASK                   0x3Fu
28446 #define PGC_GPU_PUPSCR_SW_SHIFT                  0
28447 #define PGC_GPU_PUPSCR_SW(x)                     (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW_SHIFT))&PGC_GPU_PUPSCR_SW_MASK)
28448 #define PGC_GPU_PUPSCR_SW2ISO_MASK               0x3F00u
28449 #define PGC_GPU_PUPSCR_SW2ISO_SHIFT              8
28450 #define PGC_GPU_PUPSCR_SW2ISO(x)                 (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW2ISO_SHIFT))&PGC_GPU_PUPSCR_SW2ISO_MASK)
28451 /* GPU_PDNSCR Bit Fields */
28452 #define PGC_GPU_PDNSCR_ISO_MASK                  0x3Fu
28453 #define PGC_GPU_PDNSCR_ISO_SHIFT                 0
28454 #define PGC_GPU_PDNSCR_ISO(x)                    (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO_SHIFT))&PGC_GPU_PDNSCR_ISO_MASK)
28455 #define PGC_GPU_PDNSCR_ISO2SW_MASK               0x3F00u
28456 #define PGC_GPU_PDNSCR_ISO2SW_SHIFT              8
28457 #define PGC_GPU_PDNSCR_ISO2SW(x)                 (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO2SW_SHIFT))&PGC_GPU_PDNSCR_ISO2SW_MASK)
28458 /* GPU_SR Bit Fields */
28459 #define PGC_GPU_SR_PSR_MASK                      0x1u
28460 #define PGC_GPU_SR_PSR_SHIFT                     0
28461 /* CPU_CTRL Bit Fields */
28462 #define PGC_CPU_CTRL_PCR_MASK                    0x1u
28463 #define PGC_CPU_CTRL_PCR_SHIFT                   0
28464 /* CPU_PUPSCR Bit Fields */
28465 #define PGC_CPU_PUPSCR_SW_MASK                   0x3Fu
28466 #define PGC_CPU_PUPSCR_SW_SHIFT                  0
28467 #define PGC_CPU_PUPSCR_SW(x)                     (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW_SHIFT))&PGC_CPU_PUPSCR_SW_MASK)
28468 #define PGC_CPU_PUPSCR_SW2ISO_MASK               0x3F00u
28469 #define PGC_CPU_PUPSCR_SW2ISO_SHIFT              8
28470 #define PGC_CPU_PUPSCR_SW2ISO(x)                 (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW2ISO_SHIFT))&PGC_CPU_PUPSCR_SW2ISO_MASK)
28471 /* CPU_PDNSCR Bit Fields */
28472 #define PGC_CPU_PDNSCR_ISO_MASK                  0x3Fu
28473 #define PGC_CPU_PDNSCR_ISO_SHIFT                 0
28474 #define PGC_CPU_PDNSCR_ISO(x)                    (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO_SHIFT))&PGC_CPU_PDNSCR_ISO_MASK)
28475 #define PGC_CPU_PDNSCR_ISO2SW_MASK               0x3F00u
28476 #define PGC_CPU_PDNSCR_ISO2SW_SHIFT              8
28477 #define PGC_CPU_PDNSCR_ISO2SW(x)                 (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO2SW_SHIFT))&PGC_CPU_PDNSCR_ISO2SW_MASK)
28478 /* CPU_SR Bit Fields */
28479 #define PGC_CPU_SR_PSR_MASK                      0x1u
28480 #define PGC_CPU_SR_PSR_SHIFT                     0
28481 
28482 /*!
28483  * @}
28484  */ /* end of group PGC_Register_Masks */
28485 
28486 /* PGC - Peripheral instance base addresses */
28487 /** Peripheral PGC_ARM base address */
28488 #define PGC_ARM_BASE                             (0x420DC040u)
28489 /** Peripheral PGC_ARM base pointer */
28490 #define PGC_ARM                                  ((PGC_Type *)PGC_ARM_BASE)
28491 #define PGC_ARM_BASE_PTR                         (PGC_ARM)
28492 /** Peripheral PGC_GPU base address */
28493 #define PGC_GPU_BASE                             (0x420DC000u)
28494 /** Peripheral PGC_GPU base pointer */
28495 #define PGC_GPU                                  ((PGC_Type *)PGC_GPU_BASE)
28496 #define PGC_GPU_BASE_PTR                         (PGC_GPU)
28497 /** Array initializer of PGC peripheral base addresses */
28498 #define PGC_BASE_ADDRS                           { PGC_ARM_BASE, PGC_GPU_BASE }
28499 /** Array initializer of PGC peripheral base pointers */
28500 #define PGC_BASE_PTRS                            { PGC_ARM, PGC_GPU }
28501 
28502 /* ----------------------------------------------------------------------------
28503    -- PGC - Register accessor macros
28504    ---------------------------------------------------------------------------- */
28505 
28506 /*!
28507  * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros
28508  * @{
28509  */
28510 
28511 /* PGC - Register instance definitions */
28512 /* PGC_ARM */
28513 #define PGC_ARM_PCIE_PHY_CTRL                    PGC_PCIE_PHY_CTRL_REG(PGC_ARM_BASE_PTR)
28514 #define PGC_ARM_PCIE_PHY_PUPSCR                  PGC_PCIE_PHY_PUPSCR_REG(PGC_ARM_BASE_PTR)
28515 #define PGC_ARM_PCIE_PHY_PDNSCR                  PGC_PCIE_PHY_PDNSCR_REG(PGC_ARM_BASE_PTR)
28516 #define PGC_ARM_PCIE_PHY_SR                      PGC_PCIE_PHY_SR_REG(PGC_ARM_BASE_PTR)
28517 #define PGC_ARM_MEGA_CTRL                        PGC_MEGA_CTRL_REG(PGC_ARM_BASE_PTR)
28518 #define PGC_ARM_MEGA_PUPSCR                      PGC_MEGA_PUPSCR_REG(PGC_ARM_BASE_PTR)
28519 #define PGC_ARM_MEGA_PDNSCR                      PGC_MEGA_PDNSCR_REG(PGC_ARM_BASE_PTR)
28520 #define PGC_ARM_MEGA_SR                          PGC_MEGA_SR_REG(PGC_ARM_BASE_PTR)
28521 #define PGC_ARM_DISPLAY_CTRL                     PGC_DISPLAY_CTRL_REG(PGC_ARM_BASE_PTR)
28522 #define PGC_ARM_DISPLAY_PUPSCR                   PGC_DISPLAY_PUPSCR_REG(PGC_ARM_BASE_PTR)
28523 #define PGC_ARM_DISPLAY_PDNSCR                   PGC_DISPLAY_PDNSCR_REG(PGC_ARM_BASE_PTR)
28524 #define PGC_ARM_DISPLAY_SR                       PGC_DISPLAY_SR_REG(PGC_ARM_BASE_PTR)
28525 #define PGC_ARM_GPU_CTRL                         PGC_GPU_CTRL_REG(PGC_ARM_BASE_PTR)
28526 #define PGC_ARM_GPU_PUPSCR                       PGC_GPU_PUPSCR_REG(PGC_ARM_BASE_PTR)
28527 #define PGC_ARM_GPU_PDNSCR                       PGC_GPU_PDNSCR_REG(PGC_ARM_BASE_PTR)
28528 #define PGC_ARM_GPU_SR                           PGC_GPU_SR_REG(PGC_ARM_BASE_PTR)
28529 #define PGC_ARM_CPU_CTRL                         PGC_CPU_CTRL_REG(PGC_ARM_BASE_PTR)
28530 #define PGC_ARM_CPU_PUPSCR                       PGC_CPU_PUPSCR_REG(PGC_ARM_BASE_PTR)
28531 #define PGC_ARM_CPU_PDNSCR                       PGC_CPU_PDNSCR_REG(PGC_ARM_BASE_PTR)
28532 #define PGC_ARM_CPU_SR                           PGC_CPU_SR_REG(PGC_ARM_BASE_PTR)
28533 /* PGC_GPU */
28534 #define PGC_GPU_PCIE_PHY_CTRL                    PGC_PCIE_PHY_CTRL_REG(PGC_GPU_BASE_PTR)
28535 #define PGC_GPU_PCIE_PHY_PUPSCR                  PGC_PCIE_PHY_PUPSCR_REG(PGC_GPU_BASE_PTR)
28536 #define PGC_GPU_PCIE_PHY_PDNSCR                  PGC_PCIE_PHY_PDNSCR_REG(PGC_GPU_BASE_PTR)
28537 #define PGC_GPU_PCIE_PHY_SR                      PGC_PCIE_PHY_SR_REG(PGC_GPU_BASE_PTR)
28538 #define PGC_GPU_MEGA_CTRL                        PGC_MEGA_CTRL_REG(PGC_GPU_BASE_PTR)
28539 #define PGC_GPU_MEGA_PUPSCR                      PGC_MEGA_PUPSCR_REG(PGC_GPU_BASE_PTR)
28540 #define PGC_GPU_MEGA_PDNSCR                      PGC_MEGA_PDNSCR_REG(PGC_GPU_BASE_PTR)
28541 #define PGC_GPU_MEGA_SR                          PGC_MEGA_SR_REG(PGC_GPU_BASE_PTR)
28542 #define PGC_GPU_DISPLAY_CTRL                     PGC_DISPLAY_CTRL_REG(PGC_GPU_BASE_PTR)
28543 #define PGC_GPU_DISPLAY_PUPSCR                   PGC_DISPLAY_PUPSCR_REG(PGC_GPU_BASE_PTR)
28544 #define PGC_GPU_DISPLAY_PDNSCR                   PGC_DISPLAY_PDNSCR_REG(PGC_GPU_BASE_PTR)
28545 #define PGC_GPU_DISPLAY_SR                       PGC_DISPLAY_SR_REG(PGC_GPU_BASE_PTR)
28546 #define PGC_GPU_GPU_CTRL                         PGC_GPU_CTRL_REG(PGC_GPU_BASE_PTR)
28547 #define PGC_GPU_GPU_PUPSCR                       PGC_GPU_PUPSCR_REG(PGC_GPU_BASE_PTR)
28548 #define PGC_GPU_GPU_PDNSCR                       PGC_GPU_PDNSCR_REG(PGC_GPU_BASE_PTR)
28549 #define PGC_GPU_GPU_SR                           PGC_GPU_SR_REG(PGC_GPU_BASE_PTR)
28550 #define PGC_GPU_CPU_CTRL                         PGC_CPU_CTRL_REG(PGC_GPU_BASE_PTR)
28551 #define PGC_GPU_CPU_PUPSCR                       PGC_CPU_PUPSCR_REG(PGC_GPU_BASE_PTR)
28552 #define PGC_GPU_CPU_PDNSCR                       PGC_CPU_PDNSCR_REG(PGC_GPU_BASE_PTR)
28553 #define PGC_GPU_CPU_SR                           PGC_CPU_SR_REG(PGC_GPU_BASE_PTR)
28554 
28555 /*!
28556  * @}
28557  */ /* end of group PGC_Register_Accessor_Macros */
28558 
28559 /*!
28560  * @}
28561  */ /* end of group PGC_Peripheral */
28562 
28563 /* ----------------------------------------------------------------------------
28564    -- PMU Peripheral Access Layer
28565    ---------------------------------------------------------------------------- */
28566 
28567 /*!
28568  * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
28569  * @{
28570  */
28571 
28572 /** PMU - Register Layout Typedef */
28573 typedef struct {
28574   uint8_t RESERVED_0[272];
28575   __IO  uint32_t REG_1P1;                                /**< Regulator 1P1 Register, offset: 0x110 */
28576   uint8_t RESERVED_1[12];
28577   __IO  uint32_t REG_3P0;                                /**< Regulator 3P0 Register, offset: 0x120 */
28578   uint8_t RESERVED_2[12];
28579   __IO  uint32_t REG_2P5;                                /**< Regulator 2P5 Register, offset: 0x130 */
28580   uint8_t RESERVED_3[12];
28581   __IO  uint32_t REG_CORE;                               /**< Digital Regulator Core Register, offset: 0x140 */
28582   uint8_t RESERVED_4[12];
28583   __IO  uint32_t MISC0;                                  /**< Miscellaneous Register 0, offset: 0x150 */
28584   uint8_t RESERVED_5[12];
28585   __IO  uint32_t MISC1;                                  /**< Miscellaneous Register 1, offset: 0x160 */
28586   __IO  uint32_t MISC1_SET;                              /**< Miscellaneous Register 1, offset: 0x164 */
28587   __IO  uint32_t MISC1_CLR;                              /**< Miscellaneous Register 1, offset: 0x168 */
28588   __IO  uint32_t MISC1_TOG;                              /**< Miscellaneous Register 1, offset: 0x16C */
28589   __IO  uint32_t MISC2;                                  /**< Miscellaneous Control Register, offset: 0x170 */
28590   __IO  uint32_t MISC2_SET;                              /**< Miscellaneous Control Register, offset: 0x174 */
28591   __IO  uint32_t MISC2_CLR;                              /**< Miscellaneous Control Register, offset: 0x178 */
28592   __IO  uint32_t MISC2_TOG;                              /**< Miscellaneous Control Register, offset: 0x17C */
28593   uint8_t RESERVED_6[240];
28594   __IO  uint32_t LOWPWR_CTRL_SET;                        /**< Low Power Control Register, offset: 0x270 */
28595   __IO  uint32_t LOWPWR_CTRL_CLR;                        /**< Low Power Control Register, offset: 0x274 */
28596   __IO  uint32_t LOWPWR_CTRL_TOG;                        /**< Low Power Control Register, offset: 0x278 */
28597 } PMU_Type, *PMU_MemMapPtr;
28598 
28599 /* ----------------------------------------------------------------------------
28600    -- PMU - Register accessor macros
28601    ---------------------------------------------------------------------------- */
28602 
28603 /*!
28604  * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros
28605  * @{
28606  */
28607 
28608 /* PMU - Register accessors */
28609 #define PMU_REG_1P1_REG(base)                    ((base)->REG_1P1)
28610 #define PMU_REG_3P0_REG(base)                    ((base)->REG_3P0)
28611 #define PMU_REG_2P5_REG(base)                    ((base)->REG_2P5)
28612 #define PMU_REG_CORE_REG(base)                   ((base)->REG_CORE)
28613 #define PMU_MISC0_REG(base)                      ((base)->MISC0)
28614 #define PMU_MISC1_REG(base)                      ((base)->MISC1)
28615 #define PMU_MISC1_SET_REG(base)                  ((base)->MISC1_SET)
28616 #define PMU_MISC1_CLR_REG(base)                  ((base)->MISC1_CLR)
28617 #define PMU_MISC1_TOG_REG(base)                  ((base)->MISC1_TOG)
28618 #define PMU_MISC2_REG(base)                      ((base)->MISC2)
28619 #define PMU_MISC2_SET_REG(base)                  ((base)->MISC2_SET)
28620 #define PMU_MISC2_CLR_REG(base)                  ((base)->MISC2_CLR)
28621 #define PMU_MISC2_TOG_REG(base)                  ((base)->MISC2_TOG)
28622 #define PMU_LOWPWR_CTRL_SET_REG(base)            ((base)->LOWPWR_CTRL_SET)
28623 #define PMU_LOWPWR_CTRL_CLR_REG(base)            ((base)->LOWPWR_CTRL_CLR)
28624 #define PMU_LOWPWR_CTRL_TOG_REG(base)            ((base)->LOWPWR_CTRL_TOG)
28625 
28626 /*!
28627  * @}
28628  */ /* end of group PMU_Register_Accessor_Macros */
28629 
28630 /* ----------------------------------------------------------------------------
28631    -- PMU Register Masks
28632    ---------------------------------------------------------------------------- */
28633 
28634 /*!
28635  * @addtogroup PMU_Register_Masks PMU Register Masks
28636  * @{
28637  */
28638 
28639 /* REG_1P1 Bit Fields */
28640 #define PMU_REG_1P1_ENABLE_LINREG_MASK           0x1u
28641 #define PMU_REG_1P1_ENABLE_LINREG_SHIFT          0
28642 #define PMU_REG_1P1_ENABLE_BO_MASK               0x2u
28643 #define PMU_REG_1P1_ENABLE_BO_SHIFT              1
28644 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK           0x4u
28645 #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT          2
28646 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK         0x8u
28647 #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT        3
28648 #define PMU_REG_1P1_BO_OFFSET_MASK               0x70u
28649 #define PMU_REG_1P1_BO_OFFSET_SHIFT              4
28650 #define PMU_REG_1P1_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P1_BO_OFFSET_SHIFT))&PMU_REG_1P1_BO_OFFSET_MASK)
28651 #define PMU_REG_1P1_OUTPUT_TRG_MASK              0x1F00u
28652 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT             8
28653 #define PMU_REG_1P1_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P1_OUTPUT_TRG_SHIFT))&PMU_REG_1P1_OUTPUT_TRG_MASK)
28654 #define PMU_REG_1P1_BO_VDD1P1_MASK               0x10000u
28655 #define PMU_REG_1P1_BO_VDD1P1_SHIFT              16
28656 #define PMU_REG_1P1_OK_VDD1P1_MASK               0x20000u
28657 #define PMU_REG_1P1_OK_VDD1P1_SHIFT              17
28658 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK      0x40000u
28659 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT     18
28660 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK      0x80000u
28661 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT     19
28662 /* REG_3P0 Bit Fields */
28663 #define PMU_REG_3P0_ENABLE_LINREG_MASK           0x1u
28664 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT          0
28665 #define PMU_REG_3P0_ENABLE_BO_MASK               0x2u
28666 #define PMU_REG_3P0_ENABLE_BO_SHIFT              1
28667 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK           0x4u
28668 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT          2
28669 #define PMU_REG_3P0_BO_OFFSET_MASK               0x70u
28670 #define PMU_REG_3P0_BO_OFFSET_SHIFT              4
28671 #define PMU_REG_3P0_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK)
28672 #define PMU_REG_3P0_VBUS_SEL_MASK                0x80u
28673 #define PMU_REG_3P0_VBUS_SEL_SHIFT               7
28674 #define PMU_REG_3P0_OUTPUT_TRG_MASK              0x1F00u
28675 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT             8
28676 #define PMU_REG_3P0_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK)
28677 #define PMU_REG_3P0_BO_VDD3P0_MASK               0x10000u
28678 #define PMU_REG_3P0_BO_VDD3P0_SHIFT              16
28679 #define PMU_REG_3P0_OK_VDD3P0_MASK               0x20000u
28680 #define PMU_REG_3P0_OK_VDD3P0_SHIFT              17
28681 /* REG_2P5 Bit Fields */
28682 #define PMU_REG_2P5_ENABLE_LINREG_MASK           0x1u
28683 #define PMU_REG_2P5_ENABLE_LINREG_SHIFT          0
28684 #define PMU_REG_2P5_ENABLE_BO_MASK               0x2u
28685 #define PMU_REG_2P5_ENABLE_BO_SHIFT              1
28686 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK           0x4u
28687 #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT          2
28688 #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK         0x8u
28689 #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT        3
28690 #define PMU_REG_2P5_BO_OFFSET_MASK               0x70u
28691 #define PMU_REG_2P5_BO_OFFSET_SHIFT              4
28692 #define PMU_REG_2P5_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_2P5_BO_OFFSET_SHIFT))&PMU_REG_2P5_BO_OFFSET_MASK)
28693 #define PMU_REG_2P5_OUTPUT_TRG_MASK              0x1F00u
28694 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT             8
28695 #define PMU_REG_2P5_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_2P5_OUTPUT_TRG_SHIFT))&PMU_REG_2P5_OUTPUT_TRG_MASK)
28696 #define PMU_REG_2P5_BO_VDD2P5_MASK               0x10000u
28697 #define PMU_REG_2P5_BO_VDD2P5_SHIFT              16
28698 #define PMU_REG_2P5_OK_VDD2P5_MASK               0x20000u
28699 #define PMU_REG_2P5_OK_VDD2P5_SHIFT              17
28700 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK      0x40000u
28701 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT     18
28702 /* REG_CORE Bit Fields */
28703 #define PMU_REG_CORE_REG0_TARG_MASK              0x1Fu
28704 #define PMU_REG_CORE_REG0_TARG_SHIFT             0
28705 #define PMU_REG_CORE_REG0_TARG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG0_TARG_SHIFT))&PMU_REG_CORE_REG0_TARG_MASK)
28706 #define PMU_REG_CORE_REG1_TARG_MASK              0x3E00u
28707 #define PMU_REG_CORE_REG1_TARG_SHIFT             9
28708 #define PMU_REG_CORE_REG1_TARG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG1_TARG_SHIFT))&PMU_REG_CORE_REG1_TARG_MASK)
28709 #define PMU_REG_CORE_REG2_TARG_MASK              0x7C0000u
28710 #define PMU_REG_CORE_REG2_TARG_SHIFT             18
28711 #define PMU_REG_CORE_REG2_TARG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG2_TARG_SHIFT))&PMU_REG_CORE_REG2_TARG_MASK)
28712 #define PMU_REG_CORE_RAMP_RATE_MASK              0x18000000u
28713 #define PMU_REG_CORE_RAMP_RATE_SHIFT             27
28714 #define PMU_REG_CORE_RAMP_RATE(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_RAMP_RATE_SHIFT))&PMU_REG_CORE_RAMP_RATE_MASK)
28715 #define PMU_REG_CORE_FET_ODRIVE_MASK             0x20000000u
28716 #define PMU_REG_CORE_FET_ODRIVE_SHIFT            29
28717 /* MISC0 Bit Fields */
28718 #define PMU_MISC0_REFTOP_PWD_MASK                0x1u
28719 #define PMU_MISC0_REFTOP_PWD_SHIFT               0
28720 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK        0x8u
28721 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT       3
28722 #define PMU_MISC0_REFTOP_VBGADJ_MASK             0x70u
28723 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT            4
28724 #define PMU_MISC0_REFTOP_VBGADJ(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_REFTOP_VBGADJ_SHIFT))&PMU_MISC0_REFTOP_VBGADJ_MASK)
28725 #define PMU_MISC0_REFTOP_VBGUP_MASK              0x80u
28726 #define PMU_MISC0_REFTOP_VBGUP_SHIFT             7
28727 #define PMU_MISC0_STOP_MODE_CONFIG_MASK          0xC00u
28728 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT         10
28729 #define PMU_MISC0_STOP_MODE_CONFIG(x)            (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_STOP_MODE_CONFIG_SHIFT))&PMU_MISC0_STOP_MODE_CONFIG_MASK)
28730 #define PMU_MISC0_RTC_RINGOSC_EN_MASK            0x1000u
28731 #define PMU_MISC0_RTC_RINGOSC_EN_SHIFT           12
28732 #define PMU_MISC0_OSC_I_MASK                     0x6000u
28733 #define PMU_MISC0_OSC_I_SHIFT                    13
28734 #define PMU_MISC0_OSC_I(x)                       (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_OSC_I_SHIFT))&PMU_MISC0_OSC_I_MASK)
28735 #define PMU_MISC0_OSC_XTALOK_MASK                0x8000u
28736 #define PMU_MISC0_OSC_XTALOK_SHIFT               15
28737 #define PMU_MISC0_OSC_XTALOK_EN_MASK             0x10000u
28738 #define PMU_MISC0_OSC_XTALOK_EN_SHIFT            16
28739 #define PMU_MISC0_CLKGATE_CTRL_MASK              0x2000000u
28740 #define PMU_MISC0_CLKGATE_CTRL_SHIFT             25
28741 #define PMU_MISC0_CLKGATE_DELAY_MASK             0x1C000000u
28742 #define PMU_MISC0_CLKGATE_DELAY_SHIFT            26
28743 #define PMU_MISC0_CLKGATE_DELAY(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_CLKGATE_DELAY_SHIFT))&PMU_MISC0_CLKGATE_DELAY_MASK)
28744 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK           0x20000000u
28745 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT          29
28746 #define PMU_MISC0_XTAL_24M_PWD_MASK              0x40000000u
28747 #define PMU_MISC0_XTAL_24M_PWD_SHIFT             30
28748 #define PMU_MISC0_VID_PLL_PREDIV_MASK            0x80000000u
28749 #define PMU_MISC0_VID_PLL_PREDIV_SHIFT           31
28750 /* MISC1 Bit Fields */
28751 #define PMU_MISC1_LVDS1_CLK_SEL_MASK             0x1Fu
28752 #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT            0
28753 #define PMU_MISC1_LVDS1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_LVDS1_CLK_SEL_MASK)
28754 #define PMU_MISC1_LVDS2_CLK_SEL_MASK             0x3E0u
28755 #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT            5
28756 #define PMU_MISC1_LVDS2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_LVDS2_CLK_SEL_MASK)
28757 #define PMU_MISC1_LVDSCLK1_OBEN_MASK             0x400u
28758 #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT            10
28759 #define PMU_MISC1_LVDSCLK2_OBEN_MASK             0x800u
28760 #define PMU_MISC1_LVDSCLK2_OBEN_SHIFT            11
28761 #define PMU_MISC1_LVDSCLK1_IBEN_MASK             0x1000u
28762 #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT            12
28763 #define PMU_MISC1_LVDSCLK2_IBEN_MASK             0x2000u
28764 #define PMU_MISC1_LVDSCLK2_IBEN_SHIFT            13
28765 #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK       0x10000u
28766 #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT      16
28767 #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK       0x20000u
28768 #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT      17
28769 #define PMU_MISC1_IRQ_TEMPPANIC_MASK             0x8000000u
28770 #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT            27
28771 #define PMU_MISC1_IRQ_TEMPLOW_MASK               0x10000000u
28772 #define PMU_MISC1_IRQ_TEMPLOW_SHIFT              28
28773 #define PMU_MISC1_IRQ_TEMPHIGH_MASK              0x20000000u
28774 #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT             29
28775 #define PMU_MISC1_IRQ_ANA_BO_MASK                0x40000000u
28776 #define PMU_MISC1_IRQ_ANA_BO_SHIFT               30
28777 #define PMU_MISC1_IRQ_DIG_BO_MASK                0x80000000u
28778 #define PMU_MISC1_IRQ_DIG_BO_SHIFT               31
28779 /* MISC1_SET Bit Fields */
28780 #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK         0x1Fu
28781 #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT        0
28782 #define PMU_MISC1_SET_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
28783 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK         0x3E0u
28784 #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT        5
28785 #define PMU_MISC1_SET_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
28786 #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK         0x400u
28787 #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT        10
28788 #define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK         0x800u
28789 #define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT        11
28790 #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK         0x1000u
28791 #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT        12
28792 #define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK         0x2000u
28793 #define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT        13
28794 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK   0x10000u
28795 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT  16
28796 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK   0x20000u
28797 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT  17
28798 #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK         0x8000000u
28799 #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT        27
28800 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK           0x10000000u
28801 #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT          28
28802 #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK          0x20000000u
28803 #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT         29
28804 #define PMU_MISC1_SET_IRQ_ANA_BO_MASK            0x40000000u
28805 #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT           30
28806 #define PMU_MISC1_SET_IRQ_DIG_BO_MASK            0x80000000u
28807 #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT           31
28808 /* MISC1_CLR Bit Fields */
28809 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK         0x1Fu
28810 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT        0
28811 #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
28812 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK         0x3E0u
28813 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT        5
28814 #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
28815 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK         0x400u
28816 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT        10
28817 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK         0x800u
28818 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT        11
28819 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK         0x1000u
28820 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT        12
28821 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK         0x2000u
28822 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT        13
28823 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK   0x10000u
28824 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT  16
28825 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK   0x20000u
28826 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT  17
28827 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK         0x8000000u
28828 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT        27
28829 #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK           0x10000000u
28830 #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT          28
28831 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK          0x20000000u
28832 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT         29
28833 #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK            0x40000000u
28834 #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT           30
28835 #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK            0x80000000u
28836 #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT           31
28837 /* MISC1_TOG Bit Fields */
28838 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK         0x1Fu
28839 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT        0
28840 #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
28841 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK         0x3E0u
28842 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT        5
28843 #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
28844 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK         0x400u
28845 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT        10
28846 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK         0x800u
28847 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT        11
28848 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK         0x1000u
28849 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT        12
28850 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK         0x2000u
28851 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT        13
28852 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK   0x10000u
28853 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT  16
28854 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK   0x20000u
28855 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT  17
28856 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK         0x8000000u
28857 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT        27
28858 #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK           0x10000000u
28859 #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT          28
28860 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK          0x20000000u
28861 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT         29
28862 #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK            0x40000000u
28863 #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT           30
28864 #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK            0x80000000u
28865 #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT           31
28866 /* MISC2 Bit Fields */
28867 #define PMU_MISC2_REG0_BO_OFFSET_MASK            0x7u
28868 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT           0
28869 #define PMU_MISC2_REG0_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_REG0_BO_OFFSET_MASK)
28870 #define PMU_MISC2_REG0_BO_STATUS_MASK            0x8u
28871 #define PMU_MISC2_REG0_BO_STATUS_SHIFT           3
28872 #define PMU_MISC2_REG0_ENABLE_BO_MASK            0x20u
28873 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT           5
28874 #define PMU_MISC2_PLL3_disable_MASK              0x80u
28875 #define PMU_MISC2_PLL3_disable_SHIFT             7
28876 #define PMU_MISC2_REG1_BO_OFFSET_MASK            0x700u
28877 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT           8
28878 #define PMU_MISC2_REG1_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_REG1_BO_OFFSET_MASK)
28879 #define PMU_MISC2_REG1_BO_STATUS_MASK            0x800u
28880 #define PMU_MISC2_REG1_BO_STATUS_SHIFT           11
28881 #define PMU_MISC2_REG1_ENABLE_BO_MASK            0x2000u
28882 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT           13
28883 #define PMU_MISC2_AUDIO_DIV_LSB_MASK             0x8000u
28884 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT            15
28885 #define PMU_MISC2_REG2_BO_OFFSET_MASK            0x70000u
28886 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT           16
28887 #define PMU_MISC2_REG2_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_REG2_BO_OFFSET_MASK)
28888 #define PMU_MISC2_REG2_BO_STATUS_MASK            0x80000u
28889 #define PMU_MISC2_REG2_BO_STATUS_SHIFT           19
28890 #define PMU_MISC2_REG2_ENABLE_BO_MASK            0x200000u
28891 #define PMU_MISC2_REG2_ENABLE_BO_SHIFT           21
28892 #define PMU_MISC2_REG2_OK_MASK                   0x400000u
28893 #define PMU_MISC2_REG2_OK_SHIFT                  22
28894 #define PMU_MISC2_AUDIO_DIV_MSB_MASK             0x800000u
28895 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT            23
28896 #define PMU_MISC2_REG0_STEP_TIME_MASK            0x3000000u
28897 #define PMU_MISC2_REG0_STEP_TIME_SHIFT           24
28898 #define PMU_MISC2_REG0_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG0_STEP_TIME_SHIFT))&PMU_MISC2_REG0_STEP_TIME_MASK)
28899 #define PMU_MISC2_REG1_STEP_TIME_MASK            0xC000000u
28900 #define PMU_MISC2_REG1_STEP_TIME_SHIFT           26
28901 #define PMU_MISC2_REG1_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG1_STEP_TIME_SHIFT))&PMU_MISC2_REG1_STEP_TIME_MASK)
28902 #define PMU_MISC2_REG2_STEP_TIME_MASK            0x30000000u
28903 #define PMU_MISC2_REG2_STEP_TIME_SHIFT           28
28904 #define PMU_MISC2_REG2_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG2_STEP_TIME_SHIFT))&PMU_MISC2_REG2_STEP_TIME_MASK)
28905 #define PMU_MISC2_VIDEO_DIV_MASK                 0xC0000000u
28906 #define PMU_MISC2_VIDEO_DIV_SHIFT                30
28907 #define PMU_MISC2_VIDEO_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_VIDEO_DIV_SHIFT))&PMU_MISC2_VIDEO_DIV_MASK)
28908 /* MISC2_SET Bit Fields */
28909 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK        0x7u
28910 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT       0
28911 #define PMU_MISC2_SET_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
28912 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK        0x8u
28913 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT       3
28914 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK        0x20u
28915 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT       5
28916 #define PMU_MISC2_SET_PLL3_disable_MASK          0x80u
28917 #define PMU_MISC2_SET_PLL3_disable_SHIFT         7
28918 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK        0x700u
28919 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT       8
28920 #define PMU_MISC2_SET_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
28921 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK        0x800u
28922 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT       11
28923 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK        0x2000u
28924 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT       13
28925 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK         0x8000u
28926 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT        15
28927 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK        0x70000u
28928 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT       16
28929 #define PMU_MISC2_SET_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
28930 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK        0x80000u
28931 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT       19
28932 #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK        0x200000u
28933 #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT       21
28934 #define PMU_MISC2_SET_REG2_OK_MASK               0x400000u
28935 #define PMU_MISC2_SET_REG2_OK_SHIFT              22
28936 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK         0x800000u
28937 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT        23
28938 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK        0x3000000u
28939 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT       24
28940 #define PMU_MISC2_SET_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG0_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG0_STEP_TIME_MASK)
28941 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK        0xC000000u
28942 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT       26
28943 #define PMU_MISC2_SET_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG1_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG1_STEP_TIME_MASK)
28944 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK        0x30000000u
28945 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT       28
28946 #define PMU_MISC2_SET_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG2_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG2_STEP_TIME_MASK)
28947 #define PMU_MISC2_SET_VIDEO_DIV_MASK             0xC0000000u
28948 #define PMU_MISC2_SET_VIDEO_DIV_SHIFT            30
28949 #define PMU_MISC2_SET_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_VIDEO_DIV_SHIFT))&PMU_MISC2_SET_VIDEO_DIV_MASK)
28950 /* MISC2_CLR Bit Fields */
28951 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK        0x7u
28952 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT       0
28953 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
28954 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK        0x8u
28955 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT       3
28956 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK        0x20u
28957 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT       5
28958 #define PMU_MISC2_CLR_PLL3_disable_MASK          0x80u
28959 #define PMU_MISC2_CLR_PLL3_disable_SHIFT         7
28960 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK        0x700u
28961 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT       8
28962 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
28963 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK        0x800u
28964 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT       11
28965 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK        0x2000u
28966 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT       13
28967 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK         0x8000u
28968 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT        15
28969 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK        0x70000u
28970 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT       16
28971 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
28972 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK        0x80000u
28973 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT       19
28974 #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK        0x200000u
28975 #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT       21
28976 #define PMU_MISC2_CLR_REG2_OK_MASK               0x400000u
28977 #define PMU_MISC2_CLR_REG2_OK_SHIFT              22
28978 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK         0x800000u
28979 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT        23
28980 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK        0x3000000u
28981 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT       24
28982 #define PMU_MISC2_CLR_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
28983 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK        0xC000000u
28984 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT       26
28985 #define PMU_MISC2_CLR_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
28986 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK        0x30000000u
28987 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT       28
28988 #define PMU_MISC2_CLR_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
28989 #define PMU_MISC2_CLR_VIDEO_DIV_MASK             0xC0000000u
28990 #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT            30
28991 #define PMU_MISC2_CLR_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_VIDEO_DIV_SHIFT))&PMU_MISC2_CLR_VIDEO_DIV_MASK)
28992 /* MISC2_TOG Bit Fields */
28993 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK        0x7u
28994 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT       0
28995 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
28996 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK        0x8u
28997 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT       3
28998 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK        0x20u
28999 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT       5
29000 #define PMU_MISC2_TOG_PLL3_disable_MASK          0x80u
29001 #define PMU_MISC2_TOG_PLL3_disable_SHIFT         7
29002 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK        0x700u
29003 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT       8
29004 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
29005 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK        0x800u
29006 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT       11
29007 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK        0x2000u
29008 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT       13
29009 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK         0x8000u
29010 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT        15
29011 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK        0x70000u
29012 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT       16
29013 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
29014 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK        0x80000u
29015 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT       19
29016 #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK        0x200000u
29017 #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT       21
29018 #define PMU_MISC2_TOG_REG2_OK_MASK               0x400000u
29019 #define PMU_MISC2_TOG_REG2_OK_SHIFT              22
29020 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK         0x800000u
29021 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT        23
29022 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK        0x3000000u
29023 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT       24
29024 #define PMU_MISC2_TOG_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
29025 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK        0xC000000u
29026 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT       26
29027 #define PMU_MISC2_TOG_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
29028 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK        0x30000000u
29029 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT       28
29030 #define PMU_MISC2_TOG_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
29031 #define PMU_MISC2_TOG_VIDEO_DIV_MASK             0xC0000000u
29032 #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT            30
29033 #define PMU_MISC2_TOG_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_VIDEO_DIV_SHIFT))&PMU_MISC2_TOG_VIDEO_DIV_MASK)
29034 /* LOWPWR_CTRL_SET Bit Fields */
29035 #define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK       0x1u
29036 #define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT      0
29037 #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK     0xEu
29038 #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT    1
29039 #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK)
29040 #define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK         0x10u
29041 #define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT        4
29042 #define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK        0x20u
29043 #define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT       5
29044 #define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK       0x40u
29045 #define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT      6
29046 #define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK 0x80u
29047 #define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT 7
29048 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK      0x100u
29049 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT     8
29050 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK      0x200u
29051 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT     9
29052 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK     0x400u
29053 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT    10
29054 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
29055 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
29056 #define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK 0x2000u
29057 #define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT 13
29058 #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK 0xC000u
29059 #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT 14
29060 #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
29061 #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK 0x10000u
29062 #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT 16
29063 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK     0x20000u
29064 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT    17
29065 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK     0x40000u
29066 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT    18
29067 /* LOWPWR_CTRL_CLR Bit Fields */
29068 #define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK       0x1u
29069 #define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT      0
29070 #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK     0xEu
29071 #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT    1
29072 #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK)
29073 #define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK         0x10u
29074 #define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT        4
29075 #define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK        0x20u
29076 #define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT       5
29077 #define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK       0x40u
29078 #define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT      6
29079 #define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK 0x80u
29080 #define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT 7
29081 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK      0x100u
29082 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT     8
29083 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK      0x200u
29084 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT     9
29085 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK     0x400u
29086 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT    10
29087 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
29088 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
29089 #define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK 0x2000u
29090 #define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT 13
29091 #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK 0xC000u
29092 #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT 14
29093 #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
29094 #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK 0x10000u
29095 #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT 16
29096 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK     0x20000u
29097 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT    17
29098 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK     0x40000u
29099 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT    18
29100 /* LOWPWR_CTRL_TOG Bit Fields */
29101 #define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK       0x1u
29102 #define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT      0
29103 #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK     0xEu
29104 #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT    1
29105 #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK)
29106 #define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK         0x10u
29107 #define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT        4
29108 #define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK        0x20u
29109 #define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT       5
29110 #define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK       0x40u
29111 #define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT      6
29112 #define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK 0x80u
29113 #define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT 7
29114 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK      0x100u
29115 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT     8
29116 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK      0x200u
29117 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT     9
29118 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK     0x400u
29119 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT    10
29120 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
29121 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
29122 #define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK 0x2000u
29123 #define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT 13
29124 #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK 0xC000u
29125 #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT 14
29126 #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
29127 #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK 0x10000u
29128 #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT 16
29129 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK     0x20000u
29130 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT    17
29131 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK     0x40000u
29132 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT    18
29133 
29134 /*!
29135  * @}
29136  */ /* end of group PMU_Register_Masks */
29137 
29138 /* PMU - Peripheral instance base addresses */
29139 /** Peripheral PMU base address */
29140 #define PMU_BASE                                 (0x420C8000u)
29141 /** Peripheral PMU base pointer */
29142 #define PMU                                      ((PMU_Type *)PMU_BASE)
29143 #define PMU_BASE_PTR                             (PMU)
29144 /** Array initializer of PMU peripheral base addresses */
29145 #define PMU_BASE_ADDRS                           { PMU_BASE }
29146 /** Array initializer of PMU peripheral base pointers */
29147 #define PMU_BASE_PTRS                            { PMU }
29148 /** Interrupt vectors for the PMU peripheral type */
29149 #define PMU_IRQS                                 { PMU1_IRQn }
29150 
29151 /* ----------------------------------------------------------------------------
29152    -- PMU - Register accessor macros
29153    ---------------------------------------------------------------------------- */
29154 
29155 /*!
29156  * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros
29157  * @{
29158  */
29159 
29160 /* PMU - Register instance definitions */
29161 /* PMU */
29162 #define PMU_REG_1P1                              PMU_REG_1P1_REG(PMU_BASE_PTR)
29163 #define PMU_REG_3P0                              PMU_REG_3P0_REG(PMU_BASE_PTR)
29164 #define PMU_REG_2P5                              PMU_REG_2P5_REG(PMU_BASE_PTR)
29165 #define PMU_REG_CORE                             PMU_REG_CORE_REG(PMU_BASE_PTR)
29166 #define PMU_MISC0                                PMU_MISC0_REG(PMU_BASE_PTR)
29167 #define PMU_MISC1                                PMU_MISC1_REG(PMU_BASE_PTR)
29168 #define PMU_MISC1_SET                            PMU_MISC1_SET_REG(PMU_BASE_PTR)
29169 #define PMU_MISC1_CLR                            PMU_MISC1_CLR_REG(PMU_BASE_PTR)
29170 #define PMU_MISC1_TOG                            PMU_MISC1_TOG_REG(PMU_BASE_PTR)
29171 #define PMU_MISC2                                PMU_MISC2_REG(PMU_BASE_PTR)
29172 #define PMU_MISC2_SET                            PMU_MISC2_SET_REG(PMU_BASE_PTR)
29173 #define PMU_MISC2_CLR                            PMU_MISC2_CLR_REG(PMU_BASE_PTR)
29174 #define PMU_MISC2_TOG                            PMU_MISC2_TOG_REG(PMU_BASE_PTR)
29175 #define PMU_LOWPWR_CTRL_SET                      PMU_LOWPWR_CTRL_SET_REG(PMU_BASE_PTR)
29176 #define PMU_LOWPWR_CTRL_CLR                      PMU_LOWPWR_CTRL_CLR_REG(PMU_BASE_PTR)
29177 #define PMU_LOWPWR_CTRL_TOG                      PMU_LOWPWR_CTRL_TOG_REG(PMU_BASE_PTR)
29178 
29179 /*!
29180  * @}
29181  */ /* end of group PMU_Register_Accessor_Macros */
29182 
29183 /*!
29184  * @}
29185  */ /* end of group PMU_Peripheral */
29186 
29187 /* ----------------------------------------------------------------------------
29188    -- PWM Peripheral Access Layer
29189    ---------------------------------------------------------------------------- */
29190 
29191 /*!
29192  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
29193  * @{
29194  */
29195 
29196 /** PWM - Register Layout Typedef */
29197 typedef struct {
29198   __IO  uint32_t PWMCR;                                  /**< PWM Control Register, offset: 0x0 */
29199   __IO  uint32_t PWMSR;                                  /**< PWM Status Register, offset: 0x4 */
29200   __IO  uint32_t PWMIR;                                  /**< PWM Interrupt Register, offset: 0x8 */
29201   __IO  uint32_t PWMSAR;                                 /**< PWM Sample Register, offset: 0xC */
29202   __IO  uint32_t PWMPR;                                  /**< PWM Period Register, offset: 0x10 */
29203   __I   uint32_t PWMCNR;                                 /**< PWM Counter Register, offset: 0x14 */
29204 } PWM_Type, *PWM_MemMapPtr;
29205 
29206 /* ----------------------------------------------------------------------------
29207    -- PWM - Register accessor macros
29208    ---------------------------------------------------------------------------- */
29209 
29210 /*!
29211  * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros
29212  * @{
29213  */
29214 
29215 /* PWM - Register accessors */
29216 #define PWM_PWMCR_REG(base)                      ((base)->PWMCR)
29217 #define PWM_PWMSR_REG(base)                      ((base)->PWMSR)
29218 #define PWM_PWMIR_REG(base)                      ((base)->PWMIR)
29219 #define PWM_PWMSAR_REG(base)                     ((base)->PWMSAR)
29220 #define PWM_PWMPR_REG(base)                      ((base)->PWMPR)
29221 #define PWM_PWMCNR_REG(base)                     ((base)->PWMCNR)
29222 
29223 /*!
29224  * @}
29225  */ /* end of group PWM_Register_Accessor_Macros */
29226 
29227 /* ----------------------------------------------------------------------------
29228    -- PWM Register Masks
29229    ---------------------------------------------------------------------------- */
29230 
29231 /*!
29232  * @addtogroup PWM_Register_Masks PWM Register Masks
29233  * @{
29234  */
29235 
29236 /* PWMCR Bit Fields */
29237 #define PWM_PWMCR_EN_MASK                        0x1u
29238 #define PWM_PWMCR_EN_SHIFT                       0
29239 #define PWM_PWMCR_REPEAT_MASK                    0x6u
29240 #define PWM_PWMCR_REPEAT_SHIFT                   1
29241 #define PWM_PWMCR_REPEAT(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_REPEAT_SHIFT))&PWM_PWMCR_REPEAT_MASK)
29242 #define PWM_PWMCR_SWR_MASK                       0x8u
29243 #define PWM_PWMCR_SWR_SHIFT                      3
29244 #define PWM_PWMCR_PRESCALER_MASK                 0xFFF0u
29245 #define PWM_PWMCR_PRESCALER_SHIFT                4
29246 #define PWM_PWMCR_PRESCALER(x)                   (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_PRESCALER_SHIFT))&PWM_PWMCR_PRESCALER_MASK)
29247 #define PWM_PWMCR_CLKSRC_MASK                    0x30000u
29248 #define PWM_PWMCR_CLKSRC_SHIFT                   16
29249 #define PWM_PWMCR_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_CLKSRC_SHIFT))&PWM_PWMCR_CLKSRC_MASK)
29250 #define PWM_PWMCR_POUTC_MASK                     0xC0000u
29251 #define PWM_PWMCR_POUTC_SHIFT                    18
29252 #define PWM_PWMCR_POUTC(x)                       (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_POUTC_SHIFT))&PWM_PWMCR_POUTC_MASK)
29253 #define PWM_PWMCR_HCTR_MASK                      0x100000u
29254 #define PWM_PWMCR_HCTR_SHIFT                     20
29255 #define PWM_PWMCR_BCTR_MASK                      0x200000u
29256 #define PWM_PWMCR_BCTR_SHIFT                     21
29257 #define PWM_PWMCR_DBGEN_MASK                     0x400000u
29258 #define PWM_PWMCR_DBGEN_SHIFT                    22
29259 #define PWM_PWMCR_WAITEN_MASK                    0x800000u
29260 #define PWM_PWMCR_WAITEN_SHIFT                   23
29261 #define PWM_PWMCR_DOZEN_MASK                     0x1000000u
29262 #define PWM_PWMCR_DOZEN_SHIFT                    24
29263 #define PWM_PWMCR_STOPEN_MASK                    0x2000000u
29264 #define PWM_PWMCR_STOPEN_SHIFT                   25
29265 #define PWM_PWMCR_FWM_MASK                       0xC000000u
29266 #define PWM_PWMCR_FWM_SHIFT                      26
29267 #define PWM_PWMCR_FWM(x)                         (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_FWM_SHIFT))&PWM_PWMCR_FWM_MASK)
29268 /* PWMSR Bit Fields */
29269 #define PWM_PWMSR_FIFOAV_MASK                    0x7u
29270 #define PWM_PWMSR_FIFOAV_SHIFT                   0
29271 #define PWM_PWMSR_FIFOAV(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMSR_FIFOAV_SHIFT))&PWM_PWMSR_FIFOAV_MASK)
29272 #define PWM_PWMSR_FE_MASK                        0x8u
29273 #define PWM_PWMSR_FE_SHIFT                       3
29274 #define PWM_PWMSR_ROV_MASK                       0x10u
29275 #define PWM_PWMSR_ROV_SHIFT                      4
29276 #define PWM_PWMSR_CMP_MASK                       0x20u
29277 #define PWM_PWMSR_CMP_SHIFT                      5
29278 #define PWM_PWMSR_FWE_MASK                       0x40u
29279 #define PWM_PWMSR_FWE_SHIFT                      6
29280 /* PWMIR Bit Fields */
29281 #define PWM_PWMIR_FIE_MASK                       0x1u
29282 #define PWM_PWMIR_FIE_SHIFT                      0
29283 #define PWM_PWMIR_RIE_MASK                       0x2u
29284 #define PWM_PWMIR_RIE_SHIFT                      1
29285 #define PWM_PWMIR_CIE_MASK                       0x4u
29286 #define PWM_PWMIR_CIE_SHIFT                      2
29287 /* PWMSAR Bit Fields */
29288 #define PWM_PWMSAR_SAMPLE_MASK                   0xFFFFu
29289 #define PWM_PWMSAR_SAMPLE_SHIFT                  0
29290 #define PWM_PWMSAR_SAMPLE(x)                     (((uint32_t)(((uint32_t)(x))<<PWM_PWMSAR_SAMPLE_SHIFT))&PWM_PWMSAR_SAMPLE_MASK)
29291 /* PWMPR Bit Fields */
29292 #define PWM_PWMPR_PERIOD_MASK                    0xFFFFu
29293 #define PWM_PWMPR_PERIOD_SHIFT                   0
29294 #define PWM_PWMPR_PERIOD(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMPR_PERIOD_SHIFT))&PWM_PWMPR_PERIOD_MASK)
29295 /* PWMCNR Bit Fields */
29296 #define PWM_PWMCNR_COUNT_MASK                    0xFFFFu
29297 #define PWM_PWMCNR_COUNT_SHIFT                   0
29298 #define PWM_PWMCNR_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<PWM_PWMCNR_COUNT_SHIFT))&PWM_PWMCNR_COUNT_MASK)
29299 
29300 /*!
29301  * @}
29302  */ /* end of group PWM_Register_Masks */
29303 
29304 /* PWM - Peripheral instance base addresses */
29305 /** Peripheral PWM1 base address */
29306 #define PWM1_BASE                                (0x42080000u)
29307 /** Peripheral PWM1 base pointer */
29308 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
29309 #define PWM1_BASE_PTR                            (PWM1)
29310 /** Peripheral PWM2 base address */
29311 #define PWM2_BASE                                (0x42084000u)
29312 /** Peripheral PWM2 base pointer */
29313 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
29314 #define PWM2_BASE_PTR                            (PWM2)
29315 /** Peripheral PWM3 base address */
29316 #define PWM3_BASE                                (0x42088000u)
29317 /** Peripheral PWM3 base pointer */
29318 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
29319 #define PWM3_BASE_PTR                            (PWM3)
29320 /** Peripheral PWM4 base address */
29321 #define PWM4_BASE                                (0x4208C000u)
29322 /** Peripheral PWM4 base pointer */
29323 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
29324 #define PWM4_BASE_PTR                            (PWM4)
29325 /** Peripheral PWM5 base address */
29326 #define PWM5_BASE                                (0x422A4000u)
29327 /** Peripheral PWM5 base pointer */
29328 #define PWM5                                     ((PWM_Type *)PWM5_BASE)
29329 #define PWM5_BASE_PTR                            (PWM5)
29330 /** Peripheral PWM6 base address */
29331 #define PWM6_BASE                                (0x422A8000u)
29332 /** Peripheral PWM6 base pointer */
29333 #define PWM6                                     ((PWM_Type *)PWM6_BASE)
29334 #define PWM6_BASE_PTR                            (PWM6)
29335 /** Peripheral PWM7 base address */
29336 #define PWM7_BASE                                (0x422AC000u)
29337 /** Peripheral PWM7 base pointer */
29338 #define PWM7                                     ((PWM_Type *)PWM7_BASE)
29339 #define PWM7_BASE_PTR                            (PWM7)
29340 /** Peripheral PWM8 base address */
29341 #define PWM8_BASE                                (0x422B0000u)
29342 /** Peripheral PWM8 base pointer */
29343 #define PWM8                                     ((PWM_Type *)PWM8_BASE)
29344 #define PWM8_BASE_PTR                            (PWM8)
29345 /** Array initializer of PWM peripheral base addresses */
29346 #define PWM_BASE_ADDRS                           { PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE }
29347 /** Array initializer of PWM peripheral base pointers */
29348 #define PWM_BASE_PTRS                            { PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 }
29349 
29350 /* ----------------------------------------------------------------------------
29351    -- PWM - Register accessor macros
29352    ---------------------------------------------------------------------------- */
29353 
29354 /*!
29355  * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros
29356  * @{
29357  */
29358 
29359 /* PWM - Register instance definitions */
29360 /* PWM1 */
29361 #define PWM1_PWMCR                               PWM_PWMCR_REG(PWM1_BASE_PTR)
29362 #define PWM1_PWMSR                               PWM_PWMSR_REG(PWM1_BASE_PTR)
29363 #define PWM1_PWMIR                               PWM_PWMIR_REG(PWM1_BASE_PTR)
29364 #define PWM1_PWMSAR                              PWM_PWMSAR_REG(PWM1_BASE_PTR)
29365 #define PWM1_PWMPR                               PWM_PWMPR_REG(PWM1_BASE_PTR)
29366 #define PWM1_PWMCNR                              PWM_PWMCNR_REG(PWM1_BASE_PTR)
29367 /* PWM2 */
29368 #define PWM2_PWMCR                               PWM_PWMCR_REG(PWM2_BASE_PTR)
29369 #define PWM2_PWMSR                               PWM_PWMSR_REG(PWM2_BASE_PTR)
29370 #define PWM2_PWMIR                               PWM_PWMIR_REG(PWM2_BASE_PTR)
29371 #define PWM2_PWMSAR                              PWM_PWMSAR_REG(PWM2_BASE_PTR)
29372 #define PWM2_PWMPR                               PWM_PWMPR_REG(PWM2_BASE_PTR)
29373 #define PWM2_PWMCNR                              PWM_PWMCNR_REG(PWM2_BASE_PTR)
29374 /* PWM3 */
29375 #define PWM3_PWMCR                               PWM_PWMCR_REG(PWM3_BASE_PTR)
29376 #define PWM3_PWMSR                               PWM_PWMSR_REG(PWM3_BASE_PTR)
29377 #define PWM3_PWMIR                               PWM_PWMIR_REG(PWM3_BASE_PTR)
29378 #define PWM3_PWMSAR                              PWM_PWMSAR_REG(PWM3_BASE_PTR)
29379 #define PWM3_PWMPR                               PWM_PWMPR_REG(PWM3_BASE_PTR)
29380 #define PWM3_PWMCNR                              PWM_PWMCNR_REG(PWM3_BASE_PTR)
29381 /* PWM4 */
29382 #define PWM4_PWMCR                               PWM_PWMCR_REG(PWM4_BASE_PTR)
29383 #define PWM4_PWMSR                               PWM_PWMSR_REG(PWM4_BASE_PTR)
29384 #define PWM4_PWMIR                               PWM_PWMIR_REG(PWM4_BASE_PTR)
29385 #define PWM4_PWMSAR                              PWM_PWMSAR_REG(PWM4_BASE_PTR)
29386 #define PWM4_PWMPR                               PWM_PWMPR_REG(PWM4_BASE_PTR)
29387 #define PWM4_PWMCNR                              PWM_PWMCNR_REG(PWM4_BASE_PTR)
29388 /* PWM5 */
29389 #define PWM5_PWMCR                               PWM_PWMCR_REG(PWM5_BASE_PTR)
29390 #define PWM5_PWMSR                               PWM_PWMSR_REG(PWM5_BASE_PTR)
29391 #define PWM5_PWMIR                               PWM_PWMIR_REG(PWM5_BASE_PTR)
29392 #define PWM5_PWMSAR                              PWM_PWMSAR_REG(PWM5_BASE_PTR)
29393 #define PWM5_PWMPR                               PWM_PWMPR_REG(PWM5_BASE_PTR)
29394 #define PWM5_PWMCNR                              PWM_PWMCNR_REG(PWM5_BASE_PTR)
29395 /* PWM6 */
29396 #define PWM6_PWMCR                               PWM_PWMCR_REG(PWM6_BASE_PTR)
29397 #define PWM6_PWMSR                               PWM_PWMSR_REG(PWM6_BASE_PTR)
29398 #define PWM6_PWMIR                               PWM_PWMIR_REG(PWM6_BASE_PTR)
29399 #define PWM6_PWMSAR                              PWM_PWMSAR_REG(PWM6_BASE_PTR)
29400 #define PWM6_PWMPR                               PWM_PWMPR_REG(PWM6_BASE_PTR)
29401 #define PWM6_PWMCNR                              PWM_PWMCNR_REG(PWM6_BASE_PTR)
29402 /* PWM7 */
29403 #define PWM7_PWMCR                               PWM_PWMCR_REG(PWM7_BASE_PTR)
29404 #define PWM7_PWMSR                               PWM_PWMSR_REG(PWM7_BASE_PTR)
29405 #define PWM7_PWMIR                               PWM_PWMIR_REG(PWM7_BASE_PTR)
29406 #define PWM7_PWMSAR                              PWM_PWMSAR_REG(PWM7_BASE_PTR)
29407 #define PWM7_PWMPR                               PWM_PWMPR_REG(PWM7_BASE_PTR)
29408 #define PWM7_PWMCNR                              PWM_PWMCNR_REG(PWM7_BASE_PTR)
29409 /* PWM8 */
29410 #define PWM8_PWMCR                               PWM_PWMCR_REG(PWM8_BASE_PTR)
29411 #define PWM8_PWMSR                               PWM_PWMSR_REG(PWM8_BASE_PTR)
29412 #define PWM8_PWMIR                               PWM_PWMIR_REG(PWM8_BASE_PTR)
29413 #define PWM8_PWMSAR                              PWM_PWMSAR_REG(PWM8_BASE_PTR)
29414 #define PWM8_PWMPR                               PWM_PWMPR_REG(PWM8_BASE_PTR)
29415 #define PWM8_PWMCNR                              PWM_PWMCNR_REG(PWM8_BASE_PTR)
29416 
29417 /*!
29418  * @}
29419  */ /* end of group PWM_Register_Accessor_Macros */
29420 
29421 /*!
29422  * @}
29423  */ /* end of group PWM_Peripheral */
29424 
29425 /* ----------------------------------------------------------------------------
29426    -- PXP Peripheral Access Layer
29427    ---------------------------------------------------------------------------- */
29428 
29429 /*!
29430  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
29431  * @{
29432  */
29433 
29434 /** PXP - Register Layout Typedef */
29435 typedef struct {
29436   __IO  uint32_t CTRL;                                   /**< Control Register 0, offset: 0x0 */
29437   uint8_t RESERVED_0[12];
29438   __IO  uint32_t STAT;                                   /**< Status Register, offset: 0x10 */
29439   uint8_t RESERVED_1[12];
29440   __IO  uint32_t OUT_CTRL;                               /**< Output Buffer Control Register, offset: 0x20 */
29441   uint8_t RESERVED_2[12];
29442   __IO  uint32_t OUT_BUF;                                /**< Output Frame Buffer Pointer, offset: 0x30 */
29443   uint8_t RESERVED_3[12];
29444   __IO  uint32_t OUT_BUF2;                               /**< Output Frame Buffer Pointer #2, offset: 0x40 */
29445   uint8_t RESERVED_4[12];
29446   __IO  uint32_t OUT_PITCH;                              /**< Output Buffer Pitch, offset: 0x50 */
29447   uint8_t RESERVED_5[12];
29448   __IO  uint32_t OUT_LRC;                                /**< Output Surface Lower Right Coordinate, offset: 0x60 */
29449   uint8_t RESERVED_6[12];
29450   __IO  uint32_t OUT_PS_ULC;                             /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
29451   uint8_t RESERVED_7[12];
29452   __IO  uint32_t OUT_PS_LRC;                             /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
29453   uint8_t RESERVED_8[12];
29454   __IO  uint32_t OUT_AS_ULC;                             /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
29455   uint8_t RESERVED_9[12];
29456   __IO  uint32_t OUT_AS_LRC;                             /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
29457   uint8_t RESERVED_10[12];
29458   __IO  uint32_t PS_CTRL;                                /**< Processed Surface (PS) Control Register, offset: 0xB0 */
29459   uint8_t RESERVED_11[12];
29460   __IO  uint32_t PS_BUF;                                 /**< PS Input Buffer Address, offset: 0xC0 */
29461   uint8_t RESERVED_12[12];
29462   __IO  uint32_t PS_UBUF;                                /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
29463   uint8_t RESERVED_13[12];
29464   __IO  uint32_t PS_VBUF;                                /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
29465   uint8_t RESERVED_14[12];
29466   __IO  uint32_t PS_PITCH;                               /**< Processed Surface Pitch, offset: 0xF0 */
29467   uint8_t RESERVED_15[12];
29468   __IO  uint32_t PS_BACKGROUND;                          /**< PS Background Color, offset: 0x100 */
29469   uint8_t RESERVED_16[12];
29470   __IO  uint32_t PS_SCALE;                               /**< PS Scale Factor Register, offset: 0x110 */
29471   uint8_t RESERVED_17[12];
29472   __IO  uint32_t PS_OFFSET;                              /**< PS Scale Offset Register, offset: 0x120 */
29473   uint8_t RESERVED_18[12];
29474   __IO  uint32_t PS_CLRKEYLOW;                           /**< PS Color Key Low, offset: 0x130 */
29475   uint8_t RESERVED_19[12];
29476   __IO  uint32_t PS_CLRKEYHIGH;                          /**< PS Color Key High, offset: 0x140 */
29477   uint8_t RESERVED_20[12];
29478   __IO  uint32_t AS_CTRL;                                /**< Alpha Surface Control, offset: 0x150 */
29479   uint8_t RESERVED_21[12];
29480   __IO  uint32_t AS_BUF;                                 /**< Alpha Surface Buffer Pointer, offset: 0x160 */
29481   uint8_t RESERVED_22[12];
29482   __IO  uint32_t AS_PITCH;                               /**< Alpha Surface Pitch, offset: 0x170 */
29483   uint8_t RESERVED_23[12];
29484   __IO  uint32_t AS_CLRKEYLOW;                           /**< Overlay Color Key Low, offset: 0x180 */
29485   uint8_t RESERVED_24[12];
29486   __IO  uint32_t AS_CLRKEYHIGH;                          /**< Overlay Color Key High, offset: 0x190 */
29487   uint8_t RESERVED_25[12];
29488   __IO  uint32_t CSC1_COEF0;                             /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
29489   uint8_t RESERVED_26[12];
29490   __IO  uint32_t CSC1_COEF1;                             /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
29491   uint8_t RESERVED_27[12];
29492   __IO  uint32_t CSC1_COEF2;                             /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
29493   uint8_t RESERVED_28[12];
29494   __IO  uint32_t CSC2_CTRL;                              /**< Color Space Conversion Control Register., offset: 0x1D0 */
29495   uint8_t RESERVED_29[12];
29496   __IO  uint32_t CSC2_COEF0;                             /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */
29497   uint8_t RESERVED_30[12];
29498   __IO  uint32_t CSC2_COEF1;                             /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */
29499   uint8_t RESERVED_31[12];
29500   __IO  uint32_t CSC2_COEF2;                             /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */
29501   uint8_t RESERVED_32[12];
29502   __IO  uint32_t CSC2_COEF3;                             /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */
29503   uint8_t RESERVED_33[12];
29504   __IO  uint32_t CSC2_COEF4;                             /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */
29505   uint8_t RESERVED_34[12];
29506   __IO  uint32_t CSC2_COEF5;                             /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */
29507   uint8_t RESERVED_35[12];
29508   __IO  uint32_t LUT_CTRL;                               /**< Lookup Table Control Register., offset: 0x240 */
29509   uint8_t RESERVED_36[12];
29510   __IO  uint32_t LUT_ADDR;                               /**< Lookup Table Control Register., offset: 0x250 */
29511   uint8_t RESERVED_37[12];
29512   __IO  uint32_t LUT_DATA;                               /**< Lookup Table Data Register., offset: 0x260 */
29513   uint8_t RESERVED_38[12];
29514   __IO  uint32_t LUT_EXTMEM;                             /**< Lookup Table External Memory Address Register., offset: 0x270 */
29515   uint8_t RESERVED_39[12];
29516   __IO  uint32_t CFA;                                    /**< Color Filter Array Register., offset: 0x280 */
29517   uint8_t RESERVED_40[12];
29518   __IO  uint32_t HIST_CTRL;                              /**< Histogram Control Register., offset: 0x290 */
29519   uint8_t RESERVED_41[12];
29520   __IO  uint32_t HIST2_PARAM;                            /**< 2-level Histogram Parameter Register., offset: 0x2A0 */
29521   uint8_t RESERVED_42[12];
29522   __IO  uint32_t HIST4_PARAM;                            /**< 4-level Histogram Parameter Register., offset: 0x2B0 */
29523   uint8_t RESERVED_43[12];
29524   __IO  uint32_t HIST8_PARAM0;                           /**< 8-level Histogram Parameter 0 Register., offset: 0x2C0 */
29525   uint8_t RESERVED_44[12];
29526   __IO  uint32_t HIST8_PARAM1;                           /**< 8-level Histogram Parameter 1 Register., offset: 0x2D0 */
29527   uint8_t RESERVED_45[12];
29528   __IO  uint32_t HIST16_PARAM0;                          /**< 16-level Histogram Parameter 0 Register., offset: 0x2E0 */
29529   uint8_t RESERVED_46[12];
29530   __IO  uint32_t HIST16_PARAM1;                          /**< 16-level Histogram Parameter 1 Register., offset: 0x2F0 */
29531   uint8_t RESERVED_47[12];
29532   __IO  uint32_t HIST16_PARAM2;                          /**< 16-level Histogram Parameter 2 Register., offset: 0x300 */
29533   uint8_t RESERVED_48[12];
29534   __IO  uint32_t HIST16_PARAM3;                          /**< 16-level Histogram Parameter 3 Register., offset: 0x310 */
29535   uint8_t RESERVED_49[12];
29536   __IO  uint32_t POWER;                                  /**< PXP Power Control Register., offset: 0x320 */
29537   uint8_t RESERVED_50[220];
29538   __IO  uint32_t NEXT;                                   /**< Next Frame Pointer, offset: 0x400 */
29539 } PXP_Type, *PXP_MemMapPtr;
29540 
29541 /* ----------------------------------------------------------------------------
29542    -- PXP - Register accessor macros
29543    ---------------------------------------------------------------------------- */
29544 
29545 /*!
29546  * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros
29547  * @{
29548  */
29549 
29550 /* PXP - Register accessors */
29551 #define PXP_CTRL_REG(base)                       ((base)->CTRL)
29552 #define PXP_STAT_REG(base)                       ((base)->STAT)
29553 #define PXP_OUT_CTRL_REG(base)                   ((base)->OUT_CTRL)
29554 #define PXP_OUT_BUF_REG(base)                    ((base)->OUT_BUF)
29555 #define PXP_OUT_BUF2_REG(base)                   ((base)->OUT_BUF2)
29556 #define PXP_OUT_PITCH_REG(base)                  ((base)->OUT_PITCH)
29557 #define PXP_OUT_LRC_REG(base)                    ((base)->OUT_LRC)
29558 #define PXP_OUT_PS_ULC_REG(base)                 ((base)->OUT_PS_ULC)
29559 #define PXP_OUT_PS_LRC_REG(base)                 ((base)->OUT_PS_LRC)
29560 #define PXP_OUT_AS_ULC_REG(base)                 ((base)->OUT_AS_ULC)
29561 #define PXP_OUT_AS_LRC_REG(base)                 ((base)->OUT_AS_LRC)
29562 #define PXP_PS_CTRL_REG(base)                    ((base)->PS_CTRL)
29563 #define PXP_PS_BUF_REG(base)                     ((base)->PS_BUF)
29564 #define PXP_PS_UBUF_REG(base)                    ((base)->PS_UBUF)
29565 #define PXP_PS_VBUF_REG(base)                    ((base)->PS_VBUF)
29566 #define PXP_PS_PITCH_REG(base)                   ((base)->PS_PITCH)
29567 #define PXP_PS_BACKGROUND_REG(base)              ((base)->PS_BACKGROUND)
29568 #define PXP_PS_SCALE_REG(base)                   ((base)->PS_SCALE)
29569 #define PXP_PS_OFFSET_REG(base)                  ((base)->PS_OFFSET)
29570 #define PXP_PS_CLRKEYLOW_REG(base)               ((base)->PS_CLRKEYLOW)
29571 #define PXP_PS_CLRKEYHIGH_REG(base)              ((base)->PS_CLRKEYHIGH)
29572 #define PXP_AS_CTRL_REG(base)                    ((base)->AS_CTRL)
29573 #define PXP_AS_BUF_REG(base)                     ((base)->AS_BUF)
29574 #define PXP_AS_PITCH_REG(base)                   ((base)->AS_PITCH)
29575 #define PXP_AS_CLRKEYLOW_REG(base)               ((base)->AS_CLRKEYLOW)
29576 #define PXP_AS_CLRKEYHIGH_REG(base)              ((base)->AS_CLRKEYHIGH)
29577 #define PXP_CSC1_COEF0_REG(base)                 ((base)->CSC1_COEF0)
29578 #define PXP_CSC1_COEF1_REG(base)                 ((base)->CSC1_COEF1)
29579 #define PXP_CSC1_COEF2_REG(base)                 ((base)->CSC1_COEF2)
29580 #define PXP_CSC2_CTRL_REG(base)                  ((base)->CSC2_CTRL)
29581 #define PXP_CSC2_COEF0_REG(base)                 ((base)->CSC2_COEF0)
29582 #define PXP_CSC2_COEF1_REG(base)                 ((base)->CSC2_COEF1)
29583 #define PXP_CSC2_COEF2_REG(base)                 ((base)->CSC2_COEF2)
29584 #define PXP_CSC2_COEF3_REG(base)                 ((base)->CSC2_COEF3)
29585 #define PXP_CSC2_COEF4_REG(base)                 ((base)->CSC2_COEF4)
29586 #define PXP_CSC2_COEF5_REG(base)                 ((base)->CSC2_COEF5)
29587 #define PXP_LUT_CTRL_REG(base)                   ((base)->LUT_CTRL)
29588 #define PXP_LUT_ADDR_REG(base)                   ((base)->LUT_ADDR)
29589 #define PXP_LUT_DATA_REG(base)                   ((base)->LUT_DATA)
29590 #define PXP_LUT_EXTMEM_REG(base)                 ((base)->LUT_EXTMEM)
29591 #define PXP_CFA_REG(base)                        ((base)->CFA)
29592 #define PXP_HIST_CTRL_REG(base)                  ((base)->HIST_CTRL)
29593 #define PXP_HIST2_PARAM_REG(base)                ((base)->HIST2_PARAM)
29594 #define PXP_HIST4_PARAM_REG(base)                ((base)->HIST4_PARAM)
29595 #define PXP_HIST8_PARAM0_REG(base)               ((base)->HIST8_PARAM0)
29596 #define PXP_HIST8_PARAM1_REG(base)               ((base)->HIST8_PARAM1)
29597 #define PXP_HIST16_PARAM0_REG(base)              ((base)->HIST16_PARAM0)
29598 #define PXP_HIST16_PARAM1_REG(base)              ((base)->HIST16_PARAM1)
29599 #define PXP_HIST16_PARAM2_REG(base)              ((base)->HIST16_PARAM2)
29600 #define PXP_HIST16_PARAM3_REG(base)              ((base)->HIST16_PARAM3)
29601 #define PXP_POWER_REG(base)                      ((base)->POWER)
29602 #define PXP_NEXT_REG(base)                       ((base)->NEXT)
29603 
29604 /*!
29605  * @}
29606  */ /* end of group PXP_Register_Accessor_Macros */
29607 
29608 /* ----------------------------------------------------------------------------
29609    -- PXP Register Masks
29610    ---------------------------------------------------------------------------- */
29611 
29612 /*!
29613  * @addtogroup PXP_Register_Masks PXP Register Masks
29614  * @{
29615  */
29616 
29617 /* CTRL Bit Fields */
29618 #define PXP_CTRL_ENABLE_MASK                     0x1u
29619 #define PXP_CTRL_ENABLE_SHIFT                    0
29620 #define PXP_CTRL_IRQ_ENABLE_MASK                 0x2u
29621 #define PXP_CTRL_IRQ_ENABLE_SHIFT                1
29622 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            0x4u
29623 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           2
29624 #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK         0x8u
29625 #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT        3
29626 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK       0x10u
29627 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT      4
29628 #define PXP_CTRL_RSVD0_MASK                      0xE0u
29629 #define PXP_CTRL_RSVD0_SHIFT                     5
29630 #define PXP_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD0_SHIFT))&PXP_CTRL_RSVD0_MASK)
29631 #define PXP_CTRL_ROTATE_MASK                     0x300u
29632 #define PXP_CTRL_ROTATE_SHIFT                    8
29633 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE_SHIFT))&PXP_CTRL_ROTATE_MASK)
29634 #define PXP_CTRL_HFLIP_MASK                      0x400u
29635 #define PXP_CTRL_HFLIP_SHIFT                     10
29636 #define PXP_CTRL_VFLIP_MASK                      0x800u
29637 #define PXP_CTRL_VFLIP_SHIFT                     11
29638 #define PXP_CTRL_RSVD1_MASK                      0x3FF000u
29639 #define PXP_CTRL_RSVD1_SHIFT                     12
29640 #define PXP_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD1_SHIFT))&PXP_CTRL_RSVD1_MASK)
29641 #define PXP_CTRL_ROT_POS_MASK                    0x400000u
29642 #define PXP_CTRL_ROT_POS_SHIFT                   22
29643 #define PXP_CTRL_BLOCK_SIZE_MASK                 0x800000u
29644 #define PXP_CTRL_BLOCK_SIZE_SHIFT                23
29645 #define PXP_CTRL_RSVD3_MASK                      0xF000000u
29646 #define PXP_CTRL_RSVD3_SHIFT                     24
29647 #define PXP_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD3_SHIFT))&PXP_CTRL_RSVD3_MASK)
29648 #define PXP_CTRL_EN_REPEAT_MASK                  0x10000000u
29649 #define PXP_CTRL_EN_REPEAT_SHIFT                 28
29650 #define PXP_CTRL_RSVD4_MASK                      0x20000000u
29651 #define PXP_CTRL_RSVD4_SHIFT                     29
29652 #define PXP_CTRL_CLKGATE_MASK                    0x40000000u
29653 #define PXP_CTRL_CLKGATE_SHIFT                   30
29654 #define PXP_CTRL_SFTRST_MASK                     0x80000000u
29655 #define PXP_CTRL_SFTRST_SHIFT                    31
29656 /* STAT Bit Fields */
29657 #define PXP_STAT_IRQ_MASK                        0x1u
29658 #define PXP_STAT_IRQ_SHIFT                       0
29659 #define PXP_STAT_AXI_WRITE_ERROR_MASK            0x2u
29660 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT           1
29661 #define PXP_STAT_AXI_READ_ERROR_MASK             0x4u
29662 #define PXP_STAT_AXI_READ_ERROR_SHIFT            2
29663 #define PXP_STAT_NEXT_IRQ_MASK                   0x8u
29664 #define PXP_STAT_NEXT_IRQ_SHIFT                  3
29665 #define PXP_STAT_AXI_ERROR_ID_MASK               0xF0u
29666 #define PXP_STAT_AXI_ERROR_ID_SHIFT              4
29667 #define PXP_STAT_AXI_ERROR_ID(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_SHIFT))&PXP_STAT_AXI_ERROR_ID_MASK)
29668 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      0x100u
29669 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     8
29670 #define PXP_STAT_RSVD2_MASK                      0xFE00u
29671 #define PXP_STAT_RSVD2_SHIFT                     9
29672 #define PXP_STAT_RSVD2(x)                        (((uint32_t)(((uint32_t)(x))<<PXP_STAT_RSVD2_SHIFT))&PXP_STAT_RSVD2_MASK)
29673 #define PXP_STAT_BLOCKY_MASK                     0xFF0000u
29674 #define PXP_STAT_BLOCKY_SHIFT                    16
29675 #define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKY_SHIFT))&PXP_STAT_BLOCKY_MASK)
29676 #define PXP_STAT_BLOCKX_MASK                     0xFF000000u
29677 #define PXP_STAT_BLOCKX_SHIFT                    24
29678 #define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKX_SHIFT))&PXP_STAT_BLOCKX_MASK)
29679 /* OUT_CTRL Bit Fields */
29680 #define PXP_OUT_CTRL_FORMAT_MASK                 0x1Fu
29681 #define PXP_OUT_CTRL_FORMAT_SHIFT                0
29682 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_OUT_CTRL_FORMAT_MASK)
29683 #define PXP_OUT_CTRL_RSVD0_MASK                  0xE0u
29684 #define PXP_OUT_CTRL_RSVD0_SHIFT                 5
29685 #define PXP_OUT_CTRL_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_OUT_CTRL_RSVD0_MASK)
29686 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      0x300u
29687 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     8
29688 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
29689 #define PXP_OUT_CTRL_RSVD1_MASK                  0x7FFC00u
29690 #define PXP_OUT_CTRL_RSVD1_SHIFT                 10
29691 #define PXP_OUT_CTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_OUT_CTRL_RSVD1_MASK)
29692 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           0x800000u
29693 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          23
29694 #define PXP_OUT_CTRL_ALPHA_MASK                  0xFF000000u
29695 #define PXP_OUT_CTRL_ALPHA_SHIFT                 24
29696 #define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_OUT_CTRL_ALPHA_MASK)
29697 /* OUT_BUF Bit Fields */
29698 #define PXP_OUT_BUF_ADDR_MASK                    0xFFFFFFFFu
29699 #define PXP_OUT_BUF_ADDR_SHIFT                   0
29700 #define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF_ADDR_SHIFT))&PXP_OUT_BUF_ADDR_MASK)
29701 /* OUT_BUF2 Bit Fields */
29702 #define PXP_OUT_BUF2_ADDR_MASK                   0xFFFFFFFFu
29703 #define PXP_OUT_BUF2_ADDR_SHIFT                  0
29704 #define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF2_ADDR_SHIFT))&PXP_OUT_BUF2_ADDR_MASK)
29705 /* OUT_PITCH Bit Fields */
29706 #define PXP_OUT_PITCH_PITCH_MASK                 0xFFFFu
29707 #define PXP_OUT_PITCH_PITCH_SHIFT                0
29708 #define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_PITCH_SHIFT))&PXP_OUT_PITCH_PITCH_MASK)
29709 #define PXP_OUT_PITCH_RSVD_MASK                  0xFFFF0000u
29710 #define PXP_OUT_PITCH_RSVD_SHIFT                 16
29711 #define PXP_OUT_PITCH_RSVD(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_RSVD_SHIFT))&PXP_OUT_PITCH_RSVD_MASK)
29712 /* OUT_LRC Bit Fields */
29713 #define PXP_OUT_LRC_Y_MASK                       0x3FFFu
29714 #define PXP_OUT_LRC_Y_SHIFT                      0
29715 #define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_Y_SHIFT))&PXP_OUT_LRC_Y_MASK)
29716 #define PXP_OUT_LRC_RSVD0_MASK                   0xC000u
29717 #define PXP_OUT_LRC_RSVD0_SHIFT                  14
29718 #define PXP_OUT_LRC_RSVD0(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD0_SHIFT))&PXP_OUT_LRC_RSVD0_MASK)
29719 #define PXP_OUT_LRC_X_MASK                       0x3FFF0000u
29720 #define PXP_OUT_LRC_X_SHIFT                      16
29721 #define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_X_SHIFT))&PXP_OUT_LRC_X_MASK)
29722 #define PXP_OUT_LRC_RSVD1_MASK                   0xC0000000u
29723 #define PXP_OUT_LRC_RSVD1_SHIFT                  30
29724 #define PXP_OUT_LRC_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD1_SHIFT))&PXP_OUT_LRC_RSVD1_MASK)
29725 /* OUT_PS_ULC Bit Fields */
29726 #define PXP_OUT_PS_ULC_Y_MASK                    0x3FFFu
29727 #define PXP_OUT_PS_ULC_Y_SHIFT                   0
29728 #define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_Y_SHIFT))&PXP_OUT_PS_ULC_Y_MASK)
29729 #define PXP_OUT_PS_ULC_RSVD0_MASK                0xC000u
29730 #define PXP_OUT_PS_ULC_RSVD0_SHIFT               14
29731 #define PXP_OUT_PS_ULC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_OUT_PS_ULC_RSVD0_MASK)
29732 #define PXP_OUT_PS_ULC_X_MASK                    0x3FFF0000u
29733 #define PXP_OUT_PS_ULC_X_SHIFT                   16
29734 #define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_X_SHIFT))&PXP_OUT_PS_ULC_X_MASK)
29735 #define PXP_OUT_PS_ULC_RSVD1_MASK                0xC0000000u
29736 #define PXP_OUT_PS_ULC_RSVD1_SHIFT               30
29737 #define PXP_OUT_PS_ULC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_OUT_PS_ULC_RSVD1_MASK)
29738 /* OUT_PS_LRC Bit Fields */
29739 #define PXP_OUT_PS_LRC_Y_MASK                    0x3FFFu
29740 #define PXP_OUT_PS_LRC_Y_SHIFT                   0
29741 #define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_Y_SHIFT))&PXP_OUT_PS_LRC_Y_MASK)
29742 #define PXP_OUT_PS_LRC_RSVD0_MASK                0xC000u
29743 #define PXP_OUT_PS_LRC_RSVD0_SHIFT               14
29744 #define PXP_OUT_PS_LRC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_OUT_PS_LRC_RSVD0_MASK)
29745 #define PXP_OUT_PS_LRC_X_MASK                    0x3FFF0000u
29746 #define PXP_OUT_PS_LRC_X_SHIFT                   16
29747 #define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_X_SHIFT))&PXP_OUT_PS_LRC_X_MASK)
29748 #define PXP_OUT_PS_LRC_RSVD1_MASK                0xC0000000u
29749 #define PXP_OUT_PS_LRC_RSVD1_SHIFT               30
29750 #define PXP_OUT_PS_LRC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_OUT_PS_LRC_RSVD1_MASK)
29751 /* OUT_AS_ULC Bit Fields */
29752 #define PXP_OUT_AS_ULC_Y_MASK                    0x3FFFu
29753 #define PXP_OUT_AS_ULC_Y_SHIFT                   0
29754 #define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_Y_SHIFT))&PXP_OUT_AS_ULC_Y_MASK)
29755 #define PXP_OUT_AS_ULC_RSVD0_MASK                0xC000u
29756 #define PXP_OUT_AS_ULC_RSVD0_SHIFT               14
29757 #define PXP_OUT_AS_ULC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_OUT_AS_ULC_RSVD0_MASK)
29758 #define PXP_OUT_AS_ULC_X_MASK                    0x3FFF0000u
29759 #define PXP_OUT_AS_ULC_X_SHIFT                   16
29760 #define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_X_SHIFT))&PXP_OUT_AS_ULC_X_MASK)
29761 #define PXP_OUT_AS_ULC_RSVD1_MASK                0xC0000000u
29762 #define PXP_OUT_AS_ULC_RSVD1_SHIFT               30
29763 #define PXP_OUT_AS_ULC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_OUT_AS_ULC_RSVD1_MASK)
29764 /* OUT_AS_LRC Bit Fields */
29765 #define PXP_OUT_AS_LRC_Y_MASK                    0x3FFFu
29766 #define PXP_OUT_AS_LRC_Y_SHIFT                   0
29767 #define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_Y_SHIFT))&PXP_OUT_AS_LRC_Y_MASK)
29768 #define PXP_OUT_AS_LRC_RSVD0_MASK                0xC000u
29769 #define PXP_OUT_AS_LRC_RSVD0_SHIFT               14
29770 #define PXP_OUT_AS_LRC_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_OUT_AS_LRC_RSVD0_MASK)
29771 #define PXP_OUT_AS_LRC_X_MASK                    0x3FFF0000u
29772 #define PXP_OUT_AS_LRC_X_SHIFT                   16
29773 #define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_X_SHIFT))&PXP_OUT_AS_LRC_X_MASK)
29774 #define PXP_OUT_AS_LRC_RSVD1_MASK                0xC0000000u
29775 #define PXP_OUT_AS_LRC_RSVD1_SHIFT               30
29776 #define PXP_OUT_AS_LRC_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_OUT_AS_LRC_RSVD1_MASK)
29777 /* PS_CTRL Bit Fields */
29778 #define PXP_PS_CTRL_FORMAT_MASK                  0x1Fu
29779 #define PXP_PS_CTRL_FORMAT_SHIFT                 0
29780 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_FORMAT_SHIFT))&PXP_PS_CTRL_FORMAT_MASK)
29781 #define PXP_PS_CTRL_WB_SWAP_MASK                 0x20u
29782 #define PXP_PS_CTRL_WB_SWAP_SHIFT                5
29783 #define PXP_PS_CTRL_RSVD0_MASK                   0xC0u
29784 #define PXP_PS_CTRL_RSVD0_SHIFT                  6
29785 #define PXP_PS_CTRL_RSVD0(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD0_SHIFT))&PXP_PS_CTRL_RSVD0_MASK)
29786 #define PXP_PS_CTRL_DECY_MASK                    0x300u
29787 #define PXP_PS_CTRL_DECY_SHIFT                   8
29788 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECY_SHIFT))&PXP_PS_CTRL_DECY_MASK)
29789 #define PXP_PS_CTRL_DECX_MASK                    0xC00u
29790 #define PXP_PS_CTRL_DECX_SHIFT                   10
29791 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECX_SHIFT))&PXP_PS_CTRL_DECX_MASK)
29792 #define PXP_PS_CTRL_RSVD1_MASK                   0xFFFFF000u
29793 #define PXP_PS_CTRL_RSVD1_SHIFT                  12
29794 #define PXP_PS_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD1_SHIFT))&PXP_PS_CTRL_RSVD1_MASK)
29795 /* PS_BUF Bit Fields */
29796 #define PXP_PS_BUF_ADDR_MASK                     0xFFFFFFFFu
29797 #define PXP_PS_BUF_ADDR_SHIFT                    0
29798 #define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_PS_BUF_ADDR_SHIFT))&PXP_PS_BUF_ADDR_MASK)
29799 /* PS_UBUF Bit Fields */
29800 #define PXP_PS_UBUF_ADDR_MASK                    0xFFFFFFFFu
29801 #define PXP_PS_UBUF_ADDR_SHIFT                   0
29802 #define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_PS_UBUF_ADDR_SHIFT))&PXP_PS_UBUF_ADDR_MASK)
29803 /* PS_VBUF Bit Fields */
29804 #define PXP_PS_VBUF_ADDR_MASK                    0xFFFFFFFFu
29805 #define PXP_PS_VBUF_ADDR_SHIFT                   0
29806 #define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_PS_VBUF_ADDR_SHIFT))&PXP_PS_VBUF_ADDR_MASK)
29807 /* PS_PITCH Bit Fields */
29808 #define PXP_PS_PITCH_PITCH_MASK                  0xFFFFu
29809 #define PXP_PS_PITCH_PITCH_SHIFT                 0
29810 #define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_PITCH_SHIFT))&PXP_PS_PITCH_PITCH_MASK)
29811 #define PXP_PS_PITCH_RSVD_MASK                   0xFFFF0000u
29812 #define PXP_PS_PITCH_RSVD_SHIFT                  16
29813 #define PXP_PS_PITCH_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_RSVD_SHIFT))&PXP_PS_PITCH_RSVD_MASK)
29814 /* PS_BACKGROUND Bit Fields */
29815 #define PXP_PS_BACKGROUND_COLOR_MASK             0xFFFFFFu
29816 #define PXP_PS_BACKGROUND_COLOR_SHIFT            0
29817 #define PXP_PS_BACKGROUND_COLOR(x)               (((uint32_t)(((uint32_t)(x))<<PXP_PS_BACKGROUND_COLOR_SHIFT))&PXP_PS_BACKGROUND_COLOR_MASK)
29818 #define PXP_PS_BACKGROUND_RSVD_MASK              0xFF000000u
29819 #define PXP_PS_BACKGROUND_RSVD_SHIFT             24
29820 #define PXP_PS_BACKGROUND_RSVD(x)                (((uint32_t)(((uint32_t)(x))<<PXP_PS_BACKGROUND_RSVD_SHIFT))&PXP_PS_BACKGROUND_RSVD_MASK)
29821 /* PS_SCALE Bit Fields */
29822 #define PXP_PS_SCALE_XSCALE_MASK                 0x7FFFu
29823 #define PXP_PS_SCALE_XSCALE_SHIFT                0
29824 #define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_XSCALE_SHIFT))&PXP_PS_SCALE_XSCALE_MASK)
29825 #define PXP_PS_SCALE_RSVD1_MASK                  0x8000u
29826 #define PXP_PS_SCALE_RSVD1_SHIFT                 15
29827 #define PXP_PS_SCALE_YSCALE_MASK                 0x7FFF0000u
29828 #define PXP_PS_SCALE_YSCALE_SHIFT                16
29829 #define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_YSCALE_SHIFT))&PXP_PS_SCALE_YSCALE_MASK)
29830 #define PXP_PS_SCALE_RSVD2_MASK                  0x80000000u
29831 #define PXP_PS_SCALE_RSVD2_SHIFT                 31
29832 /* PS_OFFSET Bit Fields */
29833 #define PXP_PS_OFFSET_XOFFSET_MASK               0xFFFu
29834 #define PXP_PS_OFFSET_XOFFSET_SHIFT              0
29835 #define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_PS_OFFSET_XOFFSET_MASK)
29836 #define PXP_PS_OFFSET_RSVD1_MASK                 0xF000u
29837 #define PXP_PS_OFFSET_RSVD1_SHIFT                12
29838 #define PXP_PS_OFFSET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_PS_OFFSET_RSVD1_MASK)
29839 #define PXP_PS_OFFSET_YOFFSET_MASK               0xFFF0000u
29840 #define PXP_PS_OFFSET_YOFFSET_SHIFT              16
29841 #define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_PS_OFFSET_YOFFSET_MASK)
29842 #define PXP_PS_OFFSET_RSVD2_MASK                 0xF0000000u
29843 #define PXP_PS_OFFSET_RSVD2_SHIFT                28
29844 #define PXP_PS_OFFSET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_PS_OFFSET_RSVD2_MASK)
29845 /* PS_CLRKEYLOW Bit Fields */
29846 #define PXP_PS_CLRKEYLOW_PIXEL_MASK              0xFFFFFFu
29847 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT             0
29848 #define PXP_PS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYLOW_PIXEL_SHIFT))&PXP_PS_CLRKEYLOW_PIXEL_MASK)
29849 #define PXP_PS_CLRKEYLOW_RSVD1_MASK              0xFF000000u
29850 #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT             24
29851 #define PXP_PS_CLRKEYLOW_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYLOW_RSVD1_SHIFT))&PXP_PS_CLRKEYLOW_RSVD1_MASK)
29852 /* PS_CLRKEYHIGH Bit Fields */
29853 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK             0xFFFFFFu
29854 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT            0
29855 #define PXP_PS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYHIGH_PIXEL_SHIFT))&PXP_PS_CLRKEYHIGH_PIXEL_MASK)
29856 #define PXP_PS_CLRKEYHIGH_RSVD1_MASK             0xFF000000u
29857 #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT            24
29858 #define PXP_PS_CLRKEYHIGH_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYHIGH_RSVD1_SHIFT))&PXP_PS_CLRKEYHIGH_RSVD1_MASK)
29859 /* AS_CTRL Bit Fields */
29860 #define PXP_AS_CTRL_RSVD0_MASK                   0x1u
29861 #define PXP_AS_CTRL_RSVD0_SHIFT                  0
29862 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              0x6u
29863 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             1
29864 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_AS_CTRL_ALPHA_CTRL_MASK)
29865 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         0x8u
29866 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        3
29867 #define PXP_AS_CTRL_FORMAT_MASK                  0xF0u
29868 #define PXP_AS_CTRL_FORMAT_SHIFT                 4
29869 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_FORMAT_SHIFT))&PXP_AS_CTRL_FORMAT_MASK)
29870 #define PXP_AS_CTRL_ALPHA_MASK                   0xFF00u
29871 #define PXP_AS_CTRL_ALPHA_SHIFT                  8
29872 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_SHIFT))&PXP_AS_CTRL_ALPHA_MASK)
29873 #define PXP_AS_CTRL_ROP_MASK                     0xF0000u
29874 #define PXP_AS_CTRL_ROP_SHIFT                    16
29875 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ROP_SHIFT))&PXP_AS_CTRL_ROP_MASK)
29876 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            0x100000u
29877 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           20
29878 #define PXP_AS_CTRL_RSVD1_MASK                   0xFFE00000u
29879 #define PXP_AS_CTRL_RSVD1_SHIFT                  21
29880 #define PXP_AS_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_RSVD1_SHIFT))&PXP_AS_CTRL_RSVD1_MASK)
29881 /* AS_BUF Bit Fields */
29882 #define PXP_AS_BUF_ADDR_MASK                     0xFFFFFFFFu
29883 #define PXP_AS_BUF_ADDR_SHIFT                    0
29884 #define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x))<<PXP_AS_BUF_ADDR_SHIFT))&PXP_AS_BUF_ADDR_MASK)
29885 /* AS_PITCH Bit Fields */
29886 #define PXP_AS_PITCH_PITCH_MASK                  0xFFFFu
29887 #define PXP_AS_PITCH_PITCH_SHIFT                 0
29888 #define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_PITCH_SHIFT))&PXP_AS_PITCH_PITCH_MASK)
29889 #define PXP_AS_PITCH_RSVD_MASK                   0xFFFF0000u
29890 #define PXP_AS_PITCH_RSVD_SHIFT                  16
29891 #define PXP_AS_PITCH_RSVD(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_RSVD_SHIFT))&PXP_AS_PITCH_RSVD_MASK)
29892 /* AS_CLRKEYLOW Bit Fields */
29893 #define PXP_AS_CLRKEYLOW_PIXEL_MASK              0xFFFFFFu
29894 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT             0
29895 #define PXP_AS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYLOW_PIXEL_SHIFT))&PXP_AS_CLRKEYLOW_PIXEL_MASK)
29896 #define PXP_AS_CLRKEYLOW_RSVD1_MASK              0xFF000000u
29897 #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT             24
29898 #define PXP_AS_CLRKEYLOW_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYLOW_RSVD1_SHIFT))&PXP_AS_CLRKEYLOW_RSVD1_MASK)
29899 /* AS_CLRKEYHIGH Bit Fields */
29900 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK             0xFFFFFFu
29901 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT            0
29902 #define PXP_AS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYHIGH_PIXEL_SHIFT))&PXP_AS_CLRKEYHIGH_PIXEL_MASK)
29903 #define PXP_AS_CLRKEYHIGH_RSVD1_MASK             0xFF000000u
29904 #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT            24
29905 #define PXP_AS_CLRKEYHIGH_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYHIGH_RSVD1_SHIFT))&PXP_AS_CLRKEYHIGH_RSVD1_MASK)
29906 /* CSC1_COEF0 Bit Fields */
29907 #define PXP_CSC1_COEF0_Y_OFFSET_MASK             0x1FFu
29908 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            0
29909 #define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_CSC1_COEF0_Y_OFFSET_MASK)
29910 #define PXP_CSC1_COEF0_UV_OFFSET_MASK            0x3FE00u
29911 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           9
29912 #define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_CSC1_COEF0_UV_OFFSET_MASK)
29913 #define PXP_CSC1_COEF0_C0_MASK                   0x1FFC0000u
29914 #define PXP_CSC1_COEF0_C0_SHIFT                  18
29915 #define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_C0_SHIFT))&PXP_CSC1_COEF0_C0_MASK)
29916 #define PXP_CSC1_COEF0_RSVD1_MASK                0x20000000u
29917 #define PXP_CSC1_COEF0_RSVD1_SHIFT               29
29918 #define PXP_CSC1_COEF0_BYPASS_MASK               0x40000000u
29919 #define PXP_CSC1_COEF0_BYPASS_SHIFT              30
29920 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK           0x80000000u
29921 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          31
29922 /* CSC1_COEF1 Bit Fields */
29923 #define PXP_CSC1_COEF1_C4_MASK                   0x7FFu
29924 #define PXP_CSC1_COEF1_C4_SHIFT                  0
29925 #define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C4_SHIFT))&PXP_CSC1_COEF1_C4_MASK)
29926 #define PXP_CSC1_COEF1_RSVD0_MASK                0xF800u
29927 #define PXP_CSC1_COEF1_RSVD0_SHIFT               11
29928 #define PXP_CSC1_COEF1_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_CSC1_COEF1_RSVD0_MASK)
29929 #define PXP_CSC1_COEF1_C1_MASK                   0x7FF0000u
29930 #define PXP_CSC1_COEF1_C1_SHIFT                  16
29931 #define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C1_SHIFT))&PXP_CSC1_COEF1_C1_MASK)
29932 #define PXP_CSC1_COEF1_RSVD1_MASK                0xF8000000u
29933 #define PXP_CSC1_COEF1_RSVD1_SHIFT               27
29934 #define PXP_CSC1_COEF1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_CSC1_COEF1_RSVD1_MASK)
29935 /* CSC1_COEF2 Bit Fields */
29936 #define PXP_CSC1_COEF2_C3_MASK                   0x7FFu
29937 #define PXP_CSC1_COEF2_C3_SHIFT                  0
29938 #define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C3_SHIFT))&PXP_CSC1_COEF2_C3_MASK)
29939 #define PXP_CSC1_COEF2_RSVD0_MASK                0xF800u
29940 #define PXP_CSC1_COEF2_RSVD0_SHIFT               11
29941 #define PXP_CSC1_COEF2_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_CSC1_COEF2_RSVD0_MASK)
29942 #define PXP_CSC1_COEF2_C2_MASK                   0x7FF0000u
29943 #define PXP_CSC1_COEF2_C2_SHIFT                  16
29944 #define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C2_SHIFT))&PXP_CSC1_COEF2_C2_MASK)
29945 #define PXP_CSC1_COEF2_RSVD1_MASK                0xF8000000u
29946 #define PXP_CSC1_COEF2_RSVD1_SHIFT               27
29947 #define PXP_CSC1_COEF2_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_CSC1_COEF2_RSVD1_MASK)
29948 /* CSC2_CTRL Bit Fields */
29949 #define PXP_CSC2_CTRL_BYPASS_MASK                0x1u
29950 #define PXP_CSC2_CTRL_BYPASS_SHIFT               0
29951 #define PXP_CSC2_CTRL_CSC_MODE_MASK              0x6u
29952 #define PXP_CSC2_CTRL_CSC_MODE_SHIFT             1
29953 #define PXP_CSC2_CTRL_CSC_MODE(x)                (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_CSC2_CTRL_CSC_MODE_MASK)
29954 #define PXP_CSC2_CTRL_RSVD_MASK                  0xFFFFFFF8u
29955 #define PXP_CSC2_CTRL_RSVD_SHIFT                 3
29956 #define PXP_CSC2_CTRL_RSVD(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_CSC2_CTRL_RSVD_MASK)
29957 /* CSC2_COEF0 Bit Fields */
29958 #define PXP_CSC2_COEF0_A1_MASK                   0x7FFu
29959 #define PXP_CSC2_COEF0_A1_SHIFT                  0
29960 #define PXP_CSC2_COEF0_A1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A1_SHIFT))&PXP_CSC2_COEF0_A1_MASK)
29961 #define PXP_CSC2_COEF0_RSVD0_MASK                0xF800u
29962 #define PXP_CSC2_COEF0_RSVD0_SHIFT               11
29963 #define PXP_CSC2_COEF0_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_CSC2_COEF0_RSVD0_MASK)
29964 #define PXP_CSC2_COEF0_A2_MASK                   0x7FF0000u
29965 #define PXP_CSC2_COEF0_A2_SHIFT                  16
29966 #define PXP_CSC2_COEF0_A2(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A2_SHIFT))&PXP_CSC2_COEF0_A2_MASK)
29967 #define PXP_CSC2_COEF0_RSVD1_MASK                0xF8000000u
29968 #define PXP_CSC2_COEF0_RSVD1_SHIFT               27
29969 #define PXP_CSC2_COEF0_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_CSC2_COEF0_RSVD1_MASK)
29970 /* CSC2_COEF1 Bit Fields */
29971 #define PXP_CSC2_COEF1_A3_MASK                   0x7FFu
29972 #define PXP_CSC2_COEF1_A3_SHIFT                  0
29973 #define PXP_CSC2_COEF1_A3(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_A3_SHIFT))&PXP_CSC2_COEF1_A3_MASK)
29974 #define PXP_CSC2_COEF1_RSVD0_MASK                0xF800u
29975 #define PXP_CSC2_COEF1_RSVD0_SHIFT               11
29976 #define PXP_CSC2_COEF1_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_CSC2_COEF1_RSVD0_MASK)
29977 #define PXP_CSC2_COEF1_B1_MASK                   0x7FF0000u
29978 #define PXP_CSC2_COEF1_B1_SHIFT                  16
29979 #define PXP_CSC2_COEF1_B1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_B1_SHIFT))&PXP_CSC2_COEF1_B1_MASK)
29980 #define PXP_CSC2_COEF1_RSVD1_MASK                0xF8000000u
29981 #define PXP_CSC2_COEF1_RSVD1_SHIFT               27
29982 #define PXP_CSC2_COEF1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_CSC2_COEF1_RSVD1_MASK)
29983 /* CSC2_COEF2 Bit Fields */
29984 #define PXP_CSC2_COEF2_B2_MASK                   0x7FFu
29985 #define PXP_CSC2_COEF2_B2_SHIFT                  0
29986 #define PXP_CSC2_COEF2_B2(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B2_SHIFT))&PXP_CSC2_COEF2_B2_MASK)
29987 #define PXP_CSC2_COEF2_RSVD0_MASK                0xF800u
29988 #define PXP_CSC2_COEF2_RSVD0_SHIFT               11
29989 #define PXP_CSC2_COEF2_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_CSC2_COEF2_RSVD0_MASK)
29990 #define PXP_CSC2_COEF2_B3_MASK                   0x7FF0000u
29991 #define PXP_CSC2_COEF2_B3_SHIFT                  16
29992 #define PXP_CSC2_COEF2_B3(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B3_SHIFT))&PXP_CSC2_COEF2_B3_MASK)
29993 #define PXP_CSC2_COEF2_RSVD1_MASK                0xF8000000u
29994 #define PXP_CSC2_COEF2_RSVD1_SHIFT               27
29995 #define PXP_CSC2_COEF2_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_CSC2_COEF2_RSVD1_MASK)
29996 /* CSC2_COEF3 Bit Fields */
29997 #define PXP_CSC2_COEF3_C1_MASK                   0x7FFu
29998 #define PXP_CSC2_COEF3_C1_SHIFT                  0
29999 #define PXP_CSC2_COEF3_C1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C1_SHIFT))&PXP_CSC2_COEF3_C1_MASK)
30000 #define PXP_CSC2_COEF3_RSVD0_MASK                0xF800u
30001 #define PXP_CSC2_COEF3_RSVD0_SHIFT               11
30002 #define PXP_CSC2_COEF3_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_CSC2_COEF3_RSVD0_MASK)
30003 #define PXP_CSC2_COEF3_C2_MASK                   0x7FF0000u
30004 #define PXP_CSC2_COEF3_C2_SHIFT                  16
30005 #define PXP_CSC2_COEF3_C2(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C2_SHIFT))&PXP_CSC2_COEF3_C2_MASK)
30006 #define PXP_CSC2_COEF3_RSVD1_MASK                0xF8000000u
30007 #define PXP_CSC2_COEF3_RSVD1_SHIFT               27
30008 #define PXP_CSC2_COEF3_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_CSC2_COEF3_RSVD1_MASK)
30009 /* CSC2_COEF4 Bit Fields */
30010 #define PXP_CSC2_COEF4_C3_MASK                   0x7FFu
30011 #define PXP_CSC2_COEF4_C3_SHIFT                  0
30012 #define PXP_CSC2_COEF4_C3(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_C3_SHIFT))&PXP_CSC2_COEF4_C3_MASK)
30013 #define PXP_CSC2_COEF4_RSVD0_MASK                0xF800u
30014 #define PXP_CSC2_COEF4_RSVD0_SHIFT               11
30015 #define PXP_CSC2_COEF4_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_CSC2_COEF4_RSVD0_MASK)
30016 #define PXP_CSC2_COEF4_D1_MASK                   0x1FF0000u
30017 #define PXP_CSC2_COEF4_D1_SHIFT                  16
30018 #define PXP_CSC2_COEF4_D1(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_D1_SHIFT))&PXP_CSC2_COEF4_D1_MASK)
30019 #define PXP_CSC2_COEF4_RSVD1_MASK                0xFE000000u
30020 #define PXP_CSC2_COEF4_RSVD1_SHIFT               25
30021 #define PXP_CSC2_COEF4_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_CSC2_COEF4_RSVD1_MASK)
30022 /* CSC2_COEF5 Bit Fields */
30023 #define PXP_CSC2_COEF5_D2_MASK                   0x1FFu
30024 #define PXP_CSC2_COEF5_D2_SHIFT                  0
30025 #define PXP_CSC2_COEF5_D2(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D2_SHIFT))&PXP_CSC2_COEF5_D2_MASK)
30026 #define PXP_CSC2_COEF5_RSVD0_MASK                0xFE00u
30027 #define PXP_CSC2_COEF5_RSVD0_SHIFT               9
30028 #define PXP_CSC2_COEF5_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_CSC2_COEF5_RSVD0_MASK)
30029 #define PXP_CSC2_COEF5_D3_MASK                   0x1FF0000u
30030 #define PXP_CSC2_COEF5_D3_SHIFT                  16
30031 #define PXP_CSC2_COEF5_D3(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D3_SHIFT))&PXP_CSC2_COEF5_D3_MASK)
30032 #define PXP_CSC2_COEF5_RSVD1_MASK                0xFE000000u
30033 #define PXP_CSC2_COEF5_RSVD1_SHIFT               25
30034 #define PXP_CSC2_COEF5_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_CSC2_COEF5_RSVD1_MASK)
30035 /* LUT_CTRL Bit Fields */
30036 #define PXP_LUT_CTRL_DMA_START_MASK              0x1u
30037 #define PXP_LUT_CTRL_DMA_START_SHIFT             0
30038 #define PXP_LUT_CTRL_RSVD0_MASK                  0xFEu
30039 #define PXP_LUT_CTRL_RSVD0_SHIFT                 1
30040 #define PXP_LUT_CTRL_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_LUT_CTRL_RSVD0_MASK)
30041 #define PXP_LUT_CTRL_INVALID_MASK                0x100u
30042 #define PXP_LUT_CTRL_INVALID_SHIFT               8
30043 #define PXP_LUT_CTRL_LRU_UPD_MASK                0x200u
30044 #define PXP_LUT_CTRL_LRU_UPD_SHIFT               9
30045 #define PXP_LUT_CTRL_SEL_8KB_MASK                0x400u
30046 #define PXP_LUT_CTRL_SEL_8KB_SHIFT               10
30047 #define PXP_LUT_CTRL_RSVD1_MASK                  0xF800u
30048 #define PXP_LUT_CTRL_RSVD1_SHIFT                 11
30049 #define PXP_LUT_CTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_LUT_CTRL_RSVD1_MASK)
30050 #define PXP_LUT_CTRL_OUT_MODE_MASK               0x30000u
30051 #define PXP_LUT_CTRL_OUT_MODE_SHIFT              16
30052 #define PXP_LUT_CTRL_OUT_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_LUT_CTRL_OUT_MODE_MASK)
30053 #define PXP_LUT_CTRL_RSVD2_MASK                  0xFC0000u
30054 #define PXP_LUT_CTRL_RSVD2_SHIFT                 18
30055 #define PXP_LUT_CTRL_RSVD2(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_LUT_CTRL_RSVD2_MASK)
30056 #define PXP_LUT_CTRL_LOOKUP_MODE_MASK            0x3000000u
30057 #define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT           24
30058 #define PXP_LUT_CTRL_LOOKUP_MODE(x)              (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_LUT_CTRL_LOOKUP_MODE_MASK)
30059 #define PXP_LUT_CTRL_RSVD3_MASK                  0x7C000000u
30060 #define PXP_LUT_CTRL_RSVD3_SHIFT                 26
30061 #define PXP_LUT_CTRL_RSVD3(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_LUT_CTRL_RSVD3_MASK)
30062 #define PXP_LUT_CTRL_BYPASS_MASK                 0x80000000u
30063 #define PXP_LUT_CTRL_BYPASS_SHIFT                31
30064 /* LUT_ADDR Bit Fields */
30065 #define PXP_LUT_ADDR_ADDR_MASK                   0x3FFFu
30066 #define PXP_LUT_ADDR_ADDR_SHIFT                  0
30067 #define PXP_LUT_ADDR_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_ADDR_SHIFT))&PXP_LUT_ADDR_ADDR_MASK)
30068 #define PXP_LUT_ADDR_RSVD1_MASK                  0xC000u
30069 #define PXP_LUT_ADDR_RSVD1_SHIFT                 14
30070 #define PXP_LUT_ADDR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_LUT_ADDR_RSVD1_MASK)
30071 #define PXP_LUT_ADDR_NUM_BYTES_MASK              0x7FFF0000u
30072 #define PXP_LUT_ADDR_NUM_BYTES_SHIFT             16
30073 #define PXP_LUT_ADDR_NUM_BYTES(x)                (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_LUT_ADDR_NUM_BYTES_MASK)
30074 #define PXP_LUT_ADDR_RSVD2_MASK                  0x80000000u
30075 #define PXP_LUT_ADDR_RSVD2_SHIFT                 31
30076 /* LUT_DATA Bit Fields */
30077 #define PXP_LUT_DATA_DATA_MASK                   0xFFFFFFFFu
30078 #define PXP_LUT_DATA_DATA_SHIFT                  0
30079 #define PXP_LUT_DATA_DATA(x)                     (((uint32_t)(((uint32_t)(x))<<PXP_LUT_DATA_DATA_SHIFT))&PXP_LUT_DATA_DATA_MASK)
30080 /* LUT_EXTMEM Bit Fields */
30081 #define PXP_LUT_EXTMEM_ADDR_MASK                 0xFFFFFFFFu
30082 #define PXP_LUT_EXTMEM_ADDR_SHIFT                0
30083 #define PXP_LUT_EXTMEM_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_LUT_EXTMEM_ADDR_MASK)
30084 /* CFA Bit Fields */
30085 #define PXP_CFA_DATA_MASK                        0xFFFFFFFFu
30086 #define PXP_CFA_DATA_SHIFT                       0
30087 #define PXP_CFA_DATA(x)                          (((uint32_t)(((uint32_t)(x))<<PXP_CFA_DATA_SHIFT))&PXP_CFA_DATA_MASK)
30088 /* HIST_CTRL Bit Fields */
30089 #define PXP_HIST_CTRL_STATUS_MASK                0xFu
30090 #define PXP_HIST_CTRL_STATUS_SHIFT               0
30091 #define PXP_HIST_CTRL_STATUS(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_STATUS_SHIFT))&PXP_HIST_CTRL_STATUS_MASK)
30092 #define PXP_HIST_CTRL_PANEL_MODE_MASK            0x30u
30093 #define PXP_HIST_CTRL_PANEL_MODE_SHIFT           4
30094 #define PXP_HIST_CTRL_PANEL_MODE(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_PANEL_MODE_SHIFT))&PXP_HIST_CTRL_PANEL_MODE_MASK)
30095 #define PXP_HIST_CTRL_RSVD_MASK                  0xFFFFFFC0u
30096 #define PXP_HIST_CTRL_RSVD_SHIFT                 6
30097 #define PXP_HIST_CTRL_RSVD(x)                    (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_RSVD_SHIFT))&PXP_HIST_CTRL_RSVD_MASK)
30098 /* HIST2_PARAM Bit Fields */
30099 #define PXP_HIST2_PARAM_VALUE0_MASK              0x1Fu
30100 #define PXP_HIST2_PARAM_VALUE0_SHIFT             0
30101 #define PXP_HIST2_PARAM_VALUE0(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HIST2_PARAM_VALUE0_MASK)
30102 #define PXP_HIST2_PARAM_RSVD0_MASK               0xE0u
30103 #define PXP_HIST2_PARAM_RSVD0_SHIFT              5
30104 #define PXP_HIST2_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HIST2_PARAM_RSVD0_MASK)
30105 #define PXP_HIST2_PARAM_VALUE1_MASK              0x1F00u
30106 #define PXP_HIST2_PARAM_VALUE1_SHIFT             8
30107 #define PXP_HIST2_PARAM_VALUE1(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HIST2_PARAM_VALUE1_MASK)
30108 #define PXP_HIST2_PARAM_RSVD1_MASK               0xE000u
30109 #define PXP_HIST2_PARAM_RSVD1_SHIFT              13
30110 #define PXP_HIST2_PARAM_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HIST2_PARAM_RSVD1_MASK)
30111 #define PXP_HIST2_PARAM_RSVD_MASK                0xFFFF0000u
30112 #define PXP_HIST2_PARAM_RSVD_SHIFT               16
30113 #define PXP_HIST2_PARAM_RSVD(x)                  (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HIST2_PARAM_RSVD_MASK)
30114 /* HIST4_PARAM Bit Fields */
30115 #define PXP_HIST4_PARAM_VALUE0_MASK              0x1Fu
30116 #define PXP_HIST4_PARAM_VALUE0_SHIFT             0
30117 #define PXP_HIST4_PARAM_VALUE0(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HIST4_PARAM_VALUE0_MASK)
30118 #define PXP_HIST4_PARAM_RSVD0_MASK               0xE0u
30119 #define PXP_HIST4_PARAM_RSVD0_SHIFT              5
30120 #define PXP_HIST4_PARAM_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HIST4_PARAM_RSVD0_MASK)
30121 #define PXP_HIST4_PARAM_VALUE1_MASK              0x1F00u
30122 #define PXP_HIST4_PARAM_VALUE1_SHIFT             8
30123 #define PXP_HIST4_PARAM_VALUE1(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HIST4_PARAM_VALUE1_MASK)
30124 #define PXP_HIST4_PARAM_RSVD1_MASK               0xE000u
30125 #define PXP_HIST4_PARAM_RSVD1_SHIFT              13
30126 #define PXP_HIST4_PARAM_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HIST4_PARAM_RSVD1_MASK)
30127 #define PXP_HIST4_PARAM_VALUE2_MASK              0x1F0000u
30128 #define PXP_HIST4_PARAM_VALUE2_SHIFT             16
30129 #define PXP_HIST4_PARAM_VALUE2(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HIST4_PARAM_VALUE2_MASK)
30130 #define PXP_HIST4_PARAM_RSVD2_MASK               0xE00000u
30131 #define PXP_HIST4_PARAM_RSVD2_SHIFT              21
30132 #define PXP_HIST4_PARAM_RSVD2(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HIST4_PARAM_RSVD2_MASK)
30133 #define PXP_HIST4_PARAM_VALUE3_MASK              0x1F000000u
30134 #define PXP_HIST4_PARAM_VALUE3_SHIFT             24
30135 #define PXP_HIST4_PARAM_VALUE3(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HIST4_PARAM_VALUE3_MASK)
30136 #define PXP_HIST4_PARAM_RSVD3_MASK               0xE0000000u
30137 #define PXP_HIST4_PARAM_RSVD3_SHIFT              29
30138 #define PXP_HIST4_PARAM_RSVD3(x)                 (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HIST4_PARAM_RSVD3_MASK)
30139 /* HIST8_PARAM0 Bit Fields */
30140 #define PXP_HIST8_PARAM0_VALUE0_MASK             0x1Fu
30141 #define PXP_HIST8_PARAM0_VALUE0_SHIFT            0
30142 #define PXP_HIST8_PARAM0_VALUE0(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HIST8_PARAM0_VALUE0_MASK)
30143 #define PXP_HIST8_PARAM0_RSVD0_MASK              0xE0u
30144 #define PXP_HIST8_PARAM0_RSVD0_SHIFT             5
30145 #define PXP_HIST8_PARAM0_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HIST8_PARAM0_RSVD0_MASK)
30146 #define PXP_HIST8_PARAM0_VALUE1_MASK             0x1F00u
30147 #define PXP_HIST8_PARAM0_VALUE1_SHIFT            8
30148 #define PXP_HIST8_PARAM0_VALUE1(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HIST8_PARAM0_VALUE1_MASK)
30149 #define PXP_HIST8_PARAM0_RSVD1_MASK              0xE000u
30150 #define PXP_HIST8_PARAM0_RSVD1_SHIFT             13
30151 #define PXP_HIST8_PARAM0_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HIST8_PARAM0_RSVD1_MASK)
30152 #define PXP_HIST8_PARAM0_VALUE2_MASK             0x1F0000u
30153 #define PXP_HIST8_PARAM0_VALUE2_SHIFT            16
30154 #define PXP_HIST8_PARAM0_VALUE2(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HIST8_PARAM0_VALUE2_MASK)
30155 #define PXP_HIST8_PARAM0_RSVD2_MASK              0xE00000u
30156 #define PXP_HIST8_PARAM0_RSVD2_SHIFT             21
30157 #define PXP_HIST8_PARAM0_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HIST8_PARAM0_RSVD2_MASK)
30158 #define PXP_HIST8_PARAM0_VALUE3_MASK             0x1F000000u
30159 #define PXP_HIST8_PARAM0_VALUE3_SHIFT            24
30160 #define PXP_HIST8_PARAM0_VALUE3(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HIST8_PARAM0_VALUE3_MASK)
30161 #define PXP_HIST8_PARAM0_RSVD3_MASK              0xE0000000u
30162 #define PXP_HIST8_PARAM0_RSVD3_SHIFT             29
30163 #define PXP_HIST8_PARAM0_RSVD3(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HIST8_PARAM0_RSVD3_MASK)
30164 /* HIST8_PARAM1 Bit Fields */
30165 #define PXP_HIST8_PARAM1_VALUE4_MASK             0x1Fu
30166 #define PXP_HIST8_PARAM1_VALUE4_SHIFT            0
30167 #define PXP_HIST8_PARAM1_VALUE4(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HIST8_PARAM1_VALUE4_MASK)
30168 #define PXP_HIST8_PARAM1_RSVD4_MASK              0xE0u
30169 #define PXP_HIST8_PARAM1_RSVD4_SHIFT             5
30170 #define PXP_HIST8_PARAM1_RSVD4(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HIST8_PARAM1_RSVD4_MASK)
30171 #define PXP_HIST8_PARAM1_VALUE5_MASK             0x1F00u
30172 #define PXP_HIST8_PARAM1_VALUE5_SHIFT            8
30173 #define PXP_HIST8_PARAM1_VALUE5(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HIST8_PARAM1_VALUE5_MASK)
30174 #define PXP_HIST8_PARAM1_RSVD5_MASK              0xE000u
30175 #define PXP_HIST8_PARAM1_RSVD5_SHIFT             13
30176 #define PXP_HIST8_PARAM1_RSVD5(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HIST8_PARAM1_RSVD5_MASK)
30177 #define PXP_HIST8_PARAM1_VALUE6_MASK             0x1F0000u
30178 #define PXP_HIST8_PARAM1_VALUE6_SHIFT            16
30179 #define PXP_HIST8_PARAM1_VALUE6(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HIST8_PARAM1_VALUE6_MASK)
30180 #define PXP_HIST8_PARAM1_RSVD6_MASK              0xE00000u
30181 #define PXP_HIST8_PARAM1_RSVD6_SHIFT             21
30182 #define PXP_HIST8_PARAM1_RSVD6(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HIST8_PARAM1_RSVD6_MASK)
30183 #define PXP_HIST8_PARAM1_VALUE7_MASK             0x1F000000u
30184 #define PXP_HIST8_PARAM1_VALUE7_SHIFT            24
30185 #define PXP_HIST8_PARAM1_VALUE7(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HIST8_PARAM1_VALUE7_MASK)
30186 #define PXP_HIST8_PARAM1_RSVD7_MASK              0xE0000000u
30187 #define PXP_HIST8_PARAM1_RSVD7_SHIFT             29
30188 #define PXP_HIST8_PARAM1_RSVD7(x)                (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HIST8_PARAM1_RSVD7_MASK)
30189 /* HIST16_PARAM0 Bit Fields */
30190 #define PXP_HIST16_PARAM0_VALUE0_MASK            0x1Fu
30191 #define PXP_HIST16_PARAM0_VALUE0_SHIFT           0
30192 #define PXP_HIST16_PARAM0_VALUE0(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HIST16_PARAM0_VALUE0_MASK)
30193 #define PXP_HIST16_PARAM0_RSVD0_MASK             0xE0u
30194 #define PXP_HIST16_PARAM0_RSVD0_SHIFT            5
30195 #define PXP_HIST16_PARAM0_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HIST16_PARAM0_RSVD0_MASK)
30196 #define PXP_HIST16_PARAM0_VALUE1_MASK            0x1F00u
30197 #define PXP_HIST16_PARAM0_VALUE1_SHIFT           8
30198 #define PXP_HIST16_PARAM0_VALUE1(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HIST16_PARAM0_VALUE1_MASK)
30199 #define PXP_HIST16_PARAM0_RSVD1_MASK             0xE000u
30200 #define PXP_HIST16_PARAM0_RSVD1_SHIFT            13
30201 #define PXP_HIST16_PARAM0_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HIST16_PARAM0_RSVD1_MASK)
30202 #define PXP_HIST16_PARAM0_VALUE2_MASK            0x1F0000u
30203 #define PXP_HIST16_PARAM0_VALUE2_SHIFT           16
30204 #define PXP_HIST16_PARAM0_VALUE2(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HIST16_PARAM0_VALUE2_MASK)
30205 #define PXP_HIST16_PARAM0_RSVD2_MASK             0xE00000u
30206 #define PXP_HIST16_PARAM0_RSVD2_SHIFT            21
30207 #define PXP_HIST16_PARAM0_RSVD2(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HIST16_PARAM0_RSVD2_MASK)
30208 #define PXP_HIST16_PARAM0_VALUE3_MASK            0x1F000000u
30209 #define PXP_HIST16_PARAM0_VALUE3_SHIFT           24
30210 #define PXP_HIST16_PARAM0_VALUE3(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HIST16_PARAM0_VALUE3_MASK)
30211 #define PXP_HIST16_PARAM0_RSVD3_MASK             0xE0000000u
30212 #define PXP_HIST16_PARAM0_RSVD3_SHIFT            29
30213 #define PXP_HIST16_PARAM0_RSVD3(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HIST16_PARAM0_RSVD3_MASK)
30214 /* HIST16_PARAM1 Bit Fields */
30215 #define PXP_HIST16_PARAM1_VALUE4_MASK            0x1Fu
30216 #define PXP_HIST16_PARAM1_VALUE4_SHIFT           0
30217 #define PXP_HIST16_PARAM1_VALUE4(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HIST16_PARAM1_VALUE4_MASK)
30218 #define PXP_HIST16_PARAM1_RSVD4_MASK             0xE0u
30219 #define PXP_HIST16_PARAM1_RSVD4_SHIFT            5
30220 #define PXP_HIST16_PARAM1_RSVD4(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HIST16_PARAM1_RSVD4_MASK)
30221 #define PXP_HIST16_PARAM1_VALUE5_MASK            0x1F00u
30222 #define PXP_HIST16_PARAM1_VALUE5_SHIFT           8
30223 #define PXP_HIST16_PARAM1_VALUE5(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HIST16_PARAM1_VALUE5_MASK)
30224 #define PXP_HIST16_PARAM1_RSVD5_MASK             0xE000u
30225 #define PXP_HIST16_PARAM1_RSVD5_SHIFT            13
30226 #define PXP_HIST16_PARAM1_RSVD5(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HIST16_PARAM1_RSVD5_MASK)
30227 #define PXP_HIST16_PARAM1_VALUE6_MASK            0x1F0000u
30228 #define PXP_HIST16_PARAM1_VALUE6_SHIFT           16
30229 #define PXP_HIST16_PARAM1_VALUE6(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HIST16_PARAM1_VALUE6_MASK)
30230 #define PXP_HIST16_PARAM1_RSVD6_MASK             0xE00000u
30231 #define PXP_HIST16_PARAM1_RSVD6_SHIFT            21
30232 #define PXP_HIST16_PARAM1_RSVD6(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HIST16_PARAM1_RSVD6_MASK)
30233 #define PXP_HIST16_PARAM1_VALUE7_MASK            0x1F000000u
30234 #define PXP_HIST16_PARAM1_VALUE7_SHIFT           24
30235 #define PXP_HIST16_PARAM1_VALUE7(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HIST16_PARAM1_VALUE7_MASK)
30236 #define PXP_HIST16_PARAM1_RSVD7_MASK             0xE0000000u
30237 #define PXP_HIST16_PARAM1_RSVD7_SHIFT            29
30238 #define PXP_HIST16_PARAM1_RSVD7(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HIST16_PARAM1_RSVD7_MASK)
30239 /* HIST16_PARAM2 Bit Fields */
30240 #define PXP_HIST16_PARAM2_VALUE8_MASK            0x1Fu
30241 #define PXP_HIST16_PARAM2_VALUE8_SHIFT           0
30242 #define PXP_HIST16_PARAM2_VALUE8(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HIST16_PARAM2_VALUE8_MASK)
30243 #define PXP_HIST16_PARAM2_RSVD8_MASK             0xE0u
30244 #define PXP_HIST16_PARAM2_RSVD8_SHIFT            5
30245 #define PXP_HIST16_PARAM2_RSVD8(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HIST16_PARAM2_RSVD8_MASK)
30246 #define PXP_HIST16_PARAM2_VALUE9_MASK            0x1F00u
30247 #define PXP_HIST16_PARAM2_VALUE9_SHIFT           8
30248 #define PXP_HIST16_PARAM2_VALUE9(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HIST16_PARAM2_VALUE9_MASK)
30249 #define PXP_HIST16_PARAM2_RSVD9_MASK             0xE000u
30250 #define PXP_HIST16_PARAM2_RSVD9_SHIFT            13
30251 #define PXP_HIST16_PARAM2_RSVD9(x)               (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HIST16_PARAM2_RSVD9_MASK)
30252 #define PXP_HIST16_PARAM2_VALUE10_MASK           0x1F0000u
30253 #define PXP_HIST16_PARAM2_VALUE10_SHIFT          16
30254 #define PXP_HIST16_PARAM2_VALUE10(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HIST16_PARAM2_VALUE10_MASK)
30255 #define PXP_HIST16_PARAM2_RSVD10_MASK            0xE00000u
30256 #define PXP_HIST16_PARAM2_RSVD10_SHIFT           21
30257 #define PXP_HIST16_PARAM2_RSVD10(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HIST16_PARAM2_RSVD10_MASK)
30258 #define PXP_HIST16_PARAM2_VALUE11_MASK           0x1F000000u
30259 #define PXP_HIST16_PARAM2_VALUE11_SHIFT          24
30260 #define PXP_HIST16_PARAM2_VALUE11(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HIST16_PARAM2_VALUE11_MASK)
30261 #define PXP_HIST16_PARAM2_RSVD11_MASK            0xE0000000u
30262 #define PXP_HIST16_PARAM2_RSVD11_SHIFT           29
30263 #define PXP_HIST16_PARAM2_RSVD11(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HIST16_PARAM2_RSVD11_MASK)
30264 /* HIST16_PARAM3 Bit Fields */
30265 #define PXP_HIST16_PARAM3_VALUE12_MASK           0x1Fu
30266 #define PXP_HIST16_PARAM3_VALUE12_SHIFT          0
30267 #define PXP_HIST16_PARAM3_VALUE12(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HIST16_PARAM3_VALUE12_MASK)
30268 #define PXP_HIST16_PARAM3_RSVD12_MASK            0xE0u
30269 #define PXP_HIST16_PARAM3_RSVD12_SHIFT           5
30270 #define PXP_HIST16_PARAM3_RSVD12(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HIST16_PARAM3_RSVD12_MASK)
30271 #define PXP_HIST16_PARAM3_VALUE13_MASK           0x1F00u
30272 #define PXP_HIST16_PARAM3_VALUE13_SHIFT          8
30273 #define PXP_HIST16_PARAM3_VALUE13(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HIST16_PARAM3_VALUE13_MASK)
30274 #define PXP_HIST16_PARAM3_RSVD13_MASK            0xE000u
30275 #define PXP_HIST16_PARAM3_RSVD13_SHIFT           13
30276 #define PXP_HIST16_PARAM3_RSVD13(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HIST16_PARAM3_RSVD13_MASK)
30277 #define PXP_HIST16_PARAM3_VALUE14_MASK           0x1F0000u
30278 #define PXP_HIST16_PARAM3_VALUE14_SHIFT          16
30279 #define PXP_HIST16_PARAM3_VALUE14(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HIST16_PARAM3_VALUE14_MASK)
30280 #define PXP_HIST16_PARAM3_RSVD14_MASK            0xE00000u
30281 #define PXP_HIST16_PARAM3_RSVD14_SHIFT           21
30282 #define PXP_HIST16_PARAM3_RSVD14(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HIST16_PARAM3_RSVD14_MASK)
30283 #define PXP_HIST16_PARAM3_VALUE15_MASK           0x1F000000u
30284 #define PXP_HIST16_PARAM3_VALUE15_SHIFT          24
30285 #define PXP_HIST16_PARAM3_VALUE15(x)             (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HIST16_PARAM3_VALUE15_MASK)
30286 #define PXP_HIST16_PARAM3_RSVD15_MASK            0xE0000000u
30287 #define PXP_HIST16_PARAM3_RSVD15_SHIFT           29
30288 #define PXP_HIST16_PARAM3_RSVD15(x)              (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HIST16_PARAM3_RSVD15_MASK)
30289 /* POWER Bit Fields */
30290 #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0_MASK   0x7u
30291 #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0_SHIFT  0
30292 #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0(x)     (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY0_BANK0_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY0_BANK0_MASK)
30293 #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN_MASK   0x38u
30294 #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN_SHIFT  3
30295 #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN(x)     (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY0_BANKN_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY0_BANKN_MASK)
30296 #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN_MASK   0x1C0u
30297 #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN_SHIFT  6
30298 #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN(x)     (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY1_BANKN_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY1_BANKN_MASK)
30299 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          0xE00u
30300 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         9
30301 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x))<<PXP_POWER_ROT_MEM_LP_STATE_SHIFT))&PXP_POWER_ROT_MEM_LP_STATE_MASK)
30302 #define PXP_POWER_CTRL_MASK                      0xFFFFF000u
30303 #define PXP_POWER_CTRL_SHIFT                     12
30304 #define PXP_POWER_CTRL(x)                        (((uint32_t)(((uint32_t)(x))<<PXP_POWER_CTRL_SHIFT))&PXP_POWER_CTRL_MASK)
30305 /* NEXT Bit Fields */
30306 #define PXP_NEXT_ENABLED_MASK                    0x1u
30307 #define PXP_NEXT_ENABLED_SHIFT                   0
30308 #define PXP_NEXT_RSVD_MASK                       0x2u
30309 #define PXP_NEXT_RSVD_SHIFT                      1
30310 #define PXP_NEXT_POINTER_MASK                    0xFFFFFFFCu
30311 #define PXP_NEXT_POINTER_SHIFT                   2
30312 #define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x))<<PXP_NEXT_POINTER_SHIFT))&PXP_NEXT_POINTER_MASK)
30313 
30314 /*!
30315  * @}
30316  */ /* end of group PXP_Register_Masks */
30317 
30318 /* PXP - Peripheral instance base addresses */
30319 /** Peripheral PXP base address */
30320 #define PXP_BASE                                 (0x42218000u)
30321 /** Peripheral PXP base pointer */
30322 #define PXP                                      ((PXP_Type *)PXP_BASE)
30323 #define PXP_BASE_PTR                             (PXP)
30324 /** Array initializer of PXP peripheral base addresses */
30325 #define PXP_BASE_ADDRS                           { PXP_BASE }
30326 /** Array initializer of PXP peripheral base pointers */
30327 #define PXP_BASE_PTRS                            { PXP }
30328 /** Interrupt vectors for the PXP peripheral type */
30329 #define PXP_IRQS                                 { PXP_IRQn }
30330 
30331 /* ----------------------------------------------------------------------------
30332    -- PXP - Register accessor macros
30333    ---------------------------------------------------------------------------- */
30334 
30335 /*!
30336  * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros
30337  * @{
30338  */
30339 
30340 /* PXP - Register instance definitions */
30341 /* PXP */
30342 #define PXP_CTRL                                 PXP_CTRL_REG(PXP_BASE_PTR)
30343 #define PXP_STAT                                 PXP_STAT_REG(PXP_BASE_PTR)
30344 #define PXP_OUT_CTRL                             PXP_OUT_CTRL_REG(PXP_BASE_PTR)
30345 #define PXP_OUT_BUF                              PXP_OUT_BUF_REG(PXP_BASE_PTR)
30346 #define PXP_OUT_BUF2                             PXP_OUT_BUF2_REG(PXP_BASE_PTR)
30347 #define PXP_OUT_PITCH                            PXP_OUT_PITCH_REG(PXP_BASE_PTR)
30348 #define PXP_OUT_LRC                              PXP_OUT_LRC_REG(PXP_BASE_PTR)
30349 #define PXP_OUT_PS_ULC                           PXP_OUT_PS_ULC_REG(PXP_BASE_PTR)
30350 #define PXP_OUT_PS_LRC                           PXP_OUT_PS_LRC_REG(PXP_BASE_PTR)
30351 #define PXP_OUT_AS_ULC                           PXP_OUT_AS_ULC_REG(PXP_BASE_PTR)
30352 #define PXP_OUT_AS_LRC                           PXP_OUT_AS_LRC_REG(PXP_BASE_PTR)
30353 #define PXP_PS_CTRL                              PXP_PS_CTRL_REG(PXP_BASE_PTR)
30354 #define PXP_PS_BUF                               PXP_PS_BUF_REG(PXP_BASE_PTR)
30355 #define PXP_PS_UBUF                              PXP_PS_UBUF_REG(PXP_BASE_PTR)
30356 #define PXP_PS_VBUF                              PXP_PS_VBUF_REG(PXP_BASE_PTR)
30357 #define PXP_PS_PITCH                             PXP_PS_PITCH_REG(PXP_BASE_PTR)
30358 #define PXP_PS_BACKGROUND                        PXP_PS_BACKGROUND_REG(PXP_BASE_PTR)
30359 #define PXP_PS_SCALE                             PXP_PS_SCALE_REG(PXP_BASE_PTR)
30360 #define PXP_PS_OFFSET                            PXP_PS_OFFSET_REG(PXP_BASE_PTR)
30361 #define PXP_PS_CLRKEYLOW                         PXP_PS_CLRKEYLOW_REG(PXP_BASE_PTR)
30362 #define PXP_PS_CLRKEYHIGH                        PXP_PS_CLRKEYHIGH_REG(PXP_BASE_PTR)
30363 #define PXP_AS_CTRL                              PXP_AS_CTRL_REG(PXP_BASE_PTR)
30364 #define PXP_AS_BUF                               PXP_AS_BUF_REG(PXP_BASE_PTR)
30365 #define PXP_AS_PITCH                             PXP_AS_PITCH_REG(PXP_BASE_PTR)
30366 #define PXP_AS_CLRKEYLOW                         PXP_AS_CLRKEYLOW_REG(PXP_BASE_PTR)
30367 #define PXP_AS_CLRKEYHIGH                        PXP_AS_CLRKEYHIGH_REG(PXP_BASE_PTR)
30368 #define PXP_CSC1_COEF0                           PXP_CSC1_COEF0_REG(PXP_BASE_PTR)
30369 #define PXP_CSC1_COEF1                           PXP_CSC1_COEF1_REG(PXP_BASE_PTR)
30370 #define PXP_CSC1_COEF2                           PXP_CSC1_COEF2_REG(PXP_BASE_PTR)
30371 #define PXP_CSC2_CTRL                            PXP_CSC2_CTRL_REG(PXP_BASE_PTR)
30372 #define PXP_CSC2_COEF0                           PXP_CSC2_COEF0_REG(PXP_BASE_PTR)
30373 #define PXP_CSC2_COEF1                           PXP_CSC2_COEF1_REG(PXP_BASE_PTR)
30374 #define PXP_CSC2_COEF2                           PXP_CSC2_COEF2_REG(PXP_BASE_PTR)
30375 #define PXP_CSC2_COEF3                           PXP_CSC2_COEF3_REG(PXP_BASE_PTR)
30376 #define PXP_CSC2_COEF4                           PXP_CSC2_COEF4_REG(PXP_BASE_PTR)
30377 #define PXP_CSC2_COEF5                           PXP_CSC2_COEF5_REG(PXP_BASE_PTR)
30378 #define PXP_LUT_CTRL                             PXP_LUT_CTRL_REG(PXP_BASE_PTR)
30379 #define PXP_LUT_ADDR                             PXP_LUT_ADDR_REG(PXP_BASE_PTR)
30380 #define PXP_LUT_DATA                             PXP_LUT_DATA_REG(PXP_BASE_PTR)
30381 #define PXP_LUT_EXTMEM                           PXP_LUT_EXTMEM_REG(PXP_BASE_PTR)
30382 #define PXP_CFA                                  PXP_CFA_REG(PXP_BASE_PTR)
30383 #define PXP_HIST_CTRL                            PXP_HIST_CTRL_REG(PXP_BASE_PTR)
30384 #define PXP_HIST2_PARAM                          PXP_HIST2_PARAM_REG(PXP_BASE_PTR)
30385 #define PXP_HIST4_PARAM                          PXP_HIST4_PARAM_REG(PXP_BASE_PTR)
30386 #define PXP_HIST8_PARAM0                         PXP_HIST8_PARAM0_REG(PXP_BASE_PTR)
30387 #define PXP_HIST8_PARAM1                         PXP_HIST8_PARAM1_REG(PXP_BASE_PTR)
30388 #define PXP_HIST16_PARAM0                        PXP_HIST16_PARAM0_REG(PXP_BASE_PTR)
30389 #define PXP_HIST16_PARAM1                        PXP_HIST16_PARAM1_REG(PXP_BASE_PTR)
30390 #define PXP_HIST16_PARAM2                        PXP_HIST16_PARAM2_REG(PXP_BASE_PTR)
30391 #define PXP_HIST16_PARAM3                        PXP_HIST16_PARAM3_REG(PXP_BASE_PTR)
30392 #define PXP_POWER                                PXP_POWER_REG(PXP_BASE_PTR)
30393 #define PXP_NEXT                                 PXP_NEXT_REG(PXP_BASE_PTR)
30394 
30395 /*!
30396  * @}
30397  */ /* end of group PXP_Register_Accessor_Macros */
30398 
30399 /*!
30400  * @}
30401  */ /* end of group PXP_Peripheral */
30402 
30403 /* ----------------------------------------------------------------------------
30404    -- QuadSPI Peripheral Access Layer
30405    ---------------------------------------------------------------------------- */
30406 
30407 /*!
30408  * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
30409  * @{
30410  */
30411 
30412 /** QuadSPI - Register Layout Typedef */
30413 typedef struct {
30414   __IO  uint32_t MCR;                                    /**< Module Configuration Register, offset: 0x0 */
30415   uint8_t RESERVED_0[4];
30416   __IO  uint32_t IPCR;                                   /**< IP Configuration Register, offset: 0x8 */
30417   __IO  uint32_t FLSHCR;                                 /**< Flash Configuration Register, offset: 0xC */
30418   __IO  uint32_t BUF0CR;                                 /**< Buffer0 Configuration Register, offset: 0x10 */
30419   __IO  uint32_t BUF1CR;                                 /**< Buffer1 Configuration Register, offset: 0x14 */
30420   __IO  uint32_t BUF2CR;                                 /**< Buffer2 Configuration Register, offset: 0x18 */
30421   __IO  uint32_t BUF3CR;                                 /**< Buffer3 Configuration Register, offset: 0x1C */
30422   __IO  uint32_t BFGENCR;                                /**< Buffer Generic Configuration Register, offset: 0x20 */
30423   uint8_t RESERVED_1[12];
30424   __IO  uint32_t BUF0IND;                                /**< Buffer0 Top Index Register, offset: 0x30 */
30425   __IO  uint32_t BUF1IND;                                /**< Buffer1 Top Index Register, offset: 0x34 */
30426   __IO  uint32_t BUF2IND;                                /**< Buffer2 Top Index Register, offset: 0x38 */
30427   uint8_t RESERVED_2[196];
30428   __IO  uint32_t SFAR;                                   /**< Serial Flash Address Register, offset: 0x100 */
30429   uint8_t RESERVED_3[4];
30430   __IO  uint32_t SMPR;                                   /**< Sampling Register, offset: 0x108 */
30431   __I   uint32_t RBSR;                                   /**< RX Buffer Status Register, offset: 0x10C */
30432   __IO  uint32_t RBCT;                                   /**< RX Buffer Control Register, offset: 0x110 */
30433   uint8_t RESERVED_4[60];
30434   __I   uint32_t TBSR;                                   /**< TX Buffer Status Register, offset: 0x150 */
30435   __IO  uint32_t TBDR;                                   /**< TX Buffer Data Register, offset: 0x154 */
30436   uint8_t RESERVED_5[4];
30437   __I   uint32_t SR;                                     /**< Status Register, offset: 0x15C */
30438   __IO  uint32_t FR;                                     /**< Flag Register, offset: 0x160 */
30439   __IO  uint32_t RSER;                                   /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
30440   __I   uint32_t SPNDST;                                 /**< Sequence Suspend Status Register, offset: 0x168 */
30441   __IO  uint32_t SPTRCLR;                                /**< Sequence Pointer Clear Register, offset: 0x16C */
30442   uint8_t RESERVED_6[16];
30443   __IO  uint32_t SFA1AD;                                 /**< Serial Flash A1 Top Address, offset: 0x180 */
30444   __IO  uint32_t SFA2AD;                                 /**< Serial Flash A2 Top Address, offset: 0x184 */
30445   __IO  uint32_t SFB1AD;                                 /**< Serial Flash B1Top Address, offset: 0x188 */
30446   __IO  uint32_t SFB2AD;                                 /**< Serial Flash B2Top Address, offset: 0x18C */
30447   uint8_t RESERVED_7[112];
30448   __IO  uint32_t RBDR[32];                               /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
30449   uint8_t RESERVED_8[128];
30450   __IO  uint32_t LUTKEY;                                 /**< LUT Key Register, offset: 0x300 */
30451   __IO  uint32_t LCKCR;                                  /**< LUT Lock Configuration Register, offset: 0x304 */
30452   uint8_t RESERVED_9[8];
30453   __IO  uint32_t LUT[64];                                /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
30454 } QuadSPI_Type, *QuadSPI_MemMapPtr;
30455 
30456 /* ----------------------------------------------------------------------------
30457    -- QuadSPI - Register accessor macros
30458    ---------------------------------------------------------------------------- */
30459 
30460 /*!
30461  * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros
30462  * @{
30463  */
30464 
30465 /* QuadSPI - Register accessors */
30466 #define QuadSPI_MCR_REG(base)                    ((base)->MCR)
30467 #define QuadSPI_IPCR_REG(base)                   ((base)->IPCR)
30468 #define QuadSPI_FLSHCR_REG(base)                 ((base)->FLSHCR)
30469 #define QuadSPI_BUF0CR_REG(base)                 ((base)->BUF0CR)
30470 #define QuadSPI_BUF1CR_REG(base)                 ((base)->BUF1CR)
30471 #define QuadSPI_BUF2CR_REG(base)                 ((base)->BUF2CR)
30472 #define QuadSPI_BUF3CR_REG(base)                 ((base)->BUF3CR)
30473 #define QuadSPI_BFGENCR_REG(base)                ((base)->BFGENCR)
30474 #define QuadSPI_BUF0IND_REG(base)                ((base)->BUF0IND)
30475 #define QuadSPI_BUF1IND_REG(base)                ((base)->BUF1IND)
30476 #define QuadSPI_BUF2IND_REG(base)                ((base)->BUF2IND)
30477 #define QuadSPI_SFAR_REG(base)                   ((base)->SFAR)
30478 #define QuadSPI_SMPR_REG(base)                   ((base)->SMPR)
30479 #define QuadSPI_RBSR_REG(base)                   ((base)->RBSR)
30480 #define QuadSPI_RBCT_REG(base)                   ((base)->RBCT)
30481 #define QuadSPI_TBSR_REG(base)                   ((base)->TBSR)
30482 #define QuadSPI_TBDR_REG(base)                   ((base)->TBDR)
30483 #define QuadSPI_SR_REG(base)                     ((base)->SR)
30484 #define QuadSPI_FR_REG(base)                     ((base)->FR)
30485 #define QuadSPI_RSER_REG(base)                   ((base)->RSER)
30486 #define QuadSPI_SPNDST_REG(base)                 ((base)->SPNDST)
30487 #define QuadSPI_SPTRCLR_REG(base)                ((base)->SPTRCLR)
30488 #define QuadSPI_SFA1AD_REG(base)                 ((base)->SFA1AD)
30489 #define QuadSPI_SFA2AD_REG(base)                 ((base)->SFA2AD)
30490 #define QuadSPI_SFB1AD_REG(base)                 ((base)->SFB1AD)
30491 #define QuadSPI_SFB2AD_REG(base)                 ((base)->SFB2AD)
30492 #define QuadSPI_RBDR_REG(base,index)             ((base)->RBDR[index])
30493 #define QuadSPI_LUTKEY_REG(base)                 ((base)->LUTKEY)
30494 #define QuadSPI_LCKCR_REG(base)                  ((base)->LCKCR)
30495 #define QuadSPI_LUT_REG(base,index)              ((base)->LUT[index])
30496 
30497 /*!
30498  * @}
30499  */ /* end of group QuadSPI_Register_Accessor_Macros */
30500 
30501 /* ----------------------------------------------------------------------------
30502    -- QuadSPI Register Masks
30503    ---------------------------------------------------------------------------- */
30504 
30505 /*!
30506  * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
30507  * @{
30508  */
30509 
30510 /* MCR Bit Fields */
30511 #define QuadSPI_MCR_SWRSTSD_MASK                 0x1u
30512 #define QuadSPI_MCR_SWRSTSD_SHIFT                0
30513 #define QuadSPI_MCR_SWRSTHD_MASK                 0x2u
30514 #define QuadSPI_MCR_SWRSTHD_SHIFT                1
30515 #define QuadSPI_MCR_DQS_EN_MASK                  0x40u
30516 #define QuadSPI_MCR_DQS_EN_SHIFT                 6
30517 #define QuadSPI_MCR_DDR_EN_MASK                  0x80u
30518 #define QuadSPI_MCR_DDR_EN_SHIFT                 7
30519 #define QuadSPI_MCR_CLR_RXF_MASK                 0x400u
30520 #define QuadSPI_MCR_CLR_RXF_SHIFT                10
30521 #define QuadSPI_MCR_CLR_TXF_MASK                 0x800u
30522 #define QuadSPI_MCR_CLR_TXF_SHIFT                11
30523 #define QuadSPI_MCR_MDIS_MASK                    0x4000u
30524 #define QuadSPI_MCR_MDIS_SHIFT                   14
30525 #define QuadSPI_MCR_SCLKCFG_MASK                 0xFF000000u
30526 #define QuadSPI_MCR_SCLKCFG_SHIFT                24
30527 #define QuadSPI_MCR_SCLKCFG(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SCLKCFG_SHIFT))&QuadSPI_MCR_SCLKCFG_MASK)
30528 /* IPCR Bit Fields */
30529 #define QuadSPI_IPCR_IDATSZ_MASK                 0xFFFFu
30530 #define QuadSPI_IPCR_IDATSZ_SHIFT                0
30531 #define QuadSPI_IPCR_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK)
30532 #define QuadSPI_IPCR_PAR_EN_MASK                 0x10000u
30533 #define QuadSPI_IPCR_PAR_EN_SHIFT                16
30534 #define QuadSPI_IPCR_SEQID_MASK                  0xF000000u
30535 #define QuadSPI_IPCR_SEQID_SHIFT                 24
30536 #define QuadSPI_IPCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)
30537 /* FLSHCR Bit Fields */
30538 #define QuadSPI_FLSHCR_TCSS_MASK                 0xFu
30539 #define QuadSPI_FLSHCR_TCSS_SHIFT                0
30540 #define QuadSPI_FLSHCR_TCSS(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK)
30541 #define QuadSPI_FLSHCR_TCSH_MASK                 0xF00u
30542 #define QuadSPI_FLSHCR_TCSH_SHIFT                8
30543 #define QuadSPI_FLSHCR_TCSH(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK)
30544 /* BUF0CR Bit Fields */
30545 #define QuadSPI_BUF0CR_MSTRID_MASK               0xFu
30546 #define QuadSPI_BUF0CR_MSTRID_SHIFT              0
30547 #define QuadSPI_BUF0CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK)
30548 #define QuadSPI_BUF0CR_ADATSZ_MASK               0xFF00u
30549 #define QuadSPI_BUF0CR_ADATSZ_SHIFT              8
30550 #define QuadSPI_BUF0CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK)
30551 #define QuadSPI_BUF0CR_HP_EN_MASK                0x80000000u
30552 #define QuadSPI_BUF0CR_HP_EN_SHIFT               31
30553 /* BUF1CR Bit Fields */
30554 #define QuadSPI_BUF1CR_MSTRID_MASK               0xFu
30555 #define QuadSPI_BUF1CR_MSTRID_SHIFT              0
30556 #define QuadSPI_BUF1CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK)
30557 #define QuadSPI_BUF1CR_ADATSZ_MASK               0xFF00u
30558 #define QuadSPI_BUF1CR_ADATSZ_SHIFT              8
30559 #define QuadSPI_BUF1CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK)
30560 /* BUF2CR Bit Fields */
30561 #define QuadSPI_BUF2CR_MSTRID_MASK               0xFu
30562 #define QuadSPI_BUF2CR_MSTRID_SHIFT              0
30563 #define QuadSPI_BUF2CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK)
30564 #define QuadSPI_BUF2CR_ADATSZ_MASK               0xFF00u
30565 #define QuadSPI_BUF2CR_ADATSZ_SHIFT              8
30566 #define QuadSPI_BUF2CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK)
30567 /* BUF3CR Bit Fields */
30568 #define QuadSPI_BUF3CR_MSTRID_MASK               0xFu
30569 #define QuadSPI_BUF3CR_MSTRID_SHIFT              0
30570 #define QuadSPI_BUF3CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK)
30571 #define QuadSPI_BUF3CR_ADATSZ_MASK               0xFF00u
30572 #define QuadSPI_BUF3CR_ADATSZ_SHIFT              8
30573 #define QuadSPI_BUF3CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK)
30574 #define QuadSPI_BUF3CR_ALLMST_MASK               0x80000000u
30575 #define QuadSPI_BUF3CR_ALLMST_SHIFT              31
30576 /* BFGENCR Bit Fields */
30577 #define QuadSPI_BFGENCR_SEQID_MASK               0xF000u
30578 #define QuadSPI_BFGENCR_SEQID_SHIFT              12
30579 #define QuadSPI_BFGENCR_SEQID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK)
30580 #define QuadSPI_BFGENCR_PAR_EN_MASK              0x10000u
30581 #define QuadSPI_BFGENCR_PAR_EN_SHIFT             16
30582 /* BUF0IND Bit Fields */
30583 #define QuadSPI_BUF0IND_TPINDX0_MASK             0xFFFFFFF8u
30584 #define QuadSPI_BUF0IND_TPINDX0_SHIFT            3
30585 #define QuadSPI_BUF0IND_TPINDX0(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK)
30586 /* BUF1IND Bit Fields */
30587 #define QuadSPI_BUF1IND_TPINDX1_MASK             0xFFFFFFF8u
30588 #define QuadSPI_BUF1IND_TPINDX1_SHIFT            3
30589 #define QuadSPI_BUF1IND_TPINDX1(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK)
30590 /* BUF2IND Bit Fields */
30591 #define QuadSPI_BUF2IND_TPINDX2_MASK             0xFFFFFFF8u
30592 #define QuadSPI_BUF2IND_TPINDX2_SHIFT            3
30593 #define QuadSPI_BUF2IND_TPINDX2(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)
30594 /* SFAR Bit Fields */
30595 #define QuadSPI_SFAR_SFADR_MASK                  0xFFFFFFFFu
30596 #define QuadSPI_SFAR_SFADR_SHIFT                 0
30597 #define QuadSPI_SFAR_SFADR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK)
30598 /* SMPR Bit Fields */
30599 #define QuadSPI_SMPR_HSENA_MASK                  0x1u
30600 #define QuadSPI_SMPR_HSENA_SHIFT                 0
30601 #define QuadSPI_SMPR_HSPHS_MASK                  0x2u
30602 #define QuadSPI_SMPR_HSPHS_SHIFT                 1
30603 #define QuadSPI_SMPR_HSDLY_MASK                  0x4u
30604 #define QuadSPI_SMPR_HSDLY_SHIFT                 2
30605 #define QuadSPI_SMPR_FSPHS_MASK                  0x20u
30606 #define QuadSPI_SMPR_FSPHS_SHIFT                 5
30607 #define QuadSPI_SMPR_FSDLY_MASK                  0x40u
30608 #define QuadSPI_SMPR_FSDLY_SHIFT                 6
30609 #define QuadSPI_SMPR_DDRSMP_MASK                 0x70000u
30610 #define QuadSPI_SMPR_DDRSMP_SHIFT                16
30611 #define QuadSPI_SMPR_DDRSMP(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK)
30612 /* RBSR Bit Fields */
30613 #define QuadSPI_RBSR_RDBFL_MASK                  0x3F00u
30614 #define QuadSPI_RBSR_RDBFL_SHIFT                 8
30615 #define QuadSPI_RBSR_RDBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK)
30616 #define QuadSPI_RBSR_RDCTR_MASK                  0xFFFF0000u
30617 #define QuadSPI_RBSR_RDCTR_SHIFT                 16
30618 #define QuadSPI_RBSR_RDCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK)
30619 /* RBCT Bit Fields */
30620 #define QuadSPI_RBCT_WMRK_MASK                   0x1Fu
30621 #define QuadSPI_RBCT_WMRK_SHIFT                  0
30622 #define QuadSPI_RBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK)
30623 #define QuadSPI_RBCT_RXBRD_MASK                  0x100u
30624 #define QuadSPI_RBCT_RXBRD_SHIFT                 8
30625 /* TBSR Bit Fields */
30626 #define QuadSPI_TBSR_TRBFL_MASK                  0x3F00u
30627 #define QuadSPI_TBSR_TRBFL_SHIFT                 8
30628 #define QuadSPI_TBSR_TRBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK)
30629 #define QuadSPI_TBSR_TRCTR_MASK                  0xFFFF0000u
30630 #define QuadSPI_TBSR_TRCTR_SHIFT                 16
30631 #define QuadSPI_TBSR_TRCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK)
30632 /* TBDR Bit Fields */
30633 #define QuadSPI_TBDR_TXDATA_MASK                 0xFFFFFFFFu
30634 #define QuadSPI_TBDR_TXDATA_SHIFT                0
30635 #define QuadSPI_TBDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK)
30636 /* SR Bit Fields */
30637 #define QuadSPI_SR_BUSY_MASK                     0x1u
30638 #define QuadSPI_SR_BUSY_SHIFT                    0
30639 #define QuadSPI_SR_IP_ACC_MASK                   0x2u
30640 #define QuadSPI_SR_IP_ACC_SHIFT                  1
30641 #define QuadSPI_SR_AHB_ACC_MASK                  0x4u
30642 #define QuadSPI_SR_AHB_ACC_SHIFT                 2
30643 #define QuadSPI_SR_RESERVED_MASK                 0x8u
30644 #define QuadSPI_SR_RESERVED_SHIFT                3
30645 #define QuadSPI_SR_AHBGNT_MASK                   0x20u
30646 #define QuadSPI_SR_AHBGNT_SHIFT                  5
30647 #define QuadSPI_SR_AHBTRN_MASK                   0x40u
30648 #define QuadSPI_SR_AHBTRN_SHIFT                  6
30649 #define QuadSPI_SR_AHB0NE_MASK                   0x80u
30650 #define QuadSPI_SR_AHB0NE_SHIFT                  7
30651 #define QuadSPI_SR_AHB1NE_MASK                   0x100u
30652 #define QuadSPI_SR_AHB1NE_SHIFT                  8
30653 #define QuadSPI_SR_AHB2NE_MASK                   0x200u
30654 #define QuadSPI_SR_AHB2NE_SHIFT                  9
30655 #define QuadSPI_SR_AHB3NE_MASK                   0x400u
30656 #define QuadSPI_SR_AHB3NE_SHIFT                  10
30657 #define QuadSPI_SR_AHB0FUL_MASK                  0x800u
30658 #define QuadSPI_SR_AHB0FUL_SHIFT                 11
30659 #define QuadSPI_SR_AHB1FUL_MASK                  0x1000u
30660 #define QuadSPI_SR_AHB1FUL_SHIFT                 12
30661 #define QuadSPI_SR_AHB2FUL_MASK                  0x2000u
30662 #define QuadSPI_SR_AHB2FUL_SHIFT                 13
30663 #define QuadSPI_SR_AHB3FUL_MASK                  0x4000u
30664 #define QuadSPI_SR_AHB3FUL_SHIFT                 14
30665 #define QuadSPI_SR_RXWE_MASK                     0x10000u
30666 #define QuadSPI_SR_RXWE_SHIFT                    16
30667 #define QuadSPI_SR_RXFULL_MASK                   0x80000u
30668 #define QuadSPI_SR_RXFULL_SHIFT                  19
30669 #define QuadSPI_SR_RXDMA_MASK                    0x800000u
30670 #define QuadSPI_SR_RXDMA_SHIFT                   23
30671 #define QuadSPI_SR_TXEDA_MASK                    0x1000000u
30672 #define QuadSPI_SR_TXEDA_SHIFT                   24
30673 #define QuadSPI_SR_TXFULL_MASK                   0x8000000u
30674 #define QuadSPI_SR_TXFULL_SHIFT                  27
30675 #define QuadSPI_SR_DLPSMP_MASK                   0xE0000000u
30676 #define QuadSPI_SR_DLPSMP_SHIFT                  29
30677 #define QuadSPI_SR_DLPSMP(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK)
30678 /* FR Bit Fields */
30679 #define QuadSPI_FR_TFF_MASK                      0x1u
30680 #define QuadSPI_FR_TFF_SHIFT                     0
30681 #define QuadSPI_FR_IPGEF_MASK                    0x10u
30682 #define QuadSPI_FR_IPGEF_SHIFT                   4
30683 #define QuadSPI_FR_IPIEF_MASK                    0x40u
30684 #define QuadSPI_FR_IPIEF_SHIFT                   6
30685 #define QuadSPI_FR_IPAEF_MASK                    0x80u
30686 #define QuadSPI_FR_IPAEF_SHIFT                   7
30687 #define QuadSPI_FR_IUEF_MASK                     0x800u
30688 #define QuadSPI_FR_IUEF_SHIFT                    11
30689 #define QuadSPI_FR_ABOF_MASK                     0x1000u
30690 #define QuadSPI_FR_ABOF_SHIFT                    12
30691 #define QuadSPI_FR_ABSEF_MASK                    0x8000u
30692 #define QuadSPI_FR_ABSEF_SHIFT                   15
30693 #define QuadSPI_FR_RBDF_MASK                     0x10000u
30694 #define QuadSPI_FR_RBDF_SHIFT                    16
30695 #define QuadSPI_FR_RBOF_MASK                     0x20000u
30696 #define QuadSPI_FR_RBOF_SHIFT                    17
30697 #define QuadSPI_FR_ILLINE_MASK                   0x800000u
30698 #define QuadSPI_FR_ILLINE_SHIFT                  23
30699 #define QuadSPI_FR_TBUF_MASK                     0x4000000u
30700 #define QuadSPI_FR_TBUF_SHIFT                    26
30701 #define QuadSPI_FR_TBFF_MASK                     0x8000000u
30702 #define QuadSPI_FR_TBFF_SHIFT                    27
30703 #define QuadSPI_FR_RESERVED_MASK                 0x60000000u
30704 #define QuadSPI_FR_RESERVED_SHIFT                29
30705 #define QuadSPI_FR_RESERVED(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_RESERVED_SHIFT))&QuadSPI_FR_RESERVED_MASK)
30706 #define QuadSPI_FR_DLPFF_MASK                    0x80000000u
30707 #define QuadSPI_FR_DLPFF_SHIFT                   31
30708 /* RSER Bit Fields */
30709 #define QuadSPI_RSER_TFIE_MASK                   0x1u
30710 #define QuadSPI_RSER_TFIE_SHIFT                  0
30711 #define QuadSPI_RSER_IPGEIE_MASK                 0x10u
30712 #define QuadSPI_RSER_IPGEIE_SHIFT                4
30713 #define QuadSPI_RSER_IPIEIE_MASK                 0x40u
30714 #define QuadSPI_RSER_IPIEIE_SHIFT                6
30715 #define QuadSPI_RSER_IPAEIE_MASK                 0x80u
30716 #define QuadSPI_RSER_IPAEIE_SHIFT                7
30717 #define QuadSPI_RSER_IUEIE_MASK                  0x800u
30718 #define QuadSPI_RSER_IUEIE_SHIFT                 11
30719 #define QuadSPI_RSER_ABOIE_MASK                  0x1000u
30720 #define QuadSPI_RSER_ABOIE_SHIFT                 12
30721 #define QuadSPI_RSER_ABSEIE_MASK                 0x8000u
30722 #define QuadSPI_RSER_ABSEIE_SHIFT                15
30723 #define QuadSPI_RSER_RBDIE_MASK                  0x10000u
30724 #define QuadSPI_RSER_RBDIE_SHIFT                 16
30725 #define QuadSPI_RSER_RBOIE_MASK                  0x20000u
30726 #define QuadSPI_RSER_RBOIE_SHIFT                 17
30727 #define QuadSPI_RSER_RBDDE_MASK                  0x200000u
30728 #define QuadSPI_RSER_RBDDE_SHIFT                 21
30729 #define QuadSPI_RSER_ILLINIE_MASK                0x800000u
30730 #define QuadSPI_RSER_ILLINIE_SHIFT               23
30731 #define QuadSPI_RSER_TBUIE_MASK                  0x4000000u
30732 #define QuadSPI_RSER_TBUIE_SHIFT                 26
30733 #define QuadSPI_RSER_TBFIE_MASK                  0x8000000u
30734 #define QuadSPI_RSER_TBFIE_SHIFT                 27
30735 #define QuadSPI_RSER_RESERVED_MASK               0x10000000u
30736 #define QuadSPI_RSER_RESERVED_SHIFT              28
30737 #define QuadSPI_RSER_DLPFIE_MASK                 0x80000000u
30738 #define QuadSPI_RSER_DLPFIE_SHIFT                31
30739 /* SPNDST Bit Fields */
30740 #define QuadSPI_SPNDST_SUSPND_MASK               0x1u
30741 #define QuadSPI_SPNDST_SUSPND_SHIFT              0
30742 #define QuadSPI_SPNDST_SPDBUF_MASK               0xC0u
30743 #define QuadSPI_SPNDST_SPDBUF_SHIFT              6
30744 #define QuadSPI_SPNDST_SPDBUF(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK)
30745 #define QuadSPI_SPNDST_DATLFT_MASK               0xFE00u
30746 #define QuadSPI_SPNDST_DATLFT_SHIFT              9
30747 #define QuadSPI_SPNDST_DATLFT(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK)
30748 /* SPTRCLR Bit Fields */
30749 #define QuadSPI_SPTRCLR_BFPTRC_MASK              0x1u
30750 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT             0
30751 #define QuadSPI_SPTRCLR_IPPTRC_MASK              0x100u
30752 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT             8
30753 /* SFA1AD Bit Fields */
30754 #define QuadSPI_SFA1AD_TPADA1_MASK               0xFFFFFC00u
30755 #define QuadSPI_SFA1AD_TPADA1_SHIFT              10
30756 #define QuadSPI_SFA1AD_TPADA1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK)
30757 /* SFA2AD Bit Fields */
30758 #define QuadSPI_SFA2AD_TPADA2_MASK               0xFFFFFC00u
30759 #define QuadSPI_SFA2AD_TPADA2_SHIFT              10
30760 #define QuadSPI_SFA2AD_TPADA2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK)
30761 /* SFB1AD Bit Fields */
30762 #define QuadSPI_SFB1AD_TPADB1_MASK               0xFFFFFC00u
30763 #define QuadSPI_SFB1AD_TPADB1_SHIFT              10
30764 #define QuadSPI_SFB1AD_TPADB1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK)
30765 /* SFB2AD Bit Fields */
30766 #define QuadSPI_SFB2AD_TPADB2_MASK               0xFFFFFC00u
30767 #define QuadSPI_SFB2AD_TPADB2_SHIFT              10
30768 #define QuadSPI_SFB2AD_TPADB2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK)
30769 /* RBDR Bit Fields */
30770 #define QuadSPI_RBDR_RXDATA_MASK                 0xFFFFFFFFu
30771 #define QuadSPI_RBDR_RXDATA_SHIFT                0
30772 #define QuadSPI_RBDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK)
30773 /* LUTKEY Bit Fields */
30774 #define QuadSPI_LUTKEY_KEY_MASK                  0xFFFFFFFFu
30775 #define QuadSPI_LUTKEY_KEY_SHIFT                 0
30776 #define QuadSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK)
30777 /* LCKCR Bit Fields */
30778 #define QuadSPI_LCKCR_LOCK_MASK                  0x1u
30779 #define QuadSPI_LCKCR_LOCK_SHIFT                 0
30780 #define QuadSPI_LCKCR_UNLOCK_MASK                0x2u
30781 #define QuadSPI_LCKCR_UNLOCK_SHIFT               1
30782 /* LUT Bit Fields */
30783 #define QuadSPI_LUT_OPRND0_MASK                  0xFFu
30784 #define QuadSPI_LUT_OPRND0_SHIFT                 0
30785 #define QuadSPI_LUT_OPRND0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK)
30786 #define QuadSPI_LUT_PAD0_MASK                    0x300u
30787 #define QuadSPI_LUT_PAD0_SHIFT                   8
30788 #define QuadSPI_LUT_PAD0(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK)
30789 #define QuadSPI_LUT_INSTR0_MASK                  0xFC00u
30790 #define QuadSPI_LUT_INSTR0_SHIFT                 10
30791 #define QuadSPI_LUT_INSTR0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK)
30792 #define QuadSPI_LUT_OPRND1_MASK                  0xFF0000u
30793 #define QuadSPI_LUT_OPRND1_SHIFT                 16
30794 #define QuadSPI_LUT_OPRND1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK)
30795 #define QuadSPI_LUT_PAD1_MASK                    0x3000000u
30796 #define QuadSPI_LUT_PAD1_SHIFT                   24
30797 #define QuadSPI_LUT_PAD1(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK)
30798 #define QuadSPI_LUT_INSTR1_MASK                  0xFC000000u
30799 #define QuadSPI_LUT_INSTR1_SHIFT                 26
30800 #define QuadSPI_LUT_INSTR1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK)
30801 
30802 /*!
30803  * @}
30804  */ /* end of group QuadSPI_Register_Masks */
30805 
30806 /* QuadSPI - Peripheral instance base addresses */
30807 /** Peripheral QuadSPI1 base address */
30808 #define QuadSPI1_BASE                            (0x421E0000u)
30809 /** Peripheral QuadSPI1 base pointer */
30810 #define QuadSPI1                                 ((QuadSPI_Type *)QuadSPI1_BASE)
30811 #define QuadSPI1_BASE_PTR                        (QuadSPI1)
30812 /** Peripheral QuadSPI2 base address */
30813 #define QuadSPI2_BASE                            (0x421E4000u)
30814 /** Peripheral QuadSPI2 base pointer */
30815 #define QuadSPI2                                 ((QuadSPI_Type *)QuadSPI2_BASE)
30816 #define QuadSPI2_BASE_PTR                        (QuadSPI2)
30817 /** Array initializer of QuadSPI peripheral base addresses */
30818 #define QuadSPI_BASE_ADDRS                       { QuadSPI1_BASE, QuadSPI2_BASE }
30819 /** Array initializer of QuadSPI peripheral base pointers */
30820 #define QuadSPI_BASE_PTRS                        { QuadSPI1, QuadSPI2 }
30821 /** Interrupt vectors for the QuadSPI peripheral type */
30822 #define QSPI_IRQS                                { QSPI1_IRQn, QSPI2_IRQn }
30823 
30824 /* ----------------------------------------------------------------------------
30825    -- QuadSPI - Register accessor macros
30826    ---------------------------------------------------------------------------- */
30827 
30828 /*!
30829  * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros
30830  * @{
30831  */
30832 
30833 /* QuadSPI - Register instance definitions */
30834 /* QuadSPI1 */
30835 #define QuadSPI1_MCR                             QuadSPI_MCR_REG(QuadSPI1_BASE_PTR)
30836 #define QuadSPI1_IPCR                            QuadSPI_IPCR_REG(QuadSPI1_BASE_PTR)
30837 #define QuadSPI1_FLSHCR                          QuadSPI_FLSHCR_REG(QuadSPI1_BASE_PTR)
30838 #define QuadSPI1_BUF0CR                          QuadSPI_BUF0CR_REG(QuadSPI1_BASE_PTR)
30839 #define QuadSPI1_BUF1CR                          QuadSPI_BUF1CR_REG(QuadSPI1_BASE_PTR)
30840 #define QuadSPI1_BUF2CR                          QuadSPI_BUF2CR_REG(QuadSPI1_BASE_PTR)
30841 #define QuadSPI1_BUF3CR                          QuadSPI_BUF3CR_REG(QuadSPI1_BASE_PTR)
30842 #define QuadSPI1_BFGENCR                         QuadSPI_BFGENCR_REG(QuadSPI1_BASE_PTR)
30843 #define QuadSPI1_BUF0IND                         QuadSPI_BUF0IND_REG(QuadSPI1_BASE_PTR)
30844 #define QuadSPI1_BUF1IND                         QuadSPI_BUF1IND_REG(QuadSPI1_BASE_PTR)
30845 #define QuadSPI1_BUF2IND                         QuadSPI_BUF2IND_REG(QuadSPI1_BASE_PTR)
30846 #define QuadSPI1_SFAR                            QuadSPI_SFAR_REG(QuadSPI1_BASE_PTR)
30847 #define QuadSPI1_SMPR                            QuadSPI_SMPR_REG(QuadSPI1_BASE_PTR)
30848 #define QuadSPI1_RBSR                            QuadSPI_RBSR_REG(QuadSPI1_BASE_PTR)
30849 #define QuadSPI1_RBCT                            QuadSPI_RBCT_REG(QuadSPI1_BASE_PTR)
30850 #define QuadSPI1_TBSR                            QuadSPI_TBSR_REG(QuadSPI1_BASE_PTR)
30851 #define QuadSPI1_TBDR                            QuadSPI_TBDR_REG(QuadSPI1_BASE_PTR)
30852 #define QuadSPI1_SR                              QuadSPI_SR_REG(QuadSPI1_BASE_PTR)
30853 #define QuadSPI1_FR                              QuadSPI_FR_REG(QuadSPI1_BASE_PTR)
30854 #define QuadSPI1_RSER                            QuadSPI_RSER_REG(QuadSPI1_BASE_PTR)
30855 #define QuadSPI1_SPNDST                          QuadSPI_SPNDST_REG(QuadSPI1_BASE_PTR)
30856 #define QuadSPI1_SPTRCLR                         QuadSPI_SPTRCLR_REG(QuadSPI1_BASE_PTR)
30857 #define QuadSPI1_SFA1AD                          QuadSPI_SFA1AD_REG(QuadSPI1_BASE_PTR)
30858 #define QuadSPI1_SFA2AD                          QuadSPI_SFA2AD_REG(QuadSPI1_BASE_PTR)
30859 #define QuadSPI1_SFB1AD                          QuadSPI_SFB1AD_REG(QuadSPI1_BASE_PTR)
30860 #define QuadSPI1_SFB2AD                          QuadSPI_SFB2AD_REG(QuadSPI1_BASE_PTR)
30861 #define QuadSPI1_RBDR0                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,0)
30862 #define QuadSPI1_RBDR1                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,1)
30863 #define QuadSPI1_RBDR2                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,2)
30864 #define QuadSPI1_RBDR3                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,3)
30865 #define QuadSPI1_RBDR4                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,4)
30866 #define QuadSPI1_RBDR5                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,5)
30867 #define QuadSPI1_RBDR6                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,6)
30868 #define QuadSPI1_RBDR7                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,7)
30869 #define QuadSPI1_RBDR8                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,8)
30870 #define QuadSPI1_RBDR9                           QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,9)
30871 #define QuadSPI1_RBDR10                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,10)
30872 #define QuadSPI1_RBDR11                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,11)
30873 #define QuadSPI1_RBDR12                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,12)
30874 #define QuadSPI1_RBDR13                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,13)
30875 #define QuadSPI1_RBDR14                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,14)
30876 #define QuadSPI1_RBDR15                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,15)
30877 #define QuadSPI1_RBDR16                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,16)
30878 #define QuadSPI1_RBDR17                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,17)
30879 #define QuadSPI1_RBDR18                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,18)
30880 #define QuadSPI1_RBDR19                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,19)
30881 #define QuadSPI1_RBDR20                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,20)
30882 #define QuadSPI1_RBDR21                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,21)
30883 #define QuadSPI1_RBDR22                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,22)
30884 #define QuadSPI1_RBDR23                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,23)
30885 #define QuadSPI1_RBDR24                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,24)
30886 #define QuadSPI1_RBDR25                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,25)
30887 #define QuadSPI1_RBDR26                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,26)
30888 #define QuadSPI1_RBDR27                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,27)
30889 #define QuadSPI1_RBDR28                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,28)
30890 #define QuadSPI1_RBDR29                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,29)
30891 #define QuadSPI1_RBDR30                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,30)
30892 #define QuadSPI1_RBDR31                          QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,31)
30893 #define QuadSPI1_LUTKEY                          QuadSPI_LUTKEY_REG(QuadSPI1_BASE_PTR)
30894 #define QuadSPI1_LCKCR                           QuadSPI_LCKCR_REG(QuadSPI1_BASE_PTR)
30895 #define QuadSPI1_LUT0                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,0)
30896 #define QuadSPI1_LUT1                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,1)
30897 #define QuadSPI1_LUT2                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,2)
30898 #define QuadSPI1_LUT3                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,3)
30899 #define QuadSPI1_LUT4                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,4)
30900 #define QuadSPI1_LUT5                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,5)
30901 #define QuadSPI1_LUT6                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,6)
30902 #define QuadSPI1_LUT7                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,7)
30903 #define QuadSPI1_LUT8                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,8)
30904 #define QuadSPI1_LUT9                            QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,9)
30905 #define QuadSPI1_LUT10                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,10)
30906 #define QuadSPI1_LUT11                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,11)
30907 #define QuadSPI1_LUT12                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,12)
30908 #define QuadSPI1_LUT13                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,13)
30909 #define QuadSPI1_LUT14                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,14)
30910 #define QuadSPI1_LUT15                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,15)
30911 #define QuadSPI1_LUT16                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,16)
30912 #define QuadSPI1_LUT17                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,17)
30913 #define QuadSPI1_LUT18                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,18)
30914 #define QuadSPI1_LUT19                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,19)
30915 #define QuadSPI1_LUT20                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,20)
30916 #define QuadSPI1_LUT21                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,21)
30917 #define QuadSPI1_LUT22                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,22)
30918 #define QuadSPI1_LUT23                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,23)
30919 #define QuadSPI1_LUT24                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,24)
30920 #define QuadSPI1_LUT25                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,25)
30921 #define QuadSPI1_LUT26                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,26)
30922 #define QuadSPI1_LUT27                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,27)
30923 #define QuadSPI1_LUT28                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,28)
30924 #define QuadSPI1_LUT29                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,29)
30925 #define QuadSPI1_LUT30                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,30)
30926 #define QuadSPI1_LUT31                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,31)
30927 #define QuadSPI1_LUT32                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,32)
30928 #define QuadSPI1_LUT33                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,33)
30929 #define QuadSPI1_LUT34                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,34)
30930 #define QuadSPI1_LUT35                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,35)
30931 #define QuadSPI1_LUT36                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,36)
30932 #define QuadSPI1_LUT37                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,37)
30933 #define QuadSPI1_LUT38                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,38)
30934 #define QuadSPI1_LUT39                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,39)
30935 #define QuadSPI1_LUT40                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,40)
30936 #define QuadSPI1_LUT41                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,41)
30937 #define QuadSPI1_LUT42                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,42)
30938 #define QuadSPI1_LUT43                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,43)
30939 #define QuadSPI1_LUT44                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,44)
30940 #define QuadSPI1_LUT45                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,45)
30941 #define QuadSPI1_LUT46                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,46)
30942 #define QuadSPI1_LUT47                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,47)
30943 #define QuadSPI1_LUT48                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,48)
30944 #define QuadSPI1_LUT49                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,49)
30945 #define QuadSPI1_LUT50                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,50)
30946 #define QuadSPI1_LUT51                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,51)
30947 #define QuadSPI1_LUT52                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,52)
30948 #define QuadSPI1_LUT53                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,53)
30949 #define QuadSPI1_LUT54                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,54)
30950 #define QuadSPI1_LUT55                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,55)
30951 #define QuadSPI1_LUT56                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,56)
30952 #define QuadSPI1_LUT57                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,57)
30953 #define QuadSPI1_LUT58                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,58)
30954 #define QuadSPI1_LUT59                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,59)
30955 #define QuadSPI1_LUT60                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,60)
30956 #define QuadSPI1_LUT61                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,61)
30957 #define QuadSPI1_LUT62                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,62)
30958 #define QuadSPI1_LUT63                           QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,63)
30959 /* QuadSPI2 */
30960 #define QuadSPI2_MCR                             QuadSPI_MCR_REG(QuadSPI2_BASE_PTR)
30961 #define QuadSPI2_IPCR                            QuadSPI_IPCR_REG(QuadSPI2_BASE_PTR)
30962 #define QuadSPI2_FLSHCR                          QuadSPI_FLSHCR_REG(QuadSPI2_BASE_PTR)
30963 #define QuadSPI2_BUF0CR                          QuadSPI_BUF0CR_REG(QuadSPI2_BASE_PTR)
30964 #define QuadSPI2_BUF1CR                          QuadSPI_BUF1CR_REG(QuadSPI2_BASE_PTR)
30965 #define QuadSPI2_BUF2CR                          QuadSPI_BUF2CR_REG(QuadSPI2_BASE_PTR)
30966 #define QuadSPI2_BUF3CR                          QuadSPI_BUF3CR_REG(QuadSPI2_BASE_PTR)
30967 #define QuadSPI2_BFGENCR                         QuadSPI_BFGENCR_REG(QuadSPI2_BASE_PTR)
30968 #define QuadSPI2_BUF0IND                         QuadSPI_BUF0IND_REG(QuadSPI2_BASE_PTR)
30969 #define QuadSPI2_BUF1IND                         QuadSPI_BUF1IND_REG(QuadSPI2_BASE_PTR)
30970 #define QuadSPI2_BUF2IND                         QuadSPI_BUF2IND_REG(QuadSPI2_BASE_PTR)
30971 #define QuadSPI2_SFAR                            QuadSPI_SFAR_REG(QuadSPI2_BASE_PTR)
30972 #define QuadSPI2_SMPR                            QuadSPI_SMPR_REG(QuadSPI2_BASE_PTR)
30973 #define QuadSPI2_RBSR                            QuadSPI_RBSR_REG(QuadSPI2_BASE_PTR)
30974 #define QuadSPI2_RBCT                            QuadSPI_RBCT_REG(QuadSPI2_BASE_PTR)
30975 #define QuadSPI2_TBSR                            QuadSPI_TBSR_REG(QuadSPI2_BASE_PTR)
30976 #define QuadSPI2_TBDR                            QuadSPI_TBDR_REG(QuadSPI2_BASE_PTR)
30977 #define QuadSPI2_SR                              QuadSPI_SR_REG(QuadSPI2_BASE_PTR)
30978 #define QuadSPI2_FR                              QuadSPI_FR_REG(QuadSPI2_BASE_PTR)
30979 #define QuadSPI2_RSER                            QuadSPI_RSER_REG(QuadSPI2_BASE_PTR)
30980 #define QuadSPI2_SPNDST                          QuadSPI_SPNDST_REG(QuadSPI2_BASE_PTR)
30981 #define QuadSPI2_SPTRCLR                         QuadSPI_SPTRCLR_REG(QuadSPI2_BASE_PTR)
30982 #define QuadSPI2_SFA1AD                          QuadSPI_SFA1AD_REG(QuadSPI2_BASE_PTR)
30983 #define QuadSPI2_SFA2AD                          QuadSPI_SFA2AD_REG(QuadSPI2_BASE_PTR)
30984 #define QuadSPI2_SFB1AD                          QuadSPI_SFB1AD_REG(QuadSPI2_BASE_PTR)
30985 #define QuadSPI2_SFB2AD                          QuadSPI_SFB2AD_REG(QuadSPI2_BASE_PTR)
30986 #define QuadSPI2_RBDR0                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,0)
30987 #define QuadSPI2_RBDR1                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,1)
30988 #define QuadSPI2_RBDR2                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,2)
30989 #define QuadSPI2_RBDR3                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,3)
30990 #define QuadSPI2_RBDR4                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,4)
30991 #define QuadSPI2_RBDR5                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,5)
30992 #define QuadSPI2_RBDR6                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,6)
30993 #define QuadSPI2_RBDR7                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,7)
30994 #define QuadSPI2_RBDR8                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,8)
30995 #define QuadSPI2_RBDR9                           QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,9)
30996 #define QuadSPI2_RBDR10                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,10)
30997 #define QuadSPI2_RBDR11                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,11)
30998 #define QuadSPI2_RBDR12                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,12)
30999 #define QuadSPI2_RBDR13                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,13)
31000 #define QuadSPI2_RBDR14                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,14)
31001 #define QuadSPI2_RBDR15                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,15)
31002 #define QuadSPI2_RBDR16                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,16)
31003 #define QuadSPI2_RBDR17                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,17)
31004 #define QuadSPI2_RBDR18                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,18)
31005 #define QuadSPI2_RBDR19                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,19)
31006 #define QuadSPI2_RBDR20                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,20)
31007 #define QuadSPI2_RBDR21                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,21)
31008 #define QuadSPI2_RBDR22                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,22)
31009 #define QuadSPI2_RBDR23                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,23)
31010 #define QuadSPI2_RBDR24                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,24)
31011 #define QuadSPI2_RBDR25                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,25)
31012 #define QuadSPI2_RBDR26                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,26)
31013 #define QuadSPI2_RBDR27                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,27)
31014 #define QuadSPI2_RBDR28                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,28)
31015 #define QuadSPI2_RBDR29                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,29)
31016 #define QuadSPI2_RBDR30                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,30)
31017 #define QuadSPI2_RBDR31                          QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,31)
31018 #define QuadSPI2_LUTKEY                          QuadSPI_LUTKEY_REG(QuadSPI2_BASE_PTR)
31019 #define QuadSPI2_LCKCR                           QuadSPI_LCKCR_REG(QuadSPI2_BASE_PTR)
31020 #define QuadSPI2_LUT0                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,0)
31021 #define QuadSPI2_LUT1                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,1)
31022 #define QuadSPI2_LUT2                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,2)
31023 #define QuadSPI2_LUT3                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,3)
31024 #define QuadSPI2_LUT4                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,4)
31025 #define QuadSPI2_LUT5                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,5)
31026 #define QuadSPI2_LUT6                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,6)
31027 #define QuadSPI2_LUT7                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,7)
31028 #define QuadSPI2_LUT8                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,8)
31029 #define QuadSPI2_LUT9                            QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,9)
31030 #define QuadSPI2_LUT10                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,10)
31031 #define QuadSPI2_LUT11                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,11)
31032 #define QuadSPI2_LUT12                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,12)
31033 #define QuadSPI2_LUT13                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,13)
31034 #define QuadSPI2_LUT14                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,14)
31035 #define QuadSPI2_LUT15                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,15)
31036 #define QuadSPI2_LUT16                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,16)
31037 #define QuadSPI2_LUT17                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,17)
31038 #define QuadSPI2_LUT18                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,18)
31039 #define QuadSPI2_LUT19                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,19)
31040 #define QuadSPI2_LUT20                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,20)
31041 #define QuadSPI2_LUT21                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,21)
31042 #define QuadSPI2_LUT22                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,22)
31043 #define QuadSPI2_LUT23                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,23)
31044 #define QuadSPI2_LUT24                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,24)
31045 #define QuadSPI2_LUT25                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,25)
31046 #define QuadSPI2_LUT26                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,26)
31047 #define QuadSPI2_LUT27                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,27)
31048 #define QuadSPI2_LUT28                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,28)
31049 #define QuadSPI2_LUT29                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,29)
31050 #define QuadSPI2_LUT30                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,30)
31051 #define QuadSPI2_LUT31                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,31)
31052 #define QuadSPI2_LUT32                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,32)
31053 #define QuadSPI2_LUT33                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,33)
31054 #define QuadSPI2_LUT34                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,34)
31055 #define QuadSPI2_LUT35                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,35)
31056 #define QuadSPI2_LUT36                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,36)
31057 #define QuadSPI2_LUT37                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,37)
31058 #define QuadSPI2_LUT38                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,38)
31059 #define QuadSPI2_LUT39                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,39)
31060 #define QuadSPI2_LUT40                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,40)
31061 #define QuadSPI2_LUT41                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,41)
31062 #define QuadSPI2_LUT42                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,42)
31063 #define QuadSPI2_LUT43                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,43)
31064 #define QuadSPI2_LUT44                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,44)
31065 #define QuadSPI2_LUT45                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,45)
31066 #define QuadSPI2_LUT46                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,46)
31067 #define QuadSPI2_LUT47                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,47)
31068 #define QuadSPI2_LUT48                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,48)
31069 #define QuadSPI2_LUT49                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,49)
31070 #define QuadSPI2_LUT50                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,50)
31071 #define QuadSPI2_LUT51                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,51)
31072 #define QuadSPI2_LUT52                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,52)
31073 #define QuadSPI2_LUT53                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,53)
31074 #define QuadSPI2_LUT54                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,54)
31075 #define QuadSPI2_LUT55                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,55)
31076 #define QuadSPI2_LUT56                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,56)
31077 #define QuadSPI2_LUT57                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,57)
31078 #define QuadSPI2_LUT58                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,58)
31079 #define QuadSPI2_LUT59                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,59)
31080 #define QuadSPI2_LUT60                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,60)
31081 #define QuadSPI2_LUT61                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,61)
31082 #define QuadSPI2_LUT62                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,62)
31083 #define QuadSPI2_LUT63                           QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,63)
31084 /* QuadSPI - Register array accessors */
31085 #define QuadSPI1_RBDR(index)                     QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,index)
31086 #define QuadSPI2_RBDR(index)                     QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,index)
31087 #define QuadSPI1_LUT(index)                      QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,index)
31088 #define QuadSPI2_LUT(index)                      QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,index)
31089 
31090 /*!
31091  * @}
31092  */ /* end of group QuadSPI_Register_Accessor_Macros */
31093 
31094 /*!
31095  * @}
31096  */ /* end of group QuadSPI_Peripheral */
31097 
31098 /* ----------------------------------------------------------------------------
31099    -- RDC Peripheral Access Layer
31100    ---------------------------------------------------------------------------- */
31101 
31102 /*!
31103  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
31104  * @{
31105  */
31106 
31107 /** RDC - Register Layout Typedef */
31108 typedef struct {
31109   __I   uint32_t VIR;                                    /**< Version Information, offset: 0x0 */
31110   uint8_t RESERVED_0[32];
31111   __IO  uint32_t STAT;                                   /**< Status, offset: 0x24 */
31112   __IO  uint32_t INTCTRL;                                /**< Interrupt and Control, offset: 0x28 */
31113   __IO  uint32_t INTSTAT;                                /**< Interrupt Status, offset: 0x2C */
31114   uint8_t RESERVED_1[464];
31115   __IO  uint32_t MDA[32];                                /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
31116   uint8_t RESERVED_2[384];
31117   __IO  uint32_t PDAP[110];                              /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
31118   uint8_t RESERVED_3[584];
31119   struct {                                         /* offset: 0x800, array step: 0x10 */
31120   __IO    uint32_t MRSA;                                   /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
31121   __IO    uint32_t MREA;                                   /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
31122   __IO    uint32_t MRC;                                    /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
31123   __IO    uint32_t MRVS;                                   /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
31124  } MR[55];
31125 } RDC_Type, *RDC_MemMapPtr;
31126 
31127 /* ----------------------------------------------------------------------------
31128    -- RDC - Register accessor macros
31129    ---------------------------------------------------------------------------- */
31130 
31131 /*!
31132  * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros
31133  * @{
31134  */
31135 
31136 /* RDC - Register accessors */
31137 #define RDC_VIR_REG(base)                        ((base)->VIR)
31138 #define RDC_STAT_REG(base)                       ((base)->STAT)
31139 #define RDC_INTCTRL_REG(base)                    ((base)->INTCTRL)
31140 #define RDC_INTSTAT_REG(base)                    ((base)->INTSTAT)
31141 #define RDC_MDA_REG(base,index)                  ((base)->MDA[index])
31142 #define RDC_PDAP_REG(base,index)                 ((base)->PDAP[index])
31143 #define RDC_MRSA_REG(base,index)                 ((base)->MR[index].MRSA)
31144 #define RDC_MREA_REG(base,index)                 ((base)->MR[index].MREA)
31145 #define RDC_MRC_REG(base,index)                  ((base)->MR[index].MRC)
31146 #define RDC_MRVS_REG(base,index)                 ((base)->MR[index].MRVS)
31147 
31148 /*!
31149  * @}
31150  */ /* end of group RDC_Register_Accessor_Macros */
31151 /* ----------------------------------------------------------------------------
31152    -- RDC Register Masks
31153    ---------------------------------------------------------------------------- */
31154 
31155 /*!
31156  * @addtogroup RDC_Register_Masks RDC Register Masks
31157  * @{
31158  */
31159 
31160 /* VIR Bit Fields */
31161 #define RDC_VIR_NDID_MASK                        0xFu
31162 #define RDC_VIR_NDID_SHIFT                       0
31163 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NDID_SHIFT))&RDC_VIR_NDID_MASK)
31164 #define RDC_VIR_NMSTR_MASK                       0xFF0u
31165 #define RDC_VIR_NMSTR_SHIFT                      4
31166 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NMSTR_SHIFT))&RDC_VIR_NMSTR_MASK)
31167 #define RDC_VIR_NPER_MASK                        0xFF000u
31168 #define RDC_VIR_NPER_SHIFT                       12
31169 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NPER_SHIFT))&RDC_VIR_NPER_MASK)
31170 #define RDC_VIR_NRGN_MASK                        0xFF00000u
31171 #define RDC_VIR_NRGN_SHIFT                       20
31172 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NRGN_SHIFT))&RDC_VIR_NRGN_MASK)
31173 /* STAT Bit Fields */
31174 #define RDC_STAT_DID_MASK                        0xFu
31175 #define RDC_STAT_DID_SHIFT                       0
31176 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x))<<RDC_STAT_DID_SHIFT))&RDC_STAT_DID_MASK)
31177 #define RDC_STAT_PDS_MASK                        0x100u
31178 #define RDC_STAT_PDS_SHIFT                       8
31179 /* INTCTRL Bit Fields */
31180 #define RDC_INTCTRL_RCI_EN_MASK                  0x1u
31181 #define RDC_INTCTRL_RCI_EN_SHIFT                 0
31182 /* INTSTAT Bit Fields */
31183 #define RDC_INTSTAT_INT_MASK                     0x1u
31184 #define RDC_INTSTAT_INT_SHIFT                    0
31185 /* MDA Bit Fields */
31186 #define RDC_MDA_DID_MASK                         0x3u
31187 #define RDC_MDA_DID_SHIFT                        0
31188 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x))<<RDC_MDA_DID_SHIFT))&RDC_MDA_DID_MASK)
31189 #define RDC_MDA_LCK_MASK                         0x80000000u
31190 #define RDC_MDA_LCK_SHIFT                        31
31191 /* PDAP Bit Fields */
31192 #define RDC_PDAP_D0W_MASK                        0x1u
31193 #define RDC_PDAP_D0W_SHIFT                       0
31194 #define RDC_PDAP_D0R_MASK                        0x2u
31195 #define RDC_PDAP_D0R_SHIFT                       1
31196 #define RDC_PDAP_D1W_MASK                        0x4u
31197 #define RDC_PDAP_D1W_SHIFT                       2
31198 #define RDC_PDAP_D1R_MASK                        0x8u
31199 #define RDC_PDAP_D1R_SHIFT                       3
31200 #define RDC_PDAP_D2W_MASK                        0x10u
31201 #define RDC_PDAP_D2W_SHIFT                       4
31202 #define RDC_PDAP_D2R_MASK                        0x20u
31203 #define RDC_PDAP_D2R_SHIFT                       5
31204 #define RDC_PDAP_D3W_MASK                        0x40u
31205 #define RDC_PDAP_D3W_SHIFT                       6
31206 #define RDC_PDAP_D3R_MASK                        0x80u
31207 #define RDC_PDAP_D3R_SHIFT                       7
31208 #define RDC_PDAP_SREQ_MASK                       0x40000000u
31209 #define RDC_PDAP_SREQ_SHIFT                      30
31210 #define RDC_PDAP_LCK_MASK                        0x80000000u
31211 #define RDC_PDAP_LCK_SHIFT                       31
31212 /* MRSA Bit Fields */
31213 #define RDC_MRSA_SADR_MASK                       0xFFFFFF80u
31214 #define RDC_MRSA_SADR_SHIFT                      7
31215 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRSA_SADR_SHIFT))&RDC_MRSA_SADR_MASK)
31216 /* MREA Bit Fields */
31217 #define RDC_MREA_EADR_MASK                       0xFFFFFF80u
31218 #define RDC_MREA_EADR_SHIFT                      7
31219 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MREA_EADR_SHIFT))&RDC_MREA_EADR_MASK)
31220 /* MRC Bit Fields */
31221 #define RDC_MRC_D0W_MASK                         0x1u
31222 #define RDC_MRC_D0W_SHIFT                        0
31223 #define RDC_MRC_D0R_MASK                         0x2u
31224 #define RDC_MRC_D0R_SHIFT                        1
31225 #define RDC_MRC_D1W_MASK                         0x4u
31226 #define RDC_MRC_D1W_SHIFT                        2
31227 #define RDC_MRC_D1R_MASK                         0x8u
31228 #define RDC_MRC_D1R_SHIFT                        3
31229 #define RDC_MRC_D2W_MASK                         0x10u
31230 #define RDC_MRC_D2W_SHIFT                        4
31231 #define RDC_MRC_D2R_MASK                         0x20u
31232 #define RDC_MRC_D2R_SHIFT                        5
31233 #define RDC_MRC_D3W_MASK                         0x40u
31234 #define RDC_MRC_D3W_SHIFT                        6
31235 #define RDC_MRC_D3R_MASK                         0x80u
31236 #define RDC_MRC_D3R_SHIFT                        7
31237 #define RDC_MRC_ENA_MASK                         0x40000000u
31238 #define RDC_MRC_ENA_SHIFT                        30
31239 #define RDC_MRC_LCK_MASK                         0x80000000u
31240 #define RDC_MRC_LCK_SHIFT                        31
31241 /* MRVS Bit Fields */
31242 #define RDC_MRVS_VDID_MASK                       0x3u
31243 #define RDC_MRVS_VDID_SHIFT                      0
31244 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VDID_SHIFT))&RDC_MRVS_VDID_MASK)
31245 #define RDC_MRVS_AD_MASK                         0x10u
31246 #define RDC_MRVS_AD_SHIFT                        4
31247 #define RDC_MRVS_VADR_MASK                       0xFFFFFFE0u
31248 #define RDC_MRVS_VADR_SHIFT                      5
31249 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VADR_SHIFT))&RDC_MRVS_VADR_MASK)
31250 
31251 /*!
31252  * @}
31253  */ /* end of group RDC_Register_Masks */
31254 
31255 /* RDC - Peripheral instance base addresses */
31256 /** Peripheral RDC base address */
31257 #define RDC_BASE                                 (0x420FC000u)
31258 /** Peripheral RDC base pointer */
31259 #define RDC                                      ((RDC_Type *)RDC_BASE)
31260 #define RDC_BASE_PTR                             (RDC)
31261 /** Array initializer of RDC peripheral base addresses */
31262 #define RDC_BASE_ADDRS                           { RDC_BASE }
31263 /** Array initializer of RDC peripheral base pointers */
31264 #define RDC_BASE_PTRS                            { RDC }
31265 /** Interrupt vectors for the RDC peripheral type */
31266 #define RDC_IRQS                                 { RDC_IRQn }
31267 
31268 /* ----------------------------------------------------------------------------
31269    -- RDC - Register accessor macros
31270    ---------------------------------------------------------------------------- */
31271 
31272 /*!
31273  * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros
31274  * @{
31275  */
31276 
31277 /* RDC - Register instance definitions */
31278 /* RDC */
31279 #define RDC_VIR                                  RDC_VIR_REG(RDC_BASE_PTR)
31280 #define RDC_STAT                                 RDC_STAT_REG(RDC_BASE_PTR)
31281 #define RDC_INTCTRL                              RDC_INTCTRL_REG(RDC_BASE_PTR)
31282 #define RDC_INTSTAT                              RDC_INTSTAT_REG(RDC_BASE_PTR)
31283 #define RDC_MDA0                                 RDC_MDA_REG(RDC_BASE_PTR,0)
31284 #define RDC_MDA1                                 RDC_MDA_REG(RDC_BASE_PTR,1)
31285 #define RDC_MDA2                                 RDC_MDA_REG(RDC_BASE_PTR,2)
31286 #define RDC_MDA3                                 RDC_MDA_REG(RDC_BASE_PTR,3)
31287 #define RDC_MDA4                                 RDC_MDA_REG(RDC_BASE_PTR,4)
31288 #define RDC_MDA5                                 RDC_MDA_REG(RDC_BASE_PTR,5)
31289 #define RDC_MDA6                                 RDC_MDA_REG(RDC_BASE_PTR,6)
31290 #define RDC_MDA7                                 RDC_MDA_REG(RDC_BASE_PTR,7)
31291 #define RDC_MDA8                                 RDC_MDA_REG(RDC_BASE_PTR,8)
31292 #define RDC_MDA9                                 RDC_MDA_REG(RDC_BASE_PTR,9)
31293 #define RDC_MDA10                                RDC_MDA_REG(RDC_BASE_PTR,10)
31294 #define RDC_MDA11                                RDC_MDA_REG(RDC_BASE_PTR,11)
31295 #define RDC_MDA12                                RDC_MDA_REG(RDC_BASE_PTR,12)
31296 #define RDC_MDA13                                RDC_MDA_REG(RDC_BASE_PTR,13)
31297 #define RDC_MDA14                                RDC_MDA_REG(RDC_BASE_PTR,14)
31298 #define RDC_MDA15                                RDC_MDA_REG(RDC_BASE_PTR,15)
31299 #define RDC_MDA16                                RDC_MDA_REG(RDC_BASE_PTR,16)
31300 #define RDC_MDA17                                RDC_MDA_REG(RDC_BASE_PTR,17)
31301 #define RDC_MDA18                                RDC_MDA_REG(RDC_BASE_PTR,18)
31302 #define RDC_MDA19                                RDC_MDA_REG(RDC_BASE_PTR,19)
31303 #define RDC_MDA20                                RDC_MDA_REG(RDC_BASE_PTR,20)
31304 #define RDC_MDA21                                RDC_MDA_REG(RDC_BASE_PTR,21)
31305 #define RDC_MDA22                                RDC_MDA_REG(RDC_BASE_PTR,22)
31306 #define RDC_MDA23                                RDC_MDA_REG(RDC_BASE_PTR,23)
31307 #define RDC_MDA24                                RDC_MDA_REG(RDC_BASE_PTR,24)
31308 #define RDC_MDA25                                RDC_MDA_REG(RDC_BASE_PTR,25)
31309 #define RDC_MDA26                                RDC_MDA_REG(RDC_BASE_PTR,26)
31310 #define RDC_MDA27                                RDC_MDA_REG(RDC_BASE_PTR,27)
31311 #define RDC_MDA28                                RDC_MDA_REG(RDC_BASE_PTR,28)
31312 #define RDC_MDA29                                RDC_MDA_REG(RDC_BASE_PTR,29)
31313 #define RDC_MDA30                                RDC_MDA_REG(RDC_BASE_PTR,30)
31314 #define RDC_MDA31                                RDC_MDA_REG(RDC_BASE_PTR,31)
31315 #define RDC_PDAP0                                RDC_PDAP_REG(RDC_BASE_PTR,0)
31316 #define RDC_PDAP1                                RDC_PDAP_REG(RDC_BASE_PTR,1)
31317 #define RDC_PDAP2                                RDC_PDAP_REG(RDC_BASE_PTR,2)
31318 #define RDC_PDAP3                                RDC_PDAP_REG(RDC_BASE_PTR,3)
31319 #define RDC_PDAP4                                RDC_PDAP_REG(RDC_BASE_PTR,4)
31320 #define RDC_PDAP5                                RDC_PDAP_REG(RDC_BASE_PTR,5)
31321 #define RDC_PDAP6                                RDC_PDAP_REG(RDC_BASE_PTR,6)
31322 #define RDC_PDAP7                                RDC_PDAP_REG(RDC_BASE_PTR,7)
31323 #define RDC_PDAP8                                RDC_PDAP_REG(RDC_BASE_PTR,8)
31324 #define RDC_PDAP9                                RDC_PDAP_REG(RDC_BASE_PTR,9)
31325 #define RDC_PDAP10                               RDC_PDAP_REG(RDC_BASE_PTR,10)
31326 #define RDC_PDAP11                               RDC_PDAP_REG(RDC_BASE_PTR,11)
31327 #define RDC_PDAP12                               RDC_PDAP_REG(RDC_BASE_PTR,12)
31328 #define RDC_PDAP13                               RDC_PDAP_REG(RDC_BASE_PTR,13)
31329 #define RDC_PDAP14                               RDC_PDAP_REG(RDC_BASE_PTR,14)
31330 #define RDC_PDAP15                               RDC_PDAP_REG(RDC_BASE_PTR,15)
31331 #define RDC_PDAP16                               RDC_PDAP_REG(RDC_BASE_PTR,16)
31332 #define RDC_PDAP17                               RDC_PDAP_REG(RDC_BASE_PTR,17)
31333 #define RDC_PDAP18                               RDC_PDAP_REG(RDC_BASE_PTR,18)
31334 #define RDC_PDAP19                               RDC_PDAP_REG(RDC_BASE_PTR,19)
31335 #define RDC_PDAP20                               RDC_PDAP_REG(RDC_BASE_PTR,20)
31336 #define RDC_PDAP21                               RDC_PDAP_REG(RDC_BASE_PTR,21)
31337 #define RDC_PDAP22                               RDC_PDAP_REG(RDC_BASE_PTR,22)
31338 #define RDC_PDAP23                               RDC_PDAP_REG(RDC_BASE_PTR,23)
31339 #define RDC_PDAP24                               RDC_PDAP_REG(RDC_BASE_PTR,24)
31340 #define RDC_PDAP25                               RDC_PDAP_REG(RDC_BASE_PTR,25)
31341 #define RDC_PDAP26                               RDC_PDAP_REG(RDC_BASE_PTR,26)
31342 #define RDC_PDAP27                               RDC_PDAP_REG(RDC_BASE_PTR,27)
31343 #define RDC_PDAP28                               RDC_PDAP_REG(RDC_BASE_PTR,28)
31344 #define RDC_PDAP29                               RDC_PDAP_REG(RDC_BASE_PTR,29)
31345 #define RDC_PDAP30                               RDC_PDAP_REG(RDC_BASE_PTR,30)
31346 #define RDC_PDAP31                               RDC_PDAP_REG(RDC_BASE_PTR,31)
31347 #define RDC_PDAP32                               RDC_PDAP_REG(RDC_BASE_PTR,32)
31348 #define RDC_PDAP33                               RDC_PDAP_REG(RDC_BASE_PTR,33)
31349 #define RDC_PDAP34                               RDC_PDAP_REG(RDC_BASE_PTR,34)
31350 #define RDC_PDAP35                               RDC_PDAP_REG(RDC_BASE_PTR,35)
31351 #define RDC_PDAP36                               RDC_PDAP_REG(RDC_BASE_PTR,36)
31352 #define RDC_PDAP37                               RDC_PDAP_REG(RDC_BASE_PTR,37)
31353 #define RDC_PDAP38                               RDC_PDAP_REG(RDC_BASE_PTR,38)
31354 #define RDC_PDAP39                               RDC_PDAP_REG(RDC_BASE_PTR,39)
31355 #define RDC_PDAP40                               RDC_PDAP_REG(RDC_BASE_PTR,40)
31356 #define RDC_PDAP41                               RDC_PDAP_REG(RDC_BASE_PTR,41)
31357 #define RDC_PDAP42                               RDC_PDAP_REG(RDC_BASE_PTR,42)
31358 #define RDC_PDAP43                               RDC_PDAP_REG(RDC_BASE_PTR,43)
31359 #define RDC_PDAP44                               RDC_PDAP_REG(RDC_BASE_PTR,44)
31360 #define RDC_PDAP45                               RDC_PDAP_REG(RDC_BASE_PTR,45)
31361 #define RDC_PDAP46                               RDC_PDAP_REG(RDC_BASE_PTR,46)
31362 #define RDC_PDAP47                               RDC_PDAP_REG(RDC_BASE_PTR,47)
31363 #define RDC_PDAP48                               RDC_PDAP_REG(RDC_BASE_PTR,48)
31364 #define RDC_PDAP49                               RDC_PDAP_REG(RDC_BASE_PTR,49)
31365 #define RDC_PDAP50                               RDC_PDAP_REG(RDC_BASE_PTR,50)
31366 #define RDC_PDAP51                               RDC_PDAP_REG(RDC_BASE_PTR,51)
31367 #define RDC_PDAP52                               RDC_PDAP_REG(RDC_BASE_PTR,52)
31368 #define RDC_PDAP53                               RDC_PDAP_REG(RDC_BASE_PTR,53)
31369 #define RDC_PDAP54                               RDC_PDAP_REG(RDC_BASE_PTR,54)
31370 #define RDC_PDAP55                               RDC_PDAP_REG(RDC_BASE_PTR,55)
31371 #define RDC_PDAP56                               RDC_PDAP_REG(RDC_BASE_PTR,56)
31372 #define RDC_PDAP57                               RDC_PDAP_REG(RDC_BASE_PTR,57)
31373 #define RDC_PDAP58                               RDC_PDAP_REG(RDC_BASE_PTR,58)
31374 #define RDC_PDAP59                               RDC_PDAP_REG(RDC_BASE_PTR,59)
31375 #define RDC_PDAP60                               RDC_PDAP_REG(RDC_BASE_PTR,60)
31376 #define RDC_PDAP61                               RDC_PDAP_REG(RDC_BASE_PTR,61)
31377 #define RDC_PDAP62                               RDC_PDAP_REG(RDC_BASE_PTR,62)
31378 #define RDC_PDAP63                               RDC_PDAP_REG(RDC_BASE_PTR,63)
31379 #define RDC_PDAP64                               RDC_PDAP_REG(RDC_BASE_PTR,64)
31380 #define RDC_PDAP65                               RDC_PDAP_REG(RDC_BASE_PTR,65)
31381 #define RDC_PDAP66                               RDC_PDAP_REG(RDC_BASE_PTR,66)
31382 #define RDC_PDAP67                               RDC_PDAP_REG(RDC_BASE_PTR,67)
31383 #define RDC_PDAP68                               RDC_PDAP_REG(RDC_BASE_PTR,68)
31384 #define RDC_PDAP69                               RDC_PDAP_REG(RDC_BASE_PTR,69)
31385 #define RDC_PDAP70                               RDC_PDAP_REG(RDC_BASE_PTR,70)
31386 #define RDC_PDAP71                               RDC_PDAP_REG(RDC_BASE_PTR,71)
31387 #define RDC_PDAP72                               RDC_PDAP_REG(RDC_BASE_PTR,72)
31388 #define RDC_PDAP73                               RDC_PDAP_REG(RDC_BASE_PTR,73)
31389 #define RDC_PDAP74                               RDC_PDAP_REG(RDC_BASE_PTR,74)
31390 #define RDC_PDAP75                               RDC_PDAP_REG(RDC_BASE_PTR,75)
31391 #define RDC_PDAP76                               RDC_PDAP_REG(RDC_BASE_PTR,76)
31392 #define RDC_PDAP77                               RDC_PDAP_REG(RDC_BASE_PTR,77)
31393 #define RDC_PDAP78                               RDC_PDAP_REG(RDC_BASE_PTR,78)
31394 #define RDC_PDAP79                               RDC_PDAP_REG(RDC_BASE_PTR,79)
31395 #define RDC_PDAP80                               RDC_PDAP_REG(RDC_BASE_PTR,80)
31396 #define RDC_PDAP81                               RDC_PDAP_REG(RDC_BASE_PTR,81)
31397 #define RDC_PDAP82                               RDC_PDAP_REG(RDC_BASE_PTR,82)
31398 #define RDC_PDAP83                               RDC_PDAP_REG(RDC_BASE_PTR,83)
31399 #define RDC_PDAP84                               RDC_PDAP_REG(RDC_BASE_PTR,84)
31400 #define RDC_PDAP85                               RDC_PDAP_REG(RDC_BASE_PTR,85)
31401 #define RDC_PDAP86                               RDC_PDAP_REG(RDC_BASE_PTR,86)
31402 #define RDC_PDAP87                               RDC_PDAP_REG(RDC_BASE_PTR,87)
31403 #define RDC_PDAP88                               RDC_PDAP_REG(RDC_BASE_PTR,88)
31404 #define RDC_PDAP89                               RDC_PDAP_REG(RDC_BASE_PTR,89)
31405 #define RDC_PDAP90                               RDC_PDAP_REG(RDC_BASE_PTR,90)
31406 #define RDC_PDAP91                               RDC_PDAP_REG(RDC_BASE_PTR,91)
31407 #define RDC_PDAP92                               RDC_PDAP_REG(RDC_BASE_PTR,92)
31408 #define RDC_PDAP93                               RDC_PDAP_REG(RDC_BASE_PTR,93)
31409 #define RDC_PDAP94                               RDC_PDAP_REG(RDC_BASE_PTR,94)
31410 #define RDC_PDAP95                               RDC_PDAP_REG(RDC_BASE_PTR,95)
31411 #define RDC_PDAP96                               RDC_PDAP_REG(RDC_BASE_PTR,96)
31412 #define RDC_PDAP97                               RDC_PDAP_REG(RDC_BASE_PTR,97)
31413 #define RDC_PDAP98                               RDC_PDAP_REG(RDC_BASE_PTR,98)
31414 #define RDC_PDAP99                               RDC_PDAP_REG(RDC_BASE_PTR,99)
31415 #define RDC_PDAP100                              RDC_PDAP_REG(RDC_BASE_PTR,100)
31416 #define RDC_PDAP101                              RDC_PDAP_REG(RDC_BASE_PTR,101)
31417 #define RDC_PDAP102                              RDC_PDAP_REG(RDC_BASE_PTR,102)
31418 #define RDC_PDAP103                              RDC_PDAP_REG(RDC_BASE_PTR,103)
31419 #define RDC_PDAP104                              RDC_PDAP_REG(RDC_BASE_PTR,104)
31420 #define RDC_PDAP105                              RDC_PDAP_REG(RDC_BASE_PTR,105)
31421 #define RDC_PDAP106                              RDC_PDAP_REG(RDC_BASE_PTR,106)
31422 #define RDC_PDAP107                              RDC_PDAP_REG(RDC_BASE_PTR,107)
31423 #define RDC_PDAP108                              RDC_PDAP_REG(RDC_BASE_PTR,108)
31424 #define RDC_PDAP109                              RDC_PDAP_REG(RDC_BASE_PTR,109)
31425 #define RDC_MRSA0                                RDC_MRSA_REG(RDC_BASE_PTR,0)
31426 #define RDC_MREA0                                RDC_MREA_REG(RDC_BASE_PTR,0)
31427 #define RDC_MRC0                                 RDC_MRC_REG(RDC_BASE_PTR,0)
31428 #define RDC_MRVS0                                RDC_MRVS_REG(RDC_BASE_PTR,0)
31429 #define RDC_MRSA1                                RDC_MRSA_REG(RDC_BASE_PTR,1)
31430 #define RDC_MREA1                                RDC_MREA_REG(RDC_BASE_PTR,1)
31431 #define RDC_MRC1                                 RDC_MRC_REG(RDC_BASE_PTR,1)
31432 #define RDC_MRVS1                                RDC_MRVS_REG(RDC_BASE_PTR,1)
31433 #define RDC_MRSA2                                RDC_MRSA_REG(RDC_BASE_PTR,2)
31434 #define RDC_MREA2                                RDC_MREA_REG(RDC_BASE_PTR,2)
31435 #define RDC_MRC2                                 RDC_MRC_REG(RDC_BASE_PTR,2)
31436 #define RDC_MRVS2                                RDC_MRVS_REG(RDC_BASE_PTR,2)
31437 #define RDC_MRSA3                                RDC_MRSA_REG(RDC_BASE_PTR,3)
31438 #define RDC_MREA3                                RDC_MREA_REG(RDC_BASE_PTR,3)
31439 #define RDC_MRC3                                 RDC_MRC_REG(RDC_BASE_PTR,3)
31440 #define RDC_MRVS3                                RDC_MRVS_REG(RDC_BASE_PTR,3)
31441 #define RDC_MRSA4                                RDC_MRSA_REG(RDC_BASE_PTR,4)
31442 #define RDC_MREA4                                RDC_MREA_REG(RDC_BASE_PTR,4)
31443 #define RDC_MRC4                                 RDC_MRC_REG(RDC_BASE_PTR,4)
31444 #define RDC_MRVS4                                RDC_MRVS_REG(RDC_BASE_PTR,4)
31445 #define RDC_MRSA5                                RDC_MRSA_REG(RDC_BASE_PTR,5)
31446 #define RDC_MREA5                                RDC_MREA_REG(RDC_BASE_PTR,5)
31447 #define RDC_MRC5                                 RDC_MRC_REG(RDC_BASE_PTR,5)
31448 #define RDC_MRVS5                                RDC_MRVS_REG(RDC_BASE_PTR,5)
31449 #define RDC_MRSA6                                RDC_MRSA_REG(RDC_BASE_PTR,6)
31450 #define RDC_MREA6                                RDC_MREA_REG(RDC_BASE_PTR,6)
31451 #define RDC_MRC6                                 RDC_MRC_REG(RDC_BASE_PTR,6)
31452 #define RDC_MRVS6                                RDC_MRVS_REG(RDC_BASE_PTR,6)
31453 #define RDC_MRSA7                                RDC_MRSA_REG(RDC_BASE_PTR,7)
31454 #define RDC_MREA7                                RDC_MREA_REG(RDC_BASE_PTR,7)
31455 #define RDC_MRC7                                 RDC_MRC_REG(RDC_BASE_PTR,7)
31456 #define RDC_MRVS7                                RDC_MRVS_REG(RDC_BASE_PTR,7)
31457 #define RDC_MRSA8                                RDC_MRSA_REG(RDC_BASE_PTR,8)
31458 #define RDC_MREA8                                RDC_MREA_REG(RDC_BASE_PTR,8)
31459 #define RDC_MRC8                                 RDC_MRC_REG(RDC_BASE_PTR,8)
31460 #define RDC_MRVS8                                RDC_MRVS_REG(RDC_BASE_PTR,8)
31461 #define RDC_MRSA9                                RDC_MRSA_REG(RDC_BASE_PTR,9)
31462 #define RDC_MREA9                                RDC_MREA_REG(RDC_BASE_PTR,9)
31463 #define RDC_MRC9                                 RDC_MRC_REG(RDC_BASE_PTR,9)
31464 #define RDC_MRVS9                                RDC_MRVS_REG(RDC_BASE_PTR,9)
31465 #define RDC_MRSA10                               RDC_MRSA_REG(RDC_BASE_PTR,10)
31466 #define RDC_MREA10                               RDC_MREA_REG(RDC_BASE_PTR,10)
31467 #define RDC_MRC10                                RDC_MRC_REG(RDC_BASE_PTR,10)
31468 #define RDC_MRVS10                               RDC_MRVS_REG(RDC_BASE_PTR,10)
31469 #define RDC_MRSA11                               RDC_MRSA_REG(RDC_BASE_PTR,11)
31470 #define RDC_MREA11                               RDC_MREA_REG(RDC_BASE_PTR,11)
31471 #define RDC_MRC11                                RDC_MRC_REG(RDC_BASE_PTR,11)
31472 #define RDC_MRVS11                               RDC_MRVS_REG(RDC_BASE_PTR,11)
31473 #define RDC_MRSA12                               RDC_MRSA_REG(RDC_BASE_PTR,12)
31474 #define RDC_MREA12                               RDC_MREA_REG(RDC_BASE_PTR,12)
31475 #define RDC_MRC12                                RDC_MRC_REG(RDC_BASE_PTR,12)
31476 #define RDC_MRVS12                               RDC_MRVS_REG(RDC_BASE_PTR,12)
31477 #define RDC_MRSA13                               RDC_MRSA_REG(RDC_BASE_PTR,13)
31478 #define RDC_MREA13                               RDC_MREA_REG(RDC_BASE_PTR,13)
31479 #define RDC_MRC13                                RDC_MRC_REG(RDC_BASE_PTR,13)
31480 #define RDC_MRVS13                               RDC_MRVS_REG(RDC_BASE_PTR,13)
31481 #define RDC_MRSA14                               RDC_MRSA_REG(RDC_BASE_PTR,14)
31482 #define RDC_MREA14                               RDC_MREA_REG(RDC_BASE_PTR,14)
31483 #define RDC_MRC14                                RDC_MRC_REG(RDC_BASE_PTR,14)
31484 #define RDC_MRVS14                               RDC_MRVS_REG(RDC_BASE_PTR,14)
31485 #define RDC_MRSA15                               RDC_MRSA_REG(RDC_BASE_PTR,15)
31486 #define RDC_MREA15                               RDC_MREA_REG(RDC_BASE_PTR,15)
31487 #define RDC_MRC15                                RDC_MRC_REG(RDC_BASE_PTR,15)
31488 #define RDC_MRVS15                               RDC_MRVS_REG(RDC_BASE_PTR,15)
31489 #define RDC_MRSA16                               RDC_MRSA_REG(RDC_BASE_PTR,16)
31490 #define RDC_MREA16                               RDC_MREA_REG(RDC_BASE_PTR,16)
31491 #define RDC_MRC16                                RDC_MRC_REG(RDC_BASE_PTR,16)
31492 #define RDC_MRVS16                               RDC_MRVS_REG(RDC_BASE_PTR,16)
31493 #define RDC_MRSA17                               RDC_MRSA_REG(RDC_BASE_PTR,17)
31494 #define RDC_MREA17                               RDC_MREA_REG(RDC_BASE_PTR,17)
31495 #define RDC_MRC17                                RDC_MRC_REG(RDC_BASE_PTR,17)
31496 #define RDC_MRVS17                               RDC_MRVS_REG(RDC_BASE_PTR,17)
31497 #define RDC_MRSA18                               RDC_MRSA_REG(RDC_BASE_PTR,18)
31498 #define RDC_MREA18                               RDC_MREA_REG(RDC_BASE_PTR,18)
31499 #define RDC_MRC18                                RDC_MRC_REG(RDC_BASE_PTR,18)
31500 #define RDC_MRVS18                               RDC_MRVS_REG(RDC_BASE_PTR,18)
31501 #define RDC_MRSA19                               RDC_MRSA_REG(RDC_BASE_PTR,19)
31502 #define RDC_MREA19                               RDC_MREA_REG(RDC_BASE_PTR,19)
31503 #define RDC_MRC19                                RDC_MRC_REG(RDC_BASE_PTR,19)
31504 #define RDC_MRVS19                               RDC_MRVS_REG(RDC_BASE_PTR,19)
31505 #define RDC_MRSA20                               RDC_MRSA_REG(RDC_BASE_PTR,20)
31506 #define RDC_MREA20                               RDC_MREA_REG(RDC_BASE_PTR,20)
31507 #define RDC_MRC20                                RDC_MRC_REG(RDC_BASE_PTR,20)
31508 #define RDC_MRVS20                               RDC_MRVS_REG(RDC_BASE_PTR,20)
31509 #define RDC_MRSA21                               RDC_MRSA_REG(RDC_BASE_PTR,21)
31510 #define RDC_MREA21                               RDC_MREA_REG(RDC_BASE_PTR,21)
31511 #define RDC_MRC21                                RDC_MRC_REG(RDC_BASE_PTR,21)
31512 #define RDC_MRVS21                               RDC_MRVS_REG(RDC_BASE_PTR,21)
31513 #define RDC_MRSA22                               RDC_MRSA_REG(RDC_BASE_PTR,22)
31514 #define RDC_MREA22                               RDC_MREA_REG(RDC_BASE_PTR,22)
31515 #define RDC_MRC22                                RDC_MRC_REG(RDC_BASE_PTR,22)
31516 #define RDC_MRVS22                               RDC_MRVS_REG(RDC_BASE_PTR,22)
31517 #define RDC_MRSA23                               RDC_MRSA_REG(RDC_BASE_PTR,23)
31518 #define RDC_MREA23                               RDC_MREA_REG(RDC_BASE_PTR,23)
31519 #define RDC_MRC23                                RDC_MRC_REG(RDC_BASE_PTR,23)
31520 #define RDC_MRVS23                               RDC_MRVS_REG(RDC_BASE_PTR,23)
31521 #define RDC_MRSA24                               RDC_MRSA_REG(RDC_BASE_PTR,24)
31522 #define RDC_MREA24                               RDC_MREA_REG(RDC_BASE_PTR,24)
31523 #define RDC_MRC24                                RDC_MRC_REG(RDC_BASE_PTR,24)
31524 #define RDC_MRVS24                               RDC_MRVS_REG(RDC_BASE_PTR,24)
31525 #define RDC_MRSA25                               RDC_MRSA_REG(RDC_BASE_PTR,25)
31526 #define RDC_MREA25                               RDC_MREA_REG(RDC_BASE_PTR,25)
31527 #define RDC_MRC25                                RDC_MRC_REG(RDC_BASE_PTR,25)
31528 #define RDC_MRVS25                               RDC_MRVS_REG(RDC_BASE_PTR,25)
31529 #define RDC_MRSA26                               RDC_MRSA_REG(RDC_BASE_PTR,26)
31530 #define RDC_MREA26                               RDC_MREA_REG(RDC_BASE_PTR,26)
31531 #define RDC_MRC26                                RDC_MRC_REG(RDC_BASE_PTR,26)
31532 #define RDC_MRVS26                               RDC_MRVS_REG(RDC_BASE_PTR,26)
31533 #define RDC_MRSA27                               RDC_MRSA_REG(RDC_BASE_PTR,27)
31534 #define RDC_MREA27                               RDC_MREA_REG(RDC_BASE_PTR,27)
31535 #define RDC_MRC27                                RDC_MRC_REG(RDC_BASE_PTR,27)
31536 #define RDC_MRVS27                               RDC_MRVS_REG(RDC_BASE_PTR,27)
31537 #define RDC_MRSA28                               RDC_MRSA_REG(RDC_BASE_PTR,28)
31538 #define RDC_MREA28                               RDC_MREA_REG(RDC_BASE_PTR,28)
31539 #define RDC_MRC28                                RDC_MRC_REG(RDC_BASE_PTR,28)
31540 #define RDC_MRVS28                               RDC_MRVS_REG(RDC_BASE_PTR,28)
31541 #define RDC_MRSA29                               RDC_MRSA_REG(RDC_BASE_PTR,29)
31542 #define RDC_MREA29                               RDC_MREA_REG(RDC_BASE_PTR,29)
31543 #define RDC_MRC29                                RDC_MRC_REG(RDC_BASE_PTR,29)
31544 #define RDC_MRVS29                               RDC_MRVS_REG(RDC_BASE_PTR,29)
31545 #define RDC_MRSA30                               RDC_MRSA_REG(RDC_BASE_PTR,30)
31546 #define RDC_MREA30                               RDC_MREA_REG(RDC_BASE_PTR,30)
31547 #define RDC_MRC30                                RDC_MRC_REG(RDC_BASE_PTR,30)
31548 #define RDC_MRVS30                               RDC_MRVS_REG(RDC_BASE_PTR,30)
31549 #define RDC_MRSA31                               RDC_MRSA_REG(RDC_BASE_PTR,31)
31550 #define RDC_MREA31                               RDC_MREA_REG(RDC_BASE_PTR,31)
31551 #define RDC_MRC31                                RDC_MRC_REG(RDC_BASE_PTR,31)
31552 #define RDC_MRVS31                               RDC_MRVS_REG(RDC_BASE_PTR,31)
31553 #define RDC_MRSA32                               RDC_MRSA_REG(RDC_BASE_PTR,32)
31554 #define RDC_MREA32                               RDC_MREA_REG(RDC_BASE_PTR,32)
31555 #define RDC_MRC32                                RDC_MRC_REG(RDC_BASE_PTR,32)
31556 #define RDC_MRVS32                               RDC_MRVS_REG(RDC_BASE_PTR,32)
31557 #define RDC_MRSA33                               RDC_MRSA_REG(RDC_BASE_PTR,33)
31558 #define RDC_MREA33                               RDC_MREA_REG(RDC_BASE_PTR,33)
31559 #define RDC_MRC33                                RDC_MRC_REG(RDC_BASE_PTR,33)
31560 #define RDC_MRVS33                               RDC_MRVS_REG(RDC_BASE_PTR,33)
31561 #define RDC_MRSA34                               RDC_MRSA_REG(RDC_BASE_PTR,34)
31562 #define RDC_MREA34                               RDC_MREA_REG(RDC_BASE_PTR,34)
31563 #define RDC_MRC34                                RDC_MRC_REG(RDC_BASE_PTR,34)
31564 #define RDC_MRVS34                               RDC_MRVS_REG(RDC_BASE_PTR,34)
31565 #define RDC_MRSA35                               RDC_MRSA_REG(RDC_BASE_PTR,35)
31566 #define RDC_MREA35                               RDC_MREA_REG(RDC_BASE_PTR,35)
31567 #define RDC_MRC35                                RDC_MRC_REG(RDC_BASE_PTR,35)
31568 #define RDC_MRVS35                               RDC_MRVS_REG(RDC_BASE_PTR,35)
31569 #define RDC_MRSA36                               RDC_MRSA_REG(RDC_BASE_PTR,36)
31570 #define RDC_MREA36                               RDC_MREA_REG(RDC_BASE_PTR,36)
31571 #define RDC_MRC36                                RDC_MRC_REG(RDC_BASE_PTR,36)
31572 #define RDC_MRVS36                               RDC_MRVS_REG(RDC_BASE_PTR,36)
31573 #define RDC_MRSA37                               RDC_MRSA_REG(RDC_BASE_PTR,37)
31574 #define RDC_MREA37                               RDC_MREA_REG(RDC_BASE_PTR,37)
31575 #define RDC_MRC37                                RDC_MRC_REG(RDC_BASE_PTR,37)
31576 #define RDC_MRVS37                               RDC_MRVS_REG(RDC_BASE_PTR,37)
31577 #define RDC_MRSA38                               RDC_MRSA_REG(RDC_BASE_PTR,38)
31578 #define RDC_MREA38                               RDC_MREA_REG(RDC_BASE_PTR,38)
31579 #define RDC_MRC38                                RDC_MRC_REG(RDC_BASE_PTR,38)
31580 #define RDC_MRVS38                               RDC_MRVS_REG(RDC_BASE_PTR,38)
31581 #define RDC_MRSA39                               RDC_MRSA_REG(RDC_BASE_PTR,39)
31582 #define RDC_MREA39                               RDC_MREA_REG(RDC_BASE_PTR,39)
31583 #define RDC_MRC39                                RDC_MRC_REG(RDC_BASE_PTR,39)
31584 #define RDC_MRVS39                               RDC_MRVS_REG(RDC_BASE_PTR,39)
31585 #define RDC_MRSA40                               RDC_MRSA_REG(RDC_BASE_PTR,40)
31586 #define RDC_MREA40                               RDC_MREA_REG(RDC_BASE_PTR,40)
31587 #define RDC_MRC40                                RDC_MRC_REG(RDC_BASE_PTR,40)
31588 #define RDC_MRVS40                               RDC_MRVS_REG(RDC_BASE_PTR,40)
31589 #define RDC_MRSA41                               RDC_MRSA_REG(RDC_BASE_PTR,41)
31590 #define RDC_MREA41                               RDC_MREA_REG(RDC_BASE_PTR,41)
31591 #define RDC_MRC41                                RDC_MRC_REG(RDC_BASE_PTR,41)
31592 #define RDC_MRVS41                               RDC_MRVS_REG(RDC_BASE_PTR,41)
31593 #define RDC_MRSA42                               RDC_MRSA_REG(RDC_BASE_PTR,42)
31594 #define RDC_MREA42                               RDC_MREA_REG(RDC_BASE_PTR,42)
31595 #define RDC_MRC42                                RDC_MRC_REG(RDC_BASE_PTR,42)
31596 #define RDC_MRVS42                               RDC_MRVS_REG(RDC_BASE_PTR,42)
31597 #define RDC_MRSA43                               RDC_MRSA_REG(RDC_BASE_PTR,43)
31598 #define RDC_MREA43                               RDC_MREA_REG(RDC_BASE_PTR,43)
31599 #define RDC_MRC43                                RDC_MRC_REG(RDC_BASE_PTR,43)
31600 #define RDC_MRVS43                               RDC_MRVS_REG(RDC_BASE_PTR,43)
31601 #define RDC_MRSA44                               RDC_MRSA_REG(RDC_BASE_PTR,44)
31602 #define RDC_MREA44                               RDC_MREA_REG(RDC_BASE_PTR,44)
31603 #define RDC_MRC44                                RDC_MRC_REG(RDC_BASE_PTR,44)
31604 #define RDC_MRVS44                               RDC_MRVS_REG(RDC_BASE_PTR,44)
31605 #define RDC_MRSA45                               RDC_MRSA_REG(RDC_BASE_PTR,45)
31606 #define RDC_MREA45                               RDC_MREA_REG(RDC_BASE_PTR,45)
31607 #define RDC_MRC45                                RDC_MRC_REG(RDC_BASE_PTR,45)
31608 #define RDC_MRVS45                               RDC_MRVS_REG(RDC_BASE_PTR,45)
31609 #define RDC_MRSA46                               RDC_MRSA_REG(RDC_BASE_PTR,46)
31610 #define RDC_MREA46                               RDC_MREA_REG(RDC_BASE_PTR,46)
31611 #define RDC_MRC46                                RDC_MRC_REG(RDC_BASE_PTR,46)
31612 #define RDC_MRVS46                               RDC_MRVS_REG(RDC_BASE_PTR,46)
31613 #define RDC_MRSA47                               RDC_MRSA_REG(RDC_BASE_PTR,47)
31614 #define RDC_MREA47                               RDC_MREA_REG(RDC_BASE_PTR,47)
31615 #define RDC_MRC47                                RDC_MRC_REG(RDC_BASE_PTR,47)
31616 #define RDC_MRVS47                               RDC_MRVS_REG(RDC_BASE_PTR,47)
31617 #define RDC_MRSA48                               RDC_MRSA_REG(RDC_BASE_PTR,48)
31618 #define RDC_MREA48                               RDC_MREA_REG(RDC_BASE_PTR,48)
31619 #define RDC_MRC48                                RDC_MRC_REG(RDC_BASE_PTR,48)
31620 #define RDC_MRVS48                               RDC_MRVS_REG(RDC_BASE_PTR,48)
31621 #define RDC_MRSA49                               RDC_MRSA_REG(RDC_BASE_PTR,49)
31622 #define RDC_MREA49                               RDC_MREA_REG(RDC_BASE_PTR,49)
31623 #define RDC_MRC49                                RDC_MRC_REG(RDC_BASE_PTR,49)
31624 #define RDC_MRVS49                               RDC_MRVS_REG(RDC_BASE_PTR,49)
31625 #define RDC_MRSA50                               RDC_MRSA_REG(RDC_BASE_PTR,50)
31626 #define RDC_MREA50                               RDC_MREA_REG(RDC_BASE_PTR,50)
31627 #define RDC_MRC50                                RDC_MRC_REG(RDC_BASE_PTR,50)
31628 #define RDC_MRVS50                               RDC_MRVS_REG(RDC_BASE_PTR,50)
31629 #define RDC_MRSA51                               RDC_MRSA_REG(RDC_BASE_PTR,51)
31630 #define RDC_MREA51                               RDC_MREA_REG(RDC_BASE_PTR,51)
31631 #define RDC_MRC51                                RDC_MRC_REG(RDC_BASE_PTR,51)
31632 #define RDC_MRVS51                               RDC_MRVS_REG(RDC_BASE_PTR,51)
31633 #define RDC_MRSA52                               RDC_MRSA_REG(RDC_BASE_PTR,52)
31634 #define RDC_MREA52                               RDC_MREA_REG(RDC_BASE_PTR,52)
31635 #define RDC_MRC52                                RDC_MRC_REG(RDC_BASE_PTR,52)
31636 #define RDC_MRVS52                               RDC_MRVS_REG(RDC_BASE_PTR,52)
31637 #define RDC_MRSA53                               RDC_MRSA_REG(RDC_BASE_PTR,53)
31638 #define RDC_MREA53                               RDC_MREA_REG(RDC_BASE_PTR,53)
31639 #define RDC_MRC53                                RDC_MRC_REG(RDC_BASE_PTR,53)
31640 #define RDC_MRVS53                               RDC_MRVS_REG(RDC_BASE_PTR,53)
31641 #define RDC_MRSA54                               RDC_MRSA_REG(RDC_BASE_PTR,54)
31642 #define RDC_MREA54                               RDC_MREA_REG(RDC_BASE_PTR,54)
31643 #define RDC_MRC54                                RDC_MRC_REG(RDC_BASE_PTR,54)
31644 #define RDC_MRVS54                               RDC_MRVS_REG(RDC_BASE_PTR,54)
31645 /* RDC - Register array accessors */
31646 #define RDC_MDA(index)                           RDC_MDA_REG(RDC_BASE_PTR,index)
31647 #define RDC_PDAP(index)                          RDC_PDAP_REG(RDC_BASE_PTR,index)
31648 #define RDC_MRSA(index)                          RDC_MRSA_REG(RDC_BASE_PTR,index)
31649 #define RDC_MREA(index)                          RDC_MREA_REG(RDC_BASE_PTR,index)
31650 #define RDC_MRC(index)                           RDC_MRC_REG(RDC_BASE_PTR,index)
31651 #define RDC_MRVS(index)                          RDC_MRVS_REG(RDC_BASE_PTR,index)
31652 
31653 /*!
31654  * @}
31655  */ /* end of group RDC_Register_Accessor_Macros */
31656 
31657 /*!
31658  * @}
31659  */ /* end of group RDC_Peripheral */
31660 
31661 /* ----------------------------------------------------------------------------
31662    -- RDC_SEMAPHORE Peripheral Access Layer
31663    ---------------------------------------------------------------------------- */
31664 
31665 /*!
31666  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
31667  * @{
31668  */
31669 
31670 /** RDC_SEMAPHORE - Register Layout Typedef */
31671 typedef struct {
31672   __IO  uint8_t  GATE[64];                                      /**< Gate Register, array offset: 0x0, array step: 0x1 */
31673   union {                                                       /* offset: 0x40 */
31674   __IO    uint16_t RSTGT_W;                                     /**< Reset Gate Write,offset: 0x40 */
31675   __IO    uint16_t RSTGT_R;                                     /**< Reset Gate Read,offset: 0x40 */
31676   };
31677 } RDC_SEMAPHORE_Type, *RDC_SEMAPHORE_MemMapPtr;
31678 
31679 /* ----------------------------------------------------------------------------
31680    -- RDC_SEMAPHORE - Register accessor macros
31681    ---------------------------------------------------------------------------- */
31682 
31683 /*!
31684  * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros
31685  * @{
31686  */
31687 
31688 /* RDC_SEMAPHORE - Register accessors */
31689 #define RDC_SEMAPHORE_GATE_REG(base,index)       ((base)->GATE[index])
31690 #define RDC_SEMAPHORE_RSTGT_W_REG(base)          ((base)->RSTGT_W)
31691 #define RDC_SEMAPHORE_RSTGT_R_REG(base)          ((base)->RSTGT_R)
31692 
31693 /*!
31694  * @}
31695  */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */
31696 
31697 /* ----------------------------------------------------------------------------
31698    -- RDC_SEMAPHORE Register Masks
31699    ---------------------------------------------------------------------------- */
31700 
31701 /*!
31702  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
31703  * @{
31704  */
31705 
31706 /* GATE Bit Fields */
31707 #define RDC_SEMAPHORE_GATE_GTFSM_MASK            0xFu
31708 #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT           0
31709 #define RDC_SEMAPHORE_GATE_GTFSM(x)              (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_GTFSM_SHIFT))&RDC_SEMAPHORE_GATE_GTFSM_MASK)
31710 #define RDC_SEMAPHORE_GATE_LDOM_MASK             0x60u
31711 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT            5
31712 #define RDC_SEMAPHORE_GATE_LDOM(x)               (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_LDOM_SHIFT))&RDC_SEMAPHORE_GATE_LDOM_MASK)
31713 /* RSTGT_W Bit Fields */
31714 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        0xFFu
31715 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       0
31716 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
31717 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        0xFF00u
31718 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       8
31719 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
31720 /* RSTGT_R Bit Fields */
31721 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        0xFu
31722 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       0
31723 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
31724 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        0x30u
31725 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       4
31726 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
31727 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        0xFF00u
31728 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       8
31729 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
31730 
31731 /*!
31732  * @}
31733  */ /* end of group RDC_SEMAPHORE_Register_Masks */
31734 
31735 /* RDC_SEMAPHORE - Peripheral instance base addresses */
31736 /** Peripheral RDC_SEMAPHORE1 base address */
31737 #define RDC_SEMAPHORE1_BASE                      (0x420F4000u)
31738 /** Peripheral RDC_SEMAPHORE1 base pointer */
31739 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
31740 #define RDC_SEMAPHORE1_BASE_PTR                  (RDC_SEMAPHORE1)
31741 /** Peripheral RDC_SEMAPHORE2 base address */
31742 #define RDC_SEMAPHORE2_BASE                      (0x420F8000u)
31743 /** Peripheral RDC_SEMAPHORE2 base pointer */
31744 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
31745 #define RDC_SEMAPHORE2_BASE_PTR                  (RDC_SEMAPHORE2)
31746 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
31747 #define RDC_SEMAPHORE_BASE_ADDRS                 { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
31748 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
31749 #define RDC_SEMAPHORE_BASE_PTRS                  { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
31750 
31751 /* ----------------------------------------------------------------------------
31752    -- RDC_SEMAPHORE - Register accessor macros
31753    ---------------------------------------------------------------------------- */
31754 
31755 /*!
31756  * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros
31757  * @{
31758  */
31759 
31760 /* RDC_SEMAPHORE - Register instance definitions */
31761 /* RDC_SEMAPHORE1 */
31762 #define RDC_SEMAPHORE1_GATE0                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,0)
31763 #define RDC_SEMAPHORE1_GATE1                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,1)
31764 #define RDC_SEMAPHORE1_GATE2                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,2)
31765 #define RDC_SEMAPHORE1_GATE3                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,3)
31766 #define RDC_SEMAPHORE1_GATE4                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,4)
31767 #define RDC_SEMAPHORE1_GATE5                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,5)
31768 #define RDC_SEMAPHORE1_GATE6                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,6)
31769 #define RDC_SEMAPHORE1_GATE7                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,7)
31770 #define RDC_SEMAPHORE1_GATE8                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,8)
31771 #define RDC_SEMAPHORE1_GATE9                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,9)
31772 #define RDC_SEMAPHORE1_GATE10                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,10)
31773 #define RDC_SEMAPHORE1_GATE11                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,11)
31774 #define RDC_SEMAPHORE1_GATE12                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,12)
31775 #define RDC_SEMAPHORE1_GATE13                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,13)
31776 #define RDC_SEMAPHORE1_GATE14                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,14)
31777 #define RDC_SEMAPHORE1_GATE15                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,15)
31778 #define RDC_SEMAPHORE1_GATE16                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,16)
31779 #define RDC_SEMAPHORE1_GATE17                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,17)
31780 #define RDC_SEMAPHORE1_GATE18                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,18)
31781 #define RDC_SEMAPHORE1_GATE19                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,19)
31782 #define RDC_SEMAPHORE1_GATE20                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,20)
31783 #define RDC_SEMAPHORE1_GATE21                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,21)
31784 #define RDC_SEMAPHORE1_GATE22                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,22)
31785 #define RDC_SEMAPHORE1_GATE23                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,23)
31786 #define RDC_SEMAPHORE1_GATE24                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,24)
31787 #define RDC_SEMAPHORE1_GATE25                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,25)
31788 #define RDC_SEMAPHORE1_GATE26                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,26)
31789 #define RDC_SEMAPHORE1_GATE27                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,27)
31790 #define RDC_SEMAPHORE1_GATE28                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,28)
31791 #define RDC_SEMAPHORE1_GATE29                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,29)
31792 #define RDC_SEMAPHORE1_GATE30                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,30)
31793 #define RDC_SEMAPHORE1_GATE31                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,31)
31794 #define RDC_SEMAPHORE1_GATE32                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,32)
31795 #define RDC_SEMAPHORE1_GATE33                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,33)
31796 #define RDC_SEMAPHORE1_GATE34                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,34)
31797 #define RDC_SEMAPHORE1_GATE35                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,35)
31798 #define RDC_SEMAPHORE1_GATE36                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,36)
31799 #define RDC_SEMAPHORE1_GATE37                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,37)
31800 #define RDC_SEMAPHORE1_GATE38                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,38)
31801 #define RDC_SEMAPHORE1_GATE39                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,39)
31802 #define RDC_SEMAPHORE1_GATE40                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,40)
31803 #define RDC_SEMAPHORE1_GATE41                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,41)
31804 #define RDC_SEMAPHORE1_GATE42                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,42)
31805 #define RDC_SEMAPHORE1_GATE43                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,43)
31806 #define RDC_SEMAPHORE1_GATE44                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,44)
31807 #define RDC_SEMAPHORE1_GATE45                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,45)
31808 #define RDC_SEMAPHORE1_GATE46                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,46)
31809 #define RDC_SEMAPHORE1_GATE47                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,47)
31810 #define RDC_SEMAPHORE1_GATE48                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,48)
31811 #define RDC_SEMAPHORE1_GATE49                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,49)
31812 #define RDC_SEMAPHORE1_GATE50                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,50)
31813 #define RDC_SEMAPHORE1_GATE51                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,51)
31814 #define RDC_SEMAPHORE1_GATE52                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,52)
31815 #define RDC_SEMAPHORE1_GATE53                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,53)
31816 #define RDC_SEMAPHORE1_GATE54                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,54)
31817 #define RDC_SEMAPHORE1_GATE55                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,55)
31818 #define RDC_SEMAPHORE1_GATE56                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,56)
31819 #define RDC_SEMAPHORE1_GATE57                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,57)
31820 #define RDC_SEMAPHORE1_GATE58                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,58)
31821 #define RDC_SEMAPHORE1_GATE59                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,59)
31822 #define RDC_SEMAPHORE1_GATE60                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,60)
31823 #define RDC_SEMAPHORE1_GATE61                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,61)
31824 #define RDC_SEMAPHORE1_GATE62                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,62)
31825 #define RDC_SEMAPHORE1_GATE63                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,63)
31826 #define RDC_SEMAPHORE1_RSTGT_W                   RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE1_BASE_PTR)
31827 #define RDC_SEMAPHORE1_RSTGT_R                   RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR)
31828 /* RDC_SEMAPHORE2 */
31829 #define RDC_SEMAPHORE2_GATE0                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,0)
31830 #define RDC_SEMAPHORE2_GATE1                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,1)
31831 #define RDC_SEMAPHORE2_GATE2                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,2)
31832 #define RDC_SEMAPHORE2_GATE3                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,3)
31833 #define RDC_SEMAPHORE2_GATE4                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,4)
31834 #define RDC_SEMAPHORE2_GATE5                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,5)
31835 #define RDC_SEMAPHORE2_GATE6                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,6)
31836 #define RDC_SEMAPHORE2_GATE7                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,7)
31837 #define RDC_SEMAPHORE2_GATE8                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,8)
31838 #define RDC_SEMAPHORE2_GATE9                     RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,9)
31839 #define RDC_SEMAPHORE2_GATE10                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,10)
31840 #define RDC_SEMAPHORE2_GATE11                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,11)
31841 #define RDC_SEMAPHORE2_GATE12                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,12)
31842 #define RDC_SEMAPHORE2_GATE13                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,13)
31843 #define RDC_SEMAPHORE2_GATE14                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,14)
31844 #define RDC_SEMAPHORE2_GATE15                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,15)
31845 #define RDC_SEMAPHORE2_GATE16                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,16)
31846 #define RDC_SEMAPHORE2_GATE17                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,17)
31847 #define RDC_SEMAPHORE2_GATE18                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,18)
31848 #define RDC_SEMAPHORE2_GATE19                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,19)
31849 #define RDC_SEMAPHORE2_GATE20                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,20)
31850 #define RDC_SEMAPHORE2_GATE21                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,21)
31851 #define RDC_SEMAPHORE2_GATE22                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,22)
31852 #define RDC_SEMAPHORE2_GATE23                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,23)
31853 #define RDC_SEMAPHORE2_GATE24                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,24)
31854 #define RDC_SEMAPHORE2_GATE25                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,25)
31855 #define RDC_SEMAPHORE2_GATE26                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,26)
31856 #define RDC_SEMAPHORE2_GATE27                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,27)
31857 #define RDC_SEMAPHORE2_GATE28                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,28)
31858 #define RDC_SEMAPHORE2_GATE29                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,29)
31859 #define RDC_SEMAPHORE2_GATE30                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,30)
31860 #define RDC_SEMAPHORE2_GATE31                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,31)
31861 #define RDC_SEMAPHORE2_GATE32                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,32)
31862 #define RDC_SEMAPHORE2_GATE33                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,33)
31863 #define RDC_SEMAPHORE2_GATE34                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,34)
31864 #define RDC_SEMAPHORE2_GATE35                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,35)
31865 #define RDC_SEMAPHORE2_GATE36                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,36)
31866 #define RDC_SEMAPHORE2_GATE37                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,37)
31867 #define RDC_SEMAPHORE2_GATE38                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,38)
31868 #define RDC_SEMAPHORE2_GATE39                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,39)
31869 #define RDC_SEMAPHORE2_GATE40                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,40)
31870 #define RDC_SEMAPHORE2_GATE41                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,41)
31871 #define RDC_SEMAPHORE2_GATE42                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,42)
31872 #define RDC_SEMAPHORE2_GATE43                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,43)
31873 #define RDC_SEMAPHORE2_GATE44                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,44)
31874 #define RDC_SEMAPHORE2_GATE45                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,45)
31875 #define RDC_SEMAPHORE2_GATE46                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,46)
31876 #define RDC_SEMAPHORE2_GATE47                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,47)
31877 #define RDC_SEMAPHORE2_GATE48                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,48)
31878 #define RDC_SEMAPHORE2_GATE49                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,49)
31879 #define RDC_SEMAPHORE2_GATE50                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,50)
31880 #define RDC_SEMAPHORE2_GATE51                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,51)
31881 #define RDC_SEMAPHORE2_GATE52                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,52)
31882 #define RDC_SEMAPHORE2_GATE53                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,53)
31883 #define RDC_SEMAPHORE2_GATE54                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,54)
31884 #define RDC_SEMAPHORE2_GATE55                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,55)
31885 #define RDC_SEMAPHORE2_GATE56                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,56)
31886 #define RDC_SEMAPHORE2_GATE57                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,57)
31887 #define RDC_SEMAPHORE2_GATE58                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,58)
31888 #define RDC_SEMAPHORE2_GATE59                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,59)
31889 #define RDC_SEMAPHORE2_GATE60                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,60)
31890 #define RDC_SEMAPHORE2_GATE61                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,61)
31891 #define RDC_SEMAPHORE2_GATE62                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,62)
31892 #define RDC_SEMAPHORE2_GATE63                    RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,63)
31893 #define RDC_SEMAPHORE2_RSTGT_W                   RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE2_BASE_PTR)
31894 #define RDC_SEMAPHORE2_RSTGT_R                   RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR)
31895 /* RDC_SEMAPHORE - Register array accessors */
31896 #define RDC_SEMAPHORE1_GATE(index)               RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,index)
31897 #define RDC_SEMAPHORE2_GATE(index)               RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,index)
31898 
31899 /*!
31900  * @}
31901  */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */
31902 
31903 /*!
31904  * @}
31905  */ /* end of group RDC_SEMAPHORE_Peripheral */
31906 
31907 /* ----------------------------------------------------------------------------
31908    -- ROMC Peripheral Access Layer
31909    ---------------------------------------------------------------------------- */
31910 
31911 /*!
31912  * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
31913  * @{
31914  */
31915 
31916 /** ROMC - Register Layout Typedef */
31917 typedef struct {
31918   uint8_t RESERVED_0[212];
31919   __IO  uint32_t ROMPATCHD[8];                           /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
31920   __IO  uint32_t ROMPATCHCNTL;                           /**< ROMC Control Register, offset: 0xF4 */
31921   __I   uint32_t ROMPATCHENH;                            /**< ROMC Enable Register High, offset: 0xF8 */
31922   __IO  uint32_t ROMPATCHENL;                            /**< ROMC Enable Register Low, offset: 0xFC */
31923   __IO  uint32_t ROMPATCHA[16];                          /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
31924   uint8_t RESERVED_1[200];
31925   __IO  uint32_t ROMPATCHSR;                             /**< ROMC Status Register, offset: 0x208 */
31926 } ROMC_Type, *ROMC_MemMapPtr;
31927 
31928 /* ----------------------------------------------------------------------------
31929    -- ROMC - Register accessor macros
31930    ---------------------------------------------------------------------------- */
31931 
31932 /*!
31933  * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros
31934  * @{
31935  */
31936 
31937 /* ROMC - Register accessors */
31938 #define ROMC_ROMPATCHD_REG(base,index)           ((base)->ROMPATCHD[index])
31939 #define ROMC_ROMPATCHCNTL_REG(base)              ((base)->ROMPATCHCNTL)
31940 #define ROMC_ROMPATCHENH_REG(base)               ((base)->ROMPATCHENH)
31941 #define ROMC_ROMPATCHENL_REG(base)               ((base)->ROMPATCHENL)
31942 #define ROMC_ROMPATCHA_REG(base,index)           ((base)->ROMPATCHA[index])
31943 #define ROMC_ROMPATCHSR_REG(base)                ((base)->ROMPATCHSR)
31944 
31945 /*!
31946  * @}
31947  */ /* end of group ROMC_Register_Accessor_Macros */
31948 
31949 /* ----------------------------------------------------------------------------
31950    -- ROMC Register Masks
31951    ---------------------------------------------------------------------------- */
31952 
31953 /*!
31954  * @addtogroup ROMC_Register_Masks ROMC Register Masks
31955  * @{
31956  */
31957 
31958 /* ROMPATCHD Bit Fields */
31959 #define ROMC_ROMPATCHD_DATAX_MASK                0xFFFFFFFFu
31960 #define ROMC_ROMPATCHD_DATAX_SHIFT               0
31961 #define ROMC_ROMPATCHD_DATAX(x)                  (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHD_DATAX_SHIFT))&ROMC_ROMPATCHD_DATAX_MASK)
31962 /* ROMPATCHCNTL Bit Fields */
31963 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK           0xFFu
31964 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT          0
31965 #define ROMC_ROMPATCHCNTL_DATAFIX(x)             (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHCNTL_DATAFIX_SHIFT))&ROMC_ROMPATCHCNTL_DATAFIX_MASK)
31966 #define ROMC_ROMPATCHCNTL_DIS_MASK               0x20000000u
31967 #define ROMC_ROMPATCHCNTL_DIS_SHIFT              29
31968 /* ROMPATCHENH Bit Fields */
31969 /* ROMPATCHENL Bit Fields */
31970 #define ROMC_ROMPATCHENL_ENABLE_MASK             0xFFFFu
31971 #define ROMC_ROMPATCHENL_ENABLE_SHIFT            0
31972 #define ROMC_ROMPATCHENL_ENABLE(x)               (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHENL_ENABLE_SHIFT))&ROMC_ROMPATCHENL_ENABLE_MASK)
31973 /* ROMPATCHA Bit Fields */
31974 #define ROMC_ROMPATCHA_THUMBX_MASK               0x1u
31975 #define ROMC_ROMPATCHA_THUMBX_SHIFT              0
31976 #define ROMC_ROMPATCHA_ADDRX_MASK                0x7FFFFEu
31977 #define ROMC_ROMPATCHA_ADDRX_SHIFT               1
31978 #define ROMC_ROMPATCHA_ADDRX(x)                  (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHA_ADDRX_SHIFT))&ROMC_ROMPATCHA_ADDRX_MASK)
31979 /* ROMPATCHSR Bit Fields */
31980 #define ROMC_ROMPATCHSR_SOURCE_MASK              0x3Fu
31981 #define ROMC_ROMPATCHSR_SOURCE_SHIFT             0
31982 #define ROMC_ROMPATCHSR_SOURCE(x)                (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHSR_SOURCE_SHIFT))&ROMC_ROMPATCHSR_SOURCE_MASK)
31983 #define ROMC_ROMPATCHSR_SW_MASK                  0x20000u
31984 #define ROMC_ROMPATCHSR_SW_SHIFT                 17
31985 
31986 /*!
31987  * @}
31988  */ /* end of group ROMC_Register_Masks */
31989 
31990 /* ROMC - Peripheral instance base addresses */
31991 /** Peripheral ROMC base address */
31992 #define ROMC_BASE                                (0x421AC000u)
31993 /** Peripheral ROMC base pointer */
31994 #define ROMC                                     ((ROMC_Type *)ROMC_BASE)
31995 #define ROMC_BASE_PTR                            (ROMC)
31996 /** Array initializer of ROMC peripheral base addresses */
31997 #define ROMC_BASE_ADDRS                          { ROMC_BASE }
31998 /** Array initializer of ROMC peripheral base pointers */
31999 #define ROMC_BASE_PTRS                           { ROMC }
32000 
32001 /* ----------------------------------------------------------------------------
32002    -- ROMC - Register accessor macros
32003    ---------------------------------------------------------------------------- */
32004 
32005 /*!
32006  * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros
32007  * @{
32008  */
32009 
32010 /* ROMC - Register instance definitions */
32011 /* ROMC */
32012 #define ROMC_ROMPATCH0D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,0)
32013 #define ROMC_ROMPATCH1D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,1)
32014 #define ROMC_ROMPATCH2D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,2)
32015 #define ROMC_ROMPATCH3D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,3)
32016 #define ROMC_ROMPATCH4D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,4)
32017 #define ROMC_ROMPATCH5D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,5)
32018 #define ROMC_ROMPATCH6D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,6)
32019 #define ROMC_ROMPATCH7D                          ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,7)
32020 #define ROMC_ROMPATCHCNTL                        ROMC_ROMPATCHCNTL_REG(ROMC_BASE_PTR)
32021 #define ROMC_ROMPATCHENH                         ROMC_ROMPATCHENH_REG(ROMC_BASE_PTR)
32022 #define ROMC_ROMPATCHENL                         ROMC_ROMPATCHENL_REG(ROMC_BASE_PTR)
32023 #define ROMC_ROMPATCH0A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,0)
32024 #define ROMC_ROMPATCH1A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,1)
32025 #define ROMC_ROMPATCH2A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,2)
32026 #define ROMC_ROMPATCH3A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,3)
32027 #define ROMC_ROMPATCH4A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,4)
32028 #define ROMC_ROMPATCH5A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,5)
32029 #define ROMC_ROMPATCH6A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,6)
32030 #define ROMC_ROMPATCH7A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,7)
32031 #define ROMC_ROMPATCH8A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,8)
32032 #define ROMC_ROMPATCH9A                          ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,9)
32033 #define ROMC_ROMPATCH10A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,10)
32034 #define ROMC_ROMPATCH11A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,11)
32035 #define ROMC_ROMPATCH12A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,12)
32036 #define ROMC_ROMPATCH13A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,13)
32037 #define ROMC_ROMPATCH14A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,14)
32038 #define ROMC_ROMPATCH15A                         ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,15)
32039 #define ROMC_ROMPATCHSR                          ROMC_ROMPATCHSR_REG(ROMC_BASE_PTR)
32040 /* ROMC - Register array accessors */
32041 #define ROMC_ROMPATCHD(index)                    ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,index)
32042 #define ROMC_ROMPATCHA(index)                    ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,index)
32043 
32044 /*!
32045  * @}
32046  */ /* end of group ROMC_Register_Accessor_Macros */
32047 
32048 /*!
32049  * @}
32050  */ /* end of group ROMC_Peripheral */
32051 
32052 /* ----------------------------------------------------------------------------
32053    -- SDMAARM Peripheral Access Layer
32054    ---------------------------------------------------------------------------- */
32055 
32056 /*!
32057  * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
32058  * @{
32059  */
32060 
32061 /** SDMAARM - Register Layout Typedef */
32062 typedef struct {
32063   __IO  uint32_t MC0PTR;                                 /**< ARM platform Channel 0 Pointer, offset: 0x0 */
32064   __IO  uint32_t INTR;                                   /**< Channel Interrupts, offset: 0x4 */
32065   __IO  uint32_t STOP_STAT;                              /**< Channel Stop/Channel Status, offset: 0x8 */
32066   __IO  uint32_t HSTART;                                 /**< Channel Start, offset: 0xC */
32067   __IO  uint32_t EVTOVR;                                 /**< Channel Event Override, offset: 0x10 */
32068   __IO  uint32_t DSPOVR;                                 /**< Channel BP Override, offset: 0x14 */
32069   __IO  uint32_t HOSTOVR;                                /**< Channel ARM platform Override, offset: 0x18 */
32070   __IO  uint32_t EVTPEND;                                /**< Channel Event Pending, offset: 0x1C */
32071   uint8_t RESERVED_0[4];
32072   __I   uint32_t RESET;                                  /**< Reset Register, offset: 0x24 */
32073   __I   uint32_t EVTERR;                                 /**< DMA Request Error Register, offset: 0x28 */
32074   __IO  uint32_t INTRMASK;                               /**< Channel ARM platform Interrupt Mask, offset: 0x2C */
32075   __I   uint32_t PSW;                                    /**< Schedule Status, offset: 0x30 */
32076   __I   uint32_t EVTERRDBG;                              /**< DMA Request Error Register, offset: 0x34 */
32077   __IO  uint32_t CONFIG;                                 /**< Configuration Register, offset: 0x38 */
32078   __IO  uint32_t SDMA_LOCK;                              /**< SDMA LOCK, offset: 0x3C */
32079   __IO  uint32_t ONCE_ENB;                               /**< OnCE Enable, offset: 0x40 */
32080   __IO  uint32_t ONCE_DATA;                              /**< OnCE Data Register, offset: 0x44 */
32081   __IO  uint32_t ONCE_INSTR;                             /**< OnCE Instruction Register, offset: 0x48 */
32082   __I   uint32_t ONCE_STAT;                              /**< OnCE Status Register, offset: 0x4C */
32083   __IO  uint32_t ONCE_CMD;                               /**< OnCE Command Register, offset: 0x50 */
32084   uint8_t RESERVED_1[4];
32085   __IO  uint32_t ILLINSTADDR;                            /**< Illegal Instruction Trap Address, offset: 0x58 */
32086   __IO  uint32_t CHN0ADDR;                               /**< Channel 0 Boot Address, offset: 0x5C */
32087   __I   uint32_t EVT_MIRROR;                             /**< DMA Requests, offset: 0x60 */
32088   __I   uint32_t EVT_MIRROR2;                            /**< DMA Requests 2, offset: 0x64 */
32089   uint8_t RESERVED_2[8];
32090   __IO  uint32_t XTRIG_CONF1;                            /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
32091   __IO  uint32_t XTRIG_CONF2;                            /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
32092   uint8_t RESERVED_3[136];
32093   __IO  uint32_t SDMA_CHNPRI[32];                        /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
32094   uint8_t RESERVED_4[128];
32095   __IO  uint32_t CHNENBL[48];                            /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
32096 } SDMAARM_Type, *SDMAARM_MemMapPtr;
32097 
32098 /* ----------------------------------------------------------------------------
32099    -- SDMAARM - Register accessor macros
32100    ---------------------------------------------------------------------------- */
32101 
32102 /*!
32103  * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros
32104  * @{
32105  */
32106 
32107 /* SDMAARM - Register accessors */
32108 #define SDMAARM_MC0PTR_REG(base)                 ((base)->MC0PTR)
32109 #define SDMAARM_INTR_REG(base)                   ((base)->INTR)
32110 #define SDMAARM_STOP_STAT_REG(base)              ((base)->STOP_STAT)
32111 #define SDMAARM_HSTART_REG(base)                 ((base)->HSTART)
32112 #define SDMAARM_EVTOVR_REG(base)                 ((base)->EVTOVR)
32113 #define SDMAARM_DSPOVR_REG(base)                 ((base)->DSPOVR)
32114 #define SDMAARM_HOSTOVR_REG(base)                ((base)->HOSTOVR)
32115 #define SDMAARM_EVTPEND_REG(base)                ((base)->EVTPEND)
32116 #define SDMAARM_RESET_REG(base)                  ((base)->RESET)
32117 #define SDMAARM_EVTERR_REG(base)                 ((base)->EVTERR)
32118 #define SDMAARM_INTRMASK_REG(base)               ((base)->INTRMASK)
32119 #define SDMAARM_PSW_REG(base)                    ((base)->PSW)
32120 #define SDMAARM_EVTERRDBG_REG(base)              ((base)->EVTERRDBG)
32121 #define SDMAARM_CONFIG_REG(base)                 ((base)->CONFIG)
32122 #define SDMAARM_SDMA_LOCK_REG(base)              ((base)->SDMA_LOCK)
32123 #define SDMAARM_ONCE_ENB_REG(base)               ((base)->ONCE_ENB)
32124 #define SDMAARM_ONCE_DATA_REG(base)              ((base)->ONCE_DATA)
32125 #define SDMAARM_ONCE_INSTR_REG(base)             ((base)->ONCE_INSTR)
32126 #define SDMAARM_ONCE_STAT_REG(base)              ((base)->ONCE_STAT)
32127 #define SDMAARM_ONCE_CMD_REG(base)               ((base)->ONCE_CMD)
32128 #define SDMAARM_ILLINSTADDR_REG(base)            ((base)->ILLINSTADDR)
32129 #define SDMAARM_CHN0ADDR_REG(base)               ((base)->CHN0ADDR)
32130 #define SDMAARM_EVT_MIRROR_REG(base)             ((base)->EVT_MIRROR)
32131 #define SDMAARM_EVT_MIRROR2_REG(base)            ((base)->EVT_MIRROR2)
32132 #define SDMAARM_XTRIG_CONF1_REG(base)            ((base)->XTRIG_CONF1)
32133 #define SDMAARM_XTRIG_CONF2_REG(base)            ((base)->XTRIG_CONF2)
32134 #define SDMAARM_SDMA_CHNPRI_REG(base,index)      ((base)->SDMA_CHNPRI[index])
32135 #define SDMAARM_CHNENBL_REG(base,index)          ((base)->CHNENBL[index])
32136 
32137 /*!
32138  * @}
32139  */ /* end of group SDMAARM_Register_Accessor_Macros */
32140 
32141 /* ----------------------------------------------------------------------------
32142    -- SDMAARM Register Masks
32143    ---------------------------------------------------------------------------- */
32144 
32145 /*!
32146  * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
32147  * @{
32148  */
32149 
32150 /* MC0PTR Bit Fields */
32151 #define SDMAARM_MC0PTR_MC0PTR_MASK               0xFFFFFFFFu
32152 #define SDMAARM_MC0PTR_MC0PTR_SHIFT              0
32153 #define SDMAARM_MC0PTR_MC0PTR(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_MC0PTR_MC0PTR_SHIFT))&SDMAARM_MC0PTR_MC0PTR_MASK)
32154 /* INTR Bit Fields */
32155 #define SDMAARM_INTR_HI_MASK                     0xFFFFFFFFu
32156 #define SDMAARM_INTR_HI_SHIFT                    0
32157 #define SDMAARM_INTR_HI(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTR_HI_SHIFT))&SDMAARM_INTR_HI_MASK)
32158 /* STOP_STAT Bit Fields */
32159 #define SDMAARM_STOP_STAT_HE_MASK                0xFFFFFFFFu
32160 #define SDMAARM_STOP_STAT_HE_SHIFT               0
32161 #define SDMAARM_STOP_STAT_HE(x)                  (((uint32_t)(((uint32_t)(x))<<SDMAARM_STOP_STAT_HE_SHIFT))&SDMAARM_STOP_STAT_HE_MASK)
32162 /* HSTART Bit Fields */
32163 #define SDMAARM_HSTART_HSTART_HE_MASK            0xFFFFFFFFu
32164 #define SDMAARM_HSTART_HSTART_HE_SHIFT           0
32165 #define SDMAARM_HSTART_HSTART_HE(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_HSTART_HSTART_HE_SHIFT))&SDMAARM_HSTART_HSTART_HE_MASK)
32166 /* EVTOVR Bit Fields */
32167 #define SDMAARM_EVTOVR_EO_MASK                   0xFFFFFFFFu
32168 #define SDMAARM_EVTOVR_EO_SHIFT                  0
32169 #define SDMAARM_EVTOVR_EO(x)                     (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTOVR_EO_SHIFT))&SDMAARM_EVTOVR_EO_MASK)
32170 /* DSPOVR Bit Fields */
32171 #define SDMAARM_DSPOVR_DO_MASK                   0xFFFFFFFFu
32172 #define SDMAARM_DSPOVR_DO_SHIFT                  0
32173 #define SDMAARM_DSPOVR_DO(x)                     (((uint32_t)(((uint32_t)(x))<<SDMAARM_DSPOVR_DO_SHIFT))&SDMAARM_DSPOVR_DO_MASK)
32174 /* HOSTOVR Bit Fields */
32175 #define SDMAARM_HOSTOVR_HO_MASK                  0xFFFFFFFFu
32176 #define SDMAARM_HOSTOVR_HO_SHIFT                 0
32177 #define SDMAARM_HOSTOVR_HO(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_HOSTOVR_HO_SHIFT))&SDMAARM_HOSTOVR_HO_MASK)
32178 /* EVTPEND Bit Fields */
32179 #define SDMAARM_EVTPEND_EP_MASK                  0xFFFFFFFFu
32180 #define SDMAARM_EVTPEND_EP_SHIFT                 0
32181 #define SDMAARM_EVTPEND_EP(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTPEND_EP_SHIFT))&SDMAARM_EVTPEND_EP_MASK)
32182 /* RESET Bit Fields */
32183 #define SDMAARM_RESET_RESET_MASK                 0x1u
32184 #define SDMAARM_RESET_RESET_SHIFT                0
32185 #define SDMAARM_RESET_RESCHED_MASK               0x2u
32186 #define SDMAARM_RESET_RESCHED_SHIFT              1
32187 /* EVTERR Bit Fields */
32188 #define SDMAARM_EVTERR_CHNERR_MASK               0xFFFFFFFFu
32189 #define SDMAARM_EVTERR_CHNERR_SHIFT              0
32190 #define SDMAARM_EVTERR_CHNERR(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERR_CHNERR_SHIFT))&SDMAARM_EVTERR_CHNERR_MASK)
32191 /* INTRMASK Bit Fields */
32192 #define SDMAARM_INTRMASK_HIMASK_MASK             0xFFFFFFFFu
32193 #define SDMAARM_INTRMASK_HIMASK_SHIFT            0
32194 #define SDMAARM_INTRMASK_HIMASK(x)               (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTRMASK_HIMASK_SHIFT))&SDMAARM_INTRMASK_HIMASK_MASK)
32195 /* PSW Bit Fields */
32196 #define SDMAARM_PSW_CCR_MASK                     0xFu
32197 #define SDMAARM_PSW_CCR_SHIFT                    0
32198 #define SDMAARM_PSW_CCR(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCR_SHIFT))&SDMAARM_PSW_CCR_MASK)
32199 #define SDMAARM_PSW_CCP_MASK                     0xF0u
32200 #define SDMAARM_PSW_CCP_SHIFT                    4
32201 #define SDMAARM_PSW_CCP(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCP_SHIFT))&SDMAARM_PSW_CCP_MASK)
32202 #define SDMAARM_PSW_NCR_MASK                     0x1F00u
32203 #define SDMAARM_PSW_NCR_SHIFT                    8
32204 #define SDMAARM_PSW_NCR(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCR_SHIFT))&SDMAARM_PSW_NCR_MASK)
32205 #define SDMAARM_PSW_NCP_MASK                     0xE000u
32206 #define SDMAARM_PSW_NCP_SHIFT                    13
32207 #define SDMAARM_PSW_NCP(x)                       (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCP_SHIFT))&SDMAARM_PSW_NCP_MASK)
32208 /* EVTERRDBG Bit Fields */
32209 #define SDMAARM_EVTERRDBG_CHNERR_MASK            0xFFFFFFFFu
32210 #define SDMAARM_EVTERRDBG_CHNERR_SHIFT           0
32211 #define SDMAARM_EVTERRDBG_CHNERR(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERRDBG_CHNERR_SHIFT))&SDMAARM_EVTERRDBG_CHNERR_MASK)
32212 /* CONFIG Bit Fields */
32213 #define SDMAARM_CONFIG_CSM_MASK                  0x3u
32214 #define SDMAARM_CONFIG_CSM_SHIFT                 0
32215 #define SDMAARM_CONFIG_CSM(x)                    (((uint32_t)(((uint32_t)(x))<<SDMAARM_CONFIG_CSM_SHIFT))&SDMAARM_CONFIG_CSM_MASK)
32216 #define SDMAARM_CONFIG_ACR_MASK                  0x10u
32217 #define SDMAARM_CONFIG_ACR_SHIFT                 4
32218 #define SDMAARM_CONFIG_RTDOBS_MASK               0x800u
32219 #define SDMAARM_CONFIG_RTDOBS_SHIFT              11
32220 #define SDMAARM_CONFIG_DSPDMA_MASK               0x1000u
32221 #define SDMAARM_CONFIG_DSPDMA_SHIFT              12
32222 /* SDMA_LOCK Bit Fields */
32223 #define SDMAARM_SDMA_LOCK_LOCK_MASK              0x1u
32224 #define SDMAARM_SDMA_LOCK_LOCK_SHIFT             0
32225 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK   0x2u
32226 #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT  1
32227 /* ONCE_ENB Bit Fields */
32228 #define SDMAARM_ONCE_ENB_ENB_MASK                0x1u
32229 #define SDMAARM_ONCE_ENB_ENB_SHIFT               0
32230 /* ONCE_DATA Bit Fields */
32231 #define SDMAARM_ONCE_DATA_DATA_MASK              0xFFFFFFFFu
32232 #define SDMAARM_ONCE_DATA_DATA_SHIFT             0
32233 #define SDMAARM_ONCE_DATA_DATA(x)                (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_DATA_DATA_SHIFT))&SDMAARM_ONCE_DATA_DATA_MASK)
32234 /* ONCE_INSTR Bit Fields */
32235 #define SDMAARM_ONCE_INSTR_INSTR_MASK            0xFFFFu
32236 #define SDMAARM_ONCE_INSTR_INSTR_SHIFT           0
32237 #define SDMAARM_ONCE_INSTR_INSTR(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_INSTR_INSTR_SHIFT))&SDMAARM_ONCE_INSTR_INSTR_MASK)
32238 /* ONCE_STAT Bit Fields */
32239 #define SDMAARM_ONCE_STAT_ECDR_MASK              0x7u
32240 #define SDMAARM_ONCE_STAT_ECDR_SHIFT             0
32241 #define SDMAARM_ONCE_STAT_ECDR(x)                (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_ECDR_SHIFT))&SDMAARM_ONCE_STAT_ECDR_MASK)
32242 #define SDMAARM_ONCE_STAT_MST_MASK               0x80u
32243 #define SDMAARM_ONCE_STAT_MST_SHIFT              7
32244 #define SDMAARM_ONCE_STAT_SWB_MASK               0x100u
32245 #define SDMAARM_ONCE_STAT_SWB_SHIFT              8
32246 #define SDMAARM_ONCE_STAT_ODR_MASK               0x200u
32247 #define SDMAARM_ONCE_STAT_ODR_SHIFT              9
32248 #define SDMAARM_ONCE_STAT_EDR_MASK               0x400u
32249 #define SDMAARM_ONCE_STAT_EDR_SHIFT              10
32250 #define SDMAARM_ONCE_STAT_RCV_MASK               0x800u
32251 #define SDMAARM_ONCE_STAT_RCV_SHIFT              11
32252 #define SDMAARM_ONCE_STAT_PST_MASK               0xF000u
32253 #define SDMAARM_ONCE_STAT_PST_SHIFT              12
32254 #define SDMAARM_ONCE_STAT_PST(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_PST_SHIFT))&SDMAARM_ONCE_STAT_PST_MASK)
32255 /* ONCE_CMD Bit Fields */
32256 #define SDMAARM_ONCE_CMD_CMD_MASK                0xFu
32257 #define SDMAARM_ONCE_CMD_CMD_SHIFT               0
32258 #define SDMAARM_ONCE_CMD_CMD(x)                  (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_CMD_CMD_SHIFT))&SDMAARM_ONCE_CMD_CMD_MASK)
32259 /* ILLINSTADDR Bit Fields */
32260 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK     0x3FFFu
32261 #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT    0
32262 #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x)       (((uint32_t)(((uint32_t)(x))<<SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT))&SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
32263 /* CHN0ADDR Bit Fields */
32264 #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK           0x3FFFu
32265 #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT          0
32266 #define SDMAARM_CHN0ADDR_CHN0ADDR(x)             (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT))&SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
32267 #define SDMAARM_CHN0ADDR_SMSZ_MASK               0x4000u
32268 #define SDMAARM_CHN0ADDR_SMSZ_SHIFT              14
32269 /* EVT_MIRROR Bit Fields */
32270 #define SDMAARM_EVT_MIRROR_EVENTS_MASK           0xFFFFFFFFu
32271 #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT          0
32272 #define SDMAARM_EVT_MIRROR_EVENTS(x)             (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR_EVENTS_MASK)
32273 /* EVT_MIRROR2 Bit Fields */
32274 #define SDMAARM_EVT_MIRROR2_EVENTS_MASK          0xFFFFu
32275 #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT         0
32276 #define SDMAARM_EVT_MIRROR2_EVENTS(x)            (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR2_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR2_EVENTS_MASK)
32277 /* XTRIG_CONF1 Bit Fields */
32278 #define SDMAARM_XTRIG_CONF1_NUM0_MASK            0x3Fu
32279 #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT           0
32280 #define SDMAARM_XTRIG_CONF1_NUM0(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM0_SHIFT))&SDMAARM_XTRIG_CONF1_NUM0_MASK)
32281 #define SDMAARM_XTRIG_CONF1_CNF0_MASK            0x40u
32282 #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT           6
32283 #define SDMAARM_XTRIG_CONF1_NUM1_MASK            0x3F00u
32284 #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT           8
32285 #define SDMAARM_XTRIG_CONF1_NUM1(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM1_SHIFT))&SDMAARM_XTRIG_CONF1_NUM1_MASK)
32286 #define SDMAARM_XTRIG_CONF1_CNF1_MASK            0x4000u
32287 #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT           14
32288 #define SDMAARM_XTRIG_CONF1_NUM2_MASK            0x3F0000u
32289 #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT           16
32290 #define SDMAARM_XTRIG_CONF1_NUM2(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM2_SHIFT))&SDMAARM_XTRIG_CONF1_NUM2_MASK)
32291 #define SDMAARM_XTRIG_CONF1_CNF2_MASK            0x400000u
32292 #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT           22
32293 #define SDMAARM_XTRIG_CONF1_NUM3_MASK            0x3F000000u
32294 #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT           24
32295 #define SDMAARM_XTRIG_CONF1_NUM3(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM3_SHIFT))&SDMAARM_XTRIG_CONF1_NUM3_MASK)
32296 #define SDMAARM_XTRIG_CONF1_CNF3_MASK            0x40000000u
32297 #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT           30
32298 /* XTRIG_CONF2 Bit Fields */
32299 #define SDMAARM_XTRIG_CONF2_NUM4_MASK            0x3Fu
32300 #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT           0
32301 #define SDMAARM_XTRIG_CONF2_NUM4(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM4_SHIFT))&SDMAARM_XTRIG_CONF2_NUM4_MASK)
32302 #define SDMAARM_XTRIG_CONF2_CNF4_MASK            0x40u
32303 #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT           6
32304 #define SDMAARM_XTRIG_CONF2_NUM5_MASK            0x3F00u
32305 #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT           8
32306 #define SDMAARM_XTRIG_CONF2_NUM5(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM5_SHIFT))&SDMAARM_XTRIG_CONF2_NUM5_MASK)
32307 #define SDMAARM_XTRIG_CONF2_CNF5_MASK            0x4000u
32308 #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT           14
32309 #define SDMAARM_XTRIG_CONF2_NUM6_MASK            0x3F0000u
32310 #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT           16
32311 #define SDMAARM_XTRIG_CONF2_NUM6(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM6_SHIFT))&SDMAARM_XTRIG_CONF2_NUM6_MASK)
32312 #define SDMAARM_XTRIG_CONF2_CNF6_MASK            0x400000u
32313 #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT           22
32314 #define SDMAARM_XTRIG_CONF2_NUM7_MASK            0x3F000000u
32315 #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT           24
32316 #define SDMAARM_XTRIG_CONF2_NUM7(x)              (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM7_SHIFT))&SDMAARM_XTRIG_CONF2_NUM7_MASK)
32317 #define SDMAARM_XTRIG_CONF2_CNF7_MASK            0x40000000u
32318 #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT           30
32319 /* SDMA_CHNPRI Bit Fields */
32320 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK         0x7u
32321 #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT        0
32322 #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x)           (((uint32_t)(((uint32_t)(x))<<SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT))&SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
32323 /* CHNENBL Bit Fields */
32324 #define SDMAARM_CHNENBL_ENBLn_MASK               0xFFFFFFFFu
32325 #define SDMAARM_CHNENBL_ENBLn_SHIFT              0
32326 #define SDMAARM_CHNENBL_ENBLn(x)                 (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHNENBL_ENBLn_SHIFT))&SDMAARM_CHNENBL_ENBLn_MASK)
32327 
32328 /*!
32329  * @}
32330  */ /* end of group SDMAARM_Register_Masks */
32331 
32332 /* SDMAARM - Peripheral instance base addresses */
32333 /** Peripheral SDMAARM base address */
32334 #define SDMAARM_BASE                             (0x420EC000u)
32335 /** Peripheral SDMAARM base pointer */
32336 #define SDMAARM                                  ((SDMAARM_Type *)SDMAARM_BASE)
32337 #define SDMAARM_BASE_PTR                         (SDMAARM)
32338 /** Array initializer of SDMAARM peripheral base addresses */
32339 #define SDMAARM_BASE_ADDRS                       { SDMAARM_BASE }
32340 /** Array initializer of SDMAARM peripheral base pointers */
32341 #define SDMAARM_BASE_PTRS                        { SDMAARM }
32342 /** Interrupt vectors for the SDMAARM peripheral type */
32343 #define SDMAARM_IRQS                             { SDMA_IRQn }
32344 
32345 /* ----------------------------------------------------------------------------
32346    -- SDMAARM - Register accessor macros
32347    ---------------------------------------------------------------------------- */
32348 
32349 /*!
32350  * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros
32351  * @{
32352  */
32353 
32354 /* SDMAARM - Register instance definitions */
32355 /* SDMAARM */
32356 #define SDMAARM_MC0PTR                           SDMAARM_MC0PTR_REG(SDMAARM_BASE_PTR)
32357 #define SDMAARM_INTR                             SDMAARM_INTR_REG(SDMAARM_BASE_PTR)
32358 #define SDMAARM_STOP_STAT                        SDMAARM_STOP_STAT_REG(SDMAARM_BASE_PTR)
32359 #define SDMAARM_HSTART                           SDMAARM_HSTART_REG(SDMAARM_BASE_PTR)
32360 #define SDMAARM_EVTOVR                           SDMAARM_EVTOVR_REG(SDMAARM_BASE_PTR)
32361 #define SDMAARM_DSPOVR                           SDMAARM_DSPOVR_REG(SDMAARM_BASE_PTR)
32362 #define SDMAARM_HOSTOVR                          SDMAARM_HOSTOVR_REG(SDMAARM_BASE_PTR)
32363 #define SDMAARM_EVTPEND                          SDMAARM_EVTPEND_REG(SDMAARM_BASE_PTR)
32364 #define SDMAARM_RESET                            SDMAARM_RESET_REG(SDMAARM_BASE_PTR)
32365 #define SDMAARM_EVTERR                           SDMAARM_EVTERR_REG(SDMAARM_BASE_PTR)
32366 #define SDMAARM_INTRMASK                         SDMAARM_INTRMASK_REG(SDMAARM_BASE_PTR)
32367 #define SDMAARM_PSW                              SDMAARM_PSW_REG(SDMAARM_BASE_PTR)
32368 #define SDMAARM_EVTERRDBG                        SDMAARM_EVTERRDBG_REG(SDMAARM_BASE_PTR)
32369 #define SDMAARM_CONFIG                           SDMAARM_CONFIG_REG(SDMAARM_BASE_PTR)
32370 #define SDMAARM_SDMA_LOCK                        SDMAARM_SDMA_LOCK_REG(SDMAARM_BASE_PTR)
32371 #define SDMAARM_ONCE_ENB                         SDMAARM_ONCE_ENB_REG(SDMAARM_BASE_PTR)
32372 #define SDMAARM_ONCE_DATA                        SDMAARM_ONCE_DATA_REG(SDMAARM_BASE_PTR)
32373 #define SDMAARM_ONCE_INSTR                       SDMAARM_ONCE_INSTR_REG(SDMAARM_BASE_PTR)
32374 #define SDMAARM_ONCE_STAT                        SDMAARM_ONCE_STAT_REG(SDMAARM_BASE_PTR)
32375 #define SDMAARM_ONCE_CMD                         SDMAARM_ONCE_CMD_REG(SDMAARM_BASE_PTR)
32376 #define SDMAARM_ILLINSTADDR                      SDMAARM_ILLINSTADDR_REG(SDMAARM_BASE_PTR)
32377 #define SDMAARM_CHN0ADDR                         SDMAARM_CHN0ADDR_REG(SDMAARM_BASE_PTR)
32378 #define SDMAARM_EVT_MIRROR                       SDMAARM_EVT_MIRROR_REG(SDMAARM_BASE_PTR)
32379 #define SDMAARM_EVT_MIRROR2                      SDMAARM_EVT_MIRROR2_REG(SDMAARM_BASE_PTR)
32380 #define SDMAARM_XTRIG_CONF1                      SDMAARM_XTRIG_CONF1_REG(SDMAARM_BASE_PTR)
32381 #define SDMAARM_XTRIG_CONF2                      SDMAARM_XTRIG_CONF2_REG(SDMAARM_BASE_PTR)
32382 #define SDMAARM_SDMA_CHNPRI0                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,0)
32383 #define SDMAARM_SDMA_CHNPRI1                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,1)
32384 #define SDMAARM_SDMA_CHNPRI2                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,2)
32385 #define SDMAARM_SDMA_CHNPRI3                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,3)
32386 #define SDMAARM_SDMA_CHNPRI4                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,4)
32387 #define SDMAARM_SDMA_CHNPRI5                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,5)
32388 #define SDMAARM_SDMA_CHNPRI6                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,6)
32389 #define SDMAARM_SDMA_CHNPRI7                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,7)
32390 #define SDMAARM_SDMA_CHNPRI8                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,8)
32391 #define SDMAARM_SDMA_CHNPRI9                     SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,9)
32392 #define SDMAARM_SDMA_CHNPRI10                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,10)
32393 #define SDMAARM_SDMA_CHNPRI11                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,11)
32394 #define SDMAARM_SDMA_CHNPRI12                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,12)
32395 #define SDMAARM_SDMA_CHNPRI13                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,13)
32396 #define SDMAARM_SDMA_CHNPRI14                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,14)
32397 #define SDMAARM_SDMA_CHNPRI15                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,15)
32398 #define SDMAARM_SDMA_CHNPRI16                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,16)
32399 #define SDMAARM_SDMA_CHNPRI17                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,17)
32400 #define SDMAARM_SDMA_CHNPRI18                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,18)
32401 #define SDMAARM_SDMA_CHNPRI19                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,19)
32402 #define SDMAARM_SDMA_CHNPRI20                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,20)
32403 #define SDMAARM_SDMA_CHNPRI21                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,21)
32404 #define SDMAARM_SDMA_CHNPRI22                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,22)
32405 #define SDMAARM_SDMA_CHNPRI23                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,23)
32406 #define SDMAARM_SDMA_CHNPRI24                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,24)
32407 #define SDMAARM_SDMA_CHNPRI25                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,25)
32408 #define SDMAARM_SDMA_CHNPRI26                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,26)
32409 #define SDMAARM_SDMA_CHNPRI27                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,27)
32410 #define SDMAARM_SDMA_CHNPRI28                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,28)
32411 #define SDMAARM_SDMA_CHNPRI29                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,29)
32412 #define SDMAARM_SDMA_CHNPRI30                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,30)
32413 #define SDMAARM_SDMA_CHNPRI31                    SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,31)
32414 #define SDMAARM_CHNENBL0                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,0)
32415 #define SDMAARM_CHNENBL1                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,1)
32416 #define SDMAARM_CHNENBL2                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,2)
32417 #define SDMAARM_CHNENBL3                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,3)
32418 #define SDMAARM_CHNENBL4                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,4)
32419 #define SDMAARM_CHNENBL5                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,5)
32420 #define SDMAARM_CHNENBL6                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,6)
32421 #define SDMAARM_CHNENBL7                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,7)
32422 #define SDMAARM_CHNENBL8                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,8)
32423 #define SDMAARM_CHNENBL9                         SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,9)
32424 #define SDMAARM_CHNENBL10                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,10)
32425 #define SDMAARM_CHNENBL11                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,11)
32426 #define SDMAARM_CHNENBL12                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,12)
32427 #define SDMAARM_CHNENBL13                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,13)
32428 #define SDMAARM_CHNENBL14                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,14)
32429 #define SDMAARM_CHNENBL15                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,15)
32430 #define SDMAARM_CHNENBL16                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,16)
32431 #define SDMAARM_CHNENBL17                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,17)
32432 #define SDMAARM_CHNENBL18                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,18)
32433 #define SDMAARM_CHNENBL19                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,19)
32434 #define SDMAARM_CHNENBL20                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,20)
32435 #define SDMAARM_CHNENBL21                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,21)
32436 #define SDMAARM_CHNENBL22                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,22)
32437 #define SDMAARM_CHNENBL23                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,23)
32438 #define SDMAARM_CHNENBL24                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,24)
32439 #define SDMAARM_CHNENBL25                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,25)
32440 #define SDMAARM_CHNENBL26                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,26)
32441 #define SDMAARM_CHNENBL27                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,27)
32442 #define SDMAARM_CHNENBL28                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,28)
32443 #define SDMAARM_CHNENBL29                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,29)
32444 #define SDMAARM_CHNENBL30                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,30)
32445 #define SDMAARM_CHNENBL31                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,31)
32446 #define SDMAARM_CHNENBL32                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,32)
32447 #define SDMAARM_CHNENBL33                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,33)
32448 #define SDMAARM_CHNENBL34                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,34)
32449 #define SDMAARM_CHNENBL35                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,35)
32450 #define SDMAARM_CHNENBL36                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,36)
32451 #define SDMAARM_CHNENBL37                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,37)
32452 #define SDMAARM_CHNENBL38                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,38)
32453 #define SDMAARM_CHNENBL39                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,39)
32454 #define SDMAARM_CHNENBL40                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,40)
32455 #define SDMAARM_CHNENBL41                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,41)
32456 #define SDMAARM_CHNENBL42                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,42)
32457 #define SDMAARM_CHNENBL43                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,43)
32458 #define SDMAARM_CHNENBL44                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,44)
32459 #define SDMAARM_CHNENBL45                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,45)
32460 #define SDMAARM_CHNENBL46                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,46)
32461 #define SDMAARM_CHNENBL47                        SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,47)
32462 /* SDMAARM - Register array accessors */
32463 #define SDMAARM_SDMA_CHNPRI(index)               SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,index)
32464 #define SDMAARM_CHNENBL(index)                   SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,index)
32465 
32466 /*!
32467  * @}
32468  */ /* end of group SDMAARM_Register_Accessor_Macros */
32469 
32470 /*!
32471  * @}
32472  */ /* end of group SDMAARM_Peripheral */
32473 
32474 /* ----------------------------------------------------------------------------
32475    -- SDMABP Peripheral Access Layer
32476    ---------------------------------------------------------------------------- */
32477 
32478 /*!
32479  * @addtogroup SDMABP_Peripheral_Access_Layer SDMABP Peripheral Access Layer
32480  * @{
32481  */
32482 
32483 /** SDMABP - Register Layout Typedef */
32484 typedef struct {
32485   __IO  uint32_t DC0PTR;                                 /**< Channel 0 Pointer, offset: 0x0 */
32486   __IO  uint32_t INTR;                                   /**< Channel Interrupts, offset: 0x4 */
32487   __IO  uint32_t STOP_STAT;                              /**< Channel Stop/Channel Status, offset: 0x8 */
32488   __I   uint32_t DSTART;                                 /**< Channel Start, offset: 0xC */
32489   uint8_t RESERVED_0[24];
32490   __I   uint32_t EVTERR;                                 /**< DMA Request Error Register, offset: 0x28 */
32491   __IO  uint32_t INTRMASK;                               /**< Channel DSP Interrupt Mask, offset: 0x2C */
32492   uint8_t RESERVED_1[4];
32493   __I   uint32_t EVTERRDBG;                              /**< DMA Request Error Register, offset: 0x34 */
32494 } SDMABP_Type, *SDMABP_MemMapPtr;
32495 
32496 /* ----------------------------------------------------------------------------
32497    -- SDMABP - Register accessor macros
32498    ---------------------------------------------------------------------------- */
32499 
32500 /*!
32501  * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros
32502  * @{
32503  */
32504 
32505 /* SDMABP - Register accessors */
32506 #define SDMABP_DC0PTR_REG(base)                  ((base)->DC0PTR)
32507 #define SDMABP_INTR_REG(base)                    ((base)->INTR)
32508 #define SDMABP_STOP_STAT_REG(base)               ((base)->STOP_STAT)
32509 #define SDMABP_DSTART_REG(base)                  ((base)->DSTART)
32510 #define SDMABP_EVTERR_REG(base)                  ((base)->EVTERR)
32511 #define SDMABP_INTRMASK_REG(base)                ((base)->INTRMASK)
32512 #define SDMABP_EVTERRDBG_REG(base)               ((base)->EVTERRDBG)
32513 
32514 /*!
32515  * @}
32516  */ /* end of group SDMABP_Register_Accessor_Macros */
32517 
32518 /* ----------------------------------------------------------------------------
32519    -- SDMABP Register Masks
32520    ---------------------------------------------------------------------------- */
32521 
32522 /*!
32523  * @addtogroup SDMABP_Register_Masks SDMABP Register Masks
32524  * @{
32525  */
32526 
32527 /* DC0PTR Bit Fields */
32528 #define SDMABP_DC0PTR_DC0PTR_MASK                0xFFFFFFFFu
32529 #define SDMABP_DC0PTR_DC0PTR_SHIFT               0
32530 #define SDMABP_DC0PTR_DC0PTR(x)                  (((uint32_t)(((uint32_t)(x))<<SDMABP_DC0PTR_DC0PTR_SHIFT))&SDMABP_DC0PTR_DC0PTR_MASK)
32531 /* INTR Bit Fields */
32532 #define SDMABP_INTR_DI_MASK                      0xFFFFFFFFu
32533 #define SDMABP_INTR_DI_SHIFT                     0
32534 #define SDMABP_INTR_DI(x)                        (((uint32_t)(((uint32_t)(x))<<SDMABP_INTR_DI_SHIFT))&SDMABP_INTR_DI_MASK)
32535 /* STOP_STAT Bit Fields */
32536 #define SDMABP_STOP_STAT_DE_MASK                 0xFFFFFFFFu
32537 #define SDMABP_STOP_STAT_DE_SHIFT                0
32538 #define SDMABP_STOP_STAT_DE(x)                   (((uint32_t)(((uint32_t)(x))<<SDMABP_STOP_STAT_DE_SHIFT))&SDMABP_STOP_STAT_DE_MASK)
32539 /* DSTART Bit Fields */
32540 #define SDMABP_DSTART_DSTART_DE_MASK             0xFFFFFFFFu
32541 #define SDMABP_DSTART_DSTART_DE_SHIFT            0
32542 #define SDMABP_DSTART_DSTART_DE(x)               (((uint32_t)(((uint32_t)(x))<<SDMABP_DSTART_DSTART_DE_SHIFT))&SDMABP_DSTART_DSTART_DE_MASK)
32543 /* EVTERR Bit Fields */
32544 #define SDMABP_EVTERR_CHNERR_MASK                0xFFFFFFFFu
32545 #define SDMABP_EVTERR_CHNERR_SHIFT               0
32546 #define SDMABP_EVTERR_CHNERR(x)                  (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERR_CHNERR_SHIFT))&SDMABP_EVTERR_CHNERR_MASK)
32547 /* INTRMASK Bit Fields */
32548 #define SDMABP_INTRMASK_DIMASK_MASK              0xFFFFFFFFu
32549 #define SDMABP_INTRMASK_DIMASK_SHIFT             0
32550 #define SDMABP_INTRMASK_DIMASK(x)                (((uint32_t)(((uint32_t)(x))<<SDMABP_INTRMASK_DIMASK_SHIFT))&SDMABP_INTRMASK_DIMASK_MASK)
32551 /* EVTERRDBG Bit Fields */
32552 #define SDMABP_EVTERRDBG_CHNERR_MASK             0xFFFFFFFFu
32553 #define SDMABP_EVTERRDBG_CHNERR_SHIFT            0
32554 #define SDMABP_EVTERRDBG_CHNERR(x)               (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERRDBG_CHNERR_SHIFT))&SDMABP_EVTERRDBG_CHNERR_MASK)
32555 
32556 /*!
32557  * @}
32558  */ /* end of group SDMABP_Register_Masks */
32559 
32560 /* SDMABP - Peripheral instance base addresses */
32561 /** Peripheral SDMABP base address */
32562 #define SDMABP_BASE                              (0x420EC000u)
32563 /** Peripheral SDMABP base pointer */
32564 #define SDMABP                                   ((SDMABP_Type *)SDMABP_BASE)
32565 #define SDMABP_BASE_PTR                          (SDMABP)
32566 /** Array initializer of SDMABP peripheral base addresses */
32567 #define SDMABP_BASE_ADDRS                        { SDMABP_BASE }
32568 /** Array initializer of SDMABP peripheral base pointers */
32569 #define SDMABP_BASE_PTRS                         { SDMABP }
32570 
32571 /* ----------------------------------------------------------------------------
32572    -- SDMABP - Register accessor macros
32573    ---------------------------------------------------------------------------- */
32574 
32575 /*!
32576  * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros
32577  * @{
32578  */
32579 
32580 /* SDMABP - Register instance definitions */
32581 /* SDMABP */
32582 #define SDMABP_DC0PTR                            SDMABP_DC0PTR_REG(SDMABP_BASE_PTR)
32583 #define SDMABP_INTR                              SDMABP_INTR_REG(SDMABP_BASE_PTR)
32584 #define SDMABP_STOP_STAT                         SDMABP_STOP_STAT_REG(SDMABP_BASE_PTR)
32585 #define SDMABP_DSTART                            SDMABP_DSTART_REG(SDMABP_BASE_PTR)
32586 #define SDMABP_EVTERR                            SDMABP_EVTERR_REG(SDMABP_BASE_PTR)
32587 #define SDMABP_INTRMASK                          SDMABP_INTRMASK_REG(SDMABP_BASE_PTR)
32588 #define SDMABP_EVTERRDBG                         SDMABP_EVTERRDBG_REG(SDMABP_BASE_PTR)
32589 
32590 /*!
32591  * @}
32592  */ /* end of group SDMABP_Register_Accessor_Macros */
32593 
32594 /*!
32595  * @}
32596  */ /* end of group SDMABP_Peripheral */
32597 
32598 /* ----------------------------------------------------------------------------
32599    -- SDMACORE Peripheral Access Layer
32600    ---------------------------------------------------------------------------- */
32601 
32602 /*!
32603  * @addtogroup SDMACORE_Peripheral_Access_Layer SDMACORE Peripheral Access Layer
32604  * @{
32605  */
32606 
32607 /** SDMACORE - Register Layout Typedef */
32608 typedef struct {
32609   union {                                          /* offset: 0x0 */
32610   __I     uint32_t MC0PTR;                                      /**< ARM platform Channel 0 Pointer,offset: 0x0 */
32611   struct {                                         /* offset: 0x2 */
32612       uint8_t RESERVED_0[2];
32613   __I     uint32_t CCPTR;                                       /**< Current Channel Pointer,offset: 0x2 */
32614     } CCPTR;
32615   struct {                                         /* offset: 0x3 */
32616       uint8_t RESERVED_0[3];
32617   __I     uint32_t CCR;                                         /**< Current Channel Register,offset: 0x3 */
32618     } CCR;
32619   struct {                                         /* offset: 0x4 */
32620       uint8_t RESERVED_0[4];
32621   __I     uint32_t NCR;                                         /**< Highest Pending Channel Register,offset: 0x4 */
32622     } NCR;
32623   struct {                                         /* offset: 0x5 */
32624       uint8_t RESERVED_0[5];
32625   __I     uint32_t EVENTS;                                      /**< External DMA Requests Mirror,offset: 0x5 */
32626     } EVENTS;
32627   struct {                                         /* offset: 0x6 */
32628       uint8_t RESERVED_0[6];
32629   __I     uint32_t CCPRI;                                       /**< Current Channel Priority,offset: 0x6 */
32630     } CCPRI;
32631   struct {                                         /* offset: 0x7 */
32632       uint8_t RESERVED_0[7];
32633   __I     uint32_t NCPRI;                                       /**< Next Channel Priority,offset: 0x7 */
32634     } NCPRI;
32635   struct {                                         /* offset: 0x9 */
32636       uint8_t RESERVED_0[9];
32637   __IO    uint32_t ECOUNT;                                      /**< OnCE Event Cell Counter,offset: 0x9 */
32638     } ECOUNT;
32639   struct {                                         /* offset: 0xA */
32640       uint8_t RESERVED_0[10];
32641   __IO    uint32_t ECTL;                                        /**< OnCE Event Cell Control Register,offset: 0xA */
32642     } ECTL;
32643   struct {                                         /* offset: 0xB */
32644       uint8_t RESERVED_0[11];
32645   __IO    uint32_t EAA;                                         /**< OnCE Event Address Register A,offset: 0xB */
32646     } EAA;
32647   struct {                                         /* offset: 0xC */
32648       uint8_t RESERVED_0[12];
32649   __IO    uint32_t EAB;                                         /**< OnCE Event Cell Address Register B,offset: 0xC */
32650     } EAB;
32651   struct {                                         /* offset: 0xD */
32652       uint8_t RESERVED_0[13];
32653   __IO    uint32_t EAM;                                         /**< OnCE Event Cell Address Mask,offset: 0xD */
32654     } EAM;
32655   struct {                                         /* offset: 0xE */
32656       uint8_t RESERVED_0[14];
32657   __IO    uint32_t ED;                                          /**< OnCE Event Cell Data Register,offset: 0xE */
32658     } ED;
32659   struct {                                         /* offset: 0xF */
32660       uint8_t RESERVED_0[15];
32661   __IO    uint32_t EDM;                                         /**< OnCE Event Cell Data Mask,offset: 0xF */
32662     } EDM;
32663   };
32664   uint8_t RESERVED_0[5];
32665   union {                                          /* offset: 0x18 */
32666   __IO    uint32_t RTB;                                         /**< OnCE Real-Time Buffer,offset: 0x18 */
32667   struct {                                         /* offset: 0x19 */
32668       uint8_t RESERVED_0[1];
32669   __I     uint32_t TB;                                          /**< OnCE Trace Buffer,offset: 0x19 */
32670     } TB;
32671   struct {                                         /* offset: 0x1A */
32672       uint8_t RESERVED_0[2];
32673   __I     uint32_t OSTAT;                                       /**< OnCE Status,offset: 0x1A */
32674     } OSTAT;
32675   struct {                                         /* offset: 0x1C */
32676       uint8_t RESERVED_0[4];
32677   __I     uint32_t MCHN0ADDR;                                   /**< Channel 0 Boot Address,offset: 0x1C */
32678     } MCHN0ADDR;
32679   struct {                                         /* offset: 0x1D */
32680       uint8_t RESERVED_0[5];
32681   __I     uint32_t ENDIANNESS;                                  /**< ENDIAN Status Register,offset: 0x1D */
32682     } ENDIANNESS;
32683   struct {                                         /* offset: 0x1E */
32684       uint8_t RESERVED_0[6];
32685   __I     uint32_t SDMA_LOCK;                                   /**< Lock Status Register,offset: 0x1E */
32686     } SDMA_LOCK;
32687   struct {                                         /* offset: 0x1F */
32688       uint8_t RESERVED_0[7];
32689   __I     uint32_t EVENTS2;                                     /**< External DMA Requests Mirror #2,offset: 0x1F */
32690     } EVENTS2;
32691   };
32692 } SDMACORE_Type, *SDMACORE_MemMapPtr;
32693 
32694 /* ----------------------------------------------------------------------------
32695    -- SDMACORE - Register accessor macros
32696    ---------------------------------------------------------------------------- */
32697 
32698 /*!
32699  * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros
32700  * @{
32701  */
32702 
32703 /* SDMACORE - Register accessors */
32704 #define SDMACORE_MC0PTR_REG(base)                ((base)->MC0PTR)
32705 #define SDMACORE_CCPTR_REG(base)                 ((base)->CCPTR.CCPTR)
32706 #define SDMACORE_CCR_REG(base)                   ((base)->CCR.CCR)
32707 #define SDMACORE_NCR_REG(base)                   ((base)->NCR.NCR)
32708 #define SDMACORE_EVENTS_REG(base)                ((base)->EVENTS.EVENTS)
32709 #define SDMACORE_CCPRI_REG(base)                 ((base)->CCPRI.CCPRI)
32710 #define SDMACORE_NCPRI_REG(base)                 ((base)->NCPRI.NCPRI)
32711 #define SDMACORE_ECOUNT_REG(base)                ((base)->ECOUNT.ECOUNT)
32712 #define SDMACORE_ECTL_REG(base)                  ((base)->ECTL.ECTL)
32713 #define SDMACORE_EAA_REG(base)                   ((base)->EAA.EAA)
32714 #define SDMACORE_EAB_REG(base)                   ((base)->EAB.EAB)
32715 #define SDMACORE_EAM_REG(base)                   ((base)->EAM.EAM)
32716 #define SDMACORE_ED_REG(base)                    ((base)->ED.ED)
32717 #define SDMACORE_EDM_REG(base)                   ((base)->EDM.EDM)
32718 #define SDMACORE_RTB_REG(base)                   ((base)->RTB)
32719 #define SDMACORE_TB_REG(base)                    ((base)->TB.TB)
32720 #define SDMACORE_OSTAT_REG(base)                 ((base)->OSTAT.OSTAT)
32721 #define SDMACORE_MCHN0ADDR_REG(base)             ((base)->MCHN0ADDR.MCHN0ADDR)
32722 #define SDMACORE_ENDIANNESS_REG(base)            ((base)->ENDIANNESS.ENDIANNESS)
32723 #define SDMACORE_SDMA_LOCK_REG(base)             ((base)->SDMA_LOCK.SDMA_LOCK)
32724 #define SDMACORE_EVENTS2_REG(base)               ((base)->EVENTS2.EVENTS2)
32725 
32726 /*!
32727  * @}
32728  */ /* end of group SDMACORE_Register_Accessor_Macros */
32729 
32730 /* ----------------------------------------------------------------------------
32731    -- SDMACORE Register Masks
32732    ---------------------------------------------------------------------------- */
32733 
32734 /*!
32735  * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks
32736  * @{
32737  */
32738 
32739 /* MC0PTR Bit Fields */
32740 #define SDMACORE_MC0PTR_MC0PTR_MASK              0xFFFFFFFFu
32741 #define SDMACORE_MC0PTR_MC0PTR_SHIFT             0
32742 #define SDMACORE_MC0PTR_MC0PTR(x)                (((uint32_t)(((uint32_t)(x))<<SDMACORE_MC0PTR_MC0PTR_SHIFT))&SDMACORE_MC0PTR_MC0PTR_MASK)
32743 /* CCPTR Bit Fields */
32744 #define SDMACORE_CCPTR_CCPTR_MASK                0xFFFFu
32745 #define SDMACORE_CCPTR_CCPTR_SHIFT               0
32746 #define SDMACORE_CCPTR_CCPTR(x)                  (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPTR_CCPTR_SHIFT))&SDMACORE_CCPTR_CCPTR_MASK)
32747 /* CCR Bit Fields */
32748 #define SDMACORE_CCR_CCR_MASK                    0x1Fu
32749 #define SDMACORE_CCR_CCR_SHIFT                   0
32750 #define SDMACORE_CCR_CCR(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCR_CCR_SHIFT))&SDMACORE_CCR_CCR_MASK)
32751 /* NCR Bit Fields */
32752 #define SDMACORE_NCR_NCR_MASK                    0x1Fu
32753 #define SDMACORE_NCR_NCR_SHIFT                   0
32754 #define SDMACORE_NCR_NCR(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCR_NCR_SHIFT))&SDMACORE_NCR_NCR_MASK)
32755 /* EVENTS Bit Fields */
32756 #define SDMACORE_EVENTS_EVENTS_MASK              0xFFFFFFFFu
32757 #define SDMACORE_EVENTS_EVENTS_SHIFT             0
32758 #define SDMACORE_EVENTS_EVENTS(x)                (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS_EVENTS_SHIFT))&SDMACORE_EVENTS_EVENTS_MASK)
32759 /* CCPRI Bit Fields */
32760 #define SDMACORE_CCPRI_CCPRI_MASK                0x7u
32761 #define SDMACORE_CCPRI_CCPRI_SHIFT               0
32762 #define SDMACORE_CCPRI_CCPRI(x)                  (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPRI_CCPRI_SHIFT))&SDMACORE_CCPRI_CCPRI_MASK)
32763 /* NCPRI Bit Fields */
32764 #define SDMACORE_NCPRI_NCPRI_MASK                0x7u
32765 #define SDMACORE_NCPRI_NCPRI_SHIFT               0
32766 #define SDMACORE_NCPRI_NCPRI(x)                  (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCPRI_NCPRI_SHIFT))&SDMACORE_NCPRI_NCPRI_MASK)
32767 /* ECOUNT Bit Fields */
32768 #define SDMACORE_ECOUNT_ECOUNT_MASK              0xFFFFu
32769 #define SDMACORE_ECOUNT_ECOUNT_SHIFT             0
32770 #define SDMACORE_ECOUNT_ECOUNT(x)                (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECOUNT_ECOUNT_SHIFT))&SDMACORE_ECOUNT_ECOUNT_MASK)
32771 /* ECTL Bit Fields */
32772 #define SDMACORE_ECTL_ATS_MASK                   0x3u
32773 #define SDMACORE_ECTL_ATS_SHIFT                  0
32774 #define SDMACORE_ECTL_ATS(x)                     (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATS_SHIFT))&SDMACORE_ECTL_ATS_MASK)
32775 #define SDMACORE_ECTL_AATC_MASK                  0xCu
32776 #define SDMACORE_ECTL_AATC_SHIFT                 2
32777 #define SDMACORE_ECTL_AATC(x)                    (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_AATC_SHIFT))&SDMACORE_ECTL_AATC_MASK)
32778 #define SDMACORE_ECTL_ABTC_MASK                  0x30u
32779 #define SDMACORE_ECTL_ABTC_SHIFT                 4
32780 #define SDMACORE_ECTL_ABTC(x)                    (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ABTC_SHIFT))&SDMACORE_ECTL_ABTC_MASK)
32781 #define SDMACORE_ECTL_ATC_MASK                   0xC0u
32782 #define SDMACORE_ECTL_ATC_SHIFT                  6
32783 #define SDMACORE_ECTL_ATC(x)                     (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATC_SHIFT))&SDMACORE_ECTL_ATC_MASK)
32784 #define SDMACORE_ECTL_DTC_MASK                   0x300u
32785 #define SDMACORE_ECTL_DTC_SHIFT                  8
32786 #define SDMACORE_ECTL_DTC(x)                     (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_DTC_SHIFT))&SDMACORE_ECTL_DTC_MASK)
32787 #define SDMACORE_ECTL_ECTC_MASK                  0xC00u
32788 #define SDMACORE_ECTL_ECTC_SHIFT                 10
32789 #define SDMACORE_ECTL_ECTC(x)                    (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ECTC_SHIFT))&SDMACORE_ECTL_ECTC_MASK)
32790 #define SDMACORE_ECTL_CNT_MASK                   0x1000u
32791 #define SDMACORE_ECTL_CNT_SHIFT                  12
32792 #define SDMACORE_ECTL_EN_MASK                    0x2000u
32793 #define SDMACORE_ECTL_EN_SHIFT                   13
32794 /* EAA Bit Fields */
32795 #define SDMACORE_EAA_EAA_MASK                    0xFFFFu
32796 #define SDMACORE_EAA_EAA_SHIFT                   0
32797 #define SDMACORE_EAA_EAA(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAA_EAA_SHIFT))&SDMACORE_EAA_EAA_MASK)
32798 /* EAB Bit Fields */
32799 #define SDMACORE_EAB_EAB_MASK                    0xFFFFu
32800 #define SDMACORE_EAB_EAB_SHIFT                   0
32801 #define SDMACORE_EAB_EAB(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAB_EAB_SHIFT))&SDMACORE_EAB_EAB_MASK)
32802 /* EAM Bit Fields */
32803 #define SDMACORE_EAM_EAM_MASK                    0xFFFFu
32804 #define SDMACORE_EAM_EAM_SHIFT                   0
32805 #define SDMACORE_EAM_EAM(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAM_EAM_SHIFT))&SDMACORE_EAM_EAM_MASK)
32806 /* ED Bit Fields */
32807 #define SDMACORE_ED_ED_MASK                      0xFFFFFFFFu
32808 #define SDMACORE_ED_ED_SHIFT                     0
32809 #define SDMACORE_ED_ED(x)                        (((uint32_t)(((uint32_t)(x))<<SDMACORE_ED_ED_SHIFT))&SDMACORE_ED_ED_MASK)
32810 /* EDM Bit Fields */
32811 #define SDMACORE_EDM_EDM_MASK                    0xFFFFFFFFu
32812 #define SDMACORE_EDM_EDM_SHIFT                   0
32813 #define SDMACORE_EDM_EDM(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_EDM_EDM_SHIFT))&SDMACORE_EDM_EDM_MASK)
32814 /* RTB Bit Fields */
32815 #define SDMACORE_RTB_RTB_MASK                    0xFFFFFFFFu
32816 #define SDMACORE_RTB_RTB_SHIFT                   0
32817 #define SDMACORE_RTB_RTB(x)                      (((uint32_t)(((uint32_t)(x))<<SDMACORE_RTB_RTB_SHIFT))&SDMACORE_RTB_RTB_MASK)
32818 /* TB Bit Fields */
32819 #define SDMACORE_TB_CHFADDR_MASK                 0x3FFFu
32820 #define SDMACORE_TB_CHFADDR_SHIFT                0
32821 #define SDMACORE_TB_CHFADDR(x)                   (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_CHFADDR_SHIFT))&SDMACORE_TB_CHFADDR_MASK)
32822 #define SDMACORE_TB_TADDR_MASK                   0xFFFC000u
32823 #define SDMACORE_TB_TADDR_SHIFT                  14
32824 #define SDMACORE_TB_TADDR(x)                     (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_TADDR_SHIFT))&SDMACORE_TB_TADDR_MASK)
32825 #define SDMACORE_TB_TBF_MASK                     0x10000000u
32826 #define SDMACORE_TB_TBF_SHIFT                    28
32827 /* OSTAT Bit Fields */
32828 #define SDMACORE_OSTAT_ECDR_MASK                 0x7u
32829 #define SDMACORE_OSTAT_ECDR_SHIFT                0
32830 #define SDMACORE_OSTAT_ECDR(x)                   (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_ECDR_SHIFT))&SDMACORE_OSTAT_ECDR_MASK)
32831 #define SDMACORE_OSTAT_MST_MASK                  0x80u
32832 #define SDMACORE_OSTAT_MST_SHIFT                 7
32833 #define SDMACORE_OSTAT_SWB_MASK                  0x100u
32834 #define SDMACORE_OSTAT_SWB_SHIFT                 8
32835 #define SDMACORE_OSTAT_ODR_MASK                  0x200u
32836 #define SDMACORE_OSTAT_ODR_SHIFT                 9
32837 #define SDMACORE_OSTAT_EDR_MASK                  0x400u
32838 #define SDMACORE_OSTAT_EDR_SHIFT                 10
32839 #define SDMACORE_OSTAT_RCV_MASK                  0x800u
32840 #define SDMACORE_OSTAT_RCV_SHIFT                 11
32841 #define SDMACORE_OSTAT_PST_MASK                  0xF000u
32842 #define SDMACORE_OSTAT_PST_SHIFT                 12
32843 #define SDMACORE_OSTAT_PST(x)                    (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_PST_SHIFT))&SDMACORE_OSTAT_PST_MASK)
32844 /* MCHN0ADDR Bit Fields */
32845 #define SDMACORE_MCHN0ADDR_CHN0ADDR_MASK         0x3FFFu
32846 #define SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT        0
32847 #define SDMACORE_MCHN0ADDR_CHN0ADDR(x)           (((uint32_t)(((uint32_t)(x))<<SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT))&SDMACORE_MCHN0ADDR_CHN0ADDR_MASK)
32848 #define SDMACORE_MCHN0ADDR_SMSZ_MASK             0x4000u
32849 #define SDMACORE_MCHN0ADDR_SMSZ_SHIFT            14
32850 /* ENDIANNESS Bit Fields */
32851 #define SDMACORE_ENDIANNESS_APEND_MASK           0x1u
32852 #define SDMACORE_ENDIANNESS_APEND_SHIFT          0
32853 /* SDMA_LOCK Bit Fields */
32854 #define SDMACORE_SDMA_LOCK_LOCK_MASK             0x1u
32855 #define SDMACORE_SDMA_LOCK_LOCK_SHIFT            0
32856 /* EVENTS2 Bit Fields */
32857 #define SDMACORE_EVENTS2_EVENTS_MASK             0xFFFFu
32858 #define SDMACORE_EVENTS2_EVENTS_SHIFT            0
32859 #define SDMACORE_EVENTS2_EVENTS(x)               (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS2_EVENTS_SHIFT))&SDMACORE_EVENTS2_EVENTS_MASK)
32860 
32861 /*!
32862  * @}
32863  */ /* end of group SDMACORE_Register_Masks */
32864 
32865 /* SDMACORE - Peripheral instance base addresses */
32866 /** Peripheral SDMACORE base address */
32867 #define SDMACORE_BASE                            (0x420EC000u)
32868 /** Peripheral SDMACORE base pointer */
32869 #define SDMACORE                                 ((SDMACORE_Type *)SDMACORE_BASE)
32870 #define SDMACORE_BASE_PTR                        (SDMACORE)
32871 /** Array initializer of SDMACORE peripheral base addresses */
32872 #define SDMACORE_BASE_ADDRS                      { SDMACORE_BASE }
32873 /** Array initializer of SDMACORE peripheral base pointers */
32874 #define SDMACORE_BASE_PTRS                       { SDMACORE }
32875 
32876 /* ----------------------------------------------------------------------------
32877    -- SDMACORE - Register accessor macros
32878    ---------------------------------------------------------------------------- */
32879 
32880 /*!
32881  * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros
32882  * @{
32883  */
32884 
32885 /* SDMACORE - Register instance definitions */
32886 /* SDMACORE */
32887 #define SDMACORE_MC0PTR                          SDMACORE_MC0PTR_REG(SDMACORE_BASE_PTR)
32888 #define SDMACORE_CCPTR                           SDMACORE_CCPTR_REG(SDMACORE_BASE_PTR)
32889 #define SDMACORE_CCR                             SDMACORE_CCR_REG(SDMACORE_BASE_PTR)
32890 #define SDMACORE_NCR                             SDMACORE_NCR_REG(SDMACORE_BASE_PTR)
32891 #define SDMACORE_EVENTS                          SDMACORE_EVENTS_REG(SDMACORE_BASE_PTR)
32892 #define SDMACORE_CCPRI                           SDMACORE_CCPRI_REG(SDMACORE_BASE_PTR)
32893 #define SDMACORE_NCPRI                           SDMACORE_NCPRI_REG(SDMACORE_BASE_PTR)
32894 #define SDMACORE_ECOUNT                          SDMACORE_ECOUNT_REG(SDMACORE_BASE_PTR)
32895 #define SDMACORE_ECTL                            SDMACORE_ECTL_REG(SDMACORE_BASE_PTR)
32896 #define SDMACORE_EAA                             SDMACORE_EAA_REG(SDMACORE_BASE_PTR)
32897 #define SDMACORE_EAB                             SDMACORE_EAB_REG(SDMACORE_BASE_PTR)
32898 #define SDMACORE_EAM                             SDMACORE_EAM_REG(SDMACORE_BASE_PTR)
32899 #define SDMACORE_ED                              SDMACORE_ED_REG(SDMACORE_BASE_PTR)
32900 #define SDMACORE_EDM                             SDMACORE_EDM_REG(SDMACORE_BASE_PTR)
32901 #define SDMACORE_RTB                             SDMACORE_RTB_REG(SDMACORE_BASE_PTR)
32902 #define SDMACORE_TB                              SDMACORE_TB_REG(SDMACORE_BASE_PTR)
32903 #define SDMACORE_OSTAT                           SDMACORE_OSTAT_REG(SDMACORE_BASE_PTR)
32904 #define SDMACORE_MCHN0ADDR                       SDMACORE_MCHN0ADDR_REG(SDMACORE_BASE_PTR)
32905 #define SDMACORE_ENDIANNESS                      SDMACORE_ENDIANNESS_REG(SDMACORE_BASE_PTR)
32906 #define SDMACORE_SDMA_LOCK                       SDMACORE_SDMA_LOCK_REG(SDMACORE_BASE_PTR)
32907 #define SDMACORE_EVENTS2                         SDMACORE_EVENTS2_REG(SDMACORE_BASE_PTR)
32908 
32909 /*!
32910  * @}
32911  */ /* end of group SDMACORE_Register_Accessor_Macros */
32912 
32913 /*!
32914  * @}
32915  */ /* end of group SDMACORE_Peripheral */
32916 
32917 /* ----------------------------------------------------------------------------
32918    -- SEMA4 Peripheral Access Layer
32919    ---------------------------------------------------------------------------- */
32920 
32921 /*!
32922  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
32923  * @{
32924  */
32925 
32926 /** SEMA4 - Register Layout Typedef */
32927 typedef struct {
32928   __IO  uint8_t  GATE00;                                 /**< Semaphores GATE 0 Register, offset: 0x0 */
32929   __IO  uint8_t  GATE01;                                 /**< Semaphores GATE 1 Register, offset: 0x1 */
32930   __IO  uint8_t  GATE02;                                 /**< Semaphores GATE 2 Register, offset: 0x2 */
32931   __IO  uint8_t  GATE03;                                 /**< Semaphores GATE 3 Register, offset: 0x3 */
32932   __IO  uint8_t  GATE04;                                 /**< Semaphores GATE 4 Register, offset: 0x4 */
32933   __IO  uint8_t  GATE05;                                 /**< Semaphores GATE 5 Register, offset: 0x5 */
32934   __IO  uint8_t  GATE06;                                 /**< Semaphores GATE 6 Register, offset: 0x6 */
32935   __IO  uint8_t  GATE07;                                 /**< Semaphores GATE 7 Register, offset: 0x7 */
32936   __IO  uint8_t  GATE08;                                 /**< Semaphores GATE 8 Register, offset: 0x8 */
32937   __IO  uint8_t  GATE09;                                 /**< Semaphores GATE 9 Register, offset: 0x9 */
32938   __IO  uint8_t  GATE10;                                 /**< Semaphores GATE 10 Register, offset: 0xA */
32939   __IO  uint8_t  GATE11;                                 /**< Semaphores GATE 11 Register, offset: 0xB */
32940   __IO  uint8_t  GATE12;                                 /**< Semaphores GATE 12 Register, offset: 0xC */
32941   __IO  uint8_t  GATE13;                                 /**< Semaphores GATE 13 Register, offset: 0xD */
32942   __IO  uint8_t  GATE14;                                 /**< Semaphores GATE 14 Register, offset: 0xE */
32943   __IO  uint8_t  GATE15;                                 /**< Semaphores GATE 15 Register, offset: 0xF */
32944   uint8_t RESERVED_0[48];
32945   struct {                                         /* offset: 0x40, array step: 0x8 */
32946     __IO  uint16_t INE;                                    /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
32947   uint8_t RESERVED_0[6];
32948   } CPnINE[2];
32949   uint8_t RESERVED_1[48];
32950   struct {                                         /* offset: 0x80, array step: 0x8 */
32951     __I   uint16_t NTF;                                    /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
32952   uint8_t RESERVED_0[6];
32953   } CPnNTF[2];
32954   uint8_t RESERVED_2[112];
32955   __IO  uint16_t RSTGT;                                  /**< Semaphores (Secure) Reset GATE n, offset: 0x100 */
32956   uint8_t RESERVED_3[2];
32957   __IO  uint16_t RSTNTF;                                 /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
32958 } SEMA4_Type, *SEMA4_MemMapPtr;
32959 
32960 /* ----------------------------------------------------------------------------
32961    -- SEMA4 - Register accessor macros
32962    ---------------------------------------------------------------------------- */
32963 
32964 /*!
32965  * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros
32966  * @{
32967  */
32968 
32969 /* SEMA4 - Register accessors */
32970 #define SEMA4_GATE00_REG(base)                   ((base)->GATE00)
32971 #define SEMA4_GATE01_REG(base)                   ((base)->GATE01)
32972 #define SEMA4_GATE02_REG(base)                   ((base)->GATE02)
32973 #define SEMA4_GATE03_REG(base)                   ((base)->GATE03)
32974 #define SEMA4_GATE04_REG(base)                   ((base)->GATE04)
32975 #define SEMA4_GATE05_REG(base)                   ((base)->GATE05)
32976 #define SEMA4_GATE06_REG(base)                   ((base)->GATE06)
32977 #define SEMA4_GATE07_REG(base)                   ((base)->GATE07)
32978 #define SEMA4_GATE08_REG(base)                   ((base)->GATE08)
32979 #define SEMA4_GATE09_REG(base)                   ((base)->GATE09)
32980 #define SEMA4_GATE10_REG(base)                   ((base)->GATE10)
32981 #define SEMA4_GATE11_REG(base)                   ((base)->GATE11)
32982 #define SEMA4_GATE12_REG(base)                   ((base)->GATE12)
32983 #define SEMA4_GATE13_REG(base)                   ((base)->GATE13)
32984 #define SEMA4_GATE14_REG(base)                   ((base)->GATE14)
32985 #define SEMA4_GATE15_REG(base)                   ((base)->GATE15)
32986 #define SEMA4_CPINE_REG(base,index)              ((base)->CPnINE[index].INE)
32987 #define SEMA4_CPNTF_REG(base,index)              ((base)->CPnNTF[index].NTF)
32988 #define SEMA4_RSTGT_REG(base)                    ((base)->RSTGT)
32989 #define SEMA4_RSTNTF_REG(base)                   ((base)->RSTNTF)
32990 
32991 /*!
32992  * @}
32993  */ /* end of group SEMA4_Register_Accessor_Macros */
32994 
32995 /* ----------------------------------------------------------------------------
32996    -- SEMA4 Register Masks
32997    ---------------------------------------------------------------------------- */
32998 
32999 /*!
33000  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
33001  * @{
33002  */
33003 
33004 /* GATE00 Bit Fields */
33005 #define SEMA4_GATE00_GTFSM_MASK                  0x3u
33006 #define SEMA4_GATE00_GTFSM_SHIFT                 0
33007 #define SEMA4_GATE00_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE00_GTFSM_SHIFT))&SEMA4_GATE00_GTFSM_MASK)
33008 /* GATE01 Bit Fields */
33009 #define SEMA4_GATE01_GTFSM_MASK                  0x3u
33010 #define SEMA4_GATE01_GTFSM_SHIFT                 0
33011 #define SEMA4_GATE01_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK)
33012 /* GATE02 Bit Fields */
33013 #define SEMA4_GATE02_GTFSM_MASK                  0x3u
33014 #define SEMA4_GATE02_GTFSM_SHIFT                 0
33015 #define SEMA4_GATE02_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK)
33016 /* GATE03 Bit Fields */
33017 #define SEMA4_GATE03_GTFSM_MASK                  0x3u
33018 #define SEMA4_GATE03_GTFSM_SHIFT                 0
33019 #define SEMA4_GATE03_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK)
33020 /* GATE04 Bit Fields */
33021 #define SEMA4_GATE04_GTFSM_MASK                  0x3u
33022 #define SEMA4_GATE04_GTFSM_SHIFT                 0
33023 #define SEMA4_GATE04_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE04_GTFSM_SHIFT))&SEMA4_GATE04_GTFSM_MASK)
33024 /* GATE05 Bit Fields */
33025 #define SEMA4_GATE05_GTFSM_MASK                  0x3u
33026 #define SEMA4_GATE05_GTFSM_SHIFT                 0
33027 #define SEMA4_GATE05_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK)
33028 /* GATE06 Bit Fields */
33029 #define SEMA4_GATE06_GTFSM_MASK                  0x3u
33030 #define SEMA4_GATE06_GTFSM_SHIFT                 0
33031 #define SEMA4_GATE06_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK)
33032 /* GATE07 Bit Fields */
33033 #define SEMA4_GATE07_GTFSM_MASK                  0x3u
33034 #define SEMA4_GATE07_GTFSM_SHIFT                 0
33035 #define SEMA4_GATE07_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK)
33036 /* GATE08 Bit Fields */
33037 #define SEMA4_GATE08_GTFSM_MASK                  0x3u
33038 #define SEMA4_GATE08_GTFSM_SHIFT                 0
33039 #define SEMA4_GATE08_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE08_GTFSM_SHIFT))&SEMA4_GATE08_GTFSM_MASK)
33040 /* GATE09 Bit Fields */
33041 #define SEMA4_GATE09_GTFSM_MASK                  0x3u
33042 #define SEMA4_GATE09_GTFSM_SHIFT                 0
33043 #define SEMA4_GATE09_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK)
33044 /* GATE10 Bit Fields */
33045 #define SEMA4_GATE10_GTFSM_MASK                  0x3u
33046 #define SEMA4_GATE10_GTFSM_SHIFT                 0
33047 #define SEMA4_GATE10_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK)
33048 /* GATE11 Bit Fields */
33049 #define SEMA4_GATE11_GTFSM_MASK                  0x3u
33050 #define SEMA4_GATE11_GTFSM_SHIFT                 0
33051 #define SEMA4_GATE11_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK)
33052 /* GATE12 Bit Fields */
33053 #define SEMA4_GATE12_GTFSM_MASK                  0x3u
33054 #define SEMA4_GATE12_GTFSM_SHIFT                 0
33055 #define SEMA4_GATE12_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE12_GTFSM_SHIFT))&SEMA4_GATE12_GTFSM_MASK)
33056 /* GATE13 Bit Fields */
33057 #define SEMA4_GATE13_GTFSM_MASK                  0x3u
33058 #define SEMA4_GATE13_GTFSM_SHIFT                 0
33059 #define SEMA4_GATE13_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK)
33060 /* GATE14 Bit Fields */
33061 #define SEMA4_GATE14_GTFSM_MASK                  0x3u
33062 #define SEMA4_GATE14_GTFSM_SHIFT                 0
33063 #define SEMA4_GATE14_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK)
33064 /* GATE15 Bit Fields */
33065 #define SEMA4_GATE15_GTFSM_MASK                  0x3u
33066 #define SEMA4_GATE15_GTFSM_SHIFT                 0
33067 #define SEMA4_GATE15_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK)
33068 /* CPINE Bit Fields */
33069 #define SEMA4_CPINE_INE7_MASK                    0x1u
33070 #define SEMA4_CPINE_INE7_SHIFT                   0
33071 #define SEMA4_CPINE_INE6_MASK                    0x2u
33072 #define SEMA4_CPINE_INE6_SHIFT                   1
33073 #define SEMA4_CPINE_INE5_MASK                    0x4u
33074 #define SEMA4_CPINE_INE5_SHIFT                   2
33075 #define SEMA4_CPINE_INE4_MASK                    0x8u
33076 #define SEMA4_CPINE_INE4_SHIFT                   3
33077 #define SEMA4_CPINE_INE3_MASK                    0x10u
33078 #define SEMA4_CPINE_INE3_SHIFT                   4
33079 #define SEMA4_CPINE_INE2_MASK                    0x20u
33080 #define SEMA4_CPINE_INE2_SHIFT                   5
33081 #define SEMA4_CPINE_INE1_MASK                    0x40u
33082 #define SEMA4_CPINE_INE1_SHIFT                   6
33083 #define SEMA4_CPINE_INE0_MASK                    0x80u
33084 #define SEMA4_CPINE_INE0_SHIFT                   7
33085 #define SEMA4_CPINE_INE15_MASK                   0x100u
33086 #define SEMA4_CPINE_INE15_SHIFT                  8
33087 #define SEMA4_CPINE_INE14_MASK                   0x200u
33088 #define SEMA4_CPINE_INE14_SHIFT                  9
33089 #define SEMA4_CPINE_INE13_MASK                   0x400u
33090 #define SEMA4_CPINE_INE13_SHIFT                  10
33091 #define SEMA4_CPINE_INE12_MASK                   0x800u
33092 #define SEMA4_CPINE_INE12_SHIFT                  11
33093 #define SEMA4_CPINE_INE11_MASK                   0x1000u
33094 #define SEMA4_CPINE_INE11_SHIFT                  12
33095 #define SEMA4_CPINE_INE10_MASK                   0x2000u
33096 #define SEMA4_CPINE_INE10_SHIFT                  13
33097 #define SEMA4_CPINE_INE9_MASK                    0x4000u
33098 #define SEMA4_CPINE_INE9_SHIFT                   14
33099 #define SEMA4_CPINE_INE8_MASK                    0x8000u
33100 #define SEMA4_CPINE_INE8_SHIFT                   15
33101 /* CPNTF Bit Fields */
33102 #define SEMA4_CPNTF_GN7_MASK                     0x1u
33103 #define SEMA4_CPNTF_GN7_SHIFT                    0
33104 #define SEMA4_CPNTF_GN6_MASK                     0x2u
33105 #define SEMA4_CPNTF_GN6_SHIFT                    1
33106 #define SEMA4_CPNTF_GN5_MASK                     0x4u
33107 #define SEMA4_CPNTF_GN5_SHIFT                    2
33108 #define SEMA4_CPNTF_GN4_MASK                     0x8u
33109 #define SEMA4_CPNTF_GN4_SHIFT                    3
33110 #define SEMA4_CPNTF_GN3_MASK                     0x10u
33111 #define SEMA4_CPNTF_GN3_SHIFT                    4
33112 #define SEMA4_CPNTF_GN2_MASK                     0x20u
33113 #define SEMA4_CPNTF_GN2_SHIFT                    5
33114 #define SEMA4_CPNTF_GN1_MASK                     0x40u
33115 #define SEMA4_CPNTF_GN1_SHIFT                    6
33116 #define SEMA4_CPNTF_GN0_MASK                     0x80u
33117 #define SEMA4_CPNTF_GN0_SHIFT                    7
33118 #define SEMA4_CPNTF_GN15_MASK                    0x100u
33119 #define SEMA4_CPNTF_GN15_SHIFT                   8
33120 #define SEMA4_CPNTF_GN14_MASK                    0x200u
33121 #define SEMA4_CPNTF_GN14_SHIFT                   9
33122 #define SEMA4_CPNTF_GN13_MASK                    0x400u
33123 #define SEMA4_CPNTF_GN13_SHIFT                   10
33124 #define SEMA4_CPNTF_GN12_MASK                    0x800u
33125 #define SEMA4_CPNTF_GN12_SHIFT                   11
33126 #define SEMA4_CPNTF_GN11_MASK                    0x1000u
33127 #define SEMA4_CPNTF_GN11_SHIFT                   12
33128 #define SEMA4_CPNTF_GN10_MASK                    0x2000u
33129 #define SEMA4_CPNTF_GN10_SHIFT                   13
33130 #define SEMA4_CPNTF_GN9_MASK                     0x4000u
33131 #define SEMA4_CPNTF_GN9_SHIFT                    14
33132 #define SEMA4_CPNTF_GN8_MASK                     0x8000u
33133 #define SEMA4_CPNTF_GN8_SHIFT                    15
33134 /* RSTGT Bit Fields */
33135 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    0xFFu
33136 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   0
33137 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT))&SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
33138 #define SEMA4_RSTGT_RSTGTN_MASK                  0xFF00u
33139 #define SEMA4_RSTGT_RSTGTN_SHIFT                 8
33140 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGTN_SHIFT))&SEMA4_RSTGT_RSTGTN_MASK)
33141 /* RSTNTF Bit Fields */
33142 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   0xFFu
33143 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  0
33144 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT))&SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
33145 #define SEMA4_RSTNTF_RSTNTN_MASK                 0xFF00u
33146 #define SEMA4_RSTNTF_RSTNTN_SHIFT                8
33147 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNTN_SHIFT))&SEMA4_RSTNTF_RSTNTN_MASK)
33148 
33149 /*!
33150  * @}
33151  */ /* end of group SEMA4_Register_Masks */
33152 
33153 /* SEMA4 - Peripheral instance base addresses */
33154 /** Peripheral SEMA4 base address */
33155 #define SEMA4_BASE                               (0x42290000u)
33156 /** Peripheral SEMA4 base pointer */
33157 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
33158 #define SEMA4_BASE_PTR                           (SEMA4)
33159 /** Array initializer of SEMA4 peripheral base addresses */
33160 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
33161 /** Array initializer of SEMA4 peripheral base pointers */
33162 #define SEMA4_BASE_PTRS                          { SEMA4 }
33163 /** Interrupt vectors for the SEMA4 peripheral type */
33164 #define SEMA4_IRQS                               { SEMA4_CP1_IRQn }
33165 
33166 /* ----------------------------------------------------------------------------
33167    -- SEMA4 - Register accessor macros
33168    ---------------------------------------------------------------------------- */
33169 
33170 /*!
33171  * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros
33172  * @{
33173  */
33174 
33175 /* SEMA4 - Register instance definitions */
33176 /* SEMA4 */
33177 #define SEMA4_GATE00                             SEMA4_GATE00_REG(SEMA4_BASE_PTR)
33178 #define SEMA4_GATE01                             SEMA4_GATE01_REG(SEMA4_BASE_PTR)
33179 #define SEMA4_GATE02                             SEMA4_GATE02_REG(SEMA4_BASE_PTR)
33180 #define SEMA4_GATE03                             SEMA4_GATE03_REG(SEMA4_BASE_PTR)
33181 #define SEMA4_GATE04                             SEMA4_GATE04_REG(SEMA4_BASE_PTR)
33182 #define SEMA4_GATE05                             SEMA4_GATE05_REG(SEMA4_BASE_PTR)
33183 #define SEMA4_GATE06                             SEMA4_GATE06_REG(SEMA4_BASE_PTR)
33184 #define SEMA4_GATE07                             SEMA4_GATE07_REG(SEMA4_BASE_PTR)
33185 #define SEMA4_GATE08                             SEMA4_GATE08_REG(SEMA4_BASE_PTR)
33186 #define SEMA4_GATE09                             SEMA4_GATE09_REG(SEMA4_BASE_PTR)
33187 #define SEMA4_GATE10                             SEMA4_GATE10_REG(SEMA4_BASE_PTR)
33188 #define SEMA4_GATE11                             SEMA4_GATE11_REG(SEMA4_BASE_PTR)
33189 #define SEMA4_GATE12                             SEMA4_GATE12_REG(SEMA4_BASE_PTR)
33190 #define SEMA4_GATE13                             SEMA4_GATE13_REG(SEMA4_BASE_PTR)
33191 #define SEMA4_GATE14                             SEMA4_GATE14_REG(SEMA4_BASE_PTR)
33192 #define SEMA4_GATE15                             SEMA4_GATE15_REG(SEMA4_BASE_PTR)
33193 #define SEMA4_CP0INE                             SEMA4_CPINE_REG(SEMA4_BASE_PTR,0)
33194 #define SEMA4_CP1INE                             SEMA4_CPINE_REG(SEMA4_BASE_PTR,1)
33195 #define SEMA4_CP0NTF                             SEMA4_CPNTF_REG(SEMA4_BASE_PTR,0)
33196 #define SEMA4_CP1NTF                             SEMA4_CPNTF_REG(SEMA4_BASE_PTR,1)
33197 #define SEMA4_RSTGT                              SEMA4_RSTGT_REG(SEMA4_BASE_PTR)
33198 #define SEMA4_RSTNTF                             SEMA4_RSTNTF_REG(SEMA4_BASE_PTR)
33199 /* SEMA4 - Register array accessors */
33200 #define SEMA4_CPINE(index)                       SEMA4_CPINE_REG(SEMA4_BASE_PTR,index)
33201 #define SEMA4_CPNTF(index)                       SEMA4_CPNTF_REG(SEMA4_BASE_PTR,index)
33202 
33203 /*!
33204  * @}
33205  */ /* end of group SEMA4_Register_Accessor_Macros */
33206 
33207 /*!
33208  * @}
33209  */ /* end of group SEMA4_Peripheral */
33210 
33211 /* ----------------------------------------------------------------------------
33212    -- SJC Peripheral Access Layer
33213    ---------------------------------------------------------------------------- */
33214 
33215 /*!
33216  * @addtogroup SJC_Peripheral_Access_Layer SJC Peripheral Access Layer
33217  * @{
33218  */
33219 
33220 /** SJC - Register Layout Typedef */
33221 typedef struct {
33222   union {                                          /* offset: 0x0 */
33223   __I     uint32_t GPUSR1;                                      /**< General Purpose Unsecured Status Register 1,offset: 0x0 */
33224   struct {                                         /* offset: 0x1 */
33225       uint8_t RESERVED_0[1];
33226   __I     uint32_t GPUSR2;                                      /**< General Purpose Unsecured Status Register 2,offset: 0x1 */
33227     } GPUSR2;
33228   struct {                                         /* offset: 0x2 */
33229       uint8_t RESERVED_0[2];
33230   __I     uint32_t GPUSR3;                                      /**< General Purpose Unsecured Status Register 3,offset: 0x2 */
33231     } GPUSR3;
33232   struct {                                         /* offset: 0x3 */
33233       uint8_t RESERVED_0[3];
33234   __I     uint32_t GPSSR;                                       /**< General Purpose Secured Status Register,offset: 0x3 */
33235     } GPSSR;
33236   struct {                                         /* offset: 0x4 */
33237       uint8_t RESERVED_0[4];
33238   __IO    uint32_t DCR;                                         /**< Debug Control Register,offset: 0x4 */
33239     } DCR;
33240   struct {                                         /* offset: 0x5 */
33241       uint8_t RESERVED_0[5];
33242   __I     uint32_t SSR;                                         /**< Security Status Register,offset: 0x5 */
33243     } SSR;
33244   struct {                                         /* offset: 0x7 */
33245       uint8_t RESERVED_0[7];
33246   __IO    uint32_t GPCCR;                                       /**< General Purpose Clocks Control Register,offset: 0x7 */
33247     } GPCCR;
33248   };
33249 } SJC_Type, *SJC_MemMapPtr;
33250 
33251 /* ----------------------------------------------------------------------------
33252    -- SJC - Register accessor macros
33253    ---------------------------------------------------------------------------- */
33254 
33255 /*!
33256  * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros
33257  * @{
33258  */
33259 
33260 /* SJC - Register accessors */
33261 #define SJC_GPUSR1_REG(base)                     ((base)->GPUSR1)
33262 #define SJC_GPUSR2_REG(base)                     ((base)->GPUSR2.GPUSR2)
33263 #define SJC_GPUSR3_REG(base)                     ((base)->GPUSR3.GPUSR3)
33264 #define SJC_GPSSR_REG(base)                      ((base)->GPSSR.GPSSR)
33265 #define SJC_DCR_REG(base)                        ((base)->DCR.DCR)
33266 #define SJC_SSR_REG(base)                        ((base)->SSR.SSR)
33267 #define SJC_GPCCR_REG(base)                      ((base)->GPCCR.GPCCR)
33268 
33269 /*!
33270  * @}
33271  */ /* end of group SJC_Register_Accessor_Macros */
33272 
33273  /* ----------------------------------------------------------------------------
33274    -- SJC Register Masks
33275    ---------------------------------------------------------------------------- */
33276 
33277 /*!
33278  * @addtogroup SJC_Register_Masks SJC Register Masks
33279  * @{
33280  */
33281 
33282 /* GPUSR1 Bit Fields */
33283 #define SJC_GPUSR1_A_DBG_MASK                    0x1u
33284 #define SJC_GPUSR1_A_DBG_SHIFT                   0
33285 #define SJC_GPUSR1_A_WFI_MASK                    0x2u
33286 #define SJC_GPUSR1_A_WFI_SHIFT                   1
33287 #define SJC_GPUSR1_S_STAT_MASK                   0x1Cu
33288 #define SJC_GPUSR1_S_STAT_SHIFT                  2
33289 #define SJC_GPUSR1_S_STAT(x)                     (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR1_S_STAT_SHIFT))&SJC_GPUSR1_S_STAT_MASK)
33290 #define SJC_GPUSR1_PLL_LOCK_MASK                 0x100u
33291 #define SJC_GPUSR1_PLL_LOCK_SHIFT                8
33292 /* GPUSR2 Bit Fields */
33293 #define SJC_GPUSR2_STBYWFI_MASK                  0xFu
33294 #define SJC_GPUSR2_STBYWFI_SHIFT                 0
33295 #define SJC_GPUSR2_STBYWFI(x)                    (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFI_SHIFT))&SJC_GPUSR2_STBYWFI_MASK)
33296 #define SJC_GPUSR2_S_STAT_MASK                   0xF0u
33297 #define SJC_GPUSR2_S_STAT_SHIFT                  4
33298 #define SJC_GPUSR2_S_STAT(x)                     (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_S_STAT_SHIFT))&SJC_GPUSR2_S_STAT_MASK)
33299 #define SJC_GPUSR2_STBYWFE_MASK                  0xF00u
33300 #define SJC_GPUSR2_STBYWFE_SHIFT                 8
33301 #define SJC_GPUSR2_STBYWFE(x)                    (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFE_SHIFT))&SJC_GPUSR2_STBYWFE_MASK)
33302 /* GPUSR3 Bit Fields */
33303 #define SJC_GPUSR3_IPG_WAIT_MASK                 0x1u
33304 #define SJC_GPUSR3_IPG_WAIT_SHIFT                0
33305 #define SJC_GPUSR3_IPG_STOP_MASK                 0x2u
33306 #define SJC_GPUSR3_IPG_STOP_SHIFT                1
33307 #define SJC_GPUSR3_SYS_WAIT_MASK                 0x4u
33308 #define SJC_GPUSR3_SYS_WAIT_SHIFT                2
33309 /* GPSSR Bit Fields */
33310 #define SJC_GPSSR_GPSSR_MASK                     0xFFFFFFFFu
33311 #define SJC_GPSSR_GPSSR_SHIFT                    0
33312 #define SJC_GPSSR_GPSSR(x)                       (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK)
33313 /* DCR Bit Fields */
33314 #define SJC_DCR_DE_TO_ARM_MASK                   0x1u
33315 #define SJC_DCR_DE_TO_ARM_SHIFT                  0
33316 #define SJC_DCR_DE_TO_SDMA_MASK                  0x2u
33317 #define SJC_DCR_DE_TO_SDMA_SHIFT                 1
33318 #define SJC_DCR_DEBUG_OBS_MASK                   0x8u
33319 #define SJC_DCR_DEBUG_OBS_SHIFT                  3
33320 #define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK          0x20u
33321 #define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT         5
33322 #define SJC_DCR_DIRECT_ARM_REQ_EN_MASK           0x40u
33323 #define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT          6
33324 /* SSR Bit Fields */
33325 #define SJC_SSR_KTF_MASK                         0x1u
33326 #define SJC_SSR_KTF_SHIFT                        0
33327 #define SJC_SSR_KTA_MASK                         0x2u
33328 #define SJC_SSR_KTA_SHIFT                        1
33329 #define SJC_SSR_SWF_MASK                         0x4u
33330 #define SJC_SSR_SWF_SHIFT                        2
33331 #define SJC_SSR_SWE_MASK                         0x8u
33332 #define SJC_SSR_SWE_SHIFT                        3
33333 #define SJC_SSR_EBF_MASK                         0x10u
33334 #define SJC_SSR_EBF_SHIFT                        4
33335 #define SJC_SSR_EBG_MASK                         0x20u
33336 #define SJC_SSR_EBG_SHIFT                        5
33337 #define SJC_SSR_FT_MASK                          0x100u
33338 #define SJC_SSR_FT_SHIFT                         8
33339 #define SJC_SSR_SJM_MASK                         0x600u
33340 #define SJC_SSR_SJM_SHIFT                        9
33341 #define SJC_SSR_SJM(x)                           (((uint32_t)(((uint32_t)(x))<<SJC_SSR_SJM_SHIFT))&SJC_SSR_SJM_MASK)
33342 #define SJC_SSR_RSSTAT_MASK                      0x1800u
33343 #define SJC_SSR_RSSTAT_SHIFT                     11
33344 #define SJC_SSR_RSSTAT(x)                        (((uint32_t)(((uint32_t)(x))<<SJC_SSR_RSSTAT_SHIFT))&SJC_SSR_RSSTAT_MASK)
33345 #define SJC_SSR_BOOTIND_MASK                     0x4000u
33346 #define SJC_SSR_BOOTIND_SHIFT                    14
33347 /* GPCCR Bit Fields */
33348 #define SJC_GPCCR_SCLKR_MASK                     0x1u
33349 #define SJC_GPCCR_SCLKR_SHIFT                    0
33350 #define SJC_GPCCR_ACLKOFFDIS_MASK                0x2u
33351 #define SJC_GPCCR_ACLKOFFDIS_SHIFT               1
33352 
33353 /*!
33354  * @}
33355  */ /* end of group SJC_Register_Masks */
33356 
33357 /* SJC - Peripheral instance base addresses */
33358 /** Peripheral SJC base address */
33359 #define SJC_BASE                                 (0x40u)
33360 /** Peripheral SJC base pointer */
33361 #define SJC                                      ((SJC_Type *)SJC_BASE)
33362 #define SJC_BASE_PTR                             (SJC)
33363 /** Array initializer of SJC peripheral base addresses */
33364 #define SJC_BASE_ADDRS                           { SJC_BASE }
33365 /** Array initializer of SJC peripheral base pointers */
33366 #define SJC_BASE_PTRS                            { SJC }
33367 /** Interrupt vectors for the SJC peripheral type */
33368 #define SJC_IRQS                                 { SJC_IRQn }
33369 
33370 /* ----------------------------------------------------------------------------
33371    -- SJC - Register accessor macros
33372    ---------------------------------------------------------------------------- */
33373 
33374 /*!
33375  * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros
33376  * @{
33377  */
33378 
33379 /* SJC - Register instance definitions */
33380 /* SJC */
33381 #define SJC_GPUSR1                               SJC_GPUSR1_REG(SJC_BASE_PTR)
33382 #define SJC_GPUSR2                               SJC_GPUSR2_REG(SJC_BASE_PTR)
33383 #define SJC_GPUSR3                               SJC_GPUSR3_REG(SJC_BASE_PTR)
33384 #define SJC_GPSSR                                SJC_GPSSR_REG(SJC_BASE_PTR)
33385 #define SJC_DCR                                  SJC_DCR_REG(SJC_BASE_PTR)
33386 #define SJC_SSR                                  SJC_SSR_REG(SJC_BASE_PTR)
33387 #define SJC_GPCCR                                SJC_GPCCR_REG(SJC_BASE_PTR)
33388 
33389 /*!
33390  * @}
33391  */ /* end of group SJC_Register_Accessor_Macros */
33392 
33393 /*!
33394  * @}
33395  */ /* end of group SJC_Peripheral */
33396 
33397 /* ----------------------------------------------------------------------------
33398    -- SNVS Peripheral Access Layer
33399    ---------------------------------------------------------------------------- */
33400 
33401 /*!
33402  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
33403  * @{
33404  */
33405 
33406 /** SNVS - Register Layout Typedef */
33407 typedef struct {
33408   __IO  uint32_t HPLR;                                   /**<  , offset: 0x0 */
33409   __IO  uint32_t HPCOMR;                                 /**<  , offset: 0x4 */
33410   __IO  uint32_t HPCR;                                   /**<  , offset: 0x8 */
33411   uint8_t RESERVED_0[8];
33412   __IO  uint32_t HPSR;                                   /**<  , offset: 0x14 */
33413   uint8_t RESERVED_1[12];
33414   __IO  uint32_t HPRTCMR;                                /**<  , offset: 0x24 */
33415   __IO  uint32_t HPRTCLR;                                /**<  , offset: 0x28 */
33416   __IO  uint32_t HPTAMR;                                 /**<  , offset: 0x2C */
33417   __IO  uint32_t HPTALR;                                 /**<  , offset: 0x30 */
33418   __IO  uint32_t LPLR;                                   /**<  , offset: 0x34 */
33419   __IO  uint32_t LPCR;                                   /**<  , offset: 0x38 */
33420   uint8_t RESERVED_2[16];
33421   __IO  uint32_t LPSR;                                   /**<  , offset: 0x4C */
33422   uint8_t RESERVED_3[12];
33423   __IO  uint32_t LPSMCMR;                                /**<  , offset: 0x5C */
33424   __IO  uint32_t LPSMCLR;                                /**<  , offset: 0x60 */
33425   uint8_t RESERVED_4[4];
33426   __IO  uint32_t LPGPR;                                  /**<  , offset: 0x68 */
33427   uint8_t RESERVED_5[2956];
33428   __I   uint32_t HPVIDR1;                                /**<  , offset: 0xBF8 */
33429   __I   uint32_t HPVIDR2;                                /**<  , offset: 0xBFC */
33430 } SNVS_Type, *SNVS_MemMapPtr;
33431 
33432 /* ----------------------------------------------------------------------------
33433    -- SNVS - Register accessor macros
33434    ---------------------------------------------------------------------------- */
33435 
33436 /*!
33437  * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros
33438  * @{
33439  */
33440 
33441 /* SNVS - Register accessors */
33442 #define SNVS_HPLR_REG(base)                      ((base)->HPLR)
33443 #define SNVS_HPCOMR_REG(base)                    ((base)->HPCOMR)
33444 #define SNVS_HPCR_REG(base)                      ((base)->HPCR)
33445 #define SNVS_HPSR_REG(base)                      ((base)->HPSR)
33446 #define SNVS_HPRTCMR_REG(base)                   ((base)->HPRTCMR)
33447 #define SNVS_HPRTCLR_REG(base)                   ((base)->HPRTCLR)
33448 #define SNVS_HPTAMR_REG(base)                    ((base)->HPTAMR)
33449 #define SNVS_HPTALR_REG(base)                    ((base)->HPTALR)
33450 #define SNVS_LPLR_REG(base)                      ((base)->LPLR)
33451 #define SNVS_LPCR_REG(base)                      ((base)->LPCR)
33452 #define SNVS_LPSR_REG(base)                      ((base)->LPSR)
33453 #define SNVS_LPSMCMR_REG(base)                   ((base)->LPSMCMR)
33454 #define SNVS_LPSMCLR_REG(base)                   ((base)->LPSMCLR)
33455 #define SNVS_LPGPR_REG(base)                     ((base)->LPGPR)
33456 #define SNVS_HPVIDR1_REG(base)                   ((base)->HPVIDR1)
33457 #define SNVS_HPVIDR2_REG(base)                   ((base)->HPVIDR2)
33458 
33459 /*!
33460  * @}
33461  */ /* end of group SNVS_Register_Accessor_Macros */
33462 
33463 /* ----------------------------------------------------------------------------
33464    -- SNVS Register Masks
33465    ---------------------------------------------------------------------------- */
33466 
33467 /*!
33468  * @addtogroup SNVS_Register_Masks SNVS Register Masks
33469  * @{
33470  */
33471 
33472 /* HPLR Bit Fields */
33473 #define SNVS_HPLR_MC_SL_MASK                     0x10u
33474 #define SNVS_HPLR_MC_SL_SHIFT                    4
33475 #define SNVS_HPLR_GPR_SL_MASK                    0x20u
33476 #define SNVS_HPLR_GPR_SL_SHIFT                   5
33477 /* HPCOMR Bit Fields */
33478 #define SNVS_HPCOMR_LP_SWR_MASK                  0x10u
33479 #define SNVS_HPCOMR_LP_SWR_SHIFT                 4
33480 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              0x20u
33481 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             5
33482 #define SNVS_HPCOMR_NPSWA_EN_MASK                0x80000000u
33483 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               31
33484 /* HPCR Bit Fields */
33485 #define SNVS_HPCR_RTC_EN_MASK                    0x1u
33486 #define SNVS_HPCR_RTC_EN_SHIFT                   0
33487 #define SNVS_HPCR_HPTA_EN_MASK                   0x2u
33488 #define SNVS_HPCR_HPTA_EN_SHIFT                  1
33489 #define SNVS_HPCR_PI_EN_MASK                     0x8u
33490 #define SNVS_HPCR_PI_EN_SHIFT                    3
33491 #define SNVS_HPCR_PI_FREQ_MASK                   0xF0u
33492 #define SNVS_HPCR_PI_FREQ_SHIFT                  4
33493 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_PI_FREQ_SHIFT))&SNVS_HPCR_PI_FREQ_MASK)
33494 #define SNVS_HPCR_HPCALB_EN_MASK                 0x100u
33495 #define SNVS_HPCR_HPCALB_EN_SHIFT                8
33496 #define SNVS_HPCR_HPCALB_VAL_MASK                0x7C00u
33497 #define SNVS_HPCR_HPCALB_VAL_SHIFT               10
33498 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_HPCALB_VAL_SHIFT))&SNVS_HPCR_HPCALB_VAL_MASK)
33499 #define SNVS_HPCR_BTN_CONFIG_MASK                0x7000000u
33500 #define SNVS_HPCR_BTN_CONFIG_SHIFT               24
33501 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_BTN_CONFIG_SHIFT))&SNVS_HPCR_BTN_CONFIG_MASK)
33502 #define SNVS_HPCR_BTN_MASK_MASK                  0x8000000u
33503 #define SNVS_HPCR_BTN_MASK_SHIFT                 27
33504 /* HPSR Bit Fields */
33505 #define SNVS_HPSR_BTN_MASK                       0x40u
33506 #define SNVS_HPSR_BTN_SHIFT                      6
33507 #define SNVS_HPSR_BI_MASK                        0x80u
33508 #define SNVS_HPSR_BI_SHIFT                       7
33509 /* HPRTCMR Bit Fields */
33510 #define SNVS_HPRTCMR_RTC_MASK                    0xFFFFFFFFu
33511 #define SNVS_HPRTCMR_RTC_SHIFT                   0
33512 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCMR_RTC_SHIFT))&SNVS_HPRTCMR_RTC_MASK)
33513 /* HPRTCLR Bit Fields */
33514 #define SNVS_HPRTCLR_RTC_MASK                    0xFFFFFFFFu
33515 #define SNVS_HPRTCLR_RTC_SHIFT                   0
33516 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCLR_RTC_SHIFT))&SNVS_HPRTCLR_RTC_MASK)
33517 /* HPTAMR Bit Fields */
33518 #define SNVS_HPTAMR_HPTA_MASK                    0x7FFFu
33519 #define SNVS_HPTAMR_HPTA_SHIFT                   0
33520 #define SNVS_HPTAMR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTAMR_HPTA_SHIFT))&SNVS_HPTAMR_HPTA_MASK)
33521 /* HPTALR Bit Fields */
33522 #define SNVS_HPTALR_HPTA_MASK                    0xFFFFFFFFu
33523 #define SNVS_HPTALR_HPTA_SHIFT                   0
33524 #define SNVS_HPTALR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTALR_HPTA_SHIFT))&SNVS_HPTALR_HPTA_MASK)
33525 /* LPLR Bit Fields */
33526 #define SNVS_LPLR_MC_HL_MASK                     0x10u
33527 #define SNVS_LPLR_MC_HL_SHIFT                    4
33528 #define SNVS_LPLR_GPR_HL_MASK                    0x20u
33529 #define SNVS_LPLR_GPR_HL_SHIFT                   5
33530 /* LPCR Bit Fields */
33531 #define SNVS_LPCR_MC_ENV_MASK                    0x4u
33532 #define SNVS_LPCR_MC_ENV_SHIFT                   2
33533 #define SNVS_LPCR_DP_EN_MASK                     0x20u
33534 #define SNVS_LPCR_DP_EN_SHIFT                    5
33535 #define SNVS_LPCR_TOP_MASK                       0x40u
33536 #define SNVS_LPCR_TOP_SHIFT                      6
33537 #define SNVS_LPCR_PWR_GLITCH_EN_MASK             0x80u
33538 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT            7
33539 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            0x30000u
33540 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           16
33541 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_BTN_PRESS_TIME_SHIFT))&SNVS_LPCR_BTN_PRESS_TIME_MASK)
33542 #define SNVS_LPCR_DEBOUNCE_MASK                  0xC0000u
33543 #define SNVS_LPCR_DEBOUNCE_SHIFT                 18
33544 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_DEBOUNCE_SHIFT))&SNVS_LPCR_DEBOUNCE_MASK)
33545 #define SNVS_LPCR_ON_TIME_MASK                   0x300000u
33546 #define SNVS_LPCR_ON_TIME_SHIFT                  20
33547 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_ON_TIME_SHIFT))&SNVS_LPCR_ON_TIME_MASK)
33548 #define SNVS_LPCR_PK_EN_MASK                     0x400000u
33549 #define SNVS_LPCR_PK_EN_SHIFT                    22
33550 #define SNVS_LPCR_PK_OVERRIDE_MASK               0x800000u
33551 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              23
33552 /* LPSR Bit Fields */
33553 #define SNVS_LPSR_MCR_MASK                       0x4u
33554 #define SNVS_LPSR_MCR_SHIFT                      2
33555 #define SNVS_LPSR_EO_MASK                        0x20000u
33556 #define SNVS_LPSR_EO_SHIFT                       17
33557 #define SNVS_LPSR_SPO_MASK                       0x40000u
33558 #define SNVS_LPSR_SPO_SHIFT                      18
33559 /* LPSMCMR Bit Fields */
33560 #define SNVS_LPSMCMR_MON_COUNTER_MASK            0xFFFFu
33561 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           0
33562 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MON_COUNTER_SHIFT))&SNVS_LPSMCMR_MON_COUNTER_MASK)
33563 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            0xFFFF0000u
33564 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           16
33565 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MC_ERA_BITS_SHIFT))&SNVS_LPSMCMR_MC_ERA_BITS_MASK)
33566 /* LPSMCLR Bit Fields */
33567 #define SNVS_LPSMCLR_MON_COUNTER_MASK            0xFFFFFFFFu
33568 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           0
33569 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCLR_MON_COUNTER_SHIFT))&SNVS_LPSMCLR_MON_COUNTER_MASK)
33570 /* LPGPR Bit Fields */
33571 #define SNVS_LPGPR_GPR_MASK                      0xFFFFFFFFu
33572 #define SNVS_LPGPR_GPR_SHIFT                     0
33573 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x))<<SNVS_LPGPR_GPR_SHIFT))&SNVS_LPGPR_GPR_MASK)
33574 /* HPVIDR1 Bit Fields */
33575 #define SNVS_HPVIDR1_MINOR_REV_MASK              0xFFu
33576 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             0
33577 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MINOR_REV_SHIFT))&SNVS_HPVIDR1_MINOR_REV_MASK)
33578 #define SNVS_HPVIDR1_MAJOR_REV_MASK              0xFF00u
33579 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             8
33580 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MAJOR_REV_SHIFT))&SNVS_HPVIDR1_MAJOR_REV_MASK)
33581 #define SNVS_HPVIDR1_IP_ID_MASK                  0xFFFF0000u
33582 #define SNVS_HPVIDR1_IP_ID_SHIFT                 16
33583 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_IP_ID_SHIFT))&SNVS_HPVIDR1_IP_ID_MASK)
33584 /* HPVIDR2 Bit Fields */
33585 #define SNVS_HPVIDR2_CONFIG_OPT_MASK             0xFFu
33586 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT            0
33587 #define SNVS_HPVIDR2_CONFIG_OPT(x)               (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_CONFIG_OPT_SHIFT))&SNVS_HPVIDR2_CONFIG_OPT_MASK)
33588 #define SNVS_HPVIDR2_ECO_REV_MASK                0xFF00u
33589 #define SNVS_HPVIDR2_ECO_REV_SHIFT               8
33590 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_ECO_REV_SHIFT))&SNVS_HPVIDR2_ECO_REV_MASK)
33591 #define SNVS_HPVIDR2_INTG_OPT_MASK               0xFF0000u
33592 #define SNVS_HPVIDR2_INTG_OPT_SHIFT              16
33593 #define SNVS_HPVIDR2_INTG_OPT(x)                 (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_INTG_OPT_SHIFT))&SNVS_HPVIDR2_INTG_OPT_MASK)
33594 #define SNVS_HPVIDR2_IP_ERA_MASK                 0xFF000000u
33595 #define SNVS_HPVIDR2_IP_ERA_SHIFT                24
33596 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_IP_ERA_SHIFT))&SNVS_HPVIDR2_IP_ERA_MASK)
33597 
33598 /*!
33599  * @}
33600  */ /* end of group SNVS_Register_Masks */
33601 
33602 /* SNVS - Peripheral instance base addresses */
33603 /** Peripheral SNVS base address */
33604 #define SNVS_BASE                                (0x420CC000u)
33605 /** Peripheral SNVS base pointer */
33606 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
33607 #define SNVS_BASE_PTR                            (SNVS)
33608 /** Array initializer of SNVS peripheral base addresses */
33609 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
33610 /** Array initializer of SNVS peripheral base pointers */
33611 #define SNVS_BASE_PTRS                           { SNVS }
33612 /** Interrupt vectors for the SNVS peripheral type */
33613 #define SNVS_IRQS                                { SNVS_IRQn }
33614 
33615 /* ----------------------------------------------------------------------------
33616    -- SNVS - Register accessor macros
33617    ---------------------------------------------------------------------------- */
33618 
33619 /*!
33620  * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros
33621  * @{
33622  */
33623 
33624 /* SNVS - Register instance definitions */
33625 /* SNVS */
33626 #define SNVS_HPLR                                SNVS_HPLR_REG(SNVS_BASE_PTR)
33627 #define SNVS_HPCOMR                              SNVS_HPCOMR_REG(SNVS_BASE_PTR)
33628 #define SNVS_HPCR                                SNVS_HPCR_REG(SNVS_BASE_PTR)
33629 #define SNVS_HPSR                                SNVS_HPSR_REG(SNVS_BASE_PTR)
33630 #define SNVS_HPRTCMR                             SNVS_HPRTCMR_REG(SNVS_BASE_PTR)
33631 #define SNVS_HPRTCLR                             SNVS_HPRTCLR_REG(SNVS_BASE_PTR)
33632 #define SNVS_HPTAMR                              SNVS_HPTAMR_REG(SNVS_BASE_PTR)
33633 #define SNVS_HPTALR                              SNVS_HPTALR_REG(SNVS_BASE_PTR)
33634 #define SNVS_LPLR                                SNVS_LPLR_REG(SNVS_BASE_PTR)
33635 #define SNVS_LPCR                                SNVS_LPCR_REG(SNVS_BASE_PTR)
33636 #define SNVS_LPSR                                SNVS_LPSR_REG(SNVS_BASE_PTR)
33637 #define SNVS_LPSMCMR                             SNVS_LPSMCMR_REG(SNVS_BASE_PTR)
33638 #define SNVS_LPSMCLR                             SNVS_LPSMCLR_REG(SNVS_BASE_PTR)
33639 #define SNVS_LPGPR                               SNVS_LPGPR_REG(SNVS_BASE_PTR)
33640 #define SNVS_HPVIDR1                             SNVS_HPVIDR1_REG(SNVS_BASE_PTR)
33641 #define SNVS_HPVIDR2                             SNVS_HPVIDR2_REG(SNVS_BASE_PTR)
33642 
33643 /*!
33644  * @}
33645  */ /* end of group SNVS_Register_Accessor_Macros */
33646 
33647 /*!
33648  * @}
33649  */ /* end of group SNVS_Peripheral */
33650 
33651 /* ----------------------------------------------------------------------------
33652    -- SPBA Peripheral Access Layer
33653    ---------------------------------------------------------------------------- */
33654 
33655 /*!
33656  * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
33657  * @{
33658  */
33659 
33660 /** SPBA - Register Layout Typedef */
33661 typedef struct {
33662   __IO  uint32_t PRR[32];                                /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
33663 } SPBA_Type, *SPBA_MemMapPtr;
33664 
33665 /* ----------------------------------------------------------------------------
33666    -- SPBA - Register accessor macros
33667    ---------------------------------------------------------------------------- */
33668 
33669 /*!
33670  * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros
33671  * @{
33672  */
33673 
33674 /* SPBA - Register accessors */
33675 #define SPBA_PRR_REG(base,index)                 ((base)->PRR[index])
33676 
33677 /*!
33678  * @}
33679  */ /* end of group SPBA_Register_Accessor_Macros */
33680 
33681 /* ----------------------------------------------------------------------------
33682    -- SPBA Register Masks
33683    ---------------------------------------------------------------------------- */
33684 
33685 /*!
33686  * @addtogroup SPBA_Register_Masks SPBA Register Masks
33687  * @{
33688  */
33689 
33690 /* PRR Bit Fields */
33691 #define SPBA_PRR_RARA_MASK                       0x1u
33692 #define SPBA_PRR_RARA_SHIFT                      0
33693 #define SPBA_PRR_RARB_MASK                       0x2u
33694 #define SPBA_PRR_RARB_SHIFT                      1
33695 #define SPBA_PRR_RARC_MASK                       0x4u
33696 #define SPBA_PRR_RARC_SHIFT                      2
33697 #define SPBA_PRR_ROI_MASK                        0x30000u
33698 #define SPBA_PRR_ROI_SHIFT                       16
33699 #define SPBA_PRR_ROI(x)                          (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_ROI_SHIFT))&SPBA_PRR_ROI_MASK)
33700 #define SPBA_PRR_RMO_MASK                        0xC0000000u
33701 #define SPBA_PRR_RMO_SHIFT                       30
33702 #define SPBA_PRR_RMO(x)                          (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_RMO_SHIFT))&SPBA_PRR_RMO_MASK)
33703 
33704 /*!
33705  * @}
33706  */ /* end of group SPBA_Register_Masks */
33707 
33708 /* SPBA - Peripheral instance base addresses */
33709 /** Peripheral SPBA base address */
33710 #define SPBA_BASE                                (0x40u)
33711 /** Peripheral SPBA base pointer */
33712 #define SPBA                                     ((SPBA_Type *)SPBA_BASE)
33713 #define SPBA_BASE_PTR                            (SPBA)
33714 /** Array initializer of SPBA peripheral base addresses */
33715 #define SPBA_BASE_ADDRS                          { SPBA_BASE }
33716 /** Array initializer of SPBA peripheral base pointers */
33717 #define SPBA_BASE_PTRS                           { SPBA }
33718 
33719 /* ----------------------------------------------------------------------------
33720    -- SPBA - Register accessor macros
33721    ---------------------------------------------------------------------------- */
33722 
33723 /*!
33724  * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros
33725  * @{
33726  */
33727 
33728 /* SPBA - Register instance definitions */
33729 /* SPBA */
33730 #define SPBA_PRR0                                SPBA_PRR_REG(SPBA_BASE_PTR,0)
33731 #define SPBA_PRR1                                SPBA_PRR_REG(SPBA_BASE_PTR,1)
33732 #define SPBA_PRR2                                SPBA_PRR_REG(SPBA_BASE_PTR,2)
33733 #define SPBA_PRR3                                SPBA_PRR_REG(SPBA_BASE_PTR,3)
33734 #define SPBA_PRR4                                SPBA_PRR_REG(SPBA_BASE_PTR,4)
33735 #define SPBA_PRR5                                SPBA_PRR_REG(SPBA_BASE_PTR,5)
33736 #define SPBA_PRR6                                SPBA_PRR_REG(SPBA_BASE_PTR,6)
33737 #define SPBA_PRR7                                SPBA_PRR_REG(SPBA_BASE_PTR,7)
33738 #define SPBA_PRR8                                SPBA_PRR_REG(SPBA_BASE_PTR,8)
33739 #define SPBA_PRR9                                SPBA_PRR_REG(SPBA_BASE_PTR,9)
33740 #define SPBA_PRR10                               SPBA_PRR_REG(SPBA_BASE_PTR,10)
33741 #define SPBA_PRR11                               SPBA_PRR_REG(SPBA_BASE_PTR,11)
33742 #define SPBA_PRR12                               SPBA_PRR_REG(SPBA_BASE_PTR,12)
33743 #define SPBA_PRR13                               SPBA_PRR_REG(SPBA_BASE_PTR,13)
33744 #define SPBA_PRR14                               SPBA_PRR_REG(SPBA_BASE_PTR,14)
33745 #define SPBA_PRR15                               SPBA_PRR_REG(SPBA_BASE_PTR,15)
33746 #define SPBA_PRR16                               SPBA_PRR_REG(SPBA_BASE_PTR,16)
33747 #define SPBA_PRR17                               SPBA_PRR_REG(SPBA_BASE_PTR,17)
33748 #define SPBA_PRR18                               SPBA_PRR_REG(SPBA_BASE_PTR,18)
33749 #define SPBA_PRR19                               SPBA_PRR_REG(SPBA_BASE_PTR,19)
33750 #define SPBA_PRR20                               SPBA_PRR_REG(SPBA_BASE_PTR,20)
33751 #define SPBA_PRR21                               SPBA_PRR_REG(SPBA_BASE_PTR,21)
33752 #define SPBA_PRR22                               SPBA_PRR_REG(SPBA_BASE_PTR,22)
33753 #define SPBA_PRR23                               SPBA_PRR_REG(SPBA_BASE_PTR,23)
33754 #define SPBA_PRR24                               SPBA_PRR_REG(SPBA_BASE_PTR,24)
33755 #define SPBA_PRR25                               SPBA_PRR_REG(SPBA_BASE_PTR,25)
33756 #define SPBA_PRR26                               SPBA_PRR_REG(SPBA_BASE_PTR,26)
33757 #define SPBA_PRR27                               SPBA_PRR_REG(SPBA_BASE_PTR,27)
33758 #define SPBA_PRR28                               SPBA_PRR_REG(SPBA_BASE_PTR,28)
33759 #define SPBA_PRR29                               SPBA_PRR_REG(SPBA_BASE_PTR,29)
33760 #define SPBA_PRR30                               SPBA_PRR_REG(SPBA_BASE_PTR,30)
33761 #define SPBA_PRR31                               SPBA_PRR_REG(SPBA_BASE_PTR,31)
33762 /* SPBA - Register array accessors */
33763 #define SPBA_PRR(index)                          SPBA_PRR_REG(SPBA_BASE_PTR,index)
33764 
33765 /*!
33766  * @}
33767  */ /* end of group SPBA_Register_Accessor_Macros */
33768 
33769 /*!
33770  * @}
33771  */ /* end of group SPBA_Peripheral */
33772 
33773 /* ----------------------------------------------------------------------------
33774    -- SPDIF Peripheral Access Layer
33775    ---------------------------------------------------------------------------- */
33776 
33777 /*!
33778  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
33779  * @{
33780  */
33781 
33782 /** SPDIF - Register Layout Typedef */
33783 typedef struct {
33784   __IO  uint32_t SCR;                                    /**< SPDIF Configuration Register, offset: 0x0 */
33785   __IO  uint32_t SRCD;                                   /**< CDText Control Register, offset: 0x4 */
33786   __IO  uint32_t SRPC;                                   /**< PhaseConfig Register, offset: 0x8 */
33787   __IO  uint32_t SIE;                                    /**< InterruptEn Register, offset: 0xC */
33788   union {                                          /* offset: 0x10 */
33789   __I     uint32_t SIS;                                         /**< InterruptStat Register,offset: 0x10 */
33790   __O     uint32_t SIC;                                         /**< InterruptClear Register,offset: 0x10 */
33791   struct {                                         /* offset: 0x14 */
33792       uint8_t RESERVED_0[4];
33793   __I     uint32_t SRL;                                         /**< SPDIFRxLeft Register,offset: 0x14 */
33794     } SRL;
33795   struct {                                         /* offset: 0x18 */
33796       uint8_t RESERVED_0[8];
33797   __I     uint32_t SRR;                                         /**< SPDIFRxRight Register,offset: 0x18 */
33798     } SRR;
33799   struct {                                         /* offset: 0x1C */
33800       uint8_t RESERVED_0[12];
33801   __I     uint32_t SRCSH;                                       /**< SPDIFRxCChannel_h Register,offset: 0x1C */
33802     } SRCSH;
33803   struct {                                         /* offset: 0x20 */
33804       uint8_t RESERVED_0[16];
33805   __I     uint32_t SRCSL;                                       /**< SPDIFRxCChannel_l Register,offset: 0x20 */
33806     } SRCSL;
33807   struct {                                         /* offset: 0x24 */
33808       uint8_t RESERVED_0[20];
33809   __I     uint32_t SRU;                                         /**< UchannelRx Register,offset: 0x24 */
33810     } SRU;
33811   struct {                                         /* offset: 0x28 */
33812       uint8_t RESERVED_0[24];
33813   __I     uint32_t SRQ;                                         /**< QchannelRx Register,offset: 0x28 */
33814     } SRQ;
33815   struct {                                         /* offset: 0x2C */
33816       uint8_t RESERVED_0[28];
33817   __O     uint32_t STL;                                         /**< SPDIFTxLeft Register,offset: 0x2C */
33818     } STL;
33819   struct {                                         /* offset: 0x30 */
33820       uint8_t RESERVED_0[32];
33821   __O     uint32_t STR;                                         /**< SPDIFTxRight Register,offset: 0x30 */
33822     } STR;
33823   struct {                                         /* offset: 0x34 */
33824       uint8_t RESERVED_0[36];
33825   __IO    uint32_t STCSCH;                                      /**< SPDIFTxCChannelCons_h Register,offset: 0x34 */
33826     } STCSCH;
33827   struct {                                         /* offset: 0x38 */
33828       uint8_t RESERVED_0[40];
33829   __IO    uint32_t STCSCL;                                      /**< SPDIFTxCChannelCons_l Register,offset: 0x38 */
33830     } STCSCL;
33831   };
33832   uint8_t RESERVED_0[8];
33833   __I   uint32_t SRFM;                                   /**< FreqMeas Register, offset: 0x44 */
33834   uint8_t RESERVED_1[8];
33835   __IO  uint32_t STC;                                    /**< SPDIFTxClk Register, offset: 0x50 */
33836 } SPDIF_Type, *SPDIF_MemMapPtr;
33837 
33838 /* ----------------------------------------------------------------------------
33839    -- SPDIF - Register accessor macros
33840    ---------------------------------------------------------------------------- */
33841 
33842 /*!
33843  * @addtogroup SPDIF_Register_Accessor_Macros SPDIF - Register accessor macros
33844  * @{
33845  */
33846 
33847 /* SPDIF - Register accessors */
33848 #define SPDIF_SCR_REG(base)                      ((base)->SCR)
33849 #define SPDIF_SRCD_REG(base)                     ((base)->SRCD)
33850 #define SPDIF_SRPC_REG(base)                     ((base)->SRPC)
33851 #define SPDIF_SIE_REG(base)                      ((base)->SIE)
33852 #define SPDIF_SIS_REG(base)                      ((base)->SIS)
33853 #define SPDIF_SIC_REG(base)                      ((base)->SIC)
33854 #define SPDIF_SRL_REG(base)                      ((base)->SRL.SRL)
33855 #define SPDIF_SRR_REG(base)                      ((base)->SRR.SRR)
33856 #define SPDIF_SRCSH_REG(base)                    ((base)->SRCSH.SRCSH)
33857 #define SPDIF_SRCSL_REG(base)                    ((base)->SRCSL.SRCSL)
33858 #define SPDIF_SRU_REG(base)                      ((base)->SRU.SRU)
33859 #define SPDIF_SRQ_REG(base)                      ((base)->SRQ.SRQ)
33860 #define SPDIF_STL_REG(base)                      ((base)->STL.STL)
33861 #define SPDIF_STR_REG(base)                      ((base)->STR.STR)
33862 #define SPDIF_STCSCH_REG(base)                   ((base)->STCSCH.STCSCH)
33863 #define SPDIF_STCSCL_REG(base)                   ((base)->STCSCL.STCSCL)
33864 #define SPDIF_SRFM_REG(base)                     ((base)->SRFM)
33865 #define SPDIF_STC_REG(base)                      ((base)->STC)
33866 
33867 /*!
33868  * @}
33869  */ /* end of group SPDIF_Register_Accessor_Macros */
33870 
33871 /* ----------------------------------------------------------------------------
33872    -- SPDIF Register Masks
33873    ---------------------------------------------------------------------------- */
33874 
33875 /*!
33876  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
33877  * @{
33878  */
33879 
33880 /* SCR Bit Fields */
33881 #define SPDIF_SCR_USrc_Sel_MASK                  0x3u
33882 #define SPDIF_SCR_USrc_Sel_SHIFT                 0
33883 #define SPDIF_SCR_USrc_Sel(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_USrc_Sel_SHIFT))&SPDIF_SCR_USrc_Sel_MASK)
33884 #define SPDIF_SCR_TxSel_MASK                     0x1Cu
33885 #define SPDIF_SCR_TxSel_SHIFT                    2
33886 #define SPDIF_SCR_TxSel(x)                       (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxSel_SHIFT))&SPDIF_SCR_TxSel_MASK)
33887 #define SPDIF_SCR_ValCtrl_MASK                   0x20u
33888 #define SPDIF_SCR_ValCtrl_SHIFT                  5
33889 #define SPDIF_SCR_DMA_TX_En_MASK                 0x100u
33890 #define SPDIF_SCR_DMA_TX_En_SHIFT                8
33891 #define SPDIF_SCR_DMA_Rx_En_MASK                 0x200u
33892 #define SPDIF_SCR_DMA_Rx_En_SHIFT                9
33893 #define SPDIF_SCR_TxFIFO_Ctrl_MASK               0xC00u
33894 #define SPDIF_SCR_TxFIFO_Ctrl_SHIFT              10
33895 #define SPDIF_SCR_TxFIFO_Ctrl(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFO_Ctrl_SHIFT))&SPDIF_SCR_TxFIFO_Ctrl_MASK)
33896 #define SPDIF_SCR_soft_reset_MASK                0x1000u
33897 #define SPDIF_SCR_soft_reset_SHIFT               12
33898 #define SPDIF_SCR_LOW_POWER_MASK                 0x2000u
33899 #define SPDIF_SCR_LOW_POWER_SHIFT                13
33900 #define SPDIF_SCR_TxFIFOEmpty_Sel_MASK           0x18000u
33901 #define SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT          15
33902 #define SPDIF_SCR_TxFIFOEmpty_Sel(x)             (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT))&SPDIF_SCR_TxFIFOEmpty_Sel_MASK)
33903 #define SPDIF_SCR_TxAutoSync_MASK                0x20000u
33904 #define SPDIF_SCR_TxAutoSync_SHIFT               17
33905 #define SPDIF_SCR_RxAutoSync_MASK                0x40000u
33906 #define SPDIF_SCR_RxAutoSync_SHIFT               18
33907 #define SPDIF_SCR_RxFIFOFull_Sel_MASK            0x180000u
33908 #define SPDIF_SCR_RxFIFOFull_Sel_SHIFT           19
33909 #define SPDIF_SCR_RxFIFOFull_Sel(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_RxFIFOFull_Sel_SHIFT))&SPDIF_SCR_RxFIFOFull_Sel_MASK)
33910 #define SPDIF_SCR_RxFIFO_Rst_MASK                0x200000u
33911 #define SPDIF_SCR_RxFIFO_Rst_SHIFT               21
33912 #define SPDIF_SCR_RxFIFO_Off_On_MASK             0x400000u
33913 #define SPDIF_SCR_RxFIFO_Off_On_SHIFT            22
33914 #define SPDIF_SCR_RxFIFO_Ctrl_MASK               0x800000u
33915 #define SPDIF_SCR_RxFIFO_Ctrl_SHIFT              23
33916 /* SRCD Bit Fields */
33917 #define SPDIF_SRCD_USyncMode_MASK                0x2u
33918 #define SPDIF_SRCD_USyncMode_SHIFT               1
33919 /* SRPC Bit Fields */
33920 #define SPDIF_SRPC_GainSel_MASK                  0x38u
33921 #define SPDIF_SRPC_GainSel_SHIFT                 3
33922 #define SPDIF_SRPC_GainSel(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_GainSel_SHIFT))&SPDIF_SRPC_GainSel_MASK)
33923 #define SPDIF_SRPC_LOCK_MASK                     0x40u
33924 #define SPDIF_SRPC_LOCK_SHIFT                    6
33925 #define SPDIF_SRPC_ClkSrc_Sel_MASK               0x780u
33926 #define SPDIF_SRPC_ClkSrc_Sel_SHIFT              7
33927 #define SPDIF_SRPC_ClkSrc_Sel(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_ClkSrc_Sel_SHIFT))&SPDIF_SRPC_ClkSrc_Sel_MASK)
33928 /* SIE Bit Fields */
33929 #define SPDIF_SIE_RxFIFOFul_MASK                 0x1u
33930 #define SPDIF_SIE_RxFIFOFul_SHIFT                0
33931 #define SPDIF_SIE_TxEm_MASK                      0x2u
33932 #define SPDIF_SIE_TxEm_SHIFT                     1
33933 #define SPDIF_SIE_LockLoss_MASK                  0x4u
33934 #define SPDIF_SIE_LockLoss_SHIFT                 2
33935 #define SPDIF_SIE_RxFIFOResyn_MASK               0x8u
33936 #define SPDIF_SIE_RxFIFOResyn_SHIFT              3
33937 #define SPDIF_SIE_RxFIFOUnOv_MASK                0x10u
33938 #define SPDIF_SIE_RxFIFOUnOv_SHIFT               4
33939 #define SPDIF_SIE_UQErr_MASK                     0x20u
33940 #define SPDIF_SIE_UQErr_SHIFT                    5
33941 #define SPDIF_SIE_UQSync_MASK                    0x40u
33942 #define SPDIF_SIE_UQSync_SHIFT                   6
33943 #define SPDIF_SIE_QRxOv_MASK                     0x80u
33944 #define SPDIF_SIE_QRxOv_SHIFT                    7
33945 #define SPDIF_SIE_QRxFul_MASK                    0x100u
33946 #define SPDIF_SIE_QRxFul_SHIFT                   8
33947 #define SPDIF_SIE_URxOv_MASK                     0x200u
33948 #define SPDIF_SIE_URxOv_SHIFT                    9
33949 #define SPDIF_SIE_URxFul_MASK                    0x400u
33950 #define SPDIF_SIE_URxFul_SHIFT                   10
33951 #define SPDIF_SIE_BitErr_MASK                    0x4000u
33952 #define SPDIF_SIE_BitErr_SHIFT                   14
33953 #define SPDIF_SIE_SymErr_MASK                    0x8000u
33954 #define SPDIF_SIE_SymErr_SHIFT                   15
33955 #define SPDIF_SIE_ValNoGood_MASK                 0x10000u
33956 #define SPDIF_SIE_ValNoGood_SHIFT                16
33957 #define SPDIF_SIE_CNew_MASK                      0x20000u
33958 #define SPDIF_SIE_CNew_SHIFT                     17
33959 #define SPDIF_SIE_TxResyn_MASK                   0x40000u
33960 #define SPDIF_SIE_TxResyn_SHIFT                  18
33961 #define SPDIF_SIE_TxUnOv_MASK                    0x80000u
33962 #define SPDIF_SIE_TxUnOv_SHIFT                   19
33963 #define SPDIF_SIE_Lock_MASK                      0x100000u
33964 #define SPDIF_SIE_Lock_SHIFT                     20
33965 /* SIS Bit Fields */
33966 #define SPDIF_SIS_RxFIFOFul_MASK                 0x1u
33967 #define SPDIF_SIS_RxFIFOFul_SHIFT                0
33968 #define SPDIF_SIS_TxEm_MASK                      0x2u
33969 #define SPDIF_SIS_TxEm_SHIFT                     1
33970 #define SPDIF_SIS_LockLoss_MASK                  0x4u
33971 #define SPDIF_SIS_LockLoss_SHIFT                 2
33972 #define SPDIF_SIS_RxFIFOResyn_MASK               0x8u
33973 #define SPDIF_SIS_RxFIFOResyn_SHIFT              3
33974 #define SPDIF_SIS_RxFIFOUnOv_MASK                0x10u
33975 #define SPDIF_SIS_RxFIFOUnOv_SHIFT               4
33976 #define SPDIF_SIS_UQErr_MASK                     0x20u
33977 #define SPDIF_SIS_UQErr_SHIFT                    5
33978 #define SPDIF_SIS_UQSync_MASK                    0x40u
33979 #define SPDIF_SIS_UQSync_SHIFT                   6
33980 #define SPDIF_SIS_QRxOv_MASK                     0x80u
33981 #define SPDIF_SIS_QRxOv_SHIFT                    7
33982 #define SPDIF_SIS_QRxFul_MASK                    0x100u
33983 #define SPDIF_SIS_QRxFul_SHIFT                   8
33984 #define SPDIF_SIS_URxOv_MASK                     0x200u
33985 #define SPDIF_SIS_URxOv_SHIFT                    9
33986 #define SPDIF_SIS_URxFul_MASK                    0x400u
33987 #define SPDIF_SIS_URxFul_SHIFT                   10
33988 #define SPDIF_SIS_BitErr_MASK                    0x4000u
33989 #define SPDIF_SIS_BitErr_SHIFT                   14
33990 #define SPDIF_SIS_SymErr_MASK                    0x8000u
33991 #define SPDIF_SIS_SymErr_SHIFT                   15
33992 #define SPDIF_SIS_ValNoGood_MASK                 0x10000u
33993 #define SPDIF_SIS_ValNoGood_SHIFT                16
33994 #define SPDIF_SIS_CNew_MASK                      0x20000u
33995 #define SPDIF_SIS_CNew_SHIFT                     17
33996 #define SPDIF_SIS_TxResyn_MASK                   0x40000u
33997 #define SPDIF_SIS_TxResyn_SHIFT                  18
33998 #define SPDIF_SIS_TxUnOv_MASK                    0x80000u
33999 #define SPDIF_SIS_TxUnOv_SHIFT                   19
34000 #define SPDIF_SIS_Lock_MASK                      0x100000u
34001 #define SPDIF_SIS_Lock_SHIFT                     20
34002 /* SIC Bit Fields */
34003 #define SPDIF_SIC_LockLoss_MASK                  0x4u
34004 #define SPDIF_SIC_LockLoss_SHIFT                 2
34005 #define SPDIF_SIC_RxFIFOResyn_MASK               0x8u
34006 #define SPDIF_SIC_RxFIFOResyn_SHIFT              3
34007 #define SPDIF_SIC_RxFIFOUnOv_MASK                0x10u
34008 #define SPDIF_SIC_RxFIFOUnOv_SHIFT               4
34009 #define SPDIF_SIC_UQErr_MASK                     0x20u
34010 #define SPDIF_SIC_UQErr_SHIFT                    5
34011 #define SPDIF_SIC_UQSync_MASK                    0x40u
34012 #define SPDIF_SIC_UQSync_SHIFT                   6
34013 #define SPDIF_SIC_QRxOv_MASK                     0x80u
34014 #define SPDIF_SIC_QRxOv_SHIFT                    7
34015 #define SPDIF_SIC_URxOv_MASK                     0x200u
34016 #define SPDIF_SIC_URxOv_SHIFT                    9
34017 #define SPDIF_SIC_BitErr_MASK                    0x4000u
34018 #define SPDIF_SIC_BitErr_SHIFT                   14
34019 #define SPDIF_SIC_SymErr_MASK                    0x8000u
34020 #define SPDIF_SIC_SymErr_SHIFT                   15
34021 #define SPDIF_SIC_ValNoGood_MASK                 0x10000u
34022 #define SPDIF_SIC_ValNoGood_SHIFT                16
34023 #define SPDIF_SIC_CNew_MASK                      0x20000u
34024 #define SPDIF_SIC_CNew_SHIFT                     17
34025 #define SPDIF_SIC_TxResyn_MASK                   0x40000u
34026 #define SPDIF_SIC_TxResyn_SHIFT                  18
34027 #define SPDIF_SIC_TxUnOv_MASK                    0x80000u
34028 #define SPDIF_SIC_TxUnOv_SHIFT                   19
34029 #define SPDIF_SIC_Lock_MASK                      0x100000u
34030 #define SPDIF_SIC_Lock_SHIFT                     20
34031 /* SRL Bit Fields */
34032 #define SPDIF_SRL_RxDataLeft_MASK                0xFFFFFFu
34033 #define SPDIF_SRL_RxDataLeft_SHIFT               0
34034 #define SPDIF_SRL_RxDataLeft(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRL_RxDataLeft_SHIFT))&SPDIF_SRL_RxDataLeft_MASK)
34035 /* SRR Bit Fields */
34036 #define SPDIF_SRR_RxDataRight_MASK               0xFFFFFFu
34037 #define SPDIF_SRR_RxDataRight_SHIFT              0
34038 #define SPDIF_SRR_RxDataRight(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SRR_RxDataRight_SHIFT))&SPDIF_SRR_RxDataRight_MASK)
34039 /* SRCSH Bit Fields */
34040 #define SPDIF_SRCSH_RxCChannel_h_MASK            0xFFFFFFu
34041 #define SPDIF_SRCSH_RxCChannel_h_SHIFT           0
34042 #define SPDIF_SRCSH_RxCChannel_h(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSH_RxCChannel_h_SHIFT))&SPDIF_SRCSH_RxCChannel_h_MASK)
34043 /* SRCSL Bit Fields */
34044 #define SPDIF_SRCSL_RxCChannel_l_MASK            0xFFFFFFu
34045 #define SPDIF_SRCSL_RxCChannel_l_SHIFT           0
34046 #define SPDIF_SRCSL_RxCChannel_l(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSL_RxCChannel_l_SHIFT))&SPDIF_SRCSL_RxCChannel_l_MASK)
34047 /* SRU Bit Fields */
34048 #define SPDIF_SRU_RxUChannel_MASK                0xFFFFFFu
34049 #define SPDIF_SRU_RxUChannel_SHIFT               0
34050 #define SPDIF_SRU_RxUChannel(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRU_RxUChannel_SHIFT))&SPDIF_SRU_RxUChannel_MASK)
34051 /* SRQ Bit Fields */
34052 #define SPDIF_SRQ_RxQChannel_MASK                0xFFFFFFu
34053 #define SPDIF_SRQ_RxQChannel_SHIFT               0
34054 #define SPDIF_SRQ_RxQChannel(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRQ_RxQChannel_SHIFT))&SPDIF_SRQ_RxQChannel_MASK)
34055 /* STL Bit Fields */
34056 #define SPDIF_STL_TxDataLeft_MASK                0xFFFFFFu
34057 #define SPDIF_STL_TxDataLeft_SHIFT               0
34058 #define SPDIF_STL_TxDataLeft(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_STL_TxDataLeft_SHIFT))&SPDIF_STL_TxDataLeft_MASK)
34059 /* STR Bit Fields */
34060 #define SPDIF_STR_TxDataRight_MASK               0xFFFFFFu
34061 #define SPDIF_STR_TxDataRight_SHIFT              0
34062 #define SPDIF_STR_TxDataRight(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_STR_TxDataRight_SHIFT))&SPDIF_STR_TxDataRight_MASK)
34063 /* STCSCH Bit Fields */
34064 #define SPDIF_STCSCH_TxCChannelCons_h_MASK       0xFFFFFFu
34065 #define SPDIF_STCSCH_TxCChannelCons_h_SHIFT      0
34066 #define SPDIF_STCSCH_TxCChannelCons_h(x)         (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCH_TxCChannelCons_h_SHIFT))&SPDIF_STCSCH_TxCChannelCons_h_MASK)
34067 /* STCSCL Bit Fields */
34068 #define SPDIF_STCSCL_TxCChannelCons_l_MASK       0xFFFFFFu
34069 #define SPDIF_STCSCL_TxCChannelCons_l_SHIFT      0
34070 #define SPDIF_STCSCL_TxCChannelCons_l(x)         (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCL_TxCChannelCons_l_SHIFT))&SPDIF_STCSCL_TxCChannelCons_l_MASK)
34071 /* SRFM Bit Fields */
34072 #define SPDIF_SRFM_FreqMeas_MASK                 0xFFFFFFu
34073 #define SPDIF_SRFM_FreqMeas_SHIFT                0
34074 #define SPDIF_SRFM_FreqMeas(x)                   (((uint32_t)(((uint32_t)(x))<<SPDIF_SRFM_FreqMeas_SHIFT))&SPDIF_SRFM_FreqMeas_MASK)
34075 /* STC Bit Fields */
34076 #define SPDIF_STC_TxClk_DF_MASK                  0x7Fu
34077 #define SPDIF_STC_TxClk_DF_SHIFT                 0
34078 #define SPDIF_STC_TxClk_DF(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_DF_SHIFT))&SPDIF_STC_TxClk_DF_MASK)
34079 #define SPDIF_STC_tx_all_clk_en_MASK             0x80u
34080 #define SPDIF_STC_tx_all_clk_en_SHIFT            7
34081 #define SPDIF_STC_TxClk_Source_MASK              0x700u
34082 #define SPDIF_STC_TxClk_Source_SHIFT             8
34083 #define SPDIF_STC_TxClk_Source(x)                (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_Source_SHIFT))&SPDIF_STC_TxClk_Source_MASK)
34084 #define SPDIF_STC_SYSCLK_DF_MASK                 0xFF800u
34085 #define SPDIF_STC_SYSCLK_DF_SHIFT                11
34086 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_SYSCLK_DF_SHIFT))&SPDIF_STC_SYSCLK_DF_MASK)
34087 
34088 /*!
34089  * @}
34090  */ /* end of group SPDIF_Register_Masks */
34091 
34092 /* SPDIF - Peripheral instance base addresses */
34093 /** Peripheral SPDIF base address */
34094 #define SPDIF_BASE                               (0x42004000u)
34095 /** Peripheral SPDIF base pointer */
34096 #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
34097 #define SPDIF_BASE_PTR                           (SPDIF)
34098 /** Array initializer of SPDIF peripheral base addresses */
34099 #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
34100 /** Array initializer of SPDIF peripheral base pointers */
34101 #define SPDIF_BASE_PTRS                          { SPDIF }
34102 /** Interrupt vectors for the SPDIF peripheral type */
34103 #define SPDIF_IRQS                               { SPDIF_IRQn }
34104 
34105 /* ----------------------------------------------------------------------------
34106    -- SPDIF - Register accessor macros
34107    ---------------------------------------------------------------------------- */
34108 
34109 /*!
34110  * @addtogroup SPDIF_Register_Accessor_Macros SPDIF - Register accessor macros
34111  * @{
34112  */
34113 
34114 /* SPDIF - Register instance definitions */
34115 /* SPDIF */
34116 #define SPDIF_SCR                                SPDIF_SCR_REG(SPDIF_BASE_PTR)
34117 #define SPDIF_SRCD                               SPDIF_SRCD_REG(SPDIF_BASE_PTR)
34118 #define SPDIF_SRPC                               SPDIF_SRPC_REG(SPDIF_BASE_PTR)
34119 #define SPDIF_SIE                                SPDIF_SIE_REG(SPDIF_BASE_PTR)
34120 #define SPDIF_SIS                                SPDIF_SIS_REG(SPDIF_BASE_PTR)
34121 #define SPDIF_SIC                                SPDIF_SIC_REG(SPDIF_BASE_PTR)
34122 #define SPDIF_SRL                                SPDIF_SRL_REG(SPDIF_BASE_PTR)
34123 #define SPDIF_SRR                                SPDIF_SRR_REG(SPDIF_BASE_PTR)
34124 #define SPDIF_SRCSH                              SPDIF_SRCSH_REG(SPDIF_BASE_PTR)
34125 #define SPDIF_SRCSL                              SPDIF_SRCSL_REG(SPDIF_BASE_PTR)
34126 #define SPDIF_SRU                                SPDIF_SRU_REG(SPDIF_BASE_PTR)
34127 #define SPDIF_SRQ                                SPDIF_SRQ_REG(SPDIF_BASE_PTR)
34128 #define SPDIF_STL                                SPDIF_STL_REG(SPDIF_BASE_PTR)
34129 #define SPDIF_STR                                SPDIF_STR_REG(SPDIF_BASE_PTR)
34130 #define SPDIF_STCSCH                             SPDIF_STCSCH_REG(SPDIF_BASE_PTR)
34131 #define SPDIF_STCSCL                             SPDIF_STCSCL_REG(SPDIF_BASE_PTR)
34132 #define SPDIF_SRFM                               SPDIF_SRFM_REG(SPDIF_BASE_PTR)
34133 #define SPDIF_STC                                SPDIF_STC_REG(SPDIF_BASE_PTR)
34134 
34135 /*!
34136  * @}
34137  */ /* end of group SPDIF_Register_Accessor_Macros */
34138 
34139 /*!
34140  * @}
34141  */ /* end of group SPDIF_Peripheral */
34142 
34143 /* ----------------------------------------------------------------------------
34144    -- SRC Peripheral Access Layer
34145    ---------------------------------------------------------------------------- */
34146 
34147 /*!
34148  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
34149  * @{
34150  */
34151 
34152 /** SRC - Register Layout Typedef */
34153 typedef struct {
34154   __IO  uint32_t SCR;                                    /**< SRC Control Register, offset: 0x0 */
34155   __I   uint32_t SBMR1;                                  /**< SRC Boot Mode Register 1, offset: 0x4 */
34156   __IO  uint32_t SRSR;                                   /**< SRC Reset Status Register, offset: 0x8 */
34157   uint8_t RESERVED_0[8];
34158   __I   uint32_t SISR;                                   /**< SRC Interrupt Status Register, offset: 0x14 */
34159   __IO  uint32_t SIMR;                                   /**< SRC Interrupt Mask Register, offset: 0x18 */
34160   __I   uint32_t SBMR2;                                  /**< SRC Boot Mode Register 2, offset: 0x1C */
34161   __IO  uint32_t GPR1;                                   /**< SRC General Purpose Register 1, offset: 0x20 */
34162   __IO  uint32_t GPR2;                                   /**< SRC General Purpose Register 2, offset: 0x24 */
34163   __IO  uint32_t GPR3;                                   /**< SRC General Purpose Register 3, offset: 0x28 */
34164   __IO  uint32_t GPR4;                                   /**< SRC General Purpose Register 4, offset: 0x2C */
34165   __IO  uint32_t GPR5;                                   /**< SRC General Purpose Register 5, offset: 0x30 */
34166   __IO  uint32_t GPR6;                                   /**< SRC General Purpose Register 6, offset: 0x34 */
34167   __IO  uint32_t GPR7;                                   /**< SRC General Purpose Register 7, offset: 0x38 */
34168   __IO  uint32_t GPR8;                                   /**< SRC General Purpose Register 8, offset: 0x3C */
34169   __IO  uint32_t GPR9;                                   /**< SRC General Purpose Register 9, offset: 0x40 */
34170   __IO  uint32_t GPR10;                                  /**< SRC General Purpose Register 10, offset: 0x44 */
34171 } SRC_Type, *SRC_MemMapPtr;
34172 
34173 /* ----------------------------------------------------------------------------
34174    -- SRC - Register accessor macros
34175    ---------------------------------------------------------------------------- */
34176 
34177 /*!
34178  * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros
34179  * @{
34180  */
34181 
34182 /* SRC - Register accessors */
34183 #define SRC_SCR_REG(base)                        ((base)->SCR)
34184 #define SRC_SBMR1_REG(base)                      ((base)->SBMR1)
34185 #define SRC_SRSR_REG(base)                       ((base)->SRSR)
34186 #define SRC_SISR_REG(base)                       ((base)->SISR)
34187 #define SRC_SIMR_REG(base)                       ((base)->SIMR)
34188 #define SRC_SBMR2_REG(base)                      ((base)->SBMR2)
34189 #define SRC_GPR1_REG(base)                       ((base)->GPR1)
34190 #define SRC_GPR2_REG(base)                       ((base)->GPR2)
34191 #define SRC_GPR3_REG(base)                       ((base)->GPR3)
34192 #define SRC_GPR4_REG(base)                       ((base)->GPR4)
34193 #define SRC_GPR5_REG(base)                       ((base)->GPR5)
34194 #define SRC_GPR6_REG(base)                       ((base)->GPR6)
34195 #define SRC_GPR7_REG(base)                       ((base)->GPR7)
34196 #define SRC_GPR8_REG(base)                       ((base)->GPR8)
34197 #define SRC_GPR9_REG(base)                       ((base)->GPR9)
34198 #define SRC_GPR10_REG(base)                      ((base)->GPR10)
34199 
34200 /*!
34201  * @}
34202  */ /* end of group SRC_Register_Accessor_Macros */
34203 
34204 /* ----------------------------------------------------------------------------
34205    -- SRC Register Masks
34206    ---------------------------------------------------------------------------- */
34207 
34208 /*!
34209  * @addtogroup SRC_Register_Masks SRC Register Masks
34210  * @{
34211  */
34212 
34213 /* SCR Bit Fields */
34214 #define SRC_SCR_warm_reset_enable_MASK           0x1u
34215 #define SRC_SCR_warm_reset_enable_SHIFT          0
34216 #define SRC_SCR_sw_gpu_rst_MASK                  0x2u
34217 #define SRC_SCR_sw_gpu_rst_SHIFT                 1
34218 #define SRC_SCR_m4c_rst_MASK                     0x8u
34219 #define SRC_SCR_m4c_rst_SHIFT                    3
34220 #define SRC_SCR_m4c_non_sclr_rst_MASK            0x10u
34221 #define SRC_SCR_m4c_non_sclr_rst_SHIFT           4
34222 #define SRC_SCR_warm_rst_bypass_count_MASK       0x60u
34223 #define SRC_SCR_warm_rst_bypass_count_SHIFT      5
34224 #define SRC_SCR_warm_rst_bypass_count(x)         (((uint32_t)(((uint32_t)(x))<<SRC_SCR_warm_rst_bypass_count_SHIFT))&SRC_SCR_warm_rst_bypass_count_MASK)
34225 #define SRC_SCR_mask_wdog_rst_MASK               0x780u
34226 #define SRC_SCR_mask_wdog_rst_SHIFT              7
34227 #define SRC_SCR_mask_wdog_rst(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_wdog_rst_SHIFT))&SRC_SCR_mask_wdog_rst_MASK)
34228 #define SRC_SCR_eim_rst_MASK                     0x800u
34229 #define SRC_SCR_eim_rst_SHIFT                    11
34230 #define SRC_SCR_m4p_rst_MASK                     0x1000u
34231 #define SRC_SCR_m4p_rst_SHIFT                    12
34232 #define SRC_SCR_core0_rst_MASK                   0x2000u
34233 #define SRC_SCR_core0_rst_SHIFT                  13
34234 #define SRC_SCR_core0_dbg_rst_MASK               0x20000u
34235 #define SRC_SCR_core0_dbg_rst_SHIFT              17
34236 #define SRC_SCR_mask_tempsense_reset_MASK        0x1C0000u
34237 #define SRC_SCR_mask_tempsense_reset_SHIFT       18
34238 #define SRC_SCR_mask_tempsense_reset(x)          (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_tempsense_reset_SHIFT))&SRC_SCR_mask_tempsense_reset_MASK)
34239 #define SRC_SCR_cores_dbg_rst_MASK               0x200000u
34240 #define SRC_SCR_cores_dbg_rst_SHIFT              21
34241 #define SRC_SCR_m4_enable_MASK                   0x400000u
34242 #define SRC_SCR_m4_enable_SHIFT                  22
34243 #define SRC_SCR_wdog3_rst_optn_m4_MASK           0x800000u
34244 #define SRC_SCR_wdog3_rst_optn_m4_SHIFT          23
34245 #define SRC_SCR_wdog3_rst_optn_MASK              0x1000000u
34246 #define SRC_SCR_wdog3_rst_optn_SHIFT             24
34247 #define SRC_SCR_dbg_rst_msk_pg_MASK              0x2000000u
34248 #define SRC_SCR_dbg_rst_msk_pg_SHIFT             25
34249 #define SRC_SCR_mix_rst_strch_MASK               0xC000000u
34250 #define SRC_SCR_mix_rst_strch_SHIFT              26
34251 #define SRC_SCR_mix_rst_strch(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mix_rst_strch_SHIFT))&SRC_SCR_mix_rst_strch_MASK)
34252 #define SRC_SCR_mask_wdog3_rst_MASK              0xF0000000u
34253 #define SRC_SCR_mask_wdog3_rst_SHIFT             28
34254 #define SRC_SCR_mask_wdog3_rst(x)                (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_wdog3_rst_SHIFT))&SRC_SCR_mask_wdog3_rst_MASK)
34255 /* SBMR1 Bit Fields */
34256 #define SRC_SBMR1_BOOT_CFG1_MASK                 0xFFu
34257 #define SRC_SBMR1_BOOT_CFG1_SHIFT                0
34258 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG1_SHIFT))&SRC_SBMR1_BOOT_CFG1_MASK)
34259 #define SRC_SBMR1_BOOT_CFG2_MASK                 0xFF00u
34260 #define SRC_SBMR1_BOOT_CFG2_SHIFT                8
34261 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG2_SHIFT))&SRC_SBMR1_BOOT_CFG2_MASK)
34262 #define SRC_SBMR1_BOOT_CFG3_MASK                 0xFF0000u
34263 #define SRC_SBMR1_BOOT_CFG3_SHIFT                16
34264 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG3_SHIFT))&SRC_SBMR1_BOOT_CFG3_MASK)
34265 #define SRC_SBMR1_BOOT_CFG4_MASK                 0xFF000000u
34266 #define SRC_SBMR1_BOOT_CFG4_SHIFT                24
34267 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG4_SHIFT))&SRC_SBMR1_BOOT_CFG4_MASK)
34268 /* SRSR Bit Fields */
34269 #define SRC_SRSR_ipp_reset_b_MASK                0x1u
34270 #define SRC_SRSR_ipp_reset_b_SHIFT               0
34271 #define SRC_SRSR_csu_reset_b_MASK                0x4u
34272 #define SRC_SRSR_csu_reset_b_SHIFT               2
34273 #define SRC_SRSR_ipp_user_reset_b_MASK           0x8u
34274 #define SRC_SRSR_ipp_user_reset_b_SHIFT          3
34275 #define SRC_SRSR_wdog_rst_b_MASK                 0x10u
34276 #define SRC_SRSR_wdog_rst_b_SHIFT                4
34277 #define SRC_SRSR_jtag_rst_b_MASK                 0x20u
34278 #define SRC_SRSR_jtag_rst_b_SHIFT                5
34279 #define SRC_SRSR_jtag_sw_rst_MASK                0x40u
34280 #define SRC_SRSR_jtag_sw_rst_SHIFT               6
34281 #define SRC_SRSR_wdog3_rst_b_MASK                0x80u
34282 #define SRC_SRSR_wdog3_rst_b_SHIFT               7
34283 #define SRC_SRSR_tempsense_rst_b_MASK            0x100u
34284 #define SRC_SRSR_tempsense_rst_b_SHIFT           8
34285 #define SRC_SRSR_warm_boot_MASK                  0x10000u
34286 #define SRC_SRSR_warm_boot_SHIFT                 16
34287 /* SISR Bit Fields */
34288 #define SRC_SISR_gpu_passed_reset_MASK           0x1u
34289 #define SRC_SISR_gpu_passed_reset_SHIFT          0
34290 #define SRC_SISR_m4c_passed_reset_MASK           0x4u
34291 #define SRC_SISR_m4c_passed_reset_SHIFT          2
34292 #define SRC_SISR_open_vg_passed_reset_MASK       0x8u
34293 #define SRC_SISR_open_vg_passed_reset_SHIFT      3
34294 #define SRC_SISR_m4p_passed_reset_MASK           0x10u
34295 #define SRC_SISR_m4p_passed_reset_SHIFT          4
34296 #define SRC_SISR_core0_wdog_rst_req_MASK         0x20u
34297 #define SRC_SISR_core0_wdog_rst_req_SHIFT        5
34298 /* SIMR Bit Fields */
34299 #define SRC_SIMR_mask_gpu_passed_reset_MASK      0x1u
34300 #define SRC_SIMR_mask_gpu_passed_reset_SHIFT     0
34301 #define SRC_SIMR_mask_open_vg_passed_reset_MASK  0x8u
34302 #define SRC_SIMR_mask_open_vg_passed_reset_SHIFT 3
34303 /* SBMR2 Bit Fields */
34304 #define SRC_SBMR2_SEC_CONFIG_MASK                0x3u
34305 #define SRC_SBMR2_SEC_CONFIG_SHIFT               0
34306 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_SEC_CONFIG_SHIFT))&SRC_SBMR2_SEC_CONFIG_MASK)
34307 #define SRC_SBMR2_DIR_BT_DIS_MASK                0x8u
34308 #define SRC_SBMR2_DIR_BT_DIS_SHIFT               3
34309 #define SRC_SBMR2_BT_FUSE_SEL_MASK               0x10u
34310 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              4
34311 #define SRC_SBMR2_BMOD_MASK                      0x3000000u
34312 #define SRC_SBMR2_BMOD_SHIFT                     24
34313 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_BMOD_SHIFT))&SRC_SBMR2_BMOD_MASK)
34314 /* GPR1 Bit Fields */
34315 #define SRC_GPR1_PERSISTENT_ENTRY0_MASK          0xFFFFFFFFu
34316 #define SRC_GPR1_PERSISTENT_ENTRY0_SHIFT         0
34317 #define SRC_GPR1_PERSISTENT_ENTRY0(x)            (((uint32_t)(((uint32_t)(x))<<SRC_GPR1_PERSISTENT_ENTRY0_SHIFT))&SRC_GPR1_PERSISTENT_ENTRY0_MASK)
34318 /* GPR2 Bit Fields */
34319 #define SRC_GPR2_PERSISTENT_ARG0_MASK            0xFFFFFFFFu
34320 #define SRC_GPR2_PERSISTENT_ARG0_SHIFT           0
34321 #define SRC_GPR2_PERSISTENT_ARG0(x)              (((uint32_t)(((uint32_t)(x))<<SRC_GPR2_PERSISTENT_ARG0_SHIFT))&SRC_GPR2_PERSISTENT_ARG0_MASK)
34322 /* GPR3 Bit Fields */
34323 #define SRC_GPR3_PERSISTENT_ENTRY1_MASK          0xFFFFFFFFu
34324 #define SRC_GPR3_PERSISTENT_ENTRY1_SHIFT         0
34325 #define SRC_GPR3_PERSISTENT_ENTRY1(x)            (((uint32_t)(((uint32_t)(x))<<SRC_GPR3_PERSISTENT_ENTRY1_SHIFT))&SRC_GPR3_PERSISTENT_ENTRY1_MASK)
34326 /* GPR4 Bit Fields */
34327 #define SRC_GPR4_PERSISTENT_ARG1_MASK            0xFFFFFFFFu
34328 #define SRC_GPR4_PERSISTENT_ARG1_SHIFT           0
34329 #define SRC_GPR4_PERSISTENT_ARG1(x)              (((uint32_t)(((uint32_t)(x))<<SRC_GPR4_PERSISTENT_ARG1_SHIFT))&SRC_GPR4_PERSISTENT_ARG1_MASK)
34330 /* GPR5 Bit Fields */
34331 /* GPR6 Bit Fields */
34332 /* GPR7 Bit Fields */
34333 /* GPR8 Bit Fields */
34334 /* GPR9 Bit Fields */
34335 /* GPR10 Bit Fields */
34336 
34337 /*!
34338  * @}
34339  */ /* end of group SRC_Register_Masks */
34340 
34341 /* SRC - Peripheral instance base addresses */
34342 /** Peripheral SRC base address */
34343 #define SRC_BASE                                 (0x420D8000u)
34344 /** Peripheral SRC base pointer */
34345 #define SRC                                      ((SRC_Type *)SRC_BASE)
34346 #define SRC_BASE_PTR                             (SRC)
34347 /** Array initializer of SRC peripheral base addresses */
34348 #define SRC_BASE_ADDRS                           { SRC_BASE }
34349 /** Array initializer of SRC peripheral base pointers */
34350 #define SRC_BASE_PTRS                            { SRC }
34351 /** Interrupt vectors for the SRC peripheral type */
34352 #define SRC_IRQS                                 { SRC_IRQn }
34353 
34354 /* ----------------------------------------------------------------------------
34355    -- SRC - Register accessor macros
34356    ---------------------------------------------------------------------------- */
34357 
34358 /*!
34359  * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros
34360  * @{
34361  */
34362 
34363 /* SRC - Register instance definitions */
34364 /* SRC */
34365 #define SRC_SCR                                  SRC_SCR_REG(SRC_BASE_PTR)
34366 #define SRC_SBMR1                                SRC_SBMR1_REG(SRC_BASE_PTR)
34367 #define SRC_SRSR                                 SRC_SRSR_REG(SRC_BASE_PTR)
34368 #define SRC_SISR                                 SRC_SISR_REG(SRC_BASE_PTR)
34369 #define SRC_SIMR                                 SRC_SIMR_REG(SRC_BASE_PTR)
34370 #define SRC_SBMR2                                SRC_SBMR2_REG(SRC_BASE_PTR)
34371 #define SRC_GPR1                                 SRC_GPR1_REG(SRC_BASE_PTR)
34372 #define SRC_GPR2                                 SRC_GPR2_REG(SRC_BASE_PTR)
34373 #define SRC_GPR3                                 SRC_GPR3_REG(SRC_BASE_PTR)
34374 #define SRC_GPR4                                 SRC_GPR4_REG(SRC_BASE_PTR)
34375 #define SRC_GPR5                                 SRC_GPR5_REG(SRC_BASE_PTR)
34376 #define SRC_GPR6                                 SRC_GPR6_REG(SRC_BASE_PTR)
34377 #define SRC_GPR7                                 SRC_GPR7_REG(SRC_BASE_PTR)
34378 #define SRC_GPR8                                 SRC_GPR8_REG(SRC_BASE_PTR)
34379 #define SRC_GPR9                                 SRC_GPR9_REG(SRC_BASE_PTR)
34380 #define SRC_GPR10                                SRC_GPR10_REG(SRC_BASE_PTR)
34381 
34382 /*!
34383  * @}
34384  */ /* end of group SRC_Register_Accessor_Macros */
34385 
34386 /*!
34387  * @}
34388  */ /* end of group SRC_Peripheral */
34389 
34390 /* ----------------------------------------------------------------------------
34391    -- SSI Peripheral Access Layer
34392    ---------------------------------------------------------------------------- */
34393 
34394 /*!
34395  * @addtogroup SSI_Peripheral_Access_Layer SSI Peripheral Access Layer
34396  * @{
34397  */
34398 
34399 /** SSI - Register Layout Typedef */
34400 typedef struct {
34401   __IO  uint32_t STX[2];                                 /**< SSI Transmit Data Register n, array offset: 0x0, array step: 0x4 */
34402   __I   uint32_t SRX[2];                                 /**< SSI Receive Data Register n, array offset: 0x8, array step: 0x4 */
34403   __IO  uint32_t SCR;                                    /**< SSI Control Register, offset: 0x10 */
34404   __IO  uint32_t SISR;                                   /**< SSI Interrupt Status Register, offset: 0x14 */
34405   __IO  uint32_t SIER;                                   /**< SSI Interrupt Enable Register, offset: 0x18 */
34406   __IO  uint32_t STCR;                                   /**< SSI Transmit Configuration Register, offset: 0x1C */
34407   __IO  uint32_t SRCR;                                   /**< SSI Receive Configuration Register, offset: 0x20 */
34408   __IO  uint32_t STCCR;                                  /**< SSI Transmit Clock Control Register, offset: 0x24 */
34409   __IO  uint32_t SRCCR;                                  /**< SSI Receive Clock Control Register, offset: 0x28 */
34410   __IO  uint32_t SFCSR;                                  /**< SSI FIFO Control/Status Register, offset: 0x2C */
34411   uint8_t RESERVED_0[8];
34412   __IO  uint32_t SACNT;                                  /**< SSI AC97 Control Register, offset: 0x38 */
34413   __IO  uint32_t SACADD;                                 /**< SSI AC97 Command Address Register, offset: 0x3C */
34414   __IO  uint32_t SACDAT;                                 /**< SSI AC97 Command Data Register, offset: 0x40 */
34415   __IO  uint32_t SATAG;                                  /**< SSI AC97 Tag Register, offset: 0x44 */
34416   __IO  uint32_t STMSK;                                  /**< SSI Transmit Time Slot Mask Register, offset: 0x48 */
34417   __IO  uint32_t SRMSK;                                  /**< SSI Receive Time Slot Mask Register, offset: 0x4C */
34418   __I   uint32_t SACCST;                                 /**< SSI AC97 Channel Status Register, offset: 0x50 */
34419   __O   uint32_t SACCEN;                                 /**< SSI AC97 Channel Enable Register, offset: 0x54 */
34420   __O   uint32_t SACCDIS;                                /**< SSI AC97 Channel Disable Register, offset: 0x58 */
34421 } SSI_Type, *SSI_MemMapPtr;
34422 
34423 /* ----------------------------------------------------------------------------
34424    -- SSI - Register accessor macros
34425    ---------------------------------------------------------------------------- */
34426 
34427 /*!
34428  * @addtogroup SSI_Register_Accessor_Macros SSI - Register accessor macros
34429  * @{
34430  */
34431 
34432 /* SSI - Register accessors */
34433 #define SSI_STX_REG(base,index)                  ((base)->STX[index])
34434 #define SSI_SRX_REG(base,index)                  ((base)->SRX[index])
34435 #define SSI_SCR_REG(base)                        ((base)->SCR)
34436 #define SSI_SISR_REG(base)                       ((base)->SISR)
34437 #define SSI_SIER_REG(base)                       ((base)->SIER)
34438 #define SSI_STCR_REG(base)                       ((base)->STCR)
34439 #define SSI_SRCR_REG(base)                       ((base)->SRCR)
34440 #define SSI_STCCR_REG(base)                      ((base)->STCCR)
34441 #define SSI_SRCCR_REG(base)                      ((base)->SRCCR)
34442 #define SSI_SFCSR_REG(base)                      ((base)->SFCSR)
34443 #define SSI_SACNT_REG(base)                      ((base)->SACNT)
34444 #define SSI_SACADD_REG(base)                     ((base)->SACADD)
34445 #define SSI_SACDAT_REG(base)                     ((base)->SACDAT)
34446 #define SSI_SATAG_REG(base)                      ((base)->SATAG)
34447 #define SSI_STMSK_REG(base)                      ((base)->STMSK)
34448 #define SSI_SRMSK_REG(base)                      ((base)->SRMSK)
34449 #define SSI_SACCST_REG(base)                     ((base)->SACCST)
34450 #define SSI_SACCEN_REG(base)                     ((base)->SACCEN)
34451 #define SSI_SACCDIS_REG(base)                    ((base)->SACCDIS)
34452 
34453 /*!
34454  * @}
34455  */ /* end of group SSI_Register_Accessor_Macros */
34456 
34457 /* ----------------------------------------------------------------------------
34458    -- SSI Register Masks
34459    ---------------------------------------------------------------------------- */
34460 
34461 /*!
34462  * @addtogroup SSI_Register_Masks SSI Register Masks
34463  * @{
34464  */
34465 
34466 /* STX Bit Fields */
34467 #define SSI_STX_STXn_MASK                        0xFFFFFFFFu
34468 #define SSI_STX_STXn_SHIFT                       0
34469 #define SSI_STX_STXn(x)                          (((uint32_t)(((uint32_t)(x))<<SSI_STX_STXn_SHIFT))&SSI_STX_STXn_MASK)
34470 /* SRX Bit Fields */
34471 #define SSI_SRX_SRXn_MASK                        0xFFFFFFFFu
34472 #define SSI_SRX_SRXn_SHIFT                       0
34473 #define SSI_SRX_SRXn(x)                          (((uint32_t)(((uint32_t)(x))<<SSI_SRX_SRXn_SHIFT))&SSI_SRX_SRXn_MASK)
34474 /* SCR Bit Fields */
34475 #define SSI_SCR_SSIEN_MASK                       0x1u
34476 #define SSI_SCR_SSIEN_SHIFT                      0
34477 #define SSI_SCR_TE_MASK                          0x2u
34478 #define SSI_SCR_TE_SHIFT                         1
34479 #define SSI_SCR_RE_MASK                          0x4u
34480 #define SSI_SCR_RE_SHIFT                         2
34481 #define SSI_SCR_NET_MASK                         0x8u
34482 #define SSI_SCR_NET_SHIFT                        3
34483 #define SSI_SCR_SYN_MASK                         0x10u
34484 #define SSI_SCR_SYN_SHIFT                        4
34485 #define SSI_SCR_I2S_MODE_MASK                    0x60u
34486 #define SSI_SCR_I2S_MODE_SHIFT                   5
34487 #define SSI_SCR_I2S_MODE(x)                      (((uint32_t)(((uint32_t)(x))<<SSI_SCR_I2S_MODE_SHIFT))&SSI_SCR_I2S_MODE_MASK)
34488 #define SSI_SCR_SYS_CLK_EN_MASK                  0x80u
34489 #define SSI_SCR_SYS_CLK_EN_SHIFT                 7
34490 #define SSI_SCR_TCH_EN_MASK                      0x100u
34491 #define SSI_SCR_TCH_EN_SHIFT                     8
34492 #define SSI_SCR_CLK_IST_MASK                     0x200u
34493 #define SSI_SCR_CLK_IST_SHIFT                    9
34494 #define SSI_SCR_TFR_CLK_DIS_MASK                 0x400u
34495 #define SSI_SCR_TFR_CLK_DIS_SHIFT                10
34496 #define SSI_SCR_RFR_CLK_DIS_MASK                 0x800u
34497 #define SSI_SCR_RFR_CLK_DIS_SHIFT                11
34498 #define SSI_SCR_SYNC_TX_FS_MASK                  0x1000u
34499 #define SSI_SCR_SYNC_TX_FS_SHIFT                 12
34500 /* SISR Bit Fields */
34501 #define SSI_SISR_TFE0_MASK                       0x1u
34502 #define SSI_SISR_TFE0_SHIFT                      0
34503 #define SSI_SISR_TFE1_MASK                       0x2u
34504 #define SSI_SISR_TFE1_SHIFT                      1
34505 #define SSI_SISR_RFF0_MASK                       0x4u
34506 #define SSI_SISR_RFF0_SHIFT                      2
34507 #define SSI_SISR_RFF1_MASK                       0x8u
34508 #define SSI_SISR_RFF1_SHIFT                      3
34509 #define SSI_SISR_RLS_MASK                        0x10u
34510 #define SSI_SISR_RLS_SHIFT                       4
34511 #define SSI_SISR_TLS_MASK                        0x20u
34512 #define SSI_SISR_TLS_SHIFT                       5
34513 #define SSI_SISR_RFS_MASK                        0x40u
34514 #define SSI_SISR_RFS_SHIFT                       6
34515 #define SSI_SISR_TFS_MASK                        0x80u
34516 #define SSI_SISR_TFS_SHIFT                       7
34517 #define SSI_SISR_TUE0_MASK                       0x100u
34518 #define SSI_SISR_TUE0_SHIFT                      8
34519 #define SSI_SISR_TUE1_MASK                       0x200u
34520 #define SSI_SISR_TUE1_SHIFT                      9
34521 #define SSI_SISR_ROE0_MASK                       0x400u
34522 #define SSI_SISR_ROE0_SHIFT                      10
34523 #define SSI_SISR_ROE1_MASK                       0x800u
34524 #define SSI_SISR_ROE1_SHIFT                      11
34525 #define SSI_SISR_TDE0_MASK                       0x1000u
34526 #define SSI_SISR_TDE0_SHIFT                      12
34527 #define SSI_SISR_TDE1_MASK                       0x2000u
34528 #define SSI_SISR_TDE1_SHIFT                      13
34529 #define SSI_SISR_RDR0_MASK                       0x4000u
34530 #define SSI_SISR_RDR0_SHIFT                      14
34531 #define SSI_SISR_RDR1_MASK                       0x8000u
34532 #define SSI_SISR_RDR1_SHIFT                      15
34533 #define SSI_SISR_RXT_MASK                        0x10000u
34534 #define SSI_SISR_RXT_SHIFT                       16
34535 #define SSI_SISR_CMDDU_MASK                      0x20000u
34536 #define SSI_SISR_CMDDU_SHIFT                     17
34537 #define SSI_SISR_CMDAU_MASK                      0x40000u
34538 #define SSI_SISR_CMDAU_SHIFT                     18
34539 #define SSI_SISR_TFRC_MASK                       0x800000u
34540 #define SSI_SISR_TFRC_SHIFT                      23
34541 #define SSI_SISR_RFRC_MASK                       0x1000000u
34542 #define SSI_SISR_RFRC_SHIFT                      24
34543 /* SIER Bit Fields */
34544 #define SSI_SIER_TFE0IE_MASK                     0x1u
34545 #define SSI_SIER_TFE0IE_SHIFT                    0
34546 #define SSI_SIER_TFE1IE_MASK                     0x2u
34547 #define SSI_SIER_TFE1IE_SHIFT                    1
34548 #define SSI_SIER_RFF0IE_MASK                     0x4u
34549 #define SSI_SIER_RFF0IE_SHIFT                    2
34550 #define SSI_SIER_RFF1IE_MASK                     0x8u
34551 #define SSI_SIER_RFF1IE_SHIFT                    3
34552 #define SSI_SIER_RLSIE_MASK                      0x10u
34553 #define SSI_SIER_RLSIE_SHIFT                     4
34554 #define SSI_SIER_TLSIE_MASK                      0x20u
34555 #define SSI_SIER_TLSIE_SHIFT                     5
34556 #define SSI_SIER_RFSIE_MASK                      0x40u
34557 #define SSI_SIER_RFSIE_SHIFT                     6
34558 #define SSI_SIER_TFSIE_MASK                      0x80u
34559 #define SSI_SIER_TFSIE_SHIFT                     7
34560 #define SSI_SIER_TUE0IE_MASK                     0x100u
34561 #define SSI_SIER_TUE0IE_SHIFT                    8
34562 #define SSI_SIER_TUE1IE_MASK                     0x200u
34563 #define SSI_SIER_TUE1IE_SHIFT                    9
34564 #define SSI_SIER_ROE0IE_MASK                     0x400u
34565 #define SSI_SIER_ROE0IE_SHIFT                    10
34566 #define SSI_SIER_ROE1IE_MASK                     0x800u
34567 #define SSI_SIER_ROE1IE_SHIFT                    11
34568 #define SSI_SIER_TDE0IE_MASK                     0x1000u
34569 #define SSI_SIER_TDE0IE_SHIFT                    12
34570 #define SSI_SIER_TDE1IE_MASK                     0x2000u
34571 #define SSI_SIER_TDE1IE_SHIFT                    13
34572 #define SSI_SIER_RDR0IE_MASK                     0x4000u
34573 #define SSI_SIER_RDR0IE_SHIFT                    14
34574 #define SSI_SIER_RDR1IE_MASK                     0x8000u
34575 #define SSI_SIER_RDR1IE_SHIFT                    15
34576 #define SSI_SIER_RXTIE_MASK                      0x10000u
34577 #define SSI_SIER_RXTIE_SHIFT                     16
34578 #define SSI_SIER_CMDDUIE_MASK                    0x20000u
34579 #define SSI_SIER_CMDDUIE_SHIFT                   17
34580 #define SSI_SIER_CMDAUIE_MASK                    0x40000u
34581 #define SSI_SIER_CMDAUIE_SHIFT                   18
34582 #define SSI_SIER_TIE_MASK                        0x80000u
34583 #define SSI_SIER_TIE_SHIFT                       19
34584 #define SSI_SIER_TDMAE_MASK                      0x100000u
34585 #define SSI_SIER_TDMAE_SHIFT                     20
34586 #define SSI_SIER_RIE_MASK                        0x200000u
34587 #define SSI_SIER_RIE_SHIFT                       21
34588 #define SSI_SIER_RDMAE_MASK                      0x400000u
34589 #define SSI_SIER_RDMAE_SHIFT                     22
34590 #define SSI_SIER_TFRCIE_MASK                     0x800000u
34591 #define SSI_SIER_TFRCIE_SHIFT                    23
34592 #define SSI_SIER_RFRCIE_MASK                     0x1000000u
34593 #define SSI_SIER_RFRCIE_SHIFT                    24
34594 /* STCR Bit Fields */
34595 #define SSI_STCR_TEFS_MASK                       0x1u
34596 #define SSI_STCR_TEFS_SHIFT                      0
34597 #define SSI_STCR_TFSL_MASK                       0x2u
34598 #define SSI_STCR_TFSL_SHIFT                      1
34599 #define SSI_STCR_TFSI_MASK                       0x4u
34600 #define SSI_STCR_TFSI_SHIFT                      2
34601 #define SSI_STCR_TSCKP_MASK                      0x8u
34602 #define SSI_STCR_TSCKP_SHIFT                     3
34603 #define SSI_STCR_TSHFD_MASK                      0x10u
34604 #define SSI_STCR_TSHFD_SHIFT                     4
34605 #define SSI_STCR_TXDIR_MASK                      0x20u
34606 #define SSI_STCR_TXDIR_SHIFT                     5
34607 #define SSI_STCR_TFDIR_MASK                      0x40u
34608 #define SSI_STCR_TFDIR_SHIFT                     6
34609 #define SSI_STCR_TFEN0_MASK                      0x80u
34610 #define SSI_STCR_TFEN0_SHIFT                     7
34611 #define SSI_STCR_TFEN1_MASK                      0x100u
34612 #define SSI_STCR_TFEN1_SHIFT                     8
34613 #define SSI_STCR_TXBIT0_MASK                     0x200u
34614 #define SSI_STCR_TXBIT0_SHIFT                    9
34615 /* SRCR Bit Fields */
34616 #define SSI_SRCR_REFS_MASK                       0x1u
34617 #define SSI_SRCR_REFS_SHIFT                      0
34618 #define SSI_SRCR_RFSL_MASK                       0x2u
34619 #define SSI_SRCR_RFSL_SHIFT                      1
34620 #define SSI_SRCR_RFSI_MASK                       0x4u
34621 #define SSI_SRCR_RFSI_SHIFT                      2
34622 #define SSI_SRCR_RSCKP_MASK                      0x8u
34623 #define SSI_SRCR_RSCKP_SHIFT                     3
34624 #define SSI_SRCR_RSHFD_MASK                      0x10u
34625 #define SSI_SRCR_RSHFD_SHIFT                     4
34626 #define SSI_SRCR_RXDIR_MASK                      0x20u
34627 #define SSI_SRCR_RXDIR_SHIFT                     5
34628 #define SSI_SRCR_RFDIR_MASK                      0x40u
34629 #define SSI_SRCR_RFDIR_SHIFT                     6
34630 #define SSI_SRCR_RFEN0_MASK                      0x80u
34631 #define SSI_SRCR_RFEN0_SHIFT                     7
34632 #define SSI_SRCR_RFEN1_MASK                      0x100u
34633 #define SSI_SRCR_RFEN1_SHIFT                     8
34634 #define SSI_SRCR_RXBIT0_MASK                     0x200u
34635 #define SSI_SRCR_RXBIT0_SHIFT                    9
34636 #define SSI_SRCR_RXEXT_MASK                      0x400u
34637 #define SSI_SRCR_RXEXT_SHIFT                     10
34638 /* STCCR Bit Fields */
34639 #define SSI_STCCR_PM7_PM0_MASK                   0xFFu
34640 #define SSI_STCCR_PM7_PM0_SHIFT                  0
34641 #define SSI_STCCR_PM7_PM0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_PM7_PM0_SHIFT))&SSI_STCCR_PM7_PM0_MASK)
34642 #define SSI_STCCR_DC4_DC0_MASK                   0x1F00u
34643 #define SSI_STCCR_DC4_DC0_SHIFT                  8
34644 #define SSI_STCCR_DC4_DC0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_DC4_DC0_SHIFT))&SSI_STCCR_DC4_DC0_MASK)
34645 #define SSI_STCCR_WL3_WL0_MASK                   0x1E000u
34646 #define SSI_STCCR_WL3_WL0_SHIFT                  13
34647 #define SSI_STCCR_WL3_WL0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_WL3_WL0_SHIFT))&SSI_STCCR_WL3_WL0_MASK)
34648 #define SSI_STCCR_PSR_MASK                       0x20000u
34649 #define SSI_STCCR_PSR_SHIFT                      17
34650 #define SSI_STCCR_DIV2_MASK                      0x40000u
34651 #define SSI_STCCR_DIV2_SHIFT                     18
34652 /* SRCCR Bit Fields */
34653 #define SSI_SRCCR_PM7_PM0_MASK                   0xFFu
34654 #define SSI_SRCCR_PM7_PM0_SHIFT                  0
34655 #define SSI_SRCCR_PM7_PM0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_PM7_PM0_SHIFT))&SSI_SRCCR_PM7_PM0_MASK)
34656 #define SSI_SRCCR_DC4_DC0_MASK                   0x1F00u
34657 #define SSI_SRCCR_DC4_DC0_SHIFT                  8
34658 #define SSI_SRCCR_DC4_DC0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_DC4_DC0_SHIFT))&SSI_SRCCR_DC4_DC0_MASK)
34659 #define SSI_SRCCR_WL3_WL0_MASK                   0x1E000u
34660 #define SSI_SRCCR_WL3_WL0_SHIFT                  13
34661 #define SSI_SRCCR_WL3_WL0(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_WL3_WL0_SHIFT))&SSI_SRCCR_WL3_WL0_MASK)
34662 #define SSI_SRCCR_PSR_MASK                       0x20000u
34663 #define SSI_SRCCR_PSR_SHIFT                      17
34664 #define SSI_SRCCR_DIV2_MASK                      0x40000u
34665 #define SSI_SRCCR_DIV2_SHIFT                     18
34666 /* SFCSR Bit Fields */
34667 #define SSI_SFCSR_TFWM0_MASK                     0xFu
34668 #define SSI_SFCSR_TFWM0_SHIFT                    0
34669 #define SSI_SFCSR_TFWM0(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFWM0_SHIFT))&SSI_SFCSR_TFWM0_MASK)
34670 #define SSI_SFCSR_RFWM0_MASK                     0xF0u
34671 #define SSI_SFCSR_RFWM0_SHIFT                    4
34672 #define SSI_SFCSR_RFWM0(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFWM0_SHIFT))&SSI_SFCSR_RFWM0_MASK)
34673 #define SSI_SFCSR_TFCNT0_MASK                    0xF00u
34674 #define SSI_SFCSR_TFCNT0_SHIFT                   8
34675 #define SSI_SFCSR_TFCNT0(x)                      (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFCNT0_SHIFT))&SSI_SFCSR_TFCNT0_MASK)
34676 #define SSI_SFCSR_RFCNT0_MASK                    0xF000u
34677 #define SSI_SFCSR_RFCNT0_SHIFT                   12
34678 #define SSI_SFCSR_RFCNT0(x)                      (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFCNT0_SHIFT))&SSI_SFCSR_RFCNT0_MASK)
34679 #define SSI_SFCSR_TFWM1_MASK                     0xF0000u
34680 #define SSI_SFCSR_TFWM1_SHIFT                    16
34681 #define SSI_SFCSR_TFWM1(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFWM1_SHIFT))&SSI_SFCSR_TFWM1_MASK)
34682 #define SSI_SFCSR_RFWM1_MASK                     0xF00000u
34683 #define SSI_SFCSR_RFWM1_SHIFT                    20
34684 #define SSI_SFCSR_RFWM1(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFWM1_SHIFT))&SSI_SFCSR_RFWM1_MASK)
34685 #define SSI_SFCSR_TFCNT1_MASK                    0xF000000u
34686 #define SSI_SFCSR_TFCNT1_SHIFT                   24
34687 #define SSI_SFCSR_TFCNT1(x)                      (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFCNT1_SHIFT))&SSI_SFCSR_TFCNT1_MASK)
34688 #define SSI_SFCSR_RFCNT1_MASK                    0xF0000000u
34689 #define SSI_SFCSR_RFCNT1_SHIFT                   28
34690 #define SSI_SFCSR_RFCNT1(x)                      (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFCNT1_SHIFT))&SSI_SFCSR_RFCNT1_MASK)
34691 /* SACNT Bit Fields */
34692 #define SSI_SACNT_AC97EN_MASK                    0x1u
34693 #define SSI_SACNT_AC97EN_SHIFT                   0
34694 #define SSI_SACNT_FV_MASK                        0x2u
34695 #define SSI_SACNT_FV_SHIFT                       1
34696 #define SSI_SACNT_TIF_MASK                       0x4u
34697 #define SSI_SACNT_TIF_SHIFT                      2
34698 #define SSI_SACNT_RD_MASK                        0x8u
34699 #define SSI_SACNT_RD_SHIFT                       3
34700 #define SSI_SACNT_WR_MASK                        0x10u
34701 #define SSI_SACNT_WR_SHIFT                       4
34702 #define SSI_SACNT_FRDIV_MASK                     0x7E0u
34703 #define SSI_SACNT_FRDIV_SHIFT                    5
34704 #define SSI_SACNT_FRDIV(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SACNT_FRDIV_SHIFT))&SSI_SACNT_FRDIV_MASK)
34705 /* SACADD Bit Fields */
34706 #define SSI_SACADD_SACADD_MASK                   0x7FFFFu
34707 #define SSI_SACADD_SACADD_SHIFT                  0
34708 #define SSI_SACADD_SACADD(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SACADD_SACADD_SHIFT))&SSI_SACADD_SACADD_MASK)
34709 /* SACDAT Bit Fields */
34710 #define SSI_SACDAT_SACDAT_MASK                   0xFFFFFu
34711 #define SSI_SACDAT_SACDAT_SHIFT                  0
34712 #define SSI_SACDAT_SACDAT(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SACDAT_SACDAT_SHIFT))&SSI_SACDAT_SACDAT_MASK)
34713 /* SATAG Bit Fields */
34714 #define SSI_SATAG_SATAG_MASK                     0xFFFFu
34715 #define SSI_SATAG_SATAG_SHIFT                    0
34716 #define SSI_SATAG_SATAG(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SATAG_SATAG_SHIFT))&SSI_SATAG_SATAG_MASK)
34717 /* STMSK Bit Fields */
34718 #define SSI_STMSK_STMSK_MASK                     0xFFFFFFFFu
34719 #define SSI_STMSK_STMSK_SHIFT                    0
34720 #define SSI_STMSK_STMSK(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_STMSK_STMSK_SHIFT))&SSI_STMSK_STMSK_MASK)
34721 /* SRMSK Bit Fields */
34722 #define SSI_SRMSK_SRMSK_MASK                     0xFFFFFFFFu
34723 #define SSI_SRMSK_SRMSK_SHIFT                    0
34724 #define SSI_SRMSK_SRMSK(x)                       (((uint32_t)(((uint32_t)(x))<<SSI_SRMSK_SRMSK_SHIFT))&SSI_SRMSK_SRMSK_MASK)
34725 /* SACCST Bit Fields */
34726 #define SSI_SACCST_SACCST_MASK                   0x3FFu
34727 #define SSI_SACCST_SACCST_SHIFT                  0
34728 #define SSI_SACCST_SACCST(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SACCST_SACCST_SHIFT))&SSI_SACCST_SACCST_MASK)
34729 /* SACCEN Bit Fields */
34730 #define SSI_SACCEN_SACCEN_MASK                   0x3FFu
34731 #define SSI_SACCEN_SACCEN_SHIFT                  0
34732 #define SSI_SACCEN_SACCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SSI_SACCEN_SACCEN_SHIFT))&SSI_SACCEN_SACCEN_MASK)
34733 /* SACCDIS Bit Fields */
34734 #define SSI_SACCDIS_SACCDIS_MASK                 0x3FFu
34735 #define SSI_SACCDIS_SACCDIS_SHIFT                0
34736 #define SSI_SACCDIS_SACCDIS(x)                   (((uint32_t)(((uint32_t)(x))<<SSI_SACCDIS_SACCDIS_SHIFT))&SSI_SACCDIS_SACCDIS_MASK)
34737 
34738 /*!
34739  * @}
34740  */ /* end of group SSI_Register_Masks */
34741 
34742 /* SSI - Peripheral instance base addresses */
34743 /** Peripheral SSI1 base address */
34744 #define SSI1_BASE                                (0x42028000u)
34745 /** Peripheral SSI1 base pointer */
34746 #define SSI1                                     ((SSI_Type *)SSI1_BASE)
34747 #define SSI1_BASE_PTR                            (SSI1)
34748 /** Peripheral SSI2 base address */
34749 #define SSI2_BASE                                (0x4202C000u)
34750 /** Peripheral SSI2 base pointer */
34751 #define SSI2                                     ((SSI_Type *)SSI2_BASE)
34752 #define SSI2_BASE_PTR                            (SSI2)
34753 /** Peripheral SSI3 base address */
34754 #define SSI3_BASE                                (0x42030000u)
34755 /** Peripheral SSI3 base pointer */
34756 #define SSI3                                     ((SSI_Type *)SSI3_BASE)
34757 #define SSI3_BASE_PTR                            (SSI3)
34758 /** Array initializer of SSI peripheral base addresses */
34759 #define SSI_BASE_ADDRS                           { SSI1_BASE, SSI2_BASE, SSI3_BASE }
34760 /** Array initializer of SSI peripheral base pointers */
34761 #define SSI_BASE_PTRS                            { SSI1, SSI2, SSI3 }
34762 /** Interrupt vectors for the SSI peripheral type */
34763 #define SSI_IRQS                                 { SSI1_IRQn, SSI2_IRQn, SSI3_IRQn }
34764 
34765 /* ----------------------------------------------------------------------------
34766    -- SSI - Register accessor macros
34767    ---------------------------------------------------------------------------- */
34768 
34769 /*!
34770  * @addtogroup SSI_Register_Accessor_Macros SSI - Register accessor macros
34771  * @{
34772  */
34773 
34774 /* SSI - Register instance definitions */
34775 /* SSI1 */
34776 #define SSI1_STX0                                SSI_STX_REG(SSI1_BASE_PTR,0)
34777 #define SSI1_STX1                                SSI_STX_REG(SSI1_BASE_PTR,1)
34778 #define SSI1_SRX0                                SSI_SRX_REG(SSI1_BASE_PTR,0)
34779 #define SSI1_SRX1                                SSI_SRX_REG(SSI1_BASE_PTR,1)
34780 #define SSI1_SCR                                 SSI_SCR_REG(SSI1_BASE_PTR)
34781 #define SSI1_SISR                                SSI_SISR_REG(SSI1_BASE_PTR)
34782 #define SSI1_SIER                                SSI_SIER_REG(SSI1_BASE_PTR)
34783 #define SSI1_STCR                                SSI_STCR_REG(SSI1_BASE_PTR)
34784 #define SSI1_SRCR                                SSI_SRCR_REG(SSI1_BASE_PTR)
34785 #define SSI1_STCCR                               SSI_STCCR_REG(SSI1_BASE_PTR)
34786 #define SSI1_SRCCR                               SSI_SRCCR_REG(SSI1_BASE_PTR)
34787 #define SSI1_SFCSR                               SSI_SFCSR_REG(SSI1_BASE_PTR)
34788 #define SSI1_SACNT                               SSI_SACNT_REG(SSI1_BASE_PTR)
34789 #define SSI1_SACADD                              SSI_SACADD_REG(SSI1_BASE_PTR)
34790 #define SSI1_SACDAT                              SSI_SACDAT_REG(SSI1_BASE_PTR)
34791 #define SSI1_SATAG                               SSI_SATAG_REG(SSI1_BASE_PTR)
34792 #define SSI1_STMSK                               SSI_STMSK_REG(SSI1_BASE_PTR)
34793 #define SSI1_SRMSK                               SSI_SRMSK_REG(SSI1_BASE_PTR)
34794 #define SSI1_SACCST                              SSI_SACCST_REG(SSI1_BASE_PTR)
34795 #define SSI1_SACCEN                              SSI_SACCEN_REG(SSI1_BASE_PTR)
34796 #define SSI1_SACCDIS                             SSI_SACCDIS_REG(SSI1_BASE_PTR)
34797 /* SSI2 */
34798 #define SSI2_STX0                                SSI_STX_REG(SSI2_BASE_PTR,0)
34799 #define SSI2_STX1                                SSI_STX_REG(SSI2_BASE_PTR,1)
34800 #define SSI2_SRX0                                SSI_SRX_REG(SSI2_BASE_PTR,0)
34801 #define SSI2_SRX1                                SSI_SRX_REG(SSI2_BASE_PTR,1)
34802 #define SSI2_SCR                                 SSI_SCR_REG(SSI2_BASE_PTR)
34803 #define SSI2_SISR                                SSI_SISR_REG(SSI2_BASE_PTR)
34804 #define SSI2_SIER                                SSI_SIER_REG(SSI2_BASE_PTR)
34805 #define SSI2_STCR                                SSI_STCR_REG(SSI2_BASE_PTR)
34806 #define SSI2_SRCR                                SSI_SRCR_REG(SSI2_BASE_PTR)
34807 #define SSI2_STCCR                               SSI_STCCR_REG(SSI2_BASE_PTR)
34808 #define SSI2_SRCCR                               SSI_SRCCR_REG(SSI2_BASE_PTR)
34809 #define SSI2_SFCSR                               SSI_SFCSR_REG(SSI2_BASE_PTR)
34810 #define SSI2_SACNT                               SSI_SACNT_REG(SSI2_BASE_PTR)
34811 #define SSI2_SACADD                              SSI_SACADD_REG(SSI2_BASE_PTR)
34812 #define SSI2_SACDAT                              SSI_SACDAT_REG(SSI2_BASE_PTR)
34813 #define SSI2_SATAG                               SSI_SATAG_REG(SSI2_BASE_PTR)
34814 #define SSI2_STMSK                               SSI_STMSK_REG(SSI2_BASE_PTR)
34815 #define SSI2_SRMSK                               SSI_SRMSK_REG(SSI2_BASE_PTR)
34816 #define SSI2_SACCST                              SSI_SACCST_REG(SSI2_BASE_PTR)
34817 #define SSI2_SACCEN                              SSI_SACCEN_REG(SSI2_BASE_PTR)
34818 #define SSI2_SACCDIS                             SSI_SACCDIS_REG(SSI2_BASE_PTR)
34819 /* SSI3 */
34820 #define SSI3_STX0                                SSI_STX_REG(SSI3_BASE_PTR,0)
34821 #define SSI3_STX1                                SSI_STX_REG(SSI3_BASE_PTR,1)
34822 #define SSI3_SRX0                                SSI_SRX_REG(SSI3_BASE_PTR,0)
34823 #define SSI3_SRX1                                SSI_SRX_REG(SSI3_BASE_PTR,1)
34824 #define SSI3_SCR                                 SSI_SCR_REG(SSI3_BASE_PTR)
34825 #define SSI3_SISR                                SSI_SISR_REG(SSI3_BASE_PTR)
34826 #define SSI3_SIER                                SSI_SIER_REG(SSI3_BASE_PTR)
34827 #define SSI3_STCR                                SSI_STCR_REG(SSI3_BASE_PTR)
34828 #define SSI3_SRCR                                SSI_SRCR_REG(SSI3_BASE_PTR)
34829 #define SSI3_STCCR                               SSI_STCCR_REG(SSI3_BASE_PTR)
34830 #define SSI3_SRCCR                               SSI_SRCCR_REG(SSI3_BASE_PTR)
34831 #define SSI3_SFCSR                               SSI_SFCSR_REG(SSI3_BASE_PTR)
34832 #define SSI3_SACNT                               SSI_SACNT_REG(SSI3_BASE_PTR)
34833 #define SSI3_SACADD                              SSI_SACADD_REG(SSI3_BASE_PTR)
34834 #define SSI3_SACDAT                              SSI_SACDAT_REG(SSI3_BASE_PTR)
34835 #define SSI3_SATAG                               SSI_SATAG_REG(SSI3_BASE_PTR)
34836 #define SSI3_STMSK                               SSI_STMSK_REG(SSI3_BASE_PTR)
34837 #define SSI3_SRMSK                               SSI_SRMSK_REG(SSI3_BASE_PTR)
34838 #define SSI3_SACCST                              SSI_SACCST_REG(SSI3_BASE_PTR)
34839 #define SSI3_SACCEN                              SSI_SACCEN_REG(SSI3_BASE_PTR)
34840 #define SSI3_SACCDIS                             SSI_SACCDIS_REG(SSI3_BASE_PTR)
34841 /* SSI - Register array accessors */
34842 #define SSI1_STX(index)                          SSI_STX_REG(SSI1_BASE_PTR,index)
34843 #define SSI2_STX(index)                          SSI_STX_REG(SSI2_BASE_PTR,index)
34844 #define SSI3_STX(index)                          SSI_STX_REG(SSI3_BASE_PTR,index)
34845 #define SSI1_SRX(index)                          SSI_SRX_REG(SSI1_BASE_PTR,index)
34846 #define SSI2_SRX(index)                          SSI_SRX_REG(SSI2_BASE_PTR,index)
34847 #define SSI3_SRX(index)                          SSI_SRX_REG(SSI3_BASE_PTR,index)
34848 
34849 /*!
34850  * @}
34851  */ /* end of group SSI_Register_Accessor_Macros */
34852 
34853 /*!
34854  * @}
34855  */ /* end of group SSI_Peripheral */
34856 
34857 /* ----------------------------------------------------------------------------
34858    -- TEMPMON Peripheral Access Layer
34859    ---------------------------------------------------------------------------- */
34860 
34861 /*!
34862  * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
34863  * @{
34864  */
34865 
34866 /** TEMPMON - Register Layout Typedef */
34867 typedef struct {
34868   uint8_t RESERVED_0[384];
34869   __IO  uint32_t TEMPSENSE0;                             /**< Tempsensor Control Register 0, offset: 0x180 */
34870   __IO  uint32_t TEMPSENSE0_SET;                         /**< Tempsensor Control Register 0, offset: 0x184 */
34871   __IO  uint32_t TEMPSENSE0_CLR;                         /**< Tempsensor Control Register 0, offset: 0x188 */
34872   __IO  uint32_t TEMPSENSE0_TOG;                         /**< Tempsensor Control Register 0, offset: 0x18C */
34873   __IO  uint32_t TEMPSENSE1;                             /**< Tempsensor Control Register 1, offset: 0x190 */
34874   __IO  uint32_t TEMPSENSE1_SET;                         /**< Tempsensor Control Register 1, offset: 0x194 */
34875   __IO  uint32_t TEMPSENSE1_CLR;                         /**< Tempsensor Control Register 1, offset: 0x198 */
34876   __IO  uint32_t TEMPSENSE1_TOG;                         /**< Tempsensor Control Register 1, offset: 0x19C */
34877   uint8_t RESERVED_1[240];
34878   __IO  uint32_t TEMPSENSE2;                             /**< Tempsensor Control Register 2, offset: 0x290 */
34879   __IO  uint32_t TEMPSENSE2_SET;                         /**< Tempsensor Control Register 2, offset: 0x294 */
34880   __IO  uint32_t TEMPSENSE2_CLR;                         /**< Tempsensor Control Register 2, offset: 0x298 */
34881   __IO  uint32_t TEMPSENSE2_TOG;                         /**< Tempsensor Control Register 2, offset: 0x29C */
34882 } TEMPMON_Type, *TEMPMON_MemMapPtr;
34883 
34884 /* ----------------------------------------------------------------------------
34885    -- TEMPMON - Register accessor macros
34886    ---------------------------------------------------------------------------- */
34887 
34888 /*!
34889  * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros
34890  * @{
34891  */
34892 
34893 /* TEMPMON - Register accessors */
34894 #define TEMPMON_TEMPSENSE0_REG(base)             ((base)->TEMPSENSE0)
34895 #define TEMPMON_TEMPSENSE0_SET_REG(base)         ((base)->TEMPSENSE0_SET)
34896 #define TEMPMON_TEMPSENSE0_CLR_REG(base)         ((base)->TEMPSENSE0_CLR)
34897 #define TEMPMON_TEMPSENSE0_TOG_REG(base)         ((base)->TEMPSENSE0_TOG)
34898 #define TEMPMON_TEMPSENSE1_REG(base)             ((base)->TEMPSENSE1)
34899 #define TEMPMON_TEMPSENSE1_SET_REG(base)         ((base)->TEMPSENSE1_SET)
34900 #define TEMPMON_TEMPSENSE1_CLR_REG(base)         ((base)->TEMPSENSE1_CLR)
34901 #define TEMPMON_TEMPSENSE1_TOG_REG(base)         ((base)->TEMPSENSE1_TOG)
34902 #define TEMPMON_TEMPSENSE2_REG(base)             ((base)->TEMPSENSE2)
34903 #define TEMPMON_TEMPSENSE2_SET_REG(base)         ((base)->TEMPSENSE2_SET)
34904 #define TEMPMON_TEMPSENSE2_CLR_REG(base)         ((base)->TEMPSENSE2_CLR)
34905 #define TEMPMON_TEMPSENSE2_TOG_REG(base)         ((base)->TEMPSENSE2_TOG)
34906 
34907 /*!
34908  * @}
34909  */ /* end of group TEMPMON_Register_Accessor_Macros */
34910 
34911 /* ----------------------------------------------------------------------------
34912    -- TEMPMON Register Masks
34913    ---------------------------------------------------------------------------- */
34914 
34915 /*!
34916  * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
34917  * @{
34918  */
34919 
34920 /* TEMPSENSE0 Bit Fields */
34921 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK       0x1u
34922 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT      0
34923 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK     0x2u
34924 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT    1
34925 #define TEMPMON_TEMPSENSE0_FINISHED_MASK         0x4u
34926 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT        2
34927 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK         0xFFF00u
34928 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT        8
34929 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x)           (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
34930 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK      0xFFF00000u
34931 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT     20
34932 #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x)        (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
34933 /* TEMPSENSE0_SET Bit Fields */
34934 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK   0x1u
34935 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT  0
34936 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK 0x2u
34937 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT 1
34938 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK     0x4u
34939 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT    2
34940 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK     0xFFF00u
34941 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT    8
34942 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
34943 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK  0xFFF00000u
34944 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT 20
34945 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
34946 /* TEMPSENSE0_CLR Bit Fields */
34947 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK   0x1u
34948 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT  0
34949 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK 0x2u
34950 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT 1
34951 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK     0x4u
34952 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT    2
34953 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK     0xFFF00u
34954 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT    8
34955 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
34956 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK  0xFFF00000u
34957 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT 20
34958 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
34959 /* TEMPSENSE0_TOG Bit Fields */
34960 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK   0x1u
34961 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT  0
34962 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK 0x2u
34963 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT 1
34964 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK     0x4u
34965 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT    2
34966 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK     0xFFF00u
34967 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT    8
34968 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
34969 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK  0xFFF00000u
34970 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT 20
34971 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
34972 /* TEMPSENSE1 Bit Fields */
34973 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK     0xFFFFu
34974 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT    0
34975 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x)       (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
34976 /* TEMPSENSE1_SET Bit Fields */
34977 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFFu
34978 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 0
34979 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
34980 /* TEMPSENSE1_CLR Bit Fields */
34981 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFFu
34982 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 0
34983 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
34984 /* TEMPSENSE1_TOG Bit Fields */
34985 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFFu
34986 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 0
34987 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
34988 /* TEMPSENSE2 Bit Fields */
34989 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK  0xFFFu
34990 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT 0
34991 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
34992 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK 0xFFF0000u
34993 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT 16
34994 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x)  (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
34995 /* TEMPSENSE2_SET Bit Fields */
34996 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK 0xFFFu
34997 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT 0
34998 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
34999 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK 0xFFF0000u
35000 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT 16
35001 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
35002 /* TEMPSENSE2_CLR Bit Fields */
35003 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK 0xFFFu
35004 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT 0
35005 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
35006 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK 0xFFF0000u
35007 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT 16
35008 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
35009 /* TEMPSENSE2_TOG Bit Fields */
35010 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK 0xFFFu
35011 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT 0
35012 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
35013 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK 0xFFF0000u
35014 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT 16
35015 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
35016 
35017 /*!
35018  * @}
35019  */ /* end of group TEMPMON_Register_Masks */
35020 
35021 /* TEMPMON - Peripheral instance base addresses */
35022 /** Peripheral TEMPMON base address */
35023 #define TEMPMON_BASE                             (0x420C8000u)
35024 /** Peripheral TEMPMON base pointer */
35025 #define TEMPMON                                  ((TEMPMON_Type *)TEMPMON_BASE)
35026 #define TEMPMON_BASE_PTR                         (TEMPMON)
35027 /** Array initializer of TEMPMON peripheral base addresses */
35028 #define TEMPMON_BASE_ADDRS                       { TEMPMON_BASE }
35029 /** Array initializer of TEMPMON peripheral base pointers */
35030 #define TEMPMON_BASE_PTRS                        { TEMPMON }
35031 
35032 /* ----------------------------------------------------------------------------
35033    -- TEMPMON - Register accessor macros
35034    ---------------------------------------------------------------------------- */
35035 
35036 /*!
35037  * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros
35038  * @{
35039  */
35040 
35041 /* TEMPMON - Register instance definitions */
35042 /* TEMPMON */
35043 #define TEMPMON_TEMPSENSE0                       TEMPMON_TEMPSENSE0_REG(TEMPMON_BASE_PTR)
35044 #define TEMPMON_TEMPSENSE0_SET                   TEMPMON_TEMPSENSE0_SET_REG(TEMPMON_BASE_PTR)
35045 #define TEMPMON_TEMPSENSE0_CLR                   TEMPMON_TEMPSENSE0_CLR_REG(TEMPMON_BASE_PTR)
35046 #define TEMPMON_TEMPSENSE0_TOG                   TEMPMON_TEMPSENSE0_TOG_REG(TEMPMON_BASE_PTR)
35047 #define TEMPMON_TEMPSENSE1                       TEMPMON_TEMPSENSE1_REG(TEMPMON_BASE_PTR)
35048 #define TEMPMON_TEMPSENSE1_SET                   TEMPMON_TEMPSENSE1_SET_REG(TEMPMON_BASE_PTR)
35049 #define TEMPMON_TEMPSENSE1_CLR                   TEMPMON_TEMPSENSE1_CLR_REG(TEMPMON_BASE_PTR)
35050 #define TEMPMON_TEMPSENSE1_TOG                   TEMPMON_TEMPSENSE1_TOG_REG(TEMPMON_BASE_PTR)
35051 #define TEMPMON_TEMPSENSE2                       TEMPMON_TEMPSENSE2_REG(TEMPMON_BASE_PTR)
35052 #define TEMPMON_TEMPSENSE2_SET                   TEMPMON_TEMPSENSE2_SET_REG(TEMPMON_BASE_PTR)
35053 #define TEMPMON_TEMPSENSE2_CLR                   TEMPMON_TEMPSENSE2_CLR_REG(TEMPMON_BASE_PTR)
35054 #define TEMPMON_TEMPSENSE2_TOG                   TEMPMON_TEMPSENSE2_TOG_REG(TEMPMON_BASE_PTR)
35055 
35056 /*!
35057  * @}
35058  */ /* end of group TEMPMON_Register_Accessor_Macros */
35059 
35060 /*!
35061  * @}
35062  */ /* end of group TEMPMON_Peripheral */
35063 
35064 /* ----------------------------------------------------------------------------
35065    -- UART Peripheral Access Layer
35066    ---------------------------------------------------------------------------- */
35067 
35068 /*!
35069  * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
35070  * @{
35071  */
35072 
35073 /** UART - Register Layout Typedef */
35074 typedef struct {
35075   __I   uint32_t URXD;                                   /**< UART Receiver Register, offset: 0x0 */
35076   uint8_t RESERVED_0[60];
35077   __O   uint32_t UTXD;                                   /**< UART Transmitter Register, offset: 0x40 */
35078   uint8_t RESERVED_1[60];
35079   __IO  uint32_t UCR1;                                   /**< UART Control Register 1, offset: 0x80 */
35080   __IO  uint32_t UCR2;                                   /**< UART Control Register 2, offset: 0x84 */
35081   __IO  uint32_t UCR3;                                   /**< UART Control Register 3, offset: 0x88 */
35082   __IO  uint32_t UCR4;                                   /**< UART Control Register 4, offset: 0x8C */
35083   __IO  uint32_t UFCR;                                   /**< UART FIFO Control Register, offset: 0x90 */
35084   __IO  uint32_t USR1;                                   /**< UART Status Register 1, offset: 0x94 */
35085   __IO  uint32_t USR2;                                   /**< UART Status Register 2, offset: 0x98 */
35086   __IO  uint32_t UESC;                                   /**< UART Escape Character Register, offset: 0x9C */
35087   __IO  uint32_t UTIM;                                   /**< UART Escape Timer Register, offset: 0xA0 */
35088   __IO  uint32_t UBIR;                                   /**< UART BRM Incremental Register, offset: 0xA4 */
35089   __IO  uint32_t UBMR;                                   /**< UART BRM Modulator Register, offset: 0xA8 */
35090   __I   uint32_t UBRC;                                   /**< UART Baud Rate Count Register, offset: 0xAC */
35091   __IO  uint32_t ONEMS;                                  /**< UART One Millisecond Register, offset: 0xB0 */
35092   __IO  uint32_t UTS;                                    /**< UART Test Register, offset: 0xB4 */
35093   __IO  uint32_t UMCR;                                   /**< UART RS-485 Mode Control Register, offset: 0xB8 */
35094 } UART_Type, *UART_MemMapPtr;
35095 
35096 /* ----------------------------------------------------------------------------
35097    -- UART - Register accessor macros
35098    ---------------------------------------------------------------------------- */
35099 
35100 /*!
35101  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
35102  * @{
35103  */
35104 
35105 /* UART - Register accessors */
35106 #define UART_URXD_REG(base)                      ((base)->URXD)
35107 #define UART_UTXD_REG(base)                      ((base)->UTXD)
35108 #define UART_UCR1_REG(base)                      ((base)->UCR1)
35109 #define UART_UCR2_REG(base)                      ((base)->UCR2)
35110 #define UART_UCR3_REG(base)                      ((base)->UCR3)
35111 #define UART_UCR4_REG(base)                      ((base)->UCR4)
35112 #define UART_UFCR_REG(base)                      ((base)->UFCR)
35113 #define UART_USR1_REG(base)                      ((base)->USR1)
35114 #define UART_USR2_REG(base)                      ((base)->USR2)
35115 #define UART_UESC_REG(base)                      ((base)->UESC)
35116 #define UART_UTIM_REG(base)                      ((base)->UTIM)
35117 #define UART_UBIR_REG(base)                      ((base)->UBIR)
35118 #define UART_UBMR_REG(base)                      ((base)->UBMR)
35119 #define UART_UBRC_REG(base)                      ((base)->UBRC)
35120 #define UART_ONEMS_REG(base)                     ((base)->ONEMS)
35121 #define UART_UTS_REG(base)                       ((base)->UTS)
35122 #define UART_UMCR_REG(base)                      ((base)->UMCR)
35123 
35124 /*!
35125  * @}
35126  */ /* end of group UART_Register_Accessor_Macros */
35127 
35128 /* ----------------------------------------------------------------------------
35129    -- UART Register Masks
35130    ---------------------------------------------------------------------------- */
35131 
35132 /*!
35133  * @addtogroup UART_Register_Masks UART Register Masks
35134  * @{
35135  */
35136 
35137 /* URXD Bit Fields */
35138 #define UART_URXD_RX_DATA_MASK                   0xFFu
35139 #define UART_URXD_RX_DATA_SHIFT                  0
35140 #define UART_URXD_RX_DATA(x)                     (((uint32_t)(((uint32_t)(x))<<UART_URXD_RX_DATA_SHIFT))&UART_URXD_RX_DATA_MASK)
35141 #define UART_URXD_PRERR_MASK                     0x400u
35142 #define UART_URXD_PRERR_SHIFT                    10
35143 #define UART_URXD_BRK_MASK                       0x800u
35144 #define UART_URXD_BRK_SHIFT                      11
35145 #define UART_URXD_FRMERR_MASK                    0x1000u
35146 #define UART_URXD_FRMERR_SHIFT                   12
35147 #define UART_URXD_OVRRUN_MASK                    0x2000u
35148 #define UART_URXD_OVRRUN_SHIFT                   13
35149 #define UART_URXD_ERR_MASK                       0x4000u
35150 #define UART_URXD_ERR_SHIFT                      14
35151 #define UART_URXD_CHARRDY_MASK                   0x8000u
35152 #define UART_URXD_CHARRDY_SHIFT                  15
35153 /* UTXD Bit Fields */
35154 #define UART_UTXD_TX_DATA_MASK                   0xFFu
35155 #define UART_UTXD_TX_DATA_SHIFT                  0
35156 #define UART_UTXD_TX_DATA(x)                     (((uint32_t)(((uint32_t)(x))<<UART_UTXD_TX_DATA_SHIFT))&UART_UTXD_TX_DATA_MASK)
35157 /* UCR1 Bit Fields */
35158 #define UART_UCR1_UARTEN_MASK                    0x1u
35159 #define UART_UCR1_UARTEN_SHIFT                   0
35160 #define UART_UCR1_DOZE_MASK                      0x2u
35161 #define UART_UCR1_DOZE_SHIFT                     1
35162 #define UART_UCR1_ATDMAEN_MASK                   0x4u
35163 #define UART_UCR1_ATDMAEN_SHIFT                  2
35164 #define UART_UCR1_TXDMAEN_MASK                   0x8u
35165 #define UART_UCR1_TXDMAEN_SHIFT                  3
35166 #define UART_UCR1_SNDBRK_MASK                    0x10u
35167 #define UART_UCR1_SNDBRK_SHIFT                   4
35168 #define UART_UCR1_RTSDEN_MASK                    0x20u
35169 #define UART_UCR1_RTSDEN_SHIFT                   5
35170 #define UART_UCR1_TXMPTYEN_MASK                  0x40u
35171 #define UART_UCR1_TXMPTYEN_SHIFT                 6
35172 #define UART_UCR1_IREN_MASK                      0x80u
35173 #define UART_UCR1_IREN_SHIFT                     7
35174 #define UART_UCR1_RXDMAEN_MASK                   0x100u
35175 #define UART_UCR1_RXDMAEN_SHIFT                  8
35176 #define UART_UCR1_RRDYEN_MASK                    0x200u
35177 #define UART_UCR1_RRDYEN_SHIFT                   9
35178 #define UART_UCR1_ICD_MASK                       0xC00u
35179 #define UART_UCR1_ICD_SHIFT                      10
35180 #define UART_UCR1_ICD(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UCR1_ICD_SHIFT))&UART_UCR1_ICD_MASK)
35181 #define UART_UCR1_IDEN_MASK                      0x1000u
35182 #define UART_UCR1_IDEN_SHIFT                     12
35183 #define UART_UCR1_TRDYEN_MASK                    0x2000u
35184 #define UART_UCR1_TRDYEN_SHIFT                   13
35185 #define UART_UCR1_ADBR_MASK                      0x4000u
35186 #define UART_UCR1_ADBR_SHIFT                     14
35187 #define UART_UCR1_ADEN_MASK                      0x8000u
35188 #define UART_UCR1_ADEN_SHIFT                     15
35189 /* UCR2 Bit Fields */
35190 #define UART_UCR2_SRST_MASK                      0x1u
35191 #define UART_UCR2_SRST_SHIFT                     0
35192 #define UART_UCR2_RXEN_MASK                      0x2u
35193 #define UART_UCR2_RXEN_SHIFT                     1
35194 #define UART_UCR2_TXEN_MASK                      0x4u
35195 #define UART_UCR2_TXEN_SHIFT                     2
35196 #define UART_UCR2_ATEN_MASK                      0x8u
35197 #define UART_UCR2_ATEN_SHIFT                     3
35198 #define UART_UCR2_RTSEN_MASK                     0x10u
35199 #define UART_UCR2_RTSEN_SHIFT                    4
35200 #define UART_UCR2_WS_MASK                        0x20u
35201 #define UART_UCR2_WS_SHIFT                       5
35202 #define UART_UCR2_STPB_MASK                      0x40u
35203 #define UART_UCR2_STPB_SHIFT                     6
35204 #define UART_UCR2_PROE_MASK                      0x80u
35205 #define UART_UCR2_PROE_SHIFT                     7
35206 #define UART_UCR2_PREN_MASK                      0x100u
35207 #define UART_UCR2_PREN_SHIFT                     8
35208 #define UART_UCR2_RTEC_MASK                      0x600u
35209 #define UART_UCR2_RTEC_SHIFT                     9
35210 #define UART_UCR2_RTEC(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UCR2_RTEC_SHIFT))&UART_UCR2_RTEC_MASK)
35211 #define UART_UCR2_ESCEN_MASK                     0x800u
35212 #define UART_UCR2_ESCEN_SHIFT                    11
35213 #define UART_UCR2_CTS_MASK                       0x1000u
35214 #define UART_UCR2_CTS_SHIFT                      12
35215 #define UART_UCR2_CTSC_MASK                      0x2000u
35216 #define UART_UCR2_CTSC_SHIFT                     13
35217 #define UART_UCR2_IRTS_MASK                      0x4000u
35218 #define UART_UCR2_IRTS_SHIFT                     14
35219 #define UART_UCR2_ESCI_MASK                      0x8000u
35220 #define UART_UCR2_ESCI_SHIFT                     15
35221 /* UCR3 Bit Fields */
35222 #define UART_UCR3_ACIEN_MASK                     0x1u
35223 #define UART_UCR3_ACIEN_SHIFT                    0
35224 #define UART_UCR3_INVT_MASK                      0x2u
35225 #define UART_UCR3_INVT_SHIFT                     1
35226 #define UART_UCR3_RXDMUXSEL_MASK                 0x4u
35227 #define UART_UCR3_RXDMUXSEL_SHIFT                2
35228 #define UART_UCR3_DTRDEN_MASK                    0x8u
35229 #define UART_UCR3_DTRDEN_SHIFT                   3
35230 #define UART_UCR3_AWAKEN_MASK                    0x10u
35231 #define UART_UCR3_AWAKEN_SHIFT                   4
35232 #define UART_UCR3_AIRINTEN_MASK                  0x20u
35233 #define UART_UCR3_AIRINTEN_SHIFT                 5
35234 #define UART_UCR3_RXDSEN_MASK                    0x40u
35235 #define UART_UCR3_RXDSEN_SHIFT                   6
35236 #define UART_UCR3_ADNIMP_MASK                    0x80u
35237 #define UART_UCR3_ADNIMP_SHIFT                   7
35238 #define UART_UCR3_RI_MASK                        0x100u
35239 #define UART_UCR3_RI_SHIFT                       8
35240 #define UART_UCR3_DCD_MASK                       0x200u
35241 #define UART_UCR3_DCD_SHIFT                      9
35242 #define UART_UCR3_DSR_MASK                       0x400u
35243 #define UART_UCR3_DSR_SHIFT                      10
35244 #define UART_UCR3_FRAERREN_MASK                  0x800u
35245 #define UART_UCR3_FRAERREN_SHIFT                 11
35246 #define UART_UCR3_PARERREN_MASK                  0x1000u
35247 #define UART_UCR3_PARERREN_SHIFT                 12
35248 #define UART_UCR3_DTREN_MASK                     0x2000u
35249 #define UART_UCR3_DTREN_SHIFT                    13
35250 #define UART_UCR3_DPEC_MASK                      0xC000u
35251 #define UART_UCR3_DPEC_SHIFT                     14
35252 #define UART_UCR3_DPEC(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UCR3_DPEC_SHIFT))&UART_UCR3_DPEC_MASK)
35253 /* UCR4 Bit Fields */
35254 #define UART_UCR4_DREN_MASK                      0x1u
35255 #define UART_UCR4_DREN_SHIFT                     0
35256 #define UART_UCR4_OREN_MASK                      0x2u
35257 #define UART_UCR4_OREN_SHIFT                     1
35258 #define UART_UCR4_BKEN_MASK                      0x4u
35259 #define UART_UCR4_BKEN_SHIFT                     2
35260 #define UART_UCR4_TCEN_MASK                      0x8u
35261 #define UART_UCR4_TCEN_SHIFT                     3
35262 #define UART_UCR4_LPBYP_MASK                     0x10u
35263 #define UART_UCR4_LPBYP_SHIFT                    4
35264 #define UART_UCR4_IRSC_MASK                      0x20u
35265 #define UART_UCR4_IRSC_SHIFT                     5
35266 #define UART_UCR4_IDDMAEN_MASK                   0x40u
35267 #define UART_UCR4_IDDMAEN_SHIFT                  6
35268 #define UART_UCR4_WKEN_MASK                      0x80u
35269 #define UART_UCR4_WKEN_SHIFT                     7
35270 #define UART_UCR4_ENIRI_MASK                     0x100u
35271 #define UART_UCR4_ENIRI_SHIFT                    8
35272 #define UART_UCR4_INVR_MASK                      0x200u
35273 #define UART_UCR4_INVR_SHIFT                     9
35274 #define UART_UCR4_CTSTL_MASK                     0xFC00u
35275 #define UART_UCR4_CTSTL_SHIFT                    10
35276 #define UART_UCR4_CTSTL(x)                       (((uint32_t)(((uint32_t)(x))<<UART_UCR4_CTSTL_SHIFT))&UART_UCR4_CTSTL_MASK)
35277 /* UFCR Bit Fields */
35278 #define UART_UFCR_RXTL_MASK                      0x3Fu
35279 #define UART_UFCR_RXTL_SHIFT                     0
35280 #define UART_UFCR_RXTL(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RXTL_SHIFT))&UART_UFCR_RXTL_MASK)
35281 #define UART_UFCR_DCEDTE_MASK                    0x40u
35282 #define UART_UFCR_DCEDTE_SHIFT                   6
35283 #define UART_UFCR_RFDIV_MASK                     0x380u
35284 #define UART_UFCR_RFDIV_SHIFT                    7
35285 #define UART_UFCR_RFDIV(x)                       (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RFDIV_SHIFT))&UART_UFCR_RFDIV_MASK)
35286 #define UART_UFCR_TXTL_MASK                      0xFC00u
35287 #define UART_UFCR_TXTL_SHIFT                     10
35288 #define UART_UFCR_TXTL(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UFCR_TXTL_SHIFT))&UART_UFCR_TXTL_MASK)
35289 /* USR1 Bit Fields */
35290 #define UART_USR1_SAD_MASK                       0x8u
35291 #define UART_USR1_SAD_SHIFT                      3
35292 #define UART_USR1_AWAKE_MASK                     0x10u
35293 #define UART_USR1_AWAKE_SHIFT                    4
35294 #define UART_USR1_AIRINT_MASK                    0x20u
35295 #define UART_USR1_AIRINT_SHIFT                   5
35296 #define UART_USR1_RXDS_MASK                      0x40u
35297 #define UART_USR1_RXDS_SHIFT                     6
35298 #define UART_USR1_DTRD_MASK                      0x80u
35299 #define UART_USR1_DTRD_SHIFT                     7
35300 #define UART_USR1_AGTIM_MASK                     0x100u
35301 #define UART_USR1_AGTIM_SHIFT                    8
35302 #define UART_USR1_RRDY_MASK                      0x200u
35303 #define UART_USR1_RRDY_SHIFT                     9
35304 #define UART_USR1_FRAMERR_MASK                   0x400u
35305 #define UART_USR1_FRAMERR_SHIFT                  10
35306 #define UART_USR1_ESCF_MASK                      0x800u
35307 #define UART_USR1_ESCF_SHIFT                     11
35308 #define UART_USR1_RTSD_MASK                      0x1000u
35309 #define UART_USR1_RTSD_SHIFT                     12
35310 #define UART_USR1_TRDY_MASK                      0x2000u
35311 #define UART_USR1_TRDY_SHIFT                     13
35312 #define UART_USR1_RTSS_MASK                      0x4000u
35313 #define UART_USR1_RTSS_SHIFT                     14
35314 #define UART_USR1_PARITYERR_MASK                 0x8000u
35315 #define UART_USR1_PARITYERR_SHIFT                15
35316 /* USR2 Bit Fields */
35317 #define UART_USR2_RDR_MASK                       0x1u
35318 #define UART_USR2_RDR_SHIFT                      0
35319 #define UART_USR2_ORE_MASK                       0x2u
35320 #define UART_USR2_ORE_SHIFT                      1
35321 #define UART_USR2_BRCD_MASK                      0x4u
35322 #define UART_USR2_BRCD_SHIFT                     2
35323 #define UART_USR2_TXDC_MASK                      0x8u
35324 #define UART_USR2_TXDC_SHIFT                     3
35325 #define UART_USR2_RTSF_MASK                      0x10u
35326 #define UART_USR2_RTSF_SHIFT                     4
35327 #define UART_USR2_DCDIN_MASK                     0x20u
35328 #define UART_USR2_DCDIN_SHIFT                    5
35329 #define UART_USR2_DCDDELT_MASK                   0x40u
35330 #define UART_USR2_DCDDELT_SHIFT                  6
35331 #define UART_USR2_WAKE_MASK                      0x80u
35332 #define UART_USR2_WAKE_SHIFT                     7
35333 #define UART_USR2_IRINT_MASK                     0x100u
35334 #define UART_USR2_IRINT_SHIFT                    8
35335 #define UART_USR2_RIIN_MASK                      0x200u
35336 #define UART_USR2_RIIN_SHIFT                     9
35337 #define UART_USR2_RIDELT_MASK                    0x400u
35338 #define UART_USR2_RIDELT_SHIFT                   10
35339 #define UART_USR2_ACST_MASK                      0x800u
35340 #define UART_USR2_ACST_SHIFT                     11
35341 #define UART_USR2_IDLE_MASK                      0x1000u
35342 #define UART_USR2_IDLE_SHIFT                     12
35343 #define UART_USR2_DTRF_MASK                      0x2000u
35344 #define UART_USR2_DTRF_SHIFT                     13
35345 #define UART_USR2_TXFE_MASK                      0x4000u
35346 #define UART_USR2_TXFE_SHIFT                     14
35347 #define UART_USR2_ADET_MASK                      0x8000u
35348 #define UART_USR2_ADET_SHIFT                     15
35349 /* UESC Bit Fields */
35350 #define UART_UESC_ESC_CHAR_MASK                  0xFFu
35351 #define UART_UESC_ESC_CHAR_SHIFT                 0
35352 #define UART_UESC_ESC_CHAR(x)                    (((uint32_t)(((uint32_t)(x))<<UART_UESC_ESC_CHAR_SHIFT))&UART_UESC_ESC_CHAR_MASK)
35353 /* UTIM Bit Fields */
35354 #define UART_UTIM_TIM_MASK                       0xFFFu
35355 #define UART_UTIM_TIM_SHIFT                      0
35356 #define UART_UTIM_TIM(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UTIM_TIM_SHIFT))&UART_UTIM_TIM_MASK)
35357 /* UBIR Bit Fields */
35358 #define UART_UBIR_INC_MASK                       0xFFFFu
35359 #define UART_UBIR_INC_SHIFT                      0
35360 #define UART_UBIR_INC(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UBIR_INC_SHIFT))&UART_UBIR_INC_MASK)
35361 /* UBMR Bit Fields */
35362 #define UART_UBMR_MOD_MASK                       0xFFFFu
35363 #define UART_UBMR_MOD_SHIFT                      0
35364 #define UART_UBMR_MOD(x)                         (((uint32_t)(((uint32_t)(x))<<UART_UBMR_MOD_SHIFT))&UART_UBMR_MOD_MASK)
35365 /* UBRC Bit Fields */
35366 #define UART_UBRC_BCNT_MASK                      0xFFFFu
35367 #define UART_UBRC_BCNT_SHIFT                     0
35368 #define UART_UBRC_BCNT(x)                        (((uint32_t)(((uint32_t)(x))<<UART_UBRC_BCNT_SHIFT))&UART_UBRC_BCNT_MASK)
35369 /* ONEMS Bit Fields */
35370 #define UART_ONEMS_ONEMS_MASK                    0xFFFFFFu
35371 #define UART_ONEMS_ONEMS_SHIFT                   0
35372 #define UART_ONEMS_ONEMS(x)                      (((uint32_t)(((uint32_t)(x))<<UART_ONEMS_ONEMS_SHIFT))&UART_ONEMS_ONEMS_MASK)
35373 /* UTS Bit Fields */
35374 #define UART_UTS_SOFTRST_MASK                    0x1u
35375 #define UART_UTS_SOFTRST_SHIFT                   0
35376 #define UART_UTS_RXFULL_MASK                     0x8u
35377 #define UART_UTS_RXFULL_SHIFT                    3
35378 #define UART_UTS_TXFULL_MASK                     0x10u
35379 #define UART_UTS_TXFULL_SHIFT                    4
35380 #define UART_UTS_RXEMPTY_MASK                    0x20u
35381 #define UART_UTS_RXEMPTY_SHIFT                   5
35382 #define UART_UTS_TXEMPTY_MASK                    0x40u
35383 #define UART_UTS_TXEMPTY_SHIFT                   6
35384 #define UART_UTS_RXDBG_MASK                      0x200u
35385 #define UART_UTS_RXDBG_SHIFT                     9
35386 #define UART_UTS_LOOPIR_MASK                     0x400u
35387 #define UART_UTS_LOOPIR_SHIFT                    10
35388 #define UART_UTS_DBGEN_MASK                      0x800u
35389 #define UART_UTS_DBGEN_SHIFT                     11
35390 #define UART_UTS_LOOP_MASK                       0x1000u
35391 #define UART_UTS_LOOP_SHIFT                      12
35392 #define UART_UTS_FRCPERR_MASK                    0x2000u
35393 #define UART_UTS_FRCPERR_SHIFT                   13
35394 /* UMCR Bit Fields */
35395 #define UART_UMCR_MDEN_MASK                      0x1u
35396 #define UART_UMCR_MDEN_SHIFT                     0
35397 #define UART_UMCR_SLAM_MASK                      0x2u
35398 #define UART_UMCR_SLAM_SHIFT                     1
35399 #define UART_UMCR_TXB8_MASK                      0x4u
35400 #define UART_UMCR_TXB8_SHIFT                     2
35401 #define UART_UMCR_SADEN_MASK                     0x8u
35402 #define UART_UMCR_SADEN_SHIFT                    3
35403 #define UART_UMCR_SLADDR_MASK                    0xFF00u
35404 #define UART_UMCR_SLADDR_SHIFT                   8
35405 #define UART_UMCR_SLADDR(x)                      (((uint32_t)(((uint32_t)(x))<<UART_UMCR_SLADDR_SHIFT))&UART_UMCR_SLADDR_MASK)
35406 
35407 /*!
35408  * @}
35409  */ /* end of group UART_Register_Masks */
35410 
35411 /* UART - Peripheral instance base addresses */
35412 /** Peripheral UART1 base address */
35413 #define UART1_BASE                               (0x42020000u)
35414 /** Peripheral UART1 base pointer */
35415 #define UART1                                    ((UART_Type *)UART1_BASE)
35416 #define UART1_BASE_PTR                           (UART1)
35417 /** Peripheral UART2 base address */
35418 #define UART2_BASE                               (0x421E8000u)
35419 /** Peripheral UART2 base pointer */
35420 #define UART2                                    ((UART_Type *)UART2_BASE)
35421 #define UART2_BASE_PTR                           (UART2)
35422 /** Peripheral UART3 base address */
35423 #define UART3_BASE                               (0x421EC000u)
35424 /** Peripheral UART3 base pointer */
35425 #define UART3                                    ((UART_Type *)UART3_BASE)
35426 #define UART3_BASE_PTR                           (UART3)
35427 /** Peripheral UART4 base address */
35428 #define UART4_BASE                               (0x421F0000u)
35429 /** Peripheral UART4 base pointer */
35430 #define UART4                                    ((UART_Type *)UART4_BASE)
35431 #define UART4_BASE_PTR                           (UART4)
35432 /** Peripheral UART5 base address */
35433 #define UART5_BASE                               (0x421F4000u)
35434 /** Peripheral UART5 base pointer */
35435 #define UART5                                    ((UART_Type *)UART5_BASE)
35436 #define UART5_BASE_PTR                           (UART5)
35437 /** Peripheral UART6 base address */
35438 #define UART6_BASE                               (0x422A0000u)
35439 /** Peripheral UART6 base pointer */
35440 #define UART6                                    ((UART_Type *)UART6_BASE)
35441 #define UART6_BASE_PTR                           (UART6)
35442 /** Array initializer of UART peripheral base addresses */
35443 #define UART_BASE_ADDRS                          { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE }
35444 /** Array initializer of UART peripheral base pointers */
35445 #define UART_BASE_PTRS                           { UART1, UART2, UART3, UART4, UART5, UART6 }
35446 /** Interrupt vectors for the UART peripheral type */
35447 #define UART_IRQS                                { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn }
35448 
35449 /* ----------------------------------------------------------------------------
35450    -- UART - Register accessor macros
35451    ---------------------------------------------------------------------------- */
35452 
35453 /*!
35454  * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
35455  * @{
35456  */
35457 
35458 /* UART - Register instance definitions */
35459 /* UART1 */
35460 #define UART1_URXD                               UART_URXD_REG(UART1_BASE_PTR)
35461 #define UART1_UTXD                               UART_UTXD_REG(UART1_BASE_PTR)
35462 #define UART1_UCR1                               UART_UCR1_REG(UART1_BASE_PTR)
35463 #define UART1_UCR2                               UART_UCR2_REG(UART1_BASE_PTR)
35464 #define UART1_UCR3                               UART_UCR3_REG(UART1_BASE_PTR)
35465 #define UART1_UCR4                               UART_UCR4_REG(UART1_BASE_PTR)
35466 #define UART1_UFCR                               UART_UFCR_REG(UART1_BASE_PTR)
35467 #define UART1_USR1                               UART_USR1_REG(UART1_BASE_PTR)
35468 #define UART1_USR2                               UART_USR2_REG(UART1_BASE_PTR)
35469 #define UART1_UESC                               UART_UESC_REG(UART1_BASE_PTR)
35470 #define UART1_UTIM                               UART_UTIM_REG(UART1_BASE_PTR)
35471 #define UART1_UBIR                               UART_UBIR_REG(UART1_BASE_PTR)
35472 #define UART1_UBMR                               UART_UBMR_REG(UART1_BASE_PTR)
35473 #define UART1_UBRC                               UART_UBRC_REG(UART1_BASE_PTR)
35474 #define UART1_ONEMS                              UART_ONEMS_REG(UART1_BASE_PTR)
35475 #define UART1_UTS                                UART_UTS_REG(UART1_BASE_PTR)
35476 #define UART1_UMCR                               UART_UMCR_REG(UART1_BASE_PTR)
35477 /* UART2 */
35478 #define UART2_URXD                               UART_URXD_REG(UART2_BASE_PTR)
35479 #define UART2_UTXD                               UART_UTXD_REG(UART2_BASE_PTR)
35480 #define UART2_UCR1                               UART_UCR1_REG(UART2_BASE_PTR)
35481 #define UART2_UCR2                               UART_UCR2_REG(UART2_BASE_PTR)
35482 #define UART2_UCR3                               UART_UCR3_REG(UART2_BASE_PTR)
35483 #define UART2_UCR4                               UART_UCR4_REG(UART2_BASE_PTR)
35484 #define UART2_UFCR                               UART_UFCR_REG(UART2_BASE_PTR)
35485 #define UART2_USR1                               UART_USR1_REG(UART2_BASE_PTR)
35486 #define UART2_USR2                               UART_USR2_REG(UART2_BASE_PTR)
35487 #define UART2_UESC                               UART_UESC_REG(UART2_BASE_PTR)
35488 #define UART2_UTIM                               UART_UTIM_REG(UART2_BASE_PTR)
35489 #define UART2_UBIR                               UART_UBIR_REG(UART2_BASE_PTR)
35490 #define UART2_UBMR                               UART_UBMR_REG(UART2_BASE_PTR)
35491 #define UART2_UBRC                               UART_UBRC_REG(UART2_BASE_PTR)
35492 #define UART2_ONEMS                              UART_ONEMS_REG(UART2_BASE_PTR)
35493 #define UART2_UTS                                UART_UTS_REG(UART2_BASE_PTR)
35494 #define UART2_UMCR                               UART_UMCR_REG(UART2_BASE_PTR)
35495 /* UART3 */
35496 #define UART3_URXD                               UART_URXD_REG(UART3_BASE_PTR)
35497 #define UART3_UTXD                               UART_UTXD_REG(UART3_BASE_PTR)
35498 #define UART3_UCR1                               UART_UCR1_REG(UART3_BASE_PTR)
35499 #define UART3_UCR2                               UART_UCR2_REG(UART3_BASE_PTR)
35500 #define UART3_UCR3                               UART_UCR3_REG(UART3_BASE_PTR)
35501 #define UART3_UCR4                               UART_UCR4_REG(UART3_BASE_PTR)
35502 #define UART3_UFCR                               UART_UFCR_REG(UART3_BASE_PTR)
35503 #define UART3_USR1                               UART_USR1_REG(UART3_BASE_PTR)
35504 #define UART3_USR2                               UART_USR2_REG(UART3_BASE_PTR)
35505 #define UART3_UESC                               UART_UESC_REG(UART3_BASE_PTR)
35506 #define UART3_UTIM                               UART_UTIM_REG(UART3_BASE_PTR)
35507 #define UART3_UBIR                               UART_UBIR_REG(UART3_BASE_PTR)
35508 #define UART3_UBMR                               UART_UBMR_REG(UART3_BASE_PTR)
35509 #define UART3_UBRC                               UART_UBRC_REG(UART3_BASE_PTR)
35510 #define UART3_ONEMS                              UART_ONEMS_REG(UART3_BASE_PTR)
35511 #define UART3_UTS                                UART_UTS_REG(UART3_BASE_PTR)
35512 #define UART3_UMCR                               UART_UMCR_REG(UART3_BASE_PTR)
35513 /* UART4 */
35514 #define UART4_URXD                               UART_URXD_REG(UART4_BASE_PTR)
35515 #define UART4_UTXD                               UART_UTXD_REG(UART4_BASE_PTR)
35516 #define UART4_UCR1                               UART_UCR1_REG(UART4_BASE_PTR)
35517 #define UART4_UCR2                               UART_UCR2_REG(UART4_BASE_PTR)
35518 #define UART4_UCR3                               UART_UCR3_REG(UART4_BASE_PTR)
35519 #define UART4_UCR4                               UART_UCR4_REG(UART4_BASE_PTR)
35520 #define UART4_UFCR                               UART_UFCR_REG(UART4_BASE_PTR)
35521 #define UART4_USR1                               UART_USR1_REG(UART4_BASE_PTR)
35522 #define UART4_USR2                               UART_USR2_REG(UART4_BASE_PTR)
35523 #define UART4_UESC                               UART_UESC_REG(UART4_BASE_PTR)
35524 #define UART4_UTIM                               UART_UTIM_REG(UART4_BASE_PTR)
35525 #define UART4_UBIR                               UART_UBIR_REG(UART4_BASE_PTR)
35526 #define UART4_UBMR                               UART_UBMR_REG(UART4_BASE_PTR)
35527 #define UART4_UBRC                               UART_UBRC_REG(UART4_BASE_PTR)
35528 #define UART4_ONEMS                              UART_ONEMS_REG(UART4_BASE_PTR)
35529 #define UART4_UTS                                UART_UTS_REG(UART4_BASE_PTR)
35530 #define UART4_UMCR                               UART_UMCR_REG(UART4_BASE_PTR)
35531 /* UART5 */
35532 #define UART5_URXD                               UART_URXD_REG(UART5_BASE_PTR)
35533 #define UART5_UTXD                               UART_UTXD_REG(UART5_BASE_PTR)
35534 #define UART5_UCR1                               UART_UCR1_REG(UART5_BASE_PTR)
35535 #define UART5_UCR2                               UART_UCR2_REG(UART5_BASE_PTR)
35536 #define UART5_UCR3                               UART_UCR3_REG(UART5_BASE_PTR)
35537 #define UART5_UCR4                               UART_UCR4_REG(UART5_BASE_PTR)
35538 #define UART5_UFCR                               UART_UFCR_REG(UART5_BASE_PTR)
35539 #define UART5_USR1                               UART_USR1_REG(UART5_BASE_PTR)
35540 #define UART5_USR2                               UART_USR2_REG(UART5_BASE_PTR)
35541 #define UART5_UESC                               UART_UESC_REG(UART5_BASE_PTR)
35542 #define UART5_UTIM                               UART_UTIM_REG(UART5_BASE_PTR)
35543 #define UART5_UBIR                               UART_UBIR_REG(UART5_BASE_PTR)
35544 #define UART5_UBMR                               UART_UBMR_REG(UART5_BASE_PTR)
35545 #define UART5_UBRC                               UART_UBRC_REG(UART5_BASE_PTR)
35546 #define UART5_ONEMS                              UART_ONEMS_REG(UART5_BASE_PTR)
35547 #define UART5_UTS                                UART_UTS_REG(UART5_BASE_PTR)
35548 #define UART5_UMCR                               UART_UMCR_REG(UART5_BASE_PTR)
35549 /* UART6 */
35550 #define UART6_URXD                               UART_URXD_REG(UART6_BASE_PTR)
35551 #define UART6_UTXD                               UART_UTXD_REG(UART6_BASE_PTR)
35552 #define UART6_UCR1                               UART_UCR1_REG(UART6_BASE_PTR)
35553 #define UART6_UCR2                               UART_UCR2_REG(UART6_BASE_PTR)
35554 #define UART6_UCR3                               UART_UCR3_REG(UART6_BASE_PTR)
35555 #define UART6_UCR4                               UART_UCR4_REG(UART6_BASE_PTR)
35556 #define UART6_UFCR                               UART_UFCR_REG(UART6_BASE_PTR)
35557 #define UART6_USR1                               UART_USR1_REG(UART6_BASE_PTR)
35558 #define UART6_USR2                               UART_USR2_REG(UART6_BASE_PTR)
35559 #define UART6_UESC                               UART_UESC_REG(UART6_BASE_PTR)
35560 #define UART6_UTIM                               UART_UTIM_REG(UART6_BASE_PTR)
35561 #define UART6_UBIR                               UART_UBIR_REG(UART6_BASE_PTR)
35562 #define UART6_UBMR                               UART_UBMR_REG(UART6_BASE_PTR)
35563 #define UART6_UBRC                               UART_UBRC_REG(UART6_BASE_PTR)
35564 #define UART6_ONEMS                              UART_ONEMS_REG(UART6_BASE_PTR)
35565 #define UART6_UTS                                UART_UTS_REG(UART6_BASE_PTR)
35566 #define UART6_UMCR                               UART_UMCR_REG(UART6_BASE_PTR)
35567 
35568 /*!
35569  * @}
35570  */ /* end of group UART_Register_Accessor_Macros */
35571 
35572 /*!
35573  * @}
35574  */ /* end of group UART_Peripheral */
35575 
35576 /* ----------------------------------------------------------------------------
35577    -- USBC Peripheral Access Layer
35578    ---------------------------------------------------------------------------- */
35579 
35580 /*!
35581  * @addtogroup USBC_Peripheral_Access_Layer USBC Peripheral Access Layer
35582  * @{
35583  */
35584 
35585 /** USBC - Register Layout Typedef */
35586 typedef struct {
35587   __I   uint32_t UOG1_ID;                                /**< Identification register, offset: 0x0 */
35588   __I   uint32_t UOG1_HWGENERAL;                         /**< Hardware General, offset: 0x4 */
35589   __I   uint32_t UOG1_HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
35590   __I   uint32_t UOG1_HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
35591   __I   uint32_t UOG1_HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
35592   __I   uint32_t UOG1_HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
35593   uint8_t RESERVED_0[104];
35594   __IO  uint32_t UOG1_GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
35595   __IO  uint32_t UOG1_GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
35596   __IO  uint32_t UOG1_GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
35597   __IO  uint32_t UOG1_GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
35598   __IO  uint32_t UOG1_SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
35599   uint8_t RESERVED_1[108];
35600   __I   uint8_t  UOG1_CAPLENGTH;                         /**< Capability Registers Length, offset: 0x100 */
35601   uint8_t RESERVED_2[1];
35602   __I   uint16_t UOG1_HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
35603   __I   uint32_t UOG1_HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
35604   __I   uint32_t UOG1_HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
35605   uint8_t RESERVED_3[20];
35606   __I   uint16_t UOG1_DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
35607   uint8_t RESERVED_4[2];
35608   __I   uint32_t UOG1_DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
35609   uint8_t RESERVED_5[24];
35610   __IO  uint32_t UOG1_USBCMD;                            /**< USB Command Register, offset: 0x140 */
35611   __IO  uint32_t UOG1_USBSTS;                            /**< USB Status Register, offset: 0x144 */
35612   __IO  uint32_t UOG1_USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
35613   __IO  uint32_t UOG1_FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
35614   uint8_t RESERVED_6[4];
35615   union {                                          /* offset: 0x154 */
35616   __IO    uint32_t UOG1_PERIODICLISTBASE;                       /**< Frame List Base Address,offset: 0x154 */
35617   __IO    uint32_t UOG1_DEVICEADDR;                             /**< Device Address,offset: 0x154 */
35618   struct {                                         /* offset: 0x158 */
35619       uint8_t RESERVED_0[4];
35620   __IO    uint32_t UOG1_ASYNCLISTADDR;                          /**< Next Asynch. Address,offset: 0x158 */
35621     } UOG1_ASYNCLISTADDR;
35622   struct {                                         /* offset: 0x158 */
35623       uint8_t RESERVED_0[4];
35624   __IO    uint32_t UOG1_ENDPTLISTADDR;                          /**< Endpoint List Address,offset: 0x158 */
35625     } UOG1_ENDPTLISTADDR;
35626   };
35627   uint8_t RESERVED_7[4];
35628   __IO  uint32_t UOG1_BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
35629   __IO  uint32_t UOG1_TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
35630   uint8_t RESERVED_8[16];
35631   __IO  uint32_t UOG1_ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
35632   __IO  uint32_t UOG1_ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
35633   __IO  uint32_t UOG1_CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
35634   __IO  uint32_t UOG1_PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
35635   uint8_t RESERVED_9[28];
35636   __IO  uint32_t UOG1_OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
35637   __IO  uint32_t UOG1_USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
35638   __IO  uint32_t UOG1_ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
35639   __IO  uint32_t UOG1_ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
35640   __IO  uint32_t UOG1_ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
35641   __I   uint32_t UOG1_ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
35642   __IO  uint32_t UOG1_ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
35643   __IO  uint32_t UOG1_ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
35644   __IO  uint32_t UOG1_ENDPTCTRL1;                        /**< Endpoint Control 1, offset: 0x1C4 */
35645   __IO  uint32_t UOG1_ENDPTCTRL2;                        /**< Endpoint Control 2, offset: 0x1C8 */
35646   __IO  uint32_t UOG1_ENDPTCTRL3;                        /**< Endpoint Control 3, offset: 0x1CC */
35647   __IO  uint32_t UOG1_ENDPTCTRL4;                        /**< Endpoint Control 4, offset: 0x1D0 */
35648   __IO  uint32_t UOG1_ENDPTCTRL5;                        /**< Endpoint Control 5, offset: 0x1D4 */
35649   __IO  uint32_t UOG1_ENDPTCTRL6;                        /**< Endpoint Control 6, offset: 0x1D8 */
35650   __IO  uint32_t UOG1_ENDPTCTRL7;                        /**< Endpoint Control 7, offset: 0x1DC */
35651   uint8_t RESERVED_10[32];
35652   __I   uint32_t UOG2_ID;                                /**< Identification register, offset: 0x200 */
35653   __I   uint32_t UOG2_HWGENERAL;                         /**< Hardware General, offset: 0x204 */
35654   __I   uint32_t UOG2_HWHOST;                            /**< Host Hardware Parameters, offset: 0x208 */
35655   __I   uint32_t UOG2_HWDEVICE;                          /**< Device Hardware Parameters, offset: 0x20C */
35656   __I   uint32_t UOG2_HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x210 */
35657   __I   uint32_t UOG2_HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x214 */
35658   uint8_t RESERVED_11[104];
35659   __IO  uint32_t UOG2_GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x280 */
35660   __IO  uint32_t UOG2_GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x284 */
35661   __IO  uint32_t UOG2_GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x288 */
35662   __IO  uint32_t UOG2_GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x28C */
35663   __IO  uint32_t UOG2_SBUSCFG;                           /**< System Bus Config, offset: 0x290 */
35664   uint8_t RESERVED_12[108];
35665   __I   uint8_t  UOG2_CAPLENGTH;                         /**< Capability Registers Length, offset: 0x300 */
35666   uint8_t RESERVED_13[1];
35667   __I   uint16_t UOG2_HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x302 */
35668   __I   uint32_t UOG2_HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x304 */
35669   __I   uint32_t UOG2_HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x308 */
35670   uint8_t RESERVED_14[20];
35671   __I   uint16_t UOG2_DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x320 */
35672   uint8_t RESERVED_15[2];
35673   __I   uint32_t UOG2_DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x324 */
35674   uint8_t RESERVED_16[24];
35675   __IO  uint32_t UOG2_USBCMD;                            /**< USB Command Register, offset: 0x340 */
35676   __IO  uint32_t UOG2_USBSTS;                            /**< USB Status Register, offset: 0x344 */
35677   __IO  uint32_t UOG2_USBINTR;                           /**< Interrupt Enable Register, offset: 0x348 */
35678   __IO  uint32_t UOG2_FRINDEX;                           /**< USB Frame Index, offset: 0x34C */
35679   uint8_t RESERVED_17[4];
35680   union {                                          /* offset: 0x354 */
35681   __IO    uint32_t UOG2_PERIODICLISTBASE;                       /**< Frame List Base Address,offset: 0x354 */
35682   __IO    uint32_t UOG2_DEVICEADDR;                             /**< Device Address,offset: 0x354 */
35683   struct {                                         /* offset: 0x358 */
35684       uint8_t RESERVED_0[4];
35685   __IO    uint32_t UOG2_ASYNCLISTADDR;                          /**< Next Asynch. Address,offset: 0x358 */
35686     } UOG2_ASYNCLISTADDR;
35687   struct {                                         /* offset: 0x358 */
35688       uint8_t RESERVED_0[4];
35689   __IO    uint32_t UOG2_ENDPTLISTADDR;                          /**< Endpoint List Address,offset: 0x358 */
35690     } UOG2_ENDPTLISTADDR;
35691   };
35692   uint8_t RESERVED_18[4];
35693   __IO  uint32_t UOG2_BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x360 */
35694   __IO  uint32_t UOG2_TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x364 */
35695   uint8_t RESERVED_19[16];
35696   __IO  uint32_t UOG2_ENDPTNAK;                          /**< Endpoint NAK, offset: 0x378 */
35697   __IO  uint32_t UOG2_ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x37C */
35698   __IO  uint32_t UOG2_CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x380 */
35699   __IO  uint32_t UOG2_PORTSC1;                           /**< Port Status & Control, offset: 0x384 */
35700   uint8_t RESERVED_20[28];
35701   __IO  uint32_t UOG2_OTGSC;                             /**< On-The-Go Status & control, offset: 0x3A4 */
35702   __IO  uint32_t UOG2_USBMODE;                           /**< USB Device Mode, offset: 0x3A8 */
35703   __IO  uint32_t UOG2_ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x3AC */
35704   __IO  uint32_t UOG2_ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x3B0 */
35705   __IO  uint32_t UOG2_ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x3B4 */
35706   __I   uint32_t UOG2_ENDPTSTAT;                         /**< Endpoint Status, offset: 0x3B8 */
35707   __IO  uint32_t UOG2_ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x3BC */
35708   __IO  uint32_t UOG2_ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x3C0 */
35709   __IO  uint32_t UOG2_ENDPTCTRL1;                        /**< Endpoint Control 1, offset: 0x3C4 */
35710   __IO  uint32_t UOG2_ENDPTCTRL2;                        /**< Endpoint Control 2, offset: 0x3C8 */
35711   __IO  uint32_t UOG2_ENDPTCTRL3;                        /**< Endpoint Control 3, offset: 0x3CC */
35712   __IO  uint32_t UOG2_ENDPTCTRL4;                        /**< Endpoint Control 4, offset: 0x3D0 */
35713   __IO  uint32_t UOG2_ENDPTCTRL5;                        /**< Endpoint Control 5, offset: 0x3D4 */
35714   __IO  uint32_t UOG2_ENDPTCTRL6;                        /**< Endpoint Control 6, offset: 0x3D8 */
35715   __IO  uint32_t UOG2_ENDPTCTRL7;                        /**< Endpoint Control 7, offset: 0x3DC */
35716   uint8_t RESERVED_21[32];
35717   __I   uint32_t UH1_ID;                                 /**< Identification register, offset: 0x400 */
35718   __I   uint32_t UH1_HWGENERAL;                          /**< Hardware General, offset: 0x404 */
35719   __I   uint32_t UH1_HWHOST;                             /**< Host Hardware Parameters, offset: 0x408 */
35720   uint8_t RESERVED_22[4];
35721   __I   uint32_t UH1_HWTXBUF;                            /**< TX Buffer Hardware Parameters, offset: 0x410 */
35722   __I   uint32_t UH1_HWRXBUF;                            /**< RX Buffer Hardware Parameters, offset: 0x414 */
35723   uint8_t RESERVED_23[104];
35724   __IO  uint32_t UH1_GPTIMER0LD;                         /**< General Purpose Timer #0 Load, offset: 0x480 */
35725   __IO  uint32_t UH1_GPTIMER0CTRL;                       /**< General Purpose Timer #0 Controller, offset: 0x484 */
35726   __IO  uint32_t UH1_GPTIMER1LD;                         /**< General Purpose Timer #1 Load, offset: 0x488 */
35727   __IO  uint32_t UH1_GPTIMER1CTRL;                       /**< General Purpose Timer #1 Controller, offset: 0x48C */
35728   __IO  uint32_t UH1_SBUSCFG;                            /**< System Bus Config, offset: 0x490 */
35729   uint8_t RESERVED_24[108];
35730   __I   uint8_t  UH1_CAPLENGTH;                          /**< Capability Registers Length, offset: 0x500 */
35731   uint8_t RESERVED_25[1];
35732   __I   uint16_t UH1_HCIVERSION;                         /**< Host Controller Interface Version, offset: 0x502 */
35733   __I   uint32_t UH1_HCSPARAMS;                          /**< Host Controller Structural Parameters, offset: 0x504 */
35734   __I   uint32_t UH1_HCCPARAMS;                          /**< Host Controller Capability Parameters, offset: 0x508 */
35735   uint8_t RESERVED_26[52];
35736   __IO  uint32_t UH1_USBCMD;                             /**< USB Command Register, offset: 0x540 */
35737   __IO  uint32_t UH1_USBSTS;                             /**< USB Status Register, offset: 0x544 */
35738   __IO  uint32_t UH1_USBINTR;                            /**< Interrupt Enable Register, offset: 0x548 */
35739   __IO  uint32_t UH1_FRINDEX;                            /**< USB Frame Index, offset: 0x54C */
35740   uint8_t RESERVED_27[4];
35741   __IO  uint32_t UH1_PERIODICLISTBASE;                   /**< Frame List Base Address, offset: 0x554 */
35742   __IO  uint32_t UH1_ASYNCLISTADDR;                      /**< Next Asynch. Address, offset: 0x558 */
35743   uint8_t RESERVED_28[4];
35744   __IO  uint32_t UH1_BURSTSIZE;                          /**< Programmable Burst Size, offset: 0x560 */
35745   __IO  uint32_t UH1_TXFILLTUNING;                       /**< TX FIFO Fill Tuning, offset: 0x564 */
35746   uint8_t RESERVED_29[24];
35747   __IO  uint32_t UH1_CONFIGFLAG;                         /**< Configure Flag Register, offset: 0x580 */
35748   __IO  uint32_t UH1_PORTSC1;                            /**< Port Status & Control, offset: 0x584 */
35749   uint8_t RESERVED_30[32];
35750   __IO  uint32_t UH1_USBMODE;                            /**< USB Device Mode, offset: 0x5A8 */
35751 } USBC_Type, *USBC_MemMapPtr;
35752 
35753 /* ----------------------------------------------------------------------------
35754    -- USBC - Register accessor macros
35755    ---------------------------------------------------------------------------- */
35756 
35757 /*!
35758  * @addtogroup USBC_Register_Accessor_Macros USBC - Register accessor macros
35759  * @{
35760  */
35761 
35762 /* USBC - Register accessors */
35763 #define USBC_UOG1_ID_REG(base)                   ((base)->UOG1_ID)
35764 #define USBC_UOG1_HWGENERAL_REG(base)            ((base)->UOG1_HWGENERAL)
35765 #define USBC_UOG1_HWHOST_REG(base)               ((base)->UOG1_HWHOST)
35766 #define USBC_UOG1_HWDEVICE_REG(base)             ((base)->UOG1_HWDEVICE)
35767 #define USBC_UOG1_HWTXBUF_REG(base)              ((base)->UOG1_HWTXBUF)
35768 #define USBC_UOG1_HWRXBUF_REG(base)              ((base)->UOG1_HWRXBUF)
35769 #define USBC_UOG1_GPTIMER0LD_REG(base)           ((base)->UOG1_GPTIMER0LD)
35770 #define USBC_UOG1_GPTIMER0CTRL_REG(base)         ((base)->UOG1_GPTIMER0CTRL)
35771 #define USBC_UOG1_GPTIMER1LD_REG(base)           ((base)->UOG1_GPTIMER1LD)
35772 #define USBC_UOG1_GPTIMER1CTRL_REG(base)         ((base)->UOG1_GPTIMER1CTRL)
35773 #define USBC_UOG1_SBUSCFG_REG(base)              ((base)->UOG1_SBUSCFG)
35774 #define USBC_UOG1_CAPLENGTH_REG(base)            ((base)->UOG1_CAPLENGTH)
35775 #define USBC_UOG1_HCIVERSION_REG(base)           ((base)->UOG1_HCIVERSION)
35776 #define USBC_UOG1_HCSPARAMS_REG(base)            ((base)->UOG1_HCSPARAMS)
35777 #define USBC_UOG1_HCCPARAMS_REG(base)            ((base)->UOG1_HCCPARAMS)
35778 #define USBC_UOG1_DCIVERSION_REG(base)           ((base)->UOG1_DCIVERSION)
35779 #define USBC_UOG1_DCCPARAMS_REG(base)            ((base)->UOG1_DCCPARAMS)
35780 #define USBC_UOG1_USBCMD_REG(base)               ((base)->UOG1_USBCMD)
35781 #define USBC_UOG1_USBSTS_REG(base)               ((base)->UOG1_USBSTS)
35782 #define USBC_UOG1_USBINTR_REG(base)              ((base)->UOG1_USBINTR)
35783 #define USBC_UOG1_FRINDEX_REG(base)              ((base)->UOG1_FRINDEX)
35784 #define USBC_UOG1_PERIODICLISTBASE_REG(base)     ((base)->UOG1_PERIODICLISTBASE)
35785 #define USBC_UOG1_DEVICEADDR_REG(base)           ((base)->UOG1_DEVICEADDR)
35786 #define USBC_UOG1_ASYNCLISTADDR_REG(base)        ((base)->UOG1_ASYNCLISTADDR.UOG1_ASYNCLISTADDR)
35787 #define USBC_UOG1_ENDPTLISTADDR_REG(base)        ((base)->UOG1_ENDPTLISTADDR.UOG1_ENDPTLISTADDR)
35788 #define USBC_UOG1_BURSTSIZE_REG(base)            ((base)->UOG1_BURSTSIZE)
35789 #define USBC_UOG1_TXFILLTUNING_REG(base)         ((base)->UOG1_TXFILLTUNING)
35790 #define USBC_UOG1_ENDPTNAK_REG(base)             ((base)->UOG1_ENDPTNAK)
35791 #define USBC_UOG1_ENDPTNAKEN_REG(base)           ((base)->UOG1_ENDPTNAKEN)
35792 #define USBC_UOG1_CONFIGFLAG_REG(base)           ((base)->UOG1_CONFIGFLAG)
35793 #define USBC_UOG1_PORTSC1_REG(base)              ((base)->UOG1_PORTSC1)
35794 #define USBC_UOG1_OTGSC_REG(base)                ((base)->UOG1_OTGSC)
35795 #define USBC_UOG1_USBMODE_REG(base)              ((base)->UOG1_USBMODE)
35796 #define USBC_UOG1_ENDPTSETUPSTAT_REG(base)       ((base)->UOG1_ENDPTSETUPSTAT)
35797 #define USBC_UOG1_ENDPTPRIME_REG(base)           ((base)->UOG1_ENDPTPRIME)
35798 #define USBC_UOG1_ENDPTFLUSH_REG(base)           ((base)->UOG1_ENDPTFLUSH)
35799 #define USBC_UOG1_ENDPTSTAT_REG(base)            ((base)->UOG1_ENDPTSTAT)
35800 #define USBC_UOG1_ENDPTCOMPLETE_REG(base)        ((base)->UOG1_ENDPTCOMPLETE)
35801 #define USBC_UOG1_ENDPTCTRL0_REG(base)           ((base)->UOG1_ENDPTCTRL0)
35802 #define USBC_UOG1_ENDPTCTRL1_REG(base)           ((base)->UOG1_ENDPTCTRL1)
35803 #define USBC_UOG1_ENDPTCTRL2_REG(base)           ((base)->UOG1_ENDPTCTRL2)
35804 #define USBC_UOG1_ENDPTCTRL3_REG(base)           ((base)->UOG1_ENDPTCTRL3)
35805 #define USBC_UOG1_ENDPTCTRL4_REG(base)           ((base)->UOG1_ENDPTCTRL4)
35806 #define USBC_UOG1_ENDPTCTRL5_REG(base)           ((base)->UOG1_ENDPTCTRL5)
35807 #define USBC_UOG1_ENDPTCTRL6_REG(base)           ((base)->UOG1_ENDPTCTRL6)
35808 #define USBC_UOG1_ENDPTCTRL7_REG(base)           ((base)->UOG1_ENDPTCTRL7)
35809 #define USBC_UOG2_ID_REG(base)                   ((base)->UOG2_ID)
35810 #define USBC_UOG2_HWGENERAL_REG(base)            ((base)->UOG2_HWGENERAL)
35811 #define USBC_UOG2_HWHOST_REG(base)               ((base)->UOG2_HWHOST)
35812 #define USBC_UOG2_HWDEVICE_REG(base)             ((base)->UOG2_HWDEVICE)
35813 #define USBC_UOG2_HWTXBUF_REG(base)              ((base)->UOG2_HWTXBUF)
35814 #define USBC_UOG2_HWRXBUF_REG(base)              ((base)->UOG2_HWRXBUF)
35815 #define USBC_UOG2_GPTIMER0LD_REG(base)           ((base)->UOG2_GPTIMER0LD)
35816 #define USBC_UOG2_GPTIMER0CTRL_REG(base)         ((base)->UOG2_GPTIMER0CTRL)
35817 #define USBC_UOG2_GPTIMER1LD_REG(base)           ((base)->UOG2_GPTIMER1LD)
35818 #define USBC_UOG2_GPTIMER1CTRL_REG(base)         ((base)->UOG2_GPTIMER1CTRL)
35819 #define USBC_UOG2_SBUSCFG_REG(base)              ((base)->UOG2_SBUSCFG)
35820 #define USBC_UOG2_CAPLENGTH_REG(base)            ((base)->UOG2_CAPLENGTH)
35821 #define USBC_UOG2_HCIVERSION_REG(base)           ((base)->UOG2_HCIVERSION)
35822 #define USBC_UOG2_HCSPARAMS_REG(base)            ((base)->UOG2_HCSPARAMS)
35823 #define USBC_UOG2_HCCPARAMS_REG(base)            ((base)->UOG2_HCCPARAMS)
35824 #define USBC_UOG2_DCIVERSION_REG(base)           ((base)->UOG2_DCIVERSION)
35825 #define USBC_UOG2_DCCPARAMS_REG(base)            ((base)->UOG2_DCCPARAMS)
35826 #define USBC_UOG2_USBCMD_REG(base)               ((base)->UOG2_USBCMD)
35827 #define USBC_UOG2_USBSTS_REG(base)               ((base)->UOG2_USBSTS)
35828 #define USBC_UOG2_USBINTR_REG(base)              ((base)->UOG2_USBINTR)
35829 #define USBC_UOG2_FRINDEX_REG(base)              ((base)->UOG2_FRINDEX)
35830 #define USBC_UOG2_PERIODICLISTBASE_REG(base)     ((base)->UOG2_PERIODICLISTBASE)
35831 #define USBC_UOG2_DEVICEADDR_REG(base)           ((base)->UOG2_DEVICEADDR)
35832 #define USBC_UOG2_ASYNCLISTADDR_REG(base)        ((base)->UOG2_ASYNCLISTADDR.UOG2_ASYNCLISTADDR)
35833 #define USBC_UOG2_ENDPTLISTADDR_REG(base)        ((base)->UOG2_ENDPTLISTADDR.UOG2_ENDPTLISTADDR)
35834 #define USBC_UOG2_BURSTSIZE_REG(base)            ((base)->UOG2_BURSTSIZE)
35835 #define USBC_UOG2_TXFILLTUNING_REG(base)         ((base)->UOG2_TXFILLTUNING)
35836 #define USBC_UOG2_ENDPTNAK_REG(base)             ((base)->UOG2_ENDPTNAK)
35837 #define USBC_UOG2_ENDPTNAKEN_REG(base)           ((base)->UOG2_ENDPTNAKEN)
35838 #define USBC_UOG2_CONFIGFLAG_REG(base)           ((base)->UOG2_CONFIGFLAG)
35839 #define USBC_UOG2_PORTSC1_REG(base)              ((base)->UOG2_PORTSC1)
35840 #define USBC_UOG2_OTGSC_REG(base)                ((base)->UOG2_OTGSC)
35841 #define USBC_UOG2_USBMODE_REG(base)              ((base)->UOG2_USBMODE)
35842 #define USBC_UOG2_ENDPTSETUPSTAT_REG(base)       ((base)->UOG2_ENDPTSETUPSTAT)
35843 #define USBC_UOG2_ENDPTPRIME_REG(base)           ((base)->UOG2_ENDPTPRIME)
35844 #define USBC_UOG2_ENDPTFLUSH_REG(base)           ((base)->UOG2_ENDPTFLUSH)
35845 #define USBC_UOG2_ENDPTSTAT_REG(base)            ((base)->UOG2_ENDPTSTAT)
35846 #define USBC_UOG2_ENDPTCOMPLETE_REG(base)        ((base)->UOG2_ENDPTCOMPLETE)
35847 #define USBC_UOG2_ENDPTCTRL0_REG(base)           ((base)->UOG2_ENDPTCTRL0)
35848 #define USBC_UOG2_ENDPTCTRL1_REG(base)           ((base)->UOG2_ENDPTCTRL1)
35849 #define USBC_UOG2_ENDPTCTRL2_REG(base)           ((base)->UOG2_ENDPTCTRL2)
35850 #define USBC_UOG2_ENDPTCTRL3_REG(base)           ((base)->UOG2_ENDPTCTRL3)
35851 #define USBC_UOG2_ENDPTCTRL4_REG(base)           ((base)->UOG2_ENDPTCTRL4)
35852 #define USBC_UOG2_ENDPTCTRL5_REG(base)           ((base)->UOG2_ENDPTCTRL5)
35853 #define USBC_UOG2_ENDPTCTRL6_REG(base)           ((base)->UOG2_ENDPTCTRL6)
35854 #define USBC_UOG2_ENDPTCTRL7_REG(base)           ((base)->UOG2_ENDPTCTRL7)
35855 #define USBC_UH1_ID_REG(base)                    ((base)->UH1_ID)
35856 #define USBC_UH1_HWGENERAL_REG(base)             ((base)->UH1_HWGENERAL)
35857 #define USBC_UH1_HWHOST_REG(base)                ((base)->UH1_HWHOST)
35858 #define USBC_UH1_HWTXBUF_REG(base)               ((base)->UH1_HWTXBUF)
35859 #define USBC_UH1_HWRXBUF_REG(base)               ((base)->UH1_HWRXBUF)
35860 #define USBC_UH1_GPTIMER0LD_REG(base)            ((base)->UH1_GPTIMER0LD)
35861 #define USBC_UH1_GPTIMER0CTRL_REG(base)          ((base)->UH1_GPTIMER0CTRL)
35862 #define USBC_UH1_GPTIMER1LD_REG(base)            ((base)->UH1_GPTIMER1LD)
35863 #define USBC_UH1_GPTIMER1CTRL_REG(base)          ((base)->UH1_GPTIMER1CTRL)
35864 #define USBC_UH1_SBUSCFG_REG(base)               ((base)->UH1_SBUSCFG)
35865 #define USBC_UH1_CAPLENGTH_REG(base)             ((base)->UH1_CAPLENGTH)
35866 #define USBC_UH1_HCIVERSION_REG(base)            ((base)->UH1_HCIVERSION)
35867 #define USBC_UH1_HCSPARAMS_REG(base)             ((base)->UH1_HCSPARAMS)
35868 #define USBC_UH1_HCCPARAMS_REG(base)             ((base)->UH1_HCCPARAMS)
35869 #define USBC_UH1_USBCMD_REG(base)                ((base)->UH1_USBCMD)
35870 #define USBC_UH1_USBSTS_REG(base)                ((base)->UH1_USBSTS)
35871 #define USBC_UH1_USBINTR_REG(base)               ((base)->UH1_USBINTR)
35872 #define USBC_UH1_FRINDEX_REG(base)               ((base)->UH1_FRINDEX)
35873 #define USBC_UH1_PERIODICLISTBASE_REG(base)      ((base)->UH1_PERIODICLISTBASE)
35874 #define USBC_UH1_ASYNCLISTADDR_REG(base)         ((base)->UH1_ASYNCLISTADDR)
35875 #define USBC_UH1_BURSTSIZE_REG(base)             ((base)->UH1_BURSTSIZE)
35876 #define USBC_UH1_TXFILLTUNING_REG(base)          ((base)->UH1_TXFILLTUNING)
35877 #define USBC_UH1_CONFIGFLAG_REG(base)            ((base)->UH1_CONFIGFLAG)
35878 #define USBC_UH1_PORTSC1_REG(base)               ((base)->UH1_PORTSC1)
35879 #define USBC_UH1_USBMODE_REG(base)               ((base)->UH1_USBMODE)
35880 
35881 /*!
35882  * @}
35883  */ /* end of group USBC_Register_Accessor_Macros */
35884 
35885 /* ----------------------------------------------------------------------------
35886    -- USBC Register Masks
35887    ---------------------------------------------------------------------------- */
35888 
35889 /*!
35890  * @addtogroup USBC_Register_Masks USBC Register Masks
35891  * @{
35892  */
35893 
35894 /* UOG1_ID Bit Fields */
35895 #define USBC_UOG1_ID_ID_MASK                     0x3Fu
35896 #define USBC_UOG1_ID_ID_SHIFT                    0
35897 #define USBC_UOG1_ID_ID(x)                       (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_ID_SHIFT))&USBC_UOG1_ID_ID_MASK)
35898 #define USBC_UOG1_ID_NID_MASK                    0x3F00u
35899 #define USBC_UOG1_ID_NID_SHIFT                   8
35900 #define USBC_UOG1_ID_NID(x)                      (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_NID_SHIFT))&USBC_UOG1_ID_NID_MASK)
35901 #define USBC_UOG1_ID_REVISION_MASK               0xFF0000u
35902 #define USBC_UOG1_ID_REVISION_SHIFT              16
35903 #define USBC_UOG1_ID_REVISION(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_REVISION_SHIFT))&USBC_UOG1_ID_REVISION_MASK)
35904 /* UOG1_HWGENERAL Bit Fields */
35905 #define USBC_UOG1_HWGENERAL_PHYW_MASK            0x30u
35906 #define USBC_UOG1_HWGENERAL_PHYW_SHIFT           4
35907 #define USBC_UOG1_HWGENERAL_PHYW(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_PHYW_SHIFT))&USBC_UOG1_HWGENERAL_PHYW_MASK)
35908 #define USBC_UOG1_HWGENERAL_PHYM_MASK            0x1C0u
35909 #define USBC_UOG1_HWGENERAL_PHYM_SHIFT           6
35910 #define USBC_UOG1_HWGENERAL_PHYM(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_PHYM_SHIFT))&USBC_UOG1_HWGENERAL_PHYM_MASK)
35911 #define USBC_UOG1_HWGENERAL_SM_MASK              0x600u
35912 #define USBC_UOG1_HWGENERAL_SM_SHIFT             9
35913 #define USBC_UOG1_HWGENERAL_SM(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_SM_SHIFT))&USBC_UOG1_HWGENERAL_SM_MASK)
35914 /* UOG1_HWHOST Bit Fields */
35915 #define USBC_UOG1_HWHOST_HC_MASK                 0x1u
35916 #define USBC_UOG1_HWHOST_HC_SHIFT                0
35917 #define USBC_UOG1_HWHOST_NPORT_MASK              0xEu
35918 #define USBC_UOG1_HWHOST_NPORT_SHIFT             1
35919 #define USBC_UOG1_HWHOST_NPORT(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWHOST_NPORT_SHIFT))&USBC_UOG1_HWHOST_NPORT_MASK)
35920 /* UOG1_HWDEVICE Bit Fields */
35921 #define USBC_UOG1_HWDEVICE_DC_MASK               0x1u
35922 #define USBC_UOG1_HWDEVICE_DC_SHIFT              0
35923 #define USBC_UOG1_HWDEVICE_DEVEP_MASK            0x3Eu
35924 #define USBC_UOG1_HWDEVICE_DEVEP_SHIFT           1
35925 #define USBC_UOG1_HWDEVICE_DEVEP(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWDEVICE_DEVEP_SHIFT))&USBC_UOG1_HWDEVICE_DEVEP_MASK)
35926 /* UOG1_HWTXBUF Bit Fields */
35927 #define USBC_UOG1_HWTXBUF_TXBURST_MASK           0xFFu
35928 #define USBC_UOG1_HWTXBUF_TXBURST_SHIFT          0
35929 #define USBC_UOG1_HWTXBUF_TXBURST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWTXBUF_TXBURST_SHIFT))&USBC_UOG1_HWTXBUF_TXBURST_MASK)
35930 #define USBC_UOG1_HWTXBUF_TXCHANADD_MASK         0xFF0000u
35931 #define USBC_UOG1_HWTXBUF_TXCHANADD_SHIFT        16
35932 #define USBC_UOG1_HWTXBUF_TXCHANADD(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWTXBUF_TXCHANADD_SHIFT))&USBC_UOG1_HWTXBUF_TXCHANADD_MASK)
35933 /* UOG1_HWRXBUF Bit Fields */
35934 #define USBC_UOG1_HWRXBUF_RXBURST_MASK           0xFFu
35935 #define USBC_UOG1_HWRXBUF_RXBURST_SHIFT          0
35936 #define USBC_UOG1_HWRXBUF_RXBURST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWRXBUF_RXBURST_SHIFT))&USBC_UOG1_HWRXBUF_RXBURST_MASK)
35937 #define USBC_UOG1_HWRXBUF_RXADD_MASK             0xFF00u
35938 #define USBC_UOG1_HWRXBUF_RXADD_SHIFT            8
35939 #define USBC_UOG1_HWRXBUF_RXADD(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWRXBUF_RXADD_SHIFT))&USBC_UOG1_HWRXBUF_RXADD_MASK)
35940 /* UOG1_GPTIMER0LD Bit Fields */
35941 #define USBC_UOG1_GPTIMER0LD_GPTLD_MASK          0xFFFFFFu
35942 #define USBC_UOG1_GPTIMER0LD_GPTLD_SHIFT         0
35943 #define USBC_UOG1_GPTIMER0LD_GPTLD(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER0LD_GPTLD_SHIFT))&USBC_UOG1_GPTIMER0LD_GPTLD_MASK)
35944 /* UOG1_GPTIMER0CTRL Bit Fields */
35945 #define USBC_UOG1_GPTIMER0CTRL_GPTCNT_MASK       0xFFFFFFu
35946 #define USBC_UOG1_GPTIMER0CTRL_GPTCNT_SHIFT      0
35947 #define USBC_UOG1_GPTIMER0CTRL_GPTCNT(x)         (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UOG1_GPTIMER0CTRL_GPTCNT_MASK)
35948 #define USBC_UOG1_GPTIMER0CTRL_GPTMODE_MASK      0x1000000u
35949 #define USBC_UOG1_GPTIMER0CTRL_GPTMODE_SHIFT     24
35950 #define USBC_UOG1_GPTIMER0CTRL_GPTRST_MASK       0x40000000u
35951 #define USBC_UOG1_GPTIMER0CTRL_GPTRST_SHIFT      30
35952 #define USBC_UOG1_GPTIMER0CTRL_GPTRUN_MASK       0x80000000u
35953 #define USBC_UOG1_GPTIMER0CTRL_GPTRUN_SHIFT      31
35954 /* UOG1_GPTIMER1LD Bit Fields */
35955 #define USBC_UOG1_GPTIMER1LD_GPTLD_MASK          0xFFFFFFu
35956 #define USBC_UOG1_GPTIMER1LD_GPTLD_SHIFT         0
35957 #define USBC_UOG1_GPTIMER1LD_GPTLD(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER1LD_GPTLD_SHIFT))&USBC_UOG1_GPTIMER1LD_GPTLD_MASK)
35958 /* UOG1_GPTIMER1CTRL Bit Fields */
35959 #define USBC_UOG1_GPTIMER1CTRL_GPTCNT_MASK       0xFFFFFFu
35960 #define USBC_UOG1_GPTIMER1CTRL_GPTCNT_SHIFT      0
35961 #define USBC_UOG1_GPTIMER1CTRL_GPTCNT(x)         (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UOG1_GPTIMER1CTRL_GPTCNT_MASK)
35962 #define USBC_UOG1_GPTIMER1CTRL_GPTMODE_MASK      0x1000000u
35963 #define USBC_UOG1_GPTIMER1CTRL_GPTMODE_SHIFT     24
35964 #define USBC_UOG1_GPTIMER1CTRL_GPTRST_MASK       0x40000000u
35965 #define USBC_UOG1_GPTIMER1CTRL_GPTRST_SHIFT      30
35966 #define USBC_UOG1_GPTIMER1CTRL_GPTRUN_MASK       0x80000000u
35967 #define USBC_UOG1_GPTIMER1CTRL_GPTRUN_SHIFT      31
35968 /* UOG1_SBUSCFG Bit Fields */
35969 #define USBC_UOG1_SBUSCFG_AHBBRST_MASK           0x7u
35970 #define USBC_UOG1_SBUSCFG_AHBBRST_SHIFT          0
35971 #define USBC_UOG1_SBUSCFG_AHBBRST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_SBUSCFG_AHBBRST_SHIFT))&USBC_UOG1_SBUSCFG_AHBBRST_MASK)
35972 /* UOG1_CAPLENGTH Bit Fields */
35973 #define USBC_UOG1_CAPLENGTH_CAPLENGTH_MASK       0xFFu
35974 #define USBC_UOG1_CAPLENGTH_CAPLENGTH_SHIFT      0
35975 #define USBC_UOG1_CAPLENGTH_CAPLENGTH(x)         (((uint8_t)(((uint8_t)(x))<<USBC_UOG1_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UOG1_CAPLENGTH_CAPLENGTH_MASK)
35976 /* UOG1_HCIVERSION Bit Fields */
35977 #define USBC_UOG1_HCIVERSION_HCIVERSION_MASK     0xFFFFu
35978 #define USBC_UOG1_HCIVERSION_HCIVERSION_SHIFT    0
35979 #define USBC_UOG1_HCIVERSION_HCIVERSION(x)       (((uint16_t)(((uint16_t)(x))<<USBC_UOG1_HCIVERSION_HCIVERSION_SHIFT))&USBC_UOG1_HCIVERSION_HCIVERSION_MASK)
35980 /* UOG1_HCSPARAMS Bit Fields */
35981 #define USBC_UOG1_HCSPARAMS_N_PORTS_MASK         0xFu
35982 #define USBC_UOG1_HCSPARAMS_N_PORTS_SHIFT        0
35983 #define USBC_UOG1_HCSPARAMS_N_PORTS(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PORTS_SHIFT))&USBC_UOG1_HCSPARAMS_N_PORTS_MASK)
35984 #define USBC_UOG1_HCSPARAMS_PPC_MASK             0x10u
35985 #define USBC_UOG1_HCSPARAMS_PPC_SHIFT            4
35986 #define USBC_UOG1_HCSPARAMS_N_PCC_MASK           0xF00u
35987 #define USBC_UOG1_HCSPARAMS_N_PCC_SHIFT          8
35988 #define USBC_UOG1_HCSPARAMS_N_PCC(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PCC_SHIFT))&USBC_UOG1_HCSPARAMS_N_PCC_MASK)
35989 #define USBC_UOG1_HCSPARAMS_N_CC_MASK            0xF000u
35990 #define USBC_UOG1_HCSPARAMS_N_CC_SHIFT           12
35991 #define USBC_UOG1_HCSPARAMS_N_CC(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_CC_SHIFT))&USBC_UOG1_HCSPARAMS_N_CC_MASK)
35992 #define USBC_UOG1_HCSPARAMS_PI_MASK              0x10000u
35993 #define USBC_UOG1_HCSPARAMS_PI_SHIFT             16
35994 #define USBC_UOG1_HCSPARAMS_N_PTT_MASK           0xF00000u
35995 #define USBC_UOG1_HCSPARAMS_N_PTT_SHIFT          20
35996 #define USBC_UOG1_HCSPARAMS_N_PTT(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PTT_SHIFT))&USBC_UOG1_HCSPARAMS_N_PTT_MASK)
35997 #define USBC_UOG1_HCSPARAMS_N_TT_MASK            0xF000000u
35998 #define USBC_UOG1_HCSPARAMS_N_TT_SHIFT           24
35999 #define USBC_UOG1_HCSPARAMS_N_TT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_TT_SHIFT))&USBC_UOG1_HCSPARAMS_N_TT_MASK)
36000 /* UOG1_HCCPARAMS Bit Fields */
36001 #define USBC_UOG1_HCCPARAMS_ADC_MASK             0x1u
36002 #define USBC_UOG1_HCCPARAMS_ADC_SHIFT            0
36003 #define USBC_UOG1_HCCPARAMS_PFL_MASK             0x2u
36004 #define USBC_UOG1_HCCPARAMS_PFL_SHIFT            1
36005 #define USBC_UOG1_HCCPARAMS_ASP_MASK             0x4u
36006 #define USBC_UOG1_HCCPARAMS_ASP_SHIFT            2
36007 #define USBC_UOG1_HCCPARAMS_IST_MASK             0xF0u
36008 #define USBC_UOG1_HCCPARAMS_IST_SHIFT            4
36009 #define USBC_UOG1_HCCPARAMS_IST(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCCPARAMS_IST_SHIFT))&USBC_UOG1_HCCPARAMS_IST_MASK)
36010 #define USBC_UOG1_HCCPARAMS_EECP_MASK            0xFF00u
36011 #define USBC_UOG1_HCCPARAMS_EECP_SHIFT           8
36012 #define USBC_UOG1_HCCPARAMS_EECP(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCCPARAMS_EECP_SHIFT))&USBC_UOG1_HCCPARAMS_EECP_MASK)
36013 /* UOG1_DCIVERSION Bit Fields */
36014 #define USBC_UOG1_DCIVERSION_DCIVERSION_MASK     0xFFFFu
36015 #define USBC_UOG1_DCIVERSION_DCIVERSION_SHIFT    0
36016 #define USBC_UOG1_DCIVERSION_DCIVERSION(x)       (((uint16_t)(((uint16_t)(x))<<USBC_UOG1_DCIVERSION_DCIVERSION_SHIFT))&USBC_UOG1_DCIVERSION_DCIVERSION_MASK)
36017 /* UOG1_DCCPARAMS Bit Fields */
36018 #define USBC_UOG1_DCCPARAMS_DEN_MASK             0x1Fu
36019 #define USBC_UOG1_DCCPARAMS_DEN_SHIFT            0
36020 #define USBC_UOG1_DCCPARAMS_DEN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_DCCPARAMS_DEN_SHIFT))&USBC_UOG1_DCCPARAMS_DEN_MASK)
36021 #define USBC_UOG1_DCCPARAMS_DC_MASK              0x80u
36022 #define USBC_UOG1_DCCPARAMS_DC_SHIFT             7
36023 #define USBC_UOG1_DCCPARAMS_HC_MASK              0x100u
36024 #define USBC_UOG1_DCCPARAMS_HC_SHIFT             8
36025 /* UOG1_USBCMD Bit Fields */
36026 #define USBC_UOG1_USBCMD_RS_MASK                 0x1u
36027 #define USBC_UOG1_USBCMD_RS_SHIFT                0
36028 #define USBC_UOG1_USBCMD_RST_MASK                0x2u
36029 #define USBC_UOG1_USBCMD_RST_SHIFT               1
36030 #define USBC_UOG1_USBCMD_FS_1_MASK               0xCu
36031 #define USBC_UOG1_USBCMD_FS_1_SHIFT              2
36032 #define USBC_UOG1_USBCMD_FS_1(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_FS_1_SHIFT))&USBC_UOG1_USBCMD_FS_1_MASK)
36033 #define USBC_UOG1_USBCMD_PSE_MASK                0x10u
36034 #define USBC_UOG1_USBCMD_PSE_SHIFT               4
36035 #define USBC_UOG1_USBCMD_ASE_MASK                0x20u
36036 #define USBC_UOG1_USBCMD_ASE_SHIFT               5
36037 #define USBC_UOG1_USBCMD_IAA_MASK                0x40u
36038 #define USBC_UOG1_USBCMD_IAA_SHIFT               6
36039 #define USBC_UOG1_USBCMD_ASP_MASK                0x300u
36040 #define USBC_UOG1_USBCMD_ASP_SHIFT               8
36041 #define USBC_UOG1_USBCMD_ASP(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_ASP_SHIFT))&USBC_UOG1_USBCMD_ASP_MASK)
36042 #define USBC_UOG1_USBCMD_ASPE_MASK               0x800u
36043 #define USBC_UOG1_USBCMD_ASPE_SHIFT              11
36044 #define USBC_UOG1_USBCMD_SUTW_MASK               0x2000u
36045 #define USBC_UOG1_USBCMD_SUTW_SHIFT              13
36046 #define USBC_UOG1_USBCMD_ATDTW_MASK              0x4000u
36047 #define USBC_UOG1_USBCMD_ATDTW_SHIFT             14
36048 #define USBC_UOG1_USBCMD_FS_2_MASK               0x8000u
36049 #define USBC_UOG1_USBCMD_FS_2_SHIFT              15
36050 #define USBC_UOG1_USBCMD_ITC_MASK                0xFF0000u
36051 #define USBC_UOG1_USBCMD_ITC_SHIFT               16
36052 #define USBC_UOG1_USBCMD_ITC(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_ITC_SHIFT))&USBC_UOG1_USBCMD_ITC_MASK)
36053 /* UOG1_USBSTS Bit Fields */
36054 #define USBC_UOG1_USBSTS_UI_MASK                 0x1u
36055 #define USBC_UOG1_USBSTS_UI_SHIFT                0
36056 #define USBC_UOG1_USBSTS_UEI_MASK                0x2u
36057 #define USBC_UOG1_USBSTS_UEI_SHIFT               1
36058 #define USBC_UOG1_USBSTS_PCI_MASK                0x4u
36059 #define USBC_UOG1_USBSTS_PCI_SHIFT               2
36060 #define USBC_UOG1_USBSTS_FRI_MASK                0x8u
36061 #define USBC_UOG1_USBSTS_FRI_SHIFT               3
36062 #define USBC_UOG1_USBSTS_SEI_MASK                0x10u
36063 #define USBC_UOG1_USBSTS_SEI_SHIFT               4
36064 #define USBC_UOG1_USBSTS_AAI_MASK                0x20u
36065 #define USBC_UOG1_USBSTS_AAI_SHIFT               5
36066 #define USBC_UOG1_USBSTS_URI_MASK                0x40u
36067 #define USBC_UOG1_USBSTS_URI_SHIFT               6
36068 #define USBC_UOG1_USBSTS_SRI_MASK                0x80u
36069 #define USBC_UOG1_USBSTS_SRI_SHIFT               7
36070 #define USBC_UOG1_USBSTS_SLI_MASK                0x100u
36071 #define USBC_UOG1_USBSTS_SLI_SHIFT               8
36072 #define USBC_UOG1_USBSTS_ULPII_MASK              0x400u
36073 #define USBC_UOG1_USBSTS_ULPII_SHIFT             10
36074 #define USBC_UOG1_USBSTS_HCH_MASK                0x1000u
36075 #define USBC_UOG1_USBSTS_HCH_SHIFT               12
36076 #define USBC_UOG1_USBSTS_RCL_MASK                0x2000u
36077 #define USBC_UOG1_USBSTS_RCL_SHIFT               13
36078 #define USBC_UOG1_USBSTS_PS_MASK                 0x4000u
36079 #define USBC_UOG1_USBSTS_PS_SHIFT                14
36080 #define USBC_UOG1_USBSTS_AS_MASK                 0x8000u
36081 #define USBC_UOG1_USBSTS_AS_SHIFT                15
36082 #define USBC_UOG1_USBSTS_NAKI_MASK               0x10000u
36083 #define USBC_UOG1_USBSTS_NAKI_SHIFT              16
36084 #define USBC_UOG1_USBSTS_TI0_MASK                0x1000000u
36085 #define USBC_UOG1_USBSTS_TI0_SHIFT               24
36086 #define USBC_UOG1_USBSTS_TI1_MASK                0x2000000u
36087 #define USBC_UOG1_USBSTS_TI1_SHIFT               25
36088 /* UOG1_USBINTR Bit Fields */
36089 #define USBC_UOG1_USBINTR_UE_MASK                0x1u
36090 #define USBC_UOG1_USBINTR_UE_SHIFT               0
36091 #define USBC_UOG1_USBINTR_UEE_MASK               0x2u
36092 #define USBC_UOG1_USBINTR_UEE_SHIFT              1
36093 #define USBC_UOG1_USBINTR_PCE_MASK               0x4u
36094 #define USBC_UOG1_USBINTR_PCE_SHIFT              2
36095 #define USBC_UOG1_USBINTR_FRE_MASK               0x8u
36096 #define USBC_UOG1_USBINTR_FRE_SHIFT              3
36097 #define USBC_UOG1_USBINTR_SEE_MASK               0x10u
36098 #define USBC_UOG1_USBINTR_SEE_SHIFT              4
36099 #define USBC_UOG1_USBINTR_AAE_MASK               0x20u
36100 #define USBC_UOG1_USBINTR_AAE_SHIFT              5
36101 #define USBC_UOG1_USBINTR_URE_MASK               0x40u
36102 #define USBC_UOG1_USBINTR_URE_SHIFT              6
36103 #define USBC_UOG1_USBINTR_SRE_MASK               0x80u
36104 #define USBC_UOG1_USBINTR_SRE_SHIFT              7
36105 #define USBC_UOG1_USBINTR_SLE_MASK               0x100u
36106 #define USBC_UOG1_USBINTR_SLE_SHIFT              8
36107 #define USBC_UOG1_USBINTR_ULPIE_MASK             0x400u
36108 #define USBC_UOG1_USBINTR_ULPIE_SHIFT            10
36109 #define USBC_UOG1_USBINTR_NAKE_MASK              0x10000u
36110 #define USBC_UOG1_USBINTR_NAKE_SHIFT             16
36111 #define USBC_UOG1_USBINTR_UAIE_MASK              0x40000u
36112 #define USBC_UOG1_USBINTR_UAIE_SHIFT             18
36113 #define USBC_UOG1_USBINTR_UPIE_MASK              0x80000u
36114 #define USBC_UOG1_USBINTR_UPIE_SHIFT             19
36115 #define USBC_UOG1_USBINTR_TIE0_MASK              0x1000000u
36116 #define USBC_UOG1_USBINTR_TIE0_SHIFT             24
36117 #define USBC_UOG1_USBINTR_TIE1_MASK              0x2000000u
36118 #define USBC_UOG1_USBINTR_TIE1_SHIFT             25
36119 /* UOG1_FRINDEX Bit Fields */
36120 #define USBC_UOG1_FRINDEX_FRINDEX_MASK           0x3FFFu
36121 #define USBC_UOG1_FRINDEX_FRINDEX_SHIFT          0
36122 #define USBC_UOG1_FRINDEX_FRINDEX(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_FRINDEX_FRINDEX_SHIFT))&USBC_UOG1_FRINDEX_FRINDEX_MASK)
36123 /* UOG1_PERIODICLISTBASE Bit Fields */
36124 #define USBC_UOG1_PERIODICLISTBASE_BASEADR_MASK  0xFFFFF000u
36125 #define USBC_UOG1_PERIODICLISTBASE_BASEADR_SHIFT 12
36126 #define USBC_UOG1_PERIODICLISTBASE_BASEADR(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UOG1_PERIODICLISTBASE_BASEADR_MASK)
36127 /* UOG1_DEVICEADDR Bit Fields */
36128 #define USBC_UOG1_DEVICEADDR_USBADRA_MASK        0x1000000u
36129 #define USBC_UOG1_DEVICEADDR_USBADRA_SHIFT       24
36130 #define USBC_UOG1_DEVICEADDR_USBADR_MASK         0xFE000000u
36131 #define USBC_UOG1_DEVICEADDR_USBADR_SHIFT        25
36132 #define USBC_UOG1_DEVICEADDR_USBADR(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_DEVICEADDR_USBADR_SHIFT))&USBC_UOG1_DEVICEADDR_USBADR_MASK)
36133 /* UOG1_ASYNCLISTADDR Bit Fields */
36134 #define USBC_UOG1_ASYNCLISTADDR_ASYBASE_MASK     0xFFFFFFE0u
36135 #define USBC_UOG1_ASYNCLISTADDR_ASYBASE_SHIFT    5
36136 #define USBC_UOG1_ASYNCLISTADDR_ASYBASE(x)       (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UOG1_ASYNCLISTADDR_ASYBASE_MASK)
36137 /* UOG1_ENDPTLISTADDR Bit Fields */
36138 #define USBC_UOG1_ENDPTLISTADDR_EPBASE_MASK      0xFFFFF800u
36139 #define USBC_UOG1_ENDPTLISTADDR_EPBASE_SHIFT     11
36140 #define USBC_UOG1_ENDPTLISTADDR_EPBASE(x)        (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTLISTADDR_EPBASE_SHIFT))&USBC_UOG1_ENDPTLISTADDR_EPBASE_MASK)
36141 /* UOG1_BURSTSIZE Bit Fields */
36142 #define USBC_UOG1_BURSTSIZE_RXPBURST_MASK        0xFFu
36143 #define USBC_UOG1_BURSTSIZE_RXPBURST_SHIFT       0
36144 #define USBC_UOG1_BURSTSIZE_RXPBURST(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_BURSTSIZE_RXPBURST_SHIFT))&USBC_UOG1_BURSTSIZE_RXPBURST_MASK)
36145 #define USBC_UOG1_BURSTSIZE_TXPBURST_MASK        0x1FF00u
36146 #define USBC_UOG1_BURSTSIZE_TXPBURST_SHIFT       8
36147 #define USBC_UOG1_BURSTSIZE_TXPBURST(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_BURSTSIZE_TXPBURST_SHIFT))&USBC_UOG1_BURSTSIZE_TXPBURST_MASK)
36148 /* UOG1_TXFILLTUNING Bit Fields */
36149 #define USBC_UOG1_TXFILLTUNING_TXSCHOH_MASK      0xFFu
36150 #define USBC_UOG1_TXFILLTUNING_TXSCHOH_SHIFT     0
36151 #define USBC_UOG1_TXFILLTUNING_TXSCHOH(x)        (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UOG1_TXFILLTUNING_TXSCHOH_MASK)
36152 #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_MASK  0x1F00u
36153 #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_SHIFT 8
36154 #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_MASK)
36155 #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_MASK  0x3F0000u
36156 #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_SHIFT 16
36157 #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_MASK)
36158 /* UOG1_ENDPTNAK Bit Fields */
36159 #define USBC_UOG1_ENDPTNAK_EPRN_MASK             0xFFu
36160 #define USBC_UOG1_ENDPTNAK_EPRN_SHIFT            0
36161 #define USBC_UOG1_ENDPTNAK_EPRN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAK_EPRN_SHIFT))&USBC_UOG1_ENDPTNAK_EPRN_MASK)
36162 #define USBC_UOG1_ENDPTNAK_EPTN_MASK             0xFF0000u
36163 #define USBC_UOG1_ENDPTNAK_EPTN_SHIFT            16
36164 #define USBC_UOG1_ENDPTNAK_EPTN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAK_EPTN_SHIFT))&USBC_UOG1_ENDPTNAK_EPTN_MASK)
36165 /* UOG1_ENDPTNAKEN Bit Fields */
36166 #define USBC_UOG1_ENDPTNAKEN_EPRNE_MASK          0xFFu
36167 #define USBC_UOG1_ENDPTNAKEN_EPRNE_SHIFT         0
36168 #define USBC_UOG1_ENDPTNAKEN_EPRNE(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAKEN_EPRNE_SHIFT))&USBC_UOG1_ENDPTNAKEN_EPRNE_MASK)
36169 #define USBC_UOG1_ENDPTNAKEN_EPTNE_MASK          0xFF0000u
36170 #define USBC_UOG1_ENDPTNAKEN_EPTNE_SHIFT         16
36171 #define USBC_UOG1_ENDPTNAKEN_EPTNE(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAKEN_EPTNE_SHIFT))&USBC_UOG1_ENDPTNAKEN_EPTNE_MASK)
36172 /* UOG1_CONFIGFLAG Bit Fields */
36173 #define USBC_UOG1_CONFIGFLAG_CF_MASK             0x1u
36174 #define USBC_UOG1_CONFIGFLAG_CF_SHIFT            0
36175 /* UOG1_PORTSC1 Bit Fields */
36176 #define USBC_UOG1_PORTSC1_CCS_MASK               0x1u
36177 #define USBC_UOG1_PORTSC1_CCS_SHIFT              0
36178 #define USBC_UOG1_PORTSC1_CSC_MASK               0x2u
36179 #define USBC_UOG1_PORTSC1_CSC_SHIFT              1
36180 #define USBC_UOG1_PORTSC1_PE_MASK                0x4u
36181 #define USBC_UOG1_PORTSC1_PE_SHIFT               2
36182 #define USBC_UOG1_PORTSC1_PEC_MASK               0x8u
36183 #define USBC_UOG1_PORTSC1_PEC_SHIFT              3
36184 #define USBC_UOG1_PORTSC1_OCA_MASK               0x10u
36185 #define USBC_UOG1_PORTSC1_OCA_SHIFT              4
36186 #define USBC_UOG1_PORTSC1_OCC_MASK               0x20u
36187 #define USBC_UOG1_PORTSC1_OCC_SHIFT              5
36188 #define USBC_UOG1_PORTSC1_FPR_MASK               0x40u
36189 #define USBC_UOG1_PORTSC1_FPR_SHIFT              6
36190 #define USBC_UOG1_PORTSC1_SUSP_MASK              0x80u
36191 #define USBC_UOG1_PORTSC1_SUSP_SHIFT             7
36192 #define USBC_UOG1_PORTSC1_PR_MASK                0x100u
36193 #define USBC_UOG1_PORTSC1_PR_SHIFT               8
36194 #define USBC_UOG1_PORTSC1_HSP_MASK               0x200u
36195 #define USBC_UOG1_PORTSC1_HSP_SHIFT              9
36196 #define USBC_UOG1_PORTSC1_LS_MASK                0xC00u
36197 #define USBC_UOG1_PORTSC1_LS_SHIFT               10
36198 #define USBC_UOG1_PORTSC1_LS(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_LS_SHIFT))&USBC_UOG1_PORTSC1_LS_MASK)
36199 #define USBC_UOG1_PORTSC1_PP_MASK                0x1000u
36200 #define USBC_UOG1_PORTSC1_PP_SHIFT               12
36201 #define USBC_UOG1_PORTSC1_PO_MASK                0x2000u
36202 #define USBC_UOG1_PORTSC1_PO_SHIFT               13
36203 #define USBC_UOG1_PORTSC1_PIC_MASK               0xC000u
36204 #define USBC_UOG1_PORTSC1_PIC_SHIFT              14
36205 #define USBC_UOG1_PORTSC1_PIC(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PIC_SHIFT))&USBC_UOG1_PORTSC1_PIC_MASK)
36206 #define USBC_UOG1_PORTSC1_PTC_MASK               0xF0000u
36207 #define USBC_UOG1_PORTSC1_PTC_SHIFT              16
36208 #define USBC_UOG1_PORTSC1_PTC(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PTC_SHIFT))&USBC_UOG1_PORTSC1_PTC_MASK)
36209 #define USBC_UOG1_PORTSC1_WKCN_MASK              0x100000u
36210 #define USBC_UOG1_PORTSC1_WKCN_SHIFT             20
36211 #define USBC_UOG1_PORTSC1_WKDC_MASK              0x200000u
36212 #define USBC_UOG1_PORTSC1_WKDC_SHIFT             21
36213 #define USBC_UOG1_PORTSC1_WKOC_MASK              0x400000u
36214 #define USBC_UOG1_PORTSC1_WKOC_SHIFT             22
36215 #define USBC_UOG1_PORTSC1_PHCD_MASK              0x800000u
36216 #define USBC_UOG1_PORTSC1_PHCD_SHIFT             23
36217 #define USBC_UOG1_PORTSC1_PFSC_MASK              0x1000000u
36218 #define USBC_UOG1_PORTSC1_PFSC_SHIFT             24
36219 #define USBC_UOG1_PORTSC1_PTS_2_MASK             0x2000000u
36220 #define USBC_UOG1_PORTSC1_PTS_2_SHIFT            25
36221 #define USBC_UOG1_PORTSC1_PSPD_MASK              0xC000000u
36222 #define USBC_UOG1_PORTSC1_PSPD_SHIFT             26
36223 #define USBC_UOG1_PORTSC1_PSPD(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PSPD_SHIFT))&USBC_UOG1_PORTSC1_PSPD_MASK)
36224 #define USBC_UOG1_PORTSC1_PTW_MASK               0x10000000u
36225 #define USBC_UOG1_PORTSC1_PTW_SHIFT              28
36226 #define USBC_UOG1_PORTSC1_STS_MASK               0x20000000u
36227 #define USBC_UOG1_PORTSC1_STS_SHIFT              29
36228 #define USBC_UOG1_PORTSC1_PTS_1_MASK             0xC0000000u
36229 #define USBC_UOG1_PORTSC1_PTS_1_SHIFT            30
36230 #define USBC_UOG1_PORTSC1_PTS_1(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PTS_1_SHIFT))&USBC_UOG1_PORTSC1_PTS_1_MASK)
36231 /* UOG1_OTGSC Bit Fields */
36232 #define USBC_UOG1_OTGSC_VD_MASK                  0x1u
36233 #define USBC_UOG1_OTGSC_VD_SHIFT                 0
36234 #define USBC_UOG1_OTGSC_VC_MASK                  0x2u
36235 #define USBC_UOG1_OTGSC_VC_SHIFT                 1
36236 #define USBC_UOG1_OTGSC_OT_MASK                  0x8u
36237 #define USBC_UOG1_OTGSC_OT_SHIFT                 3
36238 #define USBC_UOG1_OTGSC_DP_MASK                  0x10u
36239 #define USBC_UOG1_OTGSC_DP_SHIFT                 4
36240 #define USBC_UOG1_OTGSC_IDPU_MASK                0x20u
36241 #define USBC_UOG1_OTGSC_IDPU_SHIFT               5
36242 #define USBC_UOG1_OTGSC_ID_MASK                  0x100u
36243 #define USBC_UOG1_OTGSC_ID_SHIFT                 8
36244 #define USBC_UOG1_OTGSC_AVV_MASK                 0x200u
36245 #define USBC_UOG1_OTGSC_AVV_SHIFT                9
36246 #define USBC_UOG1_OTGSC_ASV_MASK                 0x400u
36247 #define USBC_UOG1_OTGSC_ASV_SHIFT                10
36248 #define USBC_UOG1_OTGSC_BSV_MASK                 0x800u
36249 #define USBC_UOG1_OTGSC_BSV_SHIFT                11
36250 #define USBC_UOG1_OTGSC_BSE_MASK                 0x1000u
36251 #define USBC_UOG1_OTGSC_BSE_SHIFT                12
36252 #define USBC_UOG1_OTGSC_TOG_1MS_MASK             0x2000u
36253 #define USBC_UOG1_OTGSC_TOG_1MS_SHIFT            13
36254 #define USBC_UOG1_OTGSC_DPS_MASK                 0x4000u
36255 #define USBC_UOG1_OTGSC_DPS_SHIFT                14
36256 #define USBC_UOG1_OTGSC_IDIS_MASK                0x10000u
36257 #define USBC_UOG1_OTGSC_IDIS_SHIFT               16
36258 #define USBC_UOG1_OTGSC_AVVIS_MASK               0x20000u
36259 #define USBC_UOG1_OTGSC_AVVIS_SHIFT              17
36260 #define USBC_UOG1_OTGSC_ASVIS_MASK               0x40000u
36261 #define USBC_UOG1_OTGSC_ASVIS_SHIFT              18
36262 #define USBC_UOG1_OTGSC_BSVIS_MASK               0x80000u
36263 #define USBC_UOG1_OTGSC_BSVIS_SHIFT              19
36264 #define USBC_UOG1_OTGSC_BSEIS_MASK               0x100000u
36265 #define USBC_UOG1_OTGSC_BSEIS_SHIFT              20
36266 #define USBC_UOG1_OTGSC_STATUS_1MS_MASK          0x200000u
36267 #define USBC_UOG1_OTGSC_STATUS_1MS_SHIFT         21
36268 #define USBC_UOG1_OTGSC_DPIS_MASK                0x400000u
36269 #define USBC_UOG1_OTGSC_DPIS_SHIFT               22
36270 #define USBC_UOG1_OTGSC_IDIE_MASK                0x1000000u
36271 #define USBC_UOG1_OTGSC_IDIE_SHIFT               24
36272 #define USBC_UOG1_OTGSC_AVVIE_MASK               0x2000000u
36273 #define USBC_UOG1_OTGSC_AVVIE_SHIFT              25
36274 #define USBC_UOG1_OTGSC_ASVIE_MASK               0x4000000u
36275 #define USBC_UOG1_OTGSC_ASVIE_SHIFT              26
36276 #define USBC_UOG1_OTGSC_BSVIE_MASK               0x8000000u
36277 #define USBC_UOG1_OTGSC_BSVIE_SHIFT              27
36278 #define USBC_UOG1_OTGSC_BSEIE_MASK               0x10000000u
36279 #define USBC_UOG1_OTGSC_BSEIE_SHIFT              28
36280 #define USBC_UOG1_OTGSC_EN_1MS_MASK              0x20000000u
36281 #define USBC_UOG1_OTGSC_EN_1MS_SHIFT             29
36282 #define USBC_UOG1_OTGSC_DPIE_MASK                0x40000000u
36283 #define USBC_UOG1_OTGSC_DPIE_SHIFT               30
36284 /* UOG1_USBMODE Bit Fields */
36285 #define USBC_UOG1_USBMODE_CM_MASK                0x3u
36286 #define USBC_UOG1_USBMODE_CM_SHIFT               0
36287 #define USBC_UOG1_USBMODE_CM(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBMODE_CM_SHIFT))&USBC_UOG1_USBMODE_CM_MASK)
36288 #define USBC_UOG1_USBMODE_ES_MASK                0x4u
36289 #define USBC_UOG1_USBMODE_ES_SHIFT               2
36290 #define USBC_UOG1_USBMODE_SLOM_MASK              0x8u
36291 #define USBC_UOG1_USBMODE_SLOM_SHIFT             3
36292 #define USBC_UOG1_USBMODE_SDIS_MASK              0x10u
36293 #define USBC_UOG1_USBMODE_SDIS_SHIFT             4
36294 /* UOG1_ENDPTSETUPSTAT Bit Fields */
36295 #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK 0xFFFFu
36296 #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT 0
36297 #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
36298 /* UOG1_ENDPTPRIME Bit Fields */
36299 #define USBC_UOG1_ENDPTPRIME_PERB_MASK           0xFFu
36300 #define USBC_UOG1_ENDPTPRIME_PERB_SHIFT          0
36301 #define USBC_UOG1_ENDPTPRIME_PERB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTPRIME_PERB_SHIFT))&USBC_UOG1_ENDPTPRIME_PERB_MASK)
36302 #define USBC_UOG1_ENDPTPRIME_PETB_MASK           0xFF0000u
36303 #define USBC_UOG1_ENDPTPRIME_PETB_SHIFT          16
36304 #define USBC_UOG1_ENDPTPRIME_PETB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTPRIME_PETB_SHIFT))&USBC_UOG1_ENDPTPRIME_PETB_MASK)
36305 /* UOG1_ENDPTFLUSH Bit Fields */
36306 #define USBC_UOG1_ENDPTFLUSH_FERB_MASK           0xFFu
36307 #define USBC_UOG1_ENDPTFLUSH_FERB_SHIFT          0
36308 #define USBC_UOG1_ENDPTFLUSH_FERB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTFLUSH_FERB_SHIFT))&USBC_UOG1_ENDPTFLUSH_FERB_MASK)
36309 #define USBC_UOG1_ENDPTFLUSH_FETB_MASK           0xFF0000u
36310 #define USBC_UOG1_ENDPTFLUSH_FETB_SHIFT          16
36311 #define USBC_UOG1_ENDPTFLUSH_FETB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTFLUSH_FETB_SHIFT))&USBC_UOG1_ENDPTFLUSH_FETB_MASK)
36312 /* UOG1_ENDPTSTAT Bit Fields */
36313 #define USBC_UOG1_ENDPTSTAT_ERBR_MASK            0xFFu
36314 #define USBC_UOG1_ENDPTSTAT_ERBR_SHIFT           0
36315 #define USBC_UOG1_ENDPTSTAT_ERBR(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSTAT_ERBR_SHIFT))&USBC_UOG1_ENDPTSTAT_ERBR_MASK)
36316 #define USBC_UOG1_ENDPTSTAT_ETBR_MASK            0xFF0000u
36317 #define USBC_UOG1_ENDPTSTAT_ETBR_SHIFT           16
36318 #define USBC_UOG1_ENDPTSTAT_ETBR(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSTAT_ETBR_SHIFT))&USBC_UOG1_ENDPTSTAT_ETBR_MASK)
36319 /* UOG1_ENDPTCOMPLETE Bit Fields */
36320 #define USBC_UOG1_ENDPTCOMPLETE_ERCE_MASK        0xFFu
36321 #define USBC_UOG1_ENDPTCOMPLETE_ERCE_SHIFT       0
36322 #define USBC_UOG1_ENDPTCOMPLETE_ERCE(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCOMPLETE_ERCE_SHIFT))&USBC_UOG1_ENDPTCOMPLETE_ERCE_MASK)
36323 #define USBC_UOG1_ENDPTCOMPLETE_ETCE_MASK        0xFF0000u
36324 #define USBC_UOG1_ENDPTCOMPLETE_ETCE_SHIFT       16
36325 #define USBC_UOG1_ENDPTCOMPLETE_ETCE(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCOMPLETE_ETCE_SHIFT))&USBC_UOG1_ENDPTCOMPLETE_ETCE_MASK)
36326 /* UOG1_ENDPTCTRL0 Bit Fields */
36327 #define USBC_UOG1_ENDPTCTRL0_RXS_MASK            0x1u
36328 #define USBC_UOG1_ENDPTCTRL0_RXS_SHIFT           0
36329 #define USBC_UOG1_ENDPTCTRL0_RXT_MASK            0xCu
36330 #define USBC_UOG1_ENDPTCTRL0_RXT_SHIFT           2
36331 #define USBC_UOG1_ENDPTCTRL0_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL0_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL0_RXT_MASK)
36332 #define USBC_UOG1_ENDPTCTRL0_RXE_MASK            0x80u
36333 #define USBC_UOG1_ENDPTCTRL0_RXE_SHIFT           7
36334 #define USBC_UOG1_ENDPTCTRL0_TXS_MASK            0x10000u
36335 #define USBC_UOG1_ENDPTCTRL0_TXS_SHIFT           16
36336 #define USBC_UOG1_ENDPTCTRL0_TXT_MASK            0xC0000u
36337 #define USBC_UOG1_ENDPTCTRL0_TXT_SHIFT           18
36338 #define USBC_UOG1_ENDPTCTRL0_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL0_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL0_TXT_MASK)
36339 #define USBC_UOG1_ENDPTCTRL0_TXE_MASK            0x800000u
36340 #define USBC_UOG1_ENDPTCTRL0_TXE_SHIFT           23
36341 /* UOG1_ENDPTCTRL1 Bit Fields */
36342 #define USBC_UOG1_ENDPTCTRL1_RXS_MASK            0x1u
36343 #define USBC_UOG1_ENDPTCTRL1_RXS_SHIFT           0
36344 #define USBC_UOG1_ENDPTCTRL1_RXD_MASK            0x2u
36345 #define USBC_UOG1_ENDPTCTRL1_RXD_SHIFT           1
36346 #define USBC_UOG1_ENDPTCTRL1_RXT_MASK            0xCu
36347 #define USBC_UOG1_ENDPTCTRL1_RXT_SHIFT           2
36348 #define USBC_UOG1_ENDPTCTRL1_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL1_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL1_RXT_MASK)
36349 #define USBC_UOG1_ENDPTCTRL1_RXI_MASK            0x20u
36350 #define USBC_UOG1_ENDPTCTRL1_RXI_SHIFT           5
36351 #define USBC_UOG1_ENDPTCTRL1_RXR_MASK            0x40u
36352 #define USBC_UOG1_ENDPTCTRL1_RXR_SHIFT           6
36353 #define USBC_UOG1_ENDPTCTRL1_RXE_MASK            0x80u
36354 #define USBC_UOG1_ENDPTCTRL1_RXE_SHIFT           7
36355 #define USBC_UOG1_ENDPTCTRL1_TXS_MASK            0x10000u
36356 #define USBC_UOG1_ENDPTCTRL1_TXS_SHIFT           16
36357 #define USBC_UOG1_ENDPTCTRL1_TXD_MASK            0x20000u
36358 #define USBC_UOG1_ENDPTCTRL1_TXD_SHIFT           17
36359 #define USBC_UOG1_ENDPTCTRL1_TXT_MASK            0xC0000u
36360 #define USBC_UOG1_ENDPTCTRL1_TXT_SHIFT           18
36361 #define USBC_UOG1_ENDPTCTRL1_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL1_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL1_TXT_MASK)
36362 #define USBC_UOG1_ENDPTCTRL1_TXI_MASK            0x200000u
36363 #define USBC_UOG1_ENDPTCTRL1_TXI_SHIFT           21
36364 #define USBC_UOG1_ENDPTCTRL1_TXR_MASK            0x400000u
36365 #define USBC_UOG1_ENDPTCTRL1_TXR_SHIFT           22
36366 #define USBC_UOG1_ENDPTCTRL1_TXE_MASK            0x800000u
36367 #define USBC_UOG1_ENDPTCTRL1_TXE_SHIFT           23
36368 /* UOG1_ENDPTCTRL2 Bit Fields */
36369 #define USBC_UOG1_ENDPTCTRL2_RXS_MASK            0x1u
36370 #define USBC_UOG1_ENDPTCTRL2_RXS_SHIFT           0
36371 #define USBC_UOG1_ENDPTCTRL2_RXD_MASK            0x2u
36372 #define USBC_UOG1_ENDPTCTRL2_RXD_SHIFT           1
36373 #define USBC_UOG1_ENDPTCTRL2_RXT_MASK            0xCu
36374 #define USBC_UOG1_ENDPTCTRL2_RXT_SHIFT           2
36375 #define USBC_UOG1_ENDPTCTRL2_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL2_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL2_RXT_MASK)
36376 #define USBC_UOG1_ENDPTCTRL2_RXI_MASK            0x20u
36377 #define USBC_UOG1_ENDPTCTRL2_RXI_SHIFT           5
36378 #define USBC_UOG1_ENDPTCTRL2_RXR_MASK            0x40u
36379 #define USBC_UOG1_ENDPTCTRL2_RXR_SHIFT           6
36380 #define USBC_UOG1_ENDPTCTRL2_RXE_MASK            0x80u
36381 #define USBC_UOG1_ENDPTCTRL2_RXE_SHIFT           7
36382 #define USBC_UOG1_ENDPTCTRL2_TXS_MASK            0x10000u
36383 #define USBC_UOG1_ENDPTCTRL2_TXS_SHIFT           16
36384 #define USBC_UOG1_ENDPTCTRL2_TXD_MASK            0x20000u
36385 #define USBC_UOG1_ENDPTCTRL2_TXD_SHIFT           17
36386 #define USBC_UOG1_ENDPTCTRL2_TXT_MASK            0xC0000u
36387 #define USBC_UOG1_ENDPTCTRL2_TXT_SHIFT           18
36388 #define USBC_UOG1_ENDPTCTRL2_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL2_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL2_TXT_MASK)
36389 #define USBC_UOG1_ENDPTCTRL2_TXI_MASK            0x200000u
36390 #define USBC_UOG1_ENDPTCTRL2_TXI_SHIFT           21
36391 #define USBC_UOG1_ENDPTCTRL2_TXR_MASK            0x400000u
36392 #define USBC_UOG1_ENDPTCTRL2_TXR_SHIFT           22
36393 #define USBC_UOG1_ENDPTCTRL2_TXE_MASK            0x800000u
36394 #define USBC_UOG1_ENDPTCTRL2_TXE_SHIFT           23
36395 /* UOG1_ENDPTCTRL3 Bit Fields */
36396 #define USBC_UOG1_ENDPTCTRL3_RXS_MASK            0x1u
36397 #define USBC_UOG1_ENDPTCTRL3_RXS_SHIFT           0
36398 #define USBC_UOG1_ENDPTCTRL3_RXD_MASK            0x2u
36399 #define USBC_UOG1_ENDPTCTRL3_RXD_SHIFT           1
36400 #define USBC_UOG1_ENDPTCTRL3_RXT_MASK            0xCu
36401 #define USBC_UOG1_ENDPTCTRL3_RXT_SHIFT           2
36402 #define USBC_UOG1_ENDPTCTRL3_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL3_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL3_RXT_MASK)
36403 #define USBC_UOG1_ENDPTCTRL3_RXI_MASK            0x20u
36404 #define USBC_UOG1_ENDPTCTRL3_RXI_SHIFT           5
36405 #define USBC_UOG1_ENDPTCTRL3_RXR_MASK            0x40u
36406 #define USBC_UOG1_ENDPTCTRL3_RXR_SHIFT           6
36407 #define USBC_UOG1_ENDPTCTRL3_RXE_MASK            0x80u
36408 #define USBC_UOG1_ENDPTCTRL3_RXE_SHIFT           7
36409 #define USBC_UOG1_ENDPTCTRL3_TXS_MASK            0x10000u
36410 #define USBC_UOG1_ENDPTCTRL3_TXS_SHIFT           16
36411 #define USBC_UOG1_ENDPTCTRL3_TXD_MASK            0x20000u
36412 #define USBC_UOG1_ENDPTCTRL3_TXD_SHIFT           17
36413 #define USBC_UOG1_ENDPTCTRL3_TXT_MASK            0xC0000u
36414 #define USBC_UOG1_ENDPTCTRL3_TXT_SHIFT           18
36415 #define USBC_UOG1_ENDPTCTRL3_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL3_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL3_TXT_MASK)
36416 #define USBC_UOG1_ENDPTCTRL3_TXI_MASK            0x200000u
36417 #define USBC_UOG1_ENDPTCTRL3_TXI_SHIFT           21
36418 #define USBC_UOG1_ENDPTCTRL3_TXR_MASK            0x400000u
36419 #define USBC_UOG1_ENDPTCTRL3_TXR_SHIFT           22
36420 #define USBC_UOG1_ENDPTCTRL3_TXE_MASK            0x800000u
36421 #define USBC_UOG1_ENDPTCTRL3_TXE_SHIFT           23
36422 /* UOG1_ENDPTCTRL4 Bit Fields */
36423 #define USBC_UOG1_ENDPTCTRL4_RXS_MASK            0x1u
36424 #define USBC_UOG1_ENDPTCTRL4_RXS_SHIFT           0
36425 #define USBC_UOG1_ENDPTCTRL4_RXD_MASK            0x2u
36426 #define USBC_UOG1_ENDPTCTRL4_RXD_SHIFT           1
36427 #define USBC_UOG1_ENDPTCTRL4_RXT_MASK            0xCu
36428 #define USBC_UOG1_ENDPTCTRL4_RXT_SHIFT           2
36429 #define USBC_UOG1_ENDPTCTRL4_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL4_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL4_RXT_MASK)
36430 #define USBC_UOG1_ENDPTCTRL4_RXI_MASK            0x20u
36431 #define USBC_UOG1_ENDPTCTRL4_RXI_SHIFT           5
36432 #define USBC_UOG1_ENDPTCTRL4_RXR_MASK            0x40u
36433 #define USBC_UOG1_ENDPTCTRL4_RXR_SHIFT           6
36434 #define USBC_UOG1_ENDPTCTRL4_RXE_MASK            0x80u
36435 #define USBC_UOG1_ENDPTCTRL4_RXE_SHIFT           7
36436 #define USBC_UOG1_ENDPTCTRL4_TXS_MASK            0x10000u
36437 #define USBC_UOG1_ENDPTCTRL4_TXS_SHIFT           16
36438 #define USBC_UOG1_ENDPTCTRL4_TXD_MASK            0x20000u
36439 #define USBC_UOG1_ENDPTCTRL4_TXD_SHIFT           17
36440 #define USBC_UOG1_ENDPTCTRL4_TXT_MASK            0xC0000u
36441 #define USBC_UOG1_ENDPTCTRL4_TXT_SHIFT           18
36442 #define USBC_UOG1_ENDPTCTRL4_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL4_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL4_TXT_MASK)
36443 #define USBC_UOG1_ENDPTCTRL4_TXI_MASK            0x200000u
36444 #define USBC_UOG1_ENDPTCTRL4_TXI_SHIFT           21
36445 #define USBC_UOG1_ENDPTCTRL4_TXR_MASK            0x400000u
36446 #define USBC_UOG1_ENDPTCTRL4_TXR_SHIFT           22
36447 #define USBC_UOG1_ENDPTCTRL4_TXE_MASK            0x800000u
36448 #define USBC_UOG1_ENDPTCTRL4_TXE_SHIFT           23
36449 /* UOG1_ENDPTCTRL5 Bit Fields */
36450 #define USBC_UOG1_ENDPTCTRL5_RXS_MASK            0x1u
36451 #define USBC_UOG1_ENDPTCTRL5_RXS_SHIFT           0
36452 #define USBC_UOG1_ENDPTCTRL5_RXD_MASK            0x2u
36453 #define USBC_UOG1_ENDPTCTRL5_RXD_SHIFT           1
36454 #define USBC_UOG1_ENDPTCTRL5_RXT_MASK            0xCu
36455 #define USBC_UOG1_ENDPTCTRL5_RXT_SHIFT           2
36456 #define USBC_UOG1_ENDPTCTRL5_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL5_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL5_RXT_MASK)
36457 #define USBC_UOG1_ENDPTCTRL5_RXI_MASK            0x20u
36458 #define USBC_UOG1_ENDPTCTRL5_RXI_SHIFT           5
36459 #define USBC_UOG1_ENDPTCTRL5_RXR_MASK            0x40u
36460 #define USBC_UOG1_ENDPTCTRL5_RXR_SHIFT           6
36461 #define USBC_UOG1_ENDPTCTRL5_RXE_MASK            0x80u
36462 #define USBC_UOG1_ENDPTCTRL5_RXE_SHIFT           7
36463 #define USBC_UOG1_ENDPTCTRL5_TXS_MASK            0x10000u
36464 #define USBC_UOG1_ENDPTCTRL5_TXS_SHIFT           16
36465 #define USBC_UOG1_ENDPTCTRL5_TXD_MASK            0x20000u
36466 #define USBC_UOG1_ENDPTCTRL5_TXD_SHIFT           17
36467 #define USBC_UOG1_ENDPTCTRL5_TXT_MASK            0xC0000u
36468 #define USBC_UOG1_ENDPTCTRL5_TXT_SHIFT           18
36469 #define USBC_UOG1_ENDPTCTRL5_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL5_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL5_TXT_MASK)
36470 #define USBC_UOG1_ENDPTCTRL5_TXI_MASK            0x200000u
36471 #define USBC_UOG1_ENDPTCTRL5_TXI_SHIFT           21
36472 #define USBC_UOG1_ENDPTCTRL5_TXR_MASK            0x400000u
36473 #define USBC_UOG1_ENDPTCTRL5_TXR_SHIFT           22
36474 #define USBC_UOG1_ENDPTCTRL5_TXE_MASK            0x800000u
36475 #define USBC_UOG1_ENDPTCTRL5_TXE_SHIFT           23
36476 /* UOG1_ENDPTCTRL6 Bit Fields */
36477 #define USBC_UOG1_ENDPTCTRL6_RXS_MASK            0x1u
36478 #define USBC_UOG1_ENDPTCTRL6_RXS_SHIFT           0
36479 #define USBC_UOG1_ENDPTCTRL6_RXD_MASK            0x2u
36480 #define USBC_UOG1_ENDPTCTRL6_RXD_SHIFT           1
36481 #define USBC_UOG1_ENDPTCTRL6_RXT_MASK            0xCu
36482 #define USBC_UOG1_ENDPTCTRL6_RXT_SHIFT           2
36483 #define USBC_UOG1_ENDPTCTRL6_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL6_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL6_RXT_MASK)
36484 #define USBC_UOG1_ENDPTCTRL6_RXI_MASK            0x20u
36485 #define USBC_UOG1_ENDPTCTRL6_RXI_SHIFT           5
36486 #define USBC_UOG1_ENDPTCTRL6_RXR_MASK            0x40u
36487 #define USBC_UOG1_ENDPTCTRL6_RXR_SHIFT           6
36488 #define USBC_UOG1_ENDPTCTRL6_RXE_MASK            0x80u
36489 #define USBC_UOG1_ENDPTCTRL6_RXE_SHIFT           7
36490 #define USBC_UOG1_ENDPTCTRL6_TXS_MASK            0x10000u
36491 #define USBC_UOG1_ENDPTCTRL6_TXS_SHIFT           16
36492 #define USBC_UOG1_ENDPTCTRL6_TXD_MASK            0x20000u
36493 #define USBC_UOG1_ENDPTCTRL6_TXD_SHIFT           17
36494 #define USBC_UOG1_ENDPTCTRL6_TXT_MASK            0xC0000u
36495 #define USBC_UOG1_ENDPTCTRL6_TXT_SHIFT           18
36496 #define USBC_UOG1_ENDPTCTRL6_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL6_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL6_TXT_MASK)
36497 #define USBC_UOG1_ENDPTCTRL6_TXI_MASK            0x200000u
36498 #define USBC_UOG1_ENDPTCTRL6_TXI_SHIFT           21
36499 #define USBC_UOG1_ENDPTCTRL6_TXR_MASK            0x400000u
36500 #define USBC_UOG1_ENDPTCTRL6_TXR_SHIFT           22
36501 #define USBC_UOG1_ENDPTCTRL6_TXE_MASK            0x800000u
36502 #define USBC_UOG1_ENDPTCTRL6_TXE_SHIFT           23
36503 /* UOG1_ENDPTCTRL7 Bit Fields */
36504 #define USBC_UOG1_ENDPTCTRL7_RXS_MASK            0x1u
36505 #define USBC_UOG1_ENDPTCTRL7_RXS_SHIFT           0
36506 #define USBC_UOG1_ENDPTCTRL7_RXD_MASK            0x2u
36507 #define USBC_UOG1_ENDPTCTRL7_RXD_SHIFT           1
36508 #define USBC_UOG1_ENDPTCTRL7_RXT_MASK            0xCu
36509 #define USBC_UOG1_ENDPTCTRL7_RXT_SHIFT           2
36510 #define USBC_UOG1_ENDPTCTRL7_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL7_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL7_RXT_MASK)
36511 #define USBC_UOG1_ENDPTCTRL7_RXI_MASK            0x20u
36512 #define USBC_UOG1_ENDPTCTRL7_RXI_SHIFT           5
36513 #define USBC_UOG1_ENDPTCTRL7_RXR_MASK            0x40u
36514 #define USBC_UOG1_ENDPTCTRL7_RXR_SHIFT           6
36515 #define USBC_UOG1_ENDPTCTRL7_RXE_MASK            0x80u
36516 #define USBC_UOG1_ENDPTCTRL7_RXE_SHIFT           7
36517 #define USBC_UOG1_ENDPTCTRL7_TXS_MASK            0x10000u
36518 #define USBC_UOG1_ENDPTCTRL7_TXS_SHIFT           16
36519 #define USBC_UOG1_ENDPTCTRL7_TXD_MASK            0x20000u
36520 #define USBC_UOG1_ENDPTCTRL7_TXD_SHIFT           17
36521 #define USBC_UOG1_ENDPTCTRL7_TXT_MASK            0xC0000u
36522 #define USBC_UOG1_ENDPTCTRL7_TXT_SHIFT           18
36523 #define USBC_UOG1_ENDPTCTRL7_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL7_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL7_TXT_MASK)
36524 #define USBC_UOG1_ENDPTCTRL7_TXI_MASK            0x200000u
36525 #define USBC_UOG1_ENDPTCTRL7_TXI_SHIFT           21
36526 #define USBC_UOG1_ENDPTCTRL7_TXR_MASK            0x400000u
36527 #define USBC_UOG1_ENDPTCTRL7_TXR_SHIFT           22
36528 #define USBC_UOG1_ENDPTCTRL7_TXE_MASK            0x800000u
36529 #define USBC_UOG1_ENDPTCTRL7_TXE_SHIFT           23
36530 /* UOG2_ID Bit Fields */
36531 #define USBC_UOG2_ID_ID_MASK                     0x3Fu
36532 #define USBC_UOG2_ID_ID_SHIFT                    0
36533 #define USBC_UOG2_ID_ID(x)                       (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_ID_SHIFT))&USBC_UOG2_ID_ID_MASK)
36534 #define USBC_UOG2_ID_NID_MASK                    0x3F00u
36535 #define USBC_UOG2_ID_NID_SHIFT                   8
36536 #define USBC_UOG2_ID_NID(x)                      (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_NID_SHIFT))&USBC_UOG2_ID_NID_MASK)
36537 #define USBC_UOG2_ID_REVISION_MASK               0xFF0000u
36538 #define USBC_UOG2_ID_REVISION_SHIFT              16
36539 #define USBC_UOG2_ID_REVISION(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_REVISION_SHIFT))&USBC_UOG2_ID_REVISION_MASK)
36540 /* UOG2_HWGENERAL Bit Fields */
36541 #define USBC_UOG2_HWGENERAL_PHYW_MASK            0x30u
36542 #define USBC_UOG2_HWGENERAL_PHYW_SHIFT           4
36543 #define USBC_UOG2_HWGENERAL_PHYW(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_PHYW_SHIFT))&USBC_UOG2_HWGENERAL_PHYW_MASK)
36544 #define USBC_UOG2_HWGENERAL_PHYM_MASK            0x1C0u
36545 #define USBC_UOG2_HWGENERAL_PHYM_SHIFT           6
36546 #define USBC_UOG2_HWGENERAL_PHYM(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_PHYM_SHIFT))&USBC_UOG2_HWGENERAL_PHYM_MASK)
36547 #define USBC_UOG2_HWGENERAL_SM_MASK              0x600u
36548 #define USBC_UOG2_HWGENERAL_SM_SHIFT             9
36549 #define USBC_UOG2_HWGENERAL_SM(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_SM_SHIFT))&USBC_UOG2_HWGENERAL_SM_MASK)
36550 /* UOG2_HWHOST Bit Fields */
36551 #define USBC_UOG2_HWHOST_HC_MASK                 0x1u
36552 #define USBC_UOG2_HWHOST_HC_SHIFT                0
36553 #define USBC_UOG2_HWHOST_NPORT_MASK              0xEu
36554 #define USBC_UOG2_HWHOST_NPORT_SHIFT             1
36555 #define USBC_UOG2_HWHOST_NPORT(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWHOST_NPORT_SHIFT))&USBC_UOG2_HWHOST_NPORT_MASK)
36556 /* UOG2_HWDEVICE Bit Fields */
36557 #define USBC_UOG2_HWDEVICE_DC_MASK               0x1u
36558 #define USBC_UOG2_HWDEVICE_DC_SHIFT              0
36559 #define USBC_UOG2_HWDEVICE_DEVEP_MASK            0x3Eu
36560 #define USBC_UOG2_HWDEVICE_DEVEP_SHIFT           1
36561 #define USBC_UOG2_HWDEVICE_DEVEP(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWDEVICE_DEVEP_SHIFT))&USBC_UOG2_HWDEVICE_DEVEP_MASK)
36562 /* UOG2_HWTXBUF Bit Fields */
36563 #define USBC_UOG2_HWTXBUF_TXBURST_MASK           0xFFu
36564 #define USBC_UOG2_HWTXBUF_TXBURST_SHIFT          0
36565 #define USBC_UOG2_HWTXBUF_TXBURST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWTXBUF_TXBURST_SHIFT))&USBC_UOG2_HWTXBUF_TXBURST_MASK)
36566 #define USBC_UOG2_HWTXBUF_TXCHANADD_MASK         0xFF0000u
36567 #define USBC_UOG2_HWTXBUF_TXCHANADD_SHIFT        16
36568 #define USBC_UOG2_HWTXBUF_TXCHANADD(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWTXBUF_TXCHANADD_SHIFT))&USBC_UOG2_HWTXBUF_TXCHANADD_MASK)
36569 /* UOG2_HWRXBUF Bit Fields */
36570 #define USBC_UOG2_HWRXBUF_RXBURST_MASK           0xFFu
36571 #define USBC_UOG2_HWRXBUF_RXBURST_SHIFT          0
36572 #define USBC_UOG2_HWRXBUF_RXBURST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWRXBUF_RXBURST_SHIFT))&USBC_UOG2_HWRXBUF_RXBURST_MASK)
36573 #define USBC_UOG2_HWRXBUF_RXADD_MASK             0xFF00u
36574 #define USBC_UOG2_HWRXBUF_RXADD_SHIFT            8
36575 #define USBC_UOG2_HWRXBUF_RXADD(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWRXBUF_RXADD_SHIFT))&USBC_UOG2_HWRXBUF_RXADD_MASK)
36576 /* UOG2_GPTIMER0LD Bit Fields */
36577 #define USBC_UOG2_GPTIMER0LD_GPTLD_MASK          0xFFFFFFu
36578 #define USBC_UOG2_GPTIMER0LD_GPTLD_SHIFT         0
36579 #define USBC_UOG2_GPTIMER0LD_GPTLD(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER0LD_GPTLD_SHIFT))&USBC_UOG2_GPTIMER0LD_GPTLD_MASK)
36580 /* UOG2_GPTIMER0CTRL Bit Fields */
36581 #define USBC_UOG2_GPTIMER0CTRL_GPTCNT_MASK       0xFFFFFFu
36582 #define USBC_UOG2_GPTIMER0CTRL_GPTCNT_SHIFT      0
36583 #define USBC_UOG2_GPTIMER0CTRL_GPTCNT(x)         (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UOG2_GPTIMER0CTRL_GPTCNT_MASK)
36584 #define USBC_UOG2_GPTIMER0CTRL_GPTMODE_MASK      0x1000000u
36585 #define USBC_UOG2_GPTIMER0CTRL_GPTMODE_SHIFT     24
36586 #define USBC_UOG2_GPTIMER0CTRL_GPTRST_MASK       0x40000000u
36587 #define USBC_UOG2_GPTIMER0CTRL_GPTRST_SHIFT      30
36588 #define USBC_UOG2_GPTIMER0CTRL_GPTRUN_MASK       0x80000000u
36589 #define USBC_UOG2_GPTIMER0CTRL_GPTRUN_SHIFT      31
36590 /* UOG2_GPTIMER1LD Bit Fields */
36591 #define USBC_UOG2_GPTIMER1LD_GPTLD_MASK          0xFFFFFFu
36592 #define USBC_UOG2_GPTIMER1LD_GPTLD_SHIFT         0
36593 #define USBC_UOG2_GPTIMER1LD_GPTLD(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER1LD_GPTLD_SHIFT))&USBC_UOG2_GPTIMER1LD_GPTLD_MASK)
36594 /* UOG2_GPTIMER1CTRL Bit Fields */
36595 #define USBC_UOG2_GPTIMER1CTRL_GPTCNT_MASK       0xFFFFFFu
36596 #define USBC_UOG2_GPTIMER1CTRL_GPTCNT_SHIFT      0
36597 #define USBC_UOG2_GPTIMER1CTRL_GPTCNT(x)         (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UOG2_GPTIMER1CTRL_GPTCNT_MASK)
36598 #define USBC_UOG2_GPTIMER1CTRL_GPTMODE_MASK      0x1000000u
36599 #define USBC_UOG2_GPTIMER1CTRL_GPTMODE_SHIFT     24
36600 #define USBC_UOG2_GPTIMER1CTRL_GPTRST_MASK       0x40000000u
36601 #define USBC_UOG2_GPTIMER1CTRL_GPTRST_SHIFT      30
36602 #define USBC_UOG2_GPTIMER1CTRL_GPTRUN_MASK       0x80000000u
36603 #define USBC_UOG2_GPTIMER1CTRL_GPTRUN_SHIFT      31
36604 /* UOG2_SBUSCFG Bit Fields */
36605 #define USBC_UOG2_SBUSCFG_AHBBRST_MASK           0x7u
36606 #define USBC_UOG2_SBUSCFG_AHBBRST_SHIFT          0
36607 #define USBC_UOG2_SBUSCFG_AHBBRST(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_SBUSCFG_AHBBRST_SHIFT))&USBC_UOG2_SBUSCFG_AHBBRST_MASK)
36608 /* UOG2_CAPLENGTH Bit Fields */
36609 #define USBC_UOG2_CAPLENGTH_CAPLENGTH_MASK       0xFFu
36610 #define USBC_UOG2_CAPLENGTH_CAPLENGTH_SHIFT      0
36611 #define USBC_UOG2_CAPLENGTH_CAPLENGTH(x)         (((uint8_t)(((uint8_t)(x))<<USBC_UOG2_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UOG2_CAPLENGTH_CAPLENGTH_MASK)
36612 /* UOG2_HCIVERSION Bit Fields */
36613 #define USBC_UOG2_HCIVERSION_HCIVERSION_MASK     0xFFFFu
36614 #define USBC_UOG2_HCIVERSION_HCIVERSION_SHIFT    0
36615 #define USBC_UOG2_HCIVERSION_HCIVERSION(x)       (((uint16_t)(((uint16_t)(x))<<USBC_UOG2_HCIVERSION_HCIVERSION_SHIFT))&USBC_UOG2_HCIVERSION_HCIVERSION_MASK)
36616 /* UOG2_HCSPARAMS Bit Fields */
36617 #define USBC_UOG2_HCSPARAMS_N_PORTS_MASK         0xFu
36618 #define USBC_UOG2_HCSPARAMS_N_PORTS_SHIFT        0
36619 #define USBC_UOG2_HCSPARAMS_N_PORTS(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PORTS_SHIFT))&USBC_UOG2_HCSPARAMS_N_PORTS_MASK)
36620 #define USBC_UOG2_HCSPARAMS_PPC_MASK             0x10u
36621 #define USBC_UOG2_HCSPARAMS_PPC_SHIFT            4
36622 #define USBC_UOG2_HCSPARAMS_N_PCC_MASK           0xF00u
36623 #define USBC_UOG2_HCSPARAMS_N_PCC_SHIFT          8
36624 #define USBC_UOG2_HCSPARAMS_N_PCC(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PCC_SHIFT))&USBC_UOG2_HCSPARAMS_N_PCC_MASK)
36625 #define USBC_UOG2_HCSPARAMS_N_CC_MASK            0xF000u
36626 #define USBC_UOG2_HCSPARAMS_N_CC_SHIFT           12
36627 #define USBC_UOG2_HCSPARAMS_N_CC(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_CC_SHIFT))&USBC_UOG2_HCSPARAMS_N_CC_MASK)
36628 #define USBC_UOG2_HCSPARAMS_PI_MASK              0x10000u
36629 #define USBC_UOG2_HCSPARAMS_PI_SHIFT             16
36630 #define USBC_UOG2_HCSPARAMS_N_PTT_MASK           0xF00000u
36631 #define USBC_UOG2_HCSPARAMS_N_PTT_SHIFT          20
36632 #define USBC_UOG2_HCSPARAMS_N_PTT(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PTT_SHIFT))&USBC_UOG2_HCSPARAMS_N_PTT_MASK)
36633 #define USBC_UOG2_HCSPARAMS_N_TT_MASK            0xF000000u
36634 #define USBC_UOG2_HCSPARAMS_N_TT_SHIFT           24
36635 #define USBC_UOG2_HCSPARAMS_N_TT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_TT_SHIFT))&USBC_UOG2_HCSPARAMS_N_TT_MASK)
36636 /* UOG2_HCCPARAMS Bit Fields */
36637 #define USBC_UOG2_HCCPARAMS_ADC_MASK             0x1u
36638 #define USBC_UOG2_HCCPARAMS_ADC_SHIFT            0
36639 #define USBC_UOG2_HCCPARAMS_PFL_MASK             0x2u
36640 #define USBC_UOG2_HCCPARAMS_PFL_SHIFT            1
36641 #define USBC_UOG2_HCCPARAMS_ASP_MASK             0x4u
36642 #define USBC_UOG2_HCCPARAMS_ASP_SHIFT            2
36643 #define USBC_UOG2_HCCPARAMS_IST_MASK             0xF0u
36644 #define USBC_UOG2_HCCPARAMS_IST_SHIFT            4
36645 #define USBC_UOG2_HCCPARAMS_IST(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCCPARAMS_IST_SHIFT))&USBC_UOG2_HCCPARAMS_IST_MASK)
36646 #define USBC_UOG2_HCCPARAMS_EECP_MASK            0xFF00u
36647 #define USBC_UOG2_HCCPARAMS_EECP_SHIFT           8
36648 #define USBC_UOG2_HCCPARAMS_EECP(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCCPARAMS_EECP_SHIFT))&USBC_UOG2_HCCPARAMS_EECP_MASK)
36649 /* UOG2_DCIVERSION Bit Fields */
36650 #define USBC_UOG2_DCIVERSION_DCIVERSION_MASK     0xFFFFu
36651 #define USBC_UOG2_DCIVERSION_DCIVERSION_SHIFT    0
36652 #define USBC_UOG2_DCIVERSION_DCIVERSION(x)       (((uint16_t)(((uint16_t)(x))<<USBC_UOG2_DCIVERSION_DCIVERSION_SHIFT))&USBC_UOG2_DCIVERSION_DCIVERSION_MASK)
36653 /* UOG2_DCCPARAMS Bit Fields */
36654 #define USBC_UOG2_DCCPARAMS_DEN_MASK             0x1Fu
36655 #define USBC_UOG2_DCCPARAMS_DEN_SHIFT            0
36656 #define USBC_UOG2_DCCPARAMS_DEN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_DCCPARAMS_DEN_SHIFT))&USBC_UOG2_DCCPARAMS_DEN_MASK)
36657 #define USBC_UOG2_DCCPARAMS_DC_MASK              0x80u
36658 #define USBC_UOG2_DCCPARAMS_DC_SHIFT             7
36659 #define USBC_UOG2_DCCPARAMS_HC_MASK              0x100u
36660 #define USBC_UOG2_DCCPARAMS_HC_SHIFT             8
36661 /* UOG2_USBCMD Bit Fields */
36662 #define USBC_UOG2_USBCMD_RS_MASK                 0x1u
36663 #define USBC_UOG2_USBCMD_RS_SHIFT                0
36664 #define USBC_UOG2_USBCMD_RST_MASK                0x2u
36665 #define USBC_UOG2_USBCMD_RST_SHIFT               1
36666 #define USBC_UOG2_USBCMD_FS_1_MASK               0xCu
36667 #define USBC_UOG2_USBCMD_FS_1_SHIFT              2
36668 #define USBC_UOG2_USBCMD_FS_1(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_FS_1_SHIFT))&USBC_UOG2_USBCMD_FS_1_MASK)
36669 #define USBC_UOG2_USBCMD_PSE_MASK                0x10u
36670 #define USBC_UOG2_USBCMD_PSE_SHIFT               4
36671 #define USBC_UOG2_USBCMD_ASE_MASK                0x20u
36672 #define USBC_UOG2_USBCMD_ASE_SHIFT               5
36673 #define USBC_UOG2_USBCMD_IAA_MASK                0x40u
36674 #define USBC_UOG2_USBCMD_IAA_SHIFT               6
36675 #define USBC_UOG2_USBCMD_ASP_MASK                0x300u
36676 #define USBC_UOG2_USBCMD_ASP_SHIFT               8
36677 #define USBC_UOG2_USBCMD_ASP(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_ASP_SHIFT))&USBC_UOG2_USBCMD_ASP_MASK)
36678 #define USBC_UOG2_USBCMD_ASPE_MASK               0x800u
36679 #define USBC_UOG2_USBCMD_ASPE_SHIFT              11
36680 #define USBC_UOG2_USBCMD_SUTW_MASK               0x2000u
36681 #define USBC_UOG2_USBCMD_SUTW_SHIFT              13
36682 #define USBC_UOG2_USBCMD_ATDTW_MASK              0x4000u
36683 #define USBC_UOG2_USBCMD_ATDTW_SHIFT             14
36684 #define USBC_UOG2_USBCMD_FS_2_MASK               0x8000u
36685 #define USBC_UOG2_USBCMD_FS_2_SHIFT              15
36686 #define USBC_UOG2_USBCMD_ITC_MASK                0xFF0000u
36687 #define USBC_UOG2_USBCMD_ITC_SHIFT               16
36688 #define USBC_UOG2_USBCMD_ITC(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_ITC_SHIFT))&USBC_UOG2_USBCMD_ITC_MASK)
36689 /* UOG2_USBSTS Bit Fields */
36690 #define USBC_UOG2_USBSTS_UI_MASK                 0x1u
36691 #define USBC_UOG2_USBSTS_UI_SHIFT                0
36692 #define USBC_UOG2_USBSTS_UEI_MASK                0x2u
36693 #define USBC_UOG2_USBSTS_UEI_SHIFT               1
36694 #define USBC_UOG2_USBSTS_PCI_MASK                0x4u
36695 #define USBC_UOG2_USBSTS_PCI_SHIFT               2
36696 #define USBC_UOG2_USBSTS_FRI_MASK                0x8u
36697 #define USBC_UOG2_USBSTS_FRI_SHIFT               3
36698 #define USBC_UOG2_USBSTS_SEI_MASK                0x10u
36699 #define USBC_UOG2_USBSTS_SEI_SHIFT               4
36700 #define USBC_UOG2_USBSTS_AAI_MASK                0x20u
36701 #define USBC_UOG2_USBSTS_AAI_SHIFT               5
36702 #define USBC_UOG2_USBSTS_URI_MASK                0x40u
36703 #define USBC_UOG2_USBSTS_URI_SHIFT               6
36704 #define USBC_UOG2_USBSTS_SRI_MASK                0x80u
36705 #define USBC_UOG2_USBSTS_SRI_SHIFT               7
36706 #define USBC_UOG2_USBSTS_SLI_MASK                0x100u
36707 #define USBC_UOG2_USBSTS_SLI_SHIFT               8
36708 #define USBC_UOG2_USBSTS_ULPII_MASK              0x400u
36709 #define USBC_UOG2_USBSTS_ULPII_SHIFT             10
36710 #define USBC_UOG2_USBSTS_HCH_MASK                0x1000u
36711 #define USBC_UOG2_USBSTS_HCH_SHIFT               12
36712 #define USBC_UOG2_USBSTS_RCL_MASK                0x2000u
36713 #define USBC_UOG2_USBSTS_RCL_SHIFT               13
36714 #define USBC_UOG2_USBSTS_PS_MASK                 0x4000u
36715 #define USBC_UOG2_USBSTS_PS_SHIFT                14
36716 #define USBC_UOG2_USBSTS_AS_MASK                 0x8000u
36717 #define USBC_UOG2_USBSTS_AS_SHIFT                15
36718 #define USBC_UOG2_USBSTS_NAKI_MASK               0x10000u
36719 #define USBC_UOG2_USBSTS_NAKI_SHIFT              16
36720 #define USBC_UOG2_USBSTS_TI0_MASK                0x1000000u
36721 #define USBC_UOG2_USBSTS_TI0_SHIFT               24
36722 #define USBC_UOG2_USBSTS_TI1_MASK                0x2000000u
36723 #define USBC_UOG2_USBSTS_TI1_SHIFT               25
36724 /* UOG2_USBINTR Bit Fields */
36725 #define USBC_UOG2_USBINTR_UE_MASK                0x1u
36726 #define USBC_UOG2_USBINTR_UE_SHIFT               0
36727 #define USBC_UOG2_USBINTR_UEE_MASK               0x2u
36728 #define USBC_UOG2_USBINTR_UEE_SHIFT              1
36729 #define USBC_UOG2_USBINTR_PCE_MASK               0x4u
36730 #define USBC_UOG2_USBINTR_PCE_SHIFT              2
36731 #define USBC_UOG2_USBINTR_FRE_MASK               0x8u
36732 #define USBC_UOG2_USBINTR_FRE_SHIFT              3
36733 #define USBC_UOG2_USBINTR_SEE_MASK               0x10u
36734 #define USBC_UOG2_USBINTR_SEE_SHIFT              4
36735 #define USBC_UOG2_USBINTR_AAE_MASK               0x20u
36736 #define USBC_UOG2_USBINTR_AAE_SHIFT              5
36737 #define USBC_UOG2_USBINTR_URE_MASK               0x40u
36738 #define USBC_UOG2_USBINTR_URE_SHIFT              6
36739 #define USBC_UOG2_USBINTR_SRE_MASK               0x80u
36740 #define USBC_UOG2_USBINTR_SRE_SHIFT              7
36741 #define USBC_UOG2_USBINTR_SLE_MASK               0x100u
36742 #define USBC_UOG2_USBINTR_SLE_SHIFT              8
36743 #define USBC_UOG2_USBINTR_ULPIE_MASK             0x400u
36744 #define USBC_UOG2_USBINTR_ULPIE_SHIFT            10
36745 #define USBC_UOG2_USBINTR_NAKE_MASK              0x10000u
36746 #define USBC_UOG2_USBINTR_NAKE_SHIFT             16
36747 #define USBC_UOG2_USBINTR_UAIE_MASK              0x40000u
36748 #define USBC_UOG2_USBINTR_UAIE_SHIFT             18
36749 #define USBC_UOG2_USBINTR_UPIE_MASK              0x80000u
36750 #define USBC_UOG2_USBINTR_UPIE_SHIFT             19
36751 #define USBC_UOG2_USBINTR_TIE0_MASK              0x1000000u
36752 #define USBC_UOG2_USBINTR_TIE0_SHIFT             24
36753 #define USBC_UOG2_USBINTR_TIE1_MASK              0x2000000u
36754 #define USBC_UOG2_USBINTR_TIE1_SHIFT             25
36755 /* UOG2_FRINDEX Bit Fields */
36756 #define USBC_UOG2_FRINDEX_FRINDEX_MASK           0x3FFFu
36757 #define USBC_UOG2_FRINDEX_FRINDEX_SHIFT          0
36758 #define USBC_UOG2_FRINDEX_FRINDEX(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_FRINDEX_FRINDEX_SHIFT))&USBC_UOG2_FRINDEX_FRINDEX_MASK)
36759 /* UOG2_PERIODICLISTBASE Bit Fields */
36760 #define USBC_UOG2_PERIODICLISTBASE_BASEADR_MASK  0xFFFFF000u
36761 #define USBC_UOG2_PERIODICLISTBASE_BASEADR_SHIFT 12
36762 #define USBC_UOG2_PERIODICLISTBASE_BASEADR(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UOG2_PERIODICLISTBASE_BASEADR_MASK)
36763 /* UOG2_DEVICEADDR Bit Fields */
36764 #define USBC_UOG2_DEVICEADDR_USBADRA_MASK        0x1000000u
36765 #define USBC_UOG2_DEVICEADDR_USBADRA_SHIFT       24
36766 #define USBC_UOG2_DEVICEADDR_USBADR_MASK         0xFE000000u
36767 #define USBC_UOG2_DEVICEADDR_USBADR_SHIFT        25
36768 #define USBC_UOG2_DEVICEADDR_USBADR(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_DEVICEADDR_USBADR_SHIFT))&USBC_UOG2_DEVICEADDR_USBADR_MASK)
36769 /* UOG2_ASYNCLISTADDR Bit Fields */
36770 #define USBC_UOG2_ASYNCLISTADDR_ASYBASE_MASK     0xFFFFFFE0u
36771 #define USBC_UOG2_ASYNCLISTADDR_ASYBASE_SHIFT    5
36772 #define USBC_UOG2_ASYNCLISTADDR_ASYBASE(x)       (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UOG2_ASYNCLISTADDR_ASYBASE_MASK)
36773 /* UOG2_ENDPTLISTADDR Bit Fields */
36774 #define USBC_UOG2_ENDPTLISTADDR_EPBASE_MASK      0xFFFFF800u
36775 #define USBC_UOG2_ENDPTLISTADDR_EPBASE_SHIFT     11
36776 #define USBC_UOG2_ENDPTLISTADDR_EPBASE(x)        (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTLISTADDR_EPBASE_SHIFT))&USBC_UOG2_ENDPTLISTADDR_EPBASE_MASK)
36777 /* UOG2_BURSTSIZE Bit Fields */
36778 #define USBC_UOG2_BURSTSIZE_RXPBURST_MASK        0xFFu
36779 #define USBC_UOG2_BURSTSIZE_RXPBURST_SHIFT       0
36780 #define USBC_UOG2_BURSTSIZE_RXPBURST(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_BURSTSIZE_RXPBURST_SHIFT))&USBC_UOG2_BURSTSIZE_RXPBURST_MASK)
36781 #define USBC_UOG2_BURSTSIZE_TXPBURST_MASK        0x1FF00u
36782 #define USBC_UOG2_BURSTSIZE_TXPBURST_SHIFT       8
36783 #define USBC_UOG2_BURSTSIZE_TXPBURST(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_BURSTSIZE_TXPBURST_SHIFT))&USBC_UOG2_BURSTSIZE_TXPBURST_MASK)
36784 /* UOG2_TXFILLTUNING Bit Fields */
36785 #define USBC_UOG2_TXFILLTUNING_TXSCHOH_MASK      0xFFu
36786 #define USBC_UOG2_TXFILLTUNING_TXSCHOH_SHIFT     0
36787 #define USBC_UOG2_TXFILLTUNING_TXSCHOH(x)        (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UOG2_TXFILLTUNING_TXSCHOH_MASK)
36788 #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_MASK  0x1F00u
36789 #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_SHIFT 8
36790 #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_MASK)
36791 #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_MASK  0x3F0000u
36792 #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_SHIFT 16
36793 #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES(x)    (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_MASK)
36794 /* UOG2_ENDPTNAK Bit Fields */
36795 #define USBC_UOG2_ENDPTNAK_EPRN_MASK             0xFFu
36796 #define USBC_UOG2_ENDPTNAK_EPRN_SHIFT            0
36797 #define USBC_UOG2_ENDPTNAK_EPRN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAK_EPRN_SHIFT))&USBC_UOG2_ENDPTNAK_EPRN_MASK)
36798 #define USBC_UOG2_ENDPTNAK_EPTN_MASK             0xFF0000u
36799 #define USBC_UOG2_ENDPTNAK_EPTN_SHIFT            16
36800 #define USBC_UOG2_ENDPTNAK_EPTN(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAK_EPTN_SHIFT))&USBC_UOG2_ENDPTNAK_EPTN_MASK)
36801 /* UOG2_ENDPTNAKEN Bit Fields */
36802 #define USBC_UOG2_ENDPTNAKEN_EPRNE_MASK          0xFFu
36803 #define USBC_UOG2_ENDPTNAKEN_EPRNE_SHIFT         0
36804 #define USBC_UOG2_ENDPTNAKEN_EPRNE(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAKEN_EPRNE_SHIFT))&USBC_UOG2_ENDPTNAKEN_EPRNE_MASK)
36805 #define USBC_UOG2_ENDPTNAKEN_EPTNE_MASK          0xFF0000u
36806 #define USBC_UOG2_ENDPTNAKEN_EPTNE_SHIFT         16
36807 #define USBC_UOG2_ENDPTNAKEN_EPTNE(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAKEN_EPTNE_SHIFT))&USBC_UOG2_ENDPTNAKEN_EPTNE_MASK)
36808 /* UOG2_CONFIGFLAG Bit Fields */
36809 #define USBC_UOG2_CONFIGFLAG_CF_MASK             0x1u
36810 #define USBC_UOG2_CONFIGFLAG_CF_SHIFT            0
36811 /* UOG2_PORTSC1 Bit Fields */
36812 #define USBC_UOG2_PORTSC1_CCS_MASK               0x1u
36813 #define USBC_UOG2_PORTSC1_CCS_SHIFT              0
36814 #define USBC_UOG2_PORTSC1_CSC_MASK               0x2u
36815 #define USBC_UOG2_PORTSC1_CSC_SHIFT              1
36816 #define USBC_UOG2_PORTSC1_PE_MASK                0x4u
36817 #define USBC_UOG2_PORTSC1_PE_SHIFT               2
36818 #define USBC_UOG2_PORTSC1_PEC_MASK               0x8u
36819 #define USBC_UOG2_PORTSC1_PEC_SHIFT              3
36820 #define USBC_UOG2_PORTSC1_OCA_MASK               0x10u
36821 #define USBC_UOG2_PORTSC1_OCA_SHIFT              4
36822 #define USBC_UOG2_PORTSC1_OCC_MASK               0x20u
36823 #define USBC_UOG2_PORTSC1_OCC_SHIFT              5
36824 #define USBC_UOG2_PORTSC1_FPR_MASK               0x40u
36825 #define USBC_UOG2_PORTSC1_FPR_SHIFT              6
36826 #define USBC_UOG2_PORTSC1_SUSP_MASK              0x80u
36827 #define USBC_UOG2_PORTSC1_SUSP_SHIFT             7
36828 #define USBC_UOG2_PORTSC1_PR_MASK                0x100u
36829 #define USBC_UOG2_PORTSC1_PR_SHIFT               8
36830 #define USBC_UOG2_PORTSC1_HSP_MASK               0x200u
36831 #define USBC_UOG2_PORTSC1_HSP_SHIFT              9
36832 #define USBC_UOG2_PORTSC1_LS_MASK                0xC00u
36833 #define USBC_UOG2_PORTSC1_LS_SHIFT               10
36834 #define USBC_UOG2_PORTSC1_LS(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_LS_SHIFT))&USBC_UOG2_PORTSC1_LS_MASK)
36835 #define USBC_UOG2_PORTSC1_PP_MASK                0x1000u
36836 #define USBC_UOG2_PORTSC1_PP_SHIFT               12
36837 #define USBC_UOG2_PORTSC1_PO_MASK                0x2000u
36838 #define USBC_UOG2_PORTSC1_PO_SHIFT               13
36839 #define USBC_UOG2_PORTSC1_PIC_MASK               0xC000u
36840 #define USBC_UOG2_PORTSC1_PIC_SHIFT              14
36841 #define USBC_UOG2_PORTSC1_PIC(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PIC_SHIFT))&USBC_UOG2_PORTSC1_PIC_MASK)
36842 #define USBC_UOG2_PORTSC1_PTC_MASK               0xF0000u
36843 #define USBC_UOG2_PORTSC1_PTC_SHIFT              16
36844 #define USBC_UOG2_PORTSC1_PTC(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PTC_SHIFT))&USBC_UOG2_PORTSC1_PTC_MASK)
36845 #define USBC_UOG2_PORTSC1_WKCN_MASK              0x100000u
36846 #define USBC_UOG2_PORTSC1_WKCN_SHIFT             20
36847 #define USBC_UOG2_PORTSC1_WKDC_MASK              0x200000u
36848 #define USBC_UOG2_PORTSC1_WKDC_SHIFT             21
36849 #define USBC_UOG2_PORTSC1_WKOC_MASK              0x400000u
36850 #define USBC_UOG2_PORTSC1_WKOC_SHIFT             22
36851 #define USBC_UOG2_PORTSC1_PHCD_MASK              0x800000u
36852 #define USBC_UOG2_PORTSC1_PHCD_SHIFT             23
36853 #define USBC_UOG2_PORTSC1_PFSC_MASK              0x1000000u
36854 #define USBC_UOG2_PORTSC1_PFSC_SHIFT             24
36855 #define USBC_UOG2_PORTSC1_PTS_2_MASK             0x2000000u
36856 #define USBC_UOG2_PORTSC1_PTS_2_SHIFT            25
36857 #define USBC_UOG2_PORTSC1_PSPD_MASK              0xC000000u
36858 #define USBC_UOG2_PORTSC1_PSPD_SHIFT             26
36859 #define USBC_UOG2_PORTSC1_PSPD(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PSPD_SHIFT))&USBC_UOG2_PORTSC1_PSPD_MASK)
36860 #define USBC_UOG2_PORTSC1_PTW_MASK               0x10000000u
36861 #define USBC_UOG2_PORTSC1_PTW_SHIFT              28
36862 #define USBC_UOG2_PORTSC1_STS_MASK               0x20000000u
36863 #define USBC_UOG2_PORTSC1_STS_SHIFT              29
36864 #define USBC_UOG2_PORTSC1_PTS_1_MASK             0xC0000000u
36865 #define USBC_UOG2_PORTSC1_PTS_1_SHIFT            30
36866 #define USBC_UOG2_PORTSC1_PTS_1(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PTS_1_SHIFT))&USBC_UOG2_PORTSC1_PTS_1_MASK)
36867 /* UOG2_OTGSC Bit Fields */
36868 #define USBC_UOG2_OTGSC_VD_MASK                  0x1u
36869 #define USBC_UOG2_OTGSC_VD_SHIFT                 0
36870 #define USBC_UOG2_OTGSC_VC_MASK                  0x2u
36871 #define USBC_UOG2_OTGSC_VC_SHIFT                 1
36872 #define USBC_UOG2_OTGSC_OT_MASK                  0x8u
36873 #define USBC_UOG2_OTGSC_OT_SHIFT                 3
36874 #define USBC_UOG2_OTGSC_DP_MASK                  0x10u
36875 #define USBC_UOG2_OTGSC_DP_SHIFT                 4
36876 #define USBC_UOG2_OTGSC_IDPU_MASK                0x20u
36877 #define USBC_UOG2_OTGSC_IDPU_SHIFT               5
36878 #define USBC_UOG2_OTGSC_ID_MASK                  0x100u
36879 #define USBC_UOG2_OTGSC_ID_SHIFT                 8
36880 #define USBC_UOG2_OTGSC_AVV_MASK                 0x200u
36881 #define USBC_UOG2_OTGSC_AVV_SHIFT                9
36882 #define USBC_UOG2_OTGSC_ASV_MASK                 0x400u
36883 #define USBC_UOG2_OTGSC_ASV_SHIFT                10
36884 #define USBC_UOG2_OTGSC_BSV_MASK                 0x800u
36885 #define USBC_UOG2_OTGSC_BSV_SHIFT                11
36886 #define USBC_UOG2_OTGSC_BSE_MASK                 0x1000u
36887 #define USBC_UOG2_OTGSC_BSE_SHIFT                12
36888 #define USBC_UOG2_OTGSC_TOG_1MS_MASK             0x2000u
36889 #define USBC_UOG2_OTGSC_TOG_1MS_SHIFT            13
36890 #define USBC_UOG2_OTGSC_DPS_MASK                 0x4000u
36891 #define USBC_UOG2_OTGSC_DPS_SHIFT                14
36892 #define USBC_UOG2_OTGSC_IDIS_MASK                0x10000u
36893 #define USBC_UOG2_OTGSC_IDIS_SHIFT               16
36894 #define USBC_UOG2_OTGSC_AVVIS_MASK               0x20000u
36895 #define USBC_UOG2_OTGSC_AVVIS_SHIFT              17
36896 #define USBC_UOG2_OTGSC_ASVIS_MASK               0x40000u
36897 #define USBC_UOG2_OTGSC_ASVIS_SHIFT              18
36898 #define USBC_UOG2_OTGSC_BSVIS_MASK               0x80000u
36899 #define USBC_UOG2_OTGSC_BSVIS_SHIFT              19
36900 #define USBC_UOG2_OTGSC_BSEIS_MASK               0x100000u
36901 #define USBC_UOG2_OTGSC_BSEIS_SHIFT              20
36902 #define USBC_UOG2_OTGSC_STATUS_1MS_MASK          0x200000u
36903 #define USBC_UOG2_OTGSC_STATUS_1MS_SHIFT         21
36904 #define USBC_UOG2_OTGSC_DPIS_MASK                0x400000u
36905 #define USBC_UOG2_OTGSC_DPIS_SHIFT               22
36906 #define USBC_UOG2_OTGSC_IDIE_MASK                0x1000000u
36907 #define USBC_UOG2_OTGSC_IDIE_SHIFT               24
36908 #define USBC_UOG2_OTGSC_AVVIE_MASK               0x2000000u
36909 #define USBC_UOG2_OTGSC_AVVIE_SHIFT              25
36910 #define USBC_UOG2_OTGSC_ASVIE_MASK               0x4000000u
36911 #define USBC_UOG2_OTGSC_ASVIE_SHIFT              26
36912 #define USBC_UOG2_OTGSC_BSVIE_MASK               0x8000000u
36913 #define USBC_UOG2_OTGSC_BSVIE_SHIFT              27
36914 #define USBC_UOG2_OTGSC_BSEIE_MASK               0x10000000u
36915 #define USBC_UOG2_OTGSC_BSEIE_SHIFT              28
36916 #define USBC_UOG2_OTGSC_EN_1MS_MASK              0x20000000u
36917 #define USBC_UOG2_OTGSC_EN_1MS_SHIFT             29
36918 #define USBC_UOG2_OTGSC_DPIE_MASK                0x40000000u
36919 #define USBC_UOG2_OTGSC_DPIE_SHIFT               30
36920 /* UOG2_USBMODE Bit Fields */
36921 #define USBC_UOG2_USBMODE_CM_MASK                0x3u
36922 #define USBC_UOG2_USBMODE_CM_SHIFT               0
36923 #define USBC_UOG2_USBMODE_CM(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBMODE_CM_SHIFT))&USBC_UOG2_USBMODE_CM_MASK)
36924 #define USBC_UOG2_USBMODE_ES_MASK                0x4u
36925 #define USBC_UOG2_USBMODE_ES_SHIFT               2
36926 #define USBC_UOG2_USBMODE_SLOM_MASK              0x8u
36927 #define USBC_UOG2_USBMODE_SLOM_SHIFT             3
36928 #define USBC_UOG2_USBMODE_SDIS_MASK              0x10u
36929 #define USBC_UOG2_USBMODE_SDIS_SHIFT             4
36930 /* UOG2_ENDPTSETUPSTAT Bit Fields */
36931 #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK 0xFFFFu
36932 #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT 0
36933 #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
36934 /* UOG2_ENDPTPRIME Bit Fields */
36935 #define USBC_UOG2_ENDPTPRIME_PERB_MASK           0xFFu
36936 #define USBC_UOG2_ENDPTPRIME_PERB_SHIFT          0
36937 #define USBC_UOG2_ENDPTPRIME_PERB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTPRIME_PERB_SHIFT))&USBC_UOG2_ENDPTPRIME_PERB_MASK)
36938 #define USBC_UOG2_ENDPTPRIME_PETB_MASK           0xFF0000u
36939 #define USBC_UOG2_ENDPTPRIME_PETB_SHIFT          16
36940 #define USBC_UOG2_ENDPTPRIME_PETB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTPRIME_PETB_SHIFT))&USBC_UOG2_ENDPTPRIME_PETB_MASK)
36941 /* UOG2_ENDPTFLUSH Bit Fields */
36942 #define USBC_UOG2_ENDPTFLUSH_FERB_MASK           0xFFu
36943 #define USBC_UOG2_ENDPTFLUSH_FERB_SHIFT          0
36944 #define USBC_UOG2_ENDPTFLUSH_FERB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTFLUSH_FERB_SHIFT))&USBC_UOG2_ENDPTFLUSH_FERB_MASK)
36945 #define USBC_UOG2_ENDPTFLUSH_FETB_MASK           0xFF0000u
36946 #define USBC_UOG2_ENDPTFLUSH_FETB_SHIFT          16
36947 #define USBC_UOG2_ENDPTFLUSH_FETB(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTFLUSH_FETB_SHIFT))&USBC_UOG2_ENDPTFLUSH_FETB_MASK)
36948 /* UOG2_ENDPTSTAT Bit Fields */
36949 #define USBC_UOG2_ENDPTSTAT_ERBR_MASK            0xFFu
36950 #define USBC_UOG2_ENDPTSTAT_ERBR_SHIFT           0
36951 #define USBC_UOG2_ENDPTSTAT_ERBR(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSTAT_ERBR_SHIFT))&USBC_UOG2_ENDPTSTAT_ERBR_MASK)
36952 #define USBC_UOG2_ENDPTSTAT_ETBR_MASK            0xFF0000u
36953 #define USBC_UOG2_ENDPTSTAT_ETBR_SHIFT           16
36954 #define USBC_UOG2_ENDPTSTAT_ETBR(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSTAT_ETBR_SHIFT))&USBC_UOG2_ENDPTSTAT_ETBR_MASK)
36955 /* UOG2_ENDPTCOMPLETE Bit Fields */
36956 #define USBC_UOG2_ENDPTCOMPLETE_ERCE_MASK        0xFFu
36957 #define USBC_UOG2_ENDPTCOMPLETE_ERCE_SHIFT       0
36958 #define USBC_UOG2_ENDPTCOMPLETE_ERCE(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCOMPLETE_ERCE_SHIFT))&USBC_UOG2_ENDPTCOMPLETE_ERCE_MASK)
36959 #define USBC_UOG2_ENDPTCOMPLETE_ETCE_MASK        0xFF0000u
36960 #define USBC_UOG2_ENDPTCOMPLETE_ETCE_SHIFT       16
36961 #define USBC_UOG2_ENDPTCOMPLETE_ETCE(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCOMPLETE_ETCE_SHIFT))&USBC_UOG2_ENDPTCOMPLETE_ETCE_MASK)
36962 /* UOG2_ENDPTCTRL0 Bit Fields */
36963 #define USBC_UOG2_ENDPTCTRL0_RXS_MASK            0x1u
36964 #define USBC_UOG2_ENDPTCTRL0_RXS_SHIFT           0
36965 #define USBC_UOG2_ENDPTCTRL0_RXT_MASK            0xCu
36966 #define USBC_UOG2_ENDPTCTRL0_RXT_SHIFT           2
36967 #define USBC_UOG2_ENDPTCTRL0_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL0_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL0_RXT_MASK)
36968 #define USBC_UOG2_ENDPTCTRL0_RXE_MASK            0x80u
36969 #define USBC_UOG2_ENDPTCTRL0_RXE_SHIFT           7
36970 #define USBC_UOG2_ENDPTCTRL0_TXS_MASK            0x10000u
36971 #define USBC_UOG2_ENDPTCTRL0_TXS_SHIFT           16
36972 #define USBC_UOG2_ENDPTCTRL0_TXT_MASK            0xC0000u
36973 #define USBC_UOG2_ENDPTCTRL0_TXT_SHIFT           18
36974 #define USBC_UOG2_ENDPTCTRL0_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL0_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL0_TXT_MASK)
36975 #define USBC_UOG2_ENDPTCTRL0_TXE_MASK            0x800000u
36976 #define USBC_UOG2_ENDPTCTRL0_TXE_SHIFT           23
36977 /* UOG2_ENDPTCTRL1 Bit Fields */
36978 #define USBC_UOG2_ENDPTCTRL1_RXS_MASK            0x1u
36979 #define USBC_UOG2_ENDPTCTRL1_RXS_SHIFT           0
36980 #define USBC_UOG2_ENDPTCTRL1_RXD_MASK            0x2u
36981 #define USBC_UOG2_ENDPTCTRL1_RXD_SHIFT           1
36982 #define USBC_UOG2_ENDPTCTRL1_RXT_MASK            0xCu
36983 #define USBC_UOG2_ENDPTCTRL1_RXT_SHIFT           2
36984 #define USBC_UOG2_ENDPTCTRL1_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL1_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL1_RXT_MASK)
36985 #define USBC_UOG2_ENDPTCTRL1_RXI_MASK            0x20u
36986 #define USBC_UOG2_ENDPTCTRL1_RXI_SHIFT           5
36987 #define USBC_UOG2_ENDPTCTRL1_RXR_MASK            0x40u
36988 #define USBC_UOG2_ENDPTCTRL1_RXR_SHIFT           6
36989 #define USBC_UOG2_ENDPTCTRL1_RXE_MASK            0x80u
36990 #define USBC_UOG2_ENDPTCTRL1_RXE_SHIFT           7
36991 #define USBC_UOG2_ENDPTCTRL1_TXS_MASK            0x10000u
36992 #define USBC_UOG2_ENDPTCTRL1_TXS_SHIFT           16
36993 #define USBC_UOG2_ENDPTCTRL1_TXD_MASK            0x20000u
36994 #define USBC_UOG2_ENDPTCTRL1_TXD_SHIFT           17
36995 #define USBC_UOG2_ENDPTCTRL1_TXT_MASK            0xC0000u
36996 #define USBC_UOG2_ENDPTCTRL1_TXT_SHIFT           18
36997 #define USBC_UOG2_ENDPTCTRL1_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL1_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL1_TXT_MASK)
36998 #define USBC_UOG2_ENDPTCTRL1_TXI_MASK            0x200000u
36999 #define USBC_UOG2_ENDPTCTRL1_TXI_SHIFT           21
37000 #define USBC_UOG2_ENDPTCTRL1_TXR_MASK            0x400000u
37001 #define USBC_UOG2_ENDPTCTRL1_TXR_SHIFT           22
37002 #define USBC_UOG2_ENDPTCTRL1_TXE_MASK            0x800000u
37003 #define USBC_UOG2_ENDPTCTRL1_TXE_SHIFT           23
37004 /* UOG2_ENDPTCTRL2 Bit Fields */
37005 #define USBC_UOG2_ENDPTCTRL2_RXS_MASK            0x1u
37006 #define USBC_UOG2_ENDPTCTRL2_RXS_SHIFT           0
37007 #define USBC_UOG2_ENDPTCTRL2_RXD_MASK            0x2u
37008 #define USBC_UOG2_ENDPTCTRL2_RXD_SHIFT           1
37009 #define USBC_UOG2_ENDPTCTRL2_RXT_MASK            0xCu
37010 #define USBC_UOG2_ENDPTCTRL2_RXT_SHIFT           2
37011 #define USBC_UOG2_ENDPTCTRL2_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL2_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL2_RXT_MASK)
37012 #define USBC_UOG2_ENDPTCTRL2_RXI_MASK            0x20u
37013 #define USBC_UOG2_ENDPTCTRL2_RXI_SHIFT           5
37014 #define USBC_UOG2_ENDPTCTRL2_RXR_MASK            0x40u
37015 #define USBC_UOG2_ENDPTCTRL2_RXR_SHIFT           6
37016 #define USBC_UOG2_ENDPTCTRL2_RXE_MASK            0x80u
37017 #define USBC_UOG2_ENDPTCTRL2_RXE_SHIFT           7
37018 #define USBC_UOG2_ENDPTCTRL2_TXS_MASK            0x10000u
37019 #define USBC_UOG2_ENDPTCTRL2_TXS_SHIFT           16
37020 #define USBC_UOG2_ENDPTCTRL2_TXD_MASK            0x20000u
37021 #define USBC_UOG2_ENDPTCTRL2_TXD_SHIFT           17
37022 #define USBC_UOG2_ENDPTCTRL2_TXT_MASK            0xC0000u
37023 #define USBC_UOG2_ENDPTCTRL2_TXT_SHIFT           18
37024 #define USBC_UOG2_ENDPTCTRL2_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL2_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL2_TXT_MASK)
37025 #define USBC_UOG2_ENDPTCTRL2_TXI_MASK            0x200000u
37026 #define USBC_UOG2_ENDPTCTRL2_TXI_SHIFT           21
37027 #define USBC_UOG2_ENDPTCTRL2_TXR_MASK            0x400000u
37028 #define USBC_UOG2_ENDPTCTRL2_TXR_SHIFT           22
37029 #define USBC_UOG2_ENDPTCTRL2_TXE_MASK            0x800000u
37030 #define USBC_UOG2_ENDPTCTRL2_TXE_SHIFT           23
37031 /* UOG2_ENDPTCTRL3 Bit Fields */
37032 #define USBC_UOG2_ENDPTCTRL3_RXS_MASK            0x1u
37033 #define USBC_UOG2_ENDPTCTRL3_RXS_SHIFT           0
37034 #define USBC_UOG2_ENDPTCTRL3_RXD_MASK            0x2u
37035 #define USBC_UOG2_ENDPTCTRL3_RXD_SHIFT           1
37036 #define USBC_UOG2_ENDPTCTRL3_RXT_MASK            0xCu
37037 #define USBC_UOG2_ENDPTCTRL3_RXT_SHIFT           2
37038 #define USBC_UOG2_ENDPTCTRL3_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL3_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL3_RXT_MASK)
37039 #define USBC_UOG2_ENDPTCTRL3_RXI_MASK            0x20u
37040 #define USBC_UOG2_ENDPTCTRL3_RXI_SHIFT           5
37041 #define USBC_UOG2_ENDPTCTRL3_RXR_MASK            0x40u
37042 #define USBC_UOG2_ENDPTCTRL3_RXR_SHIFT           6
37043 #define USBC_UOG2_ENDPTCTRL3_RXE_MASK            0x80u
37044 #define USBC_UOG2_ENDPTCTRL3_RXE_SHIFT           7
37045 #define USBC_UOG2_ENDPTCTRL3_TXS_MASK            0x10000u
37046 #define USBC_UOG2_ENDPTCTRL3_TXS_SHIFT           16
37047 #define USBC_UOG2_ENDPTCTRL3_TXD_MASK            0x20000u
37048 #define USBC_UOG2_ENDPTCTRL3_TXD_SHIFT           17
37049 #define USBC_UOG2_ENDPTCTRL3_TXT_MASK            0xC0000u
37050 #define USBC_UOG2_ENDPTCTRL3_TXT_SHIFT           18
37051 #define USBC_UOG2_ENDPTCTRL3_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL3_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL3_TXT_MASK)
37052 #define USBC_UOG2_ENDPTCTRL3_TXI_MASK            0x200000u
37053 #define USBC_UOG2_ENDPTCTRL3_TXI_SHIFT           21
37054 #define USBC_UOG2_ENDPTCTRL3_TXR_MASK            0x400000u
37055 #define USBC_UOG2_ENDPTCTRL3_TXR_SHIFT           22
37056 #define USBC_UOG2_ENDPTCTRL3_TXE_MASK            0x800000u
37057 #define USBC_UOG2_ENDPTCTRL3_TXE_SHIFT           23
37058 /* UOG2_ENDPTCTRL4 Bit Fields */
37059 #define USBC_UOG2_ENDPTCTRL4_RXS_MASK            0x1u
37060 #define USBC_UOG2_ENDPTCTRL4_RXS_SHIFT           0
37061 #define USBC_UOG2_ENDPTCTRL4_RXD_MASK            0x2u
37062 #define USBC_UOG2_ENDPTCTRL4_RXD_SHIFT           1
37063 #define USBC_UOG2_ENDPTCTRL4_RXT_MASK            0xCu
37064 #define USBC_UOG2_ENDPTCTRL4_RXT_SHIFT           2
37065 #define USBC_UOG2_ENDPTCTRL4_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL4_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL4_RXT_MASK)
37066 #define USBC_UOG2_ENDPTCTRL4_RXI_MASK            0x20u
37067 #define USBC_UOG2_ENDPTCTRL4_RXI_SHIFT           5
37068 #define USBC_UOG2_ENDPTCTRL4_RXR_MASK            0x40u
37069 #define USBC_UOG2_ENDPTCTRL4_RXR_SHIFT           6
37070 #define USBC_UOG2_ENDPTCTRL4_RXE_MASK            0x80u
37071 #define USBC_UOG2_ENDPTCTRL4_RXE_SHIFT           7
37072 #define USBC_UOG2_ENDPTCTRL4_TXS_MASK            0x10000u
37073 #define USBC_UOG2_ENDPTCTRL4_TXS_SHIFT           16
37074 #define USBC_UOG2_ENDPTCTRL4_TXD_MASK            0x20000u
37075 #define USBC_UOG2_ENDPTCTRL4_TXD_SHIFT           17
37076 #define USBC_UOG2_ENDPTCTRL4_TXT_MASK            0xC0000u
37077 #define USBC_UOG2_ENDPTCTRL4_TXT_SHIFT           18
37078 #define USBC_UOG2_ENDPTCTRL4_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL4_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL4_TXT_MASK)
37079 #define USBC_UOG2_ENDPTCTRL4_TXI_MASK            0x200000u
37080 #define USBC_UOG2_ENDPTCTRL4_TXI_SHIFT           21
37081 #define USBC_UOG2_ENDPTCTRL4_TXR_MASK            0x400000u
37082 #define USBC_UOG2_ENDPTCTRL4_TXR_SHIFT           22
37083 #define USBC_UOG2_ENDPTCTRL4_TXE_MASK            0x800000u
37084 #define USBC_UOG2_ENDPTCTRL4_TXE_SHIFT           23
37085 /* UOG2_ENDPTCTRL5 Bit Fields */
37086 #define USBC_UOG2_ENDPTCTRL5_RXS_MASK            0x1u
37087 #define USBC_UOG2_ENDPTCTRL5_RXS_SHIFT           0
37088 #define USBC_UOG2_ENDPTCTRL5_RXD_MASK            0x2u
37089 #define USBC_UOG2_ENDPTCTRL5_RXD_SHIFT           1
37090 #define USBC_UOG2_ENDPTCTRL5_RXT_MASK            0xCu
37091 #define USBC_UOG2_ENDPTCTRL5_RXT_SHIFT           2
37092 #define USBC_UOG2_ENDPTCTRL5_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL5_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL5_RXT_MASK)
37093 #define USBC_UOG2_ENDPTCTRL5_RXI_MASK            0x20u
37094 #define USBC_UOG2_ENDPTCTRL5_RXI_SHIFT           5
37095 #define USBC_UOG2_ENDPTCTRL5_RXR_MASK            0x40u
37096 #define USBC_UOG2_ENDPTCTRL5_RXR_SHIFT           6
37097 #define USBC_UOG2_ENDPTCTRL5_RXE_MASK            0x80u
37098 #define USBC_UOG2_ENDPTCTRL5_RXE_SHIFT           7
37099 #define USBC_UOG2_ENDPTCTRL5_TXS_MASK            0x10000u
37100 #define USBC_UOG2_ENDPTCTRL5_TXS_SHIFT           16
37101 #define USBC_UOG2_ENDPTCTRL5_TXD_MASK            0x20000u
37102 #define USBC_UOG2_ENDPTCTRL5_TXD_SHIFT           17
37103 #define USBC_UOG2_ENDPTCTRL5_TXT_MASK            0xC0000u
37104 #define USBC_UOG2_ENDPTCTRL5_TXT_SHIFT           18
37105 #define USBC_UOG2_ENDPTCTRL5_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL5_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL5_TXT_MASK)
37106 #define USBC_UOG2_ENDPTCTRL5_TXI_MASK            0x200000u
37107 #define USBC_UOG2_ENDPTCTRL5_TXI_SHIFT           21
37108 #define USBC_UOG2_ENDPTCTRL5_TXR_MASK            0x400000u
37109 #define USBC_UOG2_ENDPTCTRL5_TXR_SHIFT           22
37110 #define USBC_UOG2_ENDPTCTRL5_TXE_MASK            0x800000u
37111 #define USBC_UOG2_ENDPTCTRL5_TXE_SHIFT           23
37112 /* UOG2_ENDPTCTRL6 Bit Fields */
37113 #define USBC_UOG2_ENDPTCTRL6_RXS_MASK            0x1u
37114 #define USBC_UOG2_ENDPTCTRL6_RXS_SHIFT           0
37115 #define USBC_UOG2_ENDPTCTRL6_RXD_MASK            0x2u
37116 #define USBC_UOG2_ENDPTCTRL6_RXD_SHIFT           1
37117 #define USBC_UOG2_ENDPTCTRL6_RXT_MASK            0xCu
37118 #define USBC_UOG2_ENDPTCTRL6_RXT_SHIFT           2
37119 #define USBC_UOG2_ENDPTCTRL6_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL6_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL6_RXT_MASK)
37120 #define USBC_UOG2_ENDPTCTRL6_RXI_MASK            0x20u
37121 #define USBC_UOG2_ENDPTCTRL6_RXI_SHIFT           5
37122 #define USBC_UOG2_ENDPTCTRL6_RXR_MASK            0x40u
37123 #define USBC_UOG2_ENDPTCTRL6_RXR_SHIFT           6
37124 #define USBC_UOG2_ENDPTCTRL6_RXE_MASK            0x80u
37125 #define USBC_UOG2_ENDPTCTRL6_RXE_SHIFT           7
37126 #define USBC_UOG2_ENDPTCTRL6_TXS_MASK            0x10000u
37127 #define USBC_UOG2_ENDPTCTRL6_TXS_SHIFT           16
37128 #define USBC_UOG2_ENDPTCTRL6_TXD_MASK            0x20000u
37129 #define USBC_UOG2_ENDPTCTRL6_TXD_SHIFT           17
37130 #define USBC_UOG2_ENDPTCTRL6_TXT_MASK            0xC0000u
37131 #define USBC_UOG2_ENDPTCTRL6_TXT_SHIFT           18
37132 #define USBC_UOG2_ENDPTCTRL6_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL6_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL6_TXT_MASK)
37133 #define USBC_UOG2_ENDPTCTRL6_TXI_MASK            0x200000u
37134 #define USBC_UOG2_ENDPTCTRL6_TXI_SHIFT           21
37135 #define USBC_UOG2_ENDPTCTRL6_TXR_MASK            0x400000u
37136 #define USBC_UOG2_ENDPTCTRL6_TXR_SHIFT           22
37137 #define USBC_UOG2_ENDPTCTRL6_TXE_MASK            0x800000u
37138 #define USBC_UOG2_ENDPTCTRL6_TXE_SHIFT           23
37139 /* UOG2_ENDPTCTRL7 Bit Fields */
37140 #define USBC_UOG2_ENDPTCTRL7_RXS_MASK            0x1u
37141 #define USBC_UOG2_ENDPTCTRL7_RXS_SHIFT           0
37142 #define USBC_UOG2_ENDPTCTRL7_RXD_MASK            0x2u
37143 #define USBC_UOG2_ENDPTCTRL7_RXD_SHIFT           1
37144 #define USBC_UOG2_ENDPTCTRL7_RXT_MASK            0xCu
37145 #define USBC_UOG2_ENDPTCTRL7_RXT_SHIFT           2
37146 #define USBC_UOG2_ENDPTCTRL7_RXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL7_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL7_RXT_MASK)
37147 #define USBC_UOG2_ENDPTCTRL7_RXI_MASK            0x20u
37148 #define USBC_UOG2_ENDPTCTRL7_RXI_SHIFT           5
37149 #define USBC_UOG2_ENDPTCTRL7_RXR_MASK            0x40u
37150 #define USBC_UOG2_ENDPTCTRL7_RXR_SHIFT           6
37151 #define USBC_UOG2_ENDPTCTRL7_RXE_MASK            0x80u
37152 #define USBC_UOG2_ENDPTCTRL7_RXE_SHIFT           7
37153 #define USBC_UOG2_ENDPTCTRL7_TXS_MASK            0x10000u
37154 #define USBC_UOG2_ENDPTCTRL7_TXS_SHIFT           16
37155 #define USBC_UOG2_ENDPTCTRL7_TXD_MASK            0x20000u
37156 #define USBC_UOG2_ENDPTCTRL7_TXD_SHIFT           17
37157 #define USBC_UOG2_ENDPTCTRL7_TXT_MASK            0xC0000u
37158 #define USBC_UOG2_ENDPTCTRL7_TXT_SHIFT           18
37159 #define USBC_UOG2_ENDPTCTRL7_TXT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL7_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL7_TXT_MASK)
37160 #define USBC_UOG2_ENDPTCTRL7_TXI_MASK            0x200000u
37161 #define USBC_UOG2_ENDPTCTRL7_TXI_SHIFT           21
37162 #define USBC_UOG2_ENDPTCTRL7_TXR_MASK            0x400000u
37163 #define USBC_UOG2_ENDPTCTRL7_TXR_SHIFT           22
37164 #define USBC_UOG2_ENDPTCTRL7_TXE_MASK            0x800000u
37165 #define USBC_UOG2_ENDPTCTRL7_TXE_SHIFT           23
37166 /* UH1_ID Bit Fields */
37167 #define USBC_UH1_ID_ID_MASK                      0x3Fu
37168 #define USBC_UH1_ID_ID_SHIFT                     0
37169 #define USBC_UH1_ID_ID(x)                        (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_ID_SHIFT))&USBC_UH1_ID_ID_MASK)
37170 #define USBC_UH1_ID_NID_MASK                     0x3F00u
37171 #define USBC_UH1_ID_NID_SHIFT                    8
37172 #define USBC_UH1_ID_NID(x)                       (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_NID_SHIFT))&USBC_UH1_ID_NID_MASK)
37173 #define USBC_UH1_ID_REVISION_MASK                0xFF0000u
37174 #define USBC_UH1_ID_REVISION_SHIFT               16
37175 #define USBC_UH1_ID_REVISION(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_REVISION_SHIFT))&USBC_UH1_ID_REVISION_MASK)
37176 /* UH1_HWGENERAL Bit Fields */
37177 #define USBC_UH1_HWGENERAL_PHYW_MASK             0x30u
37178 #define USBC_UH1_HWGENERAL_PHYW_SHIFT            4
37179 #define USBC_UH1_HWGENERAL_PHYW(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_PHYW_SHIFT))&USBC_UH1_HWGENERAL_PHYW_MASK)
37180 #define USBC_UH1_HWGENERAL_PHYM_MASK             0x1C0u
37181 #define USBC_UH1_HWGENERAL_PHYM_SHIFT            6
37182 #define USBC_UH1_HWGENERAL_PHYM(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_PHYM_SHIFT))&USBC_UH1_HWGENERAL_PHYM_MASK)
37183 #define USBC_UH1_HWGENERAL_SM_MASK               0x600u
37184 #define USBC_UH1_HWGENERAL_SM_SHIFT              9
37185 #define USBC_UH1_HWGENERAL_SM(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_SM_SHIFT))&USBC_UH1_HWGENERAL_SM_MASK)
37186 /* UH1_HWHOST Bit Fields */
37187 #define USBC_UH1_HWHOST_HC_MASK                  0x1u
37188 #define USBC_UH1_HWHOST_HC_SHIFT                 0
37189 #define USBC_UH1_HWHOST_NPORT_MASK               0xEu
37190 #define USBC_UH1_HWHOST_NPORT_SHIFT              1
37191 #define USBC_UH1_HWHOST_NPORT(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWHOST_NPORT_SHIFT))&USBC_UH1_HWHOST_NPORT_MASK)
37192 /* UH1_HWTXBUF Bit Fields */
37193 #define USBC_UH1_HWTXBUF_TXBURST_MASK            0xFFu
37194 #define USBC_UH1_HWTXBUF_TXBURST_SHIFT           0
37195 #define USBC_UH1_HWTXBUF_TXBURST(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWTXBUF_TXBURST_SHIFT))&USBC_UH1_HWTXBUF_TXBURST_MASK)
37196 #define USBC_UH1_HWTXBUF_TXCHANADD_MASK          0xFF0000u
37197 #define USBC_UH1_HWTXBUF_TXCHANADD_SHIFT         16
37198 #define USBC_UH1_HWTXBUF_TXCHANADD(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWTXBUF_TXCHANADD_SHIFT))&USBC_UH1_HWTXBUF_TXCHANADD_MASK)
37199 /* UH1_HWRXBUF Bit Fields */
37200 #define USBC_UH1_HWRXBUF_RXBURST_MASK            0xFFu
37201 #define USBC_UH1_HWRXBUF_RXBURST_SHIFT           0
37202 #define USBC_UH1_HWRXBUF_RXBURST(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWRXBUF_RXBURST_SHIFT))&USBC_UH1_HWRXBUF_RXBURST_MASK)
37203 #define USBC_UH1_HWRXBUF_RXADD_MASK              0xFF00u
37204 #define USBC_UH1_HWRXBUF_RXADD_SHIFT             8
37205 #define USBC_UH1_HWRXBUF_RXADD(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWRXBUF_RXADD_SHIFT))&USBC_UH1_HWRXBUF_RXADD_MASK)
37206 /* UH1_GPTIMER0LD Bit Fields */
37207 #define USBC_UH1_GPTIMER0LD_GPTLD_MASK           0xFFFFFFu
37208 #define USBC_UH1_GPTIMER0LD_GPTLD_SHIFT          0
37209 #define USBC_UH1_GPTIMER0LD_GPTLD(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER0LD_GPTLD_SHIFT))&USBC_UH1_GPTIMER0LD_GPTLD_MASK)
37210 /* UH1_GPTIMER0CTRL Bit Fields */
37211 #define USBC_UH1_GPTIMER0CTRL_GPTCNT_MASK        0xFFFFFFu
37212 #define USBC_UH1_GPTIMER0CTRL_GPTCNT_SHIFT       0
37213 #define USBC_UH1_GPTIMER0CTRL_GPTCNT(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UH1_GPTIMER0CTRL_GPTCNT_MASK)
37214 #define USBC_UH1_GPTIMER0CTRL_GPTMODE_MASK       0x1000000u
37215 #define USBC_UH1_GPTIMER0CTRL_GPTMODE_SHIFT      24
37216 #define USBC_UH1_GPTIMER0CTRL_GPTRST_MASK        0x40000000u
37217 #define USBC_UH1_GPTIMER0CTRL_GPTRST_SHIFT       30
37218 #define USBC_UH1_GPTIMER0CTRL_GPTRUN_MASK        0x80000000u
37219 #define USBC_UH1_GPTIMER0CTRL_GPTRUN_SHIFT       31
37220 /* UH1_GPTIMER1LD Bit Fields */
37221 #define USBC_UH1_GPTIMER1LD_GPTLD_MASK           0xFFFFFFu
37222 #define USBC_UH1_GPTIMER1LD_GPTLD_SHIFT          0
37223 #define USBC_UH1_GPTIMER1LD_GPTLD(x)             (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER1LD_GPTLD_SHIFT))&USBC_UH1_GPTIMER1LD_GPTLD_MASK)
37224 /* UH1_GPTIMER1CTRL Bit Fields */
37225 #define USBC_UH1_GPTIMER1CTRL_GPTCNT_MASK        0xFFFFFFu
37226 #define USBC_UH1_GPTIMER1CTRL_GPTCNT_SHIFT       0
37227 #define USBC_UH1_GPTIMER1CTRL_GPTCNT(x)          (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UH1_GPTIMER1CTRL_GPTCNT_MASK)
37228 #define USBC_UH1_GPTIMER1CTRL_GPTMODE_MASK       0x1000000u
37229 #define USBC_UH1_GPTIMER1CTRL_GPTMODE_SHIFT      24
37230 #define USBC_UH1_GPTIMER1CTRL_GPTRST_MASK        0x40000000u
37231 #define USBC_UH1_GPTIMER1CTRL_GPTRST_SHIFT       30
37232 #define USBC_UH1_GPTIMER1CTRL_GPTRUN_MASK        0x80000000u
37233 #define USBC_UH1_GPTIMER1CTRL_GPTRUN_SHIFT       31
37234 /* UH1_SBUSCFG Bit Fields */
37235 #define USBC_UH1_SBUSCFG_AHBBRST_MASK            0x7u
37236 #define USBC_UH1_SBUSCFG_AHBBRST_SHIFT           0
37237 #define USBC_UH1_SBUSCFG_AHBBRST(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_SBUSCFG_AHBBRST_SHIFT))&USBC_UH1_SBUSCFG_AHBBRST_MASK)
37238 /* UH1_CAPLENGTH Bit Fields */
37239 #define USBC_UH1_CAPLENGTH_CAPLENGTH_MASK        0xFFu
37240 #define USBC_UH1_CAPLENGTH_CAPLENGTH_SHIFT       0
37241 #define USBC_UH1_CAPLENGTH_CAPLENGTH(x)          (((uint8_t)(((uint8_t)(x))<<USBC_UH1_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UH1_CAPLENGTH_CAPLENGTH_MASK)
37242 /* UH1_HCIVERSION Bit Fields */
37243 #define USBC_UH1_HCIVERSION_HCIVERSION_MASK      0xFFFFu
37244 #define USBC_UH1_HCIVERSION_HCIVERSION_SHIFT     0
37245 #define USBC_UH1_HCIVERSION_HCIVERSION(x)        (((uint16_t)(((uint16_t)(x))<<USBC_UH1_HCIVERSION_HCIVERSION_SHIFT))&USBC_UH1_HCIVERSION_HCIVERSION_MASK)
37246 /* UH1_HCSPARAMS Bit Fields */
37247 #define USBC_UH1_HCSPARAMS_N_PORTS_MASK          0xFu
37248 #define USBC_UH1_HCSPARAMS_N_PORTS_SHIFT         0
37249 #define USBC_UH1_HCSPARAMS_N_PORTS(x)            (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PORTS_SHIFT))&USBC_UH1_HCSPARAMS_N_PORTS_MASK)
37250 #define USBC_UH1_HCSPARAMS_PPC_MASK              0x10u
37251 #define USBC_UH1_HCSPARAMS_PPC_SHIFT             4
37252 #define USBC_UH1_HCSPARAMS_N_PCC_MASK            0xF00u
37253 #define USBC_UH1_HCSPARAMS_N_PCC_SHIFT           8
37254 #define USBC_UH1_HCSPARAMS_N_PCC(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PCC_SHIFT))&USBC_UH1_HCSPARAMS_N_PCC_MASK)
37255 #define USBC_UH1_HCSPARAMS_N_CC_MASK             0xF000u
37256 #define USBC_UH1_HCSPARAMS_N_CC_SHIFT            12
37257 #define USBC_UH1_HCSPARAMS_N_CC(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_CC_SHIFT))&USBC_UH1_HCSPARAMS_N_CC_MASK)
37258 #define USBC_UH1_HCSPARAMS_PI_MASK               0x10000u
37259 #define USBC_UH1_HCSPARAMS_PI_SHIFT              16
37260 #define USBC_UH1_HCSPARAMS_N_PTT_MASK            0xF00000u
37261 #define USBC_UH1_HCSPARAMS_N_PTT_SHIFT           20
37262 #define USBC_UH1_HCSPARAMS_N_PTT(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PTT_SHIFT))&USBC_UH1_HCSPARAMS_N_PTT_MASK)
37263 #define USBC_UH1_HCSPARAMS_N_TT_MASK             0xF000000u
37264 #define USBC_UH1_HCSPARAMS_N_TT_SHIFT            24
37265 #define USBC_UH1_HCSPARAMS_N_TT(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_TT_SHIFT))&USBC_UH1_HCSPARAMS_N_TT_MASK)
37266 /* UH1_HCCPARAMS Bit Fields */
37267 #define USBC_UH1_HCCPARAMS_ADC_MASK              0x1u
37268 #define USBC_UH1_HCCPARAMS_ADC_SHIFT             0
37269 #define USBC_UH1_HCCPARAMS_PFL_MASK              0x2u
37270 #define USBC_UH1_HCCPARAMS_PFL_SHIFT             1
37271 #define USBC_UH1_HCCPARAMS_ASP_MASK              0x4u
37272 #define USBC_UH1_HCCPARAMS_ASP_SHIFT             2
37273 #define USBC_UH1_HCCPARAMS_IST_MASK              0xF0u
37274 #define USBC_UH1_HCCPARAMS_IST_SHIFT             4
37275 #define USBC_UH1_HCCPARAMS_IST(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCCPARAMS_IST_SHIFT))&USBC_UH1_HCCPARAMS_IST_MASK)
37276 #define USBC_UH1_HCCPARAMS_EECP_MASK             0xFF00u
37277 #define USBC_UH1_HCCPARAMS_EECP_SHIFT            8
37278 #define USBC_UH1_HCCPARAMS_EECP(x)               (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCCPARAMS_EECP_SHIFT))&USBC_UH1_HCCPARAMS_EECP_MASK)
37279 /* UH1_USBCMD Bit Fields */
37280 #define USBC_UH1_USBCMD_RS_MASK                  0x1u
37281 #define USBC_UH1_USBCMD_RS_SHIFT                 0
37282 #define USBC_UH1_USBCMD_RST_MASK                 0x2u
37283 #define USBC_UH1_USBCMD_RST_SHIFT                1
37284 #define USBC_UH1_USBCMD_FS_1_MASK                0xCu
37285 #define USBC_UH1_USBCMD_FS_1_SHIFT               2
37286 #define USBC_UH1_USBCMD_FS_1(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_FS_1_SHIFT))&USBC_UH1_USBCMD_FS_1_MASK)
37287 #define USBC_UH1_USBCMD_PSE_MASK                 0x10u
37288 #define USBC_UH1_USBCMD_PSE_SHIFT                4
37289 #define USBC_UH1_USBCMD_ASE_MASK                 0x20u
37290 #define USBC_UH1_USBCMD_ASE_SHIFT                5
37291 #define USBC_UH1_USBCMD_IAA_MASK                 0x40u
37292 #define USBC_UH1_USBCMD_IAA_SHIFT                6
37293 #define USBC_UH1_USBCMD_ASP_MASK                 0x300u
37294 #define USBC_UH1_USBCMD_ASP_SHIFT                8
37295 #define USBC_UH1_USBCMD_ASP(x)                   (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_ASP_SHIFT))&USBC_UH1_USBCMD_ASP_MASK)
37296 #define USBC_UH1_USBCMD_ASPE_MASK                0x800u
37297 #define USBC_UH1_USBCMD_ASPE_SHIFT               11
37298 #define USBC_UH1_USBCMD_SUTW_MASK                0x2000u
37299 #define USBC_UH1_USBCMD_SUTW_SHIFT               13
37300 #define USBC_UH1_USBCMD_ATDTW_MASK               0x4000u
37301 #define USBC_UH1_USBCMD_ATDTW_SHIFT              14
37302 #define USBC_UH1_USBCMD_FS_2_MASK                0x8000u
37303 #define USBC_UH1_USBCMD_FS_2_SHIFT               15
37304 #define USBC_UH1_USBCMD_ITC_MASK                 0xFF0000u
37305 #define USBC_UH1_USBCMD_ITC_SHIFT                16
37306 #define USBC_UH1_USBCMD_ITC(x)                   (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_ITC_SHIFT))&USBC_UH1_USBCMD_ITC_MASK)
37307 /* UH1_USBSTS Bit Fields */
37308 #define USBC_UH1_USBSTS_UI_MASK                  0x1u
37309 #define USBC_UH1_USBSTS_UI_SHIFT                 0
37310 #define USBC_UH1_USBSTS_UEI_MASK                 0x2u
37311 #define USBC_UH1_USBSTS_UEI_SHIFT                1
37312 #define USBC_UH1_USBSTS_PCI_MASK                 0x4u
37313 #define USBC_UH1_USBSTS_PCI_SHIFT                2
37314 #define USBC_UH1_USBSTS_FRI_MASK                 0x8u
37315 #define USBC_UH1_USBSTS_FRI_SHIFT                3
37316 #define USBC_UH1_USBSTS_SEI_MASK                 0x10u
37317 #define USBC_UH1_USBSTS_SEI_SHIFT                4
37318 #define USBC_UH1_USBSTS_AAI_MASK                 0x20u
37319 #define USBC_UH1_USBSTS_AAI_SHIFT                5
37320 #define USBC_UH1_USBSTS_URI_MASK                 0x40u
37321 #define USBC_UH1_USBSTS_URI_SHIFT                6
37322 #define USBC_UH1_USBSTS_SRI_MASK                 0x80u
37323 #define USBC_UH1_USBSTS_SRI_SHIFT                7
37324 #define USBC_UH1_USBSTS_SLI_MASK                 0x100u
37325 #define USBC_UH1_USBSTS_SLI_SHIFT                8
37326 #define USBC_UH1_USBSTS_ULPII_MASK               0x400u
37327 #define USBC_UH1_USBSTS_ULPII_SHIFT              10
37328 #define USBC_UH1_USBSTS_HCH_MASK                 0x1000u
37329 #define USBC_UH1_USBSTS_HCH_SHIFT                12
37330 #define USBC_UH1_USBSTS_RCL_MASK                 0x2000u
37331 #define USBC_UH1_USBSTS_RCL_SHIFT                13
37332 #define USBC_UH1_USBSTS_PS_MASK                  0x4000u
37333 #define USBC_UH1_USBSTS_PS_SHIFT                 14
37334 #define USBC_UH1_USBSTS_AS_MASK                  0x8000u
37335 #define USBC_UH1_USBSTS_AS_SHIFT                 15
37336 #define USBC_UH1_USBSTS_NAKI_MASK                0x10000u
37337 #define USBC_UH1_USBSTS_NAKI_SHIFT               16
37338 #define USBC_UH1_USBSTS_TI0_MASK                 0x1000000u
37339 #define USBC_UH1_USBSTS_TI0_SHIFT                24
37340 #define USBC_UH1_USBSTS_TI1_MASK                 0x2000000u
37341 #define USBC_UH1_USBSTS_TI1_SHIFT                25
37342 /* UH1_USBINTR Bit Fields */
37343 #define USBC_UH1_USBINTR_UE_MASK                 0x1u
37344 #define USBC_UH1_USBINTR_UE_SHIFT                0
37345 #define USBC_UH1_USBINTR_UEE_MASK                0x2u
37346 #define USBC_UH1_USBINTR_UEE_SHIFT               1
37347 #define USBC_UH1_USBINTR_PCE_MASK                0x4u
37348 #define USBC_UH1_USBINTR_PCE_SHIFT               2
37349 #define USBC_UH1_USBINTR_FRE_MASK                0x8u
37350 #define USBC_UH1_USBINTR_FRE_SHIFT               3
37351 #define USBC_UH1_USBINTR_SEE_MASK                0x10u
37352 #define USBC_UH1_USBINTR_SEE_SHIFT               4
37353 #define USBC_UH1_USBINTR_AAE_MASK                0x20u
37354 #define USBC_UH1_USBINTR_AAE_SHIFT               5
37355 #define USBC_UH1_USBINTR_URE_MASK                0x40u
37356 #define USBC_UH1_USBINTR_URE_SHIFT               6
37357 #define USBC_UH1_USBINTR_SRE_MASK                0x80u
37358 #define USBC_UH1_USBINTR_SRE_SHIFT               7
37359 #define USBC_UH1_USBINTR_SLE_MASK                0x100u
37360 #define USBC_UH1_USBINTR_SLE_SHIFT               8
37361 #define USBC_UH1_USBINTR_ULPIE_MASK              0x400u
37362 #define USBC_UH1_USBINTR_ULPIE_SHIFT             10
37363 #define USBC_UH1_USBINTR_NAKE_MASK               0x10000u
37364 #define USBC_UH1_USBINTR_NAKE_SHIFT              16
37365 #define USBC_UH1_USBINTR_UAIE_MASK               0x40000u
37366 #define USBC_UH1_USBINTR_UAIE_SHIFT              18
37367 #define USBC_UH1_USBINTR_UPIE_MASK               0x80000u
37368 #define USBC_UH1_USBINTR_UPIE_SHIFT              19
37369 #define USBC_UH1_USBINTR_TIE0_MASK               0x1000000u
37370 #define USBC_UH1_USBINTR_TIE0_SHIFT              24
37371 #define USBC_UH1_USBINTR_TIE1_MASK               0x2000000u
37372 #define USBC_UH1_USBINTR_TIE1_SHIFT              25
37373 /* UH1_FRINDEX Bit Fields */
37374 #define USBC_UH1_FRINDEX_FRINDEX_MASK            0x3FFFu
37375 #define USBC_UH1_FRINDEX_FRINDEX_SHIFT           0
37376 #define USBC_UH1_FRINDEX_FRINDEX(x)              (((uint32_t)(((uint32_t)(x))<<USBC_UH1_FRINDEX_FRINDEX_SHIFT))&USBC_UH1_FRINDEX_FRINDEX_MASK)
37377 /* UH1_PERIODICLISTBASE Bit Fields */
37378 #define USBC_UH1_PERIODICLISTBASE_BASEADR_MASK   0xFFFFF000u
37379 #define USBC_UH1_PERIODICLISTBASE_BASEADR_SHIFT  12
37380 #define USBC_UH1_PERIODICLISTBASE_BASEADR(x)     (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UH1_PERIODICLISTBASE_BASEADR_MASK)
37381 /* UH1_ASYNCLISTADDR Bit Fields */
37382 #define USBC_UH1_ASYNCLISTADDR_ASYBASE_MASK      0xFFFFFFE0u
37383 #define USBC_UH1_ASYNCLISTADDR_ASYBASE_SHIFT     5
37384 #define USBC_UH1_ASYNCLISTADDR_ASYBASE(x)        (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UH1_ASYNCLISTADDR_ASYBASE_MASK)
37385 /* UH1_BURSTSIZE Bit Fields */
37386 #define USBC_UH1_BURSTSIZE_RXPBURST_MASK         0xFFu
37387 #define USBC_UH1_BURSTSIZE_RXPBURST_SHIFT        0
37388 #define USBC_UH1_BURSTSIZE_RXPBURST(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UH1_BURSTSIZE_RXPBURST_SHIFT))&USBC_UH1_BURSTSIZE_RXPBURST_MASK)
37389 #define USBC_UH1_BURSTSIZE_TXPBURST_MASK         0x1FF00u
37390 #define USBC_UH1_BURSTSIZE_TXPBURST_SHIFT        8
37391 #define USBC_UH1_BURSTSIZE_TXPBURST(x)           (((uint32_t)(((uint32_t)(x))<<USBC_UH1_BURSTSIZE_TXPBURST_SHIFT))&USBC_UH1_BURSTSIZE_TXPBURST_MASK)
37392 /* UH1_TXFILLTUNING Bit Fields */
37393 #define USBC_UH1_TXFILLTUNING_TXSCHOH_MASK       0xFFu
37394 #define USBC_UH1_TXFILLTUNING_TXSCHOH_SHIFT      0
37395 #define USBC_UH1_TXFILLTUNING_TXSCHOH(x)         (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UH1_TXFILLTUNING_TXSCHOH_MASK)
37396 #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH_MASK   0x1F00u
37397 #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH_SHIFT  8
37398 #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH(x)     (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UH1_TXFILLTUNING_TXSCHHEALTH_MASK)
37399 #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES_MASK   0x3F0000u
37400 #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES_SHIFT  16
37401 #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES(x)     (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UH1_TXFILLTUNING_TXFIFOTHRES_MASK)
37402 /* UH1_CONFIGFLAG Bit Fields */
37403 #define USBC_UH1_CONFIGFLAG_CF_MASK              0x1u
37404 #define USBC_UH1_CONFIGFLAG_CF_SHIFT             0
37405 /* UH1_PORTSC1 Bit Fields */
37406 #define USBC_UH1_PORTSC1_CCS_MASK                0x1u
37407 #define USBC_UH1_PORTSC1_CCS_SHIFT               0
37408 #define USBC_UH1_PORTSC1_CSC_MASK                0x2u
37409 #define USBC_UH1_PORTSC1_CSC_SHIFT               1
37410 #define USBC_UH1_PORTSC1_PE_MASK                 0x4u
37411 #define USBC_UH1_PORTSC1_PE_SHIFT                2
37412 #define USBC_UH1_PORTSC1_PEC_MASK                0x8u
37413 #define USBC_UH1_PORTSC1_PEC_SHIFT               3
37414 #define USBC_UH1_PORTSC1_OCA_MASK                0x10u
37415 #define USBC_UH1_PORTSC1_OCA_SHIFT               4
37416 #define USBC_UH1_PORTSC1_OCC_MASK                0x20u
37417 #define USBC_UH1_PORTSC1_OCC_SHIFT               5
37418 #define USBC_UH1_PORTSC1_FPR_MASK                0x40u
37419 #define USBC_UH1_PORTSC1_FPR_SHIFT               6
37420 #define USBC_UH1_PORTSC1_SUSP_MASK               0x80u
37421 #define USBC_UH1_PORTSC1_SUSP_SHIFT              7
37422 #define USBC_UH1_PORTSC1_PR_MASK                 0x100u
37423 #define USBC_UH1_PORTSC1_PR_SHIFT                8
37424 #define USBC_UH1_PORTSC1_HSP_MASK                0x200u
37425 #define USBC_UH1_PORTSC1_HSP_SHIFT               9
37426 #define USBC_UH1_PORTSC1_LS_MASK                 0xC00u
37427 #define USBC_UH1_PORTSC1_LS_SHIFT                10
37428 #define USBC_UH1_PORTSC1_LS(x)                   (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_LS_SHIFT))&USBC_UH1_PORTSC1_LS_MASK)
37429 #define USBC_UH1_PORTSC1_PP_MASK                 0x1000u
37430 #define USBC_UH1_PORTSC1_PP_SHIFT                12
37431 #define USBC_UH1_PORTSC1_PO_MASK                 0x2000u
37432 #define USBC_UH1_PORTSC1_PO_SHIFT                13
37433 #define USBC_UH1_PORTSC1_PIC_MASK                0xC000u
37434 #define USBC_UH1_PORTSC1_PIC_SHIFT               14
37435 #define USBC_UH1_PORTSC1_PIC(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PIC_SHIFT))&USBC_UH1_PORTSC1_PIC_MASK)
37436 #define USBC_UH1_PORTSC1_PTC_MASK                0xF0000u
37437 #define USBC_UH1_PORTSC1_PTC_SHIFT               16
37438 #define USBC_UH1_PORTSC1_PTC(x)                  (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PTC_SHIFT))&USBC_UH1_PORTSC1_PTC_MASK)
37439 #define USBC_UH1_PORTSC1_WKCN_MASK               0x100000u
37440 #define USBC_UH1_PORTSC1_WKCN_SHIFT              20
37441 #define USBC_UH1_PORTSC1_WKDC_MASK               0x200000u
37442 #define USBC_UH1_PORTSC1_WKDC_SHIFT              21
37443 #define USBC_UH1_PORTSC1_WKOC_MASK               0x400000u
37444 #define USBC_UH1_PORTSC1_WKOC_SHIFT              22
37445 #define USBC_UH1_PORTSC1_PHCD_MASK               0x800000u
37446 #define USBC_UH1_PORTSC1_PHCD_SHIFT              23
37447 #define USBC_UH1_PORTSC1_PFSC_MASK               0x1000000u
37448 #define USBC_UH1_PORTSC1_PFSC_SHIFT              24
37449 #define USBC_UH1_PORTSC1_PTS_2_MASK              0x2000000u
37450 #define USBC_UH1_PORTSC1_PTS_2_SHIFT             25
37451 #define USBC_UH1_PORTSC1_PSPD_MASK               0xC000000u
37452 #define USBC_UH1_PORTSC1_PSPD_SHIFT              26
37453 #define USBC_UH1_PORTSC1_PSPD(x)                 (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PSPD_SHIFT))&USBC_UH1_PORTSC1_PSPD_MASK)
37454 #define USBC_UH1_PORTSC1_PTW_MASK                0x10000000u
37455 #define USBC_UH1_PORTSC1_PTW_SHIFT               28
37456 #define USBC_UH1_PORTSC1_STS_MASK                0x20000000u
37457 #define USBC_UH1_PORTSC1_STS_SHIFT               29
37458 #define USBC_UH1_PORTSC1_PTS_1_MASK              0xC0000000u
37459 #define USBC_UH1_PORTSC1_PTS_1_SHIFT             30
37460 #define USBC_UH1_PORTSC1_PTS_1(x)                (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PTS_1_SHIFT))&USBC_UH1_PORTSC1_PTS_1_MASK)
37461 /* UH1_USBMODE Bit Fields */
37462 #define USBC_UH1_USBMODE_CM_MASK                 0x3u
37463 #define USBC_UH1_USBMODE_CM_SHIFT                0
37464 #define USBC_UH1_USBMODE_CM(x)                   (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBMODE_CM_SHIFT))&USBC_UH1_USBMODE_CM_MASK)
37465 #define USBC_UH1_USBMODE_ES_MASK                 0x4u
37466 #define USBC_UH1_USBMODE_ES_SHIFT                2
37467 #define USBC_UH1_USBMODE_SLOM_MASK               0x8u
37468 #define USBC_UH1_USBMODE_SLOM_SHIFT              3
37469 #define USBC_UH1_USBMODE_SDIS_MASK               0x10u
37470 #define USBC_UH1_USBMODE_SDIS_SHIFT              4
37471 
37472 /*!
37473  * @}
37474  */ /* end of group USBC_Register_Masks */
37475 
37476 /* USBC - Peripheral instance base addresses */
37477 /** Peripheral USBC base address */
37478 #define USBC_BASE                                (0x42184000u)
37479 /** Peripheral USBC base pointer */
37480 #define USBC                                     ((USBC_Type *)USBC_BASE)
37481 #define USBC_BASE_PTR                            (USBC)
37482 /** Array initializer of USBC peripheral base addresses */
37483 #define USBC_BASE_ADDRS                          { USBC_BASE }
37484 /** Array initializer of USBC peripheral base pointers */
37485 #define USBC_BASE_PTRS                           { USBC }
37486 
37487 /* ----------------------------------------------------------------------------
37488    -- USBC - Register accessor macros
37489    ---------------------------------------------------------------------------- */
37490 
37491 /*!
37492  * @addtogroup USBC_Register_Accessor_Macros USBC - Register accessor macros
37493  * @{
37494  */
37495 
37496 /* USBC - Register instance definitions */
37497 /* USBC */
37498 #define USBC_UOG1_ID                             USBC_UOG1_ID_REG(USBC_BASE_PTR)
37499 #define USBC_UOG1_HWGENERAL                      USBC_UOG1_HWGENERAL_REG(USBC_BASE_PTR)
37500 #define USBC_UOG1_HWHOST                         USBC_UOG1_HWHOST_REG(USBC_BASE_PTR)
37501 #define USBC_UOG1_HWDEVICE                       USBC_UOG1_HWDEVICE_REG(USBC_BASE_PTR)
37502 #define USBC_UOG1_HWTXBUF                        USBC_UOG1_HWTXBUF_REG(USBC_BASE_PTR)
37503 #define USBC_UOG1_HWRXBUF                        USBC_UOG1_HWRXBUF_REG(USBC_BASE_PTR)
37504 #define USBC_UOG1_GPTIMER0LD                     USBC_UOG1_GPTIMER0LD_REG(USBC_BASE_PTR)
37505 #define USBC_UOG1_GPTIMER0CTRL                   USBC_UOG1_GPTIMER0CTRL_REG(USBC_BASE_PTR)
37506 #define USBC_UOG1_GPTIMER1LD                     USBC_UOG1_GPTIMER1LD_REG(USBC_BASE_PTR)
37507 #define USBC_UOG1_GPTIMER1CTRL                   USBC_UOG1_GPTIMER1CTRL_REG(USBC_BASE_PTR)
37508 #define USBC_UOG1_SBUSCFG                        USBC_UOG1_SBUSCFG_REG(USBC_BASE_PTR)
37509 #define USBC_UOG1_CAPLENGTH                      USBC_UOG1_CAPLENGTH_REG(USBC_BASE_PTR)
37510 #define USBC_UOG1_HCIVERSION                     USBC_UOG1_HCIVERSION_REG(USBC_BASE_PTR)
37511 #define USBC_UOG1_HCSPARAMS                      USBC_UOG1_HCSPARAMS_REG(USBC_BASE_PTR)
37512 #define USBC_UOG1_HCCPARAMS                      USBC_UOG1_HCCPARAMS_REG(USBC_BASE_PTR)
37513 #define USBC_UOG1_DCIVERSION                     USBC_UOG1_DCIVERSION_REG(USBC_BASE_PTR)
37514 #define USBC_UOG1_DCCPARAMS                      USBC_UOG1_DCCPARAMS_REG(USBC_BASE_PTR)
37515 #define USBC_UOG1_USBCMD                         USBC_UOG1_USBCMD_REG(USBC_BASE_PTR)
37516 #define USBC_UOG1_USBSTS                         USBC_UOG1_USBSTS_REG(USBC_BASE_PTR)
37517 #define USBC_UOG1_USBINTR                        USBC_UOG1_USBINTR_REG(USBC_BASE_PTR)
37518 #define USBC_UOG1_FRINDEX                        USBC_UOG1_FRINDEX_REG(USBC_BASE_PTR)
37519 #define USBC_UOG1_PERIODICLISTBASE               USBC_UOG1_PERIODICLISTBASE_REG(USBC_BASE_PTR)
37520 #define USBC_UOG1_DEVICEADDR                     USBC_UOG1_DEVICEADDR_REG(USBC_BASE_PTR)
37521 #define USBC_UOG1_ASYNCLISTADDR                  USBC_UOG1_ASYNCLISTADDR_REG(USBC_BASE_PTR)
37522 #define USBC_UOG1_ENDPTLISTADDR                  USBC_UOG1_ENDPTLISTADDR_REG(USBC_BASE_PTR)
37523 #define USBC_UOG1_BURSTSIZE                      USBC_UOG1_BURSTSIZE_REG(USBC_BASE_PTR)
37524 #define USBC_UOG1_TXFILLTUNING                   USBC_UOG1_TXFILLTUNING_REG(USBC_BASE_PTR)
37525 #define USBC_UOG1_ENDPTNAK                       USBC_UOG1_ENDPTNAK_REG(USBC_BASE_PTR)
37526 #define USBC_UOG1_ENDPTNAKEN                     USBC_UOG1_ENDPTNAKEN_REG(USBC_BASE_PTR)
37527 #define USBC_UOG1_CONFIGFLAG                     USBC_UOG1_CONFIGFLAG_REG(USBC_BASE_PTR)
37528 #define USBC_UOG1_PORTSC1                        USBC_UOG1_PORTSC1_REG(USBC_BASE_PTR)
37529 #define USBC_UOG1_OTGSC                          USBC_UOG1_OTGSC_REG(USBC_BASE_PTR)
37530 #define USBC_UOG1_USBMODE                        USBC_UOG1_USBMODE_REG(USBC_BASE_PTR)
37531 #define USBC_UOG1_ENDPTSETUPSTAT                 USBC_UOG1_ENDPTSETUPSTAT_REG(USBC_BASE_PTR)
37532 #define USBC_UOG1_ENDPTPRIME                     USBC_UOG1_ENDPTPRIME_REG(USBC_BASE_PTR)
37533 #define USBC_UOG1_ENDPTFLUSH                     USBC_UOG1_ENDPTFLUSH_REG(USBC_BASE_PTR)
37534 #define USBC_UOG1_ENDPTSTAT                      USBC_UOG1_ENDPTSTAT_REG(USBC_BASE_PTR)
37535 #define USBC_UOG1_ENDPTCOMPLETE                  USBC_UOG1_ENDPTCOMPLETE_REG(USBC_BASE_PTR)
37536 #define USBC_UOG1_ENDPTCTRL0                     USBC_UOG1_ENDPTCTRL0_REG(USBC_BASE_PTR)
37537 #define USBC_UOG1_ENDPTCTRL1                     USBC_UOG1_ENDPTCTRL1_REG(USBC_BASE_PTR)
37538 #define USBC_UOG1_ENDPTCTRL2                     USBC_UOG1_ENDPTCTRL2_REG(USBC_BASE_PTR)
37539 #define USBC_UOG1_ENDPTCTRL3                     USBC_UOG1_ENDPTCTRL3_REG(USBC_BASE_PTR)
37540 #define USBC_UOG1_ENDPTCTRL4                     USBC_UOG1_ENDPTCTRL4_REG(USBC_BASE_PTR)
37541 #define USBC_UOG1_ENDPTCTRL5                     USBC_UOG1_ENDPTCTRL5_REG(USBC_BASE_PTR)
37542 #define USBC_UOG1_ENDPTCTRL6                     USBC_UOG1_ENDPTCTRL6_REG(USBC_BASE_PTR)
37543 #define USBC_UOG1_ENDPTCTRL7                     USBC_UOG1_ENDPTCTRL7_REG(USBC_BASE_PTR)
37544 #define USBC_UOG2_ID                             USBC_UOG2_ID_REG(USBC_BASE_PTR)
37545 #define USBC_UOG2_HWGENERAL                      USBC_UOG2_HWGENERAL_REG(USBC_BASE_PTR)
37546 #define USBC_UOG2_HWHOST                         USBC_UOG2_HWHOST_REG(USBC_BASE_PTR)
37547 #define USBC_UOG2_HWDEVICE                       USBC_UOG2_HWDEVICE_REG(USBC_BASE_PTR)
37548 #define USBC_UOG2_HWTXBUF                        USBC_UOG2_HWTXBUF_REG(USBC_BASE_PTR)
37549 #define USBC_UOG2_HWRXBUF                        USBC_UOG2_HWRXBUF_REG(USBC_BASE_PTR)
37550 #define USBC_UOG2_GPTIMER0LD                     USBC_UOG2_GPTIMER0LD_REG(USBC_BASE_PTR)
37551 #define USBC_UOG2_GPTIMER0CTRL                   USBC_UOG2_GPTIMER0CTRL_REG(USBC_BASE_PTR)
37552 #define USBC_UOG2_GPTIMER1LD                     USBC_UOG2_GPTIMER1LD_REG(USBC_BASE_PTR)
37553 #define USBC_UOG2_GPTIMER1CTRL                   USBC_UOG2_GPTIMER1CTRL_REG(USBC_BASE_PTR)
37554 #define USBC_UOG2_SBUSCFG                        USBC_UOG2_SBUSCFG_REG(USBC_BASE_PTR)
37555 #define USBC_UOG2_CAPLENGTH                      USBC_UOG2_CAPLENGTH_REG(USBC_BASE_PTR)
37556 #define USBC_UOG2_HCIVERSION                     USBC_UOG2_HCIVERSION_REG(USBC_BASE_PTR)
37557 #define USBC_UOG2_HCSPARAMS                      USBC_UOG2_HCSPARAMS_REG(USBC_BASE_PTR)
37558 #define USBC_UOG2_HCCPARAMS                      USBC_UOG2_HCCPARAMS_REG(USBC_BASE_PTR)
37559 #define USBC_UOG2_DCIVERSION                     USBC_UOG2_DCIVERSION_REG(USBC_BASE_PTR)
37560 #define USBC_UOG2_DCCPARAMS                      USBC_UOG2_DCCPARAMS_REG(USBC_BASE_PTR)
37561 #define USBC_UOG2_USBCMD                         USBC_UOG2_USBCMD_REG(USBC_BASE_PTR)
37562 #define USBC_UOG2_USBSTS                         USBC_UOG2_USBSTS_REG(USBC_BASE_PTR)
37563 #define USBC_UOG2_USBINTR                        USBC_UOG2_USBINTR_REG(USBC_BASE_PTR)
37564 #define USBC_UOG2_FRINDEX                        USBC_UOG2_FRINDEX_REG(USBC_BASE_PTR)
37565 #define USBC_UOG2_PERIODICLISTBASE               USBC_UOG2_PERIODICLISTBASE_REG(USBC_BASE_PTR)
37566 #define USBC_UOG2_DEVICEADDR                     USBC_UOG2_DEVICEADDR_REG(USBC_BASE_PTR)
37567 #define USBC_UOG2_ASYNCLISTADDR                  USBC_UOG2_ASYNCLISTADDR_REG(USBC_BASE_PTR)
37568 #define USBC_UOG2_ENDPTLISTADDR                  USBC_UOG2_ENDPTLISTADDR_REG(USBC_BASE_PTR)
37569 #define USBC_UOG2_BURSTSIZE                      USBC_UOG2_BURSTSIZE_REG(USBC_BASE_PTR)
37570 #define USBC_UOG2_TXFILLTUNING                   USBC_UOG2_TXFILLTUNING_REG(USBC_BASE_PTR)
37571 #define USBC_UOG2_ENDPTNAK                       USBC_UOG2_ENDPTNAK_REG(USBC_BASE_PTR)
37572 #define USBC_UOG2_ENDPTNAKEN                     USBC_UOG2_ENDPTNAKEN_REG(USBC_BASE_PTR)
37573 #define USBC_UOG2_CONFIGFLAG                     USBC_UOG2_CONFIGFLAG_REG(USBC_BASE_PTR)
37574 #define USBC_UOG2_PORTSC1                        USBC_UOG2_PORTSC1_REG(USBC_BASE_PTR)
37575 #define USBC_UOG2_OTGSC                          USBC_UOG2_OTGSC_REG(USBC_BASE_PTR)
37576 #define USBC_UOG2_USBMODE                        USBC_UOG2_USBMODE_REG(USBC_BASE_PTR)
37577 #define USBC_UOG2_ENDPTSETUPSTAT                 USBC_UOG2_ENDPTSETUPSTAT_REG(USBC_BASE_PTR)
37578 #define USBC_UOG2_ENDPTPRIME                     USBC_UOG2_ENDPTPRIME_REG(USBC_BASE_PTR)
37579 #define USBC_UOG2_ENDPTFLUSH                     USBC_UOG2_ENDPTFLUSH_REG(USBC_BASE_PTR)
37580 #define USBC_UOG2_ENDPTSTAT                      USBC_UOG2_ENDPTSTAT_REG(USBC_BASE_PTR)
37581 #define USBC_UOG2_ENDPTCOMPLETE                  USBC_UOG2_ENDPTCOMPLETE_REG(USBC_BASE_PTR)
37582 #define USBC_UOG2_ENDPTCTRL0                     USBC_UOG2_ENDPTCTRL0_REG(USBC_BASE_PTR)
37583 #define USBC_UOG2_ENDPTCTRL1                     USBC_UOG2_ENDPTCTRL1_REG(USBC_BASE_PTR)
37584 #define USBC_UOG2_ENDPTCTRL2                     USBC_UOG2_ENDPTCTRL2_REG(USBC_BASE_PTR)
37585 #define USBC_UOG2_ENDPTCTRL3                     USBC_UOG2_ENDPTCTRL3_REG(USBC_BASE_PTR)
37586 #define USBC_UOG2_ENDPTCTRL4                     USBC_UOG2_ENDPTCTRL4_REG(USBC_BASE_PTR)
37587 #define USBC_UOG2_ENDPTCTRL5                     USBC_UOG2_ENDPTCTRL5_REG(USBC_BASE_PTR)
37588 #define USBC_UOG2_ENDPTCTRL6                     USBC_UOG2_ENDPTCTRL6_REG(USBC_BASE_PTR)
37589 #define USBC_UOG2_ENDPTCTRL7                     USBC_UOG2_ENDPTCTRL7_REG(USBC_BASE_PTR)
37590 #define USBC_UH1_ID                              USBC_UH1_ID_REG(USBC_BASE_PTR)
37591 #define USBC_UH1_HWGENERAL                       USBC_UH1_HWGENERAL_REG(USBC_BASE_PTR)
37592 #define USBC_UH1_HWHOST                          USBC_UH1_HWHOST_REG(USBC_BASE_PTR)
37593 #define USBC_UH1_HWTXBUF                         USBC_UH1_HWTXBUF_REG(USBC_BASE_PTR)
37594 #define USBC_UH1_HWRXBUF                         USBC_UH1_HWRXBUF_REG(USBC_BASE_PTR)
37595 #define USBC_UH1_GPTIMER0LD                      USBC_UH1_GPTIMER0LD_REG(USBC_BASE_PTR)
37596 #define USBC_UH1_GPTIMER0CTRL                    USBC_UH1_GPTIMER0CTRL_REG(USBC_BASE_PTR)
37597 #define USBC_UH1_GPTIMER1LD                      USBC_UH1_GPTIMER1LD_REG(USBC_BASE_PTR)
37598 #define USBC_UH1_GPTIMER1CTRL                    USBC_UH1_GPTIMER1CTRL_REG(USBC_BASE_PTR)
37599 #define USBC_UH1_SBUSCFG                         USBC_UH1_SBUSCFG_REG(USBC_BASE_PTR)
37600 #define USBC_UH1_CAPLENGTH                       USBC_UH1_CAPLENGTH_REG(USBC_BASE_PTR)
37601 #define USBC_UH1_HCIVERSION                      USBC_UH1_HCIVERSION_REG(USBC_BASE_PTR)
37602 #define USBC_UH1_HCSPARAMS                       USBC_UH1_HCSPARAMS_REG(USBC_BASE_PTR)
37603 #define USBC_UH1_HCCPARAMS                       USBC_UH1_HCCPARAMS_REG(USBC_BASE_PTR)
37604 #define USBC_UH1_USBCMD                          USBC_UH1_USBCMD_REG(USBC_BASE_PTR)
37605 #define USBC_UH1_USBSTS                          USBC_UH1_USBSTS_REG(USBC_BASE_PTR)
37606 #define USBC_UH1_USBINTR                         USBC_UH1_USBINTR_REG(USBC_BASE_PTR)
37607 #define USBC_UH1_FRINDEX                         USBC_UH1_FRINDEX_REG(USBC_BASE_PTR)
37608 #define USBC_UH1_PERIODICLISTBASE                USBC_UH1_PERIODICLISTBASE_REG(USBC_BASE_PTR)
37609 #define USBC_UH1_ASYNCLISTADDR                   USBC_UH1_ASYNCLISTADDR_REG(USBC_BASE_PTR)
37610 #define USBC_UH1_BURSTSIZE                       USBC_UH1_BURSTSIZE_REG(USBC_BASE_PTR)
37611 #define USBC_UH1_TXFILLTUNING                    USBC_UH1_TXFILLTUNING_REG(USBC_BASE_PTR)
37612 #define USBC_UH1_CONFIGFLAG                      USBC_UH1_CONFIGFLAG_REG(USBC_BASE_PTR)
37613 #define USBC_UH1_PORTSC1                         USBC_UH1_PORTSC1_REG(USBC_BASE_PTR)
37614 #define USBC_UH1_USBMODE                         USBC_UH1_USBMODE_REG(USBC_BASE_PTR)
37615 
37616 /*!
37617  * @}
37618  */ /* end of group USBC_Register_Accessor_Macros */
37619 
37620 /*!
37621  * @}
37622  */ /* end of group USBC_Peripheral */
37623 
37624 /* ----------------------------------------------------------------------------
37625    -- USBNC Peripheral Access Layer
37626    ---------------------------------------------------------------------------- */
37627 
37628 /*!
37629  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
37630  * @{
37631  */
37632 
37633 /** USBNC - Register Layout Typedef */
37634 typedef struct {
37635   uint8_t RESERVED_0[572];
37636   __I   uint32_t USB_x_PHY_STS;                          /**< , offset: 0x23C */
37637   uint8_t RESERVED_1[20];
37638   __IO  uint32_t ADP_CFG2;                               /**< , offset: 0x254 */
37639   uint8_t RESERVED_2[1448];
37640   __IO  uint32_t USB_OTG1_CTRL;                          /**< USB OTG1 Control Register, offset: 0x800 */
37641   __IO  uint32_t USB_OTG2_CTRL;                          /**< USB OTG2 Control Register, offset: 0x804 */
37642   __IO  uint32_t USB_UH_CTRL;                            /**< USB Host Control Register, offset: 0x808 */
37643   uint8_t RESERVED_3[4];
37644   __IO  uint32_t USB_UH_HSIC_CTRL;                       /**< USB Host HSIC Control Register, offset: 0x810 */
37645   uint8_t RESERVED_4[4];
37646   __IO  uint32_t USB_OTG1_PHY_CTRL_0;                    /**< OTG1 UTMI PHY Control 0 Register, offset: 0x818 */
37647   __IO  uint32_t USB_OTG2_PHY_CTRL_0;                    /**< OTG2 UTMI PHY Control 0 Register, offset: 0x81C */
37648 } USBNC_Type, *USBNC_MemMapPtr;
37649 
37650 /* ----------------------------------------------------------------------------
37651    -- USBNC - Register accessor macros
37652    ---------------------------------------------------------------------------- */
37653 
37654 /*!
37655  * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros
37656  * @{
37657  */
37658 
37659 /* USBNC - Register accessors */
37660 #define USBNC_USB_x_PHY_STS_REG(base)            ((base)->USB_x_PHY_STS)
37661 #define USBNC_ADP_CFG2_REG(base)                 ((base)->ADP_CFG2)
37662 #define USBNC_USB_OTG1_CTRL_REG(base)            ((base)->USB_OTG1_CTRL)
37663 #define USBNC_USB_OTG2_CTRL_REG(base)            ((base)->USB_OTG2_CTRL)
37664 #define USBNC_USB_UH_CTRL_REG(base)              ((base)->USB_UH_CTRL)
37665 #define USBNC_USB_UH_HSIC_CTRL_REG(base)         ((base)->USB_UH_HSIC_CTRL)
37666 #define USBNC_USB_OTG1_PHY_CTRL_0_REG(base)      ((base)->USB_OTG1_PHY_CTRL_0)
37667 #define USBNC_USB_OTG2_PHY_CTRL_0_REG(base)      ((base)->USB_OTG2_PHY_CTRL_0)
37668 
37669 /*!
37670  * @}
37671  */ /* end of group USBNC_Register_Accessor_Macros */
37672 
37673 /* ----------------------------------------------------------------------------
37674    -- USBNC Register Masks
37675    ---------------------------------------------------------------------------- */
37676 
37677 /*!
37678  * @addtogroup USBNC_Register_Masks USBNC Register Masks
37679  * @{
37680  */
37681 
37682 /* USB_x_PHY_STS Bit Fields */
37683 #define USBNC_USB_x_PHY_STS_LINE_STATE_MASK      0x3u
37684 #define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT     0
37685 #define USBNC_USB_x_PHY_STS_LINE_STATE(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT))&USBNC_USB_x_PHY_STS_LINE_STATE_MASK)
37686 #define USBNC_USB_x_PHY_STS_SESS_VLD_MASK        0x4u
37687 #define USBNC_USB_x_PHY_STS_SESS_VLD_SHIFT       2
37688 #define USBNC_USB_x_PHY_STS_VBUS_VLD_MASK        0x8u
37689 #define USBNC_USB_x_PHY_STS_VBUS_VLD_SHIFT       3
37690 #define USBNC_USB_x_PHY_STS_ID_DIG_MASK          0x10u
37691 #define USBNC_USB_x_PHY_STS_ID_DIG_SHIFT         4
37692 #define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_MASK  0x20000000u
37693 #define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_SHIFT 29
37694 /* ADP_CFG2 Bit Fields */
37695 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK       0x7Fu
37696 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT      0
37697 #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x)         (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK)
37698 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK       0x80u
37699 #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT      7
37700 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK      0xFF00u
37701 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT     8
37702 #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK)
37703 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK      0xFF0000u
37704 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT     16
37705 #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x)        (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT))&USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK)
37706 /* USB_OTG1_CTRL Bit Fields */
37707 #define USBNC_USB_OTG1_CTRL_OVER_CUR_DIS_MASK    0x80u
37708 #define USBNC_USB_OTG1_CTRL_OVER_CUR_DIS_SHIFT   7
37709 #define USBNC_USB_OTG1_CTRL_OVER_CUR_POL_MASK    0x100u
37710 #define USBNC_USB_OTG1_CTRL_OVER_CUR_POL_SHIFT   8
37711 #define USBNC_USB_OTG1_CTRL_PWR_POL_MASK         0x200u
37712 #define USBNC_USB_OTG1_CTRL_PWR_POL_SHIFT        9
37713 #define USBNC_USB_OTG1_CTRL_WIE_MASK             0x400u
37714 #define USBNC_USB_OTG1_CTRL_WIE_SHIFT            10
37715 #define USBNC_USB_OTG1_CTRL_WKUP_SW_EN_MASK      0x4000u
37716 #define USBNC_USB_OTG1_CTRL_WKUP_SW_EN_SHIFT     14
37717 #define USBNC_USB_OTG1_CTRL_WKUP_SW_MASK         0x8000u
37718 #define USBNC_USB_OTG1_CTRL_WKUP_SW_SHIFT        15
37719 #define USBNC_USB_OTG1_CTRL_WKUP_ID_EN_MASK      0x10000u
37720 #define USBNC_USB_OTG1_CTRL_WKUP_ID_EN_SHIFT     16
37721 #define USBNC_USB_OTG1_CTRL_WKUP_VBUS_EN_MASK    0x20000u
37722 #define USBNC_USB_OTG1_CTRL_WKUP_VBUS_EN_SHIFT   17
37723 #define USBNC_USB_OTG1_CTRL_WIR_MASK             0x80000000u
37724 #define USBNC_USB_OTG1_CTRL_WIR_SHIFT            31
37725 /* USB_OTG2_CTRL Bit Fields */
37726 #define USBNC_USB_OTG2_CTRL_OVER_CUR_DIS_MASK    0x80u
37727 #define USBNC_USB_OTG2_CTRL_OVER_CUR_DIS_SHIFT   7
37728 #define USBNC_USB_OTG2_CTRL_OVER_CUR_POL_MASK    0x100u
37729 #define USBNC_USB_OTG2_CTRL_OVER_CUR_POL_SHIFT   8
37730 #define USBNC_USB_OTG2_CTRL_PWR_POL_MASK         0x200u
37731 #define USBNC_USB_OTG2_CTRL_PWR_POL_SHIFT        9
37732 #define USBNC_USB_OTG2_CTRL_WIE_MASK             0x400u
37733 #define USBNC_USB_OTG2_CTRL_WIE_SHIFT            10
37734 #define USBNC_USB_OTG2_CTRL_WKUP_SW_EN_MASK      0x4000u
37735 #define USBNC_USB_OTG2_CTRL_WKUP_SW_EN_SHIFT     14
37736 #define USBNC_USB_OTG2_CTRL_WKUP_SW_MASK         0x8000u
37737 #define USBNC_USB_OTG2_CTRL_WKUP_SW_SHIFT        15
37738 #define USBNC_USB_OTG2_CTRL_WKUP_ID_EN_MASK      0x10000u
37739 #define USBNC_USB_OTG2_CTRL_WKUP_ID_EN_SHIFT     16
37740 #define USBNC_USB_OTG2_CTRL_WKUP_VBUS_EN_MASK    0x20000u
37741 #define USBNC_USB_OTG2_CTRL_WKUP_VBUS_EN_SHIFT   17
37742 #define USBNC_USB_OTG2_CTRL_WIR_MASK             0x80000000u
37743 #define USBNC_USB_OTG2_CTRL_WIR_SHIFT            31
37744 /* USB_UH_CTRL Bit Fields */
37745 #define USBNC_USB_UH_CTRL_WIE_MASK               0x400u
37746 #define USBNC_USB_UH_CTRL_WIE_SHIFT              10
37747 #define USBNC_USB_UH_CTRL_RESET_MASK             0x800u
37748 #define USBNC_USB_UH_CTRL_RESET_SHIFT            11
37749 #define USBNC_USB_UH_CTRL_SUSPENDM_MASK          0x1000u
37750 #define USBNC_USB_UH_CTRL_SUSPENDM_SHIFT         12
37751 #define USBNC_USB_UH_CTRL_480M_CLK_ON_MASK       0x2000u
37752 #define USBNC_USB_UH_CTRL_480M_CLK_ON_SHIFT      13
37753 #define USBNC_USB_UH_CTRL_WKUP_SW_EN_MASK        0x4000u
37754 #define USBNC_USB_UH_CTRL_WKUP_SW_EN_SHIFT       14
37755 #define USBNC_USB_UH_CTRL_WKUP_SW_MASK           0x8000u
37756 #define USBNC_USB_UH_CTRL_WKUP_SW_SHIFT          15
37757 #define USBNC_USB_UH_CTRL_WIR_MASK               0x80000000u
37758 #define USBNC_USB_UH_CTRL_WIR_SHIFT              31
37759 /* USB_UH_HSIC_CTRL Bit Fields */
37760 #define USBNC_USB_UH_HSIC_CTRL_HSIC_CLK_ON_MASK  0x800u
37761 #define USBNC_USB_UH_HSIC_CTRL_HSIC_CLK_ON_SHIFT 11
37762 #define USBNC_USB_UH_HSIC_CTRL_HSIC_EN_MASK      0x1000u
37763 #define USBNC_USB_UH_HSIC_CTRL_HSIC_EN_SHIFT     12
37764 #define USBNC_USB_UH_HSIC_CTRL_CLK_VLD_MASK      0x80000000u
37765 #define USBNC_USB_UH_HSIC_CTRL_CLK_VLD_SHIFT     31
37766 /* USB_OTG1_PHY_CTRL_0 Bit Fields */
37767 #define USBNC_USB_OTG1_PHY_CTRL_0_UTMI_CLK_VLD_MASK 0x80000000u
37768 #define USBNC_USB_OTG1_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT 31
37769 /* USB_OTG2_PHY_CTRL_0 Bit Fields */
37770 #define USBNC_USB_OTG2_PHY_CTRL_0_UTMI_CLK_VLD_MASK 0x80000000u
37771 #define USBNC_USB_OTG2_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT 31
37772 
37773 /*!
37774  * @}
37775  */ /* end of group USBNC_Register_Masks */
37776 
37777 /* USBNC - Peripheral instance base addresses */
37778 /** Peripheral USBNC base address */
37779 #define USBNC_BASE                               (0x42184000u)
37780 /** Peripheral USBNC base pointer */
37781 #define USBNC                                    ((USBNC_Type *)USBNC_BASE)
37782 #define USBNC_BASE_PTR                           (USBNC)
37783 /** Array initializer of USBNC peripheral base addresses */
37784 #define USBNC_BASE_ADDRS                         { USBNC_BASE }
37785 /** Array initializer of USBNC peripheral base pointers */
37786 #define USBNC_BASE_PTRS                          { USBNC }
37787 
37788 /* ----------------------------------------------------------------------------
37789    -- USBNC - Register accessor macros
37790    ---------------------------------------------------------------------------- */
37791 
37792 /*!
37793  * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros
37794  * @{
37795  */
37796 
37797 /* USBNC - Register instance definitions */
37798 /* USBNC */
37799 #define USBNC_USB_x_PHY_STS                      USBNC_USB_x_PHY_STS_REG(USBNC_BASE_PTR)
37800 #define USBNC_ADP_CFG2                           USBNC_ADP_CFG2_REG(USBNC_BASE_PTR)
37801 #define USBNC_USB_OTG1_CTRL                      USBNC_USB_OTG1_CTRL_REG(USBNC_BASE_PTR)
37802 #define USBNC_USB_OTG2_CTRL                      USBNC_USB_OTG2_CTRL_REG(USBNC_BASE_PTR)
37803 #define USBNC_USB_UH_CTRL                        USBNC_USB_UH_CTRL_REG(USBNC_BASE_PTR)
37804 #define USBNC_USB_UH_HSIC_CTRL                   USBNC_USB_UH_HSIC_CTRL_REG(USBNC_BASE_PTR)
37805 #define USBNC_USB_OTG1_PHY_CTRL_0                USBNC_USB_OTG1_PHY_CTRL_0_REG(USBNC_BASE_PTR)
37806 #define USBNC_USB_OTG2_PHY_CTRL_0                USBNC_USB_OTG2_PHY_CTRL_0_REG(USBNC_BASE_PTR)
37807 
37808 /*!
37809  * @}
37810  */ /* end of group USBNC_Register_Accessor_Macros */
37811 
37812 /*!
37813  * @}
37814  */ /* end of group USBNC_Peripheral */
37815 
37816 /* ----------------------------------------------------------------------------
37817    -- USBPHY Peripheral Access Layer
37818    ---------------------------------------------------------------------------- */
37819 
37820 /*!
37821  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
37822  * @{
37823  */
37824 
37825 /** USBPHY - Register Layout Typedef */
37826 typedef struct {
37827   __IO  uint32_t PWD;                                    /**< USB PHY Power-Down Register, offset: 0x0 */
37828   __IO  uint32_t PWD_SET;                                /**< USB PHY Power-Down Register, offset: 0x4 */
37829   __IO  uint32_t PWD_CLR;                                /**< USB PHY Power-Down Register, offset: 0x8 */
37830   __IO  uint32_t PWD_TOG;                                /**< USB PHY Power-Down Register, offset: 0xC */
37831   __IO  uint32_t TX;                                     /**< USB PHY Transmitter Control Register, offset: 0x10 */
37832   __IO  uint32_t TX_SET;                                 /**< USB PHY Transmitter Control Register, offset: 0x14 */
37833   __IO  uint32_t TX_CLR;                                 /**< USB PHY Transmitter Control Register, offset: 0x18 */
37834   __IO  uint32_t TX_TOG;                                 /**< USB PHY Transmitter Control Register, offset: 0x1C */
37835   __IO  uint32_t RX;                                     /**< USB PHY Receiver Control Register, offset: 0x20 */
37836   __IO  uint32_t RX_SET;                                 /**< USB PHY Receiver Control Register, offset: 0x24 */
37837   __IO  uint32_t RX_CLR;                                 /**< USB PHY Receiver Control Register, offset: 0x28 */
37838   __IO  uint32_t RX_TOG;                                 /**< USB PHY Receiver Control Register, offset: 0x2C */
37839   __IO  uint32_t CTRL;                                   /**< USB PHY General Control Register, offset: 0x30 */
37840   __IO  uint32_t CTRL_SET;                               /**< USB PHY General Control Register, offset: 0x34 */
37841   __IO  uint32_t CTRL_CLR;                               /**< USB PHY General Control Register, offset: 0x38 */
37842   __IO  uint32_t CTRL_TOG;                               /**< USB PHY General Control Register, offset: 0x3C */
37843   __IO  uint32_t STATUS;                                 /**< USB PHY Status Register, offset: 0x40 */
37844   uint8_t RESERVED_0[12];
37845   __IO  uint32_t DEBUG;                                  /**< USB PHY Debug Register, offset: 0x50 */
37846   __IO  uint32_t DEBUG_SET;                              /**< USB PHY Debug Register, offset: 0x54 */
37847   __IO  uint32_t DEBUG_CLR;                              /**< USB PHY Debug Register, offset: 0x58 */
37848   __IO  uint32_t DEBUG_TOG;                              /**< USB PHY Debug Register, offset: 0x5C */
37849   __I   uint32_t DEBUG0_STATUS;                          /**< UTMI Debug Status Register 0, offset: 0x60 */
37850   uint8_t RESERVED_1[12];
37851   __IO  uint32_t DEBUG1;                                 /**< UTMI Debug Status Register 1, offset: 0x70 */
37852   __IO  uint32_t DEBUG1_SET;                             /**< UTMI Debug Status Register 1, offset: 0x74 */
37853   __IO  uint32_t DEBUG1_CLR;                             /**< UTMI Debug Status Register 1, offset: 0x78 */
37854   __IO  uint32_t DEBUG1_TOG;                             /**< UTMI Debug Status Register 1, offset: 0x7C */
37855   __I   uint32_t VERSION;                                /**< UTMI RTL Version, offset: 0x80 */
37856 } USBPHY_Type, *USBPHY_MemMapPtr;
37857 
37858 /* ----------------------------------------------------------------------------
37859    -- USBPHY - Register accessor macros
37860    ---------------------------------------------------------------------------- */
37861 
37862 /*!
37863  * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros
37864  * @{
37865  */
37866 
37867 /* USBPHY - Register accessors */
37868 #define USBPHY_PWD_REG(base)                     ((base)->PWD)
37869 #define USBPHY_PWD_SET_REG(base)                 ((base)->PWD_SET)
37870 #define USBPHY_PWD_CLR_REG(base)                 ((base)->PWD_CLR)
37871 #define USBPHY_PWD_TOG_REG(base)                 ((base)->PWD_TOG)
37872 #define USBPHY_TX_REG(base)                      ((base)->TX)
37873 #define USBPHY_TX_SET_REG(base)                  ((base)->TX_SET)
37874 #define USBPHY_TX_CLR_REG(base)                  ((base)->TX_CLR)
37875 #define USBPHY_TX_TOG_REG(base)                  ((base)->TX_TOG)
37876 #define USBPHY_RX_REG(base)                      ((base)->RX)
37877 #define USBPHY_RX_SET_REG(base)                  ((base)->RX_SET)
37878 #define USBPHY_RX_CLR_REG(base)                  ((base)->RX_CLR)
37879 #define USBPHY_RX_TOG_REG(base)                  ((base)->RX_TOG)
37880 #define USBPHY_CTRL_REG(base)                    ((base)->CTRL)
37881 #define USBPHY_CTRL_SET_REG(base)                ((base)->CTRL_SET)
37882 #define USBPHY_CTRL_CLR_REG(base)                ((base)->CTRL_CLR)
37883 #define USBPHY_CTRL_TOG_REG(base)                ((base)->CTRL_TOG)
37884 #define USBPHY_STATUS_REG(base)                  ((base)->STATUS)
37885 #define USBPHY_DEBUG_REG(base)                   ((base)->DEBUG)
37886 #define USBPHY_DEBUG_SET_REG(base)               ((base)->DEBUG_SET)
37887 #define USBPHY_DEBUG_CLR_REG(base)               ((base)->DEBUG_CLR)
37888 #define USBPHY_DEBUG_TOG_REG(base)               ((base)->DEBUG_TOG)
37889 #define USBPHY_DEBUG0_STATUS_REG(base)           ((base)->DEBUG0_STATUS)
37890 #define USBPHY_DEBUG1_REG(base)                  ((base)->DEBUG1)
37891 #define USBPHY_DEBUG1_SET_REG(base)              ((base)->DEBUG1_SET)
37892 #define USBPHY_DEBUG1_CLR_REG(base)              ((base)->DEBUG1_CLR)
37893 #define USBPHY_DEBUG1_TOG_REG(base)              ((base)->DEBUG1_TOG)
37894 #define USBPHY_VERSION_REG(base)                 ((base)->VERSION)
37895 
37896 /*!
37897  * @}
37898  */ /* end of group USBPHY_Register_Accessor_Macros */
37899 
37900 /* ----------------------------------------------------------------------------
37901    -- USBPHY Register Masks
37902    ---------------------------------------------------------------------------- */
37903 
37904 /*!
37905  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
37906  * @{
37907  */
37908 
37909 /* PWD Bit Fields */
37910 #define USBPHY_PWD_RSVD0_MASK                    0x3FFu
37911 #define USBPHY_PWD_RSVD0_SHIFT                   0
37912 #define USBPHY_PWD_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD0_SHIFT))&USBPHY_PWD_RSVD0_MASK)
37913 #define USBPHY_PWD_TXPWDFS_MASK                  0x400u
37914 #define USBPHY_PWD_TXPWDFS_SHIFT                 10
37915 #define USBPHY_PWD_TXPWDIBIAS_MASK               0x800u
37916 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              11
37917 #define USBPHY_PWD_TXPWDV2I_MASK                 0x1000u
37918 #define USBPHY_PWD_TXPWDV2I_SHIFT                12
37919 #define USBPHY_PWD_RSVD1_MASK                    0x1E000u
37920 #define USBPHY_PWD_RSVD1_SHIFT                   13
37921 #define USBPHY_PWD_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD1_SHIFT))&USBPHY_PWD_RSVD1_MASK)
37922 #define USBPHY_PWD_RXPWDENV_MASK                 0x20000u
37923 #define USBPHY_PWD_RXPWDENV_SHIFT                17
37924 #define USBPHY_PWD_RXPWD1PT1_MASK                0x40000u
37925 #define USBPHY_PWD_RXPWD1PT1_SHIFT               18
37926 #define USBPHY_PWD_RXPWDDIFF_MASK                0x80000u
37927 #define USBPHY_PWD_RXPWDDIFF_SHIFT               19
37928 #define USBPHY_PWD_RXPWDRX_MASK                  0x100000u
37929 #define USBPHY_PWD_RXPWDRX_SHIFT                 20
37930 #define USBPHY_PWD_RSVD2_MASK                    0xFFE00000u
37931 #define USBPHY_PWD_RSVD2_SHIFT                   21
37932 #define USBPHY_PWD_RSVD2(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD2_SHIFT))&USBPHY_PWD_RSVD2_MASK)
37933 /* PWD_SET Bit Fields */
37934 #define USBPHY_PWD_SET_RSVD0_MASK                0x3FFu
37935 #define USBPHY_PWD_SET_RSVD0_SHIFT               0
37936 #define USBPHY_PWD_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD0_SHIFT))&USBPHY_PWD_SET_RSVD0_MASK)
37937 #define USBPHY_PWD_SET_TXPWDFS_MASK              0x400u
37938 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             10
37939 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           0x800u
37940 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          11
37941 #define USBPHY_PWD_SET_TXPWDV2I_MASK             0x1000u
37942 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            12
37943 #define USBPHY_PWD_SET_RSVD1_MASK                0x1E000u
37944 #define USBPHY_PWD_SET_RSVD1_SHIFT               13
37945 #define USBPHY_PWD_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD1_SHIFT))&USBPHY_PWD_SET_RSVD1_MASK)
37946 #define USBPHY_PWD_SET_RXPWDENV_MASK             0x20000u
37947 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            17
37948 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            0x40000u
37949 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           18
37950 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            0x80000u
37951 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           19
37952 #define USBPHY_PWD_SET_RXPWDRX_MASK              0x100000u
37953 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             20
37954 #define USBPHY_PWD_SET_RSVD2_MASK                0xFFE00000u
37955 #define USBPHY_PWD_SET_RSVD2_SHIFT               21
37956 #define USBPHY_PWD_SET_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD2_SHIFT))&USBPHY_PWD_SET_RSVD2_MASK)
37957 /* PWD_CLR Bit Fields */
37958 #define USBPHY_PWD_CLR_RSVD0_MASK                0x3FFu
37959 #define USBPHY_PWD_CLR_RSVD0_SHIFT               0
37960 #define USBPHY_PWD_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD0_SHIFT))&USBPHY_PWD_CLR_RSVD0_MASK)
37961 #define USBPHY_PWD_CLR_TXPWDFS_MASK              0x400u
37962 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             10
37963 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           0x800u
37964 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          11
37965 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             0x1000u
37966 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            12
37967 #define USBPHY_PWD_CLR_RSVD1_MASK                0x1E000u
37968 #define USBPHY_PWD_CLR_RSVD1_SHIFT               13
37969 #define USBPHY_PWD_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD1_SHIFT))&USBPHY_PWD_CLR_RSVD1_MASK)
37970 #define USBPHY_PWD_CLR_RXPWDENV_MASK             0x20000u
37971 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            17
37972 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            0x40000u
37973 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           18
37974 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            0x80000u
37975 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           19
37976 #define USBPHY_PWD_CLR_RXPWDRX_MASK              0x100000u
37977 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             20
37978 #define USBPHY_PWD_CLR_RSVD2_MASK                0xFFE00000u
37979 #define USBPHY_PWD_CLR_RSVD2_SHIFT               21
37980 #define USBPHY_PWD_CLR_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD2_SHIFT))&USBPHY_PWD_CLR_RSVD2_MASK)
37981 /* PWD_TOG Bit Fields */
37982 #define USBPHY_PWD_TOG_RSVD0_MASK                0x3FFu
37983 #define USBPHY_PWD_TOG_RSVD0_SHIFT               0
37984 #define USBPHY_PWD_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD0_SHIFT))&USBPHY_PWD_TOG_RSVD0_MASK)
37985 #define USBPHY_PWD_TOG_TXPWDFS_MASK              0x400u
37986 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             10
37987 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           0x800u
37988 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          11
37989 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             0x1000u
37990 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            12
37991 #define USBPHY_PWD_TOG_RSVD1_MASK                0x1E000u
37992 #define USBPHY_PWD_TOG_RSVD1_SHIFT               13
37993 #define USBPHY_PWD_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD1_SHIFT))&USBPHY_PWD_TOG_RSVD1_MASK)
37994 #define USBPHY_PWD_TOG_RXPWDENV_MASK             0x20000u
37995 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            17
37996 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            0x40000u
37997 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           18
37998 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            0x80000u
37999 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           19
38000 #define USBPHY_PWD_TOG_RXPWDRX_MASK              0x100000u
38001 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             20
38002 #define USBPHY_PWD_TOG_RSVD2_MASK                0xFFE00000u
38003 #define USBPHY_PWD_TOG_RSVD2_SHIFT               21
38004 #define USBPHY_PWD_TOG_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD2_SHIFT))&USBPHY_PWD_TOG_RSVD2_MASK)
38005 /* TX Bit Fields */
38006 #define USBPHY_TX_D_CAL_MASK                     0xFu
38007 #define USBPHY_TX_D_CAL_SHIFT                    0
38008 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_D_CAL_SHIFT))&USBPHY_TX_D_CAL_MASK)
38009 #define USBPHY_TX_RSVD0_MASK                     0xF0u
38010 #define USBPHY_TX_RSVD0_SHIFT                    4
38011 #define USBPHY_TX_RSVD0(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD0_SHIFT))&USBPHY_TX_RSVD0_MASK)
38012 #define USBPHY_TX_TXCAL45DN_MASK                 0xF00u
38013 #define USBPHY_TX_TXCAL45DN_SHIFT                8
38014 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DN_SHIFT))&USBPHY_TX_TXCAL45DN_MASK)
38015 #define USBPHY_TX_RSVD1_MASK                     0xF000u
38016 #define USBPHY_TX_RSVD1_SHIFT                    12
38017 #define USBPHY_TX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD1_SHIFT))&USBPHY_TX_RSVD1_MASK)
38018 #define USBPHY_TX_TXCAL45DP_MASK                 0xF0000u
38019 #define USBPHY_TX_TXCAL45DP_SHIFT                16
38020 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DP_SHIFT))&USBPHY_TX_TXCAL45DP_MASK)
38021 #define USBPHY_TX_RSVD2_MASK                     0x3F00000u
38022 #define USBPHY_TX_RSVD2_SHIFT                    20
38023 #define USBPHY_TX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD2_SHIFT))&USBPHY_TX_RSVD2_MASK)
38024 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK        0x1C000000u
38025 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT       26
38026 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
38027 #define USBPHY_TX_RSVD5_MASK                     0xE0000000u
38028 #define USBPHY_TX_RSVD5_SHIFT                    29
38029 #define USBPHY_TX_RSVD5(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD5_SHIFT))&USBPHY_TX_RSVD5_MASK)
38030 /* TX_SET Bit Fields */
38031 #define USBPHY_TX_SET_D_CAL_MASK                 0xFu
38032 #define USBPHY_TX_SET_D_CAL_SHIFT                0
38033 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_D_CAL_SHIFT))&USBPHY_TX_SET_D_CAL_MASK)
38034 #define USBPHY_TX_SET_RSVD0_MASK                 0xF0u
38035 #define USBPHY_TX_SET_RSVD0_SHIFT                4
38036 #define USBPHY_TX_SET_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD0_SHIFT))&USBPHY_TX_SET_RSVD0_MASK)
38037 #define USBPHY_TX_SET_TXCAL45DN_MASK             0xF00u
38038 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            8
38039 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DN_SHIFT))&USBPHY_TX_SET_TXCAL45DN_MASK)
38040 #define USBPHY_TX_SET_RSVD1_MASK                 0xF000u
38041 #define USBPHY_TX_SET_RSVD1_SHIFT                12
38042 #define USBPHY_TX_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD1_SHIFT))&USBPHY_TX_SET_RSVD1_MASK)
38043 #define USBPHY_TX_SET_TXCAL45DP_MASK             0xF0000u
38044 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            16
38045 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DP_SHIFT))&USBPHY_TX_SET_TXCAL45DP_MASK)
38046 #define USBPHY_TX_SET_RSVD2_MASK                 0x3F00000u
38047 #define USBPHY_TX_SET_RSVD2_SHIFT                20
38048 #define USBPHY_TX_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD2_SHIFT))&USBPHY_TX_SET_RSVD2_MASK)
38049 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK    0x1C000000u
38050 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT   26
38051 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
38052 #define USBPHY_TX_SET_RSVD5_MASK                 0xE0000000u
38053 #define USBPHY_TX_SET_RSVD5_SHIFT                29
38054 #define USBPHY_TX_SET_RSVD5(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD5_SHIFT))&USBPHY_TX_SET_RSVD5_MASK)
38055 /* TX_CLR Bit Fields */
38056 #define USBPHY_TX_CLR_D_CAL_MASK                 0xFu
38057 #define USBPHY_TX_CLR_D_CAL_SHIFT                0
38058 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_D_CAL_SHIFT))&USBPHY_TX_CLR_D_CAL_MASK)
38059 #define USBPHY_TX_CLR_RSVD0_MASK                 0xF0u
38060 #define USBPHY_TX_CLR_RSVD0_SHIFT                4
38061 #define USBPHY_TX_CLR_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD0_SHIFT))&USBPHY_TX_CLR_RSVD0_MASK)
38062 #define USBPHY_TX_CLR_TXCAL45DN_MASK             0xF00u
38063 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            8
38064 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DN_SHIFT))&USBPHY_TX_CLR_TXCAL45DN_MASK)
38065 #define USBPHY_TX_CLR_RSVD1_MASK                 0xF000u
38066 #define USBPHY_TX_CLR_RSVD1_SHIFT                12
38067 #define USBPHY_TX_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD1_SHIFT))&USBPHY_TX_CLR_RSVD1_MASK)
38068 #define USBPHY_TX_CLR_TXCAL45DP_MASK             0xF0000u
38069 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            16
38070 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DP_SHIFT))&USBPHY_TX_CLR_TXCAL45DP_MASK)
38071 #define USBPHY_TX_CLR_RSVD2_MASK                 0x3F00000u
38072 #define USBPHY_TX_CLR_RSVD2_SHIFT                20
38073 #define USBPHY_TX_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD2_SHIFT))&USBPHY_TX_CLR_RSVD2_MASK)
38074 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK    0x1C000000u
38075 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT   26
38076 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
38077 #define USBPHY_TX_CLR_RSVD5_MASK                 0xE0000000u
38078 #define USBPHY_TX_CLR_RSVD5_SHIFT                29
38079 #define USBPHY_TX_CLR_RSVD5(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD5_SHIFT))&USBPHY_TX_CLR_RSVD5_MASK)
38080 /* TX_TOG Bit Fields */
38081 #define USBPHY_TX_TOG_D_CAL_MASK                 0xFu
38082 #define USBPHY_TX_TOG_D_CAL_SHIFT                0
38083 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_D_CAL_SHIFT))&USBPHY_TX_TOG_D_CAL_MASK)
38084 #define USBPHY_TX_TOG_RSVD0_MASK                 0xF0u
38085 #define USBPHY_TX_TOG_RSVD0_SHIFT                4
38086 #define USBPHY_TX_TOG_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD0_SHIFT))&USBPHY_TX_TOG_RSVD0_MASK)
38087 #define USBPHY_TX_TOG_TXCAL45DN_MASK             0xF00u
38088 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            8
38089 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DN_SHIFT))&USBPHY_TX_TOG_TXCAL45DN_MASK)
38090 #define USBPHY_TX_TOG_RSVD1_MASK                 0xF000u
38091 #define USBPHY_TX_TOG_RSVD1_SHIFT                12
38092 #define USBPHY_TX_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD1_SHIFT))&USBPHY_TX_TOG_RSVD1_MASK)
38093 #define USBPHY_TX_TOG_TXCAL45DP_MASK             0xF0000u
38094 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            16
38095 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DP_SHIFT))&USBPHY_TX_TOG_TXCAL45DP_MASK)
38096 #define USBPHY_TX_TOG_RSVD2_MASK                 0x3F00000u
38097 #define USBPHY_TX_TOG_RSVD2_SHIFT                20
38098 #define USBPHY_TX_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD2_SHIFT))&USBPHY_TX_TOG_RSVD2_MASK)
38099 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK    0x1C000000u
38100 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT   26
38101 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
38102 #define USBPHY_TX_TOG_RSVD5_MASK                 0xE0000000u
38103 #define USBPHY_TX_TOG_RSVD5_SHIFT                29
38104 #define USBPHY_TX_TOG_RSVD5(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD5_SHIFT))&USBPHY_TX_TOG_RSVD5_MASK)
38105 /* RX Bit Fields */
38106 #define USBPHY_RX_ENVADJ_MASK                    0x7u
38107 #define USBPHY_RX_ENVADJ_SHIFT                   0
38108 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_ENVADJ_SHIFT))&USBPHY_RX_ENVADJ_MASK)
38109 #define USBPHY_RX_RSVD0_MASK                     0x8u
38110 #define USBPHY_RX_RSVD0_SHIFT                    3
38111 #define USBPHY_RX_DISCONADJ_MASK                 0x70u
38112 #define USBPHY_RX_DISCONADJ_SHIFT                4
38113 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_DISCONADJ_SHIFT))&USBPHY_RX_DISCONADJ_MASK)
38114 #define USBPHY_RX_RSVD1_MASK                     0x3FFF80u
38115 #define USBPHY_RX_RSVD1_SHIFT                    7
38116 #define USBPHY_RX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD1_SHIFT))&USBPHY_RX_RSVD1_MASK)
38117 #define USBPHY_RX_RXDBYPASS_MASK                 0x400000u
38118 #define USBPHY_RX_RXDBYPASS_SHIFT                22
38119 #define USBPHY_RX_RSVD2_MASK                     0xFF800000u
38120 #define USBPHY_RX_RSVD2_SHIFT                    23
38121 #define USBPHY_RX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD2_SHIFT))&USBPHY_RX_RSVD2_MASK)
38122 /* RX_SET Bit Fields */
38123 #define USBPHY_RX_SET_ENVADJ_MASK                0x7u
38124 #define USBPHY_RX_SET_ENVADJ_SHIFT               0
38125 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_ENVADJ_SHIFT))&USBPHY_RX_SET_ENVADJ_MASK)
38126 #define USBPHY_RX_SET_RSVD0_MASK                 0x8u
38127 #define USBPHY_RX_SET_RSVD0_SHIFT                3
38128 #define USBPHY_RX_SET_DISCONADJ_MASK             0x70u
38129 #define USBPHY_RX_SET_DISCONADJ_SHIFT            4
38130 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_DISCONADJ_SHIFT))&USBPHY_RX_SET_DISCONADJ_MASK)
38131 #define USBPHY_RX_SET_RSVD1_MASK                 0x3FFF80u
38132 #define USBPHY_RX_SET_RSVD1_SHIFT                7
38133 #define USBPHY_RX_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD1_SHIFT))&USBPHY_RX_SET_RSVD1_MASK)
38134 #define USBPHY_RX_SET_RXDBYPASS_MASK             0x400000u
38135 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            22
38136 #define USBPHY_RX_SET_RSVD2_MASK                 0xFF800000u
38137 #define USBPHY_RX_SET_RSVD2_SHIFT                23
38138 #define USBPHY_RX_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD2_SHIFT))&USBPHY_RX_SET_RSVD2_MASK)
38139 /* RX_CLR Bit Fields */
38140 #define USBPHY_RX_CLR_ENVADJ_MASK                0x7u
38141 #define USBPHY_RX_CLR_ENVADJ_SHIFT               0
38142 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_ENVADJ_SHIFT))&USBPHY_RX_CLR_ENVADJ_MASK)
38143 #define USBPHY_RX_CLR_RSVD0_MASK                 0x8u
38144 #define USBPHY_RX_CLR_RSVD0_SHIFT                3
38145 #define USBPHY_RX_CLR_DISCONADJ_MASK             0x70u
38146 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            4
38147 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_DISCONADJ_SHIFT))&USBPHY_RX_CLR_DISCONADJ_MASK)
38148 #define USBPHY_RX_CLR_RSVD1_MASK                 0x3FFF80u
38149 #define USBPHY_RX_CLR_RSVD1_SHIFT                7
38150 #define USBPHY_RX_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD1_SHIFT))&USBPHY_RX_CLR_RSVD1_MASK)
38151 #define USBPHY_RX_CLR_RXDBYPASS_MASK             0x400000u
38152 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            22
38153 #define USBPHY_RX_CLR_RSVD2_MASK                 0xFF800000u
38154 #define USBPHY_RX_CLR_RSVD2_SHIFT                23
38155 #define USBPHY_RX_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD2_SHIFT))&USBPHY_RX_CLR_RSVD2_MASK)
38156 /* RX_TOG Bit Fields */
38157 #define USBPHY_RX_TOG_ENVADJ_MASK                0x7u
38158 #define USBPHY_RX_TOG_ENVADJ_SHIFT               0
38159 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_ENVADJ_SHIFT))&USBPHY_RX_TOG_ENVADJ_MASK)
38160 #define USBPHY_RX_TOG_RSVD0_MASK                 0x8u
38161 #define USBPHY_RX_TOG_RSVD0_SHIFT                3
38162 #define USBPHY_RX_TOG_DISCONADJ_MASK             0x70u
38163 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            4
38164 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_DISCONADJ_SHIFT))&USBPHY_RX_TOG_DISCONADJ_MASK)
38165 #define USBPHY_RX_TOG_RSVD1_MASK                 0x3FFF80u
38166 #define USBPHY_RX_TOG_RSVD1_SHIFT                7
38167 #define USBPHY_RX_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD1_SHIFT))&USBPHY_RX_TOG_RSVD1_MASK)
38168 #define USBPHY_RX_TOG_RXDBYPASS_MASK             0x400000u
38169 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            22
38170 #define USBPHY_RX_TOG_RSVD2_MASK                 0xFF800000u
38171 #define USBPHY_RX_TOG_RSVD2_SHIFT                23
38172 #define USBPHY_RX_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD2_SHIFT))&USBPHY_RX_TOG_RSVD2_MASK)
38173 /* CTRL Bit Fields */
38174 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        0x1u
38175 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       0
38176 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      0x2u
38177 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     1
38178 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         0x4u
38179 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        2
38180 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    0x8u
38181 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   3
38182 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       0x10u
38183 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      4
38184 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      0x20u
38185 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     5
38186 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          0x40u
38187 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         6
38188 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           0x80u
38189 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          7
38190 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         0x100u
38191 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        8
38192 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       0x200u
38193 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      9
38194 #define USBPHY_CTRL_RESUME_IRQ_MASK              0x400u
38195 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             10
38196 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          0x800u
38197 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         11
38198 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           0x1000u
38199 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          12
38200 #define USBPHY_CTRL_DATA_ON_LRADC_MASK           0x2000u
38201 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT          13
38202 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            0x4000u
38203 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           14
38204 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            0x8000u
38205 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           15
38206 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             0x10000u
38207 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            16
38208 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              0x20000u
38209 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             17
38210 #define USBPHY_CTRL_RSVD0_MASK                   0x40000u
38211 #define USBPHY_CTRL_RSVD0_SHIFT                  18
38212 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       0x80000u
38213 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      19
38214 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       0x100000u
38215 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      20
38216 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          0x200000u
38217 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         21
38218 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK            0x400000u
38219 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           22
38220 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          0x800000u
38221 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         23
38222 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            0x1000000u
38223 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           24
38224 #define USBPHY_CTRL_RSVD1_MASK                   0x6000000u
38225 #define USBPHY_CTRL_RSVD1_SHIFT                  25
38226 #define USBPHY_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_RSVD1_SHIFT))&USBPHY_CTRL_RSVD1_MASK)
38227 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            0x8000000u
38228 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           27
38229 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       0x10000000u
38230 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      28
38231 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           0x20000000u
38232 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          29
38233 #define USBPHY_CTRL_CLKGATE_MASK                 0x40000000u
38234 #define USBPHY_CTRL_CLKGATE_SHIFT                30
38235 #define USBPHY_CTRL_SFTRST_MASK                  0x80000000u
38236 #define USBPHY_CTRL_SFTRST_SHIFT                 31
38237 /* CTRL_SET Bit Fields */
38238 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    0x1u
38239 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   0
38240 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  0x2u
38241 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT 1
38242 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     0x4u
38243 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    2
38244 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK 0x8u
38245 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT 3
38246 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   0x10u
38247 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  4
38248 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  0x20u
38249 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT 5
38250 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      0x40u
38251 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     6
38252 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       0x80u
38253 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      7
38254 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     0x100u
38255 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    8
38256 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   0x200u
38257 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  9
38258 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          0x400u
38259 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         10
38260 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      0x800u
38261 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     11
38262 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       0x1000u
38263 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      12
38264 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK       0x2000u
38265 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT      13
38266 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        0x4000u
38267 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       14
38268 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        0x8000u
38269 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       15
38270 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         0x10000u
38271 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        16
38272 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          0x20000u
38273 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         17
38274 #define USBPHY_CTRL_SET_RSVD0_MASK               0x40000u
38275 #define USBPHY_CTRL_SET_RSVD0_SHIFT              18
38276 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   0x80000u
38277 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  19
38278 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   0x100000u
38279 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  20
38280 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      0x200000u
38281 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     21
38282 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        0x400000u
38283 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       22
38284 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      0x800000u
38285 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     23
38286 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        0x1000000u
38287 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       24
38288 #define USBPHY_CTRL_SET_RSVD1_MASK               0x6000000u
38289 #define USBPHY_CTRL_SET_RSVD1_SHIFT              25
38290 #define USBPHY_CTRL_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_SET_RSVD1_SHIFT))&USBPHY_CTRL_SET_RSVD1_MASK)
38291 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        0x8000000u
38292 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       27
38293 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   0x10000000u
38294 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  28
38295 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       0x20000000u
38296 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      29
38297 #define USBPHY_CTRL_SET_CLKGATE_MASK             0x40000000u
38298 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            30
38299 #define USBPHY_CTRL_SET_SFTRST_MASK              0x80000000u
38300 #define USBPHY_CTRL_SET_SFTRST_SHIFT             31
38301 /* CTRL_CLR Bit Fields */
38302 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    0x1u
38303 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   0
38304 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  0x2u
38305 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT 1
38306 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     0x4u
38307 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    2
38308 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK 0x8u
38309 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT 3
38310 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   0x10u
38311 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  4
38312 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  0x20u
38313 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT 5
38314 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      0x40u
38315 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     6
38316 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       0x80u
38317 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      7
38318 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     0x100u
38319 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    8
38320 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   0x200u
38321 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  9
38322 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          0x400u
38323 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         10
38324 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      0x800u
38325 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     11
38326 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       0x1000u
38327 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      12
38328 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK       0x2000u
38329 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT      13
38330 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        0x4000u
38331 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       14
38332 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        0x8000u
38333 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       15
38334 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         0x10000u
38335 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        16
38336 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          0x20000u
38337 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         17
38338 #define USBPHY_CTRL_CLR_RSVD0_MASK               0x40000u
38339 #define USBPHY_CTRL_CLR_RSVD0_SHIFT              18
38340 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   0x80000u
38341 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  19
38342 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   0x100000u
38343 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  20
38344 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      0x200000u
38345 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     21
38346 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        0x400000u
38347 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       22
38348 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      0x800000u
38349 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     23
38350 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        0x1000000u
38351 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       24
38352 #define USBPHY_CTRL_CLR_RSVD1_MASK               0x6000000u
38353 #define USBPHY_CTRL_CLR_RSVD1_SHIFT              25
38354 #define USBPHY_CTRL_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_CLR_RSVD1_SHIFT))&USBPHY_CTRL_CLR_RSVD1_MASK)
38355 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        0x8000000u
38356 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       27
38357 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   0x10000000u
38358 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  28
38359 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       0x20000000u
38360 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      29
38361 #define USBPHY_CTRL_CLR_CLKGATE_MASK             0x40000000u
38362 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            30
38363 #define USBPHY_CTRL_CLR_SFTRST_MASK              0x80000000u
38364 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             31
38365 /* CTRL_TOG Bit Fields */
38366 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    0x1u
38367 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   0
38368 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  0x2u
38369 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT 1
38370 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     0x4u
38371 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    2
38372 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK 0x8u
38373 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT 3
38374 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   0x10u
38375 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  4
38376 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  0x20u
38377 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT 5
38378 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      0x40u
38379 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     6
38380 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       0x80u
38381 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      7
38382 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     0x100u
38383 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    8
38384 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   0x200u
38385 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  9
38386 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          0x400u
38387 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         10
38388 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      0x800u
38389 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     11
38390 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       0x1000u
38391 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      12
38392 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK       0x2000u
38393 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT      13
38394 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        0x4000u
38395 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       14
38396 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        0x8000u
38397 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       15
38398 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         0x10000u
38399 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        16
38400 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          0x20000u
38401 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         17
38402 #define USBPHY_CTRL_TOG_RSVD0_MASK               0x40000u
38403 #define USBPHY_CTRL_TOG_RSVD0_SHIFT              18
38404 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   0x80000u
38405 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  19
38406 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   0x100000u
38407 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  20
38408 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      0x200000u
38409 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     21
38410 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        0x400000u
38411 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       22
38412 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      0x800000u
38413 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     23
38414 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        0x1000000u
38415 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       24
38416 #define USBPHY_CTRL_TOG_RSVD1_MASK               0x6000000u
38417 #define USBPHY_CTRL_TOG_RSVD1_SHIFT              25
38418 #define USBPHY_CTRL_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_TOG_RSVD1_SHIFT))&USBPHY_CTRL_TOG_RSVD1_MASK)
38419 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        0x8000000u
38420 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       27
38421 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   0x10000000u
38422 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  28
38423 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       0x20000000u
38424 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      29
38425 #define USBPHY_CTRL_TOG_CLKGATE_MASK             0x40000000u
38426 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            30
38427 #define USBPHY_CTRL_TOG_SFTRST_MASK              0x80000000u
38428 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             31
38429 /* STATUS Bit Fields */
38430 #define USBPHY_STATUS_RSVD0_MASK                 0x7u
38431 #define USBPHY_STATUS_RSVD0_SHIFT                0
38432 #define USBPHY_STATUS_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD0_SHIFT))&USBPHY_STATUS_RSVD0_MASK)
38433 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK 0x8u
38434 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT 3
38435 #define USBPHY_STATUS_RSVD1_MASK                 0x30u
38436 #define USBPHY_STATUS_RSVD1_SHIFT                4
38437 #define USBPHY_STATUS_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD1_SHIFT))&USBPHY_STATUS_RSVD1_MASK)
38438 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      0x40u
38439 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     6
38440 #define USBPHY_STATUS_RSVD2_MASK                 0x80u
38441 #define USBPHY_STATUS_RSVD2_SHIFT                7
38442 #define USBPHY_STATUS_OTGID_STATUS_MASK          0x100u
38443 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         8
38444 #define USBPHY_STATUS_RSVD3_MASK                 0x200u
38445 #define USBPHY_STATUS_RSVD3_SHIFT                9
38446 #define USBPHY_STATUS_RESUME_STATUS_MASK         0x400u
38447 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        10
38448 #define USBPHY_STATUS_RSVD4_MASK                 0xFFFFF800u
38449 #define USBPHY_STATUS_RSVD4_SHIFT                11
38450 #define USBPHY_STATUS_RSVD4(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD4_SHIFT))&USBPHY_STATUS_RSVD4_MASK)
38451 /* DEBUG Bit Fields */
38452 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           0x1u
38453 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          0
38454 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   0x2u
38455 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  1
38456 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            0xCu
38457 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           2
38458 #define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_HSTPULLDOWN_MASK)
38459 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          0x30u
38460 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         4
38461 #define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
38462 #define USBPHY_DEBUG_RSVD0_MASK                  0xC0u
38463 #define USBPHY_DEBUG_RSVD0_SHIFT                 6
38464 #define USBPHY_DEBUG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK)
38465 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             0xF00u
38466 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            8
38467 #define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TX2RXCOUNT_MASK)
38468 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           0x1000u
38469 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          12
38470 #define USBPHY_DEBUG_RSVD1_MASK                  0xE000u
38471 #define USBPHY_DEBUG_RSVD1_SHIFT                 13
38472 #define USBPHY_DEBUG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD1_SHIFT))&USBPHY_DEBUG_RSVD1_MASK)
38473 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      0x1F0000u
38474 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     16
38475 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
38476 #define USBPHY_DEBUG_RSVD2_MASK                  0xE00000u
38477 #define USBPHY_DEBUG_RSVD2_SHIFT                 21
38478 #define USBPHY_DEBUG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD2_SHIFT))&USBPHY_DEBUG_RSVD2_MASK)
38479 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         0x1000000u
38480 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        24
38481 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     0x1E000000u
38482 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    25
38483 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
38484 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      0x20000000u
38485 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     29
38486 #define USBPHY_DEBUG_CLKGATE_MASK                0x40000000u
38487 #define USBPHY_DEBUG_CLKGATE_SHIFT               30
38488 #define USBPHY_DEBUG_RSVD3_MASK                  0x80000000u
38489 #define USBPHY_DEBUG_RSVD3_SHIFT                 31
38490 /* DEBUG_SET Bit Fields */
38491 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       0x1u
38492 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      0
38493 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK 0x2u
38494 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT 1
38495 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        0xCu
38496 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       2
38497 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
38498 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      0x30u
38499 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     4
38500 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
38501 #define USBPHY_DEBUG_SET_RSVD0_MASK              0xC0u
38502 #define USBPHY_DEBUG_SET_RSVD0_SHIFT             6
38503 #define USBPHY_DEBUG_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD0_SHIFT))&USBPHY_DEBUG_SET_RSVD0_MASK)
38504 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         0xF00u
38505 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        8
38506 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
38507 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       0x1000u
38508 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      12
38509 #define USBPHY_DEBUG_SET_RSVD1_MASK              0xE000u
38510 #define USBPHY_DEBUG_SET_RSVD1_SHIFT             13
38511 #define USBPHY_DEBUG_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD1_SHIFT))&USBPHY_DEBUG_SET_RSVD1_MASK)
38512 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  0x1F0000u
38513 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT 16
38514 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
38515 #define USBPHY_DEBUG_SET_RSVD2_MASK              0xE00000u
38516 #define USBPHY_DEBUG_SET_RSVD2_SHIFT             21
38517 #define USBPHY_DEBUG_SET_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD2_SHIFT))&USBPHY_DEBUG_SET_RSVD2_MASK)
38518 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     0x1000000u
38519 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    24
38520 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK 0x1E000000u
38521 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT 25
38522 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
38523 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  0x20000000u
38524 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT 29
38525 #define USBPHY_DEBUG_SET_CLKGATE_MASK            0x40000000u
38526 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           30
38527 #define USBPHY_DEBUG_SET_RSVD3_MASK              0x80000000u
38528 #define USBPHY_DEBUG_SET_RSVD3_SHIFT             31
38529 /* DEBUG_CLR Bit Fields */
38530 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       0x1u
38531 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      0
38532 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK 0x2u
38533 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT 1
38534 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        0xCu
38535 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       2
38536 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
38537 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      0x30u
38538 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     4
38539 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
38540 #define USBPHY_DEBUG_CLR_RSVD0_MASK              0xC0u
38541 #define USBPHY_DEBUG_CLR_RSVD0_SHIFT             6
38542 #define USBPHY_DEBUG_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD0_SHIFT))&USBPHY_DEBUG_CLR_RSVD0_MASK)
38543 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         0xF00u
38544 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        8
38545 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
38546 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       0x1000u
38547 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      12
38548 #define USBPHY_DEBUG_CLR_RSVD1_MASK              0xE000u
38549 #define USBPHY_DEBUG_CLR_RSVD1_SHIFT             13
38550 #define USBPHY_DEBUG_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD1_SHIFT))&USBPHY_DEBUG_CLR_RSVD1_MASK)
38551 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  0x1F0000u
38552 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT 16
38553 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
38554 #define USBPHY_DEBUG_CLR_RSVD2_MASK              0xE00000u
38555 #define USBPHY_DEBUG_CLR_RSVD2_SHIFT             21
38556 #define USBPHY_DEBUG_CLR_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD2_SHIFT))&USBPHY_DEBUG_CLR_RSVD2_MASK)
38557 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     0x1000000u
38558 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    24
38559 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK 0x1E000000u
38560 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT 25
38561 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
38562 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  0x20000000u
38563 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT 29
38564 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            0x40000000u
38565 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           30
38566 #define USBPHY_DEBUG_CLR_RSVD3_MASK              0x80000000u
38567 #define USBPHY_DEBUG_CLR_RSVD3_SHIFT             31
38568 /* DEBUG_TOG Bit Fields */
38569 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       0x1u
38570 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      0
38571 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK 0x2u
38572 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT 1
38573 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        0xCu
38574 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       2
38575 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
38576 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      0x30u
38577 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     4
38578 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
38579 #define USBPHY_DEBUG_TOG_RSVD0_MASK              0xC0u
38580 #define USBPHY_DEBUG_TOG_RSVD0_SHIFT             6
38581 #define USBPHY_DEBUG_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD0_SHIFT))&USBPHY_DEBUG_TOG_RSVD0_MASK)
38582 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         0xF00u
38583 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        8
38584 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
38585 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       0x1000u
38586 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      12
38587 #define USBPHY_DEBUG_TOG_RSVD1_MASK              0xE000u
38588 #define USBPHY_DEBUG_TOG_RSVD1_SHIFT             13
38589 #define USBPHY_DEBUG_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD1_SHIFT))&USBPHY_DEBUG_TOG_RSVD1_MASK)
38590 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  0x1F0000u
38591 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT 16
38592 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
38593 #define USBPHY_DEBUG_TOG_RSVD2_MASK              0xE00000u
38594 #define USBPHY_DEBUG_TOG_RSVD2_SHIFT             21
38595 #define USBPHY_DEBUG_TOG_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD2_SHIFT))&USBPHY_DEBUG_TOG_RSVD2_MASK)
38596 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     0x1000000u
38597 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    24
38598 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK 0x1E000000u
38599 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT 25
38600 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
38601 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  0x20000000u
38602 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT 29
38603 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            0x40000000u
38604 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           30
38605 #define USBPHY_DEBUG_TOG_RSVD3_MASK              0x80000000u
38606 #define USBPHY_DEBUG_TOG_RSVD3_SHIFT             31
38607 /* DEBUG0_STATUS Bit Fields */
38608 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK 0xFFFFu
38609 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT 0
38610 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
38611 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK 0x3FF0000u
38612 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT 16
38613 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
38614 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  0xFC000000u
38615 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT 26
38616 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
38617 /* DEBUG1 Bit Fields */
38618 #define USBPHY_DEBUG1_RSVD0_MASK                 0x1FFFu
38619 #define USBPHY_DEBUG1_RSVD0_SHIFT                0
38620 #define USBPHY_DEBUG1_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD0_SHIFT))&USBPHY_DEBUG1_RSVD0_MASK)
38621 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           0x6000u
38622 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          13
38623 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_ENTAILADJVD_MASK)
38624 #define USBPHY_DEBUG1_RSVD1_MASK                 0xFFFF8000u
38625 #define USBPHY_DEBUG1_RSVD1_SHIFT                15
38626 #define USBPHY_DEBUG1_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD1_SHIFT))&USBPHY_DEBUG1_RSVD1_MASK)
38627 /* DEBUG1_SET Bit Fields */
38628 #define USBPHY_DEBUG1_SET_RSVD0_MASK             0x1FFFu
38629 #define USBPHY_DEBUG1_SET_RSVD0_SHIFT            0
38630 #define USBPHY_DEBUG1_SET_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD0_SHIFT))&USBPHY_DEBUG1_SET_RSVD0_MASK)
38631 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       0x6000u
38632 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      13
38633 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
38634 #define USBPHY_DEBUG1_SET_RSVD1_MASK             0xFFFF8000u
38635 #define USBPHY_DEBUG1_SET_RSVD1_SHIFT            15
38636 #define USBPHY_DEBUG1_SET_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD1_SHIFT))&USBPHY_DEBUG1_SET_RSVD1_MASK)
38637 /* DEBUG1_CLR Bit Fields */
38638 #define USBPHY_DEBUG1_CLR_RSVD0_MASK             0x1FFFu
38639 #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT            0
38640 #define USBPHY_DEBUG1_CLR_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD0_SHIFT))&USBPHY_DEBUG1_CLR_RSVD0_MASK)
38641 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       0x6000u
38642 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      13
38643 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
38644 #define USBPHY_DEBUG1_CLR_RSVD1_MASK             0xFFFF8000u
38645 #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT            15
38646 #define USBPHY_DEBUG1_CLR_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD1_SHIFT))&USBPHY_DEBUG1_CLR_RSVD1_MASK)
38647 /* DEBUG1_TOG Bit Fields */
38648 #define USBPHY_DEBUG1_TOG_RSVD0_MASK             0x1FFFu
38649 #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT            0
38650 #define USBPHY_DEBUG1_TOG_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD0_SHIFT))&USBPHY_DEBUG1_TOG_RSVD0_MASK)
38651 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       0x6000u
38652 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      13
38653 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
38654 #define USBPHY_DEBUG1_TOG_RSVD1_MASK             0xFFFF8000u
38655 #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT            15
38656 #define USBPHY_DEBUG1_TOG_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD1_SHIFT))&USBPHY_DEBUG1_TOG_RSVD1_MASK)
38657 /* VERSION Bit Fields */
38658 #define USBPHY_VERSION_STEP_MASK                 0xFFFFu
38659 #define USBPHY_VERSION_STEP_SHIFT                0
38660 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_STEP_SHIFT))&USBPHY_VERSION_STEP_MASK)
38661 #define USBPHY_VERSION_MINOR_MASK                0xFF0000u
38662 #define USBPHY_VERSION_MINOR_SHIFT               16
38663 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MINOR_SHIFT))&USBPHY_VERSION_MINOR_MASK)
38664 #define USBPHY_VERSION_MAJOR_MASK                0xFF000000u
38665 #define USBPHY_VERSION_MAJOR_SHIFT               24
38666 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MAJOR_SHIFT))&USBPHY_VERSION_MAJOR_MASK)
38667 
38668 /*!
38669  * @}
38670  */ /* end of group USBPHY_Register_Masks */
38671 
38672 /* USBPHY - Peripheral instance base addresses */
38673 /** Peripheral USBPHY1 base address */
38674 #define USBPHY1_BASE                             (0x420C9000u)
38675 /** Peripheral USBPHY1 base pointer */
38676 #define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
38677 #define USBPHY1_BASE_PTR                         (USBPHY1)
38678 /** Peripheral USBPHY2 base address */
38679 #define USBPHY2_BASE                             (0x420CA000u)
38680 /** Peripheral USBPHY2 base pointer */
38681 #define USBPHY2                                  ((USBPHY_Type *)USBPHY2_BASE)
38682 #define USBPHY2_BASE_PTR                         (USBPHY2)
38683 /** Array initializer of USBPHY peripheral base addresses */
38684 #define USBPHY_BASE_ADDRS                        { USBPHY1_BASE, USBPHY2_BASE }
38685 /** Array initializer of USBPHY peripheral base pointers */
38686 #define USBPHY_BASE_PTRS                         { USBPHY1, USBPHY2 }
38687 
38688 /* ----------------------------------------------------------------------------
38689    -- USBPHY - Register accessor macros
38690    ---------------------------------------------------------------------------- */
38691 
38692 /*!
38693  * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros
38694  * @{
38695  */
38696 
38697 /* USBPHY - Register instance definitions */
38698 /* USBPHY1 */
38699 #define USBPHY1_PWD                              USBPHY_PWD_REG(USBPHY1_BASE_PTR)
38700 #define USBPHY1_PWD_SET                          USBPHY_PWD_SET_REG(USBPHY1_BASE_PTR)
38701 #define USBPHY1_PWD_CLR                          USBPHY_PWD_CLR_REG(USBPHY1_BASE_PTR)
38702 #define USBPHY1_PWD_TOG                          USBPHY_PWD_TOG_REG(USBPHY1_BASE_PTR)
38703 #define USBPHY1_TX                               USBPHY_TX_REG(USBPHY1_BASE_PTR)
38704 #define USBPHY1_TX_SET                           USBPHY_TX_SET_REG(USBPHY1_BASE_PTR)
38705 #define USBPHY1_TX_CLR                           USBPHY_TX_CLR_REG(USBPHY1_BASE_PTR)
38706 #define USBPHY1_TX_TOG                           USBPHY_TX_TOG_REG(USBPHY1_BASE_PTR)
38707 #define USBPHY1_RX                               USBPHY_RX_REG(USBPHY1_BASE_PTR)
38708 #define USBPHY1_RX_SET                           USBPHY_RX_SET_REG(USBPHY1_BASE_PTR)
38709 #define USBPHY1_RX_CLR                           USBPHY_RX_CLR_REG(USBPHY1_BASE_PTR)
38710 #define USBPHY1_RX_TOG                           USBPHY_RX_TOG_REG(USBPHY1_BASE_PTR)
38711 #define USBPHY1_CTRL                             USBPHY_CTRL_REG(USBPHY1_BASE_PTR)
38712 #define USBPHY1_CTRL_SET                         USBPHY_CTRL_SET_REG(USBPHY1_BASE_PTR)
38713 #define USBPHY1_CTRL_CLR                         USBPHY_CTRL_CLR_REG(USBPHY1_BASE_PTR)
38714 #define USBPHY1_CTRL_TOG                         USBPHY_CTRL_TOG_REG(USBPHY1_BASE_PTR)
38715 #define USBPHY1_STATUS                           USBPHY_STATUS_REG(USBPHY1_BASE_PTR)
38716 #define USBPHY1_DEBUG                            USBPHY_DEBUG_REG(USBPHY1_BASE_PTR)
38717 #define USBPHY1_DEBUG_SET                        USBPHY_DEBUG_SET_REG(USBPHY1_BASE_PTR)
38718 #define USBPHY1_DEBUG_CLR                        USBPHY_DEBUG_CLR_REG(USBPHY1_BASE_PTR)
38719 #define USBPHY1_DEBUG_TOG                        USBPHY_DEBUG_TOG_REG(USBPHY1_BASE_PTR)
38720 #define USBPHY1_DEBUG0_STATUS                    USBPHY_DEBUG0_STATUS_REG(USBPHY1_BASE_PTR)
38721 #define USBPHY1_DEBUG1                           USBPHY_DEBUG1_REG(USBPHY1_BASE_PTR)
38722 #define USBPHY1_DEBUG1_SET                       USBPHY_DEBUG1_SET_REG(USBPHY1_BASE_PTR)
38723 #define USBPHY1_DEBUG1_CLR                       USBPHY_DEBUG1_CLR_REG(USBPHY1_BASE_PTR)
38724 #define USBPHY1_DEBUG1_TOG                       USBPHY_DEBUG1_TOG_REG(USBPHY1_BASE_PTR)
38725 #define USBPHY1_VERSION                          USBPHY_VERSION_REG(USBPHY1_BASE_PTR)
38726 /* USBPHY2 */
38727 #define USBPHY2_PWD                              USBPHY_PWD_REG(USBPHY2_BASE_PTR)
38728 #define USBPHY2_PWD_SET                          USBPHY_PWD_SET_REG(USBPHY2_BASE_PTR)
38729 #define USBPHY2_PWD_CLR                          USBPHY_PWD_CLR_REG(USBPHY2_BASE_PTR)
38730 #define USBPHY2_PWD_TOG                          USBPHY_PWD_TOG_REG(USBPHY2_BASE_PTR)
38731 #define USBPHY2_TX                               USBPHY_TX_REG(USBPHY2_BASE_PTR)
38732 #define USBPHY2_TX_SET                           USBPHY_TX_SET_REG(USBPHY2_BASE_PTR)
38733 #define USBPHY2_TX_CLR                           USBPHY_TX_CLR_REG(USBPHY2_BASE_PTR)
38734 #define USBPHY2_TX_TOG                           USBPHY_TX_TOG_REG(USBPHY2_BASE_PTR)
38735 #define USBPHY2_RX                               USBPHY_RX_REG(USBPHY2_BASE_PTR)
38736 #define USBPHY2_RX_SET                           USBPHY_RX_SET_REG(USBPHY2_BASE_PTR)
38737 #define USBPHY2_RX_CLR                           USBPHY_RX_CLR_REG(USBPHY2_BASE_PTR)
38738 #define USBPHY2_RX_TOG                           USBPHY_RX_TOG_REG(USBPHY2_BASE_PTR)
38739 #define USBPHY2_CTRL                             USBPHY_CTRL_REG(USBPHY2_BASE_PTR)
38740 #define USBPHY2_CTRL_SET                         USBPHY_CTRL_SET_REG(USBPHY2_BASE_PTR)
38741 #define USBPHY2_CTRL_CLR                         USBPHY_CTRL_CLR_REG(USBPHY2_BASE_PTR)
38742 #define USBPHY2_CTRL_TOG                         USBPHY_CTRL_TOG_REG(USBPHY2_BASE_PTR)
38743 #define USBPHY2_STATUS                           USBPHY_STATUS_REG(USBPHY2_BASE_PTR)
38744 #define USBPHY2_DEBUG                            USBPHY_DEBUG_REG(USBPHY2_BASE_PTR)
38745 #define USBPHY2_DEBUG_SET                        USBPHY_DEBUG_SET_REG(USBPHY2_BASE_PTR)
38746 #define USBPHY2_DEBUG_CLR                        USBPHY_DEBUG_CLR_REG(USBPHY2_BASE_PTR)
38747 #define USBPHY2_DEBUG_TOG                        USBPHY_DEBUG_TOG_REG(USBPHY2_BASE_PTR)
38748 #define USBPHY2_DEBUG0_STATUS                    USBPHY_DEBUG0_STATUS_REG(USBPHY2_BASE_PTR)
38749 #define USBPHY2_DEBUG1                           USBPHY_DEBUG1_REG(USBPHY2_BASE_PTR)
38750 #define USBPHY2_DEBUG1_SET                       USBPHY_DEBUG1_SET_REG(USBPHY2_BASE_PTR)
38751 #define USBPHY2_DEBUG1_CLR                       USBPHY_DEBUG1_CLR_REG(USBPHY2_BASE_PTR)
38752 #define USBPHY2_DEBUG1_TOG                       USBPHY_DEBUG1_TOG_REG(USBPHY2_BASE_PTR)
38753 #define USBPHY2_VERSION                          USBPHY_VERSION_REG(USBPHY2_BASE_PTR)
38754 
38755 /*!
38756  * @}
38757  */ /* end of group USBPHY_Register_Accessor_Macros */
38758 
38759 /*!
38760  * @}
38761  */ /* end of group USBPHY_Peripheral */
38762 
38763 /* ----------------------------------------------------------------------------
38764    -- USB_ANALOG Peripheral Access Layer
38765    ---------------------------------------------------------------------------- */
38766 
38767 /*!
38768  * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
38769  * @{
38770  */
38771 
38772 /** USB_ANALOG - Register Layout Typedef */
38773 typedef struct {
38774   uint8_t RESERVED_0[416];
38775   __IO  uint32_t USB1_VBUS_DETECT;                       /**< USB VBUS Detect Register, offset: 0x1A0 */
38776   __IO  uint32_t USB1_VBUS_DETECT_SET;                   /**< USB VBUS Detect Register, offset: 0x1A4 */
38777   __IO  uint32_t USB1_VBUS_DETECT_CLR;                   /**< USB VBUS Detect Register, offset: 0x1A8 */
38778   __IO  uint32_t USB1_VBUS_DETECT_TOG;                   /**< USB VBUS Detect Register, offset: 0x1AC */
38779   __IO  uint32_t USB1_CHRG_DETECT;                       /**< USB Charger Detect Register, offset: 0x1B0 */
38780   __IO  uint32_t USB1_CHRG_DETECT_SET;                   /**< USB Charger Detect Register, offset: 0x1B4 */
38781   __IO  uint32_t USB1_CHRG_DETECT_CLR;                   /**< USB Charger Detect Register, offset: 0x1B8 */
38782   __IO  uint32_t USB1_CHRG_DETECT_TOG;                   /**< USB Charger Detect Register, offset: 0x1BC */
38783   __I   uint32_t USB1_VBUS_DETECT_STAT;                  /**< USB VBUS Detect Status Register, offset: 0x1C0 */
38784   uint8_t RESERVED_1[12];
38785   __I   uint32_t USB1_CHRG_DETECT_STAT;                  /**< USB Charger Detect Status Register, offset: 0x1D0 */
38786   uint8_t RESERVED_2[28];
38787   __IO  uint32_t USB1_MISC;                              /**< USB Misc Register, offset: 0x1F0 */
38788   __IO  uint32_t USB1_MISC_SET;                          /**< USB Misc Register, offset: 0x1F4 */
38789   __IO  uint32_t USB1_MISC_CLR;                          /**< USB Misc Register, offset: 0x1F8 */
38790   __IO  uint32_t USB1_MISC_TOG;                          /**< USB Misc Register, offset: 0x1FC */
38791   __IO  uint32_t USB2_VBUS_DETECT;                       /**< USB VBUS Detect Register, offset: 0x200 */
38792   __IO  uint32_t USB2_VBUS_DETECT_SET;                   /**< USB VBUS Detect Register, offset: 0x204 */
38793   __IO  uint32_t USB2_VBUS_DETECT_CLR;                   /**< USB VBUS Detect Register, offset: 0x208 */
38794   __IO  uint32_t USB2_VBUS_DETECT_TOG;                   /**< USB VBUS Detect Register, offset: 0x20C */
38795   __IO  uint32_t USB2_CHRG_DETECT;                       /**< USB Charger Detect Register, offset: 0x210 */
38796   __IO  uint32_t USB2_CHRG_DETECT_SET;                   /**< USB Charger Detect Register, offset: 0x214 */
38797   __IO  uint32_t USB2_CHRG_DETECT_CLR;                   /**< USB Charger Detect Register, offset: 0x218 */
38798   __IO  uint32_t USB2_CHRG_DETECT_TOG;                   /**< USB Charger Detect Register, offset: 0x21C */
38799   __I   uint32_t USB2_VBUS_DETECT_STAT;                  /**< USB VBUS Detect Status Register, offset: 0x220 */
38800   uint8_t RESERVED_3[12];
38801   __I   uint32_t USB2_CHRG_DETECT_STAT;                  /**< USB Charger Detect Status Register, offset: 0x230 */
38802   uint8_t RESERVED_4[28];
38803   __IO  uint32_t USB2_MISC;                              /**< USB Misc Register, offset: 0x250 */
38804   __IO  uint32_t USB2_MISC_SET;                          /**< USB Misc Register, offset: 0x254 */
38805   __IO  uint32_t USB2_MISC_CLR;                          /**< USB Misc Register, offset: 0x258 */
38806   __IO  uint32_t USB2_MISC_TOG;                          /**< USB Misc Register, offset: 0x25C */
38807   __I   uint32_t DIGPROG;                                /**< Chip Silicon Version, offset: 0x260 */
38808 } USB_ANALOG_Type, *USB_ANALOG_MemMapPtr;
38809 
38810 /* ----------------------------------------------------------------------------
38811    -- USB_ANALOG - Register accessor macros
38812    ---------------------------------------------------------------------------- */
38813 
38814 /*!
38815  * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros
38816  * @{
38817  */
38818 
38819 /* USB_ANALOG - Register accessors */
38820 #define USB_ANALOG_USB1_VBUS_DETECT_REG(base)    ((base)->USB1_VBUS_DETECT)
38821 #define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET)
38822 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR)
38823 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG)
38824 #define USB_ANALOG_USB1_CHRG_DETECT_REG(base)    ((base)->USB1_CHRG_DETECT)
38825 #define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET)
38826 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR)
38827 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG)
38828 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT)
38829 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT)
38830 #define USB_ANALOG_USB1_MISC_REG(base)           ((base)->USB1_MISC)
38831 #define USB_ANALOG_USB1_MISC_SET_REG(base)       ((base)->USB1_MISC_SET)
38832 #define USB_ANALOG_USB1_MISC_CLR_REG(base)       ((base)->USB1_MISC_CLR)
38833 #define USB_ANALOG_USB1_MISC_TOG_REG(base)       ((base)->USB1_MISC_TOG)
38834 #define USB_ANALOG_USB2_VBUS_DETECT_REG(base)    ((base)->USB2_VBUS_DETECT)
38835 #define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET)
38836 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR)
38837 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG)
38838 #define USB_ANALOG_USB2_CHRG_DETECT_REG(base)    ((base)->USB2_CHRG_DETECT)
38839 #define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET)
38840 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR)
38841 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG)
38842 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT)
38843 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT)
38844 #define USB_ANALOG_USB2_MISC_REG(base)           ((base)->USB2_MISC)
38845 #define USB_ANALOG_USB2_MISC_SET_REG(base)       ((base)->USB2_MISC_SET)
38846 #define USB_ANALOG_USB2_MISC_CLR_REG(base)       ((base)->USB2_MISC_CLR)
38847 #define USB_ANALOG_USB2_MISC_TOG_REG(base)       ((base)->USB2_MISC_TOG)
38848 #define USB_ANALOG_DIGPROG_REG(base)             ((base)->DIGPROG)
38849 
38850 /*!
38851  * @}
38852  */ /* end of group USB_ANALOG_Register_Accessor_Macros */
38853 
38854 /* ----------------------------------------------------------------------------
38855    -- USB_ANALOG Register Masks
38856    ---------------------------------------------------------------------------- */
38857 
38858 /*!
38859  * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
38860  * @{
38861  */
38862 
38863 /* USB1_VBUS_DETECT Bit Fields */
38864 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u
38865 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0
38866 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
38867 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38868 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20
38869 #define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u
38870 #define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26
38871 #define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u
38872 #define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_SHIFT 27
38873 /* USB1_VBUS_DETECT_SET Bit Fields */
38874 #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u
38875 #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0
38876 #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
38877 #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38878 #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20
38879 #define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u
38880 #define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26
38881 #define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u
38882 #define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27
38883 /* USB1_VBUS_DETECT_CLR Bit Fields */
38884 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u
38885 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0
38886 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
38887 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38888 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20
38889 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u
38890 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26
38891 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u
38892 #define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27
38893 /* USB1_VBUS_DETECT_TOG Bit Fields */
38894 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u
38895 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0
38896 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
38897 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38898 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20
38899 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u
38900 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26
38901 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u
38902 #define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27
38903 /* USB1_CHRG_DETECT Bit Fields */
38904 #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u
38905 #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT 18
38906 #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u
38907 #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT 19
38908 #define USB_ANALOG_USB1_CHRG_DETECT_EN_B_MASK    0x100000u
38909 #define USB_ANALOG_USB1_CHRG_DETECT_EN_B_SHIFT   20
38910 /* USB1_CHRG_DETECT_SET Bit Fields */
38911 #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u
38912 #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18
38913 #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u
38914 #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19
38915 #define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_MASK 0x100000u
38916 #define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_SHIFT 20
38917 /* USB1_CHRG_DETECT_CLR Bit Fields */
38918 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u
38919 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18
38920 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u
38921 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19
38922 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_MASK 0x100000u
38923 #define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_SHIFT 20
38924 /* USB1_CHRG_DETECT_TOG Bit Fields */
38925 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u
38926 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18
38927 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u
38928 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19
38929 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_MASK 0x100000u
38930 #define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_SHIFT 20
38931 /* USB1_VBUS_DETECT_STAT Bit Fields */
38932 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_MASK 0x1u
38933 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_SHIFT 0
38934 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_MASK 0x2u
38935 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_SHIFT 1
38936 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_MASK 0x4u
38937 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_SHIFT 2
38938 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u
38939 #define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3
38940 /* USB1_CHRG_DETECT_STAT Bit Fields */
38941 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u
38942 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0
38943 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u
38944 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1
38945 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u
38946 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_SHIFT 2
38947 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u
38948 #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_SHIFT 3
38949 /* USB1_MISC Bit Fields */
38950 #define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_MASK 0x1u
38951 #define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_SHIFT 0
38952 #define USB_ANALOG_USB1_MISC_EN_DEGLITCH_MASK    0x2u
38953 #define USB_ANALOG_USB1_MISC_EN_DEGLITCH_SHIFT   1
38954 #define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_MASK    0x40000000u
38955 #define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_SHIFT   30
38956 /* USB1_MISC_SET Bit Fields */
38957 #define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u
38958 #define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0
38959 #define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_MASK 0x2u
38960 #define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_SHIFT 1
38961 #define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u
38962 #define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_SHIFT 30
38963 /* USB1_MISC_CLR Bit Fields */
38964 #define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u
38965 #define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0
38966 #define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_MASK 0x2u
38967 #define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_SHIFT 1
38968 #define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u
38969 #define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_SHIFT 30
38970 /* USB1_MISC_TOG Bit Fields */
38971 #define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u
38972 #define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0
38973 #define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_MASK 0x2u
38974 #define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_SHIFT 1
38975 #define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u
38976 #define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_SHIFT 30
38977 /* USB2_VBUS_DETECT Bit Fields */
38978 #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u
38979 #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0
38980 #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK)
38981 #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38982 #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20
38983 #define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u
38984 #define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26
38985 #define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u
38986 #define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_SHIFT 27
38987 /* USB2_VBUS_DETECT_SET Bit Fields */
38988 #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u
38989 #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0
38990 #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
38991 #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
38992 #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20
38993 #define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u
38994 #define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26
38995 #define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u
38996 #define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27
38997 /* USB2_VBUS_DETECT_CLR Bit Fields */
38998 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u
38999 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0
39000 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
39001 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
39002 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20
39003 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u
39004 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26
39005 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u
39006 #define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27
39007 /* USB2_VBUS_DETECT_TOG Bit Fields */
39008 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u
39009 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0
39010 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
39011 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
39012 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20
39013 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u
39014 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26
39015 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u
39016 #define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27
39017 /* USB2_CHRG_DETECT Bit Fields */
39018 #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u
39019 #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_SHIFT 18
39020 #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u
39021 #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_SHIFT 19
39022 #define USB_ANALOG_USB2_CHRG_DETECT_EN_B_MASK    0x100000u
39023 #define USB_ANALOG_USB2_CHRG_DETECT_EN_B_SHIFT   20
39024 /* USB2_CHRG_DETECT_SET Bit Fields */
39025 #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u
39026 #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18
39027 #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u
39028 #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19
39029 #define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_MASK 0x100000u
39030 #define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_SHIFT 20
39031 /* USB2_CHRG_DETECT_CLR Bit Fields */
39032 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u
39033 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18
39034 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u
39035 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19
39036 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_MASK 0x100000u
39037 #define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_SHIFT 20
39038 /* USB2_CHRG_DETECT_TOG Bit Fields */
39039 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u
39040 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18
39041 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u
39042 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19
39043 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_MASK 0x100000u
39044 #define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_SHIFT 20
39045 /* USB2_VBUS_DETECT_STAT Bit Fields */
39046 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_MASK 0x1u
39047 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_SHIFT 0
39048 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_MASK 0x2u
39049 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_SHIFT 1
39050 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_MASK 0x4u
39051 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_SHIFT 2
39052 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u
39053 #define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3
39054 /* USB2_CHRG_DETECT_STAT Bit Fields */
39055 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u
39056 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0
39057 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u
39058 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1
39059 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u
39060 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_SHIFT 2
39061 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u
39062 #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_SHIFT 3
39063 /* USB2_MISC Bit Fields */
39064 #define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_MASK 0x1u
39065 #define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_SHIFT 0
39066 #define USB_ANALOG_USB2_MISC_EN_DEGLITCH_MASK    0x2u
39067 #define USB_ANALOG_USB2_MISC_EN_DEGLITCH_SHIFT   1
39068 #define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_MASK    0x40000000u
39069 #define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_SHIFT   30
39070 /* USB2_MISC_SET Bit Fields */
39071 #define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u
39072 #define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0
39073 #define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_MASK 0x2u
39074 #define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_SHIFT 1
39075 #define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u
39076 #define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_SHIFT 30
39077 /* USB2_MISC_CLR Bit Fields */
39078 #define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u
39079 #define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0
39080 #define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_MASK 0x2u
39081 #define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_SHIFT 1
39082 #define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u
39083 #define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_SHIFT 30
39084 /* USB2_MISC_TOG Bit Fields */
39085 #define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u
39086 #define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0
39087 #define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_MASK 0x2u
39088 #define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_SHIFT 1
39089 #define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u
39090 #define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_SHIFT 30
39091 /* DIGPROG Bit Fields */
39092 #define USB_ANALOG_DIGPROG_MINOR_MASK            0xFFu
39093 #define USB_ANALOG_DIGPROG_MINOR_SHIFT           0
39094 #define USB_ANALOG_DIGPROG_MINOR(x)              (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MINOR_SHIFT))&USB_ANALOG_DIGPROG_MINOR_MASK)
39095 #define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK      0xFF00u
39096 #define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT     8
39097 #define USB_ANALOG_DIGPROG_MAJOR_LOWER(x)        (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK)
39098 #define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK      0xFF0000u
39099 #define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT     16
39100 #define USB_ANALOG_DIGPROG_MAJOR_UPPER(x)        (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK)
39101 
39102 /*!
39103  * @}
39104  */ /* end of group USB_ANALOG_Register_Masks */
39105 
39106 /* USB_ANALOG - Peripheral instance base addresses */
39107 /** Peripheral USB_ANALOG base address */
39108 #define USB_ANALOG_BASE                          (0x420C8000u)
39109 /** Peripheral USB_ANALOG base pointer */
39110 #define USB_ANALOG                               ((USB_ANALOG_Type *)USB_ANALOG_BASE)
39111 #define USB_ANALOG_BASE_PTR                      (USB_ANALOG)
39112 /** Array initializer of USB_ANALOG peripheral base addresses */
39113 #define USB_ANALOG_BASE_ADDRS                    { USB_ANALOG_BASE }
39114 /** Array initializer of USB_ANALOG peripheral base pointers */
39115 #define USB_ANALOG_BASE_PTRS                     { USB_ANALOG }
39116 
39117 /* ----------------------------------------------------------------------------
39118    -- USB_ANALOG - Register accessor macros
39119    ---------------------------------------------------------------------------- */
39120 
39121 /*!
39122  * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros
39123  * @{
39124  */
39125 
39126 /* USB_ANALOG - Register instance definitions */
39127 /* USB_ANALOG */
39128 #define USB_ANALOG_USB1_VBUS_DETECT              USB_ANALOG_USB1_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR)
39129 #define USB_ANALOG_USB1_VBUS_DETECT_SET          USB_ANALOG_USB1_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR)
39130 #define USB_ANALOG_USB1_VBUS_DETECT_CLR          USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR)
39131 #define USB_ANALOG_USB1_VBUS_DETECT_TOG          USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR)
39132 #define USB_ANALOG_USB1_CHRG_DETECT              USB_ANALOG_USB1_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR)
39133 #define USB_ANALOG_USB1_CHRG_DETECT_SET          USB_ANALOG_USB1_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR)
39134 #define USB_ANALOG_USB1_CHRG_DETECT_CLR          USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR)
39135 #define USB_ANALOG_USB1_CHRG_DETECT_TOG          USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR)
39136 #define USB_ANALOG_USB1_VBUS_DETECT_STAT         USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR)
39137 #define USB_ANALOG_USB1_CHRG_DETECT_STAT         USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR)
39138 #define USB_ANALOG_USB1_MISC                     USB_ANALOG_USB1_MISC_REG(USB_ANALOG_BASE_PTR)
39139 #define USB_ANALOG_USB1_MISC_SET                 USB_ANALOG_USB1_MISC_SET_REG(USB_ANALOG_BASE_PTR)
39140 #define USB_ANALOG_USB1_MISC_CLR                 USB_ANALOG_USB1_MISC_CLR_REG(USB_ANALOG_BASE_PTR)
39141 #define USB_ANALOG_USB1_MISC_TOG                 USB_ANALOG_USB1_MISC_TOG_REG(USB_ANALOG_BASE_PTR)
39142 #define USB_ANALOG_USB2_VBUS_DETECT              USB_ANALOG_USB2_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR)
39143 #define USB_ANALOG_USB2_VBUS_DETECT_SET          USB_ANALOG_USB2_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR)
39144 #define USB_ANALOG_USB2_VBUS_DETECT_CLR          USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR)
39145 #define USB_ANALOG_USB2_VBUS_DETECT_TOG          USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR)
39146 #define USB_ANALOG_USB2_CHRG_DETECT              USB_ANALOG_USB2_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR)
39147 #define USB_ANALOG_USB2_CHRG_DETECT_SET          USB_ANALOG_USB2_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR)
39148 #define USB_ANALOG_USB2_CHRG_DETECT_CLR          USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR)
39149 #define USB_ANALOG_USB2_CHRG_DETECT_TOG          USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR)
39150 #define USB_ANALOG_USB2_VBUS_DETECT_STAT         USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR)
39151 #define USB_ANALOG_USB2_CHRG_DETECT_STAT         USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR)
39152 #define USB_ANALOG_USB2_MISC                     USB_ANALOG_USB2_MISC_REG(USB_ANALOG_BASE_PTR)
39153 #define USB_ANALOG_USB2_MISC_SET                 USB_ANALOG_USB2_MISC_SET_REG(USB_ANALOG_BASE_PTR)
39154 #define USB_ANALOG_USB2_MISC_CLR                 USB_ANALOG_USB2_MISC_CLR_REG(USB_ANALOG_BASE_PTR)
39155 #define USB_ANALOG_USB2_MISC_TOG                 USB_ANALOG_USB2_MISC_TOG_REG(USB_ANALOG_BASE_PTR)
39156 #define USB_ANALOG_DIGPROG                       USB_ANALOG_DIGPROG_REG(USB_ANALOG_BASE_PTR)
39157 
39158 /*!
39159  * @}
39160  */ /* end of group USB_ANALOG_Register_Accessor_Macros */
39161 
39162 /*!
39163  * @}
39164  */ /* end of group USB_ANALOG_Peripheral */
39165 
39166 /* ----------------------------------------------------------------------------
39167    -- VDEC Peripheral Access Layer
39168    ---------------------------------------------------------------------------- */
39169 
39170 /*!
39171  * @addtogroup VDEC_Peripheral_Access_Layer VDEC Peripheral Access Layer
39172  * @{
39173  */
39174 
39175 /** VDEC - Register Layout Typedef */
39176 typedef struct {
39177   __IO  uint32_t CFC1;                                   /**< 2D Comb Filter Control 1, offset: 0x0 */
39178   uint8_t RESERVED_0[32];
39179   __IO  uint32_t BRSTGT;                                 /**< Burst GATE, offset: 0x24 */
39180   uint8_t RESERVED_1[24];
39181   __IO  uint32_t HZPOS;                                  /**< Horizontal Position, offset: 0x40 */
39182   __IO  uint32_t VRTPOS;                                 /**< Vertical Position, offset: 0x44 */
39183   uint8_t RESERVED_2[12];
39184   __IO  uint32_t HVSHFT;                                 /**< Output Conditioning and HV Shift, offset: 0x54 */
39185   __IO  uint32_t HSIGS;                                  /**< HSync Ignore Start, offset: 0x58 */
39186   __IO  uint32_t HSIGE;                                  /**< HSync Ignore End, offset: 0x5C */
39187   __IO  uint32_t VSCON1;                                 /**< VSync Control 1, offset: 0x60 */
39188   __IO  uint32_t VSCON2;                                 /**< VSync Control 2, offset: 0x64 */
39189   uint8_t RESERVED_3[4];
39190   __IO  uint32_t YCDEL;                                  /**< Y/C Delay and Chroma Debug, offset: 0x6C */
39191   __IO  uint32_t AFTCLP;                                 /**< After Clamp, offset: 0x70 */
39192   uint8_t RESERVED_4[4];
39193   __IO  uint32_t DCOFF;                                  /**< DC Offset, offset: 0x78 */
39194   uint8_t RESERVED_5[8];
39195   __IO  uint32_t CSID;                                   /**< Chroma Swap, Invert, and Debug, offset: 0x84 */
39196   __IO  uint32_t CBGN;                                   /**< Cb Gain, offset: 0x88 */
39197   __IO  uint32_t CRGN;                                   /**< Cr Gain, offset: 0x8C */
39198   __IO  uint32_t CNTR;                                   /**< Contrast, offset: 0x90 */
39199   __IO  uint32_t BRT;                                    /**< Brightness, offset: 0x94 */
39200   __IO  uint32_t HUE;                                    /**< Hue, offset: 0x98 */
39201   __IO  uint32_t CHBTH;                                  /**< Chroma Burst Threshold, offset: 0x9C */
39202   uint8_t RESERVED_6[4];
39203   __IO  uint32_t SHPIMP;                                 /**< Sharpness Improvement, offset: 0xA4 */
39204   __IO  uint32_t CHPLLIM;                                /**< Chroma PLL and Input Mode, offset: 0xA8 */
39205   __I   uint32_t VIDMOD;                                 /**< Video Mode, offset: 0xAC */
39206   __I   uint32_t VIDSTS;                                 /**< Video Status, offset: 0xB0 */
39207   __I   uint32_t NOISE;                                  /**< Noise Detector, offset: 0xB4 */
39208   __IO  uint32_t STDDBG;                                 /**< Standards and Debug, offset: 0xB8 */
39209   __IO  uint32_t MANOVR;                                 /**< Manual Override, offset: 0xBC */
39210   uint8_t RESERVED_7[8];
39211   __IO  uint32_t VSSGTH;                                 /**< VSync and Signal Thresholds, offset: 0xC8 */
39212   uint8_t RESERVED_8[4];
39213   __IO  uint32_t DBGFBH;                                 /**< Debug Framebuffer, offset: 0xD0 */
39214   __IO  uint32_t DBGFBL;                                 /**< Debug Framebuffer 2, offset: 0xD4 */
39215   __IO  uint32_t HACTS;                                  /**< H Active Start, offset: 0xD8 */
39216   __IO  uint32_t HACTE;                                  /**< H Active End, offset: 0xDC */
39217   __IO  uint32_t VACTS;                                  /**< V Active Start, offset: 0xE0 */
39218   __IO  uint32_t VACTE;                                  /**< V Active End, offset: 0xE4 */
39219   uint8_t RESERVED_9[4];
39220   __IO  uint32_t HSTIP;                                  /**< HSync Tip, offset: 0xEC */
39221   uint8_t RESERVED_10[8];
39222   __IO  uint32_t BLSCRCR;                                /**< Bluescreen Cr, offset: 0xF8 */
39223   __IO  uint32_t BLSCRCB;                                /**< Bluescreen Cb, offset: 0xFC */
39224   uint8_t RESERVED_11[4];
39225   __IO  uint32_t LMAGC2;                                 /**< Luma AGC Control 2, offset: 0x104 */
39226   uint8_t RESERVED_12[4];
39227   __IO  uint32_t CHAGC2;                                 /**< Chroma AGC Control 2, offset: 0x10C */
39228   uint8_t RESERVED_13[4];
39229   __IO  uint32_t MINTH;                                  /**< Minimum Threshold, offset: 0x114 */
39230   uint8_t RESERVED_14[4];
39231   __I   uint32_t VFRQOH;                                 /**< Vertical Lines High, offset: 0x11C */
39232   __I   uint32_t VFRQOL;                                 /**< Vertical Lines Low, offset: 0x120 */
39233   uint8_t RESERVED_15[508];
39234   __IO  uint32_t ASYNCLKFREQ1;                           /**< Asynchclk Frequency 1, offset: 0x320 */
39235   __IO  uint32_t ASYNCLKFREQ2;                           /**< Asynchclk Frequency 2, offset: 0x324 */
39236   __IO  uint32_t ASYNCLKFREQ3;                           /**< Asynchclk Frequency 3, offset: 0x328 */
39237   __IO  uint32_t ASYNCLKFREQ4;                           /**< Asynchclk Frequency 4, offset: 0x32C */
39238 } VDEC_Type, *VDEC_MemMapPtr;
39239 
39240 /* ----------------------------------------------------------------------------
39241    -- VDEC - Register accessor macros
39242    ---------------------------------------------------------------------------- */
39243 
39244 /*!
39245  * @addtogroup VDEC_Register_Accessor_Macros VDEC - Register accessor macros
39246  * @{
39247  */
39248 
39249 /* VDEC - Register accessors */
39250 #define VDEC_CFC1_REG(base)                      ((base)->CFC1)
39251 #define VDEC_BRSTGT_REG(base)                    ((base)->BRSTGT)
39252 #define VDEC_HZPOS_REG(base)                     ((base)->HZPOS)
39253 #define VDEC_VRTPOS_REG(base)                    ((base)->VRTPOS)
39254 #define VDEC_HVSHFT_REG(base)                    ((base)->HVSHFT)
39255 #define VDEC_HSIGS_REG(base)                     ((base)->HSIGS)
39256 #define VDEC_HSIGE_REG(base)                     ((base)->HSIGE)
39257 #define VDEC_VSCON1_REG(base)                    ((base)->VSCON1)
39258 #define VDEC_VSCON2_REG(base)                    ((base)->VSCON2)
39259 #define VDEC_YCDEL_REG(base)                     ((base)->YCDEL)
39260 #define VDEC_AFTCLP_REG(base)                    ((base)->AFTCLP)
39261 #define VDEC_DCOFF_REG(base)                     ((base)->DCOFF)
39262 #define VDEC_CSID_REG(base)                      ((base)->CSID)
39263 #define VDEC_CBGN_REG(base)                      ((base)->CBGN)
39264 #define VDEC_CRGN_REG(base)                      ((base)->CRGN)
39265 #define VDEC_CNTR_REG(base)                      ((base)->CNTR)
39266 #define VDEC_BRT_REG(base)                       ((base)->BRT)
39267 #define VDEC_HUE_REG(base)                       ((base)->HUE)
39268 #define VDEC_CHBTH_REG(base)                     ((base)->CHBTH)
39269 #define VDEC_SHPIMP_REG(base)                    ((base)->SHPIMP)
39270 #define VDEC_CHPLLIM_REG(base)                   ((base)->CHPLLIM)
39271 #define VDEC_VIDMOD_REG(base)                    ((base)->VIDMOD)
39272 #define VDEC_VIDSTS_REG(base)                    ((base)->VIDSTS)
39273 #define VDEC_NOISE_REG(base)                     ((base)->NOISE)
39274 #define VDEC_STDDBG_REG(base)                    ((base)->STDDBG)
39275 #define VDEC_MANOVR_REG(base)                    ((base)->MANOVR)
39276 #define VDEC_VSSGTH_REG(base)                    ((base)->VSSGTH)
39277 #define VDEC_DBGFBH_REG(base)                    ((base)->DBGFBH)
39278 #define VDEC_DBGFBL_REG(base)                    ((base)->DBGFBL)
39279 #define VDEC_HACTS_REG(base)                     ((base)->HACTS)
39280 #define VDEC_HACTE_REG(base)                     ((base)->HACTE)
39281 #define VDEC_VACTS_REG(base)                     ((base)->VACTS)
39282 #define VDEC_VACTE_REG(base)                     ((base)->VACTE)
39283 #define VDEC_HSTIP_REG(base)                     ((base)->HSTIP)
39284 #define VDEC_BLSCRCR_REG(base)                   ((base)->BLSCRCR)
39285 #define VDEC_BLSCRCB_REG(base)                   ((base)->BLSCRCB)
39286 #define VDEC_LMAGC2_REG(base)                    ((base)->LMAGC2)
39287 #define VDEC_CHAGC2_REG(base)                    ((base)->CHAGC2)
39288 #define VDEC_MINTH_REG(base)                     ((base)->MINTH)
39289 #define VDEC_VFRQOH_REG(base)                    ((base)->VFRQOH)
39290 #define VDEC_VFRQOL_REG(base)                    ((base)->VFRQOL)
39291 #define VDEC_ASYNCLKFREQ1_REG(base)              ((base)->ASYNCLKFREQ1)
39292 #define VDEC_ASYNCLKFREQ2_REG(base)              ((base)->ASYNCLKFREQ2)
39293 #define VDEC_ASYNCLKFREQ3_REG(base)              ((base)->ASYNCLKFREQ3)
39294 #define VDEC_ASYNCLKFREQ4_REG(base)              ((base)->ASYNCLKFREQ4)
39295 
39296 /*!
39297  * @}
39298  */ /* end of group VDEC_Register_Accessor_Macros */
39299 
39300 /* ----------------------------------------------------------------------------
39301    -- VDEC Register Masks
39302    ---------------------------------------------------------------------------- */
39303 
39304 /*!
39305  * @addtogroup VDEC_Register_Masks VDEC Register Masks
39306  * @{
39307  */
39308 
39309 /* CFC1 Bit Fields */
39310 #define VDEC_CFC1_rc_combmode_override_MASK      0xFu
39311 #define VDEC_CFC1_rc_combmode_override_SHIFT     0
39312 #define VDEC_CFC1_rc_combmode_override(x)        (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_combmode_override_SHIFT))&VDEC_CFC1_rc_combmode_override_MASK)
39313 #define VDEC_CFC1_rc_debugout_MASK               0xF0u
39314 #define VDEC_CFC1_rc_debugout_SHIFT              4
39315 #define VDEC_CFC1_rc_debugout(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_debugout_SHIFT))&VDEC_CFC1_rc_debugout_MASK)
39316 /* BRSTGT Bit Fields */
39317 #define VDEC_BRSTGT_rc_cburststart_MASK          0xFFu
39318 #define VDEC_BRSTGT_rc_cburststart_SHIFT         0
39319 #define VDEC_BRSTGT_rc_cburststart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_BRSTGT_rc_cburststart_SHIFT))&VDEC_BRSTGT_rc_cburststart_MASK)
39320 /* HZPOS Bit Fields */
39321 #define VDEC_HZPOS_ro_hpramp_cmp_MASK            0xFFu
39322 #define VDEC_HZPOS_ro_hpramp_cmp_SHIFT           0
39323 #define VDEC_HZPOS_ro_hpramp_cmp(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_HZPOS_ro_hpramp_cmp_SHIFT))&VDEC_HZPOS_ro_hpramp_cmp_MASK)
39324 /* VRTPOS Bit Fields */
39325 #define VDEC_VRTPOS_ro_vline_cmp_MASK            0xFFu
39326 #define VDEC_VRTPOS_ro_vline_cmp_SHIFT           0
39327 #define VDEC_VRTPOS_ro_vline_cmp(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_VRTPOS_ro_vline_cmp_SHIFT))&VDEC_VRTPOS_ro_vline_cmp_MASK)
39328 /* HVSHFT Bit Fields */
39329 #define VDEC_HVSHFT_ro_hzero_sel_MASK            0x1u
39330 #define VDEC_HVSHFT_ro_hzero_sel_SHIFT           0
39331 #define VDEC_HVSHFT_ro_invfield_MASK             0x2u
39332 #define VDEC_HVSHFT_ro_invfield_SHIFT            1
39333 #define VDEC_HVSHFT_ro_vzero_sel_MASK            0x10u
39334 #define VDEC_HVSHFT_ro_vzero_sel_SHIFT           4
39335 #define VDEC_HVSHFT_ro_useactive_MASK            0x20u
39336 #define VDEC_HVSHFT_ro_useactive_SHIFT           5
39337 #define VDEC_HVSHFT_antialias_dis_MASK           0x40u
39338 #define VDEC_HVSHFT_antialias_dis_SHIFT          6
39339 /* HSIGS Bit Fields */
39340 #define VDEC_HSIGS_rv_ignorestart_MASK           0xFFu
39341 #define VDEC_HSIGS_rv_ignorestart_SHIFT          0
39342 #define VDEC_HSIGS_rv_ignorestart(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGS_rv_ignorestart_SHIFT))&VDEC_HSIGS_rv_ignorestart_MASK)
39343 /* HSIGE Bit Fields */
39344 #define VDEC_HSIGE_rv_ignoreend_MASK             0xFFu
39345 #define VDEC_HSIGE_rv_ignoreend_SHIFT            0
39346 #define VDEC_HSIGE_rv_ignoreend(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGE_rv_ignoreend_SHIFT))&VDEC_HSIGE_rv_ignoreend_MASK)
39347 /* VSCON1 Bit Fields */
39348 #define VDEC_VSCON1_rh_vdet_dbg_MASK             0x7u
39349 #define VDEC_VSCON1_rh_vdet_dbg_SHIFT            0
39350 #define VDEC_VSCON1_rh_vdet_dbg(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON1_rh_vdet_dbg_SHIFT))&VDEC_VSCON1_rh_vdet_dbg_MASK)
39351 #define VDEC_VSCON1_rh_robust625det_MASK         0x8u
39352 #define VDEC_VSCON1_rh_robust625det_SHIFT        3
39353 #define VDEC_VSCON1_rh_dis_vsyncdetect_MASK      0x10u
39354 #define VDEC_VSCON1_rh_dis_vsyncdetect_SHIFT     4
39355 #define VDEC_VSCON1_rh_vsynchalfmode_MASK        0x20u
39356 #define VDEC_VSCON1_rh_vsynchalfmode_SHIFT       5
39357 #define VDEC_VSCON1_rh_modadd_dis_MASK           0x40u
39358 #define VDEC_VSCON1_rh_modadd_dis_SHIFT          6
39359 #define VDEC_VSCON1_rh_8or16_MASK                0x80u
39360 #define VDEC_VSCON1_rh_8or16_SHIFT               7
39361 /* VSCON2 Bit Fields */
39362 #define VDEC_VSCON2_rh_vcr_phasethr_MASK         0x3u
39363 #define VDEC_VSCON2_rh_vcr_phasethr_SHIFT        0
39364 #define VDEC_VSCON2_rh_vcr_phasethr(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_phasethr_SHIFT))&VDEC_VSCON2_rh_vcr_phasethr_MASK)
39365 #define VDEC_VSCON2_rh_vcr_force_dis_MASK        0xCu
39366 #define VDEC_VSCON2_rh_vcr_force_dis_SHIFT       2
39367 #define VDEC_VSCON2_rh_vcr_force_dis(x)          (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_force_dis_SHIFT))&VDEC_VSCON2_rh_vcr_force_dis_MASK)
39368 #define VDEC_VSCON2_rh_hsw_coring_MASK           0x30u
39369 #define VDEC_VSCON2_rh_hsw_coring_SHIFT          4
39370 #define VDEC_VSCON2_rh_hsw_coring(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_hsw_coring_SHIFT))&VDEC_VSCON2_rh_hsw_coring_MASK)
39371 #define VDEC_VSCON2_rh_smooth_hsw_MASK           0x40u
39372 #define VDEC_VSCON2_rh_smooth_hsw_SHIFT          6
39373 #define VDEC_VSCON2_rh_disable_hsw_MASK          0x80u
39374 #define VDEC_VSCON2_rh_disable_hsw_SHIFT         7
39375 /* YCDEL Bit Fields */
39376 #define VDEC_YCDEL_rd_nopalave_MASK              0x1u
39377 #define VDEC_YCDEL_rd_nopalave_SHIFT             0
39378 #define VDEC_YCDEL_rd_narrow_MASK                0x2u
39379 #define VDEC_YCDEL_rd_narrow_SHIFT               1
39380 #define VDEC_YCDEL_rd_wide_MASK                  0x4u
39381 #define VDEC_YCDEL_rd_wide_SHIFT                 2
39382 #define VDEC_YCDEL_rd_lumadel_MASK               0xF0u
39383 #define VDEC_YCDEL_rd_lumadel_SHIFT              4
39384 #define VDEC_YCDEL_rd_lumadel(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_YCDEL_rd_lumadel_SHIFT))&VDEC_YCDEL_rd_lumadel_MASK)
39385 /* AFTCLP Bit Fields */
39386 #define VDEC_AFTCLP_rh_shortframe_MASK           0x1u
39387 #define VDEC_AFTCLP_rh_shortframe_SHIFT          0
39388 #define VDEC_AFTCLP_rl_disoffset_MASK            0x2u
39389 #define VDEC_AFTCLP_rl_disoffset_SHIFT           1
39390 #define VDEC_AFTCLP_rl_resetoffset_MASK          0x4u
39391 #define VDEC_AFTCLP_rl_resetoffset_SHIFT         2
39392 #define VDEC_AFTCLP_rc_afterclamp_update_en_MASK 0x10u
39393 #define VDEC_AFTCLP_rc_afterclamp_update_en_SHIFT 4
39394 #define VDEC_AFTCLP_rc_midfield_dis_MASK         0x20u
39395 #define VDEC_AFTCLP_rc_midfield_dis_SHIFT        5
39396 #define VDEC_AFTCLP_rc_aoutoafterclamp_dis_MASK  0x40u
39397 #define VDEC_AFTCLP_rc_aoutoafterclamp_dis_SHIFT 6
39398 /* DCOFF Bit Fields */
39399 #define VDEC_DCOFF_rl_dcoffsetI_MASK             0x3u
39400 #define VDEC_DCOFF_rl_dcoffsetI_SHIFT            0
39401 #define VDEC_DCOFF_rl_dcoffsetI(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetI_SHIFT))&VDEC_DCOFF_rl_dcoffsetI_MASK)
39402 #define VDEC_DCOFF_rl_linemeasure_dis_MASK       0x8u
39403 #define VDEC_DCOFF_rl_linemeasure_dis_SHIFT      3
39404 #define VDEC_DCOFF_rl_dcoffsetP_MASK             0x70u
39405 #define VDEC_DCOFF_rl_dcoffsetP_SHIFT            4
39406 #define VDEC_DCOFF_rl_dcoffsetP(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetP_SHIFT))&VDEC_DCOFF_rl_dcoffsetP_MASK)
39407 /* CSID Bit Fields */
39408 #define VDEC_CSID_rd_swapcrcb_MASK               0x1u
39409 #define VDEC_CSID_rd_swapcrcb_SHIFT              0
39410 #define VDEC_CSID_rd_invcr_MASK                  0x2u
39411 #define VDEC_CSID_rd_invcr_SHIFT                 1
39412 #define VDEC_CSID_rd_invcb_MASK                  0x4u
39413 #define VDEC_CSID_rd_invcb_SHIFT                 2
39414 #define VDEC_CSID_rd_nopalhue_MASK               0x8u
39415 #define VDEC_CSID_rd_nopalhue_SHIFT              3
39416 #define VDEC_CSID_rd_bypasshilbert_MASK          0x80u
39417 #define VDEC_CSID_rd_bypasshilbert_SHIFT         7
39418 /* CBGN Bit Fields */
39419 #define VDEC_CBGN_rd_cbgain_MASK                 0xFFu
39420 #define VDEC_CBGN_rd_cbgain_SHIFT                0
39421 #define VDEC_CBGN_rd_cbgain(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_CBGN_rd_cbgain_SHIFT))&VDEC_CBGN_rd_cbgain_MASK)
39422 /* CRGN Bit Fields */
39423 #define VDEC_CRGN_rd_crgain_MASK                 0xFFu
39424 #define VDEC_CRGN_rd_crgain_SHIFT                0
39425 #define VDEC_CRGN_rd_crgain(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_CRGN_rd_crgain_SHIFT))&VDEC_CRGN_rd_crgain_MASK)
39426 /* CNTR Bit Fields */
39427 #define VDEC_CNTR_rd_lumagain_MASK               0xFFu
39428 #define VDEC_CNTR_rd_lumagain_SHIFT              0
39429 #define VDEC_CNTR_rd_lumagain(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_CNTR_rd_lumagain_SHIFT))&VDEC_CNTR_rd_lumagain_MASK)
39430 /* BRT Bit Fields */
39431 #define VDEC_BRT_rc_blacklevel_MASK              0xFFu
39432 #define VDEC_BRT_rc_blacklevel_SHIFT             0
39433 #define VDEC_BRT_rc_blacklevel(x)                (((uint32_t)(((uint32_t)(x))<<VDEC_BRT_rc_blacklevel_SHIFT))&VDEC_BRT_rc_blacklevel_MASK)
39434 /* HUE Bit Fields */
39435 #define VDEC_HUE_rd_ch_thresh_MASK               0xFFu
39436 #define VDEC_HUE_rd_ch_thresh_SHIFT              0
39437 #define VDEC_HUE_rd_ch_thresh(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_HUE_rd_ch_thresh_SHIFT))&VDEC_HUE_rd_ch_thresh_MASK)
39438 /* CHBTH Bit Fields */
39439 #define VDEC_CHBTH_rd_ch_thresh_MASK             0xFFu
39440 #define VDEC_CHBTH_rd_ch_thresh_SHIFT            0
39441 #define VDEC_CHBTH_rd_ch_thresh(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_CHBTH_rd_ch_thresh_SHIFT))&VDEC_CHBTH_rd_ch_thresh_MASK)
39442 /* SHPIMP Bit Fields */
39443 #define VDEC_SHPIMP_rd_peak_MASK                 0xFu
39444 #define VDEC_SHPIMP_rd_peak_SHIFT                0
39445 #define VDEC_SHPIMP_rd_peak(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_peak_SHIFT))&VDEC_SHPIMP_rd_peak_MASK)
39446 #define VDEC_SHPIMP_rd_slope_MASK                0xF0u
39447 #define VDEC_SHPIMP_rd_slope_SHIFT               4
39448 #define VDEC_SHPIMP_rd_slope(x)                  (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_slope_SHIFT))&VDEC_SHPIMP_rd_slope_MASK)
39449 /* CHPLLIM Bit Fields */
39450 #define VDEC_CHPLLIM_rd_inputcables_MASK         0x7u
39451 #define VDEC_CHPLLIM_rd_inputcables_SHIFT        0
39452 #define VDEC_CHPLLIM_rd_inputcables(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_inputcables_SHIFT))&VDEC_CHPLLIM_rd_inputcables_MASK)
39453 #define VDEC_CHPLLIM_rd_locked_force_MASK        0x8u
39454 #define VDEC_CHPLLIM_rd_locked_force_SHIFT       3
39455 #define VDEC_CHPLLIM_rd_chlock_atten_MASK        0x70u
39456 #define VDEC_CHPLLIM_rd_chlock_atten_SHIFT       4
39457 #define VDEC_CHPLLIM_rd_chlock_atten(x)          (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_chlock_atten_SHIFT))&VDEC_CHPLLIM_rd_chlock_atten_MASK)
39458 /* VIDMOD Bit Fields */
39459 #define VDEC_VIDMOD_havesignal_MASK              0x1u
39460 #define VDEC_VIDMOD_havesignal_SHIFT             0
39461 #define VDEC_VIDMOD_Hlocked_MASK                 0x2u
39462 #define VDEC_VIDMOD_Hlocked_SHIFT                1
39463 #define VDEC_VIDMOD_chroma_MASK                  0x4u
39464 #define VDEC_VIDMOD_chroma_SHIFT                 2
39465 #define VDEC_VIDMOD_ch_locked_MASK               0x8u
39466 #define VDEC_VIDMOD_ch_locked_SHIFT              3
39467 #define VDEC_VIDMOD_m625_MASK                    0x10u
39468 #define VDEC_VIDMOD_m625_SHIFT                   4
39469 #define VDEC_VIDMOD_F443_MASK                    0x40u
39470 #define VDEC_VIDMOD_F443_SHIFT                   6
39471 #define VDEC_VIDMOD_Pal_MASK                     0x80u
39472 #define VDEC_VIDMOD_Pal_SHIFT                    7
39473 /* VIDSTS Bit Fields */
39474 #define VDEC_VIDSTS_Nonarith_MASK                0x1u
39475 #define VDEC_VIDSTS_Nonarith_SHIFT               0
39476 #define VDEC_VIDSTS_Nonarith3D_MASK              0x2u
39477 #define VDEC_VIDSTS_Nonarith3D_SHIFT             1
39478 #define VDEC_VIDSTS_Vcrdetect_MASK               0x4u
39479 #define VDEC_VIDSTS_Vcrdetect_SHIFT              2
39480 /* NOISE Bit Fields */
39481 #define VDEC_NOISE_Noise_MASK                    0xFFu
39482 #define VDEC_NOISE_Noise_SHIFT                   0
39483 #define VDEC_NOISE_Noise(x)                      (((uint32_t)(((uint32_t)(x))<<VDEC_NOISE_Noise_SHIFT))&VDEC_NOISE_Noise_MASK)
39484 /* STDDBG Bit Fields */
39485 #define VDEC_STDDBG_standard_filter_MASK         0x3u
39486 #define VDEC_STDDBG_standard_filter_SHIFT        0
39487 #define VDEC_STDDBG_standard_filter(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_STDDBG_standard_filter_SHIFT))&VDEC_STDDBG_standard_filter_MASK)
39488 #define VDEC_STDDBG_force_havesignal_MASK        0x8u
39489 #define VDEC_STDDBG_force_havesignal_SHIFT       3
39490 #define VDEC_STDDBG_force_2dntsc443_MASK         0x20u
39491 #define VDEC_STDDBG_force_2dntsc443_SHIFT        5
39492 #define VDEC_STDDBG_ntscj_MASK                   0x40u
39493 #define VDEC_STDDBG_ntscj_SHIFT                  6
39494 #define VDEC_STDDBG_rd_fc_maual_MASK             0x80u
39495 #define VDEC_STDDBG_rd_fc_maual_SHIFT            7
39496 /* MANOVR Bit Fields */
39497 #define VDEC_MANOVR_manual_625_MASK              0x1u
39498 #define VDEC_MANOVR_manual_625_SHIFT             0
39499 #define VDEC_MANOVR_four43_manual_MASK           0x4u
39500 #define VDEC_MANOVR_four43_manual_SHIFT          2
39501 #define VDEC_MANOVR_pal_manual_MASK              0x8u
39502 #define VDEC_MANOVR_pal_manual_SHIFT             3
39503 #define VDEC_MANOVR_line625_override_MASK        0x10u
39504 #define VDEC_MANOVR_line625_override_SHIFT       4
39505 #define VDEC_MANOVR_f443_override_MASK           0x40u
39506 #define VDEC_MANOVR_f443_override_SHIFT          6
39507 #define VDEC_MANOVR_pal_override_MASK            0x80u
39508 #define VDEC_MANOVR_pal_override_SHIFT           7
39509 /* VSSGTH Bit Fields */
39510 #define VDEC_VSSGTH_nosigthresh_MASK             0x7u
39511 #define VDEC_VSSGTH_nosigthresh_SHIFT            0
39512 #define VDEC_VSSGTH_nosigthresh(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_nosigthresh_SHIFT))&VDEC_VSSGTH_nosigthresh_MASK)
39513 #define VDEC_VSSGTH_rh_vsynclength_MASK          0xF0u
39514 #define VDEC_VSSGTH_rh_vsynclength_SHIFT         4
39515 #define VDEC_VSSGTH_rh_vsynclength(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_rh_vsynclength_SHIFT))&VDEC_VSSGTH_rh_vsynclength_MASK)
39516 /* DBGFBH Bit Fields */
39517 #define VDEC_DBGFBH_clamp_delayH_MASK            0x3u
39518 #define VDEC_DBGFBH_clamp_delayH_SHIFT           0
39519 #define VDEC_DBGFBH_clamp_delayH(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBH_clamp_delayH_SHIFT))&VDEC_DBGFBH_clamp_delayH_MASK)
39520 /* DBGFBL Bit Fields */
39521 #define VDEC_DBGFBL_clamp_delayL_MASK            0xFFu
39522 #define VDEC_DBGFBL_clamp_delayL_SHIFT           0
39523 #define VDEC_DBGFBL_clamp_delayL(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBL_clamp_delayL_SHIFT))&VDEC_DBGFBL_clamp_delayL_MASK)
39524 /* HACTS Bit Fields */
39525 #define VDEC_HACTS_ro_hactivestart_MASK          0xFFu
39526 #define VDEC_HACTS_ro_hactivestart_SHIFT         0
39527 #define VDEC_HACTS_ro_hactivestart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_HACTS_ro_hactivestart_SHIFT))&VDEC_HACTS_ro_hactivestart_MASK)
39528 /* HACTE Bit Fields */
39529 #define VDEC_HACTE_ro_hactiveend_MASK            0xFFu
39530 #define VDEC_HACTE_ro_hactiveend_SHIFT           0
39531 #define VDEC_HACTE_ro_hactiveend(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_HACTE_ro_hactiveend_SHIFT))&VDEC_HACTE_ro_hactiveend_MASK)
39532 /* VACTS Bit Fields */
39533 #define VDEC_VACTS_ro_vactivestart_MASK          0xFFu
39534 #define VDEC_VACTS_ro_vactivestart_SHIFT         0
39535 #define VDEC_VACTS_ro_vactivestart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_VACTS_ro_vactivestart_SHIFT))&VDEC_VACTS_ro_vactivestart_MASK)
39536 /* VACTE Bit Fields */
39537 #define VDEC_VACTE_ro_vactiveend_MASK            0xFFu
39538 #define VDEC_VACTE_ro_vactiveend_SHIFT           0
39539 #define VDEC_VACTE_ro_vactiveend(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_VACTE_ro_vactiveend_SHIFT))&VDEC_VACTE_ro_vactiveend_MASK)
39540 /* HSTIP Bit Fields */
39541 #define VDEC_HSTIP_rh_tipgate_start_MASK         0xFFu
39542 #define VDEC_HSTIP_rh_tipgate_start_SHIFT        0
39543 #define VDEC_HSTIP_rh_tipgate_start(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_HSTIP_rh_tipgate_start_SHIFT))&VDEC_HSTIP_rh_tipgate_start_MASK)
39544 /* BLSCRCR Bit Fields */
39545 #define VDEC_BLSCRCR_bluescreen_y_MASK           0xFFu
39546 #define VDEC_BLSCRCR_bluescreen_y_SHIFT          0
39547 #define VDEC_BLSCRCR_bluescreen_y(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCR_bluescreen_y_SHIFT))&VDEC_BLSCRCR_bluescreen_y_MASK)
39548 /* BLSCRCB Bit Fields */
39549 #define VDEC_BLSCRCB_bluescreen_cb_MASK          0xFFu
39550 #define VDEC_BLSCRCB_bluescreen_cb_SHIFT         0
39551 #define VDEC_BLSCRCB_bluescreen_cb(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCB_bluescreen_cb_SHIFT))&VDEC_BLSCRCB_bluescreen_cb_MASK)
39552 /* LMAGC2 Bit Fields */
39553 #define VDEC_LMAGC2_ragc_target_MASK             0xFFu
39554 #define VDEC_LMAGC2_ragc_target_SHIFT            0
39555 #define VDEC_LMAGC2_ragc_target(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_LMAGC2_ragc_target_SHIFT))&VDEC_LMAGC2_ragc_target_MASK)
39556 /* CHAGC2 Bit Fields */
39557 #define VDEC_CHAGC2_rd_chagc_target_MASK         0xFFu
39558 #define VDEC_CHAGC2_rd_chagc_target_SHIFT        0
39559 #define VDEC_CHAGC2_rd_chagc_target(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_CHAGC2_rd_chagc_target_SHIFT))&VDEC_CHAGC2_rd_chagc_target_MASK)
39560 /* MINTH Bit Fields */
39561 #define VDEC_MINTH_minthresh_MASK                0xFFu
39562 #define VDEC_MINTH_minthresh_SHIFT               0
39563 #define VDEC_MINTH_minthresh(x)                  (((uint32_t)(((uint32_t)(x))<<VDEC_MINTH_minthresh_SHIFT))&VDEC_MINTH_minthresh_MASK)
39564 /* VFRQOH Bit Fields */
39565 #define VDEC_VFRQOH_vfreqo_MASK                  0xFu
39566 #define VDEC_VFRQOH_vfreqo_SHIFT                 0
39567 #define VDEC_VFRQOH_vfreqo(x)                    (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOH_vfreqo_SHIFT))&VDEC_VFRQOH_vfreqo_MASK)
39568 /* VFRQOL Bit Fields */
39569 #define VDEC_VFRQOL_vfreqo_MASK                  0xFFu
39570 #define VDEC_VFRQOL_vfreqo_SHIFT                 0
39571 #define VDEC_VFRQOL_vfreqo(x)                    (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOL_vfreqo_SHIFT))&VDEC_VFRQOL_vfreqo_MASK)
39572 /* ASYNCLKFREQ1 Bit Fields */
39573 #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_MASK 0xFFu
39574 #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_SHIFT 0
39575 #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_MASK)
39576 /* ASYNCLKFREQ2 Bit Fields */
39577 #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_MASK 0xFFu
39578 #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_SHIFT 0
39579 #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_MASK)
39580 /* ASYNCLKFREQ3 Bit Fields */
39581 #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_MASK 0xFFu
39582 #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_SHIFT 0
39583 #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_MASK)
39584 /* ASYNCLKFREQ4 Bit Fields */
39585 #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_MASK 0xFFu
39586 #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_SHIFT 0
39587 #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_MASK)
39588 
39589 /*!
39590  * @}
39591  */ /* end of group VDEC_Register_Masks */
39592 
39593 /* VDEC - Peripheral instance base addresses */
39594 /** Peripheral VDEC base address */
39595 #define VDEC_BASE                                (0x4222C000u)
39596 /** Peripheral VDEC base pointer */
39597 #define VDEC                                     ((VDEC_Type *)VDEC_BASE)
39598 #define VDEC_BASE_PTR                            (VDEC)
39599 /** Array initializer of VDEC peripheral base addresses */
39600 #define VDEC_BASE_ADDRS                          { VDEC_BASE }
39601 /** Array initializer of VDEC peripheral base pointers */
39602 #define VDEC_BASE_PTRS                           { VDEC }
39603 
39604 /* ----------------------------------------------------------------------------
39605    -- VDEC - Register accessor macros
39606    ---------------------------------------------------------------------------- */
39607 
39608 /*!
39609  * @addtogroup VDEC_Register_Accessor_Macros VDEC - Register accessor macros
39610  * @{
39611  */
39612 
39613 /* VDEC - Register instance definitions */
39614 /* VDEC */
39615 #define VDEC_CFC1                                VDEC_CFC1_REG(VDEC_BASE_PTR)
39616 #define VDEC_BRSTGT                              VDEC_BRSTGT_REG(VDEC_BASE_PTR)
39617 #define VDEC_HZPOS                               VDEC_HZPOS_REG(VDEC_BASE_PTR)
39618 #define VDEC_VRTPOS                              VDEC_VRTPOS_REG(VDEC_BASE_PTR)
39619 #define VDEC_HVSHFT                              VDEC_HVSHFT_REG(VDEC_BASE_PTR)
39620 #define VDEC_HSIGS                               VDEC_HSIGS_REG(VDEC_BASE_PTR)
39621 #define VDEC_HSIGE                               VDEC_HSIGE_REG(VDEC_BASE_PTR)
39622 #define VDEC_VSCON1                              VDEC_VSCON1_REG(VDEC_BASE_PTR)
39623 #define VDEC_VSCON2                              VDEC_VSCON2_REG(VDEC_BASE_PTR)
39624 #define VDEC_YCDEL                               VDEC_YCDEL_REG(VDEC_BASE_PTR)
39625 #define VDEC_AFTCLP                              VDEC_AFTCLP_REG(VDEC_BASE_PTR)
39626 #define VDEC_DCOFF                               VDEC_DCOFF_REG(VDEC_BASE_PTR)
39627 #define VDEC_CSID                                VDEC_CSID_REG(VDEC_BASE_PTR)
39628 #define VDEC_CBGN                                VDEC_CBGN_REG(VDEC_BASE_PTR)
39629 #define VDEC_CRGN                                VDEC_CRGN_REG(VDEC_BASE_PTR)
39630 #define VDEC_CNTR                                VDEC_CNTR_REG(VDEC_BASE_PTR)
39631 #define VDEC_BRT                                 VDEC_BRT_REG(VDEC_BASE_PTR)
39632 #define VDEC_HUE                                 VDEC_HUE_REG(VDEC_BASE_PTR)
39633 #define VDEC_CHBTH                               VDEC_CHBTH_REG(VDEC_BASE_PTR)
39634 #define VDEC_SHPIMP                              VDEC_SHPIMP_REG(VDEC_BASE_PTR)
39635 #define VDEC_CHPLLIM                             VDEC_CHPLLIM_REG(VDEC_BASE_PTR)
39636 #define VDEC_VIDMOD                              VDEC_VIDMOD_REG(VDEC_BASE_PTR)
39637 #define VDEC_VIDSTS                              VDEC_VIDSTS_REG(VDEC_BASE_PTR)
39638 #define VDEC_NOISE                               VDEC_NOISE_REG(VDEC_BASE_PTR)
39639 #define VDEC_STDDBG                              VDEC_STDDBG_REG(VDEC_BASE_PTR)
39640 #define VDEC_MANOVR                              VDEC_MANOVR_REG(VDEC_BASE_PTR)
39641 #define VDEC_VSSGTH                              VDEC_VSSGTH_REG(VDEC_BASE_PTR)
39642 #define VDEC_DBGFBH                              VDEC_DBGFBH_REG(VDEC_BASE_PTR)
39643 #define VDEC_DBGFBL                              VDEC_DBGFBL_REG(VDEC_BASE_PTR)
39644 #define VDEC_HACTS                               VDEC_HACTS_REG(VDEC_BASE_PTR)
39645 #define VDEC_HACTE                               VDEC_HACTE_REG(VDEC_BASE_PTR)
39646 #define VDEC_VACTS                               VDEC_VACTS_REG(VDEC_BASE_PTR)
39647 #define VDEC_VACTE                               VDEC_VACTE_REG(VDEC_BASE_PTR)
39648 #define VDEC_HSTIP                               VDEC_HSTIP_REG(VDEC_BASE_PTR)
39649 #define VDEC_BLSCRCR                             VDEC_BLSCRCR_REG(VDEC_BASE_PTR)
39650 #define VDEC_BLSCRCB                             VDEC_BLSCRCB_REG(VDEC_BASE_PTR)
39651 #define VDEC_LMAGC2                              VDEC_LMAGC2_REG(VDEC_BASE_PTR)
39652 #define VDEC_CHAGC2                              VDEC_CHAGC2_REG(VDEC_BASE_PTR)
39653 #define VDEC_MINTH                               VDEC_MINTH_REG(VDEC_BASE_PTR)
39654 #define VDEC_VFRQOH                              VDEC_VFRQOH_REG(VDEC_BASE_PTR)
39655 #define VDEC_VFRQOL                              VDEC_VFRQOL_REG(VDEC_BASE_PTR)
39656 #define VDEC_ASYNCLKFREQ1                        VDEC_ASYNCLKFREQ1_REG(VDEC_BASE_PTR)
39657 #define VDEC_ASYNCLKFREQ2                        VDEC_ASYNCLKFREQ2_REG(VDEC_BASE_PTR)
39658 #define VDEC_ASYNCLKFREQ3                        VDEC_ASYNCLKFREQ3_REG(VDEC_BASE_PTR)
39659 #define VDEC_ASYNCLKFREQ4                        VDEC_ASYNCLKFREQ4_REG(VDEC_BASE_PTR)
39660 
39661 /*!
39662  * @}
39663  */ /* end of group VDEC_Register_Accessor_Macros */
39664 
39665 /*!
39666  * @}
39667  */ /* end of group VDEC_Peripheral */
39668 
39669 /* ----------------------------------------------------------------------------
39670    -- WDOG Peripheral Access Layer
39671    ---------------------------------------------------------------------------- */
39672 
39673 /*!
39674  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
39675  * @{
39676  */
39677 
39678 /** WDOG - Register Layout Typedef */
39679 typedef struct {
39680   __IO  uint16_t WCR;                                    /**< Watchdog Control Register, offset: 0x0 */
39681   __IO  uint16_t WSR;                                    /**< Watchdog Service Register, offset: 0x2 */
39682   __I   uint16_t WRSR;                                   /**< Watchdog Reset Status Register, offset: 0x4 */
39683   __IO  uint16_t WICR;                                   /**< Watchdog Interrupt Control Register, offset: 0x6 */
39684   __IO  uint16_t WMCR;                                   /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
39685 } WDOG_Type, *WDOG_MemMapPtr;
39686 
39687 /* ----------------------------------------------------------------------------
39688    -- WDOG - Register accessor macros
39689    ---------------------------------------------------------------------------- */
39690 
39691 /*!
39692  * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
39693  * @{
39694  */
39695 
39696 /* WDOG - Register accessors */
39697 #define WDOG_WCR_REG(base)                       ((base)->WCR)
39698 #define WDOG_WSR_REG(base)                       ((base)->WSR)
39699 #define WDOG_WRSR_REG(base)                      ((base)->WRSR)
39700 #define WDOG_WICR_REG(base)                      ((base)->WICR)
39701 #define WDOG_WMCR_REG(base)                      ((base)->WMCR)
39702 
39703 /*!
39704  * @}
39705  */ /* end of group WDOG_Register_Accessor_Macros */
39706 
39707 /* ----------------------------------------------------------------------------
39708    -- WDOG Register Masks
39709    ---------------------------------------------------------------------------- */
39710 
39711 /*!
39712  * @addtogroup WDOG_Register_Masks WDOG Register Masks
39713  * @{
39714  */
39715 
39716 /* WCR Bit Fields */
39717 #define WDOG_WCR_WDZST_MASK                      0x1u
39718 #define WDOG_WCR_WDZST_SHIFT                     0
39719 #define WDOG_WCR_WDBG_MASK                       0x2u
39720 #define WDOG_WCR_WDBG_SHIFT                      1
39721 #define WDOG_WCR_WDE_MASK                        0x4u
39722 #define WDOG_WCR_WDE_SHIFT                       2
39723 #define WDOG_WCR_WDT_MASK                        0x8u
39724 #define WDOG_WCR_WDT_SHIFT                       3
39725 #define WDOG_WCR_SRS_MASK                        0x10u
39726 #define WDOG_WCR_SRS_SHIFT                       4
39727 #define WDOG_WCR_WDA_MASK                        0x20u
39728 #define WDOG_WCR_WDA_SHIFT                       5
39729 #define WDOG_WCR_SRE_MASK                        0x40u
39730 #define WDOG_WCR_SRE_SHIFT                       6
39731 #define WDOG_WCR_WDW_MASK                        0x80u
39732 #define WDOG_WCR_WDW_SHIFT                       7
39733 #define WDOG_WCR_WT_MASK                         0xFF00u
39734 #define WDOG_WCR_WT_SHIFT                        8
39735 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x))<<WDOG_WCR_WT_SHIFT))&WDOG_WCR_WT_MASK)
39736 /* WSR Bit Fields */
39737 #define WDOG_WSR_WSR_MASK                        0xFFFFu
39738 #define WDOG_WSR_WSR_SHIFT                       0
39739 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_WSR_WSR_SHIFT))&WDOG_WSR_WSR_MASK)
39740 /* WRSR Bit Fields */
39741 #define WDOG_WRSR_SFTW_MASK                      0x1u
39742 #define WDOG_WRSR_SFTW_SHIFT                     0
39743 #define WDOG_WRSR_TOUT_MASK                      0x2u
39744 #define WDOG_WRSR_TOUT_SHIFT                     1
39745 #define WDOG_WRSR_POR_MASK                       0x10u
39746 #define WDOG_WRSR_POR_SHIFT                      4
39747 /* WICR Bit Fields */
39748 #define WDOG_WICR_WICT_MASK                      0xFFu
39749 #define WDOG_WICR_WICT_SHIFT                     0
39750 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x))<<WDOG_WICR_WICT_SHIFT))&WDOG_WICR_WICT_MASK)
39751 #define WDOG_WICR_WTIS_MASK                      0x4000u
39752 #define WDOG_WICR_WTIS_SHIFT                     14
39753 #define WDOG_WICR_WIE_MASK                       0x8000u
39754 #define WDOG_WICR_WIE_SHIFT                      15
39755 /* WMCR Bit Fields */
39756 #define WDOG_WMCR_PDE_MASK                       0x1u
39757 #define WDOG_WMCR_PDE_SHIFT                      0
39758 
39759 /*!
39760  * @}
39761  */ /* end of group WDOG_Register_Masks */
39762 
39763 /* WDOG - Peripheral instance base addresses */
39764 /** Peripheral WDOG1 base address */
39765 #define WDOG1_BASE                               (0x420BC000u)
39766 /** Peripheral WDOG1 base pointer */
39767 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
39768 #define WDOG1_BASE_PTR                           (WDOG1)
39769 /** Peripheral WDOG2 base address */
39770 #define WDOG2_BASE                               (0x420C0000u)
39771 /** Peripheral WDOG2 base pointer */
39772 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
39773 #define WDOG2_BASE_PTR                           (WDOG2)
39774 /** Peripheral WDOG3 base address */
39775 #define WDOG3_BASE                               (0x42288000u)
39776 /** Peripheral WDOG3 base pointer */
39777 #define WDOG3                                    ((WDOG_Type *)WDOG3_BASE)
39778 #define WDOG3_BASE_PTR                           (WDOG3)
39779 /** Array initializer of WDOG peripheral base addresses */
39780 #define WDOG_BASE_ADDRS                          { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE }
39781 /** Array initializer of WDOG peripheral base pointers */
39782 #define WDOG_BASE_PTRS                           { WDOG1, WDOG2, WDOG3 }
39783 /** Interrupt vectors for the WDOG peripheral type */
39784 #define WDOG_IRQS                                { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn }
39785 
39786 /* ----------------------------------------------------------------------------
39787    -- WDOG - Register accessor macros
39788    ---------------------------------------------------------------------------- */
39789 
39790 /*!
39791  * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
39792  * @{
39793  */
39794 
39795 /* WDOG - Register instance definitions */
39796 /* WDOG1 */
39797 #define WDOG1_WCR                                WDOG_WCR_REG(WDOG1_BASE_PTR)
39798 #define WDOG1_WSR                                WDOG_WSR_REG(WDOG1_BASE_PTR)
39799 #define WDOG1_WRSR                               WDOG_WRSR_REG(WDOG1_BASE_PTR)
39800 #define WDOG1_WICR                               WDOG_WICR_REG(WDOG1_BASE_PTR)
39801 #define WDOG1_WMCR                               WDOG_WMCR_REG(WDOG1_BASE_PTR)
39802 /* WDOG2 */
39803 #define WDOG2_WCR                                WDOG_WCR_REG(WDOG2_BASE_PTR)
39804 #define WDOG2_WSR                                WDOG_WSR_REG(WDOG2_BASE_PTR)
39805 #define WDOG2_WRSR                               WDOG_WRSR_REG(WDOG2_BASE_PTR)
39806 #define WDOG2_WICR                               WDOG_WICR_REG(WDOG2_BASE_PTR)
39807 #define WDOG2_WMCR                               WDOG_WMCR_REG(WDOG2_BASE_PTR)
39808 /* WDOG3 */
39809 #define WDOG3_WCR                                WDOG_WCR_REG(WDOG3_BASE_PTR)
39810 #define WDOG3_WSR                                WDOG_WSR_REG(WDOG3_BASE_PTR)
39811 #define WDOG3_WRSR                               WDOG_WRSR_REG(WDOG3_BASE_PTR)
39812 #define WDOG3_WICR                               WDOG_WICR_REG(WDOG3_BASE_PTR)
39813 #define WDOG3_WMCR                               WDOG_WMCR_REG(WDOG3_BASE_PTR)
39814 
39815 /*!
39816  * @}
39817  */ /* end of group WDOG_Register_Accessor_Macros */
39818 
39819 /*!
39820  * @}
39821  */ /* end of group WDOG_Peripheral */
39822 
39823 /* ----------------------------------------------------------------------------
39824    -- XTALOSC24M Peripheral Access Layer
39825    ---------------------------------------------------------------------------- */
39826 
39827 /*!
39828  * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer
39829  * @{
39830  */
39831 
39832 /** XTALOSC24M - Register Layout Typedef */
39833 typedef struct {
39834   uint8_t RESERVED_0[336];
39835   __IO  uint32_t MISC0;                                  /**< Miscellaneous Register 0, offset: 0x150 */
39836   uint8_t RESERVED_1[284];
39837   __IO  uint32_t LOWPWR_CTRL;                            /**< XTAL OSC (LP) Control Register, offset: 0x270 */
39838   __IO  uint32_t LOWPWR_CTRL_SET;                        /**< XTAL OSC (LP) Control Register, offset: 0x274 */
39839   __IO  uint32_t LOWPWR_CTRL_CLR;                        /**< XTAL OSC (LP) Control Register, offset: 0x278 */
39840   __IO  uint32_t LOWPWR_CTRL_TOG;                        /**< XTAL OSC (LP) Control Register, offset: 0x27C */
39841   uint8_t RESERVED_2[32];
39842   __IO  uint32_t OSC_CONFIG0;                            /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */
39843   __IO  uint32_t OSC_CONFIG0_SET;                        /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */
39844   __IO  uint32_t OSC_CONFIG0_CLR;                        /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */
39845   __IO  uint32_t OSC_CONFIG0_TOG;                        /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */
39846   __IO  uint32_t OSC_CONFIG1;                            /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */
39847   __IO  uint32_t OSC_CONFIG1_SET;                        /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */
39848   __IO  uint32_t OSC_CONFIG1_CLR;                        /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */
39849   __IO  uint32_t OSC_CONFIG1_TOG;                        /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */
39850   __IO  uint32_t OSC_CONFIG2;                            /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */
39851   __IO  uint32_t OSC_CONFIG2_SET;                        /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */
39852   __IO  uint32_t OSC_CONFIG2_CLR;                        /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */
39853   __IO  uint32_t OSC_CONFIG2_TOG;                        /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */
39854 } XTALOSC24M_Type, *XTALOSC24M_MemMapPtr;
39855 
39856 /* ----------------------------------------------------------------------------
39857    -- XTALOSC24M - Register accessor macros
39858    ---------------------------------------------------------------------------- */
39859 
39860 /*!
39861  * @addtogroup XTALOSC24M_Register_Accessor_Macros XTALOSC24M - Register accessor macros
39862  * @{
39863  */
39864 
39865 /* XTALOSC24M - Register accessors */
39866 #define XTALOSC24M_MISC0_REG(base)               ((base)->MISC0)
39867 #define XTALOSC24M_LOWPWR_CTRL_REG(base)         ((base)->LOWPWR_CTRL)
39868 #define XTALOSC24M_LOWPWR_CTRL_SET_REG(base)     ((base)->LOWPWR_CTRL_SET)
39869 #define XTALOSC24M_LOWPWR_CTRL_CLR_REG(base)     ((base)->LOWPWR_CTRL_CLR)
39870 #define XTALOSC24M_LOWPWR_CTRL_TOG_REG(base)     ((base)->LOWPWR_CTRL_TOG)
39871 #define XTALOSC24M_OSC_CONFIG0_REG(base)         ((base)->OSC_CONFIG0)
39872 #define XTALOSC24M_OSC_CONFIG0_SET_REG(base)     ((base)->OSC_CONFIG0_SET)
39873 #define XTALOSC24M_OSC_CONFIG0_CLR_REG(base)     ((base)->OSC_CONFIG0_CLR)
39874 #define XTALOSC24M_OSC_CONFIG0_TOG_REG(base)     ((base)->OSC_CONFIG0_TOG)
39875 #define XTALOSC24M_OSC_CONFIG1_REG(base)         ((base)->OSC_CONFIG1)
39876 #define XTALOSC24M_OSC_CONFIG1_SET_REG(base)     ((base)->OSC_CONFIG1_SET)
39877 #define XTALOSC24M_OSC_CONFIG1_CLR_REG(base)     ((base)->OSC_CONFIG1_CLR)
39878 #define XTALOSC24M_OSC_CONFIG1_TOG_REG(base)     ((base)->OSC_CONFIG1_TOG)
39879 #define XTALOSC24M_OSC_CONFIG2_REG(base)         ((base)->OSC_CONFIG2)
39880 #define XTALOSC24M_OSC_CONFIG2_SET_REG(base)     ((base)->OSC_CONFIG2_SET)
39881 #define XTALOSC24M_OSC_CONFIG2_CLR_REG(base)     ((base)->OSC_CONFIG2_CLR)
39882 #define XTALOSC24M_OSC_CONFIG2_TOG_REG(base)     ((base)->OSC_CONFIG2_TOG)
39883 
39884 /*!
39885  * @}
39886  */ /* end of group XTALOSC24M_Register_Accessor_Macros */
39887 
39888 /* ----------------------------------------------------------------------------
39889    -- XTALOSC24M Register Masks
39890    ---------------------------------------------------------------------------- */
39891 
39892 /*!
39893  * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks
39894  * @{
39895  */
39896 
39897 /* MISC0 Bit Fields */
39898 #define XTALOSC24M_MISC0_REFTOP_PWD_MASK         0x1u
39899 #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT        0
39900 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u
39901 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT 3
39902 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK      0x70u
39903 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT     4
39904 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT))&XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
39905 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK       0x80u
39906 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT      7
39907 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK   0xC00u
39908 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT  10
39909 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT))&XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
39910 #define XTALOSC24M_MISC0_RTC_RINGOSC_EN_MASK     0x1000u
39911 #define XTALOSC24M_MISC0_RTC_RINGOSC_EN_SHIFT    12
39912 #define XTALOSC24M_MISC0_OSC_I_MASK              0x6000u
39913 #define XTALOSC24M_MISC0_OSC_I_SHIFT             13
39914 #define XTALOSC24M_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_OSC_I_SHIFT))&XTALOSC24M_MISC0_OSC_I_MASK)
39915 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK         0x8000u
39916 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT        15
39917 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK      0x10000u
39918 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT     16
39919 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK       0x2000000u
39920 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT      25
39921 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK      0x1C000000u
39922 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT     26
39923 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT))&XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
39924 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK    0x20000000u
39925 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT   29
39926 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK       0x40000000u
39927 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT      30
39928 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK     0x80000000u
39929 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT    31
39930 /* LOWPWR_CTRL Bit Fields */
39931 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK    0x1u
39932 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT   0
39933 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK  0xEu
39934 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT 1
39935 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK)
39936 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK      0x10u
39937 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT     4
39938 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK     0x20u
39939 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT    5
39940 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK    0x40u
39941 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT   6
39942 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK 0x80u
39943 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT 7
39944 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK   0x100u
39945 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT  8
39946 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK   0x200u
39947 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT  9
39948 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK  0x400u
39949 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10
39950 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u
39951 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11
39952 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK 0x2000u
39953 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT 13
39954 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK 0xC000u
39955 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT 14
39956 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
39957 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK 0x10000u
39958 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT 16
39959 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK  0x20000u
39960 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 17
39961 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK  0x40000u
39962 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 18
39963 /* LOWPWR_CTRL_SET Bit Fields */
39964 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK 0x1u
39965 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT 0
39966 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK 0xEu
39967 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT 1
39968 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK)
39969 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK  0x10u
39970 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT 4
39971 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK 0x20u
39972 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT 5
39973 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK 0x40u
39974 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT 6
39975 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK 0x80u
39976 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT 7
39977 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u
39978 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8
39979 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u
39980 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9
39981 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u
39982 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10
39983 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
39984 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
39985 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK 0x2000u
39986 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT 13
39987 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK 0xC000u
39988 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT 14
39989 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
39990 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK 0x10000u
39991 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT 16
39992 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x20000u
39993 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 17
39994 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x40000u
39995 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 18
39996 /* LOWPWR_CTRL_CLR Bit Fields */
39997 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK 0x1u
39998 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT 0
39999 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK 0xEu
40000 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT 1
40001 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK)
40002 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK  0x10u
40003 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT 4
40004 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK 0x20u
40005 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT 5
40006 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK 0x40u
40007 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT 6
40008 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK 0x80u
40009 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT 7
40010 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u
40011 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8
40012 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u
40013 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9
40014 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u
40015 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10
40016 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
40017 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
40018 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK 0x2000u
40019 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT 13
40020 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK 0xC000u
40021 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT 14
40022 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
40023 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK 0x10000u
40024 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT 16
40025 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x20000u
40026 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 17
40027 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x40000u
40028 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 18
40029 /* LOWPWR_CTRL_TOG Bit Fields */
40030 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK 0x1u
40031 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT 0
40032 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK 0xEu
40033 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT 1
40034 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK)
40035 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK  0x10u
40036 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT 4
40037 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK 0x20u
40038 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT 5
40039 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK 0x40u
40040 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT 6
40041 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK 0x80u
40042 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT 7
40043 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u
40044 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8
40045 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u
40046 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9
40047 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u
40048 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10
40049 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
40050 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
40051 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK 0x2000u
40052 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT 13
40053 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK 0xC000u
40054 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT 14
40055 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
40056 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK 0x10000u
40057 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT 16
40058 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x20000u
40059 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 17
40060 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x40000u
40061 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 18
40062 /* OSC_CONFIG0 Bit Fields */
40063 #define XTALOSC24M_OSC_CONFIG0_START_MASK        0x1u
40064 #define XTALOSC24M_OSC_CONFIG0_START_SHIFT       0
40065 #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK       0x2u
40066 #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT      1
40067 #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK       0x4u
40068 #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT      2
40069 #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK       0x8u
40070 #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT      3
40071 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK  0xFF0u
40072 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4
40073 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x)    (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
40074 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK    0xF000u
40075 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT   12
40076 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x)      (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
40077 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK   0xF0000u
40078 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT  16
40079 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x)     (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
40080 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK 0xFF000000u
40081 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24
40082 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
40083 /* OSC_CONFIG0_SET Bit Fields */
40084 #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK    0x1u
40085 #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT   0
40086 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK   0x2u
40087 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT  1
40088 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK   0x4u
40089 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT  2
40090 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK   0x8u
40091 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT  3
40092 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK 0xFF0u
40093 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT 4
40094 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
40095 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK 0xF000u
40096 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT 12
40097 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
40098 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK 0xF0000u
40099 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT 16
40100 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
40101 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK 0xFF000000u
40102 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT 24
40103 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
40104 /* OSC_CONFIG0_CLR Bit Fields */
40105 #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK    0x1u
40106 #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT   0
40107 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK   0x2u
40108 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT  1
40109 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK   0x4u
40110 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT  2
40111 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK   0x8u
40112 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT  3
40113 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK 0xFF0u
40114 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT 4
40115 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
40116 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK 0xF000u
40117 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT 12
40118 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
40119 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK 0xF0000u
40120 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT 16
40121 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
40122 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK 0xFF000000u
40123 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT 24
40124 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
40125 /* OSC_CONFIG0_TOG Bit Fields */
40126 #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK    0x1u
40127 #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT   0
40128 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK   0x2u
40129 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT  1
40130 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK   0x4u
40131 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT  2
40132 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK   0x8u
40133 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT  3
40134 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK 0xFF0u
40135 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT 4
40136 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
40137 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK 0xF000u
40138 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT 12
40139 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
40140 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK 0xF0000u
40141 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT 16
40142 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
40143 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK 0xFF000000u
40144 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT 24
40145 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
40146 /* OSC_CONFIG1 Bit Fields */
40147 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK 0xFFFu
40148 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0
40149 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
40150 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK 0xFFF00000u
40151 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20
40152 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
40153 /* OSC_CONFIG1_SET Bit Fields */
40154 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK 0xFFFu
40155 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT 0
40156 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
40157 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK 0xFFF00000u
40158 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT 20
40159 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
40160 /* OSC_CONFIG1_CLR Bit Fields */
40161 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK 0xFFFu
40162 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT 0
40163 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
40164 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK 0xFFF00000u
40165 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT 20
40166 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
40167 /* OSC_CONFIG1_TOG Bit Fields */
40168 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK 0xFFFu
40169 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT 0
40170 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
40171 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK 0xFFF00000u
40172 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT 20
40173 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
40174 /* OSC_CONFIG2 Bit Fields */
40175 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xFFFu
40176 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0
40177 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x)   (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
40178 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK    0x10000u
40179 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT   16
40180 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK       0x20000u
40181 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT      17
40182 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK 0x80000000u
40183 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT 31
40184 /* OSC_CONFIG2_SET Bit Fields */
40185 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK 0xFFFu
40186 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT 0
40187 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
40188 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK 0x10000u
40189 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT 16
40190 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK   0x20000u
40191 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT  17
40192 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK 0x80000000u
40193 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT 31
40194 /* OSC_CONFIG2_CLR Bit Fields */
40195 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK 0xFFFu
40196 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT 0
40197 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
40198 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK 0x10000u
40199 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT 16
40200 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK   0x20000u
40201 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT  17
40202 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK 0x80000000u
40203 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT 31
40204 /* OSC_CONFIG2_TOG Bit Fields */
40205 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK 0xFFFu
40206 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT 0
40207 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
40208 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK 0x10000u
40209 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT 16
40210 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK   0x20000u
40211 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT  17
40212 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK 0x80000000u
40213 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT 31
40214 
40215 /*!
40216  * @}
40217  */ /* end of group XTALOSC24M_Register_Masks */
40218 
40219 /* XTALOSC24M - Peripheral instance base addresses */
40220 /** Peripheral XTALOSC24M base address */
40221 #define XTALOSC24M_BASE                          (0x420C8000u)
40222 /** Peripheral XTALOSC24M base pointer */
40223 #define XTALOSC24M                               ((XTALOSC24M_Type *)XTALOSC24M_BASE)
40224 #define XTALOSC24M_BASE_PTR                      (XTALOSC24M)
40225 /** Array initializer of XTALOSC24M peripheral base addresses */
40226 #define XTALOSC24M_BASE_ADDRS                    { XTALOSC24M_BASE }
40227 /** Array initializer of XTALOSC24M peripheral base pointers */
40228 #define XTALOSC24M_BASE_PTRS                     { XTALOSC24M }
40229 
40230 /* ----------------------------------------------------------------------------
40231    -- XTALOSC24M - Register accessor macros
40232    ---------------------------------------------------------------------------- */
40233 
40234 /*!
40235  * @addtogroup XTALOSC24M_Register_Accessor_Macros XTALOSC24M - Register accessor macros
40236  * @{
40237  */
40238 
40239 /* XTALOSC24M - Register instance definitions */
40240 /* XTALOSC24M */
40241 #define XTALOSC24M_MISC0                         XTALOSC24M_MISC0_REG(XTALOSC24M_BASE_PTR)
40242 #define XTALOSC24M_LOWPWR_CTRL                   XTALOSC24M_LOWPWR_CTRL_REG(XTALOSC24M_BASE_PTR)
40243 #define XTALOSC24M_LOWPWR_CTRL_SET               XTALOSC24M_LOWPWR_CTRL_SET_REG(XTALOSC24M_BASE_PTR)
40244 #define XTALOSC24M_LOWPWR_CTRL_CLR               XTALOSC24M_LOWPWR_CTRL_CLR_REG(XTALOSC24M_BASE_PTR)
40245 #define XTALOSC24M_LOWPWR_CTRL_TOG               XTALOSC24M_LOWPWR_CTRL_TOG_REG(XTALOSC24M_BASE_PTR)
40246 #define XTALOSC24M_OSC_CONFIG0                   XTALOSC24M_OSC_CONFIG0_REG(XTALOSC24M_BASE_PTR)
40247 #define XTALOSC24M_OSC_CONFIG0_SET               XTALOSC24M_OSC_CONFIG0_SET_REG(XTALOSC24M_BASE_PTR)
40248 #define XTALOSC24M_OSC_CONFIG0_CLR               XTALOSC24M_OSC_CONFIG0_CLR_REG(XTALOSC24M_BASE_PTR)
40249 #define XTALOSC24M_OSC_CONFIG0_TOG               XTALOSC24M_OSC_CONFIG0_TOG_REG(XTALOSC24M_BASE_PTR)
40250 #define XTALOSC24M_OSC_CONFIG1                   XTALOSC24M_OSC_CONFIG1_REG(XTALOSC24M_BASE_PTR)
40251 #define XTALOSC24M_OSC_CONFIG1_SET               XTALOSC24M_OSC_CONFIG1_SET_REG(XTALOSC24M_BASE_PTR)
40252 #define XTALOSC24M_OSC_CONFIG1_CLR               XTALOSC24M_OSC_CONFIG1_CLR_REG(XTALOSC24M_BASE_PTR)
40253 #define XTALOSC24M_OSC_CONFIG1_TOG               XTALOSC24M_OSC_CONFIG1_TOG_REG(XTALOSC24M_BASE_PTR)
40254 #define XTALOSC24M_OSC_CONFIG2                   XTALOSC24M_OSC_CONFIG2_REG(XTALOSC24M_BASE_PTR)
40255 #define XTALOSC24M_OSC_CONFIG2_SET               XTALOSC24M_OSC_CONFIG2_SET_REG(XTALOSC24M_BASE_PTR)
40256 #define XTALOSC24M_OSC_CONFIG2_CLR               XTALOSC24M_OSC_CONFIG2_CLR_REG(XTALOSC24M_BASE_PTR)
40257 #define XTALOSC24M_OSC_CONFIG2_TOG               XTALOSC24M_OSC_CONFIG2_TOG_REG(XTALOSC24M_BASE_PTR)
40258 
40259 /*!
40260  * @}
40261  */ /* end of group XTALOSC24M_Register_Accessor_Macros */
40262 
40263 /*!
40264  * @}
40265  */ /* end of group XTALOSC24M_Peripheral */
40266 
40267 /* ----------------------------------------------------------------------------
40268    -- uSDHC Peripheral Access Layer
40269    ---------------------------------------------------------------------------- */
40270 
40271 /*!
40272  * @addtogroup uSDHC_Peripheral_Access_Layer uSDHC Peripheral Access Layer
40273  * @{
40274  */
40275 
40276 /** uSDHC - Register Layout Typedef */
40277 typedef struct {
40278   __IO  uint32_t DS_ADDR;                                /**< DMA System Address, offset: 0x0 */
40279   __IO  uint32_t BLK_ATT;                                /**< Block Attributes, offset: 0x4 */
40280   __IO  uint32_t CMD_ARG;                                /**< Command Argument, offset: 0x8 */
40281   __IO  uint32_t CMD_XFR_TYP;                            /**< Command Transfer Type, offset: 0xC */
40282   __I   uint32_t CMD_RSP0;                               /**< Command Response0, offset: 0x10 */
40283   __I   uint32_t CMD_RSP1;                               /**< Command Response1, offset: 0x14 */
40284   __I   uint32_t CMD_RSP2;                               /**< Command Response2, offset: 0x18 */
40285   __I   uint32_t CMD_RSP3;                               /**< Command Response3, offset: 0x1C */
40286   __IO  uint32_t DATA_BUFF_ACC_PORT;                     /**< Data Buffer Access Port, offset: 0x20 */
40287   __I   uint32_t PRES_STATE;                             /**< Present State, offset: 0x24 */
40288   __IO  uint32_t PROT_CTRL;                              /**< Protocol Control, offset: 0x28 */
40289   __IO  uint32_t SYS_CTRL;                               /**< System Control, offset: 0x2C */
40290   __IO  uint32_t INT_STATUS;                             /**< Interrupt Status, offset: 0x30 */
40291   __IO  uint32_t INT_STATUS_EN;                          /**< Interrupt Status Enable, offset: 0x34 */
40292   __IO  uint32_t INT_SIGNAL_EN;                          /**< Interrupt Signal Enable, offset: 0x38 */
40293   __I   uint32_t AUTOCMD12_ERR_STATUS;                   /**< Auto CMD12 Error Status, offset: 0x3C */
40294   __I   uint32_t HOST_CTRL_CAP;                          /**< Host Controller Capabilities, offset: 0x40 */
40295   __IO  uint32_t WTMK_LVL;                               /**< Watermark Level, offset: 0x44 */
40296   __IO  uint32_t MIX_CTRL;                               /**< Mixer Control, offset: 0x48 */
40297   uint8_t RESERVED_0[4];
40298   __O   uint32_t FORCE_EVENT;                            /**< Force Event, offset: 0x50 */
40299   __I   uint32_t ADMA_ERR_STATUS;                        /**< ADMA Error Status Register, offset: 0x54 */
40300   __IO  uint32_t ADMA_SYS_ADDR;                          /**< ADMA System Address, offset: 0x58 */
40301   uint8_t RESERVED_1[4];
40302   __IO  uint32_t DLL_CTRL;                               /**< DLL (Delay Line) Control, offset: 0x60 */
40303   __I   uint32_t DLL_STATUS;                             /**< DLL Status, offset: 0x64 */
40304   __IO  uint32_t CLK_TUNE_CTRL_STATUS;                   /**< CLK Tuning Control and Status, offset: 0x68 */
40305   uint8_t RESERVED_2[84];
40306   __IO  uint32_t VEND_SPEC;                              /**< Vendor Specific Register, offset: 0xC0 */
40307   __IO  uint32_t MMC_BOOT;                               /**< MMC Boot Register, offset: 0xC4 */
40308   __IO  uint32_t VEND_SPEC2;                             /**< Vendor Specific 2 Register, offset: 0xC8 */
40309   __IO  uint32_t TUNING_CTRL;                            /**< Tuning Control Register, offset: 0xCC */
40310 } uSDHC_Type, *uSDHC_MemMapPtr;
40311 
40312 /* ----------------------------------------------------------------------------
40313    -- uSDHC - Register accessor macros
40314    ---------------------------------------------------------------------------- */
40315 
40316 /*!
40317  * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros
40318  * @{
40319  */
40320 
40321 /* uSDHC - Register accessors */
40322 #define uSDHC_DS_ADDR_REG(base)                  ((base)->DS_ADDR)
40323 #define uSDHC_BLK_ATT_REG(base)                  ((base)->BLK_ATT)
40324 #define uSDHC_CMD_ARG_REG(base)                  ((base)->CMD_ARG)
40325 #define uSDHC_CMD_XFR_TYP_REG(base)              ((base)->CMD_XFR_TYP)
40326 #define uSDHC_CMD_RSP0_REG(base)                 ((base)->CMD_RSP0)
40327 #define uSDHC_CMD_RSP1_REG(base)                 ((base)->CMD_RSP1)
40328 #define uSDHC_CMD_RSP2_REG(base)                 ((base)->CMD_RSP2)
40329 #define uSDHC_CMD_RSP3_REG(base)                 ((base)->CMD_RSP3)
40330 #define uSDHC_DATA_BUFF_ACC_PORT_REG(base)       ((base)->DATA_BUFF_ACC_PORT)
40331 #define uSDHC_PRES_STATE_REG(base)               ((base)->PRES_STATE)
40332 #define uSDHC_PROT_CTRL_REG(base)                ((base)->PROT_CTRL)
40333 #define uSDHC_SYS_CTRL_REG(base)                 ((base)->SYS_CTRL)
40334 #define uSDHC_INT_STATUS_REG(base)               ((base)->INT_STATUS)
40335 #define uSDHC_INT_STATUS_EN_REG(base)            ((base)->INT_STATUS_EN)
40336 #define uSDHC_INT_SIGNAL_EN_REG(base)            ((base)->INT_SIGNAL_EN)
40337 #define uSDHC_AUTOCMD12_ERR_STATUS_REG(base)     ((base)->AUTOCMD12_ERR_STATUS)
40338 #define uSDHC_HOST_CTRL_CAP_REG(base)            ((base)->HOST_CTRL_CAP)
40339 #define uSDHC_WTMK_LVL_REG(base)                 ((base)->WTMK_LVL)
40340 #define uSDHC_MIX_CTRL_REG(base)                 ((base)->MIX_CTRL)
40341 #define uSDHC_FORCE_EVENT_REG(base)              ((base)->FORCE_EVENT)
40342 #define uSDHC_ADMA_ERR_STATUS_REG(base)          ((base)->ADMA_ERR_STATUS)
40343 #define uSDHC_ADMA_SYS_ADDR_REG(base)            ((base)->ADMA_SYS_ADDR)
40344 #define uSDHC_DLL_CTRL_REG(base)                 ((base)->DLL_CTRL)
40345 #define uSDHC_DLL_STATUS_REG(base)               ((base)->DLL_STATUS)
40346 #define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base)     ((base)->CLK_TUNE_CTRL_STATUS)
40347 #define uSDHC_VEND_SPEC_REG(base)                ((base)->VEND_SPEC)
40348 #define uSDHC_MMC_BOOT_REG(base)                 ((base)->MMC_BOOT)
40349 #define uSDHC_VEND_SPEC2_REG(base)               ((base)->VEND_SPEC2)
40350 #define uSDHC_TUNING_CTRL_REG(base)              ((base)->TUNING_CTRL)
40351 
40352 /*!
40353  * @}
40354  */ /* end of group uSDHC_Register_Accessor_Macros */
40355 
40356 /* ----------------------------------------------------------------------------
40357    -- uSDHC Register Masks
40358    ---------------------------------------------------------------------------- */
40359 
40360 /*!
40361  * @addtogroup uSDHC_Register_Masks uSDHC Register Masks
40362  * @{
40363  */
40364 
40365 /* DS_ADDR Bit Fields */
40366 #define uSDHC_DS_ADDR_DS_ADDR_MASK               0xFFFFFFFCu
40367 #define uSDHC_DS_ADDR_DS_ADDR_SHIFT              2
40368 #define uSDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_DS_ADDR_DS_ADDR_SHIFT))&uSDHC_DS_ADDR_DS_ADDR_MASK)
40369 /* BLK_ATT Bit Fields */
40370 #define uSDHC_BLK_ATT_BLKSIZE_MASK               0x1FFFu
40371 #define uSDHC_BLK_ATT_BLKSIZE_SHIFT              0
40372 #define uSDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKSIZE_SHIFT))&uSDHC_BLK_ATT_BLKSIZE_MASK)
40373 #define uSDHC_BLK_ATT_BLKCNT_MASK                0xFFFF0000u
40374 #define uSDHC_BLK_ATT_BLKCNT_SHIFT               16
40375 #define uSDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKCNT_SHIFT))&uSDHC_BLK_ATT_BLKCNT_MASK)
40376 /* CMD_ARG Bit Fields */
40377 #define uSDHC_CMD_ARG_CMDARG_MASK                0xFFFFFFFFu
40378 #define uSDHC_CMD_ARG_CMDARG_SHIFT               0
40379 #define uSDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_ARG_CMDARG_SHIFT))&uSDHC_CMD_ARG_CMDARG_MASK)
40380 /* CMD_XFR_TYP Bit Fields */
40381 #define uSDHC_CMD_XFR_TYP_RSPTYP_MASK            0x30000u
40382 #define uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT           16
40383 #define uSDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT))&uSDHC_CMD_XFR_TYP_RSPTYP_MASK)
40384 #define uSDHC_CMD_XFR_TYP_CCCEN_MASK             0x80000u
40385 #define uSDHC_CMD_XFR_TYP_CCCEN_SHIFT            19
40386 #define uSDHC_CMD_XFR_TYP_CICEN_MASK             0x100000u
40387 #define uSDHC_CMD_XFR_TYP_CICEN_SHIFT            20
40388 #define uSDHC_CMD_XFR_TYP_DPSEL_MASK             0x200000u
40389 #define uSDHC_CMD_XFR_TYP_DPSEL_SHIFT            21
40390 #define uSDHC_CMD_XFR_TYP_CMDTYP_MASK            0xC00000u
40391 #define uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT           22
40392 #define uSDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT))&uSDHC_CMD_XFR_TYP_CMDTYP_MASK)
40393 #define uSDHC_CMD_XFR_TYP_CMDINX_MASK            0x3F000000u
40394 #define uSDHC_CMD_XFR_TYP_CMDINX_SHIFT           24
40395 #define uSDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDINX_SHIFT))&uSDHC_CMD_XFR_TYP_CMDINX_MASK)
40396 /* CMD_RSP0 Bit Fields */
40397 #define uSDHC_CMD_RSP0_CMDRSP0_MASK              0xFFFFFFFFu
40398 #define uSDHC_CMD_RSP0_CMDRSP0_SHIFT             0
40399 #define uSDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP0_CMDRSP0_SHIFT))&uSDHC_CMD_RSP0_CMDRSP0_MASK)
40400 /* CMD_RSP1 Bit Fields */
40401 #define uSDHC_CMD_RSP1_CMDRSP1_MASK              0xFFFFFFFFu
40402 #define uSDHC_CMD_RSP1_CMDRSP1_SHIFT             0
40403 #define uSDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP1_CMDRSP1_SHIFT))&uSDHC_CMD_RSP1_CMDRSP1_MASK)
40404 /* CMD_RSP2 Bit Fields */
40405 #define uSDHC_CMD_RSP2_CMDRSP2_MASK              0xFFFFFFFFu
40406 #define uSDHC_CMD_RSP2_CMDRSP2_SHIFT             0
40407 #define uSDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP2_CMDRSP2_SHIFT))&uSDHC_CMD_RSP2_CMDRSP2_MASK)
40408 /* CMD_RSP3 Bit Fields */
40409 #define uSDHC_CMD_RSP3_CMDRSP3_MASK              0xFFFFFFFFu
40410 #define uSDHC_CMD_RSP3_CMDRSP3_SHIFT             0
40411 #define uSDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP3_CMDRSP3_SHIFT))&uSDHC_CMD_RSP3_CMDRSP3_MASK)
40412 /* DATA_BUFF_ACC_PORT Bit Fields */
40413 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    0xFFFFFFFFu
40414 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   0
40415 #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT))&uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
40416 /* PRES_STATE Bit Fields */
40417 #define uSDHC_PRES_STATE_CIHB_MASK               0x1u
40418 #define uSDHC_PRES_STATE_CIHB_SHIFT              0
40419 #define uSDHC_PRES_STATE_CDIHB_MASK              0x2u
40420 #define uSDHC_PRES_STATE_CDIHB_SHIFT             1
40421 #define uSDHC_PRES_STATE_DLA_MASK                0x4u
40422 #define uSDHC_PRES_STATE_DLA_SHIFT               2
40423 #define uSDHC_PRES_STATE_SDSTB_MASK              0x8u
40424 #define uSDHC_PRES_STATE_SDSTB_SHIFT             3
40425 #define uSDHC_PRES_STATE_IPGOFF_MASK             0x10u
40426 #define uSDHC_PRES_STATE_IPGOFF_SHIFT            4
40427 #define uSDHC_PRES_STATE_HCKOFF_MASK             0x20u
40428 #define uSDHC_PRES_STATE_HCKOFF_SHIFT            5
40429 #define uSDHC_PRES_STATE_PEROFF_MASK             0x40u
40430 #define uSDHC_PRES_STATE_PEROFF_SHIFT            6
40431 #define uSDHC_PRES_STATE_SDOFF_MASK              0x80u
40432 #define uSDHC_PRES_STATE_SDOFF_SHIFT             7
40433 #define uSDHC_PRES_STATE_WTA_MASK                0x100u
40434 #define uSDHC_PRES_STATE_WTA_SHIFT               8
40435 #define uSDHC_PRES_STATE_RTA_MASK                0x200u
40436 #define uSDHC_PRES_STATE_RTA_SHIFT               9
40437 #define uSDHC_PRES_STATE_BWEN_MASK               0x400u
40438 #define uSDHC_PRES_STATE_BWEN_SHIFT              10
40439 #define uSDHC_PRES_STATE_BREN_MASK               0x800u
40440 #define uSDHC_PRES_STATE_BREN_SHIFT              11
40441 #define uSDHC_PRES_STATE_RTR_MASK                0x1000u
40442 #define uSDHC_PRES_STATE_RTR_SHIFT               12
40443 #define uSDHC_PRES_STATE_TSCD_MASK               0x8000u
40444 #define uSDHC_PRES_STATE_TSCD_SHIFT              15
40445 #define uSDHC_PRES_STATE_CINST_MASK              0x10000u
40446 #define uSDHC_PRES_STATE_CINST_SHIFT             16
40447 #define uSDHC_PRES_STATE_CDPL_MASK               0x40000u
40448 #define uSDHC_PRES_STATE_CDPL_SHIFT              18
40449 #define uSDHC_PRES_STATE_WPSPL_MASK              0x80000u
40450 #define uSDHC_PRES_STATE_WPSPL_SHIFT             19
40451 #define uSDHC_PRES_STATE_CLSL_MASK               0x800000u
40452 #define uSDHC_PRES_STATE_CLSL_SHIFT              23
40453 #define uSDHC_PRES_STATE_DLSL_MASK               0xFF000000u
40454 #define uSDHC_PRES_STATE_DLSL_SHIFT              24
40455 #define uSDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_PRES_STATE_DLSL_SHIFT))&uSDHC_PRES_STATE_DLSL_MASK)
40456 /* PROT_CTRL Bit Fields */
40457 #define uSDHC_PROT_CTRL_LCTL_MASK                0x1u
40458 #define uSDHC_PROT_CTRL_LCTL_SHIFT               0
40459 #define uSDHC_PROT_CTRL_DTW_MASK                 0x6u
40460 #define uSDHC_PROT_CTRL_DTW_SHIFT                1
40461 #define uSDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DTW_SHIFT))&uSDHC_PROT_CTRL_DTW_MASK)
40462 #define uSDHC_PROT_CTRL_D3CD_MASK                0x8u
40463 #define uSDHC_PROT_CTRL_D3CD_SHIFT               3
40464 #define uSDHC_PROT_CTRL_EMODE_MASK               0x30u
40465 #define uSDHC_PROT_CTRL_EMODE_SHIFT              4
40466 #define uSDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_EMODE_SHIFT))&uSDHC_PROT_CTRL_EMODE_MASK)
40467 #define uSDHC_PROT_CTRL_CDTL_MASK                0x40u
40468 #define uSDHC_PROT_CTRL_CDTL_SHIFT               6
40469 #define uSDHC_PROT_CTRL_CDSS_MASK                0x80u
40470 #define uSDHC_PROT_CTRL_CDSS_SHIFT               7
40471 #define uSDHC_PROT_CTRL_DMASEL_MASK              0x300u
40472 #define uSDHC_PROT_CTRL_DMASEL_SHIFT             8
40473 #define uSDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DMASEL_SHIFT))&uSDHC_PROT_CTRL_DMASEL_MASK)
40474 #define uSDHC_PROT_CTRL_SABGREQ_MASK             0x10000u
40475 #define uSDHC_PROT_CTRL_SABGREQ_SHIFT            16
40476 #define uSDHC_PROT_CTRL_CREQ_MASK                0x20000u
40477 #define uSDHC_PROT_CTRL_CREQ_SHIFT               17
40478 #define uSDHC_PROT_CTRL_RWCTL_MASK               0x40000u
40479 #define uSDHC_PROT_CTRL_RWCTL_SHIFT              18
40480 #define uSDHC_PROT_CTRL_IABG_MASK                0x80000u
40481 #define uSDHC_PROT_CTRL_IABG_SHIFT               19
40482 #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     0x100000u
40483 #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    20
40484 #define uSDHC_PROT_CTRL_WECINT_MASK              0x1000000u
40485 #define uSDHC_PROT_CTRL_WECINT_SHIFT             24
40486 #define uSDHC_PROT_CTRL_WECINS_MASK              0x2000000u
40487 #define uSDHC_PROT_CTRL_WECINS_SHIFT             25
40488 #define uSDHC_PROT_CTRL_WECRM_MASK               0x4000000u
40489 #define uSDHC_PROT_CTRL_WECRM_SHIFT              26
40490 #define uSDHC_PROT_CTRL_BURST_LEN_EN_MASK        0x38000000u
40491 #define uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       27
40492 #define uSDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT))&uSDHC_PROT_CTRL_BURST_LEN_EN_MASK)
40493 #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    0x40000000u
40494 #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   30
40495 /* SYS_CTRL Bit Fields */
40496 #define uSDHC_SYS_CTRL_DVS_MASK                  0xF0u
40497 #define uSDHC_SYS_CTRL_DVS_SHIFT                 4
40498 #define uSDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DVS_SHIFT))&uSDHC_SYS_CTRL_DVS_MASK)
40499 #define uSDHC_SYS_CTRL_SDCLKFS_MASK              0xFF00u
40500 #define uSDHC_SYS_CTRL_SDCLKFS_SHIFT             8
40501 #define uSDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_SDCLKFS_SHIFT))&uSDHC_SYS_CTRL_SDCLKFS_MASK)
40502 #define uSDHC_SYS_CTRL_DTOCV_MASK                0xF0000u
40503 #define uSDHC_SYS_CTRL_DTOCV_SHIFT               16
40504 #define uSDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DTOCV_SHIFT))&uSDHC_SYS_CTRL_DTOCV_MASK)
40505 #define uSDHC_SYS_CTRL_IPP_RST_N_MASK            0x800000u
40506 #define uSDHC_SYS_CTRL_IPP_RST_N_SHIFT           23
40507 #define uSDHC_SYS_CTRL_RSTA_MASK                 0x1000000u
40508 #define uSDHC_SYS_CTRL_RSTA_SHIFT                24
40509 #define uSDHC_SYS_CTRL_RSTC_MASK                 0x2000000u
40510 #define uSDHC_SYS_CTRL_RSTC_SHIFT                25
40511 #define uSDHC_SYS_CTRL_RSTD_MASK                 0x4000000u
40512 #define uSDHC_SYS_CTRL_RSTD_SHIFT                26
40513 #define uSDHC_SYS_CTRL_INITA_MASK                0x8000000u
40514 #define uSDHC_SYS_CTRL_INITA_SHIFT               27
40515 #define uSDHC_SYS_CTRL_RSTT_MASK                 0x10000000u
40516 #define uSDHC_SYS_CTRL_RSTT_SHIFT                28
40517 /* INT_STATUS Bit Fields */
40518 #define uSDHC_INT_STATUS_CC_MASK                 0x1u
40519 #define uSDHC_INT_STATUS_CC_SHIFT                0
40520 #define uSDHC_INT_STATUS_TC_MASK                 0x2u
40521 #define uSDHC_INT_STATUS_TC_SHIFT                1
40522 #define uSDHC_INT_STATUS_BGE_MASK                0x4u
40523 #define uSDHC_INT_STATUS_BGE_SHIFT               2
40524 #define uSDHC_INT_STATUS_DINT_MASK               0x8u
40525 #define uSDHC_INT_STATUS_DINT_SHIFT              3
40526 #define uSDHC_INT_STATUS_BWR_MASK                0x10u
40527 #define uSDHC_INT_STATUS_BWR_SHIFT               4
40528 #define uSDHC_INT_STATUS_BRR_MASK                0x20u
40529 #define uSDHC_INT_STATUS_BRR_SHIFT               5
40530 #define uSDHC_INT_STATUS_CINS_MASK               0x40u
40531 #define uSDHC_INT_STATUS_CINS_SHIFT              6
40532 #define uSDHC_INT_STATUS_CRM_MASK                0x80u
40533 #define uSDHC_INT_STATUS_CRM_SHIFT               7
40534 #define uSDHC_INT_STATUS_CINT_MASK               0x100u
40535 #define uSDHC_INT_STATUS_CINT_SHIFT              8
40536 #define uSDHC_INT_STATUS_RTE_MASK                0x1000u
40537 #define uSDHC_INT_STATUS_RTE_SHIFT               12
40538 #define uSDHC_INT_STATUS_TP_MASK                 0x4000u
40539 #define uSDHC_INT_STATUS_TP_SHIFT                14
40540 #define uSDHC_INT_STATUS_CTOE_MASK               0x10000u
40541 #define uSDHC_INT_STATUS_CTOE_SHIFT              16
40542 #define uSDHC_INT_STATUS_CCE_MASK                0x20000u
40543 #define uSDHC_INT_STATUS_CCE_SHIFT               17
40544 #define uSDHC_INT_STATUS_CEBE_MASK               0x40000u
40545 #define uSDHC_INT_STATUS_CEBE_SHIFT              18
40546 #define uSDHC_INT_STATUS_CIE_MASK                0x80000u
40547 #define uSDHC_INT_STATUS_CIE_SHIFT               19
40548 #define uSDHC_INT_STATUS_DTOE_MASK               0x100000u
40549 #define uSDHC_INT_STATUS_DTOE_SHIFT              20
40550 #define uSDHC_INT_STATUS_DCE_MASK                0x200000u
40551 #define uSDHC_INT_STATUS_DCE_SHIFT               21
40552 #define uSDHC_INT_STATUS_DEBE_MASK               0x400000u
40553 #define uSDHC_INT_STATUS_DEBE_SHIFT              22
40554 #define uSDHC_INT_STATUS_AC12E_MASK              0x1000000u
40555 #define uSDHC_INT_STATUS_AC12E_SHIFT             24
40556 #define uSDHC_INT_STATUS_TNE_MASK                0x4000000u
40557 #define uSDHC_INT_STATUS_TNE_SHIFT               26
40558 #define uSDHC_INT_STATUS_DMAE_MASK               0x10000000u
40559 #define uSDHC_INT_STATUS_DMAE_SHIFT              28
40560 /* INT_STATUS_EN Bit Fields */
40561 #define uSDHC_INT_STATUS_EN_CCSEN_MASK           0x1u
40562 #define uSDHC_INT_STATUS_EN_CCSEN_SHIFT          0
40563 #define uSDHC_INT_STATUS_EN_TCSEN_MASK           0x2u
40564 #define uSDHC_INT_STATUS_EN_TCSEN_SHIFT          1
40565 #define uSDHC_INT_STATUS_EN_BGESEN_MASK          0x4u
40566 #define uSDHC_INT_STATUS_EN_BGESEN_SHIFT         2
40567 #define uSDHC_INT_STATUS_EN_DINTSEN_MASK         0x8u
40568 #define uSDHC_INT_STATUS_EN_DINTSEN_SHIFT        3
40569 #define uSDHC_INT_STATUS_EN_BWRSEN_MASK          0x10u
40570 #define uSDHC_INT_STATUS_EN_BWRSEN_SHIFT         4
40571 #define uSDHC_INT_STATUS_EN_BRRSEN_MASK          0x20u
40572 #define uSDHC_INT_STATUS_EN_BRRSEN_SHIFT         5
40573 #define uSDHC_INT_STATUS_EN_CINSSEN_MASK         0x40u
40574 #define uSDHC_INT_STATUS_EN_CINSSEN_SHIFT        6
40575 #define uSDHC_INT_STATUS_EN_CRMSEN_MASK          0x80u
40576 #define uSDHC_INT_STATUS_EN_CRMSEN_SHIFT         7
40577 #define uSDHC_INT_STATUS_EN_CINTSEN_MASK         0x100u
40578 #define uSDHC_INT_STATUS_EN_CINTSEN_SHIFT        8
40579 #define uSDHC_INT_STATUS_EN_RTESEN_MASK          0x1000u
40580 #define uSDHC_INT_STATUS_EN_RTESEN_SHIFT         12
40581 #define uSDHC_INT_STATUS_EN_TPSEN_MASK           0x4000u
40582 #define uSDHC_INT_STATUS_EN_TPSEN_SHIFT          14
40583 #define uSDHC_INT_STATUS_EN_CTOESEN_MASK         0x10000u
40584 #define uSDHC_INT_STATUS_EN_CTOESEN_SHIFT        16
40585 #define uSDHC_INT_STATUS_EN_CCESEN_MASK          0x20000u
40586 #define uSDHC_INT_STATUS_EN_CCESEN_SHIFT         17
40587 #define uSDHC_INT_STATUS_EN_CEBESEN_MASK         0x40000u
40588 #define uSDHC_INT_STATUS_EN_CEBESEN_SHIFT        18
40589 #define uSDHC_INT_STATUS_EN_CIESEN_MASK          0x80000u
40590 #define uSDHC_INT_STATUS_EN_CIESEN_SHIFT         19
40591 #define uSDHC_INT_STATUS_EN_DTOESEN_MASK         0x100000u
40592 #define uSDHC_INT_STATUS_EN_DTOESEN_SHIFT        20
40593 #define uSDHC_INT_STATUS_EN_DCESEN_MASK          0x200000u
40594 #define uSDHC_INT_STATUS_EN_DCESEN_SHIFT         21
40595 #define uSDHC_INT_STATUS_EN_DEBESEN_MASK         0x400000u
40596 #define uSDHC_INT_STATUS_EN_DEBESEN_SHIFT        22
40597 #define uSDHC_INT_STATUS_EN_AC12ESEN_MASK        0x1000000u
40598 #define uSDHC_INT_STATUS_EN_AC12ESEN_SHIFT       24
40599 #define uSDHC_INT_STATUS_EN_TNESEN_MASK          0x4000000u
40600 #define uSDHC_INT_STATUS_EN_TNESEN_SHIFT         26
40601 #define uSDHC_INT_STATUS_EN_DMAESEN_MASK         0x10000000u
40602 #define uSDHC_INT_STATUS_EN_DMAESEN_SHIFT        28
40603 /* INT_SIGNAL_EN Bit Fields */
40604 #define uSDHC_INT_SIGNAL_EN_CCIEN_MASK           0x1u
40605 #define uSDHC_INT_SIGNAL_EN_CCIEN_SHIFT          0
40606 #define uSDHC_INT_SIGNAL_EN_TCIEN_MASK           0x2u
40607 #define uSDHC_INT_SIGNAL_EN_TCIEN_SHIFT          1
40608 #define uSDHC_INT_SIGNAL_EN_BGEIEN_MASK          0x4u
40609 #define uSDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         2
40610 #define uSDHC_INT_SIGNAL_EN_DINTIEN_MASK         0x8u
40611 #define uSDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        3
40612 #define uSDHC_INT_SIGNAL_EN_BWRIEN_MASK          0x10u
40613 #define uSDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         4
40614 #define uSDHC_INT_SIGNAL_EN_BRRIEN_MASK          0x20u
40615 #define uSDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         5
40616 #define uSDHC_INT_SIGNAL_EN_CINSIEN_MASK         0x40u
40617 #define uSDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        6
40618 #define uSDHC_INT_SIGNAL_EN_CRMIEN_MASK          0x80u
40619 #define uSDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         7
40620 #define uSDHC_INT_SIGNAL_EN_CINTIEN_MASK         0x100u
40621 #define uSDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        8
40622 #define uSDHC_INT_SIGNAL_EN_RTEIEN_MASK          0x1000u
40623 #define uSDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         12
40624 #define uSDHC_INT_SIGNAL_EN_TPIEN_MASK           0x4000u
40625 #define uSDHC_INT_SIGNAL_EN_TPIEN_SHIFT          14
40626 #define uSDHC_INT_SIGNAL_EN_CTOEIEN_MASK         0x10000u
40627 #define uSDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        16
40628 #define uSDHC_INT_SIGNAL_EN_CCEIEN_MASK          0x20000u
40629 #define uSDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         17
40630 #define uSDHC_INT_SIGNAL_EN_CEBEIEN_MASK         0x40000u
40631 #define uSDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        18
40632 #define uSDHC_INT_SIGNAL_EN_CIEIEN_MASK          0x80000u
40633 #define uSDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         19
40634 #define uSDHC_INT_SIGNAL_EN_DTOEIEN_MASK         0x100000u
40635 #define uSDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        20
40636 #define uSDHC_INT_SIGNAL_EN_DCEIEN_MASK          0x200000u
40637 #define uSDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         21
40638 #define uSDHC_INT_SIGNAL_EN_DEBEIEN_MASK         0x400000u
40639 #define uSDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        22
40640 #define uSDHC_INT_SIGNAL_EN_AC12EIEN_MASK        0x1000000u
40641 #define uSDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       24
40642 #define uSDHC_INT_SIGNAL_EN_TNEIEN_MASK          0x4000000u
40643 #define uSDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         26
40644 #define uSDHC_INT_SIGNAL_EN_DMAEIEN_MASK         0x10000000u
40645 #define uSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        28
40646 /* AUTOCMD12_ERR_STATUS Bit Fields */
40647 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   0x1u
40648 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  0
40649 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  0x2u
40650 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT 1
40651 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  0x4u
40652 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT 2
40653 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   0x8u
40654 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  3
40655 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   0x10u
40656 #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  4
40657 #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK 0x80u
40658 #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT 7
40659 #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK 0x400000u
40660 #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT 22
40661 #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK 0x800000u
40662 #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT 23
40663 /* HOST_CTRL_CAP Bit Fields */
40664 #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   0x1u
40665 #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  0
40666 #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  0x2u
40667 #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT 1
40668 #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   0x4u
40669 #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  2
40670 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK 0xF00u
40671 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT 8
40672 #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT))&uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
40673 #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK 0x2000u
40674 #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT 13
40675 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   0xC000u
40676 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  14
40677 #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT))&uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
40678 #define uSDHC_HOST_CTRL_CAP_MBL_MASK             0x70000u
40679 #define uSDHC_HOST_CTRL_CAP_MBL_SHIFT            16
40680 #define uSDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_MBL_SHIFT))&uSDHC_HOST_CTRL_CAP_MBL_MASK)
40681 #define uSDHC_HOST_CTRL_CAP_ADMAS_MASK           0x100000u
40682 #define uSDHC_HOST_CTRL_CAP_ADMAS_SHIFT          20
40683 #define uSDHC_HOST_CTRL_CAP_HSS_MASK             0x200000u
40684 #define uSDHC_HOST_CTRL_CAP_HSS_SHIFT            21
40685 #define uSDHC_HOST_CTRL_CAP_DMAS_MASK            0x400000u
40686 #define uSDHC_HOST_CTRL_CAP_DMAS_SHIFT           22
40687 #define uSDHC_HOST_CTRL_CAP_SRS_MASK             0x800000u
40688 #define uSDHC_HOST_CTRL_CAP_SRS_SHIFT            23
40689 #define uSDHC_HOST_CTRL_CAP_VS33_MASK            0x1000000u
40690 #define uSDHC_HOST_CTRL_CAP_VS33_SHIFT           24
40691 #define uSDHC_HOST_CTRL_CAP_VS30_MASK            0x2000000u
40692 #define uSDHC_HOST_CTRL_CAP_VS30_SHIFT           25
40693 #define uSDHC_HOST_CTRL_CAP_VS18_MASK            0x4000000u
40694 #define uSDHC_HOST_CTRL_CAP_VS18_SHIFT           26
40695 /* WTMK_LVL Bit Fields */
40696 #define uSDHC_WTMK_LVL_RD_WML_MASK               0xFFu
40697 #define uSDHC_WTMK_LVL_RD_WML_SHIFT              0
40698 #define uSDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_WML_SHIFT))&uSDHC_WTMK_LVL_RD_WML_MASK)
40699 #define uSDHC_WTMK_LVL_RD_BRST_LEN_MASK          0x1F00u
40700 #define uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         8
40701 #define uSDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_RD_BRST_LEN_MASK)
40702 #define uSDHC_WTMK_LVL_WR_WML_MASK               0xFF0000u
40703 #define uSDHC_WTMK_LVL_WR_WML_SHIFT              16
40704 #define uSDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_WML_SHIFT))&uSDHC_WTMK_LVL_WR_WML_MASK)
40705 #define uSDHC_WTMK_LVL_WR_BRST_LEN_MASK          0x1F000000u
40706 #define uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         24
40707 #define uSDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_WR_BRST_LEN_MASK)
40708 /* MIX_CTRL Bit Fields */
40709 #define uSDHC_MIX_CTRL_DMAEN_MASK                0x1u
40710 #define uSDHC_MIX_CTRL_DMAEN_SHIFT               0
40711 #define uSDHC_MIX_CTRL_BCEN_MASK                 0x2u
40712 #define uSDHC_MIX_CTRL_BCEN_SHIFT                1
40713 #define uSDHC_MIX_CTRL_AC12EN_MASK               0x4u
40714 #define uSDHC_MIX_CTRL_AC12EN_SHIFT              2
40715 #define uSDHC_MIX_CTRL_DDR_EN_MASK               0x8u
40716 #define uSDHC_MIX_CTRL_DDR_EN_SHIFT              3
40717 #define uSDHC_MIX_CTRL_DTDSEL_MASK               0x10u
40718 #define uSDHC_MIX_CTRL_DTDSEL_SHIFT              4
40719 #define uSDHC_MIX_CTRL_MSBSEL_MASK               0x20u
40720 #define uSDHC_MIX_CTRL_MSBSEL_SHIFT              5
40721 #define uSDHC_MIX_CTRL_NIBBLE_POS_MASK           0x40u
40722 #define uSDHC_MIX_CTRL_NIBBLE_POS_SHIFT          6
40723 #define uSDHC_MIX_CTRL_AC23EN_MASK               0x80u
40724 #define uSDHC_MIX_CTRL_AC23EN_SHIFT              7
40725 #define uSDHC_MIX_CTRL_EXE_TUNE_MASK             0x400000u
40726 #define uSDHC_MIX_CTRL_EXE_TUNE_SHIFT            22
40727 #define uSDHC_MIX_CTRL_SMP_CLK_SEL_MASK          0x800000u
40728 #define uSDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         23
40729 #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         0x1000000u
40730 #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        24
40731 #define uSDHC_MIX_CTRL_FBCLK_SEL_MASK            0x2000000u
40732 #define uSDHC_MIX_CTRL_FBCLK_SEL_SHIFT           25
40733 /* FORCE_EVENT Bit Fields */
40734 #define uSDHC_FORCE_EVENT_FEVTAC12NE_MASK        0x1u
40735 #define uSDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       0
40736 #define uSDHC_FORCE_EVENT_FEVTAC12TOE_MASK       0x2u
40737 #define uSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      1
40738 #define uSDHC_FORCE_EVENT_FEVTAC12CE_MASK        0x4u
40739 #define uSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       2
40740 #define uSDHC_FORCE_EVENT_FEVTAC12EBE_MASK       0x8u
40741 #define uSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      3
40742 #define uSDHC_FORCE_EVENT_FEVTAC12IE_MASK        0x10u
40743 #define uSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       4
40744 #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     0x80u
40745 #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    7
40746 #define uSDHC_FORCE_EVENT_FEVTCTOE_MASK          0x10000u
40747 #define uSDHC_FORCE_EVENT_FEVTCTOE_SHIFT         16
40748 #define uSDHC_FORCE_EVENT_FEVTCCE_MASK           0x20000u
40749 #define uSDHC_FORCE_EVENT_FEVTCCE_SHIFT          17
40750 #define uSDHC_FORCE_EVENT_FEVTCEBE_MASK          0x40000u
40751 #define uSDHC_FORCE_EVENT_FEVTCEBE_SHIFT         18
40752 #define uSDHC_FORCE_EVENT_FEVTCIE_MASK           0x80000u
40753 #define uSDHC_FORCE_EVENT_FEVTCIE_SHIFT          19
40754 #define uSDHC_FORCE_EVENT_FEVTDTOE_MASK          0x100000u
40755 #define uSDHC_FORCE_EVENT_FEVTDTOE_SHIFT         20
40756 #define uSDHC_FORCE_EVENT_FEVTDCE_MASK           0x200000u
40757 #define uSDHC_FORCE_EVENT_FEVTDCE_SHIFT          21
40758 #define uSDHC_FORCE_EVENT_FEVTDEBE_MASK          0x400000u
40759 #define uSDHC_FORCE_EVENT_FEVTDEBE_SHIFT         22
40760 #define uSDHC_FORCE_EVENT_FEVTAC12E_MASK         0x1000000u
40761 #define uSDHC_FORCE_EVENT_FEVTAC12E_SHIFT        24
40762 #define uSDHC_FORCE_EVENT_FEVTTNE_MASK           0x4000000u
40763 #define uSDHC_FORCE_EVENT_FEVTTNE_SHIFT          26
40764 #define uSDHC_FORCE_EVENT_FEVTDMAE_MASK          0x10000000u
40765 #define uSDHC_FORCE_EVENT_FEVTDMAE_SHIFT         28
40766 #define uSDHC_FORCE_EVENT_FEVTCINT_MASK          0x80000000u
40767 #define uSDHC_FORCE_EVENT_FEVTCINT_SHIFT         31
40768 /* ADMA_ERR_STATUS Bit Fields */
40769 #define uSDHC_ADMA_ERR_STATUS_ADMAES_MASK        0x3u
40770 #define uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       0
40771 #define uSDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT))&uSDHC_ADMA_ERR_STATUS_ADMAES_MASK)
40772 #define uSDHC_ADMA_ERR_STATUS_ADMALME_MASK       0x4u
40773 #define uSDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      2
40774 #define uSDHC_ADMA_ERR_STATUS_ADMADCE_MASK       0x8u
40775 #define uSDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      3
40776 /* ADMA_SYS_ADDR Bit Fields */
40777 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        0xFFFFFFFCu
40778 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       2
40779 #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT))&uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
40780 /* DLL_CTRL Bit Fields */
40781 #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      0x1u
40782 #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     0
40783 #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       0x2u
40784 #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      1
40785 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u
40786 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2
40787 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK 0x78u
40788 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT 3
40789 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
40790 #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK 0x80u
40791 #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT 7
40792 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u
40793 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT 8
40794 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u
40795 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9
40796 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
40797 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK 0x70000u
40798 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT 16
40799 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
40800 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u
40801 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20
40802 #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
40803 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u
40804 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT 28
40805 #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
40806 /* DLL_STATUS Bit Fields */
40807 #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   0x1u
40808 #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  0
40809 #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   0x2u
40810 #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  1
40811 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    0x1FCu
40812 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   2
40813 #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
40814 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    0xFE00u
40815 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   9
40816 #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
40817 /* CLK_TUNE_CTRL_STATUS Bit Fields */
40818 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK 0xFu
40819 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT 0
40820 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
40821 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK 0xF0u
40822 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT 4
40823 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
40824 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK 0x7F00u
40825 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT 8
40826 #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
40827 #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  0x8000u
40828 #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT 15
40829 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK 0xF0000u
40830 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT 16
40831 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
40832 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK 0xF00000u
40833 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT 20
40834 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
40835 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK 0x7F000000u
40836 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT 24
40837 #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
40838 #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  0x80000000u
40839 #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT 31
40840 /* VEND_SPEC Bit Fields */
40841 #define uSDHC_VEND_SPEC_EXT_DMA_EN_MASK          0x1u
40842 #define uSDHC_VEND_SPEC_EXT_DMA_EN_SHIFT         0
40843 #define uSDHC_VEND_SPEC_VSELECT_MASK             0x2u
40844 #define uSDHC_VEND_SPEC_VSELECT_SHIFT            1
40845 #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     0x4u
40846 #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    2
40847 #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  0x8u
40848 #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT 3
40849 #define uSDHC_VEND_SPEC_DAT3_CD_POL_MASK         0x10u
40850 #define uSDHC_VEND_SPEC_DAT3_CD_POL_SHIFT        4
40851 #define uSDHC_VEND_SPEC_CD_POL_MASK              0x20u
40852 #define uSDHC_VEND_SPEC_CD_POL_SHIFT             5
40853 #define uSDHC_VEND_SPEC_WP_POL_MASK              0x40u
40854 #define uSDHC_VEND_SPEC_WP_POL_SHIFT             6
40855 #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK     0x80u
40856 #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT    7
40857 #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        0x100u
40858 #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       8
40859 #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK     0x800u
40860 #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT    11
40861 #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_MASK        0x1000u
40862 #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT       12
40863 #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK  0x2000u
40864 #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT 13
40865 #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK    0x4000u
40866 #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT   14
40867 #define uSDHC_VEND_SPEC_CRC_CHK_DIS_MASK         0x8000u
40868 #define uSDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        15
40869 #define uSDHC_VEND_SPEC_INT_ST_VAL_MASK          0xFF0000u
40870 #define uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT         16
40871 #define uSDHC_VEND_SPEC_INT_ST_VAL(x)            (((uint32_t)(((uint32_t)(x))<<uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT))&uSDHC_VEND_SPEC_INT_ST_VAL_MASK)
40872 #define uSDHC_VEND_SPEC_CMD_BYTE_EN_MASK         0x80000000u
40873 #define uSDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        31
40874 /* MMC_BOOT Bit Fields */
40875 #define uSDHC_MMC_BOOT_DTOCV_ACK_MASK            0xFu
40876 #define uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT           0
40877 #define uSDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT))&uSDHC_MMC_BOOT_DTOCV_ACK_MASK)
40878 #define uSDHC_MMC_BOOT_BOOT_ACK_MASK             0x10u
40879 #define uSDHC_MMC_BOOT_BOOT_ACK_SHIFT            4
40880 #define uSDHC_MMC_BOOT_BOOT_MODE_MASK            0x20u
40881 #define uSDHC_MMC_BOOT_BOOT_MODE_SHIFT           5
40882 #define uSDHC_MMC_BOOT_BOOT_EN_MASK              0x40u
40883 #define uSDHC_MMC_BOOT_BOOT_EN_SHIFT             6
40884 #define uSDHC_MMC_BOOT_AUTO_SABG_EN_MASK         0x80u
40885 #define uSDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        7
40886 #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     0x100u
40887 #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    8
40888 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         0xFFFF0000u
40889 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        16
40890 #define uSDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT))&uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
40891 /* VEND_SPEC2 Bit Fields */
40892 #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK  0x1u
40893 #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT 0
40894 #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_MASK      0x2u
40895 #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT     1
40896 #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK     0x4u
40897 #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT    2
40898 #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   0x8u
40899 #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  3
40900 #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     0x10u
40901 #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    4
40902 #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     0x20u
40903 #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    5
40904 #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      0x40u
40905 #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     6
40906 #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK 0x80u
40907 #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT 7
40908 /* TUNING_CTRL Bit Fields */
40909 #define uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK  0xFFu
40910 #define uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT 0
40911 #define uSDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
40912 #define uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK    0xFF00u
40913 #define uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   8
40914 #define uSDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT))&uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
40915 #define uSDHC_TUNING_CTRL_TUNING_STEP_MASK       0x70000u
40916 #define uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT      16
40917 #define uSDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_STEP_MASK)
40918 #define uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK     0x700000u
40919 #define uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    20
40920 #define uSDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT))&uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
40921 #define uSDHC_TUNING_CTRL_STD_TUNING_EN_MASK     0x1000000u
40922 #define uSDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    24
40923 
40924 /*!
40925  * @}
40926  */ /* end of group uSDHC_Register_Masks */
40927 
40928 /* uSDHC - Peripheral instance base addresses */
40929 /** Peripheral uSDHC1 base address */
40930 #define uSDHC1_BASE                              (0x42190000u)
40931 /** Peripheral uSDHC1 base pointer */
40932 #define uSDHC1                                   ((uSDHC_Type *)uSDHC1_BASE)
40933 #define uSDHC1_BASE_PTR                          (uSDHC1)
40934 /** Peripheral uSDHC2 base address */
40935 #define uSDHC2_BASE                              (0x42194000u)
40936 /** Peripheral uSDHC2 base pointer */
40937 #define uSDHC2                                   ((uSDHC_Type *)uSDHC2_BASE)
40938 #define uSDHC2_BASE_PTR                          (uSDHC2)
40939 /** Peripheral uSDHC3 base address */
40940 #define uSDHC3_BASE                              (0x42198000u)
40941 /** Peripheral uSDHC3 base pointer */
40942 #define uSDHC3                                   ((uSDHC_Type *)uSDHC3_BASE)
40943 #define uSDHC3_BASE_PTR                          (uSDHC3)
40944 /** Peripheral uSDHC4 base address */
40945 #define uSDHC4_BASE                              (0x4219C000u)
40946 /** Peripheral uSDHC4 base pointer */
40947 #define uSDHC4                                   ((uSDHC_Type *)uSDHC4_BASE)
40948 #define uSDHC4_BASE_PTR                          (uSDHC4)
40949 /** Array initializer of uSDHC peripheral base addresses */
40950 #define uSDHC_BASE_ADDRS                         { uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE, uSDHC4_BASE }
40951 /** Array initializer of uSDHC peripheral base pointers */
40952 #define uSDHC_BASE_PTRS                          { uSDHC1, uSDHC2, uSDHC3, uSDHC4 }
40953 /** Interrupt vectors for the uSDHC peripheral type */
40954 #define uSDHC_IRQS                               { USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn, USDHC4_IRQn }
40955 
40956 /* ----------------------------------------------------------------------------
40957    -- uSDHC - Register accessor macros
40958    ---------------------------------------------------------------------------- */
40959 
40960 /*!
40961  * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros
40962  * @{
40963  */
40964 
40965 /* uSDHC - Register instance definitions */
40966 /* uSDHC1 */
40967 #define uSDHC1_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC1_BASE_PTR)
40968 #define uSDHC1_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC1_BASE_PTR)
40969 #define uSDHC1_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC1_BASE_PTR)
40970 #define uSDHC1_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC1_BASE_PTR)
40971 #define uSDHC1_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC1_BASE_PTR)
40972 #define uSDHC1_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC1_BASE_PTR)
40973 #define uSDHC1_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC1_BASE_PTR)
40974 #define uSDHC1_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC1_BASE_PTR)
40975 #define uSDHC1_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC1_BASE_PTR)
40976 #define uSDHC1_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC1_BASE_PTR)
40977 #define uSDHC1_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC1_BASE_PTR)
40978 #define uSDHC1_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC1_BASE_PTR)
40979 #define uSDHC1_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC1_BASE_PTR)
40980 #define uSDHC1_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC1_BASE_PTR)
40981 #define uSDHC1_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC1_BASE_PTR)
40982 #define uSDHC1_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC1_BASE_PTR)
40983 #define uSDHC1_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC1_BASE_PTR)
40984 #define uSDHC1_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC1_BASE_PTR)
40985 #define uSDHC1_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC1_BASE_PTR)
40986 #define uSDHC1_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC1_BASE_PTR)
40987 #define uSDHC1_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC1_BASE_PTR)
40988 #define uSDHC1_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC1_BASE_PTR)
40989 #define uSDHC1_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC1_BASE_PTR)
40990 #define uSDHC1_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC1_BASE_PTR)
40991 #define uSDHC1_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC1_BASE_PTR)
40992 #define uSDHC1_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC1_BASE_PTR)
40993 #define uSDHC1_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC1_BASE_PTR)
40994 #define uSDHC1_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC1_BASE_PTR)
40995 #define uSDHC1_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC1_BASE_PTR)
40996 /* uSDHC2 */
40997 #define uSDHC2_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC2_BASE_PTR)
40998 #define uSDHC2_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC2_BASE_PTR)
40999 #define uSDHC2_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC2_BASE_PTR)
41000 #define uSDHC2_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC2_BASE_PTR)
41001 #define uSDHC2_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC2_BASE_PTR)
41002 #define uSDHC2_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC2_BASE_PTR)
41003 #define uSDHC2_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC2_BASE_PTR)
41004 #define uSDHC2_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC2_BASE_PTR)
41005 #define uSDHC2_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC2_BASE_PTR)
41006 #define uSDHC2_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC2_BASE_PTR)
41007 #define uSDHC2_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC2_BASE_PTR)
41008 #define uSDHC2_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC2_BASE_PTR)
41009 #define uSDHC2_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC2_BASE_PTR)
41010 #define uSDHC2_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC2_BASE_PTR)
41011 #define uSDHC2_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC2_BASE_PTR)
41012 #define uSDHC2_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC2_BASE_PTR)
41013 #define uSDHC2_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC2_BASE_PTR)
41014 #define uSDHC2_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC2_BASE_PTR)
41015 #define uSDHC2_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC2_BASE_PTR)
41016 #define uSDHC2_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC2_BASE_PTR)
41017 #define uSDHC2_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC2_BASE_PTR)
41018 #define uSDHC2_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC2_BASE_PTR)
41019 #define uSDHC2_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC2_BASE_PTR)
41020 #define uSDHC2_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC2_BASE_PTR)
41021 #define uSDHC2_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC2_BASE_PTR)
41022 #define uSDHC2_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC2_BASE_PTR)
41023 #define uSDHC2_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC2_BASE_PTR)
41024 #define uSDHC2_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC2_BASE_PTR)
41025 #define uSDHC2_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC2_BASE_PTR)
41026 /* uSDHC3 */
41027 #define uSDHC3_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC3_BASE_PTR)
41028 #define uSDHC3_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC3_BASE_PTR)
41029 #define uSDHC3_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC3_BASE_PTR)
41030 #define uSDHC3_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC3_BASE_PTR)
41031 #define uSDHC3_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC3_BASE_PTR)
41032 #define uSDHC3_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC3_BASE_PTR)
41033 #define uSDHC3_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC3_BASE_PTR)
41034 #define uSDHC3_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC3_BASE_PTR)
41035 #define uSDHC3_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC3_BASE_PTR)
41036 #define uSDHC3_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC3_BASE_PTR)
41037 #define uSDHC3_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC3_BASE_PTR)
41038 #define uSDHC3_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC3_BASE_PTR)
41039 #define uSDHC3_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC3_BASE_PTR)
41040 #define uSDHC3_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC3_BASE_PTR)
41041 #define uSDHC3_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC3_BASE_PTR)
41042 #define uSDHC3_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC3_BASE_PTR)
41043 #define uSDHC3_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC3_BASE_PTR)
41044 #define uSDHC3_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC3_BASE_PTR)
41045 #define uSDHC3_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC3_BASE_PTR)
41046 #define uSDHC3_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC3_BASE_PTR)
41047 #define uSDHC3_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC3_BASE_PTR)
41048 #define uSDHC3_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC3_BASE_PTR)
41049 #define uSDHC3_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC3_BASE_PTR)
41050 #define uSDHC3_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC3_BASE_PTR)
41051 #define uSDHC3_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC3_BASE_PTR)
41052 #define uSDHC3_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC3_BASE_PTR)
41053 #define uSDHC3_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC3_BASE_PTR)
41054 #define uSDHC3_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC3_BASE_PTR)
41055 #define uSDHC3_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC3_BASE_PTR)
41056 /* uSDHC4 */
41057 #define uSDHC4_DS_ADDR                           uSDHC_DS_ADDR_REG(uSDHC4_BASE_PTR)
41058 #define uSDHC4_BLK_ATT                           uSDHC_BLK_ATT_REG(uSDHC4_BASE_PTR)
41059 #define uSDHC4_CMD_ARG                           uSDHC_CMD_ARG_REG(uSDHC4_BASE_PTR)
41060 #define uSDHC4_CMD_XFR_TYP                       uSDHC_CMD_XFR_TYP_REG(uSDHC4_BASE_PTR)
41061 #define uSDHC4_CMD_RSP0                          uSDHC_CMD_RSP0_REG(uSDHC4_BASE_PTR)
41062 #define uSDHC4_CMD_RSP1                          uSDHC_CMD_RSP1_REG(uSDHC4_BASE_PTR)
41063 #define uSDHC4_CMD_RSP2                          uSDHC_CMD_RSP2_REG(uSDHC4_BASE_PTR)
41064 #define uSDHC4_CMD_RSP3                          uSDHC_CMD_RSP3_REG(uSDHC4_BASE_PTR)
41065 #define uSDHC4_DATA_BUFF_ACC_PORT                uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC4_BASE_PTR)
41066 #define uSDHC4_PRES_STATE                        uSDHC_PRES_STATE_REG(uSDHC4_BASE_PTR)
41067 #define uSDHC4_PROT_CTRL                         uSDHC_PROT_CTRL_REG(uSDHC4_BASE_PTR)
41068 #define uSDHC4_SYS_CTRL                          uSDHC_SYS_CTRL_REG(uSDHC4_BASE_PTR)
41069 #define uSDHC4_INT_STATUS                        uSDHC_INT_STATUS_REG(uSDHC4_BASE_PTR)
41070 #define uSDHC4_INT_STATUS_EN                     uSDHC_INT_STATUS_EN_REG(uSDHC4_BASE_PTR)
41071 #define uSDHC4_INT_SIGNAL_EN                     uSDHC_INT_SIGNAL_EN_REG(uSDHC4_BASE_PTR)
41072 #define uSDHC4_AUTOCMD12_ERR_STATUS              uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC4_BASE_PTR)
41073 #define uSDHC4_HOST_CTRL_CAP                     uSDHC_HOST_CTRL_CAP_REG(uSDHC4_BASE_PTR)
41074 #define uSDHC4_WTMK_LVL                          uSDHC_WTMK_LVL_REG(uSDHC4_BASE_PTR)
41075 #define uSDHC4_MIX_CTRL                          uSDHC_MIX_CTRL_REG(uSDHC4_BASE_PTR)
41076 #define uSDHC4_FORCE_EVENT                       uSDHC_FORCE_EVENT_REG(uSDHC4_BASE_PTR)
41077 #define uSDHC4_ADMA_ERR_STATUS                   uSDHC_ADMA_ERR_STATUS_REG(uSDHC4_BASE_PTR)
41078 #define uSDHC4_ADMA_SYS_ADDR                     uSDHC_ADMA_SYS_ADDR_REG(uSDHC4_BASE_PTR)
41079 #define uSDHC4_DLL_CTRL                          uSDHC_DLL_CTRL_REG(uSDHC4_BASE_PTR)
41080 #define uSDHC4_DLL_STATUS                        uSDHC_DLL_STATUS_REG(uSDHC4_BASE_PTR)
41081 #define uSDHC4_CLK_TUNE_CTRL_STATUS              uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC4_BASE_PTR)
41082 #define uSDHC4_VEND_SPEC                         uSDHC_VEND_SPEC_REG(uSDHC4_BASE_PTR)
41083 #define uSDHC4_MMC_BOOT                          uSDHC_MMC_BOOT_REG(uSDHC4_BASE_PTR)
41084 #define uSDHC4_VEND_SPEC2                        uSDHC_VEND_SPEC2_REG(uSDHC4_BASE_PTR)
41085 #define uSDHC4_TUNING_CTRL                       uSDHC_TUNING_CTRL_REG(uSDHC4_BASE_PTR)
41086 
41087 /*!
41088  * @}
41089  */ /* end of group uSDHC_Register_Accessor_Macros */
41090 
41091 /*!
41092  * @}
41093  */ /* end of group uSDHC_Peripheral */
41094 
41095 /*
41096 ** End of section using anonymous unions
41097 */
41098 
41099 #if defined(__ARMCC_VERSION)
41100   #pragma pop
41101 #elif defined(__GNUC__)
41102   /* leave anonymous unions enabled */
41103 #elif defined(__IAR_SYSTEMS_ICC__)
41104   #pragma language=default
41105 #else
41106   #error Not supported compiler type
41107 #endif
41108 
41109 /*!
41110  * @}
41111  */ /* end of group Peripheral_defines */
41112 
41113 
41114 /* ----------------------------------------------------------------------------
41115    -- Backward Compatibility
41116    ---------------------------------------------------------------------------- */
41117 
41118 /*!
41119  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
41120  * @{
41121  */
41122 
41123 /* No backward compatibility issues. */
41124 
41125 /*!
41126  * @}
41127  */ /* end of group Backward_Compatibility_Symbols */
41128 
41129 
41130 #else /* #if !defined(MCIMX6X_M4_H_) */
41131   /* There is already included the same memory map. Check if it is compatible (has the same major version) */
41132   #if (MCU_MEM_MAP_VERSION != 0x0100u)
41133     #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
41134       #warning There are included two not compatible versions of memory maps. Please check possible differences.
41135     #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
41136   #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
41137 #endif  /* #if !defined(MCIMX6X_M4_H_) */
41138 
41139 /* MCIMX6X_M4.h, eof. */
41140