/* ** ################################################################### ** Processors: MCIMX6X_M4 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: ** Version: rev. 1.0, 2015-07-17 ** Build: b150707 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCIMX6X_M4 ** ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. ** All rights reserved. ** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2015-07-17) ** Initial version . ** ** ################################################################### */ /*! * @file MCIMX6X_M4.h * @version 1.0 * @date 2015-07-17 * @brief CMSIS Peripheral Access Layer for MCIMX6X_M4 * * CMSIS Peripheral Access Layer for MCIMX6X_M4 */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MCIMX6X_M4_H_) /* Check if memory map has not been already included */ #define MCIMX6X_M4_H_ #define MCU_MCIMX6X_M4 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MCIMX6X_M4 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000u /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ Cortex_M4_IRQn = 0, /**< Cache Controller interrupt */ DAP_IRQn = 1, /**< Debug Access Port interrupt request. */ SDMA_IRQn = 2, /**< SDMA interrupt request from all channels. */ Reserved0_IRQn = 3, /**< Reserved */ SNVS_IRQn = 4, /**< PMIC power off request. */ LCDIF1_IRQn = 5, /**< LCDIF1 Sync Interrupt */ LCDIF2_IRQn = 6, /**< LCDIF2 Sync Interrupt */ CSI1_IRQn = 7, /**< CMOS Sensor Interface interrupt request */ PXP_IRQn = 8, /**< PXP interrupt */ Reserved1_IRQn = 9, /**< Reserved */ GPU_IRQn = 10, /**< GPU general interrupt request */ WDOG3_IRQn = 11, /**< WDOG3 interrupt request */ SEMA4_CP1_IRQn = 12, /**< SEMA4 CP1 interrupt request. */ APBHDMA_IRQn = 13, /**< Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ EIM_IRQn = 14, /**< EIM interrupt request. */ BCH_IRQn = 15, /**< BCH operation complete interrupt. */ GPMI_IRQn = 16, /**< GPMI operation timeout error interrupt. */ UART6_IRQn = 17, /**< UART6 interrupt request. */ eCSPI5_IRQn = 18, /**< eCSPI5 interrupt request. */ SNVS_CONSOLIDATED_IRQn = 19, /**< SNVS consolidated interrupt. */ SNVS_SECURITY_IRQn = 20, /**< SNVS security interrupt. */ CSU_IRQn = 21, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ USDHC1_IRQn = 22, /**< uSDHC1 (Enhanced SDHC) interrupt request */ USDHC2_IRQn = 23, /**< uSDHC2 (Enhanced SDHC) interrupt request. */ USDHC3_IRQn = 24, /**< uSDHC3 (Enhanced SDHC) interrupt request. */ USDHC4_IRQn = 25, /**< uSDHC4 (Enhanced SDHC) interrupt request. */ UART1_IRQn = 26, /**< UART1 interrupt request. */ UART2_IRQn = 27, /**< UART2 interrupt request. */ UART3_IRQn = 28, /**< UART3 interrupt request. */ UART4_IRQn = 29, /**< UART4 interrupt request. */ UART5_IRQn = 30, /**< UART5 interrupt request. */ eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request. */ eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request. */ eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request. */ eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request. */ I2C4_IRQn = 35, /**< I2C4 interrupt request */ I2C1_IRQn = 36, /**< I2C1 interrupt request. */ I2C2_IRQn = 37, /**< I2C2 interrupt request. */ I2C3_IRQn = 38, /**< I2C3 interrupt request. */ RDC_IRQn = 39, /**< RDC interrupt request. */ USB_IRQn = 40, /**< USB HISC Host interrupt request. */ CSI2_IRQn = 41, /**< CSI interrupt */ USB_OTG2_IRQn = 42, /**< USB OTG 2 interrupt request. */ USB_OTG1_IRQn = 43, /**< USB OTG 1 interrupt request. */ USB_PHY1_IRQn = 44, /**< UTMI0 interrupt request. */ USB_PHY2_IRQn = 45, /**< UTMI1 interrupt request. */ SSI1_IRQn = 46, /**< SSI1 interrupt request. */ SSI2_IRQn = 47, /**< SSI2 interrupt request. */ SSI3_IRQn = 48, /**< SSI3 interrupt request. */ Temperature_Monitor_IRQn = 49, /**< Temperature Sensor (temp. greater than threshold) interrupt request. */ ASRC_IRQn = 50, /**< ASRC interrupt request. */ ESAI_IRQn = 51, /**< ESAI interrupt request */ SPDIF_IRQn = 52, /**< SPDIF Rx/Tx interrupt. */ MLB_ERROR_IRQn = 53, /**< MLB error interrupt request. */ PMU1_IRQn = 54, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ GPT_IRQn = 55, /**< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines. */ EPIT1_IRQn = 56, /**< EPIT1 output compare interrupt. */ EPIT2_IRQn = 57, /**< EPIT2 output compare interrupt. */ GPIO1_INT7_IRQn = 58, /**< INT7 interrupt request. */ GPIO1_INT6_IRQn = 59, /**< INT6 interrupt request. */ GPIO1_INT5_IRQn = 60, /**< INT5 interrupt request. */ GPIO1_INT4_IRQn = 61, /**< INT4 interrupt request. */ GPIO1_INT3_IRQn = 62, /**< INT3 interrupt request. */ GPIO1_INT2_IRQn = 63, /**< INT2 interrupt request. */ GPIO1_INT1_IRQn = 64, /**< INT1 interrupt request. */ GPIO1_INT0_IRQn = 65, /**< INT0 interrupt request. */ GPIO1_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ GPIO1_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ GPIO2_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ GPIO2_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ GPIO3_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ GPIO3_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ GPIO4_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ GPIO4_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ GPIO5_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ GPIO5_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ GPIO6_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO6 signals 0 - 15. */ GPIO6_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO6 signals 16 - 31. */ GPIO7_INT15_0_IRQn = 78, /**< Combined interrupt indication for GPIO7 signals 0 - 15. */ GPIO7_INT31_16_IRQn = 79, /**< Combined interrupt indication for GPIO7 signals 16 - 31. */ WDOG1_IRQn = 80, /**< WDOG1 timer reset interrupt request. */ WDOG2_IRQn = 81, /**< WDOG2 timer reset interrupt request. */ KPP_IRQn = 82, /**< Key Pad interrupt request */ PWM1_PWM5_IRQn = 83, /**< Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ PWM2_PWM6_IRQn = 84, /**< Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ PWM3_PWM7_IRQn = 85, /**< Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ PWM4_PWM8_IRQn = 86, /**< Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ CCM1_IRQn = 87, /**< CCM interrupt request 1. */ CCM2_IRQn = 88, /**< CCM interrupt request 2. */ GPC_IRQn = 89, /**< GPC interrupt request 1. */ MU_A9_IRQn = 90, /**< Message unit interrupt to A9 core */ SRC_IRQn = 91, /**< SRC interrupt request. */ CPU_L2I_IRQn = 92, /**< L2 interrupt request. */ CPU_PCEI_IRQn = 93, /**< Parity Check error interrupt request. */ CPU_PUI_IRQn = 94, /**< Performance Unit interrupt. */ CPU_CTI_IRQn = 95, /**< CTI trigger outputs interrupt. */ SRC_CPU_WDOG_IRQn = 96, /**< Combined CPU wdog interrupts (4x) out of SRC. */ SAI1_IRQn = 97, /**< SAI1 interrupt request. */ SAI2_IRQn = 98, /**< SAI2 interrupt request. */ MU_M4_IRQn = 99, /**< Message unit Interrupt to M4 core */ ADC1_IRQn = 100, /**< ADC1 interrupt request. */ ADC2_IRQn = 101, /**< ADC2 interrupt request. */ ENET2_IRQn = 102, /**< ENET2 Interrupt Request. */ ENET2_TI_IRQn = 103, /**< ENET2 1588 Timer interrupt [synchronous] request. */ SJC_IRQn = 104, /**< SJC interrupt from General Purpose register. */ CAAM1_IRQn = 105, /**< CAAM job ring 0 interrupt. */ CAAM2_IRQn = 106, /**< CAAM job ring 1 interrupt. */ QSPI1_IRQn = 107, /**< QSPI1 interrupt request. */ TZASC_IRQn = 108, /**< TZASC (PL380) interrupt request. */ QSPI2_IRQn = 109, /**< QSPI2 interrupt request. */ FLEXCAN1_IRQn = 110, /**< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ FLEXCAN2_IRQn = 111, /**< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ Reserved2_IRQn = 112, /**< Reserved */ Reserved3_IRQn = 113, /**< Reserved */ Reserved4_IRQn = 114, /**< Reserved */ Reserved5_IRQn = 115, /**< Reserved */ SEMA4_CP0_IRQn = 116, /**< SEMA4 CP0 interrupt request */ MLB_IRCI_IRQn = 117, /**< Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158. */ ENET1_IRQn = 118, /**< ENET1 Interrupt Request. */ ENET1_TI_IRQn = 119, /**< ENET1 1588 Timer interrupt [synchronous] request. */ PCIe1_IRQn = 120, /**< PCIe interrupt request 1. */ PCIe2_IRQn = 121, /**< PCIe interrupt request 2. */ PCIe3_IRQn = 122, /**< PCIe interrupt request 3. */ PCIe4_IRQn = 123, /**< PCIe interrupt request 4. */ DCIC1_IRQn = 124, /**< DCIC1 interrupt request. */ DCIC2_IRQn = 125, /**< DCIC2 interrupt request. */ MLB_LOCI_IRQn = 126, /**< Logical OR of channel[63:32] interrupt requests. */ PMU2_IRQn = 127, /**< Brown out of core, gpu, and chip digital regulators occurred. */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration * @{ */ #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t HC0; /**< Control register for hardware triggers, offset: 0x0 */ __IO uint32_t HC1; /**< Control register for hardware triggers, offset: 0x4 */ __I uint32_t HS; /**< Status register for HW triggers, offset: 0x8 */ __IO uint32_t R0; /**< Data result register for HW triggers, offset: 0xC */ __IO uint32_t R1; /**< Data result register for HW triggers, offset: 0x10 */ __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ __IO uint32_t GC; /**< General control register, offset: 0x18 */ __IO uint32_t GS; /**< General status register, offset: 0x1C */ __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ } ADC_Type, *ADC_MemMapPtr; /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register accessors */ #define ADC_HC0_REG(base) ((base)->HC0) #define ADC_HC1_REG(base) ((base)->HC1) #define ADC_HS_REG(base) ((base)->HS) #define ADC_R0_REG(base) ((base)->R0) #define ADC_R1_REG(base) ((base)->R1) #define ADC_CFG_REG(base) ((base)->CFG) #define ADC_GC_REG(base) ((base)->GC) #define ADC_GS_REG(base) ((base)->GS) #define ADC_CV_REG(base) ((base)->CV) #define ADC_OFS_REG(base) ((base)->OFS) #define ADC_CAL_REG(base) ((base)->CAL) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* HC0 Bit Fields */ #define ADC_HC0_ADCH_MASK 0x1Fu #define ADC_HC0_ADCH_SHIFT 0 #define ADC_HC0_ADCH(x) (((uint32_t)(((uint32_t)(x))<BLOCK_ID) #define AFE_PDBUF_REG(base) ((base)->PDBUF) #define AFE_SWRST_REG(base) ((base)->SWRST) #define AFE_BGREG_REG(base) ((base)->BGREG) #define AFE_ACCESSAR_ID_REG(base) ((base)->ACCESSAR_ID) #define AFE_PDADC_REG(base) ((base)->PDADC) #define AFE_PDSARH_REG(base) ((base)->PDSARH) #define AFE_PDSARL_REG(base) ((base)->PDSARL) #define AFE_PDADCRFH_REG(base) ((base)->PDADCRFH) #define AFE_PDADCRFL_REG(base) ((base)->PDADCRFL) #define AFE_ADCGN_REG(base) ((base)->ADCGN) #define AFE_REFTRIML_REG(base) ((base)->REFTRIML) #define AFE_REFTRIMH_REG(base) ((base)->REFTRIMH) #define AFE_DACAMP_REG(base) ((base)->DACAMP) #define AFE_CLMPDAT_REG(base) ((base)->CLMPDAT) #define AFE_CLMPAMP_REG(base) ((base)->CLMPAMP) #define AFE_CLAMP_REG(base) ((base)->CLAMP) #define AFE_INPBUF_REG(base) ((base)->INPBUF) #define AFE_INPFLT_REG(base) ((base)->INPFLT) #define AFE_ADCDGN_REG(base) ((base)->ADCDGN) #define AFE_OFFDRV_REG(base) ((base)->OFFDRV) #define AFE_INPCONFIG_REG(base) ((base)->INPCONFIG) #define AFE_PROGDELAY_REG(base) ((base)->PROGDELAY) #define AFE_ADCOMT_REG(base) ((base)->ADCOMT) #define AFE_ALGDELAY_REG(base) ((base)->ALGDELAY) #define AFE_ACC_ID_REG(base) ((base)->ACC_ID) #define AFE_ACCSTA_REG(base) ((base)->ACCSTA) #define AFE_ACCNOSLI_REG(base) ((base)->ACCNOSLI) #define AFE_ACCCALCON_REG(base) ((base)->ACCCALCON) #define AFE_BWEWRICTRL_REG(base) ((base)->BWEWRICTRL) #define AFE_SELSLI_REG(base) ((base)->SELSLI) #define AFE_SELBYT_REG(base) ((base)->SELBYT) #define AFE_REDVAL_REG(base) ((base)->REDVAL) #define AFE_WRIBYT_REG(base) ((base)->WRIBYT) /*! * @} */ /* end of group AFE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AFE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AFE_Register_Masks AFE Register Masks * @{ */ /* BLOCK_ID Bit Fields */ #define AFE_BLOCK_ID_BLOCK_ID_MASK 0xFFu #define AFE_BLOCK_ID_BLOCK_ID_SHIFT 0 #define AFE_BLOCK_ID_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x))<ASRCTR) #define ASRC_ASRIER_REG(base) ((base)->ASRIER) #define ASRC_ASRCNCR_REG(base) ((base)->ASRCNCR) #define ASRC_ASRCFG_REG(base) ((base)->ASRCFG) #define ASRC_ASRCSR_REG(base) ((base)->ASRCSR) #define ASRC_ASRCDR1_REG(base) ((base)->ASRCDR1) #define ASRC_ASRCDR2_REG(base) ((base)->ASRCDR2) #define ASRC_ASRSTR_REG(base) ((base)->ASRSTR) #define ASRC_ASRPMn_REG(base,index) ((base)->ASRPMn[index]) #define ASRC_ASRTFR1_REG(base) ((base)->ASRTFR1) #define ASRC_ASRCCR_REG(base) ((base)->ASRCCR) #define ASRC_ASRDI_REG(base,index) ((base)->ASRD[index].ASRDI) #define ASRC_ASRDO_REG(base,index) ((base)->ASRD[index].ASRDO) #define ASRC_ASRIDRHA_REG(base) ((base)->ASRIDRHA) #define ASRC_ASRIDRLA_REG(base) ((base)->ASRIDRLA) #define ASRC_ASRIDRHB_REG(base) ((base)->ASRIDRHB) #define ASRC_ASRIDRLB_REG(base) ((base)->ASRIDRLB) #define ASRC_ASRIDRHC_REG(base) ((base)->ASRIDRHC) #define ASRC_ASRIDRLC_REG(base) ((base)->ASRIDRLC) #define ASRC_ASR76K_REG(base) ((base)->ASR76K) #define ASRC_ASR56K_REG(base) ((base)->ASR56K) #define ASRC_ASRMCRA_REG(base) ((base)->ASRMCRA) #define ASRC_ASRFSTA_REG(base) ((base)->ASRFSTA) #define ASRC_ASRMCRB_REG(base) ((base)->ASRMCRB) #define ASRC_ASRFSTB_REG(base) ((base)->ASRFSTB) #define ASRC_ASRMCRC_REG(base) ((base)->ASRMCRC) #define ASRC_ASRFSTC_REG(base) ((base)->ASRFSTC) #define ASRC_ASRMCR1_REG(base,index) ((base)->ASRMCR1[index]) /*! * @} */ /* end of group ASRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ASRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Register_Masks ASRC Register Masks * @{ */ /* ASRCTR Bit Fields */ #define ASRC_ASRCTR_ASRCEN_MASK 0x1u #define ASRC_ASRCTR_ASRCEN_SHIFT 0 #define ASRC_ASRCTR_ASREA_MASK 0x2u #define ASRC_ASRCTR_ASREA_SHIFT 1 #define ASRC_ASRCTR_ASREB_MASK 0x4u #define ASRC_ASRCTR_ASREB_SHIFT 2 #define ASRC_ASRCTR_ASREC_MASK 0x8u #define ASRC_ASRCTR_ASREC_SHIFT 3 #define ASRC_ASRCTR_SRST_MASK 0x10u #define ASRC_ASRCTR_SRST_SHIFT 4 #define ASRC_ASRCTR_IDRA_MASK 0x2000u #define ASRC_ASRCTR_IDRA_SHIFT 13 #define ASRC_ASRCTR_USRA_MASK 0x4000u #define ASRC_ASRCTR_USRA_SHIFT 14 #define ASRC_ASRCTR_IDRB_MASK 0x8000u #define ASRC_ASRCTR_IDRB_SHIFT 15 #define ASRC_ASRCTR_USRB_MASK 0x10000u #define ASRC_ASRCTR_USRB_SHIFT 16 #define ASRC_ASRCTR_IDRC_MASK 0x20000u #define ASRC_ASRCTR_IDRC_SHIFT 17 #define ASRC_ASRCTR_USRC_MASK 0x40000u #define ASRC_ASRCTR_USRC_SHIFT 18 #define ASRC_ASRCTR_ATSA_MASK 0x100000u #define ASRC_ASRCTR_ATSA_SHIFT 20 #define ASRC_ASRCTR_ATSB_MASK 0x200000u #define ASRC_ASRCTR_ATSB_SHIFT 21 #define ASRC_ASRCTR_ATSC_MASK 0x400000u #define ASRC_ASRCTR_ATSC_SHIFT 22 /* ASRIER Bit Fields */ #define ASRC_ASRIER_ADIEA_MASK 0x1u #define ASRC_ASRIER_ADIEA_SHIFT 0 #define ASRC_ASRIER_ADIEB_MASK 0x2u #define ASRC_ASRIER_ADIEB_SHIFT 1 #define ASRC_ASRIER_ADIEC_MASK 0x4u #define ASRC_ASRIER_ADIEC_SHIFT 2 #define ASRC_ASRIER_ADOEA_MASK 0x8u #define ASRC_ASRIER_ADOEA_SHIFT 3 #define ASRC_ASRIER_ADOEB_MASK 0x10u #define ASRC_ASRIER_ADOEB_SHIFT 4 #define ASRC_ASRIER_ADOEC_MASK 0x20u #define ASRC_ASRIER_ADOEC_SHIFT 5 #define ASRC_ASRIER_AOLIE_MASK 0x40u #define ASRC_ASRIER_AOLIE_SHIFT 6 #define ASRC_ASRIER_AFPWE_MASK 0x80u #define ASRC_ASRIER_AFPWE_SHIFT 7 /* ASRCNCR Bit Fields */ #define ASRC_ASRCNCR_ANCA_MASK 0xFu #define ASRC_ASRCNCR_ANCA_SHIFT 0 #define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x))<PTCR1) #define AUDMUX_PDCR1_REG(base) ((base)->PDCR1) #define AUDMUX_PTCR2_REG(base) ((base)->PTCR2) #define AUDMUX_PDCR2_REG(base) ((base)->PDCR2) #define AUDMUX_PTCR3_REG(base) ((base)->PTCR3) #define AUDMUX_PDCR3_REG(base) ((base)->PDCR3) #define AUDMUX_PTCR4_REG(base) ((base)->PTCR4) #define AUDMUX_PDCR4_REG(base) ((base)->PDCR4) #define AUDMUX_PTCR5_REG(base) ((base)->PTCR5) #define AUDMUX_PDCR5_REG(base) ((base)->PDCR5) #define AUDMUX_PTCR6_REG(base) ((base)->PTCR6) #define AUDMUX_PDCR6_REG(base) ((base)->PDCR6) #define AUDMUX_PTCR7_REG(base) ((base)->PTCR7) #define AUDMUX_PDCR7_REG(base) ((base)->PDCR7) /*! * @} */ /* end of group AUDMUX_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AUDMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDMUX_Register_Masks AUDMUX Register Masks * @{ */ /* PTCR1 Bit Fields */ #define AUDMUX_PTCR1_SYN_MASK 0x800u #define AUDMUX_PTCR1_SYN_SHIFT 11 #define AUDMUX_PTCR1_RCSEL_MASK 0xF000u #define AUDMUX_PTCR1_RCSEL_SHIFT 12 #define AUDMUX_PTCR1_RCSEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) #define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define BCH_STATUS0_REG(base) ((base)->STATUS0) #define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) #define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) #define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) #define BCH_MODE_REG(base) ((base)->MODE) #define BCH_MODE_SET_REG(base) ((base)->MODE_SET) #define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) #define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) #define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) #define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) #define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) #define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) #define BCH_DATAPTR_REG(base) ((base)->DATAPTR) #define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) #define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) #define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) #define BCH_METAPTR_REG(base) ((base)->METAPTR) #define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) #define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) #define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) #define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) #define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) #define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) #define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) #define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) #define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) #define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) #define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) #define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) #define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) #define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) #define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) #define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) #define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) #define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) #define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) #define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) #define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) #define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) #define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) #define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) #define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) #define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) #define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) #define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) #define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) #define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) #define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) #define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) #define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) #define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) #define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) #define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) #define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) #define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) #define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) #define BCH_DEBUG0_REG(base) ((base)->DEBUG0) #define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) #define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) #define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) #define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) #define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) #define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) #define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) #define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) #define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) #define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) #define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) #define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) #define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) #define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) #define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) #define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) #define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) #define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) #define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) #define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) #define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) #define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) #define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) #define BCH_VERSION_REG(base) ((base)->VERSION) #define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) #define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) #define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) #define BCH_DEBUG1_REG(base) ((base)->DEBUG1) #define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) #define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) #define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) /*! * @} */ /* end of group BCH_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Register_Masks BCH Register Masks * @{ */ /* CTRL Bit Fields */ #define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u #define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 #define BCH_CTRL_RSVD0_MASK 0x2u #define BCH_CTRL_RSVD0_SHIFT 1 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 #define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u #define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 #define BCH_CTRL_RSVD1_MASK 0xF0u #define BCH_CTRL_RSVD1_SHIFT 4 #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) #define CAN_ECR_REG(base) ((base)->ECR) #define CAN_ESR1_REG(base) ((base)->ESR1) #define CAN_IMASK2_REG(base) ((base)->IMASK2) #define CAN_IMASK1_REG(base) ((base)->IMASK1) #define CAN_IFLAG2_REG(base) ((base)->IFLAG2) #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) #define CAN_CTRL2_REG(base) ((base)->CTRL2) #define CAN_ESR2_REG(base) ((base)->ESR2) #define CAN_CRCR_REG(base) ((base)->CRCR) #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) #define CAN_RXFIR_REG(base) ((base)->RXFIR) #define CAN_CS_REG(base,index) ((base)->MB[index].CS) #define CAN_CS_COUNT 64 #define CAN_ID_REG(base,index) ((base)->MB[index].ID) #define CAN_ID_COUNT 64 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) #define CAN_WORD0_COUNT 64 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) #define CAN_WORD1_COUNT 64 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) #define CAN_RXIMR_COUNT 64 #define CAN_GFWR_REG(base) ((base)->GFWR) /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /* MCR Bit Fields */ #define CAN_MCR_MAXMB_MASK 0x7Fu #define CAN_MCR_MAXMB_SHIFT 0 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<CCR) #define CCM_CCDR_REG(base) ((base)->CCDR) #define CCM_CSR_REG(base) ((base)->CSR) #define CCM_CCSR_REG(base) ((base)->CCSR) #define CCM_CACRR_REG(base) ((base)->CACRR) #define CCM_CBCDR_REG(base) ((base)->CBCDR) #define CCM_CBCMR_REG(base) ((base)->CBCMR) #define CCM_CSCMR1_REG(base) ((base)->CSCMR1) #define CCM_CSCMR2_REG(base) ((base)->CSCMR2) #define CCM_CSCDR1_REG(base) ((base)->CSCDR1) #define CCM_CS1CDR_REG(base) ((base)->CS1CDR) #define CCM_CS2CDR_REG(base) ((base)->CS2CDR) #define CCM_CDCDR_REG(base) ((base)->CDCDR) #define CCM_CHSCCDR_REG(base) ((base)->CHSCCDR) #define CCM_CSCDR2_REG(base) ((base)->CSCDR2) #define CCM_CSCDR3_REG(base) ((base)->CSCDR3) #define CCM_CWDR_REG(base) ((base)->CWDR) #define CCM_CDHIPR_REG(base) ((base)->CDHIPR) #define CCM_CLPCR_REG(base) ((base)->CLPCR) #define CCM_CISR_REG(base) ((base)->CISR) #define CCM_CIMR_REG(base) ((base)->CIMR) #define CCM_CCOSR_REG(base) ((base)->CCOSR) #define CCM_CGPR_REG(base) ((base)->CGPR) #define CCM_CCGR0_REG(base) ((base)->CCGR0) #define CCM_CCGR1_REG(base) ((base)->CCGR1) #define CCM_CCGR2_REG(base) ((base)->CCGR2) #define CCM_CCGR3_REG(base) ((base)->CCGR3) #define CCM_CCGR4_REG(base) ((base)->CCGR4) #define CCM_CCGR5_REG(base) ((base)->CCGR5) #define CCM_CCGR6_REG(base) ((base)->CCGR6) #define CCM_CMEOR_REG(base) ((base)->CMEOR) /*! * @} */ /* end of group CCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Register_Masks CCM Register Masks * @{ */ /* CCR Bit Fields */ #define CCM_CCR_OSCNT_MASK 0x7Fu #define CCM_CCR_OSCNT_SHIFT 0 #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) #define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) #define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) #define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) #define CCM_ANALOG_PLL_USB1_REG(base) ((base)->PLL_USB1) #define CCM_ANALOG_PLL_USB1_SET_REG(base) ((base)->PLL_USB1_SET) #define CCM_ANALOG_PLL_USB1_CLR_REG(base) ((base)->PLL_USB1_CLR) #define CCM_ANALOG_PLL_USB1_TOG_REG(base) ((base)->PLL_USB1_TOG) #define CCM_ANALOG_PLL_USB2_REG(base) ((base)->PLL_USB2) #define CCM_ANALOG_PLL_USB2_SET_REG(base) ((base)->PLL_USB2_SET) #define CCM_ANALOG_PLL_USB2_CLR_REG(base) ((base)->PLL_USB2_CLR) #define CCM_ANALOG_PLL_USB2_TOG_REG(base) ((base)->PLL_USB2_TOG) #define CCM_ANALOG_PLL_SYS_REG(base) ((base)->PLL_SYS) #define CCM_ANALOG_PLL_SYS_SET_REG(base) ((base)->PLL_SYS_SET) #define CCM_ANALOG_PLL_SYS_CLR_REG(base) ((base)->PLL_SYS_CLR) #define CCM_ANALOG_PLL_SYS_TOG_REG(base) ((base)->PLL_SYS_TOG) #define CCM_ANALOG_PLL_SYS_SS_REG(base) ((base)->PLL_SYS_SS) #define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) #define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) #define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) #define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) #define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) #define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) #define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) #define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) #define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) #define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) #define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) #define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) #define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) #define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) #define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) #define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) #define CCM_ANALOG_PFD_480_REG(base) ((base)->PFD_480) #define CCM_ANALOG_PFD_480_SET_REG(base) ((base)->PFD_480_SET) #define CCM_ANALOG_PFD_480_CLR_REG(base) ((base)->PFD_480_CLR) #define CCM_ANALOG_PFD_480_TOG_REG(base) ((base)->PFD_480_TOG) #define CCM_ANALOG_PFD_528_REG(base) ((base)->PFD_528) #define CCM_ANALOG_PFD_528_SET_REG(base) ((base)->PFD_528_SET) #define CCM_ANALOG_PFD_528_CLR_REG(base) ((base)->PFD_528_CLR) #define CCM_ANALOG_PFD_528_TOG_REG(base) ((base)->PFD_528_TOG) #define CCM_ANALOG_MISC0_REG(base) ((base)->MISC0) #define CCM_ANALOG_MISC0_SET_REG(base) ((base)->MISC0_SET) #define CCM_ANALOG_MISC0_CLR_REG(base) ((base)->MISC0_CLR) #define CCM_ANALOG_MISC0_TOG_REG(base) ((base)->MISC0_TOG) #define CCM_ANALOG_MISC1_REG(base) ((base)->MISC1) #define CCM_ANALOG_MISC1_SET_REG(base) ((base)->MISC1_SET) #define CCM_ANALOG_MISC1_CLR_REG(base) ((base)->MISC1_CLR) #define CCM_ANALOG_MISC1_TOG_REG(base) ((base)->MISC1_TOG) #define CCM_ANALOG_MISC2_REG(base) ((base)->MISC2) #define CCM_ANALOG_MISC2_SET_REG(base) ((base)->MISC2_SET) #define CCM_ANALOG_MISC2_CLR_REG(base) ((base)->MISC2_CLR) #define CCM_ANALOG_MISC2_TOG_REG(base) ((base)->MISC2_TOG) /*! * @} */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CCM_ANALOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks * @{ */ /* PLL_ARM Bit Fields */ #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) #define CSI_CSICR2_REG(base) ((base)->CSICR2) #define CSI_CSICR3_REG(base) ((base)->CSICR3) #define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) #define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) #define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) #define CSI_CSISR_REG(base) ((base)->CSISR) #define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) #define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) #define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) #define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) #define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) #define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) #define CSI_CSICR18_REG(base) ((base)->CSICR18) #define CSI_CSICR19_REG(base) ((base)->CSICR19) /*! * @} */ /* end of group CSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CSI_Register_Masks CSI Register Masks * @{ */ /* CSICR1 Bit Fields */ #define CSI_CSICR1_PIXEL_BIT_MASK 0x1u #define CSI_CSICR1_PIXEL_BIT_SHIFT 0 #define CSI_CSICR1_REDGE_MASK 0x2u #define CSI_CSICR1_REDGE_SHIFT 1 #define CSI_CSICR1_INV_PCLK_MASK 0x4u #define CSI_CSICR1_INV_PCLK_SHIFT 2 #define CSI_CSICR1_INV_DATA_MASK 0x8u #define CSI_CSICR1_INV_DATA_SHIFT 3 #define CSI_CSICR1_GCLK_MODE_MASK 0x10u #define CSI_CSICR1_GCLK_MODE_SHIFT 4 #define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u #define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 #define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u #define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 #define CSI_CSICR1_PACK_DIR_MASK 0x80u #define CSI_CSICR1_PACK_DIR_SHIFT 7 #define CSI_CSICR1_FCC_MASK 0x100u #define CSI_CSICR1_FCC_SHIFT 8 #define CSI_CSICR1_CCIR_EN_MASK 0x400u #define CSI_CSICR1_CCIR_EN_SHIFT 10 #define CSI_CSICR1_HSYNC_POL_MASK 0x800u #define CSI_CSICR1_HSYNC_POL_SHIFT 11 #define CSI_CSICR1_SOF_INTEN_MASK 0x10000u #define CSI_CSICR1_SOF_INTEN_SHIFT 16 #define CSI_CSICR1_SOF_POL_MASK 0x20000u #define CSI_CSICR1_SOF_POL_SHIFT 17 #define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u #define CSI_CSICR1_RXFF_INTEN_SHIFT 18 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 #define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u #define CSI_CSICR1_STATFF_INTEN_SHIFT 21 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 #define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u #define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 #define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u #define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 #define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u #define CSI_CSICR1_COF_INT_EN_SHIFT 26 #define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u #define CSI_CSICR1_VIDEO_MODE_SHIFT 27 #define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u #define CSI_CSICR1_PrP_IF_EN_SHIFT 28 #define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u #define CSI_CSICR1_EOF_INT_EN_SHIFT 29 #define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u #define CSI_CSICR1_EXT_VSYNC_SHIFT 30 #define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u #define CSI_CSICR1_SWAP16_EN_SHIFT 31 /* CSICR2 Bit Fields */ #define CSI_CSICR2_HSC_MASK 0xFFu #define CSI_CSICR2_HSC_SHIFT 0 #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<DCICC) #define DCIC_DCICIC_REG(base) ((base)->DCICIC) #define DCIC_DCICS_REG(base) ((base)->DCICS) #define DCIC_DCICRC_REG(base) ((base)->DCICRC) #define DCIC_DCICRS_REG(base) ((base)->DCICRS) #define DCIC_DCICRRS_REG(base) ((base)->DCICRRS) #define DCIC_DCICRCS_REG(base) ((base)->DCICRCS) /*! * @} */ /* end of group DCIC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DCIC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DCIC_Register_Masks DCIC Register Masks * @{ */ /* DCICC Bit Fields */ #define DCIC_DCICC_IC_EN_MASK 0x1u #define DCIC_DCICC_IC_EN_SHIFT 0 #define DCIC_DCICC_DE_POL_MASK 0x10u #define DCIC_DCICC_DE_POL_SHIFT 4 #define DCIC_DCICC_HSYNC_POL_MASK 0x20u #define DCIC_DCICC_HSYNC_POL_SHIFT 5 #define DCIC_DCICC_VSYNC_POL_MASK 0x40u #define DCIC_DCICC_VSYNC_POL_SHIFT 6 #define DCIC_DCICC_CLK_POL_MASK 0x80u #define DCIC_DCICC_CLK_POL_SHIFT 7 /* DCICIC Bit Fields */ #define DCIC_DCICIC_EI_MASK_MASK 0x1u #define DCIC_DCICIC_EI_MASK_SHIFT 0 #define DCIC_DCICIC_FI_MASK_MASK 0x2u #define DCIC_DCICIC_FI_MASK_SHIFT 1 #define DCIC_DCICIC_FREEZE_MASK_MASK 0x8u #define DCIC_DCICIC_FREEZE_MASK_SHIFT 3 #define DCIC_DCICIC_EXT_SIG_EN_MASK 0x10000u #define DCIC_DCICIC_EXT_SIG_EN_SHIFT 16 /* DCICS Bit Fields */ #define DCIC_DCICS_ROI_MATCH_STAT_MASK 0xFFFFu #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT 0 #define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x))<THRS) #define DVFSC_COUN_REG(base) ((base)->COUN) #define DVFSC_SIG1_REG(base) ((base)->SIG1) #define DVFSC_DVFSSIG0_REG(base) ((base)->DVFSSIG0) #define DVFSC_DVFSGPC0_REG(base) ((base)->DVFSGPC0) #define DVFSC_DVFSGPC1_REG(base) ((base)->DVFSGPC1) #define DVFSC_DVFSGPBT_REG(base) ((base)->DVFSGPBT) #define DVFSC_DVFSEMAC_REG(base) ((base)->DVFSEMAC) #define DVFSC_CNTR_REG(base) ((base)->CNTR) #define DVFSC_DVFSLTR0_0_REG(base) ((base)->DVFSLTR0_0) #define DVFSC_DVFSLTR0_1_REG(base) ((base)->DVFSLTR0_1) #define DVFSC_DVFSLTR1_0_REG(base) ((base)->DVFSLTR1_0) #define DVFSC_DVFSLTR1_1_REG(base) ((base)->DVFSLTR1_1) #define DVFSC_DVFSPT0_REG(base) ((base)->DVFSPT0) #define DVFSC_DVFSPT1_REG(base) ((base)->DVFSPT1) #define DVFSC_DVFSPT2_REG(base) ((base)->DVFSPT2) #define DVFSC_DVFSPT3_REG(base) ((base)->DVFSPT3) /*! * @} */ /* end of group DVFSC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DVFSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DVFSC_Register_Masks DVFSC Register Masks * @{ */ /* THRS Bit Fields */ #define DVFSC_THRS_PNCTHR_MASK 0x3Fu #define DVFSC_THRS_PNCTHR_SHIFT 0 #define DVFSC_THRS_PNCTHR(x) (((uint32_t)(((uint32_t)(x))<RXDATA) #define ECSPI_TXDATA_REG(base) ((base)->TXDATA) #define ECSPI_CONREG_REG(base) ((base)->CONREG) #define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) #define ECSPI_INTREG_REG(base) ((base)->INTREG) #define ECSPI_DMAREG_REG(base) ((base)->DMAREG) #define ECSPI_STATREG_REG(base) ((base)->STATREG) #define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) #define ECSPI_TESTREG_REG(base) ((base)->TESTREG) #define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) /*! * @} */ /* end of group ECSPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ECSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ECSPI_Register_Masks ECSPI Register Masks * @{ */ /* RXDATA Bit Fields */ #define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 #define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSGCR1) #define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) #define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) #define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) #define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) #define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) #define EIM_WCR_REG(base) ((base)->WCR) #define EIM_DCR_REG(base) ((base)->DCR) #define EIM_DSR_REG(base) ((base)->DSR) #define EIM_WIAR_REG(base) ((base)->WIAR) #define EIM_EAR_REG(base) ((base)->EAR) /*! * @} */ /* end of group EIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EIM_Register_Masks EIM Register Masks * @{ */ /* CSGCR1 Bit Fields */ #define EIM_CSGCR1_CSEN_MASK 0x1u #define EIM_CSGCR1_CSEN_SHIFT 0 #define EIM_CSGCR1_SWR_MASK 0x2u #define EIM_CSGCR1_SWR_SHIFT 1 #define EIM_CSGCR1_SRD_MASK 0x4u #define EIM_CSGCR1_SRD_SHIFT 2 #define EIM_CSGCR1_MUM_MASK 0x8u #define EIM_CSGCR1_MUM_SHIFT 3 #define EIM_CSGCR1_WFL_MASK 0x10u #define EIM_CSGCR1_WFL_SHIFT 4 #define EIM_CSGCR1_RFL_MASK 0x20u #define EIM_CSGCR1_RFL_SHIFT 5 #define EIM_CSGCR1_CRE_MASK 0x40u #define EIM_CSGCR1_CRE_SHIFT 6 #define EIM_CSGCR1_CREP_MASK 0x80u #define EIM_CSGCR1_CREP_SHIFT 7 #define EIM_CSGCR1_BL_MASK 0x700u #define EIM_CSGCR1_BL_SHIFT 8 #define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<EIR) #define ENET_EIMR_REG(base) ((base)->EIMR) #define ENET_RDAR_REG(base) ((base)->RDAR) #define ENET_TDAR_REG(base) ((base)->TDAR) #define ENET_ECR_REG(base) ((base)->ECR) #define ENET_MMFR_REG(base) ((base)->MMFR) #define ENET_MSCR_REG(base) ((base)->MSCR) #define ENET_MIBC_REG(base) ((base)->MIBC) #define ENET_RCR_REG(base) ((base)->RCR) #define ENET_TCR_REG(base) ((base)->TCR) #define ENET_PALR_REG(base) ((base)->PALR) #define ENET_PAUR_REG(base) ((base)->PAUR) #define ENET_OPD_REG(base) ((base)->OPD) #define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) #define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) #define ENET_IAUR_REG(base) ((base)->IAUR) #define ENET_IALR_REG(base) ((base)->IALR) #define ENET_GAUR_REG(base) ((base)->GAUR) #define ENET_GALR_REG(base) ((base)->GALR) #define ENET_TFWR_REG(base) ((base)->TFWR) #define ENET_RDSR1_REG(base) ((base)->RDSR1) #define ENET_TDSR1_REG(base) ((base)->TDSR1) #define ENET_MRBR1_REG(base) ((base)->MRBR1) #define ENET_RDSR2_REG(base) ((base)->RDSR2) #define ENET_TDSR2_REG(base) ((base)->TDSR2) #define ENET_MRBR2_REG(base) ((base)->MRBR2) #define ENET_RDSR_REG(base) ((base)->RDSR) #define ENET_TDSR_REG(base) ((base)->TDSR) #define ENET_MRBR_REG(base) ((base)->MRBR) #define ENET_RSFL_REG(base) ((base)->RSFL) #define ENET_RSEM_REG(base) ((base)->RSEM) #define ENET_RAEM_REG(base) ((base)->RAEM) #define ENET_RAFL_REG(base) ((base)->RAFL) #define ENET_TSEM_REG(base) ((base)->TSEM) #define ENET_TAEM_REG(base) ((base)->TAEM) #define ENET_TAFL_REG(base) ((base)->TAFL) #define ENET_TIPG_REG(base) ((base)->TIPG) #define ENET_FTRL_REG(base) ((base)->FTRL) #define ENET_TACC_REG(base) ((base)->TACC) #define ENET_RACC_REG(base) ((base)->RACC) #define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) #define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) #define ENET_RDAR1_REG(base) ((base)->RDAR1) #define ENET_TDAR1_REG(base) ((base)->TDAR1) #define ENET_RDAR2_REG(base) ((base)->RDAR2) #define ENET_TDAR2_REG(base) ((base)->TDAR2) #define ENET_QOS_REG(base) ((base)->QOS) #define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) #define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) #define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) #define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) #define ENET_ATCR_REG(base) ((base)->ATCR) #define ENET_ATVR_REG(base) ((base)->ATVR) #define ENET_ATOFF_REG(base) ((base)->ATOFF) #define ENET_ATPER_REG(base) ((base)->ATPER) #define ENET_ATCOR_REG(base) ((base)->ATCOR) #define ENET_ATINC_REG(base) ((base)->ATINC) #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) #define ENET_TGSR_REG(base) ((base)->TGSR) #define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) #define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) /*! * @} */ /* end of group ENET_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /* EIR Bit Fields */ #define ENET_EIR_RXB1_MASK 0x1u #define ENET_EIR_RXB1_SHIFT 0 #define ENET_EIR_RXF1_MASK 0x2u #define ENET_EIR_RXF1_SHIFT 1 #define ENET_EIR_TXB1_MASK 0x4u #define ENET_EIR_TXB1_SHIFT 2 #define ENET_EIR_TXF1_MASK 0x8u #define ENET_EIR_TXF1_SHIFT 3 #define ENET_EIR_RXB2_MASK 0x10u #define ENET_EIR_RXB2_SHIFT 4 #define ENET_EIR_RXF2_MASK 0x20u #define ENET_EIR_RXF2_SHIFT 5 #define ENET_EIR_TXB2_MASK 0x40u #define ENET_EIR_TXB2_SHIFT 6 #define ENET_EIR_TXF2_MASK 0x80u #define ENET_EIR_TXF2_SHIFT 7 #define ENET_EIR_RXFLUSH_0_MASK 0x1000u #define ENET_EIR_RXFLUSH_0_SHIFT 12 #define ENET_EIR_RXFLUSH_1_MASK 0x2000u #define ENET_EIR_RXFLUSH_1_SHIFT 13 #define ENET_EIR_RXFLUSH_2_MASK 0x4000u #define ENET_EIR_RXFLUSH_2_SHIFT 14 #define ENET_EIR_TS_TIMER_MASK 0x8000u #define ENET_EIR_TS_TIMER_SHIFT 15 #define ENET_EIR_TS_AVAIL_MASK 0x10000u #define ENET_EIR_TS_AVAIL_SHIFT 16 #define ENET_EIR_WAKEUP_MASK 0x20000u #define ENET_EIR_WAKEUP_SHIFT 17 #define ENET_EIR_PLR_MASK 0x40000u #define ENET_EIR_PLR_SHIFT 18 #define ENET_EIR_UN_MASK 0x80000u #define ENET_EIR_UN_SHIFT 19 #define ENET_EIR_RL_MASK 0x100000u #define ENET_EIR_RL_SHIFT 20 #define ENET_EIR_LC_MASK 0x200000u #define ENET_EIR_LC_SHIFT 21 #define ENET_EIR_EBERR_MASK 0x400000u #define ENET_EIR_EBERR_SHIFT 22 #define ENET_EIR_MII_MASK 0x800000u #define ENET_EIR_MII_SHIFT 23 #define ENET_EIR_RXB_MASK 0x1000000u #define ENET_EIR_RXB_SHIFT 24 #define ENET_EIR_RXF_MASK 0x2000000u #define ENET_EIR_RXF_SHIFT 25 #define ENET_EIR_TXB_MASK 0x4000000u #define ENET_EIR_TXB_SHIFT 26 #define ENET_EIR_TXF_MASK 0x8000000u #define ENET_EIR_TXF_SHIFT 27 #define ENET_EIR_GRA_MASK 0x10000000u #define ENET_EIR_GRA_SHIFT 28 #define ENET_EIR_BABT_MASK 0x20000000u #define ENET_EIR_BABT_SHIFT 29 #define ENET_EIR_BABR_MASK 0x40000000u #define ENET_EIR_BABR_SHIFT 30 /* EIMR Bit Fields */ #define ENET_EIMR_RXB1_MASK 0x1u #define ENET_EIMR_RXB1_SHIFT 0 #define ENET_EIMR_RXF1_MASK 0x2u #define ENET_EIMR_RXF1_SHIFT 1 #define ENET_EIMR_TXB1_MASK 0x4u #define ENET_EIMR_TXB1_SHIFT 2 #define ENET_EIMR_TXF1_MASK 0x8u #define ENET_EIMR_TXF1_SHIFT 3 #define ENET_EIMR_RXB2_MASK 0x10u #define ENET_EIMR_RXB2_SHIFT 4 #define ENET_EIMR_RXF2_MASK 0x20u #define ENET_EIMR_RXF2_SHIFT 5 #define ENET_EIMR_TXB2_MASK 0x40u #define ENET_EIMR_TXB2_SHIFT 6 #define ENET_EIMR_TXF2_MASK 0x80u #define ENET_EIMR_TXF2_SHIFT 7 #define ENET_EIMR_RXFLUSH_0_MASK 0x1000u #define ENET_EIMR_RXFLUSH_0_SHIFT 12 #define ENET_EIMR_RXFLUSH_1_MASK 0x2000u #define ENET_EIMR_RXFLUSH_1_SHIFT 13 #define ENET_EIMR_RXFLUSH_2_MASK 0x4000u #define ENET_EIMR_RXFLUSH_2_SHIFT 14 #define ENET_EIMR_TS_TIMER_MASK 0x8000u #define ENET_EIMR_TS_TIMER_SHIFT 15 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u #define ENET_EIMR_TS_AVAIL_SHIFT 16 #define ENET_EIMR_WAKEUP_MASK 0x20000u #define ENET_EIMR_WAKEUP_SHIFT 17 #define ENET_EIMR_PLR_MASK 0x40000u #define ENET_EIMR_PLR_SHIFT 18 #define ENET_EIMR_UN_MASK 0x80000u #define ENET_EIMR_UN_SHIFT 19 #define ENET_EIMR_RL_MASK 0x100000u #define ENET_EIMR_RL_SHIFT 20 #define ENET_EIMR_LC_MASK 0x200000u #define ENET_EIMR_LC_SHIFT 21 #define ENET_EIMR_EBERR_MASK 0x400000u #define ENET_EIMR_EBERR_SHIFT 22 #define ENET_EIMR_MII_MASK 0x800000u #define ENET_EIMR_MII_SHIFT 23 #define ENET_EIMR_RXB_MASK 0x1000000u #define ENET_EIMR_RXB_SHIFT 24 #define ENET_EIMR_RXF_MASK 0x2000000u #define ENET_EIMR_RXF_SHIFT 25 #define ENET_EIMR_TXB_MASK 0x4000000u #define ENET_EIMR_TXB_SHIFT 26 #define ENET_EIMR_TXF_MASK 0x8000000u #define ENET_EIMR_TXF_SHIFT 27 #define ENET_EIMR_GRA_MASK 0x10000000u #define ENET_EIMR_GRA_SHIFT 28 #define ENET_EIMR_BABT_MASK 0x20000000u #define ENET_EIMR_BABT_SHIFT 29 #define ENET_EIMR_BABR_MASK 0x40000000u #define ENET_EIMR_BABR_SHIFT 30 /* RDAR Bit Fields */ #define ENET_RDAR_RDAR_MASK 0x1000000u #define ENET_RDAR_RDAR_SHIFT 24 /* TDAR Bit Fields */ #define ENET_TDAR_TDAR_MASK 0x1000000u #define ENET_TDAR_TDAR_SHIFT 24 /* ECR Bit Fields */ #define ENET_ECR_RESET_MASK 0x1u #define ENET_ECR_RESET_SHIFT 0 #define ENET_ECR_ETHEREN_MASK 0x2u #define ENET_ECR_ETHEREN_SHIFT 1 #define ENET_ECR_MAGICEN_MASK 0x4u #define ENET_ECR_MAGICEN_SHIFT 2 #define ENET_ECR_SLEEP_MASK 0x8u #define ENET_ECR_SLEEP_SHIFT 3 #define ENET_ECR_EN1588_MASK 0x10u #define ENET_ECR_EN1588_SHIFT 4 #define ENET_ECR_SPEED_MASK 0x20u #define ENET_ECR_SPEED_SHIFT 5 #define ENET_ECR_DBGEN_MASK 0x40u #define ENET_ECR_DBGEN_SHIFT 6 #define ENET_ECR_DBSWP_MASK 0x100u #define ENET_ECR_DBSWP_SHIFT 8 #define ENET_ECR_SVLANEN_MASK 0x200u #define ENET_ECR_SVLANEN_SHIFT 9 #define ENET_ECR_VLANUSE2ND_MASK 0x400u #define ENET_ECR_VLANUSE2ND_SHIFT 10 #define ENET_ECR_SVLANDBL_MASK 0x800u #define ENET_ECR_SVLANDBL_SHIFT 11 /* MMFR Bit Fields */ #define ENET_MMFR_DATA_MASK 0xFFFFu #define ENET_MMFR_DATA_SHIFT 0 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CR) #define EPIT_SR_REG(base) ((base)->SR) #define EPIT_LR_REG(base) ((base)->LR) #define EPIT_CMPR_REG(base) ((base)->CMPR) #define EPIT_CNR_REG(base) ((base)->CNR) /*! * @} */ /* end of group EPIT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EPIT_Register_Masks EPIT Register Masks * @{ */ /* CR Bit Fields */ #define EPIT_CR_EN_MASK 0x1u #define EPIT_CR_EN_SHIFT 0 #define EPIT_CR_ENMOD_MASK 0x2u #define EPIT_CR_ENMOD_SHIFT 1 #define EPIT_CR_OCIEN_MASK 0x4u #define EPIT_CR_OCIEN_SHIFT 2 #define EPIT_CR_RLD_MASK 0x8u #define EPIT_CR_RLD_SHIFT 3 #define EPIT_CR_PRESCALAR_MASK 0xFFF0u #define EPIT_CR_PRESCALAR_SHIFT 4 #define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x))<ETDR) #define ESAI_ERDR_REG(base) ((base)->ERDR) #define ESAI_ECR_REG(base) ((base)->ECR) #define ESAI_ESR_REG(base) ((base)->ESR) #define ESAI_TFCR_REG(base) ((base)->TFCR) #define ESAI_TFSR_REG(base) ((base)->TFSR) #define ESAI_RFCR_REG(base) ((base)->RFCR) #define ESAI_RFSR_REG(base) ((base)->RFSR) #define ESAI_TX_REG(base,index) ((base)->TX[index]) #define ESAI_TSR_REG(base) ((base)->TSR) #define ESAI_RX_REG(base,index) ((base)->RX[index]) #define ESAI_SAISR_REG(base) ((base)->SAISR) #define ESAI_SAICR_REG(base) ((base)->SAICR) #define ESAI_TCR_REG(base) ((base)->TCR) #define ESAI_TCCR_REG(base) ((base)->TCCR) #define ESAI_RCR_REG(base) ((base)->RCR) #define ESAI_RCCR_REG(base) ((base)->RCCR) #define ESAI_TSMA_REG(base) ((base)->TSMA) #define ESAI_TSMB_REG(base) ((base)->TSMB) #define ESAI_RSMA_REG(base) ((base)->RSMA) #define ESAI_RSMB_REG(base) ((base)->RSMB) #define ESAI_PRRC_REG(base) ((base)->PRRC) #define ESAI_PCRC_REG(base) ((base)->PCRC) /*! * @} */ /* end of group ESAI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ESAI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ESAI_Register_Masks ESAI Register Masks * @{ */ /* ETDR Bit Fields */ #define ESAI_ETDR_ETDR_MASK 0xFFFFFFFFu #define ESAI_ETDR_ETDR_SHIFT 0 #define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define GIS_CTRL_SET_REG(base) ((base)->CTRL_SET) #define GIS_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define GIS_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define GIS_CONFIG0_REG(base) ((base)->CONFIG0) #define GIS_CONFIG0_SET_REG(base) ((base)->CONFIG0_SET) #define GIS_CONFIG0_CLR_REG(base) ((base)->CONFIG0_CLR) #define GIS_CONFIG0_TOG_REG(base) ((base)->CONFIG0_TOG) #define GIS_CONFIG1_REG(base) ((base)->CONFIG1) #define GIS_CONFIG1_SET_REG(base) ((base)->CONFIG1_SET) #define GIS_CONFIG1_CLR_REG(base) ((base)->CONFIG1_CLR) #define GIS_CONFIG1_TOG_REG(base) ((base)->CONFIG1_TOG) #define GIS_FB0_REG(base) ((base)->FB0) #define GIS_FB1_REG(base) ((base)->FB1) #define GIS_PXP_FB0_REG(base) ((base)->PXP_FB0) #define GIS_PXP_FB1_REG(base) ((base)->PXP_FB1) #define GIS_CH0_CTRL_REG(base) ((base)->CH0_CTRL) #define GIS_CH0_CTRL_SET_REG(base) ((base)->CH0_CTRL_SET) #define GIS_CH0_CTRL_CLR_REG(base) ((base)->CH0_CTRL_CLR) #define GIS_CH0_CTRL_TOG_REG(base) ((base)->CH0_CTRL_TOG) #define GIS_CH0_ADDR0_REG(base) ((base)->CH0_ADDR0) #define GIS_CH0_ADDR0_SET_REG(base) ((base)->CH0_ADDR0_SET) #define GIS_CH0_ADDR0_CLR_REG(base) ((base)->CH0_ADDR0_CLR) #define GIS_CH0_ADDR0_TOG_REG(base) ((base)->CH0_ADDR0_TOG) #define GIS_CH0_DATA0_REG(base) ((base)->CH0_DATA0) #define GIS_CH0_ADDR1_REG(base) ((base)->CH0_ADDR1) #define GIS_CH0_ADDR1_SET_REG(base) ((base)->CH0_ADDR1_SET) #define GIS_CH0_ADDR1_CLR_REG(base) ((base)->CH0_ADDR1_CLR) #define GIS_CH0_ADDR1_TOG_REG(base) ((base)->CH0_ADDR1_TOG) #define GIS_CH0_DATA1_REG(base) ((base)->CH0_DATA1) #define GIS_CH0_ADDR2_REG(base) ((base)->CH0_ADDR2) #define GIS_CH0_ADDR2_SET_REG(base) ((base)->CH0_ADDR2_SET) #define GIS_CH0_ADDR2_CLR_REG(base) ((base)->CH0_ADDR2_CLR) #define GIS_CH0_ADDR2_TOG_REG(base) ((base)->CH0_ADDR2_TOG) #define GIS_CH0_DATA2_REG(base) ((base)->CH0_DATA2) #define GIS_CH0_ADDR3_REG(base) ((base)->CH0_ADDR3) #define GIS_CH0_ADDR3_SET_REG(base) ((base)->CH0_ADDR3_SET) #define GIS_CH0_ADDR3_CLR_REG(base) ((base)->CH0_ADDR3_CLR) #define GIS_CH0_ADDR3_TOG_REG(base) ((base)->CH0_ADDR3_TOG) #define GIS_CH0_DATA3_REG(base) ((base)->CH0_DATA3) #define GIS_CH1_CTRL_REG(base) ((base)->CH1_CTRL) #define GIS_CH1_CTRL_SET_REG(base) ((base)->CH1_CTRL_SET) #define GIS_CH1_CTRL_CLR_REG(base) ((base)->CH1_CTRL_CLR) #define GIS_CH1_CTRL_TOG_REG(base) ((base)->CH1_CTRL_TOG) #define GIS_CH1_ADDR0_REG(base) ((base)->CH1_ADDR0) #define GIS_CH1_ADDR0_SET_REG(base) ((base)->CH1_ADDR0_SET) #define GIS_CH1_ADDR0_CLR_REG(base) ((base)->CH1_ADDR0_CLR) #define GIS_CH1_ADDR0_TOG_REG(base) ((base)->CH1_ADDR0_TOG) #define GIS_CH1_DATA0_REG(base) ((base)->CH1_DATA0) #define GIS_CH1_ADDR1_REG(base) ((base)->CH1_ADDR1) #define GIS_CH1_ADDR1_SET_REG(base) ((base)->CH1_ADDR1_SET) #define GIS_CH1_ADDR1_CLR_REG(base) ((base)->CH1_ADDR1_CLR) #define GIS_CH1_ADDR1_TOG_REG(base) ((base)->CH1_ADDR1_TOG) #define GIS_CH1_DATA1_REG(base) ((base)->CH1_DATA1) #define GIS_CH1_ADDR2_REG(base) ((base)->CH1_ADDR2) #define GIS_CH1_ADDR2_SET_REG(base) ((base)->CH1_ADDR2_SET) #define GIS_CH1_ADDR2_CLR_REG(base) ((base)->CH1_ADDR2_CLR) #define GIS_CH1_ADDR2_TOG_REG(base) ((base)->CH1_ADDR2_TOG) #define GIS_CH1_DATA2_REG(base) ((base)->CH1_DATA2) #define GIS_CH1_ADDR3_REG(base) ((base)->CH1_ADDR3) #define GIS_CH1_ADDR3_SET_REG(base) ((base)->CH1_ADDR3_SET) #define GIS_CH1_ADDR3_CLR_REG(base) ((base)->CH1_ADDR3_CLR) #define GIS_CH1_ADDR3_TOG_REG(base) ((base)->CH1_ADDR3_TOG) #define GIS_CH1_DATA3_REG(base) ((base)->CH1_DATA3) #define GIS_CH2_CTRL_REG(base) ((base)->CH2_CTRL) #define GIS_CH2_CTRL_SET_REG(base) ((base)->CH2_CTRL_SET) #define GIS_CH2_CTRL_CLR_REG(base) ((base)->CH2_CTRL_CLR) #define GIS_CH2_CTRL_TOG_REG(base) ((base)->CH2_CTRL_TOG) #define GIS_CH2_ADDR0_REG(base) ((base)->CH2_ADDR0) #define GIS_CH2_ADDR0_SET_REG(base) ((base)->CH2_ADDR0_SET) #define GIS_CH2_ADDR0_CLR_REG(base) ((base)->CH2_ADDR0_CLR) #define GIS_CH2_ADDR0_TOG_REG(base) ((base)->CH2_ADDR0_TOG) #define GIS_CH2_DATA0_REG(base) ((base)->CH2_DATA0) #define GIS_CH2_ADDR1_REG(base) ((base)->CH2_ADDR1) #define GIS_CH2_ADDR1_SET_REG(base) ((base)->CH2_ADDR1_SET) #define GIS_CH2_ADDR1_CLR_REG(base) ((base)->CH2_ADDR1_CLR) #define GIS_CH2_ADDR1_TOG_REG(base) ((base)->CH2_ADDR1_TOG) #define GIS_CH2_DATA1_REG(base) ((base)->CH2_DATA1) #define GIS_CH2_ADDR2_REG(base) ((base)->CH2_ADDR2) #define GIS_CH2_ADDR2_SET_REG(base) ((base)->CH2_ADDR2_SET) #define GIS_CH2_ADDR2_CLR_REG(base) ((base)->CH2_ADDR2_CLR) #define GIS_CH2_ADDR2_TOG_REG(base) ((base)->CH2_ADDR2_TOG) #define GIS_CH2_DATA2_REG(base) ((base)->CH2_DATA2) #define GIS_CH2_ADDR3_REG(base) ((base)->CH2_ADDR3) #define GIS_CH2_ADDR3_SET_REG(base) ((base)->CH2_ADDR3_SET) #define GIS_CH2_ADDR3_CLR_REG(base) ((base)->CH2_ADDR3_CLR) #define GIS_CH2_ADDR3_TOG_REG(base) ((base)->CH2_ADDR3_TOG) #define GIS_CH2_DATA3_REG(base) ((base)->CH2_DATA3) #define GIS_CH3_CTRL_REG(base) ((base)->CH3_CTRL) #define GIS_CH3_CTRL_SET_REG(base) ((base)->CH3_CTRL_SET) #define GIS_CH3_CTRL_CLR_REG(base) ((base)->CH3_CTRL_CLR) #define GIS_CH3_CTRL_TOG_REG(base) ((base)->CH3_CTRL_TOG) #define GIS_CH3_ADDR0_REG(base) ((base)->CH3_ADDR0) #define GIS_CH3_ADDR0_SET_REG(base) ((base)->CH3_ADDR0_SET) #define GIS_CH3_ADDR0_CLR_REG(base) ((base)->CH3_ADDR0_CLR) #define GIS_CH3_ADDR0_TOG_REG(base) ((base)->CH3_ADDR0_TOG) #define GIS_CH3_DATA0_REG(base) ((base)->CH3_DATA0) #define GIS_CH3_ADDR1_REG(base) ((base)->CH3_ADDR1) #define GIS_CH3_ADDR1_SET_REG(base) ((base)->CH3_ADDR1_SET) #define GIS_CH3_ADDR1_CLR_REG(base) ((base)->CH3_ADDR1_CLR) #define GIS_CH3_ADDR1_TOG_REG(base) ((base)->CH3_ADDR1_TOG) #define GIS_CH3_DATA1_REG(base) ((base)->CH3_DATA1) #define GIS_CH3_ADDR2_REG(base) ((base)->CH3_ADDR2) #define GIS_CH3_ADDR2_SET_REG(base) ((base)->CH3_ADDR2_SET) #define GIS_CH3_ADDR2_CLR_REG(base) ((base)->CH3_ADDR2_CLR) #define GIS_CH3_ADDR2_TOG_REG(base) ((base)->CH3_ADDR2_TOG) #define GIS_CH3_DATA2_REG(base) ((base)->CH3_DATA2) #define GIS_CH3_ADDR3_REG(base) ((base)->CH3_ADDR3) #define GIS_CH3_ADDR3_SET_REG(base) ((base)->CH3_ADDR3_SET) #define GIS_CH3_ADDR3_CLR_REG(base) ((base)->CH3_ADDR3_CLR) #define GIS_CH3_ADDR3_TOG_REG(base) ((base)->CH3_ADDR3_TOG) #define GIS_CH3_DATA3_REG(base) ((base)->CH3_DATA3) #define GIS_CH4_CTRL_REG(base) ((base)->CH4_CTRL) #define GIS_CH4_CTRL_SET_REG(base) ((base)->CH4_CTRL_SET) #define GIS_CH4_CTRL_CLR_REG(base) ((base)->CH4_CTRL_CLR) #define GIS_CH4_CTRL_TOG_REG(base) ((base)->CH4_CTRL_TOG) #define GIS_CH4_ADDR0_REG(base) ((base)->CH4_ADDR0) #define GIS_CH4_ADDR0_SET_REG(base) ((base)->CH4_ADDR0_SET) #define GIS_CH4_ADDR0_CLR_REG(base) ((base)->CH4_ADDR0_CLR) #define GIS_CH4_ADDR0_TOG_REG(base) ((base)->CH4_ADDR0_TOG) #define GIS_CH4_DATA0_REG(base) ((base)->CH4_DATA0) #define GIS_CH4_ADDR1_REG(base) ((base)->CH4_ADDR1) #define GIS_CH4_ADDR1_SET_REG(base) ((base)->CH4_ADDR1_SET) #define GIS_CH4_ADDR1_CLR_REG(base) ((base)->CH4_ADDR1_CLR) #define GIS_CH4_ADDR1_TOG_REG(base) ((base)->CH4_ADDR1_TOG) #define GIS_CH4_DATA1_REG(base) ((base)->CH4_DATA1) #define GIS_CH4_ADDR2_REG(base) ((base)->CH4_ADDR2) #define GIS_CH4_ADDR2_SET_REG(base) ((base)->CH4_ADDR2_SET) #define GIS_CH4_ADDR2_CLR_REG(base) ((base)->CH4_ADDR2_CLR) #define GIS_CH4_ADDR2_TOG_REG(base) ((base)->CH4_ADDR2_TOG) #define GIS_CH4_DATA2_REG(base) ((base)->CH4_DATA2) #define GIS_CH4_ADDR3_REG(base) ((base)->CH4_ADDR3) #define GIS_CH4_ADDR3_SET_REG(base) ((base)->CH4_ADDR3_SET) #define GIS_CH4_ADDR3_CLR_REG(base) ((base)->CH4_ADDR3_CLR) #define GIS_CH4_ADDR3_TOG_REG(base) ((base)->CH4_ADDR3_TOG) #define GIS_CH4_DATA3_REG(base) ((base)->CH4_DATA3) #define GIS_CH5_CTRL_REG(base) ((base)->CH5_CTRL) #define GIS_CH5_CTRL_SET_REG(base) ((base)->CH5_CTRL_SET) #define GIS_CH5_CTRL_CLR_REG(base) ((base)->CH5_CTRL_CLR) #define GIS_CH5_CTRL_TOG_REG(base) ((base)->CH5_CTRL_TOG) #define GIS_CH5_ADDR0_REG(base) ((base)->CH5_ADDR0) #define GIS_CH5_ADDR0_SET_REG(base) ((base)->CH5_ADDR0_SET) #define GIS_CH5_ADDR0_CLR_REG(base) ((base)->CH5_ADDR0_CLR) #define GIS_CH5_ADDR0_TOG_REG(base) ((base)->CH5_ADDR0_TOG) #define GIS_CH5_DATA0_REG(base) ((base)->CH5_DATA0) #define GIS_CH5_ADDR1_REG(base) ((base)->CH5_ADDR1) #define GIS_CH5_ADDR1_SET_REG(base) ((base)->CH5_ADDR1_SET) #define GIS_CH5_ADDR1_CLR_REG(base) ((base)->CH5_ADDR1_CLR) #define GIS_CH5_ADDR1_TOG_REG(base) ((base)->CH5_ADDR1_TOG) #define GIS_CH5_DATA1_REG(base) ((base)->CH5_DATA1) #define GIS_CH5_ADDR2_REG(base) ((base)->CH5_ADDR2) #define GIS_CH5_ADDR2_SET_REG(base) ((base)->CH5_ADDR2_SET) #define GIS_CH5_ADDR2_CLR_REG(base) ((base)->CH5_ADDR2_CLR) #define GIS_CH5_ADDR2_TOG_REG(base) ((base)->CH5_ADDR2_TOG) #define GIS_CH5_DATA2_REG(base) ((base)->CH5_DATA2) #define GIS_CH5_ADDR3_REG(base) ((base)->CH5_ADDR3) #define GIS_CH5_ADDR3_SET_REG(base) ((base)->CH5_ADDR3_SET) #define GIS_CH5_ADDR3_CLR_REG(base) ((base)->CH5_ADDR3_CLR) #define GIS_CH5_ADDR3_TOG_REG(base) ((base)->CH5_ADDR3_TOG) #define GIS_CH5_DATA3_REG(base) ((base)->CH5_DATA3) #define GIS_DEBUG0_REG(base) ((base)->DEBUG0) #define GIS_DEBUG1_REG(base) ((base)->DEBUG1) #define GIS_VERSION_REG(base) ((base)->VERSION) /*! * @} */ /* end of group GIS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GIS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GIS_Register_Masks GIS Register Masks * @{ */ /* CTRL Bit Fields */ #define GIS_CTRL_ENABLE_MASK 0x1u #define GIS_CTRL_ENABLE_SHIFT 0 #define GIS_CTRL_FB_START_MASK 0x2u #define GIS_CTRL_FB_START_SHIFT 1 #define GIS_CTRL_LCDIF_SEL_MASK 0x4u #define GIS_CTRL_LCDIF_SEL_SHIFT 2 #define GIS_CTRL_CSI_SEL_MASK 0x8u #define GIS_CTRL_CSI_SEL_SHIFT 3 #define GIS_CTRL_CSI0_IRQ_POLARITY_MASK 0x10u #define GIS_CTRL_CSI0_IRQ_POLARITY_SHIFT 4 #define GIS_CTRL_CSI1_IRQ_POLARITY_MASK 0x20u #define GIS_CTRL_CSI1_IRQ_POLARITY_SHIFT 5 #define GIS_CTRL_PXP_IRQ_POLARITY_MASK 0x40u #define GIS_CTRL_PXP_IRQ_POLARITY_SHIFT 6 #define GIS_CTRL_LCDIF0_IRQ_POLARITY_MASK 0x80u #define GIS_CTRL_LCDIF0_IRQ_POLARITY_SHIFT 7 #define GIS_CTRL_LCDIF1_IRQ_POLARITY_MASK 0x100u #define GIS_CTRL_LCDIF1_IRQ_POLARITY_SHIFT 8 #define GIS_CTRL_CLKGATE_MASK 0x40000000u #define GIS_CTRL_CLKGATE_SHIFT 30 #define GIS_CTRL_SFTRST_MASK 0x80000000u #define GIS_CTRL_SFTRST_SHIFT 31 /* CTRL_SET Bit Fields */ #define GIS_CTRL_SET_ENABLE_MASK 0x1u #define GIS_CTRL_SET_ENABLE_SHIFT 0 #define GIS_CTRL_SET_FB_START_MASK 0x2u #define GIS_CTRL_SET_FB_START_SHIFT 1 #define GIS_CTRL_SET_LCDIF_SEL_MASK 0x4u #define GIS_CTRL_SET_LCDIF_SEL_SHIFT 2 #define GIS_CTRL_SET_CSI_SEL_MASK 0x8u #define GIS_CTRL_SET_CSI_SEL_SHIFT 3 #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_MASK 0x10u #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_SHIFT 4 #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_MASK 0x20u #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_SHIFT 5 #define GIS_CTRL_SET_PXP_IRQ_POLARITY_MASK 0x40u #define GIS_CTRL_SET_PXP_IRQ_POLARITY_SHIFT 6 #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_MASK 0x80u #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_SHIFT 7 #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_MASK 0x100u #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_SHIFT 8 #define GIS_CTRL_SET_CLKGATE_MASK 0x40000000u #define GIS_CTRL_SET_CLKGATE_SHIFT 30 #define GIS_CTRL_SET_SFTRST_MASK 0x80000000u #define GIS_CTRL_SET_SFTRST_SHIFT 31 /* CTRL_CLR Bit Fields */ #define GIS_CTRL_CLR_ENABLE_MASK 0x1u #define GIS_CTRL_CLR_ENABLE_SHIFT 0 #define GIS_CTRL_CLR_FB_START_MASK 0x2u #define GIS_CTRL_CLR_FB_START_SHIFT 1 #define GIS_CTRL_CLR_LCDIF_SEL_MASK 0x4u #define GIS_CTRL_CLR_LCDIF_SEL_SHIFT 2 #define GIS_CTRL_CLR_CSI_SEL_MASK 0x8u #define GIS_CTRL_CLR_CSI_SEL_SHIFT 3 #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_MASK 0x10u #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_SHIFT 4 #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_MASK 0x20u #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_SHIFT 5 #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_MASK 0x40u #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_SHIFT 6 #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_MASK 0x80u #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_SHIFT 7 #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_MASK 0x100u #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_SHIFT 8 #define GIS_CTRL_CLR_CLKGATE_MASK 0x40000000u #define GIS_CTRL_CLR_CLKGATE_SHIFT 30 #define GIS_CTRL_CLR_SFTRST_MASK 0x80000000u #define GIS_CTRL_CLR_SFTRST_SHIFT 31 /* CTRL_TOG Bit Fields */ #define GIS_CTRL_TOG_ENABLE_MASK 0x1u #define GIS_CTRL_TOG_ENABLE_SHIFT 0 #define GIS_CTRL_TOG_FB_START_MASK 0x2u #define GIS_CTRL_TOG_FB_START_SHIFT 1 #define GIS_CTRL_TOG_LCDIF_SEL_MASK 0x4u #define GIS_CTRL_TOG_LCDIF_SEL_SHIFT 2 #define GIS_CTRL_TOG_CSI_SEL_MASK 0x8u #define GIS_CTRL_TOG_CSI_SEL_SHIFT 3 #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_MASK 0x10u #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_SHIFT 4 #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_MASK 0x20u #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_SHIFT 5 #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_MASK 0x40u #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_SHIFT 6 #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_MASK 0x80u #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_SHIFT 7 #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_MASK 0x100u #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_SHIFT 8 #define GIS_CTRL_TOG_CLKGATE_MASK 0x40000000u #define GIS_CTRL_TOG_CLKGATE_SHIFT 30 #define GIS_CTRL_TOG_SFTRST_MASK 0x80000000u #define GIS_CTRL_TOG_SFTRST_SHIFT 31 /* CONFIG0 Bit Fields */ #define GIS_CONFIG0_CH0_MAPPING_MASK 0x7u #define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 #define GIS_CONFIG0_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<CNTR) #define GPC_PGR_REG(base) ((base)->PGR) #define GPC_IMR1_REG(base) ((base)->IMR1) #define GPC_IMR2_REG(base) ((base)->IMR2) #define GPC_IMR3_REG(base) ((base)->IMR3) #define GPC_IMR4_REG(base) ((base)->IMR4) #define GPC_ISR1_REG(base) ((base)->ISR1) #define GPC_ISR2_REG(base) ((base)->ISR2) #define GPC_ISR3_REG(base) ((base)->ISR3) #define GPC_ISR4_REG(base) ((base)->ISR4) #define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) #define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) #define GPC_DR_REG(base) ((base)->DR) /*! * @} */ /* end of group GPC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Register_Masks GPC Register Masks * @{ */ /* CNTR Bit Fields */ #define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u #define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 #define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u #define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 #define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u #define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 #define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u #define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 #define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u #define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 #define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u #define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 #define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u #define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 #define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u #define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 #define GPC_CNTR_DVFS0CR_MASK 0x10000u #define GPC_CNTR_DVFS0CR_SHIFT 16 #define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u #define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 #define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u #define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 #define GPC_CNTR_GPCIRQM_MASK 0x200000u #define GPC_CNTR_GPCIRQM_SHIFT 21 #define GPC_CNTR_L2_PGE_MASK 0x400000u #define GPC_CNTR_L2_PGE_SHIFT 22 /* PGR Bit Fields */ #define GPC_PGR_DRCIC_MASK 0x60000000u #define GPC_PGR_DRCIC_SHIFT 29 #define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<DR) #define GPIO_GDIR_REG(base) ((base)->GDIR) #define GPIO_PSR_REG(base) ((base)->PSR) #define GPIO_ICR1_REG(base) ((base)->ICR1) #define GPIO_ICR2_REG(base) ((base)->ICR2) #define GPIO_IMR_REG(base) ((base)->IMR) #define GPIO_ISR_REG(base) ((base)->ISR) #define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /* DR Bit Fields */ #define GPIO_DR_DR_MASK 0xFFFFFFFFu #define GPIO_DR_DR_SHIFT 0 #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) #define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) #define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) #define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) #define GPMI_COMPARE_REG(base) ((base)->COMPARE) #define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) #define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) #define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) #define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) #define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) #define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) #define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) #define GPMI_CTRL1_REG(base) ((base)->CTRL1) #define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) #define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) #define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) #define GPMI_TIMING0_REG(base) ((base)->TIMING0) #define GPMI_TIMING1_REG(base) ((base)->TIMING1) #define GPMI_TIMING2_REG(base) ((base)->TIMING2) #define GPMI_DATA_REG(base) ((base)->DATA) #define GPMI_STAT_REG(base) ((base)->STAT) #define GPMI_DEBUG_REG(base) ((base)->DEBUG) #define GPMI_VERSION_REG(base) ((base)->VERSION) #define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) #define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) #define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) #define GPMI_WRITE_DDR_DLL_CTRL_REG(base) ((base)->WRITE_DDR_DLL_CTRL) #define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) #define GPMI_WRITE_DDR_DLL_STS_REG(base) ((base)->WRITE_DDR_DLL_STS) /*! * @} */ /* end of group GPMI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPMI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Register_Masks GPMI Register Masks * @{ */ /* CTRL0 Bit Fields */ #define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu #define GPMI_CTRL0_XFER_COUNT_SHIFT 0 #define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) #define GPT_PR_REG(base) ((base)->PR) #define GPT_SR_REG(base) ((base)->SR) #define GPT_IR_REG(base) ((base)->IR) #define GPT_OCR1_REG(base) ((base)->OCR1) #define GPT_OCR2_REG(base) ((base)->OCR2) #define GPT_OCR3_REG(base) ((base)->OCR3) #define GPT_ICR1_REG(base) ((base)->ICR1) #define GPT_ICR2_REG(base) ((base)->ICR2) #define GPT_CNT_REG(base) ((base)->CNT) /*! * @} */ /* end of group GPT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Register_Masks GPT Register Masks * @{ */ /* CR Bit Fields */ #define GPT_CR_EN_MASK 0x1u #define GPT_CR_EN_SHIFT 0 #define GPT_CR_ENMOD_MASK 0x2u #define GPT_CR_ENMOD_SHIFT 1 #define GPT_CR_DBGEN_MASK 0x4u #define GPT_CR_DBGEN_SHIFT 2 #define GPT_CR_WAITEN_MASK 0x8u #define GPT_CR_WAITEN_SHIFT 3 #define GPT_CR_DOZEEN_MASK 0x10u #define GPT_CR_DOZEEN_SHIFT 4 #define GPT_CR_STOPEN_MASK 0x20u #define GPT_CR_STOPEN_SHIFT 5 #define GPT_CR_CLKSRC_MASK 0x1C0u #define GPT_CR_CLKSRC_SHIFT 6 #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) #define I2C_IFDR_REG(base) ((base)->IFDR) #define I2C_I2CR_REG(base) ((base)->I2CR) #define I2C_I2SR_REG(base) ((base)->I2SR) #define I2C_I2DR_REG(base) ((base)->I2DR) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* IADR Bit Fields */ #define I2C_IADR_ADR_MASK 0xFEu #define I2C_IADR_ADR_SHIFT 1 #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) #define I2S_TCR1_REG(base) ((base)->TCR1) #define I2S_TCR2_REG(base) ((base)->TCR2) #define I2S_TCR3_REG(base) ((base)->TCR3) #define I2S_TCR4_REG(base) ((base)->TCR4) #define I2S_TCR5_REG(base) ((base)->TCR5) #define I2S_TDR_REG(base,index) ((base)->TDR[index]) #define I2S_TFR_REG(base,index) ((base)->TFR[index]) #define I2S_TMR_REG(base) ((base)->TMR) #define I2S_RCSR_REG(base) ((base)->RCSR) #define I2S_RCR1_REG(base) ((base)->RCR1) #define I2S_RCR2_REG(base) ((base)->RCR2) #define I2S_RCR3_REG(base) ((base)->RCR3) #define I2S_RCR4_REG(base) ((base)->RCR4) #define I2S_RCR5_REG(base) ((base)->RCR5) #define I2S_RDR_REG(base,index) ((base)->RDR[index]) #define I2S_RFR_REG(base,index) ((base)->RFR[index]) #define I2S_RMR_REG(base) ((base)->RMR) /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /* TCSR Bit Fields */ #define I2S_TCSR_FRDE_MASK 0x1u #define I2S_TCSR_FRDE_SHIFT 0 #define I2S_TCSR_FWDE_MASK 0x2u #define I2S_TCSR_FWDE_SHIFT 1 #define I2S_TCSR_FRIE_MASK 0x100u #define I2S_TCSR_FRIE_SHIFT 8 #define I2S_TCSR_FWIE_MASK 0x200u #define I2S_TCSR_FWIE_SHIFT 9 #define I2S_TCSR_FEIE_MASK 0x400u #define I2S_TCSR_FEIE_SHIFT 10 #define I2S_TCSR_SEIE_MASK 0x800u #define I2S_TCSR_SEIE_SHIFT 11 #define I2S_TCSR_WSIE_MASK 0x1000u #define I2S_TCSR_WSIE_SHIFT 12 #define I2S_TCSR_FRF_MASK 0x10000u #define I2S_TCSR_FRF_SHIFT 16 #define I2S_TCSR_FWF_MASK 0x20000u #define I2S_TCSR_FWF_SHIFT 17 #define I2S_TCSR_FEF_MASK 0x40000u #define I2S_TCSR_FEF_SHIFT 18 #define I2S_TCSR_SEF_MASK 0x80000u #define I2S_TCSR_SEF_SHIFT 19 #define I2S_TCSR_WSF_MASK 0x100000u #define I2S_TCSR_WSF_SHIFT 20 #define I2S_TCSR_SR_MASK 0x1000000u #define I2S_TCSR_SR_SHIFT 24 #define I2S_TCSR_FR_MASK 0x2000000u #define I2S_TCSR_FR_SHIFT 25 #define I2S_TCSR_BCE_MASK 0x10000000u #define I2S_TCSR_BCE_SHIFT 28 #define I2S_TCSR_DBGE_MASK 0x20000000u #define I2S_TCSR_DBGE_SHIFT 29 #define I2S_TCSR_STOPE_MASK 0x40000000u #define I2S_TCSR_STOPE_SHIFT 30 #define I2S_TCSR_TE_MASK 0x80000000u #define I2S_TCSR_TE_SHIFT 31 /* TCR1 Bit Fields */ #define I2S_TCR1_TFW_MASK 0x1Fu #define I2S_TCR1_TFW_SHIFT 0 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA00) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA01) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA02) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA03) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA04) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA05) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA06) #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA07) #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_HSYNC) #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_MCLK) #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_PIXCLK) #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_VSYNC) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDC) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDIO) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_COL) #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_CRS) #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_RX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_TX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL0) #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL1) #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL2) #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL3) #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL4) #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW0) #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW1) #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW2) #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW3) #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW4) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_CLK) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA00) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA01) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA02) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA03) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA04) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA05) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA06) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA07) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA08) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA09) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA10) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA11) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA12) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA13) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA14) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA15) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA16) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA17) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA18) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA19) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA20) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA21) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA22) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA23) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_ENABLE) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_HSYNC) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_RESET) #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_VSYNC) #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_ALE) #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE0_B) #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE1_B) #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CLE) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA00) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA01) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA02) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA03) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA04) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA05) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA06) #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA07) #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_RE_B) #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_READY_B) #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WE_B) #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WP_B) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DQS) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SCLK) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS0_B) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS1_B) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DQS) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SCLK) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS0_B) #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS1_B) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD0) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD1) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD2) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD3) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RXC) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD0) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD1) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD2) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD3) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TXC) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD0) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD1) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD2) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD3) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RXC) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD0) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD1) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD2) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD3) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TXC) #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA4) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA5) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA6) #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA7) #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_RESET_B) #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_DATA) #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_STROBE) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR00) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR01) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR02) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR03) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR04) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR06) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR07) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR08) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR09) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR10) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR11) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR12) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR13) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR14) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR15) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM0) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM1) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM3) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RAS_B) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CAS_B) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS0_B) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS1_B) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDWE_B) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT0) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT1) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA0) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA2) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE0) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE1) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCLK0_P) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS0_P) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS1_P) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS2_P) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P) #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RESET) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA00) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA01) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA02) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA03) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA04) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA05) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA06) #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA07) #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_HSYNC) #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_MCLK) #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_PIXCLK) #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_VSYNC) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDC) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDIO) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_COL) #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_CRS) #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_RX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_TX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL0) #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL1) #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL2) #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL3) #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL4) #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW0) #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW1) #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW2) #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW3) #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW4) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_CLK) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA00) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA01) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA02) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA03) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA04) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA05) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA06) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA07) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA08) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA09) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA10) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA11) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA12) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA13) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA14) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA15) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA16) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA17) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA18) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA19) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA20) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA21) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA22) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA23) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_ENABLE) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_HSYNC) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_RESET) #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_VSYNC) #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_ALE) #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE0_B) #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE1_B) #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CLE) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA00) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA01) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA02) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA03) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA04) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA05) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA06) #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA07) #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_RE_B) #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_READY_B) #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WE_B) #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WP_B) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DQS) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SCLK) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS0_B) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS1_B) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DQS) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SCLK) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS0_B) #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS1_B) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD0) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD1) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD2) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD3) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RXC) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD0) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD1) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD2) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD3) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TXC) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD0) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD1) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD2) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD3) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RXC) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD0) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD1) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD2) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD3) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TXC) #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA4) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA5) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA6) #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA7) #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_RESET_B) #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_DATA) #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_STROBE) #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(base) ((base)->SW_PAD_CTL_GRP_ADDDS) #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE_CTL) #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPKE) #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPK) #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(base) ((base)->SW_PAD_CTL_GRP_DDRHYS) #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE) #define IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(base) ((base)->SW_PAD_CTL_GRP_B0DS) #define IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(base) ((base)->SW_PAD_CTL_GRP_B1DS) #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(base) ((base)->SW_PAD_CTL_GRP_CTLDS) #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(base) ((base)->SW_PAD_CTL_GRP_DDR_TYPE) #define IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(base) ((base)->SW_PAD_CTL_GRP_B2DS) #define IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(base) ((base)->SW_PAD_CTL_GRP_B3DS) #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_OTG_ID_SELECT_INPUT) #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_UH1_ID_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT) #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT) #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN1_IPP_IND_CANRX_SELECT_INPUT) #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN2_IPP_IND_CANRX_SELECT_INPUT) #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_0) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_1) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_2) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_3) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_4) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_5) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_6) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_7) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_8) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_9) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_11) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_12) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_13) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_14) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_15) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_16) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_17) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_18) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_19) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_20) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_21) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_22) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_23) #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_10) #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_HSYNC_SELECT_INPUT) #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_PIXCLK_SELECT_INPUT) #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_VSYNC_SELECT_INPUT) #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(base) ((base)->CSI1_TVDECODER_IN_FIELD_SELECT_INPUT) #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT) #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MISO_SELECT_INPUT) #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0) #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT) #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MISO_SELECT_INPUT) #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0) #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT) #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MISO_SELECT_INPUT) #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0) #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT) #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MISO_SELECT_INPUT) #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0) #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT) #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MISO_SELECT_INPUT) #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0) #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET1_IPG_CLK_RMII_SELECT_INPUT) #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT) #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT) #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET2_IPG_CLK_RMII_SELECT_INPUT) #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT) #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FSR_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FST_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKR_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKT_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKR_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKT_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO0_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO1_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT) #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT) #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SCL_IN_SELECT_INPUT) #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SDA_IN_SELECT_INPUT) #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SCL_IN_SELECT_INPUT) #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SDA_IN_SELECT_INPUT) #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SCL_IN_SELECT_INPUT) #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SDA_IN_SELECT_INPUT) #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SCL_IN_SELECT_INPUT) #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SDA_IN_SELECT_INPUT) #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_5) #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_6) #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_7) #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_5) #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_6) #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_7) #define IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(base) ((base)->LCD1_BUSY_SELECT_INPUT) #define IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(base) ((base)->LCD2_BUSY_SELECT_INPUT) #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_CLK_IN_SELECT_INPUT) #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_DATA_IN_SELECT_INPUT) #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_SIG_IN_SELECT_INPUT) #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT) #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT) #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT) #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT) #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT) #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT) #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT) #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT) #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_14) #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_15) #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(base) ((base)->SPDIF_SPDIF_IN1_SELECT_INPUT) #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(base) ((base)->SPDIF_TX_CLK2_SELECT_INPUT) #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RTS_B_SELECT_INPUT) #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RXD_MUX_SELECT_INPUT) #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG2_OC_SELECT_INPUT) #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG_OC_SELECT_INPUT) #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_CARD_DET_SELECT_INPUT) #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_WP_ON_SELECT_INPUT) #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_CARD_DET_SELECT_INPUT) #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_WP_ON_SELECT_INPUT) #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_CARD_DET_SELECT_INPUT) #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_WP_ON_SELECT_INPUT) /*! * @} */ /* end of group IOMUXC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- IOMUXC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks * @{ */ /* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) #define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) #define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) #define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) #define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) #define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) #define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) #define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) #define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) #define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) #define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) #define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) #define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) #define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) /*! * @} */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks * @{ */ /* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK 0x80u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT 7 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK 0x100u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT 8 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK 0x200u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT 9 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK 0x400u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT 10 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK 0x800u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT 11 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK 0x1000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT 12 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK 0x2000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT 13 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK 0x4000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT 14 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK 0x8000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT 15 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK 0x10000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT 16 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK 0x20000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT 17 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK 0x40000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT 18 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK 0x80000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT 19 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK 0x100000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT 20 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK 0x200000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT 21 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK 0x400000u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT 22 /* GPR1 Bit Fields */ #define IOMUXC_GPR_GPR1_ACT_CS0_MASK 0x1u #define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT 0 #define IOMUXC_GPR_GPR1_ADDRS0_MASK 0x6u #define IOMUXC_GPR_GPR1_ADDRS0_SHIFT 1 #define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<KPCR) #define KPP_KPSR_REG(base) ((base)->KPSR) #define KPP_KDDR_REG(base) ((base)->KDDR) #define KPP_KPDR_REG(base) ((base)->KPDR) /*! * @} */ /* end of group KPP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- KPP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup KPP_Register_Masks KPP Register Masks * @{ */ /* KPCR Bit Fields */ #define KPP_KPCR_KRE_MASK 0xFFu #define KPP_KPCR_KRE_SHIFT 0 #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) #define LCDIF_RL_SET_REG(base) ((base)->RL_SET) #define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) #define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) #define LCDIF_CTRL1_REG(base) ((base)->CTRL1) #define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) #define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) #define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) #define LCDIF_CTRL2_REG(base) ((base)->CTRL2) #define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) #define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) #define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) #define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) #define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) #define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) #define LCDIF_TIMING_REG(base) ((base)->TIMING) #define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) #define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) #define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) #define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) #define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) #define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) #define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) #define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) #define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) #define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) #define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) #define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) #define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) #define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) #define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) #define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) #define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) #define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) #define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) #define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) #define LCDIF_DATA_REG(base) ((base)->DATA) #define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) #define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) #define LCDIF_STAT_REG(base) ((base)->STAT) #define LCDIF_VERSION_REG(base) ((base)->VERSION) #define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) #define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) #define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) #define LCDIF_THRES_REG(base) ((base)->THRES) #define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) #define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) #define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) #define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) #define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) #define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) #define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) #define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) #define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) /*! * @} */ /* end of group LCDIF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Register_Masks LCDIF Register Masks * @{ */ /* RL Bit Fields */ #define LCDIF_RL_RUN_MASK 0x1u #define LCDIF_RL_RUN_SHIFT 0 #define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u #define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 #define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u #define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 #define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u #define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 #define LCDIF_RL_RSRVD0_MASK 0x10u #define LCDIF_RL_RSRVD0_SHIFT 4 #define LCDIF_RL_MASTER_MASK 0x20u #define LCDIF_RL_MASTER_SHIFT 5 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u #define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 #define LCDIF_RL_WORD_LENGTH_MASK 0x300u #define LCDIF_RL_WORD_LENGTH_SHIFT 8 #define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<CTRL) /*! * @} */ /* end of group LDB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LDB_Register_Masks LDB Register Masks * @{ */ /* CTRL Bit Fields */ #define LDB_CTRL_ch0_mode_MASK 0x3u #define LDB_CTRL_ch0_mode_SHIFT 0 #define LDB_CTRL_ch0_mode(x) (((uint32_t)(((uint32_t)(x))<PCCCR) #define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) #define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) #define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) #define LMEM_PSCCR_REG(base) ((base)->PSCCR) #define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) #define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) #define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) /*! * @} */ /* end of group LMEM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LMEM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Register_Masks LMEM Register Masks * @{ */ /* PCCCR Bit Fields */ #define LMEM_PCCCR_ENCACHE_MASK 0x1u #define LMEM_PCCCR_ENCACHE_SHIFT 0 #define LMEM_PCCCR_ENWRBUF_MASK 0x2u #define LMEM_PCCCR_ENWRBUF_SHIFT 1 #define LMEM_PCCCR_PCCR2_MASK 0x4u #define LMEM_PCCCR_PCCR2_SHIFT 2 #define LMEM_PCCCR_PCCR3_MASK 0x8u #define LMEM_PCCCR_PCCR3_SHIFT 3 #define LMEM_PCCCR_INVW0_MASK 0x1000000u #define LMEM_PCCCR_INVW0_SHIFT 24 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u #define LMEM_PCCCR_PUSHW0_SHIFT 25 #define LMEM_PCCCR_INVW1_MASK 0x4000000u #define LMEM_PCCCR_INVW1_SHIFT 26 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u #define LMEM_PCCCR_PUSHW1_SHIFT 27 #define LMEM_PCCCR_GO_MASK 0x80000000u #define LMEM_PCCCR_GO_SHIFT 31 /* PCCLCR Bit Fields */ #define LMEM_PCCLCR_LGO_MASK 0x1u #define LMEM_PCCLCR_LGO_SHIFT 0 #define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu #define LMEM_PCCLCR_CACHEADDR_SHIFT 2 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_FADR_REG(base) ((base)->FADR) #define MCM_FATR_REG(base) ((base)->FATR) #define MCM_FDR_REG(base) ((base)->FDR) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<MLBC0) #define MLB_MS0_REG(base) ((base)->MS0) #define MLB_MLBPC2_REG(base) ((base)->MLBPC2.MLBPC2) #define MLB_MS1_REG(base) ((base)->MS1) #define MLB_MSS_REG(base) ((base)->MSS) #define MLB_MSD_REG(base) ((base)->MSD) #define MLB_MIEN_REG(base) ((base)->MIEN) #define MLB_MLBC1_REG(base) ((base)->MLBC1) #define MLB_HCTL_REG(base) ((base)->HCTL) #define MLB_HCMR0_REG(base) ((base)->HCMR0) #define MLB_HCMR1_REG(base) ((base)->HCMR1) #define MLB_HCER0_REG(base) ((base)->HCER0) #define MLB_HCER1_REG(base) ((base)->HCER1) #define MLB_HCBR0_REG(base) ((base)->HCBR0) #define MLB_HCBR1_REG(base) ((base)->HCBR1) #define MLB_MDAT0_REG(base) ((base)->MDAT0) #define MLB_MDAT1_REG(base) ((base)->MDAT1) #define MLB_MDAT2_REG(base) ((base)->MDAT2) #define MLB_MDAT3_REG(base) ((base)->MDAT3) #define MLB_MDWE0_REG(base) ((base)->MDWE0) #define MLB_MDWE1_REG(base) ((base)->MDWE1) #define MLB_MDWE2_REG(base) ((base)->MDWE2) #define MLB_MDWE3_REG(base) ((base)->MDWE3) #define MLB_MCTL_REG(base) ((base)->MCTL) #define MLB_MADR_REG(base) ((base)->MADR) #define MLB_ACTL_REG(base) ((base)->ACTL) #define MLB_ACSR0_REG(base) ((base)->ACSR0) #define MLB_ACSR1_REG(base) ((base)->ACSR1) #define MLB_ACMR0_REG(base) ((base)->ACMR0) #define MLB_ACMR1_REG(base) ((base)->ACMR1) /*! * @} */ /* end of group MLB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MLB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MLB_Register_Masks MLB Register Masks * @{ */ /* MLBC0 Bit Fields */ #define MLB_MLBC0_MLBEN_MASK 0x1u #define MLB_MLBC0_MLBEN_SHIFT 0 #define MLB_MLBC0_MLBCLK_2_0_MASK 0x1Cu #define MLB_MLBC0_MLBCLK_2_0_SHIFT 2 #define MLB_MLBC0_MLBCLK_2_0(x) (((uint32_t)(((uint32_t)(x))<MDCTL) #define MMDC_MDPDC_REG(base) ((base)->MDPDC) #define MMDC_MDOTC_REG(base) ((base)->MDOTC) #define MMDC_MDCFG0_REG(base) ((base)->MDCFG0) #define MMDC_MDCFG1_REG(base) ((base)->MDCFG1) #define MMDC_MDCFG2_REG(base) ((base)->MDCFG2) #define MMDC_MDMISC_REG(base) ((base)->MDMISC) #define MMDC_MDSCR_REG(base) ((base)->MDSCR) #define MMDC_MDREF_REG(base) ((base)->MDREF) #define MMDC_MDRWD_REG(base) ((base)->MDRWD) #define MMDC_MDOR_REG(base) ((base)->MDOR) #define MMDC_MDMRR_REG(base) ((base)->MDMRR) #define MMDC_MDCFG3LP_REG(base) ((base)->MDCFG3LP) #define MMDC_MDMR4_REG(base) ((base)->MDMR4) #define MMDC_MDASP_REG(base) ((base)->MDASP) #define MMDC_MAARCR_REG(base) ((base)->MAARCR) #define MMDC_MAPSR_REG(base) ((base)->MAPSR) #define MMDC_MAEXIDR0_REG(base) ((base)->MAEXIDR0) #define MMDC_MAEXIDR1_REG(base) ((base)->MAEXIDR1) #define MMDC_MADPCR0_REG(base) ((base)->MADPCR0) #define MMDC_MADPCR1_REG(base) ((base)->MADPCR1) #define MMDC_MADPSR0_REG(base) ((base)->MADPSR0) #define MMDC_MADPSR1_REG(base) ((base)->MADPSR1) #define MMDC_MADPSR2_REG(base) ((base)->MADPSR2) #define MMDC_MADPSR3_REG(base) ((base)->MADPSR3) #define MMDC_MADPSR4_REG(base) ((base)->MADPSR4) #define MMDC_MADPSR5_REG(base) ((base)->MADPSR5) #define MMDC_MASBS0_REG(base) ((base)->MASBS0) #define MMDC_MASBS1_REG(base) ((base)->MASBS1) #define MMDC_MAGENP_REG(base) ((base)->MAGENP) #define MMDC_MPZQHWCTRL_REG(base) ((base)->MPZQHWCTRL) #define MMDC_MPZQSWCTRL_REG(base) ((base)->MPZQSWCTRL) #define MMDC_MPWLGCR_REG(base) ((base)->MPWLGCR) #define MMDC_MPWLDECTRL0_REG(base) ((base)->MPWLDECTRL0) #define MMDC_MPWLDECTRL1_REG(base) ((base)->MPWLDECTRL1) #define MMDC_MPWLDLST_REG(base) ((base)->MPWLDLST) #define MMDC_MPODTCTRL_REG(base) ((base)->MPODTCTRL) #define MMDC_MPRDDQBY0DL_REG(base) ((base)->MPRDDQBY0DL) #define MMDC_MPRDDQBY1DL_REG(base) ((base)->MPRDDQBY1DL) #define MMDC_MPRDDQBY2DL_REG(base) ((base)->MPRDDQBY2DL) #define MMDC_MPRDDQBY3DL_REG(base) ((base)->MPRDDQBY3DL) #define MMDC_MPWRDQBY0DL_REG(base) ((base)->MPWRDQBY0DL) #define MMDC_MPWRDQBY1DL_REG(base) ((base)->MPWRDQBY1DL) #define MMDC_MPWRDQBY2DL_REG(base) ((base)->MPWRDQBY2DL) #define MMDC_MPWRDQBY3DL_REG(base) ((base)->MPWRDQBY3DL) #define MMDC_MPDGCTRL0_REG(base) ((base)->MPDGCTRL0) #define MMDC_MPDGCTRL1_REG(base) ((base)->MPDGCTRL1) #define MMDC_MPDGDLST0_REG(base) ((base)->MPDGDLST0) #define MMDC_MPRDDLCTL_REG(base) ((base)->MPRDDLCTL) #define MMDC_MPRDDLST_REG(base) ((base)->MPRDDLST) #define MMDC_MPWRDLCTL_REG(base) ((base)->MPWRDLCTL) #define MMDC_MPWRDLST_REG(base) ((base)->MPWRDLST) #define MMDC_MPSDCTRL_REG(base) ((base)->MPSDCTRL) #define MMDC_MPZQLP2CTL_REG(base) ((base)->MPZQLP2CTL) #define MMDC_MPRDDLHWCTL_REG(base) ((base)->MPRDDLHWCTL) #define MMDC_MPWRDLHWCTL_REG(base) ((base)->MPWRDLHWCTL) #define MMDC_MPRDDLHWST0_REG(base) ((base)->MPRDDLHWST0) #define MMDC_MPRDDLHWST1_REG(base) ((base)->MPRDDLHWST1) #define MMDC_MPWRDLHWST0_REG(base) ((base)->MPWRDLHWST0) #define MMDC_MPWRDLHWST1_REG(base) ((base)->MPWRDLHWST1) #define MMDC_MPWLHWERR_REG(base) ((base)->MPWLHWERR) #define MMDC_MPDGHWST0_REG(base) ((base)->MPDGHWST0) #define MMDC_MPDGHWST1_REG(base) ((base)->MPDGHWST1) #define MMDC_MPDGHWST2_REG(base) ((base)->MPDGHWST2) #define MMDC_MPDGHWST3_REG(base) ((base)->MPDGHWST3) #define MMDC_MPPDCMPR1_REG(base) ((base)->MPPDCMPR1) #define MMDC_MPPDCMPR2_REG(base) ((base)->MPPDCMPR2) #define MMDC_MPSWDAR0_REG(base) ((base)->MPSWDAR0) #define MMDC_MPSWDRDR0_REG(base) ((base)->MPSWDRDR0) #define MMDC_MPSWDRDR1_REG(base) ((base)->MPSWDRDR1) #define MMDC_MPSWDRDR2_REG(base) ((base)->MPSWDRDR2) #define MMDC_MPSWDRDR3_REG(base) ((base)->MPSWDRDR3) #define MMDC_MPSWDRDR4_REG(base) ((base)->MPSWDRDR4) #define MMDC_MPSWDRDR5_REG(base) ((base)->MPSWDRDR5) #define MMDC_MPSWDRDR6_REG(base) ((base)->MPSWDRDR6) #define MMDC_MPSWDRDR7_REG(base) ((base)->MPSWDRDR7) #define MMDC_MPMUR0_REG(base) ((base)->MPMUR0) #define MMDC_MPWRCADL_REG(base) ((base)->MPWRCADL) #define MMDC_MPDCCR_REG(base) ((base)->MPDCCR) /*! * @} */ /* end of group MMDC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MMDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMDC_Register_Masks MMDC Register Masks * @{ */ /* MDCTL Bit Fields */ #define MMDC_MDCTL_DSIZ_MASK 0x30000u #define MMDC_MDCTL_DSIZ_SHIFT 16 #define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x))<TR[index]) #define MU_TR_COUNT 4 #define MU_RR_REG(base,index) ((base)->RR[index]) #define MU_RR_COUNT 4 #define MU_SR_REG(base) ((base)->SR) #define MU_CR_REG(base) ((base)->CR) /*! * @} */ /* end of group MU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /* TR Bit Fields */ #define MU_TR_TR0_MASK 0xFFFFFFFFu #define MU_TR_TR0_SHIFT 0 #define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) #define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define OCOTP_TIMING_REG(base) ((base)->TIMING) #define OCOTP_DATA_REG(base) ((base)->DATA) #define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) #define OCOTP_READ_FUSE_DATA_REG(base) ((base)->READ_FUSE_DATA) #define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) #define OCOTP_SCS_REG(base) ((base)->SCS) #define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) #define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) #define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) #define OCOTP_VERSION_REG(base) ((base)->VERSION) #define OCOTP_LOCK_REG(base) ((base)->LOCK) #define OCOTP_CFG0_REG(base) ((base)->CFG0) #define OCOTP_CFG1_REG(base) ((base)->CFG1) #define OCOTP_CFG2_REG(base) ((base)->CFG2) #define OCOTP_CFG3_REG(base) ((base)->CFG3) #define OCOTP_CFG4_REG(base) ((base)->CFG4) #define OCOTP_CFG5_REG(base) ((base)->CFG5) #define OCOTP_CFG6_REG(base) ((base)->CFG6) #define OCOTP_MEM0_REG(base) ((base)->MEM0) #define OCOTP_MEM1_REG(base) ((base)->MEM1) #define OCOTP_MEM2_REG(base) ((base)->MEM2) #define OCOTP_MEM3_REG(base) ((base)->MEM3) #define OCOTP_MEM4_REG(base) ((base)->MEM4) #define OCOTP_ANA0_REG(base) ((base)->ANA0) #define OCOTP_ANA1_REG(base) ((base)->ANA1) #define OCOTP_ANA2_REG(base) ((base)->ANA2) #define OCOTP_SRK0_REG(base) ((base)->SRK0) #define OCOTP_SRK1_REG(base) ((base)->SRK1) #define OCOTP_SRK2_REG(base) ((base)->SRK2) #define OCOTP_SRK3_REG(base) ((base)->SRK3) #define OCOTP_SRK4_REG(base) ((base)->SRK4) #define OCOTP_SRK5_REG(base) ((base)->SRK5) #define OCOTP_SRK6_REG(base) ((base)->SRK6) #define OCOTP_SRK7_REG(base) ((base)->SRK7) #define OCOTP_RESP0_REG(base) ((base)->RESP0) #define OCOTP_HSJC_RESP1_REG(base) ((base)->HSJC_RESP1) #define OCOTP_MAC0_REG(base) ((base)->MAC0) #define OCOTP_MAC1_REG(base) ((base)->MAC1) #define OCOTP_MAC2_REG(base) ((base)->MAC2) #define OCOTP_GP1_REG(base) ((base)->GP1) #define OCOTP_GP2_REG(base) ((base)->GP2) #define OCOTP_MISC_CONF_REG(base) ((base)->MISC_CONF) #define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) #define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) #define OCOTP_GP30_REG(base) ((base)->GP30) #define OCOTP_GP31_REG(base) ((base)->GP31) #define OCOTP_GP32_REG(base) ((base)->GP32) #define OCOTP_GP33_REG(base) ((base)->GP33) #define OCOTP_GP34_REG(base) ((base)->GP34) #define OCOTP_GP35_REG(base) ((base)->GP35) #define OCOTP_GP36_REG(base) ((base)->GP36) /*! * @} */ /* end of group OCOTP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- OCOTP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_Register_Masks OCOTP Register Masks * @{ */ /* CTRL Bit Fields */ #define OCOTP_CTRL_ADDR_MASK 0x7Fu #define OCOTP_CTRL_ADDR_SHIFT 0 #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<PCIE_PHY_CTRL) #define PGC_PCIE_PHY_PUPSCR_REG(base) ((base)->PCIE_PHY_PUPSCR) #define PGC_PCIE_PHY_PDNSCR_REG(base) ((base)->PCIE_PHY_PDNSCR) #define PGC_PCIE_PHY_SR_REG(base) ((base)->PCIE_PHY_SR) #define PGC_MEGA_CTRL_REG(base) ((base)->MEGA_CTRL) #define PGC_MEGA_PUPSCR_REG(base) ((base)->MEGA_PUPSCR) #define PGC_MEGA_PDNSCR_REG(base) ((base)->MEGA_PDNSCR) #define PGC_MEGA_SR_REG(base) ((base)->MEGA_SR) #define PGC_DISPLAY_CTRL_REG(base) ((base)->DISPLAY_CTRL) #define PGC_DISPLAY_PUPSCR_REG(base) ((base)->DISPLAY_PUPSCR) #define PGC_DISPLAY_PDNSCR_REG(base) ((base)->DISPLAY_PDNSCR) #define PGC_DISPLAY_SR_REG(base) ((base)->DISPLAY_SR) #define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) #define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) #define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) #define PGC_GPU_SR_REG(base) ((base)->GPU_SR) #define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) #define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) #define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) #define PGC_CPU_SR_REG(base) ((base)->CPU_SR) /*! * @} */ /* end of group PGC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PGC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PGC_Register_Masks PGC Register Masks * @{ */ /* PCIE_PHY_CTRL Bit Fields */ #define PGC_PCIE_PHY_CTRL_PCR_MASK 0x1u #define PGC_PCIE_PHY_CTRL_PCR_SHIFT 0 /* PCIE_PHY_PUPSCR Bit Fields */ #define PGC_PCIE_PHY_PUPSCR_SW_MASK 0x3Fu #define PGC_PCIE_PHY_PUPSCR_SW_SHIFT 0 #define PGC_PCIE_PHY_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<REG_1P1) #define PMU_REG_3P0_REG(base) ((base)->REG_3P0) #define PMU_REG_2P5_REG(base) ((base)->REG_2P5) #define PMU_REG_CORE_REG(base) ((base)->REG_CORE) #define PMU_MISC0_REG(base) ((base)->MISC0) #define PMU_MISC1_REG(base) ((base)->MISC1) #define PMU_MISC1_SET_REG(base) ((base)->MISC1_SET) #define PMU_MISC1_CLR_REG(base) ((base)->MISC1_CLR) #define PMU_MISC1_TOG_REG(base) ((base)->MISC1_TOG) #define PMU_MISC2_REG(base) ((base)->MISC2) #define PMU_MISC2_SET_REG(base) ((base)->MISC2_SET) #define PMU_MISC2_CLR_REG(base) ((base)->MISC2_CLR) #define PMU_MISC2_TOG_REG(base) ((base)->MISC2_TOG) #define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) #define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) #define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) /*! * @} */ /* end of group PMU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMU_Register_Masks PMU Register Masks * @{ */ /* REG_1P1 Bit Fields */ #define PMU_REG_1P1_ENABLE_LINREG_MASK 0x1u #define PMU_REG_1P1_ENABLE_LINREG_SHIFT 0 #define PMU_REG_1P1_ENABLE_BO_MASK 0x2u #define PMU_REG_1P1_ENABLE_BO_SHIFT 1 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK 0x4u #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT 2 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK 0x8u #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT 3 #define PMU_REG_1P1_BO_OFFSET_MASK 0x70u #define PMU_REG_1P1_BO_OFFSET_SHIFT 4 #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) #define PWM_PWMSR_REG(base) ((base)->PWMSR) #define PWM_PWMIR_REG(base) ((base)->PWMIR) #define PWM_PWMSAR_REG(base) ((base)->PWMSAR) #define PWM_PWMPR_REG(base) ((base)->PWMPR) #define PWM_PWMCNR_REG(base) ((base)->PWMCNR) /*! * @} */ /* end of group PWM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Register_Masks PWM Register Masks * @{ */ /* PWMCR Bit Fields */ #define PWM_PWMCR_EN_MASK 0x1u #define PWM_PWMCR_EN_SHIFT 0 #define PWM_PWMCR_REPEAT_MASK 0x6u #define PWM_PWMCR_REPEAT_SHIFT 1 #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define PXP_STAT_REG(base) ((base)->STAT) #define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) #define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) #define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) #define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) #define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) #define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) #define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) #define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) #define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) #define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) #define PXP_PS_BUF_REG(base) ((base)->PS_BUF) #define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) #define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) #define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) #define PXP_PS_BACKGROUND_REG(base) ((base)->PS_BACKGROUND) #define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) #define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) #define PXP_PS_CLRKEYLOW_REG(base) ((base)->PS_CLRKEYLOW) #define PXP_PS_CLRKEYHIGH_REG(base) ((base)->PS_CLRKEYHIGH) #define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) #define PXP_AS_BUF_REG(base) ((base)->AS_BUF) #define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) #define PXP_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) #define PXP_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) #define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) #define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) #define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) #define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) #define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) #define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) #define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) #define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) #define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) #define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) #define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) #define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) #define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) #define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) #define PXP_CFA_REG(base) ((base)->CFA) #define PXP_HIST_CTRL_REG(base) ((base)->HIST_CTRL) #define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) #define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) #define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) #define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) #define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) #define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) #define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) #define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) #define PXP_POWER_REG(base) ((base)->POWER) #define PXP_NEXT_REG(base) ((base)->NEXT) /*! * @} */ /* end of group PXP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PXP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PXP_Register_Masks PXP Register Masks * @{ */ /* CTRL Bit Fields */ #define PXP_CTRL_ENABLE_MASK 0x1u #define PXP_CTRL_ENABLE_SHIFT 0 #define PXP_CTRL_IRQ_ENABLE_MASK 0x2u #define PXP_CTRL_IRQ_ENABLE_SHIFT 1 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK 0x10u #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT 4 #define PXP_CTRL_RSVD0_MASK 0xE0u #define PXP_CTRL_RSVD0_SHIFT 5 #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) #define QuadSPI_IPCR_REG(base) ((base)->IPCR) #define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) #define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) #define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) #define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) #define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) #define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) #define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) #define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) #define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) #define QuadSPI_SFAR_REG(base) ((base)->SFAR) #define QuadSPI_SMPR_REG(base) ((base)->SMPR) #define QuadSPI_RBSR_REG(base) ((base)->RBSR) #define QuadSPI_RBCT_REG(base) ((base)->RBCT) #define QuadSPI_TBSR_REG(base) ((base)->TBSR) #define QuadSPI_TBDR_REG(base) ((base)->TBDR) #define QuadSPI_SR_REG(base) ((base)->SR) #define QuadSPI_FR_REG(base) ((base)->FR) #define QuadSPI_RSER_REG(base) ((base)->RSER) #define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) #define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) #define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) #define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) #define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) #define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) #define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) #define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) #define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) #define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) /*! * @} */ /* end of group QuadSPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- QuadSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks * @{ */ /* MCR Bit Fields */ #define QuadSPI_MCR_SWRSTSD_MASK 0x1u #define QuadSPI_MCR_SWRSTSD_SHIFT 0 #define QuadSPI_MCR_SWRSTHD_MASK 0x2u #define QuadSPI_MCR_SWRSTHD_SHIFT 1 #define QuadSPI_MCR_DQS_EN_MASK 0x40u #define QuadSPI_MCR_DQS_EN_SHIFT 6 #define QuadSPI_MCR_DDR_EN_MASK 0x80u #define QuadSPI_MCR_DDR_EN_SHIFT 7 #define QuadSPI_MCR_CLR_RXF_MASK 0x400u #define QuadSPI_MCR_CLR_RXF_SHIFT 10 #define QuadSPI_MCR_CLR_TXF_MASK 0x800u #define QuadSPI_MCR_CLR_TXF_SHIFT 11 #define QuadSPI_MCR_MDIS_MASK 0x4000u #define QuadSPI_MCR_MDIS_SHIFT 14 #define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u #define QuadSPI_MCR_SCLKCFG_SHIFT 24 #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<VIR) #define RDC_STAT_REG(base) ((base)->STAT) #define RDC_INTCTRL_REG(base) ((base)->INTCTRL) #define RDC_INTSTAT_REG(base) ((base)->INTSTAT) #define RDC_MDA_REG(base,index) ((base)->MDA[index]) #define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) #define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) #define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) #define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) #define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) /*! * @} */ /* end of group RDC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_Register_Masks RDC Register Masks * @{ */ /* VIR Bit Fields */ #define RDC_VIR_NDID_MASK 0xFu #define RDC_VIR_NDID_SHIFT 0 #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) #define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks * @{ */ /* GATE Bit Fields */ #define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 #define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) #define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) #define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) #define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) #define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) #define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) /*! * @} */ /* end of group ROMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ROMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMC_Register_Masks ROMC Register Masks * @{ */ /* ROMPATCHD Bit Fields */ #define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu #define ROMC_ROMPATCHD_DATAX_SHIFT 0 #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) #define SDMAARM_INTR_REG(base) ((base)->INTR) #define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) #define SDMAARM_HSTART_REG(base) ((base)->HSTART) #define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) #define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) #define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) #define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) #define SDMAARM_RESET_REG(base) ((base)->RESET) #define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) #define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) #define SDMAARM_PSW_REG(base) ((base)->PSW) #define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) #define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) #define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) #define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) #define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) #define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) #define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) #define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) #define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) #define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) #define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) #define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) #define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) #define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) #define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) #define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) /*! * @} */ /* end of group SDMAARM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMAARM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks * @{ */ /* MC0PTR Bit Fields */ #define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu #define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 #define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<DC0PTR) #define SDMABP_INTR_REG(base) ((base)->INTR) #define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) #define SDMABP_DSTART_REG(base) ((base)->DSTART) #define SDMABP_EVTERR_REG(base) ((base)->EVTERR) #define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) #define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) /*! * @} */ /* end of group SDMABP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMABP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMABP_Register_Masks SDMABP Register Masks * @{ */ /* DC0PTR Bit Fields */ #define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu #define SDMABP_DC0PTR_DC0PTR_SHIFT 0 #define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) #define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) #define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) #define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) #define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) #define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) #define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) #define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) #define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) #define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) #define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) #define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) #define SDMACORE_ED_REG(base) ((base)->ED.ED) #define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) #define SDMACORE_RTB_REG(base) ((base)->RTB) #define SDMACORE_TB_REG(base) ((base)->TB.TB) #define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) #define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) #define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) #define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) #define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) /*! * @} */ /* end of group SDMACORE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMACORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks * @{ */ /* MC0PTR Bit Fields */ #define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu #define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 #define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<GATE00) #define SEMA4_GATE01_REG(base) ((base)->GATE01) #define SEMA4_GATE02_REG(base) ((base)->GATE02) #define SEMA4_GATE03_REG(base) ((base)->GATE03) #define SEMA4_GATE04_REG(base) ((base)->GATE04) #define SEMA4_GATE05_REG(base) ((base)->GATE05) #define SEMA4_GATE06_REG(base) ((base)->GATE06) #define SEMA4_GATE07_REG(base) ((base)->GATE07) #define SEMA4_GATE08_REG(base) ((base)->GATE08) #define SEMA4_GATE09_REG(base) ((base)->GATE09) #define SEMA4_GATE10_REG(base) ((base)->GATE10) #define SEMA4_GATE11_REG(base) ((base)->GATE11) #define SEMA4_GATE12_REG(base) ((base)->GATE12) #define SEMA4_GATE13_REG(base) ((base)->GATE13) #define SEMA4_GATE14_REG(base) ((base)->GATE14) #define SEMA4_GATE15_REG(base) ((base)->GATE15) #define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) #define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) #define SEMA4_RSTGT_REG(base) ((base)->RSTGT) #define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) /*! * @} */ /* end of group SEMA4_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SEMA4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks * @{ */ /* GATE00 Bit Fields */ #define SEMA4_GATE00_GTFSM_MASK 0x3u #define SEMA4_GATE00_GTFSM_SHIFT 0 #define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<GPUSR1) #define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) #define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) #define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) #define SJC_DCR_REG(base) ((base)->DCR.DCR) #define SJC_SSR_REG(base) ((base)->SSR.SSR) #define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) /*! * @} */ /* end of group SJC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SJC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SJC_Register_Masks SJC Register Masks * @{ */ /* GPUSR1 Bit Fields */ #define SJC_GPUSR1_A_DBG_MASK 0x1u #define SJC_GPUSR1_A_DBG_SHIFT 0 #define SJC_GPUSR1_A_WFI_MASK 0x2u #define SJC_GPUSR1_A_WFI_SHIFT 1 #define SJC_GPUSR1_S_STAT_MASK 0x1Cu #define SJC_GPUSR1_S_STAT_SHIFT 2 #define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<HPLR) #define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) #define SNVS_HPCR_REG(base) ((base)->HPCR) #define SNVS_HPSR_REG(base) ((base)->HPSR) #define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) #define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) #define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) #define SNVS_HPTALR_REG(base) ((base)->HPTALR) #define SNVS_LPLR_REG(base) ((base)->LPLR) #define SNVS_LPCR_REG(base) ((base)->LPCR) #define SNVS_LPSR_REG(base) ((base)->LPSR) #define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) #define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) #define SNVS_LPGPR_REG(base) ((base)->LPGPR) #define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) #define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) /*! * @} */ /* end of group SNVS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SNVS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Register_Masks SNVS Register Masks * @{ */ /* HPLR Bit Fields */ #define SNVS_HPLR_MC_SL_MASK 0x10u #define SNVS_HPLR_MC_SL_SHIFT 4 #define SNVS_HPLR_GPR_SL_MASK 0x20u #define SNVS_HPLR_GPR_SL_SHIFT 5 /* HPCOMR Bit Fields */ #define SNVS_HPCOMR_LP_SWR_MASK 0x10u #define SNVS_HPCOMR_LP_SWR_SHIFT 4 #define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 #define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u #define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 /* HPCR Bit Fields */ #define SNVS_HPCR_RTC_EN_MASK 0x1u #define SNVS_HPCR_RTC_EN_SHIFT 0 #define SNVS_HPCR_HPTA_EN_MASK 0x2u #define SNVS_HPCR_HPTA_EN_SHIFT 1 #define SNVS_HPCR_PI_EN_MASK 0x8u #define SNVS_HPCR_PI_EN_SHIFT 3 #define SNVS_HPCR_PI_FREQ_MASK 0xF0u #define SNVS_HPCR_PI_FREQ_SHIFT 4 #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) /*! * @} */ /* end of group SPBA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPBA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPBA_Register_Masks SPBA Register Masks * @{ */ /* PRR Bit Fields */ #define SPBA_PRR_RARA_MASK 0x1u #define SPBA_PRR_RARA_SHIFT 0 #define SPBA_PRR_RARB_MASK 0x2u #define SPBA_PRR_RARB_SHIFT 1 #define SPBA_PRR_RARC_MASK 0x4u #define SPBA_PRR_RARC_SHIFT 2 #define SPBA_PRR_ROI_MASK 0x30000u #define SPBA_PRR_ROI_SHIFT 16 #define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) #define SPDIF_SRCD_REG(base) ((base)->SRCD) #define SPDIF_SRPC_REG(base) ((base)->SRPC) #define SPDIF_SIE_REG(base) ((base)->SIE) #define SPDIF_SIS_REG(base) ((base)->SIS) #define SPDIF_SIC_REG(base) ((base)->SIC) #define SPDIF_SRL_REG(base) ((base)->SRL.SRL) #define SPDIF_SRR_REG(base) ((base)->SRR.SRR) #define SPDIF_SRCSH_REG(base) ((base)->SRCSH.SRCSH) #define SPDIF_SRCSL_REG(base) ((base)->SRCSL.SRCSL) #define SPDIF_SRU_REG(base) ((base)->SRU.SRU) #define SPDIF_SRQ_REG(base) ((base)->SRQ.SRQ) #define SPDIF_STL_REG(base) ((base)->STL.STL) #define SPDIF_STR_REG(base) ((base)->STR.STR) #define SPDIF_STCSCH_REG(base) ((base)->STCSCH.STCSCH) #define SPDIF_STCSCL_REG(base) ((base)->STCSCL.STCSCL) #define SPDIF_SRFM_REG(base) ((base)->SRFM) #define SPDIF_STC_REG(base) ((base)->STC) /*! * @} */ /* end of group SPDIF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPDIF_Register_Masks SPDIF Register Masks * @{ */ /* SCR Bit Fields */ #define SPDIF_SCR_USrc_Sel_MASK 0x3u #define SPDIF_SCR_USrc_Sel_SHIFT 0 #define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x))<SCR) #define SRC_SBMR1_REG(base) ((base)->SBMR1) #define SRC_SRSR_REG(base) ((base)->SRSR) #define SRC_SISR_REG(base) ((base)->SISR) #define SRC_SIMR_REG(base) ((base)->SIMR) #define SRC_SBMR2_REG(base) ((base)->SBMR2) #define SRC_GPR1_REG(base) ((base)->GPR1) #define SRC_GPR2_REG(base) ((base)->GPR2) #define SRC_GPR3_REG(base) ((base)->GPR3) #define SRC_GPR4_REG(base) ((base)->GPR4) #define SRC_GPR5_REG(base) ((base)->GPR5) #define SRC_GPR6_REG(base) ((base)->GPR6) #define SRC_GPR7_REG(base) ((base)->GPR7) #define SRC_GPR8_REG(base) ((base)->GPR8) #define SRC_GPR9_REG(base) ((base)->GPR9) #define SRC_GPR10_REG(base) ((base)->GPR10) /*! * @} */ /* end of group SRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_Register_Masks SRC Register Masks * @{ */ /* SCR Bit Fields */ #define SRC_SCR_warm_reset_enable_MASK 0x1u #define SRC_SCR_warm_reset_enable_SHIFT 0 #define SRC_SCR_sw_gpu_rst_MASK 0x2u #define SRC_SCR_sw_gpu_rst_SHIFT 1 #define SRC_SCR_m4c_rst_MASK 0x8u #define SRC_SCR_m4c_rst_SHIFT 3 #define SRC_SCR_m4c_non_sclr_rst_MASK 0x10u #define SRC_SCR_m4c_non_sclr_rst_SHIFT 4 #define SRC_SCR_warm_rst_bypass_count_MASK 0x60u #define SRC_SCR_warm_rst_bypass_count_SHIFT 5 #define SRC_SCR_warm_rst_bypass_count(x) (((uint32_t)(((uint32_t)(x))<STX[index]) #define SSI_SRX_REG(base,index) ((base)->SRX[index]) #define SSI_SCR_REG(base) ((base)->SCR) #define SSI_SISR_REG(base) ((base)->SISR) #define SSI_SIER_REG(base) ((base)->SIER) #define SSI_STCR_REG(base) ((base)->STCR) #define SSI_SRCR_REG(base) ((base)->SRCR) #define SSI_STCCR_REG(base) ((base)->STCCR) #define SSI_SRCCR_REG(base) ((base)->SRCCR) #define SSI_SFCSR_REG(base) ((base)->SFCSR) #define SSI_SACNT_REG(base) ((base)->SACNT) #define SSI_SACADD_REG(base) ((base)->SACADD) #define SSI_SACDAT_REG(base) ((base)->SACDAT) #define SSI_SATAG_REG(base) ((base)->SATAG) #define SSI_STMSK_REG(base) ((base)->STMSK) #define SSI_SRMSK_REG(base) ((base)->SRMSK) #define SSI_SACCST_REG(base) ((base)->SACCST) #define SSI_SACCEN_REG(base) ((base)->SACCEN) #define SSI_SACCDIS_REG(base) ((base)->SACCDIS) /*! * @} */ /* end of group SSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SSI_Register_Masks SSI Register Masks * @{ */ /* STX Bit Fields */ #define SSI_STX_STXn_MASK 0xFFFFFFFFu #define SSI_STX_STXn_SHIFT 0 #define SSI_STX_STXn(x) (((uint32_t)(((uint32_t)(x))<TEMPSENSE0) #define TEMPMON_TEMPSENSE0_SET_REG(base) ((base)->TEMPSENSE0_SET) #define TEMPMON_TEMPSENSE0_CLR_REG(base) ((base)->TEMPSENSE0_CLR) #define TEMPMON_TEMPSENSE0_TOG_REG(base) ((base)->TEMPSENSE0_TOG) #define TEMPMON_TEMPSENSE1_REG(base) ((base)->TEMPSENSE1) #define TEMPMON_TEMPSENSE1_SET_REG(base) ((base)->TEMPSENSE1_SET) #define TEMPMON_TEMPSENSE1_CLR_REG(base) ((base)->TEMPSENSE1_CLR) #define TEMPMON_TEMPSENSE1_TOG_REG(base) ((base)->TEMPSENSE1_TOG) #define TEMPMON_TEMPSENSE2_REG(base) ((base)->TEMPSENSE2) #define TEMPMON_TEMPSENSE2_SET_REG(base) ((base)->TEMPSENSE2_SET) #define TEMPMON_TEMPSENSE2_CLR_REG(base) ((base)->TEMPSENSE2_CLR) #define TEMPMON_TEMPSENSE2_TOG_REG(base) ((base)->TEMPSENSE2_TOG) /*! * @} */ /* end of group TEMPMON_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- TEMPMON Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks * @{ */ /* TEMPSENSE0 Bit Fields */ #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK 0x1u #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT 0 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK 0x2u #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT 1 #define TEMPMON_TEMPSENSE0_FINISHED_MASK 0x4u #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT 2 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK 0xFFF00u #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<URXD) #define UART_UTXD_REG(base) ((base)->UTXD) #define UART_UCR1_REG(base) ((base)->UCR1) #define UART_UCR2_REG(base) ((base)->UCR2) #define UART_UCR3_REG(base) ((base)->UCR3) #define UART_UCR4_REG(base) ((base)->UCR4) #define UART_UFCR_REG(base) ((base)->UFCR) #define UART_USR1_REG(base) ((base)->USR1) #define UART_USR2_REG(base) ((base)->USR2) #define UART_UESC_REG(base) ((base)->UESC) #define UART_UTIM_REG(base) ((base)->UTIM) #define UART_UBIR_REG(base) ((base)->UBIR) #define UART_UBMR_REG(base) ((base)->UBMR) #define UART_UBRC_REG(base) ((base)->UBRC) #define UART_ONEMS_REG(base) ((base)->ONEMS) #define UART_UTS_REG(base) ((base)->UTS) #define UART_UMCR_REG(base) ((base)->UMCR) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /* URXD Bit Fields */ #define UART_URXD_RX_DATA_MASK 0xFFu #define UART_URXD_RX_DATA_SHIFT 0 #define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<UOG1_ID) #define USBC_UOG1_HWGENERAL_REG(base) ((base)->UOG1_HWGENERAL) #define USBC_UOG1_HWHOST_REG(base) ((base)->UOG1_HWHOST) #define USBC_UOG1_HWDEVICE_REG(base) ((base)->UOG1_HWDEVICE) #define USBC_UOG1_HWTXBUF_REG(base) ((base)->UOG1_HWTXBUF) #define USBC_UOG1_HWRXBUF_REG(base) ((base)->UOG1_HWRXBUF) #define USBC_UOG1_GPTIMER0LD_REG(base) ((base)->UOG1_GPTIMER0LD) #define USBC_UOG1_GPTIMER0CTRL_REG(base) ((base)->UOG1_GPTIMER0CTRL) #define USBC_UOG1_GPTIMER1LD_REG(base) ((base)->UOG1_GPTIMER1LD) #define USBC_UOG1_GPTIMER1CTRL_REG(base) ((base)->UOG1_GPTIMER1CTRL) #define USBC_UOG1_SBUSCFG_REG(base) ((base)->UOG1_SBUSCFG) #define USBC_UOG1_CAPLENGTH_REG(base) ((base)->UOG1_CAPLENGTH) #define USBC_UOG1_HCIVERSION_REG(base) ((base)->UOG1_HCIVERSION) #define USBC_UOG1_HCSPARAMS_REG(base) ((base)->UOG1_HCSPARAMS) #define USBC_UOG1_HCCPARAMS_REG(base) ((base)->UOG1_HCCPARAMS) #define USBC_UOG1_DCIVERSION_REG(base) ((base)->UOG1_DCIVERSION) #define USBC_UOG1_DCCPARAMS_REG(base) ((base)->UOG1_DCCPARAMS) #define USBC_UOG1_USBCMD_REG(base) ((base)->UOG1_USBCMD) #define USBC_UOG1_USBSTS_REG(base) ((base)->UOG1_USBSTS) #define USBC_UOG1_USBINTR_REG(base) ((base)->UOG1_USBINTR) #define USBC_UOG1_FRINDEX_REG(base) ((base)->UOG1_FRINDEX) #define USBC_UOG1_PERIODICLISTBASE_REG(base) ((base)->UOG1_PERIODICLISTBASE) #define USBC_UOG1_DEVICEADDR_REG(base) ((base)->UOG1_DEVICEADDR) #define USBC_UOG1_ASYNCLISTADDR_REG(base) ((base)->UOG1_ASYNCLISTADDR.UOG1_ASYNCLISTADDR) #define USBC_UOG1_ENDPTLISTADDR_REG(base) ((base)->UOG1_ENDPTLISTADDR.UOG1_ENDPTLISTADDR) #define USBC_UOG1_BURSTSIZE_REG(base) ((base)->UOG1_BURSTSIZE) #define USBC_UOG1_TXFILLTUNING_REG(base) ((base)->UOG1_TXFILLTUNING) #define USBC_UOG1_ENDPTNAK_REG(base) ((base)->UOG1_ENDPTNAK) #define USBC_UOG1_ENDPTNAKEN_REG(base) ((base)->UOG1_ENDPTNAKEN) #define USBC_UOG1_CONFIGFLAG_REG(base) ((base)->UOG1_CONFIGFLAG) #define USBC_UOG1_PORTSC1_REG(base) ((base)->UOG1_PORTSC1) #define USBC_UOG1_OTGSC_REG(base) ((base)->UOG1_OTGSC) #define USBC_UOG1_USBMODE_REG(base) ((base)->UOG1_USBMODE) #define USBC_UOG1_ENDPTSETUPSTAT_REG(base) ((base)->UOG1_ENDPTSETUPSTAT) #define USBC_UOG1_ENDPTPRIME_REG(base) ((base)->UOG1_ENDPTPRIME) #define USBC_UOG1_ENDPTFLUSH_REG(base) ((base)->UOG1_ENDPTFLUSH) #define USBC_UOG1_ENDPTSTAT_REG(base) ((base)->UOG1_ENDPTSTAT) #define USBC_UOG1_ENDPTCOMPLETE_REG(base) ((base)->UOG1_ENDPTCOMPLETE) #define USBC_UOG1_ENDPTCTRL0_REG(base) ((base)->UOG1_ENDPTCTRL0) #define USBC_UOG1_ENDPTCTRL1_REG(base) ((base)->UOG1_ENDPTCTRL1) #define USBC_UOG1_ENDPTCTRL2_REG(base) ((base)->UOG1_ENDPTCTRL2) #define USBC_UOG1_ENDPTCTRL3_REG(base) ((base)->UOG1_ENDPTCTRL3) #define USBC_UOG1_ENDPTCTRL4_REG(base) ((base)->UOG1_ENDPTCTRL4) #define USBC_UOG1_ENDPTCTRL5_REG(base) ((base)->UOG1_ENDPTCTRL5) #define USBC_UOG1_ENDPTCTRL6_REG(base) ((base)->UOG1_ENDPTCTRL6) #define USBC_UOG1_ENDPTCTRL7_REG(base) ((base)->UOG1_ENDPTCTRL7) #define USBC_UOG2_ID_REG(base) ((base)->UOG2_ID) #define USBC_UOG2_HWGENERAL_REG(base) ((base)->UOG2_HWGENERAL) #define USBC_UOG2_HWHOST_REG(base) ((base)->UOG2_HWHOST) #define USBC_UOG2_HWDEVICE_REG(base) ((base)->UOG2_HWDEVICE) #define USBC_UOG2_HWTXBUF_REG(base) ((base)->UOG2_HWTXBUF) #define USBC_UOG2_HWRXBUF_REG(base) ((base)->UOG2_HWRXBUF) #define USBC_UOG2_GPTIMER0LD_REG(base) ((base)->UOG2_GPTIMER0LD) #define USBC_UOG2_GPTIMER0CTRL_REG(base) ((base)->UOG2_GPTIMER0CTRL) #define USBC_UOG2_GPTIMER1LD_REG(base) ((base)->UOG2_GPTIMER1LD) #define USBC_UOG2_GPTIMER1CTRL_REG(base) ((base)->UOG2_GPTIMER1CTRL) #define USBC_UOG2_SBUSCFG_REG(base) ((base)->UOG2_SBUSCFG) #define USBC_UOG2_CAPLENGTH_REG(base) ((base)->UOG2_CAPLENGTH) #define USBC_UOG2_HCIVERSION_REG(base) ((base)->UOG2_HCIVERSION) #define USBC_UOG2_HCSPARAMS_REG(base) ((base)->UOG2_HCSPARAMS) #define USBC_UOG2_HCCPARAMS_REG(base) ((base)->UOG2_HCCPARAMS) #define USBC_UOG2_DCIVERSION_REG(base) ((base)->UOG2_DCIVERSION) #define USBC_UOG2_DCCPARAMS_REG(base) ((base)->UOG2_DCCPARAMS) #define USBC_UOG2_USBCMD_REG(base) ((base)->UOG2_USBCMD) #define USBC_UOG2_USBSTS_REG(base) ((base)->UOG2_USBSTS) #define USBC_UOG2_USBINTR_REG(base) ((base)->UOG2_USBINTR) #define USBC_UOG2_FRINDEX_REG(base) ((base)->UOG2_FRINDEX) #define USBC_UOG2_PERIODICLISTBASE_REG(base) ((base)->UOG2_PERIODICLISTBASE) #define USBC_UOG2_DEVICEADDR_REG(base) ((base)->UOG2_DEVICEADDR) #define USBC_UOG2_ASYNCLISTADDR_REG(base) ((base)->UOG2_ASYNCLISTADDR.UOG2_ASYNCLISTADDR) #define USBC_UOG2_ENDPTLISTADDR_REG(base) ((base)->UOG2_ENDPTLISTADDR.UOG2_ENDPTLISTADDR) #define USBC_UOG2_BURSTSIZE_REG(base) ((base)->UOG2_BURSTSIZE) #define USBC_UOG2_TXFILLTUNING_REG(base) ((base)->UOG2_TXFILLTUNING) #define USBC_UOG2_ENDPTNAK_REG(base) ((base)->UOG2_ENDPTNAK) #define USBC_UOG2_ENDPTNAKEN_REG(base) ((base)->UOG2_ENDPTNAKEN) #define USBC_UOG2_CONFIGFLAG_REG(base) ((base)->UOG2_CONFIGFLAG) #define USBC_UOG2_PORTSC1_REG(base) ((base)->UOG2_PORTSC1) #define USBC_UOG2_OTGSC_REG(base) ((base)->UOG2_OTGSC) #define USBC_UOG2_USBMODE_REG(base) ((base)->UOG2_USBMODE) #define USBC_UOG2_ENDPTSETUPSTAT_REG(base) ((base)->UOG2_ENDPTSETUPSTAT) #define USBC_UOG2_ENDPTPRIME_REG(base) ((base)->UOG2_ENDPTPRIME) #define USBC_UOG2_ENDPTFLUSH_REG(base) ((base)->UOG2_ENDPTFLUSH) #define USBC_UOG2_ENDPTSTAT_REG(base) ((base)->UOG2_ENDPTSTAT) #define USBC_UOG2_ENDPTCOMPLETE_REG(base) ((base)->UOG2_ENDPTCOMPLETE) #define USBC_UOG2_ENDPTCTRL0_REG(base) ((base)->UOG2_ENDPTCTRL0) #define USBC_UOG2_ENDPTCTRL1_REG(base) ((base)->UOG2_ENDPTCTRL1) #define USBC_UOG2_ENDPTCTRL2_REG(base) ((base)->UOG2_ENDPTCTRL2) #define USBC_UOG2_ENDPTCTRL3_REG(base) ((base)->UOG2_ENDPTCTRL3) #define USBC_UOG2_ENDPTCTRL4_REG(base) ((base)->UOG2_ENDPTCTRL4) #define USBC_UOG2_ENDPTCTRL5_REG(base) ((base)->UOG2_ENDPTCTRL5) #define USBC_UOG2_ENDPTCTRL6_REG(base) ((base)->UOG2_ENDPTCTRL6) #define USBC_UOG2_ENDPTCTRL7_REG(base) ((base)->UOG2_ENDPTCTRL7) #define USBC_UH1_ID_REG(base) ((base)->UH1_ID) #define USBC_UH1_HWGENERAL_REG(base) ((base)->UH1_HWGENERAL) #define USBC_UH1_HWHOST_REG(base) ((base)->UH1_HWHOST) #define USBC_UH1_HWTXBUF_REG(base) ((base)->UH1_HWTXBUF) #define USBC_UH1_HWRXBUF_REG(base) ((base)->UH1_HWRXBUF) #define USBC_UH1_GPTIMER0LD_REG(base) ((base)->UH1_GPTIMER0LD) #define USBC_UH1_GPTIMER0CTRL_REG(base) ((base)->UH1_GPTIMER0CTRL) #define USBC_UH1_GPTIMER1LD_REG(base) ((base)->UH1_GPTIMER1LD) #define USBC_UH1_GPTIMER1CTRL_REG(base) ((base)->UH1_GPTIMER1CTRL) #define USBC_UH1_SBUSCFG_REG(base) ((base)->UH1_SBUSCFG) #define USBC_UH1_CAPLENGTH_REG(base) ((base)->UH1_CAPLENGTH) #define USBC_UH1_HCIVERSION_REG(base) ((base)->UH1_HCIVERSION) #define USBC_UH1_HCSPARAMS_REG(base) ((base)->UH1_HCSPARAMS) #define USBC_UH1_HCCPARAMS_REG(base) ((base)->UH1_HCCPARAMS) #define USBC_UH1_USBCMD_REG(base) ((base)->UH1_USBCMD) #define USBC_UH1_USBSTS_REG(base) ((base)->UH1_USBSTS) #define USBC_UH1_USBINTR_REG(base) ((base)->UH1_USBINTR) #define USBC_UH1_FRINDEX_REG(base) ((base)->UH1_FRINDEX) #define USBC_UH1_PERIODICLISTBASE_REG(base) ((base)->UH1_PERIODICLISTBASE) #define USBC_UH1_ASYNCLISTADDR_REG(base) ((base)->UH1_ASYNCLISTADDR) #define USBC_UH1_BURSTSIZE_REG(base) ((base)->UH1_BURSTSIZE) #define USBC_UH1_TXFILLTUNING_REG(base) ((base)->UH1_TXFILLTUNING) #define USBC_UH1_CONFIGFLAG_REG(base) ((base)->UH1_CONFIGFLAG) #define USBC_UH1_PORTSC1_REG(base) ((base)->UH1_PORTSC1) #define USBC_UH1_USBMODE_REG(base) ((base)->UH1_USBMODE) /*! * @} */ /* end of group USBC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBC_Register_Masks USBC Register Masks * @{ */ /* UOG1_ID Bit Fields */ #define USBC_UOG1_ID_ID_MASK 0x3Fu #define USBC_UOG1_ID_ID_SHIFT 0 #define USBC_UOG1_ID_ID(x) (((uint32_t)(((uint32_t)(x))<USB_x_PHY_STS) #define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) #define USBNC_USB_OTG1_CTRL_REG(base) ((base)->USB_OTG1_CTRL) #define USBNC_USB_OTG2_CTRL_REG(base) ((base)->USB_OTG2_CTRL) #define USBNC_USB_UH_CTRL_REG(base) ((base)->USB_UH_CTRL) #define USBNC_USB_UH_HSIC_CTRL_REG(base) ((base)->USB_UH_HSIC_CTRL) #define USBNC_USB_OTG1_PHY_CTRL_0_REG(base) ((base)->USB_OTG1_PHY_CTRL_0) #define USBNC_USB_OTG2_PHY_CTRL_0_REG(base) ((base)->USB_OTG2_PHY_CTRL_0) /*! * @} */ /* end of group USBNC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /* USB_x_PHY_STS Bit Fields */ #define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u #define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 #define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<PWD) #define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) #define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) #define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) #define USBPHY_TX_REG(base) ((base)->TX) #define USBPHY_TX_SET_REG(base) ((base)->TX_SET) #define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) #define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) #define USBPHY_RX_REG(base) ((base)->RX) #define USBPHY_RX_SET_REG(base) ((base)->RX_SET) #define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) #define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) #define USBPHY_CTRL_REG(base) ((base)->CTRL) #define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) #define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define USBPHY_STATUS_REG(base) ((base)->STATUS) #define USBPHY_DEBUG_REG(base) ((base)->DEBUG) #define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) #define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) #define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) #define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) #define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) #define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) #define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) #define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) #define USBPHY_VERSION_REG(base) ((base)->VERSION) /*! * @} */ /* end of group USBPHY_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Register_Masks USBPHY Register Masks * @{ */ /* PWD Bit Fields */ #define USBPHY_PWD_RSVD0_MASK 0x3FFu #define USBPHY_PWD_RSVD0_SHIFT 0 #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<USB1_VBUS_DETECT) #define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) #define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) #define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) #define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) #define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) #define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) #define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) #define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) #define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) #define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) #define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) #define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) #define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) #define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) #define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) #define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) #define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) #define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) #define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) #define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) #define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) #define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) #define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) #define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) #define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) #define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) #define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) #define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) /*! * @} */ /* end of group USB_ANALOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB_ANALOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks * @{ */ /* USB1_VBUS_DETECT Bit Fields */ #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<CFC1) #define VDEC_BRSTGT_REG(base) ((base)->BRSTGT) #define VDEC_HZPOS_REG(base) ((base)->HZPOS) #define VDEC_VRTPOS_REG(base) ((base)->VRTPOS) #define VDEC_HVSHFT_REG(base) ((base)->HVSHFT) #define VDEC_HSIGS_REG(base) ((base)->HSIGS) #define VDEC_HSIGE_REG(base) ((base)->HSIGE) #define VDEC_VSCON1_REG(base) ((base)->VSCON1) #define VDEC_VSCON2_REG(base) ((base)->VSCON2) #define VDEC_YCDEL_REG(base) ((base)->YCDEL) #define VDEC_AFTCLP_REG(base) ((base)->AFTCLP) #define VDEC_DCOFF_REG(base) ((base)->DCOFF) #define VDEC_CSID_REG(base) ((base)->CSID) #define VDEC_CBGN_REG(base) ((base)->CBGN) #define VDEC_CRGN_REG(base) ((base)->CRGN) #define VDEC_CNTR_REG(base) ((base)->CNTR) #define VDEC_BRT_REG(base) ((base)->BRT) #define VDEC_HUE_REG(base) ((base)->HUE) #define VDEC_CHBTH_REG(base) ((base)->CHBTH) #define VDEC_SHPIMP_REG(base) ((base)->SHPIMP) #define VDEC_CHPLLIM_REG(base) ((base)->CHPLLIM) #define VDEC_VIDMOD_REG(base) ((base)->VIDMOD) #define VDEC_VIDSTS_REG(base) ((base)->VIDSTS) #define VDEC_NOISE_REG(base) ((base)->NOISE) #define VDEC_STDDBG_REG(base) ((base)->STDDBG) #define VDEC_MANOVR_REG(base) ((base)->MANOVR) #define VDEC_VSSGTH_REG(base) ((base)->VSSGTH) #define VDEC_DBGFBH_REG(base) ((base)->DBGFBH) #define VDEC_DBGFBL_REG(base) ((base)->DBGFBL) #define VDEC_HACTS_REG(base) ((base)->HACTS) #define VDEC_HACTE_REG(base) ((base)->HACTE) #define VDEC_VACTS_REG(base) ((base)->VACTS) #define VDEC_VACTE_REG(base) ((base)->VACTE) #define VDEC_HSTIP_REG(base) ((base)->HSTIP) #define VDEC_BLSCRCR_REG(base) ((base)->BLSCRCR) #define VDEC_BLSCRCB_REG(base) ((base)->BLSCRCB) #define VDEC_LMAGC2_REG(base) ((base)->LMAGC2) #define VDEC_CHAGC2_REG(base) ((base)->CHAGC2) #define VDEC_MINTH_REG(base) ((base)->MINTH) #define VDEC_VFRQOH_REG(base) ((base)->VFRQOH) #define VDEC_VFRQOL_REG(base) ((base)->VFRQOL) #define VDEC_ASYNCLKFREQ1_REG(base) ((base)->ASYNCLKFREQ1) #define VDEC_ASYNCLKFREQ2_REG(base) ((base)->ASYNCLKFREQ2) #define VDEC_ASYNCLKFREQ3_REG(base) ((base)->ASYNCLKFREQ3) #define VDEC_ASYNCLKFREQ4_REG(base) ((base)->ASYNCLKFREQ4) /*! * @} */ /* end of group VDEC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- VDEC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VDEC_Register_Masks VDEC Register Masks * @{ */ /* CFC1 Bit Fields */ #define VDEC_CFC1_rc_combmode_override_MASK 0xFu #define VDEC_CFC1_rc_combmode_override_SHIFT 0 #define VDEC_CFC1_rc_combmode_override(x) (((uint32_t)(((uint32_t)(x))<WCR) #define WDOG_WSR_REG(base) ((base)->WSR) #define WDOG_WRSR_REG(base) ((base)->WRSR) #define WDOG_WICR_REG(base) ((base)->WICR) #define WDOG_WMCR_REG(base) ((base)->WMCR) /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /* WCR Bit Fields */ #define WDOG_WCR_WDZST_MASK 0x1u #define WDOG_WCR_WDZST_SHIFT 0 #define WDOG_WCR_WDBG_MASK 0x2u #define WDOG_WCR_WDBG_SHIFT 1 #define WDOG_WCR_WDE_MASK 0x4u #define WDOG_WCR_WDE_SHIFT 2 #define WDOG_WCR_WDT_MASK 0x8u #define WDOG_WCR_WDT_SHIFT 3 #define WDOG_WCR_SRS_MASK 0x10u #define WDOG_WCR_SRS_SHIFT 4 #define WDOG_WCR_WDA_MASK 0x20u #define WDOG_WCR_WDA_SHIFT 5 #define WDOG_WCR_SRE_MASK 0x40u #define WDOG_WCR_SRE_SHIFT 6 #define WDOG_WCR_WDW_MASK 0x80u #define WDOG_WCR_WDW_SHIFT 7 #define WDOG_WCR_WT_MASK 0xFF00u #define WDOG_WCR_WT_SHIFT 8 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<MISC0) #define XTALOSC24M_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) #define XTALOSC24M_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) #define XTALOSC24M_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) #define XTALOSC24M_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) #define XTALOSC24M_OSC_CONFIG0_REG(base) ((base)->OSC_CONFIG0) #define XTALOSC24M_OSC_CONFIG0_SET_REG(base) ((base)->OSC_CONFIG0_SET) #define XTALOSC24M_OSC_CONFIG0_CLR_REG(base) ((base)->OSC_CONFIG0_CLR) #define XTALOSC24M_OSC_CONFIG0_TOG_REG(base) ((base)->OSC_CONFIG0_TOG) #define XTALOSC24M_OSC_CONFIG1_REG(base) ((base)->OSC_CONFIG1) #define XTALOSC24M_OSC_CONFIG1_SET_REG(base) ((base)->OSC_CONFIG1_SET) #define XTALOSC24M_OSC_CONFIG1_CLR_REG(base) ((base)->OSC_CONFIG1_CLR) #define XTALOSC24M_OSC_CONFIG1_TOG_REG(base) ((base)->OSC_CONFIG1_TOG) #define XTALOSC24M_OSC_CONFIG2_REG(base) ((base)->OSC_CONFIG2) #define XTALOSC24M_OSC_CONFIG2_SET_REG(base) ((base)->OSC_CONFIG2_SET) #define XTALOSC24M_OSC_CONFIG2_CLR_REG(base) ((base)->OSC_CONFIG2_CLR) #define XTALOSC24M_OSC_CONFIG2_TOG_REG(base) ((base)->OSC_CONFIG2_TOG) /*! * @} */ /* end of group XTALOSC24M_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- XTALOSC24M Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks * @{ */ /* MISC0 Bit Fields */ #define XTALOSC24M_MISC0_REFTOP_PWD_MASK 0x1u #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT 0 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK 0x70u #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT 4 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) #define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) #define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) #define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) #define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) #define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) #define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) #define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) #define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) #define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) #define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) #define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) #define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) #define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) #define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) #define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) #define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) #define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) #define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) #define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) #define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) #define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) #define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) #define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) #define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) #define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) #define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) #define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) /*! * @} */ /* end of group uSDHC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- uSDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup uSDHC_Register_Masks uSDHC Register Masks * @{ */ /* DS_ADDR Bit Fields */ #define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu #define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 #define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<