1 /* 2 * Copyright 2022, 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_ 8 #define HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_ 9 10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h> 11 12 /* SIUL2_0 */ 13 #define PA1_EIRQ_1 NXP_S32_PINMUX(0, 0, 1, 0, 69, 2) 14 #define PA3_EIRQ_0 NXP_S32_PINMUX(0, 0, 3, 0, 68, 2) 15 #define PA5_EIRQ_2 NXP_S32_PINMUX(0, 0, 5, 0, 70, 2) 16 #define PA12_EIRQ_3 NXP_S32_PINMUX(0, 0, 12, 0, 71, 2) 17 #define PA13_EIRQ_4 NXP_S32_PINMUX(0, 0, 13, 0, 72, 2) 18 #define PA14_EIRQ_5 NXP_S32_PINMUX(0, 0, 14, 0, 73, 2) 19 20 /* LINFLEX_0 */ 21 #define PA0_LIN_0_TX NXP_S32_PINMUX(0, 0, 0, 1, 0, 0) 22 #define PA1_LIN_0_RX NXP_S32_PINMUX(0, 0, 1, 0, 47, 2) 23 24 /* GTM */ 25 #define PA0_GTM_000_O NXP_S32_PINMUX(0, 0, 0, 2, 0, 0) 26 #define PA1_GTM_001_O NXP_S32_PINMUX(0, 0, 1, 1, 0, 0) 27 #define PA2_GTM_002_O NXP_S32_PINMUX(0, 0, 2, 2, 0, 0) 28 #define PA3_GTM_003_O NXP_S32_PINMUX(0, 0, 3, 1, 0, 0) 29 #define PA4_GTM_004_O NXP_S32_PINMUX(0, 0, 4, 2, 0, 0) 30 #define PA5_GTM_005_O NXP_S32_PINMUX(0, 0, 5, 1, 0, 0) 31 #define PA6_GTM_006_O NXP_S32_PINMUX(0, 0, 6, 2, 0, 0) 32 #define PA7_GTM_007_O NXP_S32_PINMUX(0, 0, 7, 2, 0, 0) 33 #define PA8_GTM_008_O NXP_S32_PINMUX(0, 0, 8, 1, 0, 0) 34 #define PA9_GTM_009_O NXP_S32_PINMUX(0, 0, 9, 1, 0, 0) 35 #define PA10_GTM_010_O NXP_S32_PINMUX(0, 0, 10, 1, 0, 0) 36 #define PA11_GTM_011_O NXP_S32_PINMUX(0, 0, 11, 2, 0, 0) 37 #define PA12_GTM_012_O NXP_S32_PINMUX(0, 0, 12, 2, 0, 0) 38 #define PA13_GTM_013_O NXP_S32_PINMUX(0, 0, 13, 1, 0, 0) 39 #define PA14_GTM_014_O NXP_S32_PINMUX(0, 0, 14, 2, 0, 0) 40 #define PA14_GTM_A2_3_0_HR NXP_S32_PINMUX(0, 0, 14, 3, 0, 0) 41 #define PB6_GTM_022_O NXP_S32_PINMUX(0, 0, 22, 2, 0, 0) 42 #define PB6_GTM_A1_2_1_HR NXP_S32_PINMUX(0, 0, 22, 3, 0, 0) 43 #define PB7_GTM_023_O NXP_S32_PINMUX(0, 0, 23, 1, 0, 0) 44 #define PB7_GTM_A1_2_0_HR NXP_S32_PINMUX(0, 0, 23, 2, 0, 0) 45 #define PD7_GTM_039_O NXP_S32_PINMUX(1, 1, 39, 1, 0, 0) 46 #define PD9_GTM_040_O NXP_S32_PINMUX(1, 1, 41, 2, 0, 0) 47 #define PD10_GTM_041_O NXP_S32_PINMUX(1, 1, 42, 2, 0, 0) 48 #define PD11_GTM_042_O NXP_S32_PINMUX(1, 1, 43, 1, 0, 0) 49 #define PD12_GTM_043_O NXP_S32_PINMUX(1, 1, 44, 2, 0, 0) 50 #define PD13_GTM_044_O NXP_S32_PINMUX(1, 1, 45, 1, 0, 0) 51 #define PD14_GTM_045_O NXP_S32_PINMUX(1, 1, 46, 2, 0, 0) 52 #define PD15_GTM_046_O NXP_S32_PINMUX(1, 1, 47, 4, 0, 0) 53 #define PE0_GTM_047_O NXP_S32_PINMUX(1, 1, 48, 4, 0, 0) 54 #define PE1_GTM_048_O NXP_S32_PINMUX(1, 1, 49, 4, 0, 0) 55 #define PE2_GTM_049_O NXP_S32_PINMUX(1, 1, 50, 3, 0, 0) 56 #define PE3_GTM_050_O NXP_S32_PINMUX(1, 1, 51, 3, 0, 0) 57 #define PE4_GTM_051_O NXP_S32_PINMUX(1, 1, 52, 2, 0, 0) 58 #define PE5_GTM_052_O NXP_S32_PINMUX(1, 1, 53, 2, 0, 0) 59 #define PE6_GTM_053_O NXP_S32_PINMUX(1, 1, 54, 2, 0, 0) 60 #define PE7_GTM_054_O NXP_S32_PINMUX(1, 1, 55, 2, 0, 0) 61 #define PE8_GTM_055_O NXP_S32_PINMUX(1, 1, 56, 2, 0, 0) 62 #define PE9_GTM_056_O NXP_S32_PINMUX(1, 1, 57, 2, 0, 0) 63 #define PE10_GTM_057_O NXP_S32_PINMUX(1, 1, 58, 2, 0, 0) 64 #define PE11_GTM_058_O NXP_S32_PINMUX(1, 1, 59, 2, 0, 0) 65 #define PE12_GTM_059_O NXP_S32_PINMUX(1, 1, 60, 2, 0, 0) 66 #define PE13_GTM_060_O NXP_S32_PINMUX(1, 1, 61, 4, 0, 0) 67 #define PE14_GTM_061_O NXP_S32_PINMUX(1, 1, 62, 4, 0, 0) 68 #define PE15_GTM_062_O NXP_S32_PINMUX(1, 1, 63, 4, 0, 0) 69 #define PF0_GTM_063_O NXP_S32_PINMUX(1, 1, 64, 3, 0, 0) 70 #define PF1_GTM_064_O NXP_S32_PINMUX(1, 1, 65, 3, 0, 0) 71 #define PF2_GTM_065_O NXP_S32_PINMUX(1, 1, 66, 2, 0, 0) 72 #define PF3_GTM_066_O NXP_S32_PINMUX(1, 1, 67, 2, 0, 0) 73 #define PF4_GTM_067_O NXP_S32_PINMUX(1, 1, 68, 2, 0, 0) 74 #define PF5_GTM_068_O NXP_S32_PINMUX(1, 1, 69, 2, 0, 0) 75 #define PF6_GTM_069_O NXP_S32_PINMUX(1, 1, 70, 2, 0, 0) 76 #define PF7_GTM_070_O NXP_S32_PINMUX(1, 1, 71, 2, 0, 0) 77 #define PF8_GTM_071_O NXP_S32_PINMUX(1, 1, 72, 2, 0, 0) 78 #define PF9_GTM_072_O NXP_S32_PINMUX(1, 1, 73, 1, 0, 0) 79 #define PF10_GTM_073_O NXP_S32_PINMUX(1, 1, 74, 1, 0, 0) 80 #define PF11_GTM_074_O NXP_S32_PINMUX(1, 1, 75, 1, 0, 0) 81 #define PH12_GTM_091_O NXP_S32_PINMUX(4, 4, 92, 1, 0, 0) 82 #define PH13_GTM_092_O NXP_S32_PINMUX(4, 4, 93, 2, 0, 0) 83 #define PH14_GTM_093_O NXP_S32_PINMUX(4, 4, 94, 2, 0, 0) 84 #define PH15_GTM_094_O NXP_S32_PINMUX(4, 4, 95, 2, 0, 0) 85 #define PI0_GTM_095_O NXP_S32_PINMUX(4, 4, 96, 2, 0, 0) 86 #define PI1_GTM_096_O NXP_S32_PINMUX(4, 4, 97, 2, 0, 0) 87 #define PI2_GTM_097_O NXP_S32_PINMUX(4, 4, 98, 2, 0, 0) 88 #define PI3_GTM_098_O NXP_S32_PINMUX(4, 4, 99, 2, 0, 0) 89 #define PI4_GTM_099_O NXP_S32_PINMUX(4, 4, 100, 2, 0, 0) 90 #define PI5_GTM_100_O NXP_S32_PINMUX(4, 4, 101, 2, 0, 0) 91 #define PI6_GTM_101_O NXP_S32_PINMUX(4, 4, 102, 2, 0, 0) 92 #define PI7_GTM_102_O NXP_S32_PINMUX(4, 4, 103, 2, 0, 0) 93 #define PI8_GTM_103_O NXP_S32_PINMUX(4, 4, 104, 2, 0, 0) 94 #define PI9_GTM_104_O NXP_S32_PINMUX(4, 4, 105, 2, 0, 0) 95 #define PI10_GTM_105_O NXP_S32_PINMUX(4, 4, 106, 3, 0, 0) 96 #define PI11_GTM_106_O NXP_S32_PINMUX(4, 4, 107, 3, 0, 0) 97 #define PI12_GTM_107_O NXP_S32_PINMUX(4, 4, 108, 6, 0, 0) 98 #define PI13_GTM_108_O NXP_S32_PINMUX(4, 4, 109, 3, 0, 0) 99 #define PI14_GTM_109_O NXP_S32_PINMUX(4, 4, 110, 4, 0, 0) 100 #define PI15_GTM_110_O NXP_S32_PINMUX(4, 4, 111, 2, 0, 0) 101 #define PJ0_GTM_111_O NXP_S32_PINMUX(4, 4, 112, 5, 0, 0) 102 #define PJ1_GTM_112_O NXP_S32_PINMUX(4, 4, 113, 3, 0, 0) 103 #define PJ2_GTM_113_O NXP_S32_PINMUX(4, 4, 114, 5, 0, 0) 104 #define PJ3_GTM_114_O NXP_S32_PINMUX(4, 4, 115, 4, 0, 0) 105 #define PJ4_GTM_115_O NXP_S32_PINMUX(4, 4, 116, 4, 0, 0) 106 #define PJ5_GTM_116_O NXP_S32_PINMUX(4, 4, 117, 4, 0, 0) 107 #define PJ6_GTM_117_O NXP_S32_PINMUX(4, 4, 118, 2, 0, 0) 108 #define PJ7_GTM_118_O NXP_S32_PINMUX(4, 4, 119, 1, 0, 0) 109 #define PJ8_GTM_119_O NXP_S32_PINMUX(4, 4, 120, 2, 0, 0) 110 #define PJ9_GTM_120_O NXP_S32_PINMUX(4, 4, 121, 1, 0, 0) 111 #define PJ10_GTM_121_O NXP_S32_PINMUX(4, 4, 122, 1, 0, 0) 112 #define PJ11_GTM_122_O NXP_S32_PINMUX(4, 4, 123, 2, 0, 0) 113 #define PJ12_GTM_123_O NXP_S32_PINMUX(4, 4, 124, 1, 0, 0) 114 #define PJ13_GTM_124_O NXP_S32_PINMUX(4, 4, 125, 3, 0, 0) 115 #define PJ14_GTM_125_O NXP_S32_PINMUX(4, 4, 126, 1, 0, 0) 116 #define PJ15_GTM_126_O NXP_S32_PINMUX(4, 4, 127, 2, 0, 0) 117 #define PK0_GTM_127_O NXP_S32_PINMUX(4, 4, 128, 1, 0, 0) 118 #define PK1_GTM_128_O NXP_S32_PINMUX(4, 4, 129, 1, 0, 0) 119 #define PK2_GTM_129_O NXP_S32_PINMUX(4, 4, 130, 1, 0, 0) 120 #define PK3_GTM_130_O NXP_S32_PINMUX(4, 4, 131, 1, 0, 0) 121 #define PK4_GTM_131_O NXP_S32_PINMUX(4, 4, 132, 1, 0, 0) 122 #define PK5_GTM_132_O NXP_S32_PINMUX(4, 4, 133, 1, 0, 0) 123 #define PK6_GTM_133_O NXP_S32_PINMUX(4, 4, 134, 1, 0, 0) 124 #define PK7_GTM_134_O NXP_S32_PINMUX(4, 4, 135, 1, 0, 0) 125 #define PK8_GTM_135_O NXP_S32_PINMUX(4, 4, 136, 1, 0, 0) 126 #define PK9_GTM_136_O NXP_S32_PINMUX(4, 4, 137, 1, 0, 0) 127 #define PK10_GTM_137_O NXP_S32_PINMUX(4, 4, 138, 1, 0, 0) 128 #define PK11_GTM_138_O NXP_S32_PINMUX(4, 4, 139, 1, 0, 0) 129 #define PK12_GTM_139_O NXP_S32_PINMUX(4, 4, 140, 3, 0, 0) 130 #define PK13_GTM_140_O NXP_S32_PINMUX(4, 4, 141, 2, 0, 0) 131 #define PK14_GTM_141_O NXP_S32_PINMUX(4, 4, 142, 3, 0, 0) 132 #define PK15_GTM_142_O NXP_S32_PINMUX(4, 4, 143, 3, 0, 0) 133 #define PL0_GTM_143_O NXP_S32_PINMUX(4, 4, 144, 3, 0, 0) 134 #define PL1_GTM_144_O NXP_S32_PINMUX(4, 4, 145, 3, 0, 0) 135 #define PM2_GTM_145_O NXP_S32_PINMUX(5, 5, 146, 2, 0, 0) 136 #define PM3_GTM_146_O NXP_S32_PINMUX(5, 5, 147, 1, 0, 0) 137 #define PM4_GTM_147_O NXP_S32_PINMUX(5, 5, 148, 2, 0, 0) 138 #define PM5_GTM_148_O NXP_S32_PINMUX(5, 5, 149, 1, 0, 0) 139 #define PM6_GTM_149_O NXP_S32_PINMUX(5, 5, 150, 2, 0, 0) 140 #define PM7_GTM_150_O NXP_S32_PINMUX(5, 5, 151, 1, 0, 0) 141 #define PM8_GTM_151_O NXP_S32_PINMUX(5, 5, 152, 2, 0, 0) 142 #define PM9_GTM_152_O NXP_S32_PINMUX(5, 5, 153, 1, 0, 0) 143 #define PM10_GTM_153_O NXP_S32_PINMUX(5, 5, 154, 2, 0, 0) 144 #define PM11_GTM_154_O NXP_S32_PINMUX(5, 5, 155, 1, 0, 0) 145 #define PM12_GTM_155_O NXP_S32_PINMUX(5, 5, 156, 1, 0, 0) 146 #define PM13_GTM_156_O NXP_S32_PINMUX(5, 5, 157, 2, 0, 0) 147 #define PM14_GTM_157_O NXP_S32_PINMUX(5, 5, 158, 1, 0, 0) 148 #define PM15_GTM_158_O NXP_S32_PINMUX(5, 5, 159, 2, 0, 0) 149 #define PN0_GTM_159_O NXP_S32_PINMUX(5, 5, 160, 1, 0, 0) 150 #define PN1_GTM_160_O NXP_S32_PINMUX(5, 5, 161, 2, 0, 0) 151 #define PN2_GTM_161_O NXP_S32_PINMUX(5, 5, 162, 1, 0, 0) 152 #define PN3_GTM_162_O NXP_S32_PINMUX(5, 5, 163, 1, 0, 0) 153 #define PN4_GTM_163_O NXP_S32_PINMUX(5, 5, 164, 1, 0, 0) 154 #define PN5_GTM_164_O NXP_S32_PINMUX(5, 5, 165, 1, 0, 0) 155 #define PN6_GTM_165_O NXP_S32_PINMUX(5, 5, 166, 1, 0, 0) 156 #define PN7_GTM_166_O NXP_S32_PINMUX(5, 5, 167, 1, 0, 0) 157 #define PN8_GTM_167_O NXP_S32_PINMUX(5, 5, 168, 1, 0, 0) 158 #define PN9_GTM_168_O NXP_S32_PINMUX(5, 5, 169, 1, 0, 0) 159 160 /* FR_0 */ 161 #define PA0_FR_0_TXE_B_B NXP_S32_PINMUX(0, 0, 0, 3, 0, 0) 162 #define PA1_FR_0_TXD_B NXP_S32_PINMUX(0, 0, 1, 2, 0, 0) 163 #define PA2_FR_0_RXD_B NXP_S32_PINMUX(0, 0, 2, 0, 39, 2) 164 #define PA4_FR_0_DBG0 NXP_S32_PINMUX(0, 0, 4, 3, 0, 0) 165 #define PA5_FR_0_DBG1 NXP_S32_PINMUX(0, 0, 5, 3, 0, 0) 166 #define PA6_FR_0_TXE_A_B NXP_S32_PINMUX(0, 0, 6, 1, 0, 0) 167 #define PA7_FR_0_TXD_A NXP_S32_PINMUX(0, 0, 7, 1, 0, 0) 168 #define PA8_FR_0_RXD_A NXP_S32_PINMUX(0, 0, 8, 0, 38, 2) 169 #define PA9_FR_0_DBG2 NXP_S32_PINMUX(0, 0, 9, 3, 0, 0) 170 #define PA10_FR_0_DBG3 NXP_S32_PINMUX(0, 0, 10, 2, 0, 0) 171 172 /* SPI_0 */ 173 #define PA0_DSPI_0_PCS2 NXP_S32_PINMUX(0, 0, 0, 4, 0, 0) 174 #define PA1_DSPI_0_PCS3 NXP_S32_PINMUX(0, 0, 1, 3, 0, 0) 175 #define PA2_DSPI_0_PCS0_O NXP_S32_PINMUX(0, 0, 2, 3, 0, 0) 176 #define PA2_DSPI_0_PCS0_I NXP_S32_PINMUX(0, 0, 2, 0, 3, 2) 177 #define PA3_DSPI_0_PCS1 NXP_S32_PINMUX(0, 0, 3, 2, 0, 0) 178 #define PA6_DSPI_0_SCK_O NXP_S32_PINMUX(0, 0, 6, 4, 0, 0) 179 #define PA6_DSPI_0_SCK_I NXP_S32_PINMUX(0, 0, 6, 0, 4, 2) 180 #define PA7_DSPI_0_SIN NXP_S32_PINMUX(0, 0, 7, 0, 5, 2) 181 #define PA8_DSPI_0_SOUT NXP_S32_PINMUX(0, 0, 8, 2, 0, 0) 182 #define PA9_DSPI_0_PCS4 NXP_S32_PINMUX(0, 0, 9, 2, 0, 0) 183 184 /* EMIOS_1 */ 185 #define PA0_EMIOS_1_CH6_O NXP_S32_PINMUX(0, 0, 0, 5, 0, 0) 186 #define PA0_EMIOS_1_CH6_I NXP_S32_PINMUX(0, 0, 0, 0, 35, 2) 187 #define PA1_EMIOS_1_CH7_O NXP_S32_PINMUX(0, 0, 1, 5, 0, 0) 188 #define PA1_EMIOS_1_CH7_I NXP_S32_PINMUX(0, 0, 1, 0, 36, 2) 189 #define PA2_EMIOS_1_CH1_O NXP_S32_PINMUX(0, 0, 2, 5, 0, 0) 190 #define PA2_EMIOS_1_CH1_I NXP_S32_PINMUX(0, 0, 2, 0, 11, 2) 191 #define PA3_EMIOS_1_CH2_O NXP_S32_PINMUX(0, 0, 3, 4, 0, 0) 192 #define PA3_EMIOS_1_CH2_I NXP_S32_PINMUX(0, 0, 3, 0, 19, 2) 193 #define PA4_EMIOS_1_CH5_O NXP_S32_PINMUX(0, 0, 4, 5, 0, 0) 194 #define PA4_EMIOS_1_CH5_I NXP_S32_PINMUX(0, 0, 4, 0, 34, 2) 195 #define PA5_EMIOS_1_CH0_O NXP_S32_PINMUX(0, 0, 5, 5, 0, 0) 196 #define PA5_EMIOS_1_CH0_I NXP_S32_PINMUX(0, 0, 5, 0, 10, 2) 197 #define PA6_EMIOS_1_CH3_O NXP_S32_PINMUX(0, 0, 6, 6, 0, 0) 198 #define PA6_EMIOS_1_CH3_I NXP_S32_PINMUX(0, 0, 6, 0, 30, 2) 199 #define PA7_EMIOS_1_CH4_O NXP_S32_PINMUX(0, 0, 7, 6, 0, 0) 200 #define PA7_EMIOS_1_CH4_I NXP_S32_PINMUX(0, 0, 7, 0, 33, 2) 201 #define PA11_EMIOS_1_CH16_O NXP_S32_PINMUX(0, 0, 11, 4, 0, 0) 202 #define PA11_EMIOS_1_CH16_I NXP_S32_PINMUX(0, 0, 11, 0, 15, 2) 203 #define PA12_EMIOS_1_CH23_O NXP_S32_PINMUX(0, 0, 12, 5, 0, 0) 204 #define PA12_EMIOS_1_CH23_I NXP_S32_PINMUX(0, 0, 12, 0, 23, 2) 205 #define PA13_EMIOS_1_CH22_O NXP_S32_PINMUX(0, 0, 13, 3, 0, 0) 206 #define PA13_EMIOS_1_CH22_I NXP_S32_PINMUX(0, 0, 13, 0, 22, 2) 207 #define PA14_EMIOS_1_CH31_O NXP_S32_PINMUX(0, 0, 14, 5, 0, 0) 208 #define PA14_EMIOS_1_CH31_I NXP_S32_PINMUX(0, 0, 14, 0, 32, 2) 209 #define PB6_EMIOS_1_CH18_O NXP_S32_PINMUX(0, 0, 22, 5, 0, 0) 210 #define PB6_EMIOS_1_CH18_I NXP_S32_PINMUX(0, 0, 22, 0, 17, 2) 211 #define PB7_EMIOS_1_CH19_O NXP_S32_PINMUX(0, 0, 23, 4, 0, 0) 212 #define PB7_EMIOS_1_CH19_I NXP_S32_PINMUX(0, 0, 23, 0, 18, 2) 213 #define PI15_EMIOS_1_CH16_I NXP_S32_PINMUX(4, 0, 111, 0, 15, 3) 214 #define PJ0_EMIOS_1_CH23_I NXP_S32_PINMUX(4, 0, 112, 0, 23, 3) 215 #define PJ1_EMIOS_1_CH21_I NXP_S32_PINMUX(4, 0, 113, 0, 21, 3) 216 #define PJ2_EMIOS_1_CH20_I NXP_S32_PINMUX(4, 0, 114, 0, 20, 3) 217 #define PJ3_EMIOS_1_CH19_I NXP_S32_PINMUX(4, 0, 115, 0, 18, 3) 218 #define PJ4_EMIOS_1_CH18_I NXP_S32_PINMUX(4, 0, 116, 0, 17, 3) 219 #define PJ5_EMIOS_1_CH17_I NXP_S32_PINMUX(4, 0, 117, 0, 16, 3) 220 #define PJ8_EMIOS_1_CH31_I NXP_S32_PINMUX(4, 0, 120, 0, 32, 3) 221 #define PJ9_EMIOS_1_CH30_I NXP_S32_PINMUX(4, 0, 121, 0, 31, 3) 222 #define PJ11_EMIOS_1_CH29_I NXP_S32_PINMUX(4, 0, 123, 0, 29, 3) 223 #define PJ12_EMIOS_1_CH28_I NXP_S32_PINMUX(4, 0, 124, 0, 28, 3) 224 #define PJ13_EMIOS_1_CH27_I NXP_S32_PINMUX(4, 0, 125, 0, 27, 3) 225 #define PJ14_EMIOS_1_CH26_I NXP_S32_PINMUX(4, 0, 126, 0, 26, 3) 226 #define PJ15_EMIOS_1_CH25_I NXP_S32_PINMUX(4, 0, 127, 0, 25, 3) 227 #define PK0_EMIOS_1_CH24_I NXP_S32_PINMUX(4, 0, 128, 0, 24, 3) 228 #define PK1_EMIOS_1_CH23_I NXP_S32_PINMUX(4, 0, 129, 0, 23, 4) 229 #define PK2_EMIOS_1_CH22_I NXP_S32_PINMUX(4, 0, 130, 0, 22, 3) 230 #define PK3_EMIOS_1_CH8_I NXP_S32_PINMUX(4, 0, 131, 0, 37, 3) 231 #define PK4_EMIOS_1_CH17_I NXP_S32_PINMUX(4, 0, 132, 0, 16, 4) 232 #define PK5_EMIOS_1_CH10_I NXP_S32_PINMUX(4, 0, 133, 0, 12, 3) 233 #define PK6_EMIOS_1_CH20_I NXP_S32_PINMUX(4, 0, 134, 0, 20, 4) 234 #define PK7_EMIOS_1_CH12_I NXP_S32_PINMUX(4, 0, 135, 0, 13, 3) 235 #define PK8_EMIOS_1_CH21_I NXP_S32_PINMUX(4, 0, 136, 0, 21, 4) 236 #define PK9_EMIOS_1_CH14_I NXP_S32_PINMUX(4, 0, 137, 0, 14, 3) 237 #define PK10_EMIOS_1_CH0_I NXP_S32_PINMUX(4, 0, 138, 0, 10, 3) 238 #define PK11_EMIOS_1_CH1_I NXP_S32_PINMUX(4, 0, 139, 0, 11, 3) 239 #define PK12_EMIOS_1_CH2_I NXP_S32_PINMUX(4, 0, 140, 0, 19, 3) 240 #define PK13_EMIOS_1_CH3_I NXP_S32_PINMUX(4, 0, 141, 0, 30, 3) 241 #define PK14_EMIOS_1_CH4_I NXP_S32_PINMUX(4, 0, 142, 0, 33, 3) 242 #define PK15_EMIOS_1_CH5_I NXP_S32_PINMUX(4, 0, 143, 0, 34, 3) 243 #define PL0_EMIOS_1_CH6_I NXP_S32_PINMUX(4, 0, 144, 0, 35, 3) 244 #define PL1_EMIOS_1_CH7_I NXP_S32_PINMUX(4, 0, 145, 0, 36, 3) 245 246 /* CTU */ 247 #define PA0_CTU_EXT_IN NXP_S32_PINMUX(0, 0, 0, 0, 2, 2) 248 #define PA8_CTU_EXT_IN NXP_S32_PINMUX(0, 0, 8, 0, 2, 3) 249 250 /* EMIOS_0 */ 251 #define PA0_EMIOS_0_CH6_I NXP_S32_PINMUX(0, 4, 0, 0, 322, 3) 252 #define PA1_EMIOS_0_CH7_I NXP_S32_PINMUX(0, 4, 1, 0, 323, 3) 253 #define PA2_EMIOS_0_CH1_I NXP_S32_PINMUX(0, 4, 2, 0, 317, 3) 254 #define PA3_EMIOS_0_CH2_I NXP_S32_PINMUX(0, 4, 3, 0, 318, 3) 255 #define PA4_EMIOS_0_CH5_I NXP_S32_PINMUX(0, 4, 4, 0, 321, 3) 256 #define PA5_EMIOS_0_CH0_I NXP_S32_PINMUX(0, 4, 5, 0, 316, 3) 257 #define PA6_EMIOS_0_CH3_I NXP_S32_PINMUX(0, 4, 6, 0, 319, 3) 258 #define PA7_EMIOS_0_CH4_I NXP_S32_PINMUX(0, 4, 7, 0, 320, 3) 259 #define PA11_EMIOS_0_CH16_I NXP_S32_PINMUX(0, 4, 11, 0, 328, 3) 260 #define PA12_EMIOS_0_CH23_I NXP_S32_PINMUX(0, 4, 12, 0, 335, 4) 261 #define PA13_EMIOS_0_CH22_I NXP_S32_PINMUX(0, 4, 13, 0, 334, 3) 262 #define PA14_EMIOS_0_CH31_I NXP_S32_PINMUX(0, 4, 14, 0, 343, 3) 263 #define PB6_EMIOS_0_CH18_I NXP_S32_PINMUX(0, 4, 22, 0, 330, 3) 264 #define PB7_EMIOS_0_CH19_I NXP_S32_PINMUX(0, 4, 23, 0, 331, 3) 265 #define PI15_EMIOS_0_CH16_O NXP_S32_PINMUX(4, 4, 111, 5, 0, 0) 266 #define PI15_EMIOS_0_CH16_I NXP_S32_PINMUX(4, 4, 111, 0, 328, 2) 267 #define PJ0_EMIOS_0_CH23_O NXP_S32_PINMUX(4, 4, 112, 6, 0, 0) 268 #define PJ0_EMIOS_0_CH23_I NXP_S32_PINMUX(4, 4, 112, 0, 335, 2) 269 #define PJ1_EMIOS_0_CH21_O NXP_S32_PINMUX(4, 4, 113, 4, 0, 0) 270 #define PJ1_EMIOS_0_CH21_I NXP_S32_PINMUX(4, 4, 113, 0, 333, 3) 271 #define PJ2_EMIOS_0_CH20_O NXP_S32_PINMUX(4, 4, 114, 6, 0, 0) 272 #define PJ2_EMIOS_0_CH20_I NXP_S32_PINMUX(4, 4, 114, 0, 332, 2) 273 #define PJ3_EMIOS_0_CH19_O NXP_S32_PINMUX(4, 4, 115, 5, 0, 0) 274 #define PJ3_EMIOS_0_CH19_I NXP_S32_PINMUX(4, 4, 115, 0, 331, 2) 275 #define PJ4_EMIOS_0_CH18_O NXP_S32_PINMUX(4, 4, 116, 6, 0, 0) 276 #define PJ4_EMIOS_0_CH18_I NXP_S32_PINMUX(4, 4, 116, 0, 330, 2) 277 #define PJ5_EMIOS_0_CH17_O NXP_S32_PINMUX(4, 4, 117, 5, 0, 0) 278 #define PJ5_EMIOS_0_CH17_I NXP_S32_PINMUX(4, 4, 117, 0, 329, 2) 279 #define PJ8_EMIOS_0_CH31_O NXP_S32_PINMUX(4, 4, 120, 5, 0, 0) 280 #define PJ8_EMIOS_0_CH31_I NXP_S32_PINMUX(4, 4, 120, 0, 343, 2) 281 #define PJ9_EMIOS_0_CH30_O NXP_S32_PINMUX(4, 4, 121, 3, 0, 0) 282 #define PJ9_EMIOS_0_CH30_I NXP_S32_PINMUX(4, 4, 121, 0, 342, 2) 283 #define PJ11_EMIOS_0_CH29_O NXP_S32_PINMUX(4, 4, 123, 4, 0, 0) 284 #define PJ11_EMIOS_0_CH29_I NXP_S32_PINMUX(4, 4, 123, 0, 341, 2) 285 #define PJ12_EMIOS_0_CH28_O NXP_S32_PINMUX(4, 4, 124, 3, 0, 0) 286 #define PJ12_EMIOS_0_CH28_I NXP_S32_PINMUX(4, 4, 124, 0, 340, 2) 287 #define PJ13_EMIOS_0_CH27_O NXP_S32_PINMUX(4, 4, 125, 5, 0, 0) 288 #define PJ13_EMIOS_0_CH27_I NXP_S32_PINMUX(4, 4, 125, 0, 339, 2) 289 #define PJ14_EMIOS_0_CH26_O NXP_S32_PINMUX(4, 4, 126, 3, 0, 0) 290 #define PJ14_EMIOS_0_CH26_I NXP_S32_PINMUX(4, 4, 126, 0, 338, 2) 291 #define PJ15_EMIOS_0_CH25_O NXP_S32_PINMUX(4, 4, 127, 4, 0, 0) 292 #define PJ15_EMIOS_0_CH25_I NXP_S32_PINMUX(4, 4, 127, 0, 337, 2) 293 #define PK0_EMIOS_0_CH24_O NXP_S32_PINMUX(4, 4, 128, 2, 0, 0) 294 #define PK0_EMIOS_0_CH24_I NXP_S32_PINMUX(4, 4, 128, 0, 336, 2) 295 #define PK1_EMIOS_0_CH23_O NXP_S32_PINMUX(4, 4, 129, 2, 0, 0) 296 #define PK1_EMIOS_0_CH23_I NXP_S32_PINMUX(4, 4, 129, 0, 335, 3) 297 #define PK2_EMIOS_0_CH22_O NXP_S32_PINMUX(4, 4, 130, 2, 0, 0) 298 #define PK2_EMIOS_0_CH22_I NXP_S32_PINMUX(4, 4, 130, 0, 334, 2) 299 #define PK3_EMIOS_0_CH8_O NXP_S32_PINMUX(4, 4, 131, 2, 0, 0) 300 #define PK3_EMIOS_0_CH8_I NXP_S32_PINMUX(4, 4, 131, 0, 324, 2) 301 #define PK4_EMIOS_0_CH17_O NXP_S32_PINMUX(4, 4, 132, 2, 0, 0) 302 #define PK4_EMIOS_0_CH17_I NXP_S32_PINMUX(4, 4, 132, 0, 329, 3) 303 #define PK5_EMIOS_0_CH10_O NXP_S32_PINMUX(4, 4, 133, 3, 0, 0) 304 #define PK5_EMIOS_0_CH10_I NXP_S32_PINMUX(4, 4, 133, 0, 325, 2) 305 #define PK6_EMIOS_0_CH20_O NXP_S32_PINMUX(4, 4, 134, 3, 0, 0) 306 #define PK6_EMIOS_0_CH20_I NXP_S32_PINMUX(4, 4, 134, 0, 332, 3) 307 #define PK7_EMIOS_0_CH12_O NXP_S32_PINMUX(4, 4, 135, 3, 0, 0) 308 #define PK7_EMIOS_0_CH12_I NXP_S32_PINMUX(4, 4, 135, 0, 326, 2) 309 #define PK8_EMIOS_0_CH21_O NXP_S32_PINMUX(4, 4, 136, 3, 0, 0) 310 #define PK8_EMIOS_0_CH21_I NXP_S32_PINMUX(4, 4, 136, 0, 333, 2) 311 #define PK9_EMIOS_0_CH14_O NXP_S32_PINMUX(4, 4, 137, 3, 0, 0) 312 #define PK9_EMIOS_0_CH14_I NXP_S32_PINMUX(4, 4, 137, 0, 327, 2) 313 #define PK10_EMIOS_0_CH0_O NXP_S32_PINMUX(4, 4, 138, 3, 0, 0) 314 #define PK10_EMIOS_0_CH0_I NXP_S32_PINMUX(4, 4, 138, 0, 316, 2) 315 #define PK11_EMIOS_0_CH1_O NXP_S32_PINMUX(4, 4, 139, 2, 0, 0) 316 #define PK11_EMIOS_0_CH1_I NXP_S32_PINMUX(4, 4, 139, 0, 317, 2) 317 #define PK12_EMIOS_0_CH2_O NXP_S32_PINMUX(4, 4, 140, 4, 0, 0) 318 #define PK12_EMIOS_0_CH2_I NXP_S32_PINMUX(4, 4, 140, 0, 318, 2) 319 #define PK13_EMIOS_0_CH3_O NXP_S32_PINMUX(4, 4, 141, 3, 0, 0) 320 #define PK13_EMIOS_0_CH3_I NXP_S32_PINMUX(4, 4, 141, 0, 319, 2) 321 #define PK14_EMIOS_0_CH4_O NXP_S32_PINMUX(4, 4, 142, 4, 0, 0) 322 #define PK14_EMIOS_0_CH4_I NXP_S32_PINMUX(4, 4, 142, 0, 320, 2) 323 #define PK15_EMIOS_0_CH5_O NXP_S32_PINMUX(4, 4, 143, 4, 0, 0) 324 #define PK15_EMIOS_0_CH5_I NXP_S32_PINMUX(4, 4, 143, 0, 321, 2) 325 #define PL0_EMIOS_0_CH6_O NXP_S32_PINMUX(4, 4, 144, 4, 0, 0) 326 #define PL0_EMIOS_0_CH6_I NXP_S32_PINMUX(4, 4, 144, 0, 322, 2) 327 #define PL1_EMIOS_0_CH7_O NXP_S32_PINMUX(4, 4, 145, 4, 0, 0) 328 #define PL1_EMIOS_0_CH7_I NXP_S32_PINMUX(4, 4, 145, 0, 323, 2) 329 330 /* I3C_0 */ 331 #define PA1_I3C_0_SDA3_O NXP_S32_PINMUX(0, 0, 1, 4, 0, 0) 332 #define PA1_I3C_0_SDA3_I NXP_S32_PINMUX(0, 0, 1, 0, 46, 2) 333 #define PA4_I3C_0_SDA2_O NXP_S32_PINMUX(0, 0, 4, 4, 0, 0) 334 #define PA4_I3C_0_SDA2_I NXP_S32_PINMUX(0, 0, 4, 0, 45, 2) 335 #define PA5_I3C_0_SDA1_O NXP_S32_PINMUX(0, 0, 5, 4, 0, 0) 336 #define PA5_I3C_0_SDA1_I NXP_S32_PINMUX(0, 0, 5, 0, 44, 2) 337 #define PA6_I3C_0_SDA0_O NXP_S32_PINMUX(0, 0, 6, 5, 0, 0) 338 #define PA6_I3C_0_SDA0_I NXP_S32_PINMUX(0, 0, 6, 0, 43, 2) 339 #define PA7_I3C_0_SCL_O NXP_S32_PINMUX(0, 0, 7, 5, 0, 0) 340 #define PA7_I3C_0_SCL_I NXP_S32_PINMUX(0, 0, 7, 0, 42, 2) 341 #define PA8_I3C_0_PUR NXP_S32_PINMUX(0, 0, 8, 3, 0, 0) 342 343 /* LINFLEX_1 */ 344 #define PA2_LIN_1_TX NXP_S32_PINMUX(0, 0, 2, 1, 0, 0) 345 #define PA3_LIN_1_RX NXP_S32_PINMUX(0, 0, 3, 0, 48, 2) 346 347 /* PSI5_S_0 */ 348 #define PA2_PSI5_S_0_TX NXP_S32_PINMUX(0, 0, 2, 4, 0, 0) 349 #define PA3_PSI5_S_0_RX NXP_S32_PINMUX(0, 0, 3, 0, 59, 2) 350 #define PA5_PSI5_S_0_TXCLK NXP_S32_PINMUX(0, 0, 5, 2, 0, 0) 351 #define PB7_PSI5_S_0_TX NXP_S32_PINMUX(0, 0, 23, 5, 0, 0) 352 353 /* PSI5_0 */ 354 #define PA2_PSI5_0_SDIN0 NXP_S32_PINMUX(0, 0, 2, 0, 55, 2) 355 #define PA3_PSI5_0_SDOUT0 NXP_S32_PINMUX(0, 0, 3, 3, 0, 0) 356 #define PA6_PSI5_0_SDIN1 NXP_S32_PINMUX(0, 0, 6, 0, 56, 2) 357 #define PA7_PSI5_0_SDOUT1 NXP_S32_PINMUX(0, 0, 7, 4, 0, 0) 358 #define PA12_PSI5_0_SDIN0 NXP_S32_PINMUX(0, 0, 12, 0, 55, 3) 359 360 /* CAN_HUB */ 361 #define PA4_CAN_0_TX NXP_S32_PINMUX(0, 0, 4, 1, 0, 0) 362 #define PA5_CAN_0_RX NXP_S32_PINMUX(0, 3, 5, 0, 0, 2) 363 #define PA12_CAN_0_TX NXP_S32_PINMUX(0, 0, 12, 3, 0, 0) 364 #define PA13_CAN_0_RX NXP_S32_PINMUX(0, 3, 13, 0, 0, 3) 365 #define PB6_CAN_1_TX NXP_S32_PINMUX(0, 0, 22, 1, 0, 0) 366 #define PB7_CAN_1_RX NXP_S32_PINMUX(0, 3, 23, 0, 1, 2) 367 #define PE1_CAN_3_TX NXP_S32_PINMUX(1, 1, 49, 6, 0, 0) 368 #define PE2_CAN_3_RX NXP_S32_PINMUX(1, 3, 50, 0, 3, 3) 369 #define PE3_CAN_4_TX NXP_S32_PINMUX(1, 1, 51, 4, 0, 0) 370 #define PE4_CAN_4_RX NXP_S32_PINMUX(1, 3, 52, 0, 4, 3) 371 #define PI10_CAN_6_TX NXP_S32_PINMUX(4, 4, 106, 4, 0, 0) 372 #define PI11_CAN_6_RX NXP_S32_PINMUX(4, 3, 107, 0, 6, 2) 373 #define PI12_CAN_7_TX NXP_S32_PINMUX(4, 4, 108, 3, 0, 0) 374 #define PI13_CAN_7_RX NXP_S32_PINMUX(4, 3, 109, 0, 7, 2) 375 #define PI14_CAN_8_TX NXP_S32_PINMUX(4, 4, 110, 3, 0, 0) 376 #define PI15_CAN_8_RX NXP_S32_PINMUX(4, 3, 111, 0, 8, 2) 377 #define PJ0_CAN_3_TX NXP_S32_PINMUX(4, 4, 112, 4, 0, 0) 378 #define PJ1_CAN_3_RX NXP_S32_PINMUX(4, 3, 113, 0, 3, 5) 379 #define PJ2_CAN_4_TX NXP_S32_PINMUX(4, 4, 114, 4, 0, 0) 380 #define PJ3_CAN_4_RX NXP_S32_PINMUX(4, 3, 115, 0, 4, 5) 381 #define PJ4_CAN_6_TX NXP_S32_PINMUX(4, 4, 116, 5, 0, 0) 382 #define PJ5_CAN_6_RX NXP_S32_PINMUX(4, 3, 117, 0, 6, 3) 383 #define PJ6_CAN_7_TX NXP_S32_PINMUX(4, 4, 118, 5, 0, 0) 384 #define PJ7_CAN_7_RX NXP_S32_PINMUX(4, 3, 119, 0, 7, 3) 385 #define PJ8_CAN_12_TX NXP_S32_PINMUX(4, 4, 120, 3, 0, 0) 386 #define PJ9_CAN_12_RX NXP_S32_PINMUX(4, 3, 121, 0, 12, 2) 387 #define PJ10_CAN_17_TX NXP_S32_PINMUX(4, 4, 122, 3, 0, 0) 388 #define PJ11_CAN_17_RX NXP_S32_PINMUX(4, 3, 123, 0, 17, 2) 389 #define PJ13_CAN_2_TX NXP_S32_PINMUX(4, 4, 125, 2, 0, 0) 390 #define PJ14_CAN_2_RX NXP_S32_PINMUX(4, 3, 126, 0, 2, 3) 391 #define PJ15_CAN_12_TX NXP_S32_PINMUX(4, 4, 127, 1, 0, 0) 392 #define PJ15_CAN_18_TX NXP_S32_PINMUX(4, 4, 127, 6, 0, 0) 393 #define PK0_CAN_12_RX NXP_S32_PINMUX(4, 3, 128, 0, 12, 3) 394 #define PK0_CAN_18_RX NXP_S32_PINMUX(4, 3, 128, 0, 18, 2) 395 #define PK1_CAN_19_TX NXP_S32_PINMUX(4, 4, 129, 4, 0, 0) 396 #define PK2_CAN_19_RX NXP_S32_PINMUX(4, 3, 130, 0, 19, 2) 397 #define PK3_CAN_20_TX NXP_S32_PINMUX(4, 4, 131, 3, 0, 0) 398 #define PK4_CAN_20_RX NXP_S32_PINMUX(4, 3, 132, 0, 20, 2) 399 #define PK5_CAN_21_TX NXP_S32_PINMUX(4, 4, 133, 4, 0, 0) 400 #define PK6_CAN_1_TX NXP_S32_PINMUX(4, 4, 134, 4, 0, 0) 401 #define PK7_CAN_1_RX NXP_S32_PINMUX(4, 3, 135, 0, 1, 3) 402 #define PK9_CAN_21_RX NXP_S32_PINMUX(4, 3, 137, 0, 21, 2) 403 #define PK10_CAN_12_TX NXP_S32_PINMUX(4, 4, 138, 2, 0, 0) 404 #define PK10_CAN_6_TX NXP_S32_PINMUX(4, 4, 138, 4, 0, 0) 405 #define PK11_CAN_6_RX NXP_S32_PINMUX(4, 3, 139, 0, 6, 4) 406 #define PK11_CAN_12_RX NXP_S32_PINMUX(4, 3, 139, 0, 12, 4) 407 #define PK12_CAN_7_TX NXP_S32_PINMUX(4, 4, 140, 5, 0, 0) 408 #define PK13_CAN_7_RX NXP_S32_PINMUX(4, 3, 141, 0, 7, 4) 409 #define PK14_CAN_8_TX NXP_S32_PINMUX(4, 4, 142, 5, 0, 0) 410 #define PK15_CAN_8_RX NXP_S32_PINMUX(4, 3, 143, 0, 8, 3) 411 #define PM2_CAN_10_TX NXP_S32_PINMUX(5, 5, 146, 1, 0, 0) 412 #define PM3_CAN_10_RX NXP_S32_PINMUX(5, 3, 147, 0, 10, 2) 413 #define PM4_CAN_11_TX NXP_S32_PINMUX(5, 5, 148, 1, 0, 0) 414 #define PM5_CAN_11_RX NXP_S32_PINMUX(5, 3, 149, 0, 11, 2) 415 #define PM6_CAN_1_TX NXP_S32_PINMUX(5, 5, 150, 5, 0, 0) 416 #define PM7_CAN_1_RX NXP_S32_PINMUX(5, 3, 151, 0, 1, 4) 417 #define PM8_CAN_22_TX NXP_S32_PINMUX(5, 5, 152, 4, 0, 0) 418 #define PM9_CAN_22_RX NXP_S32_PINMUX(5, 3, 153, 0, 22, 2) 419 #define PM10_CAN_13_TX NXP_S32_PINMUX(5, 5, 154, 1, 0, 0) 420 #define PM11_CAN_13_RX NXP_S32_PINMUX(5, 3, 155, 0, 13, 2) 421 #define PM13_CAN_2_TX NXP_S32_PINMUX(5, 5, 157, 4, 0, 0) 422 #define PM14_CAN_2_RX NXP_S32_PINMUX(5, 3, 158, 0, 2, 4) 423 #define PM15_CAN_9_TX NXP_S32_PINMUX(5, 5, 159, 1, 0, 0) 424 #define PN0_CAN_9_RX NXP_S32_PINMUX(5, 3, 160, 0, 9, 2) 425 #define PN1_CAN_5_TX NXP_S32_PINMUX(5, 5, 161, 1, 0, 0) 426 #define PN1_CAN_23_TX NXP_S32_PINMUX(5, 5, 161, 5, 0, 0) 427 #define PN2_CAN_5_RX NXP_S32_PINMUX(5, 3, 162, 0, 5, 3) 428 #define PN2_CAN_23_RX NXP_S32_PINMUX(5, 3, 162, 0, 23, 2) 429 #define PN4_CAN_1_TX NXP_S32_PINMUX(5, 5, 164, 3, 0, 0) 430 #define PN5_CAN_1_RX NXP_S32_PINMUX(5, 3, 165, 0, 1, 5) 431 #define PN6_CAN_2_TX NXP_S32_PINMUX(5, 5, 166, 3, 0, 0) 432 #define PN7_CAN_2_RX NXP_S32_PINMUX(5, 3, 167, 0, 2, 5) 433 434 /* FR_1 */ 435 #define PA6_FR_1_TXE_B_B NXP_S32_PINMUX(0, 0, 6, 3, 0, 0) 436 #define PA7_FR_1_TXD_B NXP_S32_PINMUX(0, 0, 7, 3, 0, 0) 437 #define PA8_FR_1_RXD_B NXP_S32_PINMUX(0, 0, 8, 0, 41, 2) 438 #define PA11_FR_1_DBG0 NXP_S32_PINMUX(0, 0, 11, 3, 0, 0) 439 #define PA12_FR_1_DBG1 NXP_S32_PINMUX(0, 0, 12, 4, 0, 0) 440 #define PA13_FR_1_DBG2 NXP_S32_PINMUX(0, 0, 13, 2, 0, 0) 441 442 /* DEBUG */ 443 #define PA8_EVTI_B_0 NXP_S32_PINMUX(0, 0, 8, 0, 85, 2) 444 #define PA9_EVTO_B_0 NXP_S32_PINMUX(0, 0, 9, 4, 0, 0) 445 446 /* MC_CGM_0 */ 447 #define PA9_CLKOUT_0 NXP_S32_PINMUX(0, 0, 9, 5, 0, 0) 448 449 /* BOOT */ 450 #define PA9_BOOTMOD_0 NXP_S32_PINMUX(0, 0, 9, 0, 0, 0) 451 #define PA10_BOOTMOD_1 NXP_S32_PINMUX(0, 0, 10, 0, 1, 0) 452 453 /* MISC */ 454 #define PA9_TAMPER_IN NXP_S32_PINMUX(0, 0, 9, 0, 51, 2) 455 #define PO11_TAMPER_OUT NXP_S32_PINMUX(0, 0, 171, 2, 0, 0) 456 457 /* SINC */ 458 #define PA10_SINC_MCLK_OUT2 NXP_S32_PINMUX(0, 0, 10, 3, 0, 0) 459 #define PA11_SINC_MCLK_OUT0 NXP_S32_PINMUX(0, 0, 11, 6, 0, 0) 460 #define PA11_SINC_MCLK_OUT1 NXP_S32_PINMUX(0, 0, 11, 7, 0, 0) 461 #define PB7_SINC_MBIT3 NXP_S32_PINMUX(0, 0, 23, 0, 63, 2) 462 463 /* MSC_0_DSPI */ 464 #define PA11_DSPI_10_PCS0_O NXP_S32_PINMUX(0, 0, 11, 1, 0, 0) 465 #define PA12_DSPI_10_PCS1 NXP_S32_PINMUX(0, 0, 12, 1, 0, 0) 466 #define PB6_DSPI_10_PCS2 NXP_S32_PINMUX(0, 0, 22, 6, 0, 0) 467 #define LVDS_DSPI_10_SIN NXP_S32_PINMUX(0, 0, 500, 0, 0, 0) 468 #define LVDS_DSPI_10_SOUT NXP_S32_PINMUX(0, 0, 501, 0, 0, 0) 469 #define LVDS_DSPI_10_SCK NXP_S32_PINMUX(0, 0, 502, 0, 0, 0) 470 471 /* SPI_1 */ 472 #define PA11_DSPI_1_PCS4 NXP_S32_PINMUX(0, 0, 11, 5, 0, 0) 473 474 /* LINFLEX_2 */ 475 #define PA13_LIN_2_TX NXP_S32_PINMUX(0, 0, 13, 4, 0, 0) 476 #define PA14_LIN_2_RX NXP_S32_PINMUX(0, 0, 14, 0, 50, 2) 477 478 /* MSC_0_LIN */ 479 #define PA13_LIN_12_RX NXP_S32_PINMUX(0, 0, 13, 0, 49, 2) 480 #define PA14_LIN_12_TX NXP_S32_PINMUX(0, 0, 14, 1, 0, 0) 481 482 /* LCU_1 */ 483 #define PA14_LCU_1_OUT0 NXP_S32_PINMUX(0, 0, 14, 4, 0, 0) 484 #define PB6_LCU_1_OUT8 NXP_S32_PINMUX(0, 0, 22, 4, 0, 0) 485 #define PB7_LCU_1_OUT9 NXP_S32_PINMUX(0, 0, 23, 3, 0, 0) 486 487 /* NETC */ 488 #define PD9_TMR_1588_CLK_O NXP_S32_PINMUX(1, 1, 41, 3, 0, 0) 489 #define PD10_ETH_1_MII_TXER NXP_S32_PINMUX(1, 1, 42, 1, 0, 0) 490 #define PD10_TMR_1588_CLK_O NXP_S32_PINMUX(1, 1, 42, 3, 0, 0) 491 #define PD11_TMR_1588_TRIG1 NXP_S32_PINMUX(1, 1, 43, 0, 178, 2) 492 #define PD11_ETH_1_MII_RXER NXP_S32_PINMUX(1, 1, 43, 0, 165, 2) 493 #define PD11_ETH_1_RMII_RXER NXP_S32_PINMUX(1, 1, 43, 0, 174, 2) 494 #define PD12_TMR_1588_ALARM1 NXP_S32_PINMUX(1, 1, 44, 1, 0, 0) 495 #define PD12_TMR_1588_PP1 NXP_S32_PINMUX(1, 1, 44, 4, 0, 0) 496 #define PD12_ETH_1_MII_CRS NXP_S32_PINMUX(1, 1, 44, 0, 157, 2) 497 #define PD13_TMR_1588_PP2 NXP_S32_PINMUX(1, 1, 45, 2, 0, 0) 498 #define PD13_TMR_1588_CLK_O NXP_S32_PINMUX(1, 1, 45, 3, 0, 0) 499 #define PD13_ETH_1_MII_COL NXP_S32_PINMUX(1, 1, 45, 0, 156, 2) 500 #define PD13_TMR_1588_TRIG2 NXP_S32_PINMUX(1, 1, 45, 0, 179, 2) 501 #define PD14_ETH_1_RGMII_TXC NXP_S32_PINMUX(1, 1, 46, 1, 0, 0) 502 #define PD15_ETH_1_RGMII_TXCTL NXP_S32_PINMUX(1, 1, 47, 1, 0, 0) 503 #define PD15_ETH_1_MII_TXEN NXP_S32_PINMUX(1, 1, 47, 2, 0, 0) 504 #define PD15_ETH_1_RMII_TXEN NXP_S32_PINMUX(1, 1, 47, 3, 0, 0) 505 #define PD15_ETH_1_RGMII_RXCTL NXP_S32_PINMUX(1, 1, 47, 0, 166, 3) 506 #define PE0_ETH_1_RGMII_TXD_0 NXP_S32_PINMUX(1, 1, 48, 1, 0, 0) 507 #define PE0_ETH_1_MII_TXD_0 NXP_S32_PINMUX(1, 1, 48, 2, 0, 0) 508 #define PE0_ETH_1_RMII_TXD_0 NXP_S32_PINMUX(1, 1, 48, 3, 0, 0) 509 #define PE0_ETH_1_RGMII_RXD_0 NXP_S32_PINMUX(1, 1, 48, 0, 167, 3) 510 #define PE1_ETH_1_RGMII_TXD_1 NXP_S32_PINMUX(1, 1, 49, 1, 0, 0) 511 #define PE1_ETH_1_MII_TXD_1 NXP_S32_PINMUX(1, 1, 49, 2, 0, 0) 512 #define PE1_ETH_1_RMII_TXD_1 NXP_S32_PINMUX(1, 1, 49, 3, 0, 0) 513 #define PE1_ETH_1_RGMII_RXD_1 NXP_S32_PINMUX(1, 1, 49, 0, 168, 3) 514 #define PE2_ETH_1_RGMII_TXD_2 NXP_S32_PINMUX(1, 1, 50, 1, 0, 0) 515 #define PE2_ETH_1_MII_TXD_2 NXP_S32_PINMUX(1, 1, 50, 2, 0, 0) 516 #define PE2_TMR_1588_PP2 NXP_S32_PINMUX(1, 1, 50, 4, 0, 0) 517 #define PE2_ETH_1_RGMII_RXD_2 NXP_S32_PINMUX(1, 1, 50, 0, 169, 3) 518 #define PE3_ETH_1_RGMII_TXD_3 NXP_S32_PINMUX(1, 1, 51, 1, 0, 0) 519 #define PE3_ETH_1_MII_TXD_3 NXP_S32_PINMUX(1, 1, 51, 2, 0, 0) 520 #define PE3_TMR_1588_PP2 NXP_S32_PINMUX(1, 1, 51, 5, 0, 0) 521 #define PE3_ETH_1_RGMII_RXD_3 NXP_S32_PINMUX(1, 1, 51, 0, 170, 3) 522 #define PE4_ETH_1_RGMII_TST_TXC NXP_S32_PINMUX(1, 1, 52, 1, 0, 0) 523 #define PE5_ETH_1_RGMII_TST_TXCTL NXP_S32_PINMUX(1, 1, 53, 1, 0, 0) 524 #define PE5_ETH_1_MII_RXDV NXP_S32_PINMUX(1, 1, 53, 0, 164, 2) 525 #define PE5_ETH_1_RGMII_RXCTL NXP_S32_PINMUX(1, 1, 53, 0, 166, 2) 526 #define PE5_ETH_1_RMII_CRS_DV NXP_S32_PINMUX(1, 1, 53, 0, 171, 2) 527 #define PE6_ETH_1_RGMII_TST_TXD_0 NXP_S32_PINMUX(1, 1, 54, 1, 0, 0) 528 #define PE6_ETH_1_MII_RXD_0 NXP_S32_PINMUX(1, 1, 54, 0, 160, 2) 529 #define PE6_ETH_1_RGMII_RXD_0 NXP_S32_PINMUX(1, 1, 54, 0, 167, 2) 530 #define PE6_ETH_1_RMII_RXD_0 NXP_S32_PINMUX(1, 1, 54, 0, 172, 2) 531 #define PE7_ETH_1_RGMII_TST_TXD_1 NXP_S32_PINMUX(1, 1, 55, 1, 0, 0) 532 #define PE7_ETH_1_MII_RXD_1 NXP_S32_PINMUX(1, 1, 55, 0, 161, 2) 533 #define PE7_ETH_1_RGMII_RXD_1 NXP_S32_PINMUX(1, 1, 55, 0, 168, 2) 534 #define PE7_ETH_1_RMII_RXD_1 NXP_S32_PINMUX(1, 1, 55, 0, 173, 2) 535 #define PE8_ETH_1_RGMII_TST_TXD_2 NXP_S32_PINMUX(1, 1, 56, 1, 0, 0) 536 #define PE8_TMR_1588_TRIG1 NXP_S32_PINMUX(1, 1, 56, 0, 178, 3) 537 #define PE8_ETH_1_MII_RXD_2 NXP_S32_PINMUX(1, 1, 56, 0, 162, 2) 538 #define PE8_ETH_1_RGMII_RXD_2 NXP_S32_PINMUX(1, 1, 56, 0, 169, 2) 539 #define PE9_ETH_1_RGMII_TST_TXD_3 NXP_S32_PINMUX(1, 1, 57, 1, 0, 0) 540 #define PE9_TMR_1588_TRIG2 NXP_S32_PINMUX(1, 1, 57, 0, 179, 3) 541 #define PE9_ETH_1_MII_RXD_3 NXP_S32_PINMUX(1, 1, 57, 0, 163, 2) 542 #define PE9_ETH_1_RGMII_RXD_3 NXP_S32_PINMUX(1, 1, 57, 0, 170, 2) 543 #define PE10_ETH_MDC_O NXP_S32_PINMUX(1, 1, 58, 1, 0, 0) 544 #define PE10_ETH_MDC_I NXP_S32_PINMUX(1, 1, 58, 0, 176, 2) 545 #define PE11_ETH_MDIO_O NXP_S32_PINMUX(1, 1, 59, 1, 0, 0) 546 #define PE11_ETH_MDIO_I NXP_S32_PINMUX(1, 1, 59, 0, 175, 2) 547 #define PE12_ETH_0_RGMII_TXC NXP_S32_PINMUX(1, 1, 60, 1, 0, 0) 548 #define PE13_ETH_0_RGMII_TXCTL NXP_S32_PINMUX(1, 1, 61, 1, 0, 0) 549 #define PE13_ETH_0_MII_TXEN NXP_S32_PINMUX(1, 1, 61, 2, 0, 0) 550 #define PE13_ETH_0_RMII_TXEN NXP_S32_PINMUX(1, 1, 61, 3, 0, 0) 551 #define PE13_ETH_0_RGMII_RXCTL NXP_S32_PINMUX(1, 1, 61, 0, 147, 3) 552 #define PE14_ETH_0_RGMII_TXD_0 NXP_S32_PINMUX(1, 1, 62, 1, 0, 0) 553 #define PE14_ETH_0_MII_TXD_0 NXP_S32_PINMUX(1, 1, 62, 2, 0, 0) 554 #define PE14_ETH_0_RMII_TXD_0 NXP_S32_PINMUX(1, 1, 62, 3, 0, 0) 555 #define PE14_ETH_0_RGMII_RXD_0 NXP_S32_PINMUX(1, 1, 62, 0, 148, 3) 556 #define PE15_ETH_0_RGMII_TXD_1 NXP_S32_PINMUX(1, 1, 63, 1, 0, 0) 557 #define PE15_ETH_0_MII_TXD_1 NXP_S32_PINMUX(1, 1, 63, 2, 0, 0) 558 #define PE15_ETH_0_RMII_TXD_1 NXP_S32_PINMUX(1, 1, 63, 3, 0, 0) 559 #define PE15_ETH_0_RGMII_RXD_1 NXP_S32_PINMUX(1, 1, 63, 0, 149, 3) 560 #define PF0_ETH_0_RGMII_TXD_2 NXP_S32_PINMUX(1, 1, 64, 1, 0, 0) 561 #define PF0_ETH_0_MII_TXD_2 NXP_S32_PINMUX(1, 1, 64, 2, 0, 0) 562 #define PF0_TMR_1588_PP1 NXP_S32_PINMUX(1, 1, 64, 4, 0, 0) 563 #define PF0_TMR_1588_ALARM1 NXP_S32_PINMUX(1, 1, 64, 5, 0, 0) 564 #define PF0_ETH_0_RGMII_RXD_2 NXP_S32_PINMUX(1, 1, 64, 0, 150, 3) 565 #define PF1_ETH_0_RGMII_TXD_3 NXP_S32_PINMUX(1, 1, 65, 1, 0, 0) 566 #define PF1_ETH_0_MII_TXD_3 NXP_S32_PINMUX(1, 1, 65, 2, 0, 0) 567 #define PF1_TMR_1588_PP2 NXP_S32_PINMUX(1, 1, 65, 4, 0, 0) 568 #define PF1_TMR_1588_ALARM2 NXP_S32_PINMUX(1, 1, 65, 5, 0, 0) 569 #define PF1_ETH_0_RGMII_RXD_3 NXP_S32_PINMUX(1, 1, 65, 0, 151, 3) 570 #define PF2_ETH_0_RGMII_TST_TXC NXP_S32_PINMUX(1, 1, 66, 1, 0, 0) 571 #define PF3_ETH_0_RGMII_TST_TXCTL NXP_S32_PINMUX(1, 1, 67, 1, 0, 0) 572 #define PF3_ETH_0_MII_RXDV NXP_S32_PINMUX(1, 1, 67, 0, 145, 2) 573 #define PF3_ETH_0_RGMII_RXCTL NXP_S32_PINMUX(1, 1, 67, 0, 147, 2) 574 #define PF3_ETH_0_RMII_CRS_DV NXP_S32_PINMUX(1, 1, 67, 0, 152, 2) 575 #define PF4_ETH_0_RGMII_TST_TXD_0 NXP_S32_PINMUX(1, 1, 68, 1, 0, 0) 576 #define PF4_ETH_0_MII_RXD_0 NXP_S32_PINMUX(1, 1, 68, 0, 141, 2) 577 #define PF4_ETH_0_RGMII_RXD_0 NXP_S32_PINMUX(1, 1, 68, 0, 148, 2) 578 #define PF4_ETH_0_RMII_RXD_0 NXP_S32_PINMUX(1, 1, 68, 0, 153, 2) 579 #define PF5_ETH_0_RGMII_TST_TXD_1 NXP_S32_PINMUX(1, 1, 69, 1, 0, 0) 580 #define PF5_ETH_0_MII_RXD_1 NXP_S32_PINMUX(1, 1, 69, 0, 142, 2) 581 #define PF5_ETH_0_RGMII_RXD_1 NXP_S32_PINMUX(1, 1, 69, 0, 149, 2) 582 #define PF5_ETH_0_RMII_RXD_1 NXP_S32_PINMUX(1, 1, 69, 0, 154, 2) 583 #define PF6_ETH_0_RGMII_TST_TXD_2 NXP_S32_PINMUX(1, 1, 70, 1, 0, 0) 584 #define PF6_TMR_1588_ALARM2 NXP_S32_PINMUX(1, 1, 70, 3, 0, 0) 585 #define PF6_TMR_1588_TRIG1 NXP_S32_PINMUX(1, 1, 70, 0, 178, 4) 586 #define PF6_ETH_0_MII_RXD_2 NXP_S32_PINMUX(1, 1, 70, 0, 143, 2) 587 #define PF6_ETH_0_RGMII_RXD_2 NXP_S32_PINMUX(1, 1, 70, 0, 150, 2) 588 #define PF7_ETH_0_RGMII_TST_TXD_3 NXP_S32_PINMUX(1, 1, 71, 1, 0, 0) 589 #define PF7_TMR_1588_ALARM1 NXP_S32_PINMUX(1, 1, 71, 3, 0, 0) 590 #define PF7_ETH_0_MII_RXD_3 NXP_S32_PINMUX(1, 1, 71, 0, 144, 2) 591 #define PF7_ETH_0_RGMII_RXD_3 NXP_S32_PINMUX(1, 1, 71, 0, 151, 2) 592 #define PF7_TMR_1588_TRIG2 NXP_S32_PINMUX(1, 1, 71, 0, 179, 4) 593 #define PF8_ETH_0_MII_TXER NXP_S32_PINMUX(1, 1, 72, 1, 0, 0) 594 #define PF8_TMR_1588_CLK_O NXP_S32_PINMUX(1, 1, 72, 3, 0, 0) 595 #define PF9_TMR_1588_TRIG1 NXP_S32_PINMUX(1, 1, 73, 0, 178, 5) 596 #define PF9_ETH_0_MII_RXER NXP_S32_PINMUX(1, 1, 73, 0, 146, 2) 597 #define PF9_ETH_0_RMII_RXER NXP_S32_PINMUX(1, 1, 73, 0, 155, 2) 598 #define PF10_TMR_1588_ALARM1 NXP_S32_PINMUX(1, 1, 74, 2, 0, 0) 599 #define PF10_TMR_1588_PP1 NXP_S32_PINMUX(1, 1, 74, 3, 0, 0) 600 #define PF10_ETH_0_MII_CRS NXP_S32_PINMUX(1, 1, 74, 0, 138, 2) 601 #define PF11_TMR_1588_PP2 NXP_S32_PINMUX(1, 1, 75, 2, 0, 0) 602 #define PF11_TMR_1588_CLK_O NXP_S32_PINMUX(1, 1, 75, 3, 0, 0) 603 #define PF11_ETH_0_MII_COL NXP_S32_PINMUX(1, 1, 75, 0, 137, 2) 604 #define PF11_TMR_1588_TRIG2 NXP_S32_PINMUX(1, 1, 75, 0, 179, 5) 605 #define PJ9_TMR_1588_TRIG1 NXP_S32_PINMUX(4, 1, 121, 0, 178, 7) 606 607 /* TRGMUX_1 */ 608 #define PB6_TRGMUX_1_XIN5 NXP_S32_PINMUX(0, 0, 22, 0, 76, 2) 609 610 /* ADC_0 */ 611 #define PB6_ADCSAR0_TRG NXP_S32_PINMUX(0, 0, 22, 0, 86, 2) 612 #define PB7_ADCSAR0_INJ_TRG NXP_S32_PINMUX(0, 0, 23, 0, 87, 2) 613 614 /* JTAGC */ 615 #define PO10_TDI NXP_S32_PINMUX(0, 0, 170, 0, 82, 0) 616 #define PO11_TDO NXP_S32_PINMUX(0, 0, 171, 1, 0, 0) 617 #define PO12_TMS_O NXP_S32_PINMUX(0, 0, 172, 1, 0, 0) 618 #define PO12_TMS_I NXP_S32_PINMUX(0, 0, 172, 0, 83, 0) 619 #define PO13_TCK NXP_S32_PINMUX(0, 0, 173, 0, 84, 0) 620 621 /* SPI_3 */ 622 #define PD11_DSPI_3_PCS3 NXP_S32_PINMUX(1, 1, 43, 2, 0, 0) 623 #define PD12_DSPI_3_SCK_O NXP_S32_PINMUX(1, 1, 44, 3, 0, 0) 624 #define PD12_DSPI_3_SCK_I NXP_S32_PINMUX(1, 1, 44, 0, 131, 3) 625 #define PD13_DSPI_3_SIN NXP_S32_PINMUX(1, 1, 45, 0, 132, 3) 626 #define PD14_DSPI_3_SOUT NXP_S32_PINMUX(1, 1, 46, 3, 0, 0) 627 #define PD15_DSPI_3_PCS0_O NXP_S32_PINMUX(1, 1, 47, 5, 0, 0) 628 #define PD15_DSPI_3_PCS0_I NXP_S32_PINMUX(1, 1, 47, 0, 130, 3) 629 #define PE0_DSPI_3_PCS1 NXP_S32_PINMUX(1, 1, 48, 5, 0, 0) 630 #define PE1_DSPI_3_PCS2 NXP_S32_PINMUX(1, 1, 49, 5, 0, 0) 631 632 /* LPI2C_1 */ 633 #define PE8_I2C_1_SCL_O NXP_S32_PINMUX(1, 1, 56, 3, 0, 0) 634 #define PE8_I2C_1_SCL_I NXP_S32_PINMUX(1, 1, 56, 0, 180, 3) 635 #define PE9_I2C_1_SDA_O NXP_S32_PINMUX(1, 1, 57, 3, 0, 0) 636 #define PE9_I2C_1_SDA_I NXP_S32_PINMUX(1, 1, 57, 0, 181, 3) 637 638 /* LINFLEX_4 */ 639 #define PD15_LIN_4_TX NXP_S32_PINMUX(1, 1, 47, 6, 0, 0) 640 #define PE0_LIN_4_RX NXP_S32_PINMUX(1, 1, 48, 0, 186, 3) 641 642 /* LINFLEX_5 */ 643 #define PE5_LIN_5_TX NXP_S32_PINMUX(1, 1, 53, 4, 0, 0) 644 #define PE6_LIN_5_RX NXP_S32_PINMUX(1, 1, 54, 0, 187, 3) 645 646 /* MC_CGM_1 */ 647 #define PD7_LFAST_0_EXT_REF_CLK_O NXP_S32_PINMUX(1, 1, 39, 2, 0, 0) 648 #define PD7_LFAST_0_EXT_REF_CLK_I NXP_S32_PINMUX(1, 1, 39, 0, 207, 2) 649 #define PD9_CLKOUT_1 NXP_S32_PINMUX(1, 1, 41, 1, 0, 0) 650 #define PD9_TMR_1588_CLK_I NXP_S32_PINMUX(1, 1, 41, 0, 177, 2) 651 #define PD9_ETH_RGMII_REF_CLK NXP_S32_PINMUX(1, 1, 41, 0, 136, 2) 652 #define PD10_TMR_1588_CLK_I NXP_S32_PINMUX(1, 1, 42, 0, 177, 3) 653 #define PD12_TMR_1588_CLK_I NXP_S32_PINMUX(1, 1, 44, 0, 177, 4) 654 #define PD14_ETH_1_TX_CLK NXP_S32_PINMUX(1, 1, 46, 0, 158, 2) 655 #define PE4_ETH_1_REF_RMII_CLK NXP_S32_PINMUX(1, 1, 52, 4, 0, 0) 656 #define PE4_ETH_1_RX_CLK NXP_S32_PINMUX(1, 1, 52, 0, 159, 2) 657 #define PE12_ETH_0_TX_CLK NXP_S32_PINMUX(1, 1, 60, 0, 139, 2) 658 #define PF2_ETH_0_REF_RMII_CLK NXP_S32_PINMUX(1, 1, 66, 3, 0, 0) 659 #define PF2_ETH_0_RX_CLK NXP_S32_PINMUX(1, 1, 66, 0, 140, 2) 660 #define PF8_TMR_1588_CLK_I NXP_S32_PINMUX(1, 1, 72, 0, 177, 5) 661 #define PF10_TMR_1588_CLK_I NXP_S32_PINMUX(1, 1, 74, 0, 177, 6) 662 663 /* MC_CGM_3 */ 664 #define PD8_CLKOUT_4 NXP_S32_PINMUX(1, 1, 40, 1, 0, 0) 665 666 /* SPI_4 */ 667 #define PE2_DSPI_4_SCK_O NXP_S32_PINMUX(1, 1, 50, 5, 0, 0) 668 #define PE2_DSPI_4_SCK_I NXP_S32_PINMUX(1, 1, 50, 0, 134, 2) 669 #define PE3_DSPI_4_SIN NXP_S32_PINMUX(1, 1, 51, 0, 135, 2) 670 #define PE4_DSPI_4_SOUT NXP_S32_PINMUX(1, 1, 52, 3, 0, 0) 671 #define PE5_DSPI_4_PCS0_O NXP_S32_PINMUX(1, 1, 53, 3, 0, 0) 672 #define PE5_DSPI_4_PCS0_I NXP_S32_PINMUX(1, 1, 53, 0, 133, 2) 673 #define PE6_DSPI_4_PCS1 NXP_S32_PINMUX(1, 1, 54, 3, 0, 0) 674 #define PE7_DSPI_4_PCS2 NXP_S32_PINMUX(1, 1, 55, 3, 0, 0) 675 676 /* SIUL2_4 */ 677 #define PI11_EIRQ_0 NXP_S32_PINMUX(4, 4, 107, 0, 357, 2) 678 #define PI13_EIRQ_1 NXP_S32_PINMUX(4, 4, 109, 0, 358, 2) 679 #define PJ12_EIRQ_2 NXP_S32_PINMUX(4, 4, 124, 0, 359, 2) 680 #define PK4_EIRQ_3 NXP_S32_PINMUX(4, 4, 132, 0, 360, 2) 681 #define PK6_EIRQ_4 NXP_S32_PINMUX(4, 4, 134, 0, 361, 2) 682 #define PK9_EIRQ_5 NXP_S32_PINMUX(4, 4, 137, 0, 362, 2) 683 #define PK11_EIRQ_6 NXP_S32_PINMUX(4, 4, 139, 0, 363, 2) 684 #define PK13_EIRQ_7 NXP_S32_PINMUX(4, 4, 141, 0, 364, 2) 685 686 /* QUADSPI_0 */ 687 #define PH12_QSPI_0_INTA_B NXP_S32_PINMUX(4, 4, 92, 0, 292, 2) 688 #define PH13_QSPI_0_CS_A0 NXP_S32_PINMUX(4, 4, 93, 1, 0, 0) 689 #define PH14_QSPI_0_DATA_A_O1 NXP_S32_PINMUX(4, 4, 94, 1, 0, 0) 690 #define PH15_QSPI_0_DATA_A_O5 NXP_S32_PINMUX(4, 4, 95, 1, 0, 0) 691 #define PI0_QSPI_0_DATA_A_O7 NXP_S32_PINMUX(4, 4, 96, 1, 0, 0) 692 #define PI1_QSPI_0_DATA_A_O3 NXP_S32_PINMUX(4, 4, 97, 1, 0, 0) 693 #define PI2_QSPI_0_CK_A_B NXP_S32_PINMUX(4, 4, 98, 1, 0, 0) 694 #define PI3_QSPI_0_CK_A NXP_S32_PINMUX(4, 4, 99, 1, 0, 0) 695 #define PI4_QSPI_0_DATA_A_O0 NXP_S32_PINMUX(4, 4, 100, 1, 0, 0) 696 #define PI5_QSPI_0_DATA_A_O4 NXP_S32_PINMUX(4, 4, 101, 1, 0, 0) 697 #define PI6_QSPI_0_DQS_A_O NXP_S32_PINMUX(4, 4, 102, 1, 0, 0) 698 #define PI7_QSPI_0_DATA_A_O6 NXP_S32_PINMUX(4, 4, 103, 1, 0, 0) 699 #define PI8_QSPI_0_DATA_A_O2 NXP_S32_PINMUX(4, 4, 104, 1, 0, 0) 700 #define PI9_QSPI_0_CS_A1 NXP_S32_PINMUX(4, 4, 105, 1, 0, 0) 701 702 /* QUADSPI_1 */ 703 #define PI10_QSPI_1_DATA_A_O0 NXP_S32_PINMUX(4, 4, 106, 1, 0, 0) 704 #define PI11_QSPI_1_DATA_A_O3 NXP_S32_PINMUX(4, 4, 107, 1, 0, 0) 705 #define PI12_QSPI_1_CS_A0 NXP_S32_PINMUX(4, 4, 108, 1, 0, 0) 706 #define PI13_QSPI_1_DATA_A_O4 NXP_S32_PINMUX(4, 4, 109, 1, 0, 0) 707 #define PI14_QSPI_1_DATA_A_O1 NXP_S32_PINMUX(4, 4, 110, 1, 0, 0) 708 #define PI15_QSPI_1_DQS_A_O NXP_S32_PINMUX(4, 4, 111, 6, 0, 0) 709 #define PI15_QSPI_1_DQS_A_I NXP_S32_PINMUX(4, 4, 111, 0, 295, 2) 710 #define PJ0_QSPI_1_DATA_A_O7 NXP_S32_PINMUX(4, 4, 112, 1, 0, 0) 711 #define PJ1_QSPI_1_CK_A NXP_S32_PINMUX(4, 4, 113, 1, 0, 0) 712 #define PJ2_QSPI_1_CK_A_B NXP_S32_PINMUX(4, 4, 114, 1, 0, 0) 713 #define PJ3_QSPI_1_DATA_A_O5 NXP_S32_PINMUX(4, 4, 115, 1, 0, 0) 714 #define PJ4_QSPI_1_DATA_A_O2 NXP_S32_PINMUX(4, 4, 116, 1, 0, 0) 715 #define PJ5_QSPI_1_DATA_A_O6 NXP_S32_PINMUX(4, 4, 117, 1, 0, 0) 716 #define PJ6_QSPI_1_CS_A1 NXP_S32_PINMUX(4, 4, 118, 1, 0, 0) 717 #define PJ7_QSPI_1_INTA_B NXP_S32_PINMUX(4, 4, 119, 0, 293, 2) 718 #define PK11_QSPI_1_INTB_B NXP_S32_PINMUX(4, 4, 139, 0, 294, 2) 719 #define PK12_QSPI_1_DATA_B_O3 NXP_S32_PINMUX(4, 4, 140, 1, 0, 0) 720 #define PK13_QSPI_1_DATA_B_O2 NXP_S32_PINMUX(4, 4, 141, 1, 0, 0) 721 #define PK14_QSPI_1_CK_B NXP_S32_PINMUX(4, 4, 142, 1, 0, 0) 722 #define PK15_QSPI_1_CS_B0 NXP_S32_PINMUX(4, 4, 143, 1, 0, 0) 723 #define PL0_QSPI_1_DATA_B_O1 NXP_S32_PINMUX(4, 4, 144, 1, 0, 0) 724 #define PL1_QSPI_1_DATA_B_O0 NXP_S32_PINMUX(4, 4, 145, 1, 0, 0) 725 726 /* USDHC */ 727 #define PI10_SD_0_CMD_O NXP_S32_PINMUX(4, 4, 106, 2, 0, 0) 728 #define PI11_SD_0_D0_O NXP_S32_PINMUX(4, 4, 107, 2, 0, 0) 729 #define PI12_SD_0_D1_O NXP_S32_PINMUX(4, 4, 108, 2, 0, 0) 730 #define PI13_SD_0_D2_O NXP_S32_PINMUX(4, 4, 109, 2, 0, 0) 731 #define PI14_SD_0_D3_O NXP_S32_PINMUX(4, 4, 110, 2, 0, 0) 732 #define PI15_SD_0_CLK_O NXP_S32_PINMUX(4, 4, 111, 1, 0, 0) 733 #define PI15_SD_0_CLK_I NXP_S32_PINMUX(4, 4, 111, 0, 371, 2) 734 #define PJ0_SD_0_D5_O NXP_S32_PINMUX(4, 4, 112, 2, 0, 0) 735 #define PJ1_SD_0_D4_O NXP_S32_PINMUX(4, 4, 113, 2, 0, 0) 736 #define PJ2_SD_0_D6_O NXP_S32_PINMUX(4, 4, 114, 2, 0, 0) 737 #define PJ3_SD_0_D7_O NXP_S32_PINMUX(4, 4, 115, 2, 0, 0) 738 #define PJ4_SD_0_RST NXP_S32_PINMUX(4, 4, 116, 2, 0, 0) 739 #define PJ5_SD_0_VSELECT NXP_S32_PINMUX(4, 4, 117, 2, 0, 0) 740 741 /* SPI_6 */ 742 #define PI10_DSPI_6_SCK_O NXP_S32_PINMUX(4, 4, 106, 5, 0, 0) 743 #define PI10_DSPI_6_SCK_I NXP_S32_PINMUX(4, 4, 106, 0, 305, 2) 744 #define PI11_DSPI_6_SIN NXP_S32_PINMUX(4, 4, 107, 0, 306, 2) 745 #define PI12_DSPI_6_SOUT NXP_S32_PINMUX(4, 4, 108, 4, 0, 0) 746 #define PI13_DSPI_6_PCS0_O NXP_S32_PINMUX(4, 4, 109, 4, 0, 0) 747 #define PI13_DSPI_6_PCS0_I NXP_S32_PINMUX(4, 4, 109, 0, 307, 2) 748 #define PI14_DSPI_6_PCS1 NXP_S32_PINMUX(4, 4, 110, 5, 0, 0) 749 #define PI15_DSPI_6_PCS2 NXP_S32_PINMUX(4, 4, 111, 3, 0, 0) 750 #define PJ6_DSPI_6_PCS3 NXP_S32_PINMUX(4, 4, 118, 4, 0, 0) 751 #define PJ7_DSPI_6_PCS4 NXP_S32_PINMUX(4, 4, 119, 3, 0, 0) 752 #define PK12_DSPI_6_SCK_O NXP_S32_PINMUX(4, 4, 140, 2, 0, 0) 753 #define PK12_DSPI_6_SCK_I NXP_S32_PINMUX(4, 4, 140, 0, 305, 3) 754 #define PK13_DSPI_6_SIN NXP_S32_PINMUX(4, 4, 141, 0, 306, 3) 755 #define PK14_DSPI_6_SOUT NXP_S32_PINMUX(4, 4, 142, 2, 0, 0) 756 #define PK15_DSPI_6_PCS0_O NXP_S32_PINMUX(4, 4, 143, 2, 0, 0) 757 #define PK15_DSPI_6_PCS0_I NXP_S32_PINMUX(4, 4, 143, 0, 307, 3) 758 #define PL0_DSPI_6_PCS1 NXP_S32_PINMUX(4, 4, 144, 2, 0, 0) 759 #define PL1_DSPI_6_PCS2 NXP_S32_PINMUX(4, 4, 145, 2, 0, 0) 760 761 /* LPI2C_2 */ 762 #define PI10_I2C_2_SCL_O NXP_S32_PINMUX(4, 4, 106, 6, 0, 0) 763 #define PI10_I2C_2_SCL_I NXP_S32_PINMUX(4, 4, 106, 0, 311, 2) 764 #define PI12_I2C_2_SDA_O NXP_S32_PINMUX(4, 4, 108, 5, 0, 0) 765 #define PI12_I2C_2_SDA_I NXP_S32_PINMUX(4, 4, 108, 0, 312, 2) 766 #define PJ10_I2C_2_SCL_O NXP_S32_PINMUX(4, 4, 122, 4, 0, 0) 767 #define PJ10_I2C_2_SCL_I NXP_S32_PINMUX(4, 4, 122, 0, 311, 3) 768 #define PJ11_I2C_2_SDA_O NXP_S32_PINMUX(4, 4, 123, 5, 0, 0) 769 #define PJ11_I2C_2_SDA_I NXP_S32_PINMUX(4, 4, 123, 0, 312, 3) 770 771 /* SPI_5 */ 772 #define PJ0_DSPI_5_SOUT NXP_S32_PINMUX(4, 4, 112, 3, 0, 0) 773 #define PJ1_DSPI_5_SIN NXP_S32_PINMUX(4, 4, 113, 0, 303, 2) 774 #define PJ2_DSPI_5_SCK_O NXP_S32_PINMUX(4, 4, 114, 3, 0, 0) 775 #define PJ2_DSPI_5_SCK_I NXP_S32_PINMUX(4, 4, 114, 0, 302, 2) 776 #define PJ3_DSPI_5_PCS0_O NXP_S32_PINMUX(4, 4, 115, 3, 0, 0) 777 #define PJ3_DSPI_5_PCS0_I NXP_S32_PINMUX(4, 4, 115, 0, 304, 2) 778 #define PJ4_DSPI_5_PCS1 NXP_S32_PINMUX(4, 4, 116, 3, 0, 0) 779 #define PJ5_DSPI_5_PCS2 NXP_S32_PINMUX(4, 4, 117, 3, 0, 0) 780 #define PJ6_DSPI_5_PCS3 NXP_S32_PINMUX(4, 4, 118, 3, 0, 0) 781 #define PJ7_DSPI_5_PCS4 NXP_S32_PINMUX(4, 4, 119, 2, 0, 0) 782 783 /* MC_CGM_4 */ 784 #define PJ2_CLKOUT_2 NXP_S32_PINMUX(4, 4, 114, 7, 0, 0) 785 786 /* PSI5_1 */ 787 #define PJ3_PSI5_1_SDIN0 NXP_S32_PINMUX(4, 4, 115, 0, 344, 2) 788 #define PJ4_PSI5_1_SDOUT0 NXP_S32_PINMUX(4, 4, 116, 7, 0, 0) 789 #define PJ5_PSI5_1_SDIN1 NXP_S32_PINMUX(4, 4, 117, 0, 345, 2) 790 #define PJ6_PSI5_1_SDOUT1 NXP_S32_PINMUX(4, 4, 118, 6, 0, 0) 791 #define PJ8_PSI5_1_SDIN0 NXP_S32_PINMUX(4, 4, 120, 0, 344, 3) 792 #define PJ9_PSI5_1_SDOUT0 NXP_S32_PINMUX(4, 4, 121, 4, 0, 0) 793 #define PJ11_PSI5_1_SDIN1 NXP_S32_PINMUX(4, 4, 123, 0, 345, 3) 794 #define PJ12_PSI5_1_SDOUT1 NXP_S32_PINMUX(4, 4, 124, 4, 0, 0) 795 #define PJ13_PSI5_1_SDIN2 NXP_S32_PINMUX(4, 4, 125, 0, 346, 2) 796 #define PJ14_PSI5_1_SDOUT2 NXP_S32_PINMUX(4, 4, 126, 4, 0, 0) 797 #define PJ15_PSI5_1_SDIN3 NXP_S32_PINMUX(4, 4, 127, 0, 347, 2) 798 #define PK0_PSI5_1_SDOUT3 NXP_S32_PINMUX(4, 4, 128, 3, 0, 0) 799 800 /* LINFLEX_6 */ 801 #define PJ8_LIN_6_TX NXP_S32_PINMUX(4, 4, 120, 1, 0, 0) 802 #define PJ9_LIN_6_RX NXP_S32_PINMUX(4, 4, 121, 0, 256, 2) 803 804 /* LCU_0 */ 805 #define PJ8_LCU_0_OUT0 NXP_S32_PINMUX(4, 4, 120, 4, 0, 0) 806 #define PJ9_LCU_0_OUT1 NXP_S32_PINMUX(4, 4, 121, 2, 0, 0) 807 #define PJ11_LCU_0_OUT2 NXP_S32_PINMUX(4, 4, 123, 3, 0, 0) 808 #define PJ12_LCU_0_OUT3 NXP_S32_PINMUX(4, 4, 124, 2, 0, 0) 809 #define PJ13_LCU_0_OUT4 NXP_S32_PINMUX(4, 4, 125, 4, 0, 0) 810 #define PJ14_LCU_0_OUT5 NXP_S32_PINMUX(4, 4, 126, 2, 0, 0) 811 #define PJ15_LCU_0_OUT6 NXP_S32_PINMUX(4, 4, 127, 3, 0, 0) 812 #define PK5_LCU_0_OUT7 NXP_S32_PINMUX(4, 4, 133, 2, 0, 0) 813 #define PK6_LCU_0_OUT8 NXP_S32_PINMUX(4, 4, 134, 2, 0, 0) 814 #define PK7_LCU_0_OUT9 NXP_S32_PINMUX(4, 4, 135, 2, 0, 0) 815 #define PK8_LCU_0_OUT10 NXP_S32_PINMUX(4, 4, 136, 2, 0, 0) 816 #define PK9_LCU_0_OUT11 NXP_S32_PINMUX(4, 4, 137, 2, 0, 0) 817 818 /* PSI5_S_1 */ 819 #define PJ10_PSI5_S_1_TXCLK NXP_S32_PINMUX(4, 4, 122, 2, 0, 0) 820 #define PK1_PSI5_S_1_TXCLK NXP_S32_PINMUX(4, 4, 129, 3, 0, 0) 821 #define PK2_PSI5_S_1_TX NXP_S32_PINMUX(4, 4, 130, 3, 0, 0) 822 #define PK3_PSI5_S_1_RX NXP_S32_PINMUX(4, 4, 131, 0, 348, 2) 823 824 /* TRGMUX_0 */ 825 #define PJ10_TRGMUX_0_XIN5 NXP_S32_PINMUX(4, 4, 122, 0, 370, 2) 826 #define PK0_TRGMUX_0_XIN0 NXP_S32_PINMUX(4, 4, 128, 0, 365, 2) 827 #define PK1_TRGMUX_0_XIN1 NXP_S32_PINMUX(4, 4, 129, 0, 366, 2) 828 #define PK2_TRGMUX_0_XIN2 NXP_S32_PINMUX(4, 4, 130, 0, 367, 2) 829 #define PK3_TRGMUX_0_XIN3 NXP_S32_PINMUX(4, 4, 131, 0, 368, 2) 830 #define PK4_TRGMUX_0_XIN4 NXP_S32_PINMUX(4, 4, 132, 0, 369, 2) 831 #define PK8_TRGMUX_0_XIN5 NXP_S32_PINMUX(4, 4, 136, 0, 370, 3) 832 #define PK10_TRGMUX_0_XIN5 NXP_S32_PINMUX(4, 4, 138, 0, 370, 4) 833 834 /* LINFLEX_7 */ 835 #define PJ11_LIN_7_TX NXP_S32_PINMUX(4, 4, 123, 1, 0, 0) 836 #define PJ12_LIN_7_RX NXP_S32_PINMUX(4, 4, 124, 0, 257, 2) 837 838 /* SPI_7 */ 839 #define PJ12_DSPI_7_PCS1 NXP_S32_PINMUX(4, 4, 124, 5, 0, 0) 840 #define PJ13_DSPI_7_SCK_O NXP_S32_PINMUX(4, 4, 125, 6, 0, 0) 841 #define PJ13_DSPI_7_SCK_I NXP_S32_PINMUX(4, 4, 125, 0, 308, 2) 842 #define PJ14_DSPI_7_SIN NXP_S32_PINMUX(4, 4, 126, 0, 309, 2) 843 #define PJ15_DSPI_7_SOUT NXP_S32_PINMUX(4, 4, 127, 5, 0, 0) 844 #define PK0_DSPI_7_PCS0_O NXP_S32_PINMUX(4, 4, 128, 4, 0, 0) 845 #define PK0_DSPI_7_PCS0_I NXP_S32_PINMUX(4, 4, 128, 0, 310, 2) 846 #define PK4_DSPI_7_PCS4 NXP_S32_PINMUX(4, 4, 132, 3, 0, 0) 847 #define PK6_DSPI_7_PCS3 NXP_S32_PINMUX(4, 4, 134, 5, 0, 0) 848 #define PK8_DSPI_7_PCS2 NXP_S32_PINMUX(4, 4, 136, 4, 0, 0) 849 850 /* LINFLEX_8 */ 851 #define PJ13_LIN_8_TX NXP_S32_PINMUX(4, 4, 125, 1, 0, 0) 852 #define PJ14_LIN_8_RX NXP_S32_PINMUX(4, 4, 126, 0, 258, 2) 853 854 /* SRX_1 */ 855 #define PK1_SENT_1_CH0_I NXP_S32_PINMUX(4, 4, 129, 0, 349, 2) 856 #define PK2_SENT_1_CH1_I NXP_S32_PINMUX(4, 4, 130, 0, 350, 2) 857 #define PK3_SENT_1_CH2_I NXP_S32_PINMUX(4, 4, 131, 0, 351, 2) 858 #define PK4_SENT_1_CH3_I NXP_S32_PINMUX(4, 4, 132, 0, 352, 2) 859 #define PK5_SENT_1_CH4_I NXP_S32_PINMUX(4, 4, 133, 0, 353, 2) 860 #define PK6_SENT_1_CH5_I NXP_S32_PINMUX(4, 4, 134, 0, 354, 2) 861 #define PK7_SENT_1_CH6_I NXP_S32_PINMUX(4, 4, 135, 0, 355, 2) 862 #define PK8_SENT_1_CH7_I NXP_S32_PINMUX(4, 4, 136, 0, 356, 2) 863 #define PK10_SENT_1_CH0_I NXP_S32_PINMUX(4, 4, 138, 0, 349, 3) 864 #define PK11_SENT_1_CH1_I NXP_S32_PINMUX(4, 4, 139, 0, 350, 3) 865 #define PK12_SENT_1_CH2_I NXP_S32_PINMUX(4, 4, 140, 0, 351, 3) 866 #define PK13_SENT_1_CH3_I NXP_S32_PINMUX(4, 4, 141, 0, 352, 3) 867 #define PK14_SENT_1_CH4_I NXP_S32_PINMUX(4, 4, 142, 0, 353, 3) 868 #define PK15_SENT_1_CH5_I NXP_S32_PINMUX(4, 4, 143, 0, 354, 3) 869 #define PL0_SENT_1_CH6_I NXP_S32_PINMUX(4, 4, 144, 0, 355, 3) 870 #define PL1_SENT_1_CH7_I NXP_S32_PINMUX(4, 4, 145, 0, 356, 3) 871 872 /* SIUL2_5 */ 873 #define PM3_EIRQ_0 NXP_S32_PINMUX(5, 5, 147, 0, 467, 2) 874 #define PM5_EIRQ_1 NXP_S32_PINMUX(5, 5, 149, 0, 468, 2) 875 #define PM7_EIRQ_2 NXP_S32_PINMUX(5, 5, 151, 0, 469, 2) 876 #define PM9_EIRQ_3 NXP_S32_PINMUX(5, 5, 153, 0, 470, 2) 877 #define PN0_EIRQ_4 NXP_S32_PINMUX(5, 5, 160, 0, 471, 2) 878 #define PN2_EIRQ_5 NXP_S32_PINMUX(5, 5, 162, 0, 472, 2) 879 #define PN5_EIRQ_6 NXP_S32_PINMUX(5, 5, 165, 0, 473, 2) 880 #define PN6_EIRQ_7 NXP_S32_PINMUX(5, 5, 166, 0, 474, 2) 881 882 /* SPI_9 */ 883 #define PM4_DSPI_9_PCS4 NXP_S32_PINMUX(5, 5, 148, 3, 0, 0) 884 #define PM5_DSPI_9_PCS3 NXP_S32_PINMUX(5, 5, 149, 2, 0, 0) 885 #define PM6_DSPI_9_PCS2 NXP_S32_PINMUX(5, 5, 150, 4, 0, 0) 886 #define PM7_DSPI_9_PCS1 NXP_S32_PINMUX(5, 5, 151, 3, 0, 0) 887 #define PM13_DSPI_9_SCK_O NXP_S32_PINMUX(5, 5, 157, 3, 0, 0) 888 #define PM13_DSPI_9_SCK_I NXP_S32_PINMUX(5, 5, 157, 0, 453, 2) 889 #define PM14_DSPI_9_SOUT NXP_S32_PINMUX(5, 5, 158, 2, 0, 0) 890 #define PN1_DSPI_9_SIN NXP_S32_PINMUX(5, 5, 161, 0, 454, 2) 891 #define PN2_DSPI_9_PCS0_O NXP_S32_PINMUX(5, 5, 162, 3, 0, 0) 892 #define PN2_DSPI_9_PCS0_I NXP_S32_PINMUX(5, 5, 162, 0, 452, 2) 893 894 /* SPI_8 */ 895 #define PM5_DSPI_8_PCS0_O NXP_S32_PINMUX(5, 5, 149, 3, 0, 0) 896 #define PM5_DSPI_8_PCS0_I NXP_S32_PINMUX(5, 5, 149, 0, 449, 4) 897 #define PM6_DSPI_8_SCK_O NXP_S32_PINMUX(5, 5, 150, 3, 0, 0) 898 #define PM6_DSPI_8_SCK_I NXP_S32_PINMUX(5, 5, 150, 0, 450, 2) 899 #define PM7_DSPI_8_SOUT NXP_S32_PINMUX(5, 5, 151, 2, 0, 0) 900 #define PM8_DSPI_8_SIN NXP_S32_PINMUX(5, 5, 152, 0, 451, 2) 901 #define PM9_DSPI_8_PCS0_O NXP_S32_PINMUX(5, 5, 153, 2, 0, 0) 902 #define PM9_DSPI_8_PCS0_I NXP_S32_PINMUX(5, 5, 153, 0, 449, 2) 903 #define PM15_DSPI_8_PCS1 NXP_S32_PINMUX(5, 5, 159, 3, 0, 0) 904 #define PN0_DSPI_8_PCS2 NXP_S32_PINMUX(5, 5, 160, 2, 0, 0) 905 #define PN1_DSPI_8_PCS3 NXP_S32_PINMUX(5, 5, 161, 3, 0, 0) 906 #define PN2_DSPI_8_PCS4 NXP_S32_PINMUX(5, 5, 162, 2, 0, 0) 907 #define PN3_DSPI_8_SOUT NXP_S32_PINMUX(5, 5, 163, 2, 0, 0) 908 #define PN4_DSPI_8_SCK_O NXP_S32_PINMUX(5, 5, 164, 2, 0, 0) 909 #define PN4_DSPI_8_SCK_I NXP_S32_PINMUX(5, 5, 164, 0, 450, 3) 910 #define PN5_DSPI_8_SIN NXP_S32_PINMUX(5, 5, 165, 0, 451, 3) 911 #define PN6_DSPI_8_PCS0_O NXP_S32_PINMUX(5, 5, 166, 2, 0, 0) 912 #define PN6_DSPI_8_PCS0_I NXP_S32_PINMUX(5, 5, 166, 0, 449, 3) 913 #define PN7_DSPI_8_PCS1 NXP_S32_PINMUX(5, 5, 167, 2, 0, 0) 914 #define PN8_DSPI_8_PCS2 NXP_S32_PINMUX(5, 5, 168, 2, 0, 0) 915 #define PN9_DSPI_8_PCS3 NXP_S32_PINMUX(5, 5, 169, 2, 0, 0) 916 917 /* LINFLEX_9 */ 918 #define PM6_LIN_9_TX NXP_S32_PINMUX(5, 5, 150, 1, 0, 0) 919 #define PM7_LIN_9_RX NXP_S32_PINMUX(5, 5, 151, 0, 466, 2) 920 921 /* LINFLEX_10 */ 922 #define PM8_LIN_10_TX NXP_S32_PINMUX(5, 5, 152, 1, 0, 0) 923 #define PM9_LIN_10_RX NXP_S32_PINMUX(5, 5, 153, 0, 464, 2) 924 925 /* CANXL_0 */ 926 #define PM8_CANXL_0_TX NXP_S32_PINMUX(5, 5, 152, 3, 0, 0) 927 #define PM9_CANXL_0_RX NXP_S32_PINMUX(5, 5, 153, 0, 462, 2) 928 #define PM12_CANXL_0_RX NXP_S32_PINMUX(5, 5, 156, 0, 462, 4) 929 #define PN1_CANXL_0_TX NXP_S32_PINMUX(5, 5, 161, 4, 0, 0) 930 #define PN2_CANXL_0_RX NXP_S32_PINMUX(5, 5, 162, 0, 462, 3) 931 932 /* CANXL_1 */ 933 #define PM10_CANXL_1_TX NXP_S32_PINMUX(5, 5, 154, 3, 0, 0) 934 #define PM11_CANXL_1_RX NXP_S32_PINMUX(5, 5, 155, 0, 463, 2) 935 936 /* MC_CGM_5 */ 937 #define PM12_CLKOUT_3 NXP_S32_PINMUX(5, 5, 156, 2, 0, 0) 938 939 /* LINFLEX_11 */ 940 #define PM13_LIN_11_TX NXP_S32_PINMUX(5, 5, 157, 1, 0, 0) 941 #define PM14_LIN_11_RX NXP_S32_PINMUX(5, 5, 158, 0, 465, 2) 942 943 #endif /* HAL_NXP_DTS_NXP_S32_S32Z27_BGA400_PINCTRL_H_ */ 944
